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misc: Remove any reference to the ALPHA ISA
2020-06-08 Giacomo Travaglinimisc: Remove any reference to the ALPHA ISA
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-05-28 Giacomo Travaglinisystem: Remove CNTFRQ_EL0 write from arm64 boot
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2020-05-28 Giacomo Travaglinidev-arm: Make CNTFRQ a GenericTimer parameter
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-05-14 Giacomo Travaglinimisc: Add Arm contributions to gem5-20 RELEASE-NOTES.md
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-05-12 Giacomo Travagliniscons: Add readCommandWithReturn helper
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-05-09 Giacomo Travagliniarch-arm: SVE instruction in EL1s cannot be trapped...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-05-09 Giacomo Travagliniarch-arm: CPTR.FPEN controlling SVE enablement
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-05-09 Giacomo Travagliniarch-arm: Remove checkSveTrap method
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-05-06 Giacomo Travaglinipython: Manually convert float to int when using %x
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-05-06 Giacomo Travagliniutil: Make cpt_upgraders python3 compatible
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-05-06 Giacomo Travagliniutil: Port git hooks to python3
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-05-04 Giacomo Travagliniarch-arm: Decode SEVL instruction for A32 and T32 IS
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-04-28 Giacomo Travagliniconfigs: Do not require args.kernel to be set in baremetal.py
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-04-28 Giacomo Travaglinisim, arch-arm: Restore capability of running without...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-04-27 Giacomo Travagliniarch-arm: SVE instructions do not use AHP format
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-04-27 Giacomo Travagliniarch-arm: Do not increment exponent if FPSCR.FZ in...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-04-23 Giacomo Travagliniconfigs: Use workloads.py in baremetal.py
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-04-23 Giacomo Travagliniconfigs: Produce list of workload types in workloads.py
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-04-23 Giacomo Travagliniconfigs: Add an example workloads module
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-04-21 Giacomo Travagliniconfigs: Add --machine-type option to baremetal.py
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-04-21 Giacomo Travagliniconfigs: Add --semi-path option to baremetal.py
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-04-19 Giacomo Travagliniarch-sparc: MAP_32BIT does not exist on solaris
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-04-15 Giacomo Travaglinitests: Run realview(64) tests with VExpress_GEM5_Foundation
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-04-15 Giacomo Travagliniarch-arm: Override ISA::takeOverFrom for the Arm ISA
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-04-15 Giacomo Travagliniarch, cpu: Add a takeOverFrom method for switching...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-04-15 Giacomo Travagliniarch-arm: Remove unnecessary haveGICv3CPUInterface
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-04-14 Giacomo Travaglinitests: Fail checkpoint regressions if no cpt has been...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-04-14 Giacomo Travaglinitests: Reduce checkpoint interval used by realview...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-04-14 Giacomo Travaglinidev-arm: Fix checkpointing for the GenericTimer
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-04-14 Giacomo Travagliniarch-arm: Handle empty object_file scenario in ArmFsWorkload
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-04-06 Giacomo Travagliniarch-arm: CNTHCTL trap to EL2 only if ARMv8.6-ECV implemented
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-04-01 Giacomo Travagliniconfigs: Enabling SimObj CLI for baremetal platform
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-03-30 Giacomo Travaglinidev-arm: Fix pci_mem_base setting in VExpress_GEM5_Base
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-03-26 Giacomo Travaglinidev-arm: Don't use args and kwargs on attachIO
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-03-25 Giacomo Travagliniconfigs: Use ArmFsWorkload for Arm baremetal
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-03-25 Giacomo Travagliniconfigs: Initialize atags_addr in baremetal.py
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-03-25 Giacomo Travagliniconfigs: Enable Semihosting for baremetal.py
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-03-25 Giacomo Travagliniconfigs: Make --disk-image optional in baremetal.py
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-03-24 Giacomo Travagliniarch-arm: Make load_addr_mask=0 for ArmFsLinux only
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-03-24 Giacomo Travagliniarch-arm: Fix aapcs32/aapcs64 compilation issues
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-03-23 Giacomo Travaglinidev-arm: Add flash1 memory to VExpress_GEM5 platform
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-03-19 Giacomo Travaglinitests: Add --bin-path option to insttest regressions
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-03-19 Giacomo Travagliniarch-arm: Fix ArmSystem::_resetAddr evalutation
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-03-16 Giacomo Travaglinipower: Fix regStats for PowerModel and PowerModelState
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-03-13 Giacomo Travagliniarch-x86: Add Python 3 workarounds for long
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-03-13 Giacomo Travagliniarch-x86: Fix imports for Python 3 compatibility
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-03-13 Giacomo Travaglinitests: Use relative path for python3 compliance
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-03-13 Giacomo Travagliniarch: list.sort() sorting by key only in python3
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-03-13 Giacomo Travaglinidev-arm: Fix VExpressFastmodel.py indentation
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-03-13 Giacomo Travagliniarch: Convert exec keyword to exec() function
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-03-13 Giacomo Travagliniarch: Bring closure out of p_global_let
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-03-13 Giacomo Travaglinimisc: Make exception handling python3 compliant
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-03-13 Giacomo Travaglinimisc: Text vs Byte string in python3
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-03-13 Giacomo Travagliniscons: file removed from python3
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-03-13 Giacomo Travaglinimisc: Views and Iterators instead of Lists in python3
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-03-13 Giacomo Travagliniarch-arm: Fix Arch detection in FS if there is not...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-03-10 Giacomo Travagliniarch-arm: Remove unnecessary RegIndex set for VSTR...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-03-10 Giacomo Travagliniarch-arm: Hint the compiler to inline getArmSystem
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-03-10 Giacomo Travagliniarch-arm: Speedup ARM execution by avoiding expensive...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-03-10 Giacomo Travagliniarch-arm: python3 "/" will always produce a float
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-03-10 Giacomo Travaglinimisc: Replace basestring with six.string_types
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-03-10 Giacomo Travaglinimisc: Replace __metaclass__ with six.add_metaclass
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-03-10 Giacomo Travaglinimisc: string.join has been removed in python3
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-03-10 Giacomo Travaglinipython: The new module has been removed in python3
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-03-04 Giacomo Travagliniarch-arm: Remove unused getArmSystem helper
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-03-03 Giacomo Travaglinitests: simple_ruby_test's valid_host is X86 only
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-02-28 Giacomo Travaglinilearning-gem5: Use zero initialization in hello_goodbye...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-02-20 Giacomo Travaglinidev-arm: Fix setupBootloader for VExpress_GEM5_V2
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-02-19 Giacomo Travaglinicpu: Fix vector renaming bug
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-02-19 Giacomo Travagliniarch, arch-arm: Use BaseISA in RenameMode interface
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-02-17 Giacomo Travagliniarch-arm: Be more verbose on load/store construction
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-02-17 Giacomo Travaglinibase: Use a int to store fgetc return value
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-02-17 Giacomo Travagliniarch-arm: Fix ArmKVM build
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-02-17 Giacomo Travaglinicpu: Mark ExecContext::tcBase() as const
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-02-13 Giacomo Travagliniext: Add failure node to JUnit xml file
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-02-11 Giacomo Travaglinitests,misc: update TESTING.md documentation
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-02-10 Giacomo Travaglinitests: hello_se using host tag
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-02-10 Giacomo Travaglinitests: Add --host tag
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-02-10 Giacomo Travagliniconfigs: Using VExpress_GEM5_V1 as a default for Options.py
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-02-10 Giacomo Travagliniarch-arm: LDTRSW was not marked as unpriviledged
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-02-06 Giacomo Travaglinitests: Move old quick regressions back into their original set
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-02-04 Giacomo Travagliniarch-arm: Split translateFs to distinguish when MMU...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-01-22 Giacomo Travaglinitests: Fix python line break in m5_exit test
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-01-21 Giacomo Travaglinitests: Add a timeout to getremotetime
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-01-21 Giacomo Travaglinitests: Adding --bin-path option to select tests bin...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-01-21 Giacomo Travaglinitests: fs/linux/arm passing M5_PATH via commandline
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-01-09 Giacomo Travaglinibase, gpu-compute: Move gpu AMOs into the generic header
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-01-08 Giacomo Travagliniarch, base: Move arm AtomicOpFunctor into the generic...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-01-08 Giacomo Travaglinibase: Move AtomicOpFunctors to a dedicated header
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-01-07 Giacomo Travaglinisystem-arm: GICv2/GICv3 have different Distributor...
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-01-07 Giacomo Travaglinisystem-arm: Rename ARM bootloader source
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-01-07 Giacomo Travaglinisystem-arm: Rename ARM bootloader directories
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2020-01-06 Giacomo Travaglinidev-arm: Fix SMMUv3 16KB next-level table address masking
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-12-23 Giacomo Travaglinitests: Always print stderr in gem5 Fixtures
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-12-20 Giacomo Travagliniconfigs: arm realview(64) regressions using VExpress_GEM5_V1
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-12-11 Giacomo Travagliniarch-arm: Always initialize SVE memData
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-12-11 Giacomo Travagliniarch-arm: Avoid creating an empty byteEnable vector
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-12-11 Giacomo Travaglinicpu: Replace empty byteEnable check with Request::isMasked
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-12-11 Giacomo Travaglinicpu: Fix coding style (byteEnable->byte_enable)
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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2019-12-11 Giacomo Travaglinicpu: Add byteEnable assertions to readMem and initateMemRead
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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