rename LoadStoreInterface signals to include _i and _o suffixes

got fed up of not knowing which Signal was which direction

diff --git a/src/soc/experiment/lsmem.py b/src/soc/experiment/lsmem.py
index 29d1b4e88611be0a43496d9cd9577f0acc10534d..b8099d9a8cfee24f0b47fd5fcf916209d64d3a89 100644 (file)
--- a/src/soc/experiment/lsmem.py
+++ b/src/soc/experiment/lsmem.py
@@ -22,80 +22,80 @@ class TestMemLoadStoreUnit(LoadStoreUnitInterface, Elaboratable):
         do_store = Signal() # set when doing a store while valid and not stalled
 
         m.d.comb += [
-            do_load.eq(self.x_load & (self.x_valid & ~self.x_stall)),
-            do_store.eq(self.x_store & (self.x_valid & ~self.x_stall)),
+            do_load.eq(self.x_ld_i & (self.x_valid_i & ~self.x_stall_i)),
+            do_store.eq(self.x_st_i & (self.x_valid_i & ~self.x_stall_i)),
             ]
         m.d.comb += [
-            mem.rdport.addr.eq(self.x_addr[2:]),
-            self.m_load_data.eq(mem.rdport.data),
+            mem.rdport.addr.eq(self.x_addr_i[2:]),
+            self.m_ld_data_o.eq(mem.rdport.data),
 
-            mem.wrport.addr.eq(self.x_addr[2:]),
-            mem.wrport.en.eq(Mux(do_store, self.x_mask, 0)),
-            mem.wrport.data.eq(self.x_store_data)
+            mem.wrport.addr.eq(self.x_addr_i[2:]),
+            mem.wrport.en.eq(Mux(do_store, self.x_mask_i, 0)),
+            mem.wrport.data.eq(self.x_st_data_i)
             ]
 
         return m
 
 
 def write_to_addr(dut, addr, value):
-    yield dut.x_addr.eq(addr)
-    yield dut.x_store_data.eq(value)
-    yield dut.x_store.eq(1)
-    yield dut.x_mask.eq(-1)
-    yield dut.x_valid.eq(1)
-    yield dut.x_stall.eq(1)
+    yield dut.x_addr_i.eq(addr)
+    yield dut.x_st_data_i.eq(value)
+    yield dut.x_st_i.eq(1)
+    yield dut.x_mask_i.eq(-1)
+    yield dut.x_valid_i.eq(1)
+    yield dut.x_stall_i.eq(1)
     yield
     yield
     
-    yield dut.x_stall.eq(0)
+    yield dut.x_stall_i.eq(0)
     yield
-    yield dut.x_store.eq(0)
-    while (yield dut.x_stall):
+    yield dut.x_st_i.eq(0)
+    while (yield dut.x_stall_i):
         yield
 
 
 def read_from_addr(dut, addr):
-    yield dut.x_addr.eq(addr)
-    yield dut.x_load.eq(1)
-    yield dut.x_valid.eq(1)
-    yield dut.x_stall.eq(1)
+    yield dut.x_addr_i.eq(addr)
+    yield dut.x_ld_i.eq(1)
+    yield dut.x_valid_i.eq(1)
+    yield dut.x_stall_i.eq(1)
     yield
-    yield dut.x_stall.eq(0)
+    yield dut.x_stall_i.eq(0)
     yield
-    yield dut.x_load.eq(0)
+    yield dut.x_ld_i.eq(0)
     yield Settle()
-    while (yield dut.x_stall):
+    while (yield dut.x_stall_i):
         yield
-    assert (yield dut.x_valid)
-    return (yield dut.m_load_data)
+    assert (yield dut.x_valid_i)
+    return (yield dut.m_ld_data_o)
 
 
 def write_byte(dut, addr, val):
     offset = addr & 0x3
-    yield dut.x_addr.eq(addr)
-    yield dut.x_store.eq(1)
-    yield dut.x_store_data.eq(val << (offset * 8))
-    yield dut.x_mask.eq(1 << offset)
-    yield dut.x_valid.eq(1)
+    yield dut.x_addr_i.eq(addr)
+    yield dut.x_st_i.eq(1)
+    yield dut.x_st_data_i.eq(val << (offset * 8))
+    yield dut.x_mask_i.eq(1 << offset)
+    yield dut.x_valid_i.eq(1)
 
     yield
-    yield dut.x_store.eq(0)
-    while (yield dut.x_stall):
+    yield dut.x_st_i.eq(0)
+    while (yield dut.x_stall_i):
         yield
 
 
 def read_byte(dut, addr):
     offset = addr & 0x3
-    yield dut.x_addr.eq(addr)
-    yield dut.x_load.eq(1)
-    yield dut.x_valid.eq(1)
+    yield dut.x_addr_i.eq(addr)
+    yield dut.x_ld_i.eq(1)
+    yield dut.x_valid_i.eq(1)
     yield
-    yield dut.x_load.eq(0)
+    yield dut.x_ld_i.eq(0)
     yield Settle()
-    while (yield dut.x_stall):
+    while (yield dut.x_stall_i):
         yield
-    assert (yield dut.x_valid)
-    val = (yield dut.m_load_data)
+    assert (yield dut.x_valid_i)
+    val = (yield dut.m_ld_data_o)
     return (val >> (offset * 8)) & 0xff
 
 

diff --git a/src/soc/minerva/units/loadstore.py b/src/soc/minerva/units/loadstore.py
index e04cc0661bb6352fdc3d6e6fd41e426f168c5492..ae7ba0ae2938e886da6088bc50434617064c3609 100644 (file)
--- a/src/soc/minerva/units/loadstore.py
+++ b/src/soc/minerva/units/loadstore.py
@@ -16,31 +16,33 @@ class LoadStoreUnitInterface:
         badwid = addr_wid-log2_int(mask_wid) # TODO: is this correct?
 
         # INPUTS
-        self.x_addr = Signal(addr_wid)       # address used for loads/stores
-        self.x_mask = Signal(mask_wid)       # Mask of which bytes to write
-        self.x_load = Signal()               # set to do a memory load
-        self.x_store = Signal()              # set to do a memory store
-        self.x_store_data = Signal(data_wid) # The data to write when storing
-        self.x_stall = Signal()              # do nothing until low
-        self.x_valid = Signal()              # Whether x pipeline stage is
-                                             # currently enabled (I
-                                             # think?). Set to 1 for #now
-        self.m_stall = Signal()              # do nothing until low
-        self.m_valid = Signal()              # Whether m pipeline stage is
-                                             # currently enabled. Set
-                                             # to 1 for now
+        self.x_addr_i = Signal(addr_wid)    # address used for loads/stores
+        self.x_mask_i = Signal(mask_wid)    # Mask of which bytes to write
+        self.x_ld_i = Signal()              # set to do a memory load
+        self.x_st_i = Signal()              # set to do a memory store
+        self.x_st_data_i = Signal(data_wid) # The data to write when storing
+
+        self.x_stall_i = Signal()           # do nothing until low
+        self.x_valid_i = Signal()           # Whether x pipeline stage is
+                                            # currently enabled (I
+                                            # think?). Set to 1 for #now
+        self.m_stall_i = Signal()           # do nothing until low
+        self.m_valid_i = Signal()           # Whether m pipeline stage is
+                                            # currently enabled. Set
+                                            # to 1 for now
 
         # OUTPUTS
-        self.x_busy = Signal()              # set when the memory is busy
-        self.m_busy = Signal()              # set when the memory is busy
-        self.m_load_data = Signal(data_wid) # Data returned from memory read
-        # Data validity is NOT indicated by m_valid or x_valid as
+        self.x_busy_o = Signal()            # set when the memory is busy
+        self.m_busy_o = Signal()            # set when the memory is busy
+
+        self.m_ld_data_o = Signal(data_wid) # Data returned from memory read
+        # Data validity is NOT indicated by m_valid_i or x_valid_i as
         # those are inputs. I believe it is valid on the next cycle
         # after raising m_load where busy is low
 
-        self.m_load_error = Signal()    # if there was an error when loading
-        self.m_store_error = Signal()   # if there was an error when storing
-        self.m_badaddr = Signal(badwid) # The address of the load/store error
+        self.m_load_err_o = Signal()      # if there was an error when loading
+        self.m_store_err_o = Signal()     # if there was an error when storing
+        self.m_badaddr_o = Signal(badwid) # The address of the load/store error
 
 
 class BareLoadStoreUnit(LoadStoreUnitInterface, Elaboratable):
@@ -48,41 +50,41 @@ class BareLoadStoreUnit(LoadStoreUnitInterface, Elaboratable):
         m = Module()
 
         with m.If(self.dbus.cyc):
-            with m.If(self.dbus.ack | self.dbus.err | ~self.m_valid):
+            with m.If(self.dbus.ack | self.dbus.err | ~self.m_valid_i):
                 m.d.sync += [
                     self.dbus.cyc.eq(0),
                     self.dbus.stb.eq(0),
-                    self.m_load_data.eq(self.dbus.dat_r)
+                    self.m_ld_data_o.eq(self.dbus.dat_r)
                 ]
-        with m.Elif((self.x_load | self.x_store) &
-                     self.x_valid & ~self.x_stall):
+        with m.Elif((self.x_ld_i | self.x_st_i) &
+                     self.x_valid_i & ~self.x_stall_i):
             m.d.sync += [
                 self.dbus.cyc.eq(1),
                 self.dbus.stb.eq(1),
-                self.dbus.adr.eq(self.x_addr[2:]),
-                self.dbus.sel.eq(self.x_mask),
-                self.dbus.we.eq(self.x_store),
-                self.dbus.dat_w.eq(self.x_store_data)
+                self.dbus.adr.eq(self.x_addr_i[2:]),
+                self.dbus.sel.eq(self.x_mask_i),
+                self.dbus.we.eq(self.x_st_i),
+                self.dbus.dat_w.eq(self.x_st_data_i)
             ]
 
         with m.If(self.dbus.cyc & self.dbus.err):
             m.d.sync += [
-                self.m_load_error.eq(~self.dbus.we),
-                self.m_store_error.eq(self.dbus.we),
-                self.m_badaddr.eq(self.dbus.adr)
+                self.m_load_err_o.eq(~self.dbus.we),
+                self.m_store_err_o.eq(self.dbus.we),
+                self.m_badaddr_o.eq(self.dbus.adr)
             ]
-        with m.Elif(~self.m_stall):
+        with m.Elif(~self.m_stall_i):
             m.d.sync += [
-                self.m_load_error.eq(0),
-                self.m_store_error.eq(0)
+                self.m_load_err_o.eq(0),
+                self.m_store_err_o.eq(0)
             ]
 
-        m.d.comb += self.x_busy.eq(self.dbus.cyc)
+        m.d.comb += self.x_busy_o.eq(self.dbus.cyc)
 
-        with m.If(self.m_load_error | self.m_store_error):
-            m.d.comb += self.m_busy.eq(0)
+        with m.If(self.m_load_err_o | self.m_store_err_o):
+            m.d.comb += self.m_busy_o.eq(0)
         with m.Else():
-            m.d.comb += self.m_busy.eq(self.dbus.cyc)
+            m.d.comb += self.m_busy_o.eq(self.dbus.cyc)
 
         return m
 
@@ -107,20 +109,20 @@ class CachedLoadStoreUnit(LoadStoreUnitInterface, Elaboratable):
         x_dcache_select = Signal()
         m_dcache_select = Signal()
 
-        m.d.comb += x_dcache_select.eq((self.x_addr >= dcache.base) &
-                                       (self.x_addr < dcache.limit))
-        with m.If(~self.x_stall):
+        m.d.comb += x_dcache_select.eq((self.x_addr_i >= dcache.base) &
+                                       (self.x_addr_i < dcache.limit))
+        with m.If(~self.x_stall_i):
             m.d.sync += m_dcache_select.eq(x_dcache_select)
 
         m.d.comb += [
-            dcache.s1_addr.eq(self.x_addr[2:]),
+            dcache.s1_addr.eq(self.x_addr_i[2:]),
             dcache.s1_flush.eq(self.x_flush),
-            dcache.s1_stall.eq(self.x_stall),
-            dcache.s1_valid.eq(self.x_valid & x_dcache_select),
+            dcache.s1_stall.eq(self.x_stall_i),
+            dcache.s1_valid.eq(self.x_valid_i & x_dcache_select),
             dcache.s2_addr.eq(self.m_addr[2:]),
             dcache.s2_re.eq(self.m_load),
             dcache.s2_evict.eq(self.m_store),
-            dcache.s2_valid.eq(self.m_valid & m_dcache_select)
+            dcache.s2_valid.eq(self.m_valid_i & m_dcache_select)
         ]
 
         wrbuf_w_data = Record([("addr", 30), ("mask", 4), ("data", 32)])
@@ -129,11 +131,11 @@ class CachedLoadStoreUnit(LoadStoreUnitInterface, Elaboratable):
                                               depth=dcache.nwords)
         m.d.comb += [
             wrbuf.w_data.eq(wrbuf_w_data),
-            wrbuf_w_data.addr.eq(self.x_addr[2:]),
-            wrbuf_w_data.mask.eq(self.x_mask),
-            wrbuf_w_data.data.eq(self.x_store_data),
-            wrbuf.w_en.eq(self.x_store & self.x_valid &
-                          x_dcache_select & ~self.x_stall),
+            wrbuf_w_data.addr.eq(self.x_addr_i[2:]),
+            wrbuf_w_data.mask.eq(self.x_mask_i),
+            wrbuf_w_data.data.eq(self.x_st_data_i),
+            wrbuf.w_en.eq(self.x_st_i & self.x_valid_i &
+                          x_dcache_select & ~self.x_stall_i),
             wrbuf_r_data.eq(wrbuf.r_data),
         ]
 
@@ -174,56 +176,56 @@ class CachedLoadStoreUnit(LoadStoreUnitInterface, Elaboratable):
         bare_port = dbus_arbiter.port(priority=2)
         bare_rdata = Signal.like(bare_port.dat_r)
         with m.If(bare_port.cyc):
-            with m.If(bare_port.ack | bare_port.err | ~self.m_valid):
+            with m.If(bare_port.ack | bare_port.err | ~self.m_valid_i):
                 m.d.sync += [
                     bare_port.cyc.eq(0),
                     bare_port.stb.eq(0),
                     bare_rdata.eq(bare_port.dat_r)
                 ]
-        with m.Elif((self.x_load | self.x_store) &
-                    ~x_dcache_select & self.x_valid & ~self.x_stall):
+        with m.Elif((self.x_ld_i | self.x_st_i) &
+                    ~x_dcache_select & self.x_valid_i & ~self.x_stall_i):
             m.d.sync += [
                 bare_port.cyc.eq(1),
                 bare_port.stb.eq(1),
-                bare_port.adr.eq(self.x_addr[2:]),
-                bare_port.sel.eq(self.x_mask),
-                bare_port.we.eq(self.x_store),
-                bare_port.dat_w.eq(self.x_store_data)
+                bare_port.adr.eq(self.x_addr_i[2:]),
+                bare_port.sel.eq(self.x_mask_i),
+                bare_port.we.eq(self.x_st_i),
+                bare_port.dat_w.eq(self.x_st_data_i)
             ]
 
         with m.If(self.dbus.cyc & self.dbus.err):
             m.d.sync += [
-                self.m_load_error.eq(~self.dbus.we),
-                self.m_store_error.eq(self.dbus.we),
-                self.m_badaddr.eq(self.dbus.adr)
+                self.m_load_err_o.eq(~self.dbus.we),
+                self.m_store_err_o.eq(self.dbus.we),
+                self.m_badaddr_o.eq(self.dbus.adr)
             ]
-        with m.Elif(~self.m_stall):
+        with m.Elif(~self.m_stall_i):
             m.d.sync += [
-                self.m_load_error.eq(0),
-                self.m_store_error.eq(0)
+                self.m_load_err_o.eq(0),
+                self.m_store_err_o.eq(0)
             ]
 
         with m.If(self.x_fence_i):
-            m.d.comb += self.x_busy.eq(wrbuf.r_rdy)
+            m.d.comb += self.x_busy_o.eq(wrbuf.r_rdy)
         with m.Elif(x_dcache_select):
-            m.d.comb += self.x_busy.eq(self.x_store & ~wrbuf.w_rdy)
+            m.d.comb += self.x_busy_o.eq(self.x_st_i & ~wrbuf.w_rdy)
         with m.Else():
-            m.d.comb += self.x_busy.eq(bare_port.cyc)
+            m.d.comb += self.x_busy_o.eq(bare_port.cyc)
 
-        with m.If(self.m_load_error | self.m_store_error):
+        with m.If(self.m_load_err_o | self.m_store_err_o):
             m.d.comb += [
-                self.m_busy.eq(0),
-                self.m_load_data.eq(0)
+                self.m_busy_o.eq(0),
+                self.m_ld_data_o.eq(0)
             ]
         with m.Elif(m_dcache_select):
             m.d.comb += [
-                self.m_busy.eq(dcache.s2_re & dcache.s2_miss),
-                self.m_load_data.eq(dcache.s2_rdata)
+                self.m_busy_o.eq(dcache.s2_re & dcache.s2_miss),
+                self.m_ld_data_o.eq(dcache.s2_rdata)
             ]
         with m.Else():
             m.d.comb += [
-                self.m_busy.eq(bare_port.cyc),
-                self.m_load_data.eq(bare_rdata)
+                self.m_busy_o.eq(bare_port.cyc),
+                self.m_ld_data_o.eq(bare_rdata)
             ]
 
         return m