whoops, regfiles are uppercase

diff --git a/src/soc/simple/core.py b/src/soc/simple/core.py
index 702e3b479c984b5e20328a24492b85443affaa6f..c6e4161795542751812d8ad7dee2721d5c5788d4 100644 (file)
--- a/src/soc/simple/core.py
+++ b/src/soc/simple/core.py
@@ -90,7 +90,7 @@ class NonProductionCore(Elaboratable):
                 (rdflag, read, wid, fuspec) = fspec
 
                 # "munge" the regfile port index, due to full-port access
-                if regfile in ['xer', 'cr']:
+                if regfile in ['XER', 'CA']:
                     if regname.startswith('full'):
                         rpidx = 0 # by convention, first port
                     else: