remove clock, use rename on clk in settings

diff --git a/examples/alu.py b/examples/alu.py
index 2fa14a00b716c8b10baf2d58aa1aefd3a8e1cee3..3979b08ef2b5a564c9fe47d9e1969f50dff1dc7f 100644 (file)
--- a/examples/alu.py
+++ b/examples/alu.py
@@ -9,13 +9,13 @@ class ALU(Elaboratable):
         self.b   = Signal(width)
         self.o   = Signal(width)
         self.co  = Signal()
-        self.m_clock   = Signal(reset_less=True)
-        self.p_reset   = Signal(reset_less=True)
+        #self.m_clock   = Signal(reset_less=True)
+        #self.p_reset   = Signal(reset_less=True)
 
     def elaborate(self, platform):
         m = Module()
-        m.domains.sync = ClockDomain()
-        m.d.comb += ClockSignal().eq(self.m_clock)
+        #m.domains.sync = ClockDomain()
+        #m.d.comb += ClockSignal().eq(self.m_clock)
 
         with m.If(self.sel == 0b00):
             m.d.sync += self.o.eq(self.a | self.b)
@@ -35,6 +35,5 @@ def create_ilang(dut, ports, test_name):
 
 if __name__ == "__main__":
     alu = ALU(width=16)
-    create_ilang(alu, [alu.m_clock, alu.p_reset,
-                       alu.o, alu.a, alu.b, alu.co], "alu")
+    create_ilang(alu, [alu.o, alu.a, alu.b, alu.co], "alu")