add link to regspecs on wiki

diff --git a/src/soc/experiment/compalu_multi.py b/src/soc/experiment/compalu_multi.py
index c39d863f9956138ab1e6f9db39b2afb0df5ef931..b25749c8b879969ee044e3717e68061b4585d0c0 100644 (file)
--- a/src/soc/experiment/compalu_multi.py
+++ b/src/soc/experiment/compalu_multi.py
@@ -67,7 +67,7 @@ def go_record(n, name):
     r.rel.reset_less = True
     return r
 
-
+# see https://libre-soc.org/3d_gpu/architecture/regfile/ section on regspecs
 def get_regspec_bitwidth(regspec, srcdest, idx):
     bitspec = regspec[srcdest][idx]
     wid = 0
@@ -96,6 +96,8 @@ class CompUnitRecord(RecordObject):
 
     :subkls:      the class (not an instance) needed to construct the opcode
     :rwid:        either an integer (specifies width of all regs) or a "regspec"
+
+    see https://libre-soc.org/3d_gpu/architecture/regfile/ section on regspecs
     """
     def __init__(self, subkls, rwid, n_src=None, n_dst=None, name=None):
         RecordObject.__init__(self, name)

diff --git a/src/soc/fu/cr/pipe_data.py b/src/soc/fu/cr/pipe_data.py
index 599d20025ecf0ad2472fc7c50a4939d69871b3c8..0eae72f0509cb0bfa7ed7c9367909fb0e19770e4 100644 (file)
--- a/src/soc/fu/cr/pipe_data.py
+++ b/src/soc/fu/cr/pipe_data.py
@@ -1,3 +1,7 @@
+"""
+Links:
+* https://libre-soc.org/3d_gpu/architecture/regfile/ section on regspecs
+"""
 from nmigen import Signal, Const
 from ieee754.fpcommon.getop import FPPipeContext
 from soc.fu.pipe_data import IntegerData, CommonPipeSpec