yield mmu.rin.prtbl.eq(0x1000000) # set process table
yield
- memsize = 256
+ memsize = 64
for i in range(1024):
addr = randint(0, memsize-1)
data = randint(0, (1<<64)-1)
addr *= 8
+ addr += 0x10000
yield from pi_st(pi, addr, data, 8, msr_pr=1)
yield
ld_data = yield from pi_ld(pi, addr, 8, msr_pr=1)
- print ("dcache_random random ld data", hex(data), hex(read))
print ("addr",addr)
+ print ("dcache_random random ld data", hex(data), hex(ld_data))
+ if data!=ld_data:
+ print("==== data read at random test differs")
+ #assert(data==ld_data)
yield
stop = True
# dcache_load at addr 0
mem = {
+ 0x10000: # PARTITION_TABLE_2
+ # PATB_GR=1 PRTB=0x1000 PRTS=0xb
+ b(0x800000000100000b),
+
+ 0x30000: # RADIX_ROOT_PTE
+ # V = 1 L = 0 NLB = 0x400 NLS = 9
+ b(0x8000000000040009),
+
+ 0x40000: # RADIX_SECOND_LEVEL
+ # V = 1 L = 1 SW = 0 RPN = 0
+ # R = 1 C = 1 ATT = 0 EAA 0x7
+ b(0xc000000000000183),
+
+ 0x1000000: # PROCESS_TABLE_3
+ # RTS1 = 0x2 RPDB = 0x300 RTS2 = 0x5 RPDS = 13
+ b(0x40000000000300ad),
}
# nmigen Simulation
test_radixmiss_mmu()
### tests taken from src/soc/experiment/test/test_dcache.py
test_dcache_regression()
- #test_dcache_random()
+ test_dcache_random() #first access to memory fails - investigate
#TODO test_dcache()