add an extra domain dramsync2x in preparation for

AsyncBridge

diff --git a/src/ecp5_crg.py b/src/ecp5_crg.py
index 1740169befd5ffa2d8444a8ef59beaced7679eb6..239a5e624845881746cb563689aec174643fab0d 100644 (file)
--- a/src/ecp5_crg.py
+++ b/src/ecp5_crg.py
@@ -279,5 +279,11 @@ class ECP5CRG(Elaboratable):
         m.d.comb += ClockSignal("dramsync").eq(ClockSignal("sync"))
         m.d.comb += ResetSignal("dramsync").eq(reset_ok)
 
+        # and a dram 2x sigh
+        cd_dramsync2x = ClockDomain("dramsync2x", local=False)
+        m.domains += cd_dramsync2x
+        m.d.comb += ClockSignal("dramsync2x").eq(ClockSignal("sync2x"))
+        m.d.comb += ResetSignal("dramsync2x").eq(reset_ok)
+
         return m