Add HiFive1 target.

diff --git a/debug/targets.py b/debug/targets.py
index bcebc0b613ef83797a01fc4dc7d9d77370bf0223..52b623cc59262353b4a84d4582b1a862c1438588 100644 (file)
--- a/debug/targets.py
+++ b/debug/targets.py
@@ -92,6 +92,10 @@ class FreedomE300Target(Target):
     instruction_hardware_breakpoint_count = 2
     openocd_config = "targets/%s/openocd.cfg" % name
 
+class HiFive1Target(FreedomE300Target):
+    name = "HiFive1"
+    openocd_config = "targets/%s/openocd.cfg" % name
+
 class FreedomE300SimTarget(Target):
     name = "freedom-e300-sim"
     xlen = 32
@@ -130,7 +134,8 @@ targets = [
         FreedomE300Target,
         FreedomU500Target,
         FreedomE300SimTarget,
-        FreedomU500SimTarget]
+        FreedomU500SimTarget,
+        HiFive1Target]
 
 def add_target_options(parser):
     group = parser.add_mutually_exclusive_group(required=True)

diff --git a/debug/targets/HiFive1/link.lds b/debug/targets/HiFive1/link.lds
new file mode 100755 (executable)
index 0000000..1dbb99c
--- /dev/null
+++ b/debug/targets/HiFive1/link.lds
@@ -0,0 +1,34 @@
+OUTPUT_ARCH( "riscv" )
+
+SECTIONS
+{
+  . = 0x80000000;
+  .text : 
+  {
+    *(.text.entry)
+    *(.text)
+  }
+
+  /* data segment */
+  .data : { *(.data) }
+
+  .sdata : {
+    _gp = . + 0x800;
+    *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2)
+    *(.srodata*)
+    *(.sdata .sdata.* .gnu.linkonce.s.*)
+  }
+
+  /* bss segment */
+  .sbss : {
+    *(.sbss .sbss.* .gnu.linkonce.sb.*)
+    *(.scommon)
+  }
+  .bss : { *(.bss) }
+
+  __malloc_start = .;
+  . = . + 512;
+
+  /* End of uninitalized data segement */
+  _end = .;
+}

diff --git a/debug/targets/HiFive1/openocd.cfg b/debug/targets/HiFive1/openocd.cfg
new file mode 100644 (file)
index 0000000..d2c2879
--- /dev/null
+++ b/debug/targets/HiFive1/openocd.cfg
@@ -0,0 +1,23 @@
+adapter_khz     10000
+
+interface ftdi
+ftdi_device_desc "Dual RS232-HS"
+ftdi_vid_pid 0x0403 0x6010
+
+ftdi_layout_init 0x0008 0x001b
+ftdi_layout_signal nSRST -oe 0x0020
+
+# ...
+
+set _CHIPNAME riscv
+jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME riscv -chain-position $_TARGETNAME
+$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 8096 -work-area-backup 1
+
+flash bank my_first_flash fespi 0x20000000 0 0 0 $_TARGETNAME
+init
+#reset
+halt
+flash protect 0 64 last off