work-in-progress on DDR3 firmware. sigh

diff --git a/coldboot/Makefile b/coldboot/Makefile
index 1180178e7746f40420697d18e20179148876c391..01ec008b169ae6525ef6b32d78ab1dd78b361758 100644 (file)
--- a/coldboot/Makefile
+++ b/coldboot/Makefile
@@ -7,10 +7,10 @@ endif
 
 # a multiplier factor on sleep loops. this allows simulations to run
 # at much shorter intervals
-LONG_TIMER_MULT ?= 10000
-SHORT_TIMER_MULT ?= 100
-#LONG_TIMER_MULT ?= 1
-#SHORT_TIMER_MULT ?= 1
+LONG_TIMER_MULT = 10000
+SHORT_TIMER_MULT = 100
+#LONG_TIMER_MULT = 1
+#SHORT_TIMER_MULT = 1
 
 LIBGRAMDIR = ../libgram
 LIBGRAMINC = ../libgram/include

diff --git a/coldboot/coldboot.c b/coldboot/coldboot.c
index 408b90ce0e45344b0ec4bf3c9f35e4bf6e7ede17..2f1374f20c1881266981b1f76e30a86602e45f89 100644 (file)
--- a/coldboot/coldboot.c
+++ b/coldboot/coldboot.c
@@ -72,8 +72,8 @@ int main(void) {
                .mode_registers = {
                        0x320, 0x6, 0x200, 0x0
                },
-               .rdly_p0 = 0,
-               .rdly_p1 = 0,
+               .rdly_p0 = 5,
+               .rdly_p1 = 5,
        };
        struct gramProfile profile2;
        gram_init(&ctx, &profile, (void*)DRAM_BASE, //0x10000000,
@@ -91,7 +91,7 @@ int main(void) {
     return 0;
 #endif
 
-#if 0
+#if 1
        puts("Rdly\np0: ");
        for (size_t i = 0; i < 8; i++) {
                profile2.rdly_p0 = i;
@@ -149,21 +149,31 @@ int main(void) {
                writel(0xDEAF0000 | i*4, (unsigned long)&(ram[i]));
        }
 
-       for (size_t i = 0; i < kNumIterations; i++) {
-               if (readl((unsigned long)&(ram[i])) != (0xDEAF0000 | i*4)) {
-                       puts("fail : *(0x");
-                       uart_writeuint32(&ram[i]);
-                       puts(") = ");
-                       uart_writeuint32(ram[i]);
-                       puts("\n");
-                       failcnt++;
-
-                       if (failcnt > 10) {
-                               puts("Test canceled (more than 10 errors)\n");
-                               break;
-                       }
-               }
-       }
+       for (int dly = 0; dly < 8; dly++) {
+        failcnt = 0;
+        profile2.rdly_p0 = dly;
+        profile2.rdly_p1 = dly;
+        puts("p0 rdly:");
+        uart_writeuint32(profile2.rdly_p0);
+        puts(" p1 rdly:");
+        uart_writeuint32(profile2.rdly_p1);
+               gram_load_calibration(&ctx, &profile2);
+        for (size_t i = 0; i < kNumIterations; i++) {
+            if (readl((unsigned long)&(ram[i])) != (0xDEAF0000 | i*4)) {
+                puts("fail : *(0x");
+                uart_writeuint32(&ram[i]);
+                puts(") = ");
+                uart_writeuint32(ram[i]);
+                puts("\n");
+                failcnt++;
+
+                if (failcnt > 10) {
+                    puts("Test canceled (more than 10 errors)\n");
+                    break;
+                }
+            }
+        }
+    }
        puts("done\n");
 
        return 0;

diff --git a/libgram/src/dfii.c b/libgram/src/dfii.c
index a915a274b4d32fc051651260d5ca41fa1fd42621..3d873450729ddbe333cd5a99ec0e8b16b06e28e4 100644 (file)
--- a/libgram/src/dfii.c
+++ b/libgram/src/dfii.c
@@ -14,8 +14,10 @@ static void dfii_setcontrol(const struct gramCtx *ctx, uint32_t val) {
 #endif
 }
 
-void dfii_rst(const struct gramCtx *ctx) {
-               dfii_setcontrol(ctx, DFII_CONTROL_ODT| DFII_CONTROL_RESET);
+void dfii_reset(const struct gramCtx *ctx) {
+        dfii_set_p0_address(ctx, 0);
+        dfii_set_p0_baddress(ctx, 0);
+               dfii_setcontrol(ctx, DFII_CONTROL_ODT|DFII_CONTROL_RESET);
 }
 
 void dfii_setsw(const struct gramCtx *ctx, bool software_control) {
@@ -60,17 +62,21 @@ static void dfii_set_mr(const struct gramCtx *ctx, uint8_t mr, uint16_t val) {
        dfii_p0_command(ctx, DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS);
 }
 
+//comment these in to speed up icarus verilog simulations dramatically
+//#define LONG_TIMER_MULT 1
+//#define SHORT_TIMER_MULT 1
+
 #define MR0_DLL_RESET (1 << 8)
 void dfii_initseq(const struct gramCtx *ctx, const struct gramProfile *profile) {
        /* Release reset */
        dfii_set_p0_address(ctx, 0x0);
        dfii_set_p0_baddress(ctx, 0);
        dfii_setcontrol(ctx, DFII_CONTROL_ODT|DFII_CONTROL_RESET);
-       cdelay(5*LONG_TIMER_MULT);
+       //cdelay(5*LONG_TIMER_MULT);
 
        /* Bring CKE high */
-       dfii_set_p0_address(ctx, 0x0);
-       dfii_set_p0_baddress(ctx, 0);
+       //dfii_set_p0_address(ctx, 0x0);
+       //dfii_set_p0_baddress(ctx, 0);
        dfii_setcontrol(ctx, DFII_CONTROL_CKE|DFII_CONTROL_ODT|DFII_CONTROL_RESET);
        cdelay(1*LONG_TIMER_MULT);
 

diff --git a/libgram/src/init.c b/libgram/src/init.c
index 91d3fd2493f331bd0d6e2d81d5024f5e77bb8235..191ecb0e3a20f89f672907fab1e4021bef149b26 100644 (file)
--- a/libgram/src/init.c
+++ b/libgram/src/init.c
@@ -16,10 +16,6 @@ int gram_init(struct gramCtx *ctx, const struct gramProfile *profile, void *ddr_
     //puts("bdet");
     //uart_writeuint32((unsigned long)&(ctx->phy->burstdet));
 
-       //dfii_reset(ctx);
-    //puts("reset\n");
-       dfii_setsw(ctx, true);
-    //puts("dfii_setsw\n");
        dfii_initseq(ctx, profile);
     puts("initseq\n");
        gram_load_calibration(ctx, profile);

diff --git a/src/ls2.py b/src/ls2.py
index 9ca2e86564f916cf071ca5b9aec751c7aee9f459..e67e1ef35411235b82bd582246dd4f9d3ba9ecf8 100644 (file)
--- a/src/ls2.py
+++ b/src/ls2.py
@@ -339,8 +339,8 @@ class DDR3SoC(SoC, Elaboratable):
         if ddr_pins is not None or fpga == 'sim':
             ddrmodule = dram_cls(clk_freq, "1:2") # match DDR3 ASIC P/N
 
-            drs = lambda x: x
-            #drs = DomainRenamer("dramsync")
+            #drs = lambda x: x
+            drs = DomainRenamer("dramsync")
 
             if fpga == 'sim':
                 self.ddrphy = FakePHY(module=ddrmodule,
@@ -546,6 +546,8 @@ if __name__ == "__main__":
     clk_freq = 70e6
     if fpga == 'sim':
         clk_freq = 100e6
+    if fpga == 'versa_ecp5':
+        clk_freq = 55e6
 
     # select a firmware file
     firmware = None