attribute \generator "nMigen"
attribute \nmigen.hierarchy "test_issuer.core.pdecode2.dec.dec19"
module \dec19
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:229"
wire width 32 input 0 \opcode_in
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_11100 "Z23"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
wire width 5 output 2 \form
- attribute \enum_base_type "InternalOp"
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
+ attribute \enum_value_1001010 "OP_MTMSR"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
wire width 7 output 3 \internal_op
attribute \enum_base_type "In1Sel"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "RC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
wire width 2 output 10 \rc_sel
attribute \enum_base_type "LdstLen"
attribute \enum_value_0000 "NONE"
attribute \enum_value_1000 "is8B"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
wire width 4 output 11 \ldst_len
+ attribute \enum_base_type "LDSTMode"
+ attribute \enum_value_00 "NONE"
+ attribute \enum_value_01 "update"
+ attribute \enum_value_10 "cix"
+ attribute \enum_value_11 "cx"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+ wire width 2 output 12 \upd
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
- wire width 2 output 12 \cry_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 13 \inv_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 14 \inv_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 15 \cry_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 16 \br
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 17 \sgn_ext
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 18 \upd
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
+ wire width 2 output 13 \cry_in
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 14 \inv_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 15 \inv_out
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 16 \cry_out
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 17 \br
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 18 \sgn_ext
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 output 19 \rsrv
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 output 20 \is_32b
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 output 21 \sgn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 output 22 \lk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 output 23 \sgl_pipe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
wire width 8 output 24 \asmcode
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:257"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:267"
wire width 10 \opcode_switch
process $group_0
assign \opcode_switch 10'0000000000
assign \opcode_switch \opcode_in [10:1]
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:257"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:267"
wire width 5 \opcode_switch$1
process $group_1
assign \function_unit 11'00000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0000000000
assign \function_unit 11'00001000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0100000001
assign \function_unit 11'00001000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0010000001
assign \function_unit 11'00001000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0100100001
assign \function_unit 11'00001000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0011100001
assign \function_unit 11'00001000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0000100001
assign \function_unit 11'00001000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0111000001
assign \function_unit 11'00001000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0110100001
assign \function_unit 11'00001000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0011000001
assign \function_unit 11'00001000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'1000010000
assign \function_unit 11'00000100000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0000010000
assign \function_unit 11'00000100000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'1000110000
assign \function_unit 11'00000100000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0010010110
assign \function_unit 11'00000000010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0000010010
assign \function_unit 11'00010000000
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch$1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \function_unit 11'00000000010
end
end
process $group_2
assign \form 5'00000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0000000000
assign \form 5'01001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0100000001
assign \form 5'01001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0010000001
assign \form 5'01001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0100100001
assign \form 5'01001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0011100001
assign \form 5'01001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0000100001
assign \form 5'01001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0111000001
assign \form 5'01001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0110100001
assign \form 5'01001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0011000001
assign \form 5'01001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'1000010000
assign \form 5'01001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0000010000
assign \form 5'01001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'1000110000
assign \form 5'01001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0010010110
assign \form 5'01001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0000010010
assign \form 5'01001
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch$1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \form 5'00111
end
end
process $group_3
assign \internal_op 7'0000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0000000000
assign \internal_op 7'0101010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0100000001
assign \internal_op 7'1000101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0010000001
assign \internal_op 7'1000101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0100100001
assign \internal_op 7'1000101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0011100001
assign \internal_op 7'1000101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0000100001
assign \internal_op 7'1000101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0111000001
assign \internal_op 7'1000101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0110100001
assign \internal_op 7'1000101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0011000001
assign \internal_op 7'1000101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'1000010000
assign \internal_op 7'0001000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0000010000
assign \internal_op 7'0001000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'1000110000
assign \internal_op 7'0001000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0010010110
assign \internal_op 7'0100100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0000010010
assign \internal_op 7'1000110
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch$1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \internal_op 7'0000000
end
end
process $group_4
assign \in1_sel 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0000000000
assign \in1_sel 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0100000001
assign \in1_sel 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0010000001
assign \in1_sel 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0100100001
assign \in1_sel 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0011100001
assign \in1_sel 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0000100001
assign \in1_sel 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0111000001
assign \in1_sel 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0110100001
assign \in1_sel 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0011000001
assign \in1_sel 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'1000010000
assign \in1_sel 3'011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0000010000
assign \in1_sel 3'011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'1000110000
assign \in1_sel 3'011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0010010110
assign \in1_sel 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0000010010
assign \in1_sel 3'011
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch$1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \in1_sel 3'000
end
end
process $group_5
assign \in2_sel 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0000000000
assign \in2_sel 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0100000001
assign \in2_sel 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0010000001
assign \in2_sel 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0100100001
assign \in2_sel 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0011100001
assign \in2_sel 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0000100001
assign \in2_sel 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0111000001
assign \in2_sel 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0110100001
assign \in2_sel 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0011000001
assign \in2_sel 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'1000010000
assign \in2_sel 4'1100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0000010000
assign \in2_sel 4'1100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'1000110000
assign \in2_sel 4'1100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0010010110
assign \in2_sel 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0000010010
assign \in2_sel 4'1100
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch$1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \in2_sel 4'0000
end
end
process $group_6
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0000000000
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0100000001
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0010000001
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0100100001
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0011100001
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0000100001
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0111000001
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0110100001
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0011000001
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'1000010000
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0000010000
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'1000110000
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0010010110
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0000010010
assign \in3_sel 2'00
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch$1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \in3_sel 2'00
end
end
process $group_7
assign \out_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0000000000
assign \out_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0100000001
assign \out_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0010000001
assign \out_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0100100001
assign \out_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0011100001
assign \out_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0000100001
assign \out_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0111000001
assign \out_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0110100001
assign \out_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0011000001
assign \out_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'1000010000
assign \out_sel 2'11
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0000010000
assign \out_sel 2'11
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'1000110000
assign \out_sel 2'11
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0010010110
assign \out_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0000010010
assign \out_sel 2'00
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch$1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \out_sel 2'00
end
end
process $group_8
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0000000000
assign \cr_in 3'011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0100000001
assign \cr_in 3'100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0010000001
assign \cr_in 3'100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0100100001
assign \cr_in 3'100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0011100001
assign \cr_in 3'100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0000100001
assign \cr_in 3'100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0111000001
assign \cr_in 3'100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0110100001
assign \cr_in 3'100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0011000001
assign \cr_in 3'100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'1000010000
assign \cr_in 3'010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0000010000
assign \cr_in 3'010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'1000110000
assign \cr_in 3'010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0010010110
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0000010010
assign \cr_in 3'000
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch$1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \cr_in 3'000
end
end
process $group_9
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0000000000
assign \cr_out 3'010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0100000001
assign \cr_out 3'011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0010000001
assign \cr_out 3'011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0100100001
assign \cr_out 3'011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0011100001
assign \cr_out 3'011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0000100001
assign \cr_out 3'011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0111000001
assign \cr_out 3'011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0110100001
assign \cr_out 3'011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0011000001
assign \cr_out 3'011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'1000010000
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0000010000
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'1000110000
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0010010110
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0000010010
assign \cr_out 3'000
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch$1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \cr_out 3'000
end
end
process $group_10
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0000000000
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0100000001
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0010000001
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0100100001
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0011100001
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0000100001
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0111000001
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0110100001
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0011000001
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'1000010000
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0000010000
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'1000110000
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0010010110
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0000010010
assign \ldst_len 4'0000
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch$1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \ldst_len 4'0000
end
sync init
end
process $group_11
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+ switch \opcode_switch
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 10'0000000000
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 10'0100000001
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 10'0010000001
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 10'0100100001
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 10'0011100001
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 10'0000100001
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 10'0111000001
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 10'0110100001
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 10'0011000001
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 10'1000010000
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 10'0000010000
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 10'1000110000
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 10'0010010110
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 10'0000010010
+ assign \upd 2'00
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+ switch \opcode_switch$1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00010
+ assign \upd 2'00
+ end
+ sync init
+ end
+ process $group_12
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0000000000
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0100000001
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0010000001
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0100100001
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0011100001
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0000100001
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0111000001
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0110100001
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0011000001
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'1000010000
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0000010000
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'1000110000
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0010010110
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0000010010
assign \rc_sel 2'00
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch$1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \rc_sel 2'10
end
sync init
end
- process $group_12
+ process $group_13
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0000000000
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0100000001
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0010000001
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0100100001
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0011100001
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0000100001
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0111000001
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0110100001
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0011000001
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'1000010000
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0000010000
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'1000110000
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0010010110
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0000010010
assign \cry_in 2'00
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch$1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \cry_in 2'00
end
sync init
end
- process $group_13
+ process $group_14
assign \asmcode 8'00000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0000000000
assign \asmcode 8'01101010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0100000001
assign \asmcode 8'00100101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0010000001
assign \asmcode 8'00100110
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0100100001
assign \asmcode 8'00100111
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0011100001
assign \asmcode 8'00101000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0000100001
assign \asmcode 8'00101001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0111000001
assign \asmcode 8'00101010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0110100001
assign \asmcode 8'00101011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0011000001
assign \asmcode 8'00101100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'1000010000
assign \asmcode 8'00010110
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0000010000
assign \asmcode 8'00010111
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'1000110000
assign \asmcode 8'00011000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0010010110
assign \asmcode 8'01001011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0000010010
- assign \asmcode 8'10001110
+ assign \asmcode 8'10001111
end
sync init
end
- process $group_14
+ process $group_15
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0000000000
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0100000001
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0010000001
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0100100001
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0011100001
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0000100001
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0111000001
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0110100001
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0011000001
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'1000010000
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0000010000
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'1000110000
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0010010110
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0000010010
assign \inv_a 1'0
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch$1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \inv_a 1'0
end
sync init
end
- process $group_15
+ process $group_16
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0000000000
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0100000001
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0010000001
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0100100001
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0011100001
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0000100001
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0111000001
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0110100001
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0011000001
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'1000010000
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0000010000
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'1000110000
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0010010110
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0000010010
assign \inv_out 1'0
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch$1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \inv_out 1'0
end
sync init
end
- process $group_16
+ process $group_17
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0000000000
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0100000001
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0010000001
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0100100001
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0011100001
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0000100001
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0111000001
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0110100001
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0011000001
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'1000010000
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0000010000
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'1000110000
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0010010110
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0000010010
assign \cry_out 1'0
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch$1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \cry_out 1'0
end
sync init
end
- process $group_17
+ process $group_18
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0000000000
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0100000001
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0010000001
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0100100001
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0011100001
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0000100001
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0111000001
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0110100001
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0011000001
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'1000010000
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0000010000
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'1000110000
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0010010110
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0000010010
assign \br 1'0
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch$1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \br 1'0
end
sync init
end
- process $group_18
+ process $group_19
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0000000000
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0100000001
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0010000001
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0100100001
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0011100001
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0000100001
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0111000001
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0110100001
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0011000001
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'1000010000
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0000010000
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'1000110000
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0010010110
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0000010010
assign \sgn_ext 1'0
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch$1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \sgn_ext 1'0
end
sync init
end
- process $group_19
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
- switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 10'0000000000
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 10'0100000001
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 10'0010000001
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 10'0100100001
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 10'0011100001
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 10'0000100001
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 10'0111000001
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 10'0110100001
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 10'0011000001
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 10'1000010000
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 10'0000010000
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 10'1000110000
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 10'0010010110
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 10'0000010010
- assign \upd 1'0
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
- switch \opcode_switch$1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00010
- assign \upd 1'0
- end
- sync init
- end
process $group_20
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0000000000
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0100000001
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0010000001
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0100100001
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0011100001
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0000100001
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0111000001
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0110100001
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0011000001
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'1000010000
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0000010000
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'1000110000
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0010010110
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0000010010
assign \rsrv 1'0
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch$1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \rsrv 1'0
end
end
process $group_21
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0000000000
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0100000001
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0010000001
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0100100001
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0011100001
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0000100001
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0111000001
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0110100001
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0011000001
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'1000010000
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0000010000
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'1000110000
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0010010110
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0000010010
assign \is_32b 1'0
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch$1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \is_32b 1'0
end
end
process $group_22
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0000000000
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0100000001
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0010000001
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0100100001
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0011100001
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0000100001
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0111000001
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0110100001
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0011000001
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'1000010000
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0000010000
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'1000110000
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0010010110
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0000010010
assign \sgn 1'0
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch$1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \sgn 1'0
end
end
process $group_23
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0000000000
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0100000001
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0010000001
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0100100001
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0011100001
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0000100001
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0111000001
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0110100001
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0011000001
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'1000010000
assign \lk 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0000010000
assign \lk 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'1000110000
assign \lk 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0010010110
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0000010010
assign \lk 1'0
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch$1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \lk 1'0
end
end
process $group_24
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0000000000
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0100000001
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0010000001
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0100100001
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0011100001
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0000100001
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0111000001
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0110100001
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0011000001
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'1000010000
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0000010000
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'1000110000
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0010010110
assign \sgl_pipe 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 10'0000010010
assign \sgl_pipe 1'0
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch$1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \sgl_pipe 1'1
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "test_issuer.core.pdecode2.dec.dec30"
module \dec30
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:229"
wire width 32 input 0 \opcode_in
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_11100 "Z23"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
wire width 5 output 2 \form
- attribute \enum_base_type "InternalOp"
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
+ attribute \enum_value_1001010 "OP_MTMSR"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
wire width 7 output 3 \internal_op
attribute \enum_base_type "In1Sel"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "RC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
wire width 2 output 10 \rc_sel
attribute \enum_base_type "LdstLen"
attribute \enum_value_0000 "NONE"
attribute \enum_value_1000 "is8B"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
wire width 4 output 11 \ldst_len
+ attribute \enum_base_type "LDSTMode"
+ attribute \enum_value_00 "NONE"
+ attribute \enum_value_01 "update"
+ attribute \enum_value_10 "cix"
+ attribute \enum_value_11 "cx"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+ wire width 2 output 12 \upd
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
- wire width 2 output 12 \cry_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 13 \inv_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 14 \inv_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 15 \cry_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 16 \br
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 17 \sgn_ext
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 18 \upd
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
+ wire width 2 output 13 \cry_in
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 14 \inv_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 15 \inv_out
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 16 \cry_out
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 17 \br
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 18 \sgn_ext
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 output 19 \rsrv
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 output 20 \is_32b
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 output 21 \sgn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 output 22 \lk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 output 23 \sgl_pipe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
wire width 8 output 24 \asmcode
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:257"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:267"
wire width 4 \opcode_switch
process $group_0
assign \opcode_switch 4'0000
end
process $group_1
assign \function_unit 11'00000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0100
assign \function_unit 11'00000001000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0101
assign \function_unit 11'00000001000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0000
assign \function_unit 11'00000001000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0001
assign \function_unit 11'00000001000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0010
assign \function_unit 11'00000001000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0011
assign \function_unit 11'00000001000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0110
assign \function_unit 11'00000001000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0111
assign \function_unit 11'00000001000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'1000
assign \function_unit 11'00000001000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'1001
assign \function_unit 11'00000001000
end
end
process $group_2
assign \form 5'00000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0100
assign \form 5'10100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0101
assign \form 5'10100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0000
assign \form 5'10101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0001
assign \form 5'10101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0010
assign \form 5'10100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0011
assign \form 5'10100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0110
assign \form 5'10100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0111
assign \form 5'10100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'1000
assign \form 5'10100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'1001
assign \form 5'10100
end
end
process $group_3
assign \internal_op 7'0000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0100
assign \internal_op 7'0111000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0101
assign \internal_op 7'0111000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0000
assign \internal_op 7'0111001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0001
assign \internal_op 7'0111001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0010
assign \internal_op 7'0111010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0011
assign \internal_op 7'0111010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0110
assign \internal_op 7'0111000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0111
assign \internal_op 7'0111000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'1000
assign \internal_op 7'0111001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'1001
assign \internal_op 7'0111010
end
end
process $group_4
assign \in1_sel 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0100
assign \in1_sel 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0101
assign \in1_sel 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0000
assign \in1_sel 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0001
assign \in1_sel 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0010
assign \in1_sel 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0011
assign \in1_sel 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0110
assign \in1_sel 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0111
assign \in1_sel 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'1000
assign \in1_sel 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'1001
assign \in1_sel 3'000
end
end
process $group_5
assign \in2_sel 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0100
assign \in2_sel 4'1010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0101
assign \in2_sel 4'1010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0000
assign \in2_sel 4'1010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0001
assign \in2_sel 4'1010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0010
assign \in2_sel 4'1010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0011
assign \in2_sel 4'1010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0110
assign \in2_sel 4'1010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0111
assign \in2_sel 4'1010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'1000
assign \in2_sel 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'1001
assign \in2_sel 4'0001
end
end
process $group_6
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0100
assign \in3_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0101
assign \in3_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0000
assign \in3_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0001
assign \in3_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0010
assign \in3_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0011
assign \in3_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0110
assign \in3_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0111
assign \in3_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'1000
assign \in3_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'1001
assign \in3_sel 2'01
end
end
process $group_7
assign \out_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0100
assign \out_sel 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0101
assign \out_sel 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0000
assign \out_sel 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0001
assign \out_sel 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0010
assign \out_sel 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0011
assign \out_sel 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0110
assign \out_sel 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0111
assign \out_sel 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'1000
assign \out_sel 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'1001
assign \out_sel 2'10
end
end
process $group_8
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0100
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0101
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0000
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0001
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0010
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0011
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0110
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0111
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'1000
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'1001
assign \cr_in 3'000
end
end
process $group_9
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0100
assign \cr_out 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0101
assign \cr_out 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0000
assign \cr_out 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0001
assign \cr_out 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0010
assign \cr_out 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0011
assign \cr_out 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0110
assign \cr_out 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0111
assign \cr_out 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'1000
assign \cr_out 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'1001
assign \cr_out 3'001
end
end
process $group_10
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0100
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0101
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0000
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0001
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0010
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0011
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0110
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0111
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'1000
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'1001
assign \ldst_len 4'0000
end
sync init
end
process $group_11
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+ switch \opcode_switch
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 4'0100
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 4'0101
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 4'0000
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 4'0001
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 4'0010
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 4'0011
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 4'0110
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 4'0111
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 4'1000
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 4'1001
+ assign \upd 2'00
+ end
+ sync init
+ end
+ process $group_12
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0100
assign \rc_sel 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0101
assign \rc_sel 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0000
assign \rc_sel 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0001
assign \rc_sel 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0010
assign \rc_sel 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0011
assign \rc_sel 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0110
assign \rc_sel 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0111
assign \rc_sel 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'1000
assign \rc_sel 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'1001
assign \rc_sel 2'10
end
sync init
end
- process $group_12
+ process $group_13
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0100
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0101
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0000
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0001
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0010
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0011
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0110
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0111
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'1000
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'1001
assign \cry_in 2'00
end
sync init
end
- process $group_13
+ process $group_14
assign \asmcode 8'00000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0100
- assign \asmcode 8'10010001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ assign \asmcode 8'10010010
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0101
- assign \asmcode 8'10010001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 4'0000
assign \asmcode 8'10010010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 4'0000
+ assign \asmcode 8'10010011
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0001
- assign \asmcode 8'10010010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 4'0010
assign \asmcode 8'10010011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 4'0010
+ assign \asmcode 8'10010100
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0011
- assign \asmcode 8'10010011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 4'0110
assign \asmcode 8'10010100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 4'0110
+ assign \asmcode 8'10010101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0111
- assign \asmcode 8'10010100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ assign \asmcode 8'10010101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'1000
- assign \asmcode 8'10001111
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 4'1001
assign \asmcode 8'10010000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 4'1001
+ assign \asmcode 8'10010001
end
sync init
end
- process $group_14
+ process $group_15
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0100
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0101
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0000
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0001
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0010
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0011
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0110
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0111
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'1000
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'1001
assign \inv_a 1'0
end
sync init
end
- process $group_15
+ process $group_16
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0100
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0101
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0000
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0001
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0010
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0011
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0110
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0111
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'1000
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'1001
assign \inv_out 1'0
end
sync init
end
- process $group_16
+ process $group_17
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0100
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0101
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0000
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0001
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0010
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0011
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0110
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0111
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'1000
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'1001
assign \cry_out 1'0
end
sync init
end
- process $group_17
+ process $group_18
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0100
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0101
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0000
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0001
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0010
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0011
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0110
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0111
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'1000
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'1001
assign \br 1'0
end
sync init
end
- process $group_18
+ process $group_19
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0100
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0101
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0000
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0001
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0010
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0011
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0110
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0111
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'1000
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'1001
assign \sgn_ext 1'0
end
sync init
end
- process $group_19
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
- switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 4'0100
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 4'0101
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 4'0000
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 4'0001
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 4'0010
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 4'0011
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 4'0110
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 4'0111
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 4'1000
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 4'1001
- assign \upd 1'0
- end
- sync init
- end
process $group_20
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0100
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0101
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0000
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0001
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0010
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0011
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0110
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0111
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'1000
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'1001
assign \rsrv 1'0
end
end
process $group_21
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0100
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0101
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0000
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0001
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0010
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0011
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0110
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0111
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'1000
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'1001
assign \is_32b 1'0
end
end
process $group_22
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0100
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0101
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0000
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0001
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0010
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0011
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0110
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0111
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'1000
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'1001
assign \sgn 1'0
end
end
process $group_23
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0100
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0101
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0000
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0001
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0010
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0011
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0110
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0111
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'1000
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'1001
assign \lk 1'0
end
end
process $group_24
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0100
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0101
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0000
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0001
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0010
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0011
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0110
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'0111
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'1000
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 4'1001
assign \sgl_pipe 1'0
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "test_issuer.core.pdecode2.dec.dec31.dec_sub10"
module \dec_sub10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:229"
wire width 32 input 0 \opcode_in
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_11100 "Z23"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
wire width 5 output 2 \form
- attribute \enum_base_type "InternalOp"
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
+ attribute \enum_value_1001010 "OP_MTMSR"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
wire width 7 output 3 \internal_op
attribute \enum_base_type "In1Sel"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "RC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
wire width 2 output 10 \rc_sel
attribute \enum_base_type "LdstLen"
attribute \enum_value_0000 "NONE"
attribute \enum_value_1000 "is8B"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
wire width 4 output 11 \ldst_len
+ attribute \enum_base_type "LDSTMode"
+ attribute \enum_value_00 "NONE"
+ attribute \enum_value_01 "update"
+ attribute \enum_value_10 "cix"
+ attribute \enum_value_11 "cx"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+ wire width 2 output 12 \upd
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
- wire width 2 output 12 \cry_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 13 \inv_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 14 \inv_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 15 \cry_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 16 \br
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 17 \sgn_ext
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 18 \upd
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
+ wire width 2 output 13 \cry_in
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 14 \inv_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 15 \inv_out
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 16 \cry_out
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 17 \br
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 18 \sgn_ext
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 output 19 \rsrv
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 output 20 \is_32b
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 output 21 \sgn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 output 22 \lk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 output 23 \sgl_pipe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
wire width 8 output 24 \asmcode
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:257"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:267"
wire width 5 \opcode_switch
process $group_0
assign \opcode_switch 5'00000
end
process $group_1
assign \function_unit 11'00000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \function_unit 11'00000000010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \function_unit 11'00000000010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \function_unit 11'00000000010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \function_unit 11'00000000010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \function_unit 11'00000000010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10100
assign \function_unit 11'00000000010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \function_unit 11'00000000010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10111
assign \function_unit 11'00000000010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00110
assign \function_unit 11'00000000010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10110
assign \function_unit 11'00000000010
end
end
process $group_2
assign \form 5'00000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \form 5'10001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \form 5'10001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \form 5'10001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \form 5'10001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \form 5'10001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10100
assign \form 5'10001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \form 5'10001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10111
assign \form 5'10001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00110
assign \form 5'10001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10110
assign \form 5'10001
end
end
process $group_3
assign \internal_op 7'0000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \internal_op 7'0000010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \internal_op 7'0000010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \internal_op 7'0000010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \internal_op 7'0000010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \internal_op 7'0000010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10100
assign \internal_op 7'0000010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \internal_op 7'0000010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10111
assign \internal_op 7'0000010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00110
assign \internal_op 7'0000010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10110
assign \internal_op 7'0000010
end
end
process $group_4
assign \in1_sel 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \in1_sel 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \in1_sel 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \in1_sel 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \in1_sel 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \in1_sel 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10100
assign \in1_sel 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \in1_sel 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10111
assign \in1_sel 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00110
assign \in1_sel 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10110
assign \in1_sel 3'001
end
end
process $group_5
assign \in2_sel 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \in2_sel 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \in2_sel 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \in2_sel 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \in2_sel 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \in2_sel 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10100
assign \in2_sel 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \in2_sel 4'1001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10111
assign \in2_sel 4'1001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00110
assign \in2_sel 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10110
assign \in2_sel 4'0000
end
end
process $group_6
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10100
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10111
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00110
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10110
assign \in3_sel 2'00
end
end
process $group_7
assign \out_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \out_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \out_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \out_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \out_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \out_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10100
assign \out_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \out_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10111
assign \out_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00110
assign \out_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10110
assign \out_sel 2'01
end
end
process $group_8
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10100
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10111
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00110
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10110
assign \cr_in 3'000
end
end
process $group_9
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \cr_out 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \cr_out 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \cr_out 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \cr_out 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \cr_out 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10100
assign \cr_out 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \cr_out 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10111
assign \cr_out 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00110
assign \cr_out 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10110
assign \cr_out 3'001
end
end
process $group_10
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10100
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10111
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00110
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10110
assign \ldst_len 4'0000
end
sync init
end
process $group_11
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+ switch \opcode_switch
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01000
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11000
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00000
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'10000
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00100
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'10100
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00111
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'10111
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00110
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'10110
+ assign \upd 2'00
+ end
+ sync init
+ end
+ process $group_12
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \rc_sel 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \rc_sel 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \rc_sel 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \rc_sel 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \rc_sel 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10100
assign \rc_sel 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \rc_sel 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10111
assign \rc_sel 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00110
assign \rc_sel 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10110
assign \rc_sel 2'10
end
sync init
end
- process $group_12
+ process $group_13
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \cry_in 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10100
assign \cry_in 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \cry_in 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10111
assign \cry_in 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00110
assign \cry_in 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10110
assign \cry_in 2'10
end
sync init
end
- process $group_13
+ process $group_14
assign \asmcode 8'00000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \asmcode 8'00000001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \asmcode 8'00001100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \asmcode 8'00000010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \asmcode 8'00000011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \asmcode 8'00000100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10100
assign \asmcode 8'00000101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \asmcode 8'00001010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10111
assign \asmcode 8'00001011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00110
assign \asmcode 8'00001101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10110
assign \asmcode 8'00001110
end
sync init
end
- process $group_14
+ process $group_15
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10100
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10111
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00110
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10110
assign \inv_a 1'0
end
sync init
end
- process $group_15
+ process $group_16
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10100
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10111
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00110
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10110
assign \inv_out 1'0
end
sync init
end
- process $group_16
+ process $group_17
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \cry_out 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \cry_out 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \cry_out 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10100
assign \cry_out 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \cry_out 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10111
assign \cry_out 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00110
assign \cry_out 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10110
assign \cry_out 1'1
end
sync init
end
- process $group_17
+ process $group_18
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10100
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10111
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00110
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10110
assign \br 1'0
end
sync init
end
- process $group_18
+ process $group_19
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10100
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10111
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00110
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10110
assign \sgn_ext 1'0
end
sync init
end
- process $group_19
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
- switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01000
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'11000
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00000
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'10000
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00100
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'10100
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00111
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'10111
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00110
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'10110
- assign \upd 1'0
- end
- sync init
- end
process $group_20
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10100
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10111
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00110
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10110
assign \rsrv 1'0
end
end
process $group_21
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10100
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10111
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00110
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10110
assign \is_32b 1'0
end
end
process $group_22
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10100
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10111
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00110
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10110
assign \sgn 1'0
end
end
process $group_23
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10100
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10111
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00110
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10110
assign \lk 1'0
end
end
process $group_24
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10100
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10111
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00110
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10110
assign \sgl_pipe 1'0
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "test_issuer.core.pdecode2.dec.dec31.dec_sub28"
module \dec_sub28
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:229"
wire width 32 input 0 \opcode_in
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_11100 "Z23"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
wire width 5 output 2 \form
- attribute \enum_base_type "InternalOp"
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
+ attribute \enum_value_1001010 "OP_MTMSR"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
wire width 7 output 3 \internal_op
attribute \enum_base_type "In1Sel"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "RC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
wire width 2 output 10 \rc_sel
attribute \enum_base_type "LdstLen"
attribute \enum_value_0000 "NONE"
attribute \enum_value_1000 "is8B"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
wire width 4 output 11 \ldst_len
+ attribute \enum_base_type "LDSTMode"
+ attribute \enum_value_00 "NONE"
+ attribute \enum_value_01 "update"
+ attribute \enum_value_10 "cix"
+ attribute \enum_value_11 "cx"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+ wire width 2 output 12 \upd
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
- wire width 2 output 12 \cry_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 13 \inv_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 14 \inv_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 15 \cry_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 16 \br
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 17 \sgn_ext
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 18 \upd
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
+ wire width 2 output 13 \cry_in
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 14 \inv_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 15 \inv_out
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 16 \cry_out
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 17 \br
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 18 \sgn_ext
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 output 19 \rsrv
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 output 20 \is_32b
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 output 21 \sgn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 output 22 \lk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 output 23 \sgl_pipe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
wire width 8 output 24 \asmcode
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:257"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:267"
wire width 5 \opcode_switch
process $group_0
assign \opcode_switch 5'00000
end
process $group_1
assign \function_unit 11'00000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \function_unit 11'00000010000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \function_unit 11'00000010000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \function_unit 11'00000010000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01111
assign \function_unit 11'00000010000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \function_unit 11'00000010000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01110
assign \function_unit 11'00000010000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00011
assign \function_unit 11'00000010000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01101
assign \function_unit 11'00000010000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01100
assign \function_unit 11'00000010000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01001
assign \function_unit 11'00000010000
end
end
process $group_2
assign \form 5'00000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \form 5'01000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \form 5'01000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \form 5'01000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01111
assign \form 5'01000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \form 5'01000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01110
assign \form 5'01000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00011
assign \form 5'01000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01101
assign \form 5'01000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01100
assign \form 5'01000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01001
assign \form 5'01000
end
end
process $group_3
assign \internal_op 7'0000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \internal_op 7'0000100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \internal_op 7'0000100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \internal_op 7'0001001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01111
assign \internal_op 7'0001011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \internal_op 7'1000011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01110
assign \internal_op 7'0000100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00011
assign \internal_op 7'0110101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01101
assign \internal_op 7'0110101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01100
assign \internal_op 7'0110101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01001
assign \internal_op 7'1000011
end
end
process $group_4
assign \in1_sel 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \in1_sel 3'100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \in1_sel 3'100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \in1_sel 3'100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01111
assign \in1_sel 3'100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \in1_sel 3'100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01110
assign \in1_sel 3'100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00011
assign \in1_sel 3'100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01101
assign \in1_sel 3'100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01100
assign \in1_sel 3'100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01001
assign \in1_sel 3'100
end
end
process $group_5
assign \in2_sel 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \in2_sel 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \in2_sel 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \in2_sel 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01111
assign \in2_sel 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \in2_sel 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01110
assign \in2_sel 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00011
assign \in2_sel 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01101
assign \in2_sel 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01100
assign \in2_sel 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01001
assign \in2_sel 4'0001
end
end
process $group_6
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01111
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01110
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00011
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01101
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01100
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01001
assign \in3_sel 2'00
end
end
process $group_7
assign \out_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \out_sel 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \out_sel 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \out_sel 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01111
assign \out_sel 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \out_sel 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01110
assign \out_sel 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00011
assign \out_sel 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01101
assign \out_sel 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01100
assign \out_sel 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01001
assign \out_sel 2'10
end
end
process $group_8
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01111
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01110
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00011
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01101
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01100
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01001
assign \cr_in 3'000
end
end
process $group_9
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \cr_out 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \cr_out 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01111
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \cr_out 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01110
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00011
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01101
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01100
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01001
assign \cr_out 3'001
end
end
process $group_10
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01111
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01110
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00011
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01101
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01100
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01001
assign \ldst_len 4'0000
end
sync init
end
process $group_11
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+ switch \opcode_switch
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00000
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00001
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00111
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01111
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01000
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01110
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00011
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01101
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01100
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01001
+ assign \upd 2'00
+ end
+ sync init
+ end
+ process $group_12
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \rc_sel 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \rc_sel 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01111
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \rc_sel 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01110
assign \rc_sel 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00011
assign \rc_sel 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01101
assign \rc_sel 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01100
assign \rc_sel 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01001
assign \rc_sel 2'10
end
sync init
end
- process $group_12
+ process $group_13
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01111
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01110
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00011
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01101
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01100
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01001
assign \cry_in 2'00
end
sync init
end
- process $group_13
+ process $group_14
assign \asmcode 8'00000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \asmcode 8'00001111
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \asmcode 8'00010000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \asmcode 8'00011001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01111
assign \asmcode 8'00011011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \asmcode 8'01000011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01110
- assign \asmcode 8'10000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ assign \asmcode 8'10000001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00011
- assign \asmcode 8'10000100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01101
assign \asmcode 8'10000101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01100
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01101
assign \asmcode 8'10000110
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01100
+ assign \asmcode 8'10000111
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01001
- assign \asmcode 8'11001001
+ assign \asmcode 8'11001010
end
sync init
end
- process $group_14
+ process $group_15
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \inv_a 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01111
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01110
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00011
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01101
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01100
assign \inv_a 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01001
assign \inv_a 1'0
end
sync init
end
- process $group_15
+ process $group_16
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01111
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \inv_out 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01110
assign \inv_out 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00011
assign \inv_out 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01101
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01100
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01001
assign \inv_out 1'0
end
sync init
end
- process $group_16
+ process $group_17
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01111
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01110
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00011
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01101
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01100
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01001
assign \cry_out 1'0
end
sync init
end
- process $group_17
+ process $group_18
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01111
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01110
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00011
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01101
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01100
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01001
assign \br 1'0
end
sync init
end
- process $group_18
+ process $group_19
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01111
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01110
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00011
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01101
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01100
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01001
assign \sgn_ext 1'0
end
sync init
end
- process $group_19
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
- switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00000
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00001
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00111
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01111
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01000
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01110
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00011
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01101
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01100
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01001
- assign \upd 1'0
- end
- sync init
- end
process $group_20
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01111
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01110
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00011
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01101
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01100
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01001
assign \rsrv 1'0
end
end
process $group_21
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01111
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01110
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00011
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01101
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01100
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01001
assign \is_32b 1'0
end
end
process $group_22
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01111
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01110
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00011
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01101
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01100
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01001
assign \sgn 1'0
end
end
process $group_23
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01111
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01110
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00011
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01101
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01100
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01001
assign \lk 1'0
end
end
process $group_24
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01111
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01110
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00011
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01101
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01100
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01001
assign \sgl_pipe 1'0
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "test_issuer.core.pdecode2.dec.dec31.dec_sub0"
module \dec_sub0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:229"
wire width 32 input 0 \opcode_in
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_11100 "Z23"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
wire width 5 output 2 \form
- attribute \enum_base_type "InternalOp"
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
+ attribute \enum_value_1001010 "OP_MTMSR"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
wire width 7 output 3 \internal_op
attribute \enum_base_type "In1Sel"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "RC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
wire width 2 output 10 \rc_sel
attribute \enum_base_type "LdstLen"
attribute \enum_value_0000 "NONE"
attribute \enum_value_1000 "is8B"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
wire width 4 output 11 \ldst_len
+ attribute \enum_base_type "LDSTMode"
+ attribute \enum_value_00 "NONE"
+ attribute \enum_value_01 "update"
+ attribute \enum_value_10 "cix"
+ attribute \enum_value_11 "cx"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+ wire width 2 output 12 \upd
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
- wire width 2 output 12 \cry_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 13 \inv_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 14 \inv_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 15 \cry_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 16 \br
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 17 \sgn_ext
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 18 \upd
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
+ wire width 2 output 13 \cry_in
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 14 \inv_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 15 \inv_out
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 16 \cry_out
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 17 \br
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 18 \sgn_ext
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 output 19 \rsrv
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 output 20 \is_32b
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 output 21 \sgn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 output 22 \lk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 output 23 \sgl_pipe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
wire width 8 output 24 \asmcode
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:257"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:267"
wire width 5 \opcode_switch
process $group_0
assign \opcode_switch 5'00000
end
process $group_1
assign \function_unit 11'00000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \function_unit 11'00000000010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \function_unit 11'00000000010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \function_unit 11'00000000010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \function_unit 11'00001000000
end
end
process $group_2
assign \form 5'00000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \form 5'01000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \form 5'01000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \form 5'01000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \form 5'11000
end
end
process $group_3
assign \internal_op 7'0000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \internal_op 7'0001010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \internal_op 7'0001100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \internal_op 7'0001010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \internal_op 7'0111011
end
end
process $group_4
assign \in1_sel 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \in1_sel 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \in1_sel 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \in1_sel 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \in1_sel 3'000
end
end
process $group_5
assign \in2_sel 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \in2_sel 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \in2_sel 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \in2_sel 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \in2_sel 4'0000
end
end
process $group_6
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \in3_sel 2'00
end
end
process $group_7
assign \out_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \out_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \out_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \out_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \out_sel 2'01
end
end
process $group_8
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \cr_in 3'011
end
end
process $group_9
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \cr_out 3'010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \cr_out 3'010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \cr_out 3'010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \cr_out 3'000
end
end
process $group_10
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \ldst_len 4'0000
end
sync init
end
process $group_11
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+ switch \opcode_switch
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00000
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00111
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00001
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00100
+ assign \upd 2'00
+ end
+ sync init
+ end
+ process $group_12
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \rc_sel 2'00
end
sync init
end
- process $group_12
+ process $group_13
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \cry_in 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \cry_in 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \cry_in 2'00
end
sync init
end
- process $group_13
+ process $group_14
assign \asmcode 8'00000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \asmcode 8'00011010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \asmcode 8'00011100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \asmcode 8'00011110
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
- assign \asmcode 8'10011000
+ assign \asmcode 8'10011001
end
sync init
end
- process $group_14
+ process $group_15
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \inv_a 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \inv_a 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \inv_a 1'0
end
sync init
end
- process $group_15
+ process $group_16
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \inv_out 1'0
end
sync init
end
- process $group_16
+ process $group_17
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \cry_out 1'0
end
sync init
end
- process $group_17
+ process $group_18
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \br 1'0
end
sync init
end
- process $group_18
+ process $group_19
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \sgn_ext 1'0
end
sync init
end
- process $group_19
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
- switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00000
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00111
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00001
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00100
- assign \upd 1'0
- end
- sync init
- end
process $group_20
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \rsrv 1'0
end
end
process $group_21
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \is_32b 1'0
end
end
process $group_22
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \sgn 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \sgn 1'0
end
end
process $group_23
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \lk 1'0
end
end
process $group_24
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \sgl_pipe 1'0
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "test_issuer.core.pdecode2.dec.dec31.dec_sub26"
module \dec_sub26
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:229"
wire width 32 input 0 \opcode_in
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_11100 "Z23"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
wire width 5 output 2 \form
- attribute \enum_base_type "InternalOp"
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
+ attribute \enum_value_1001010 "OP_MTMSR"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
wire width 7 output 3 \internal_op
attribute \enum_base_type "In1Sel"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "RC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
wire width 2 output 10 \rc_sel
attribute \enum_base_type "LdstLen"
attribute \enum_value_0000 "NONE"
attribute \enum_value_1000 "is8B"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
wire width 4 output 11 \ldst_len
+ attribute \enum_base_type "LDSTMode"
+ attribute \enum_value_00 "NONE"
+ attribute \enum_value_01 "update"
+ attribute \enum_value_10 "cix"
+ attribute \enum_value_11 "cx"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+ wire width 2 output 12 \upd
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
- wire width 2 output 12 \cry_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 13 \inv_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 14 \inv_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 15 \cry_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 16 \br
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 17 \sgn_ext
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 18 \upd
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
+ wire width 2 output 13 \cry_in
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 14 \inv_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 15 \inv_out
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 16 \cry_out
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 17 \br
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 18 \sgn_ext
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 output 19 \rsrv
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 output 20 \is_32b
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 output 21 \sgn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 output 22 \lk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 output 23 \sgl_pipe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
wire width 8 output 24 \asmcode
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:257"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:267"
wire width 5 \opcode_switch
process $group_0
assign \opcode_switch 5'00000
end
process $group_1
assign \function_unit 11'00000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \function_unit 11'00000010000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \function_unit 11'00000010000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10001
assign \function_unit 11'00000010000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \function_unit 11'00000010000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11101
assign \function_unit 11'00000000010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11100
assign \function_unit 11'00000000010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11110
assign \function_unit 11'00000000010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11011
+ assign \function_unit 11'00000001000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00011
assign \function_unit 11'00000010000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01111
assign \function_unit 11'00000010000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01011
assign \function_unit 11'00000010000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00101
assign \function_unit 11'00000010000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \function_unit 11'00000010000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \function_unit 11'00000001000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11001
assign \function_unit 11'00000001000
end
end
process $group_2
assign \form 5'00000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \form 5'01000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \form 5'01000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10001
assign \form 5'01000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \form 5'01000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11101
assign \form 5'01000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11100
assign \form 5'01000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11110
assign \form 5'01000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11011
+ assign \form 5'10000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00011
assign \form 5'01000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01111
assign \form 5'01000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01011
assign \form 5'01000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00101
assign \form 5'01000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \form 5'01000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \form 5'01000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11001
assign \form 5'10000
end
end
process $group_3
assign \internal_op 7'0000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \internal_op 7'0001110
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \internal_op 7'0001110
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10001
assign \internal_op 7'0001110
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \internal_op 7'0001110
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11101
assign \internal_op 7'0011111
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11100
assign \internal_op 7'0011111
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11110
assign \internal_op 7'0011111
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11011
+ assign \internal_op 7'0100000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00011
assign \internal_op 7'0110110
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01111
assign \internal_op 7'0110110
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01011
assign \internal_op 7'0110110
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00101
assign \internal_op 7'0110111
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \internal_op 7'0110111
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \internal_op 7'0111101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11001
assign \internal_op 7'0111101
end
end
process $group_4
assign \in1_sel 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \in1_sel 3'100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \in1_sel 3'100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10001
assign \in1_sel 3'100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \in1_sel 3'100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11101
assign \in1_sel 3'100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11100
assign \in1_sel 3'100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11110
assign \in1_sel 3'100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11011
+ assign \in1_sel 3'000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00011
assign \in1_sel 3'100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01111
assign \in1_sel 3'100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01011
assign \in1_sel 3'100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00101
assign \in1_sel 3'100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \in1_sel 3'100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \in1_sel 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11001
assign \in1_sel 3'000
end
end
process $group_5
assign \in2_sel 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \in2_sel 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \in2_sel 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10001
assign \in2_sel 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \in2_sel 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11101
assign \in2_sel 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11100
assign \in2_sel 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11110
assign \in2_sel 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11011
+ assign \in2_sel 4'1010
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00011
assign \in2_sel 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01111
assign \in2_sel 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01011
assign \in2_sel 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00101
assign \in2_sel 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \in2_sel 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \in2_sel 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11001
assign \in2_sel 4'1010
end
end
process $group_6
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10001
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11101
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11100
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11110
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11011
+ assign \in3_sel 2'01
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00011
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01111
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01011
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00101
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \in3_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11001
assign \in3_sel 2'01
end
end
process $group_7
assign \out_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \out_sel 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \out_sel 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10001
assign \out_sel 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \out_sel 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11101
assign \out_sel 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11100
assign \out_sel 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11110
assign \out_sel 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11011
+ assign \out_sel 2'10
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00011
assign \out_sel 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01111
assign \out_sel 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01011
assign \out_sel 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00101
assign \out_sel 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \out_sel 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \out_sel 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11001
assign \out_sel 2'10
end
end
process $group_8
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10001
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11101
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11100
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11110
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11011
+ assign \cr_in 3'000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00011
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01111
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01011
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00101
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11001
assign \cr_in 3'000
end
end
process $group_9
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \cr_out 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \cr_out 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10001
assign \cr_out 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \cr_out 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11101
assign \cr_out 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11100
assign \cr_out 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11110
assign \cr_out 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11011
+ assign \cr_out 3'001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00011
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01111
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01011
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00101
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \cr_out 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11001
assign \cr_out 3'001
end
end
process $group_10
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10001
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11101
assign \ldst_len 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11100
assign \ldst_len 4'0010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11110
assign \ldst_len 4'0100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11011
+ assign \ldst_len 4'0000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00011
assign \ldst_len 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01111
assign \ldst_len 4'1000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01011
assign \ldst_len 4'0100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00101
assign \ldst_len 4'1000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \ldst_len 4'0100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11001
assign \ldst_len 4'0000
end
sync init
end
process $group_11
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+ switch \opcode_switch
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00001
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00000
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'10001
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'10000
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11101
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11100
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11110
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11011
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00011
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01111
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01011
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00101
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00100
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11000
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11001
+ assign \upd 2'00
+ end
+ sync init
+ end
+ process $group_12
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \rc_sel 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \rc_sel 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10001
assign \rc_sel 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \rc_sel 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11101
assign \rc_sel 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11100
assign \rc_sel 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11110
assign \rc_sel 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11011
+ assign \rc_sel 2'10
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00011
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01111
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01011
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00101
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \rc_sel 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11001
assign \rc_sel 2'10
end
sync init
end
- process $group_12
+ process $group_13
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10001
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11101
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11100
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11110
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11011
+ assign \cry_in 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00011
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01111
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01011
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00101
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11001
assign \cry_in 2'00
end
sync init
end
- process $group_13
+ process $group_14
assign \asmcode 8'00000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \asmcode 8'00100001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \asmcode 8'00100010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10001
assign \asmcode 8'00100011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \asmcode 8'00100100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11101
assign \asmcode 8'01000100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11100
assign \asmcode 8'01000101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11110
assign \asmcode 8'01000110
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11011
+ assign \asmcode 8'01000111
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00011
- assign \asmcode 8'10001001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01111
assign \asmcode 8'10001010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01011
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01111
assign \asmcode 8'10001011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01011
assign \asmcode 8'10001100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00100
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00101
assign \asmcode 8'10001101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00100
+ assign \asmcode 8'10001110
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
- assign \asmcode 8'10011100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'11001
assign \asmcode 8'10011101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11001
+ assign \asmcode 8'10011110
end
sync init
end
- process $group_14
+ process $group_15
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10001
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11101
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11100
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11110
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11011
+ assign \inv_a 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00011
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01111
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01011
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00101
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11001
assign \inv_a 1'0
end
sync init
end
- process $group_15
+ process $group_16
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10001
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11101
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11100
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11110
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11011
+ assign \inv_out 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00011
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01111
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01011
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00101
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11001
assign \inv_out 1'0
end
sync init
end
- process $group_16
+ process $group_17
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10001
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11101
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11100
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11110
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11011
+ assign \cry_out 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00011
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01111
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01011
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00101
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \cry_out 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11001
assign \cry_out 1'1
end
sync init
end
- process $group_17
+ process $group_18
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10001
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11101
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11100
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11110
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11011
+ assign \br 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00011
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01111
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01011
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00101
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11001
assign \br 1'0
end
sync init
end
- process $group_18
+ process $group_19
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10001
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11101
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11100
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11110
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11011
+ assign \sgn_ext 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00011
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01111
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01011
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00101
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11001
assign \sgn_ext 1'0
end
sync init
end
- process $group_19
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
- switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00001
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00000
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'10001
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'10000
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'11101
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'11100
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'11110
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00011
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01111
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01011
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00101
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00100
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'11000
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'11001
- assign \upd 1'0
- end
- sync init
- end
process $group_20
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10001
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11101
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11100
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11110
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11011
+ assign \rsrv 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00011
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01111
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01011
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00101
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11001
assign \rsrv 1'0
end
end
process $group_21
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \is_32b 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10001
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \is_32b 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11101
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11100
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11110
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11011
+ assign \is_32b 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00011
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01111
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01011
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00101
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11001
assign \is_32b 1'0
end
end
process $group_22
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10001
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11101
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11100
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11110
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11011
+ assign \sgn 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00011
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01111
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01011
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00101
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \sgn 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11001
assign \sgn 1'1
end
end
process $group_23
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10001
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11101
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11100
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11110
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11011
+ assign \lk 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00011
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01111
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01011
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00101
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11001
assign \lk 1'0
end
end
process $group_24
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10001
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11101
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11100
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11110
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11011
+ assign \sgl_pipe 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00011
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01111
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01011
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00101
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11001
assign \sgl_pipe 1'0
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "test_issuer.core.pdecode2.dec.dec31.dec_sub19"
module \dec_sub19
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:229"
wire width 32 input 0 \opcode_in
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_11100 "Z23"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
wire width 5 output 2 \form
- attribute \enum_base_type "InternalOp"
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
+ attribute \enum_value_1001010 "OP_MTMSR"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
wire width 7 output 3 \internal_op
attribute \enum_base_type "In1Sel"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "RC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
wire width 2 output 10 \rc_sel
attribute \enum_base_type "LdstLen"
attribute \enum_value_0000 "NONE"
attribute \enum_value_1000 "is8B"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
wire width 4 output 11 \ldst_len
+ attribute \enum_base_type "LDSTMode"
+ attribute \enum_value_00 "NONE"
+ attribute \enum_value_01 "update"
+ attribute \enum_value_10 "cix"
+ attribute \enum_value_11 "cx"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+ wire width 2 output 12 \upd
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
- wire width 2 output 12 \cry_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 13 \inv_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 14 \inv_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 15 \cry_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 16 \br
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 17 \sgn_ext
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 18 \upd
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
+ wire width 2 output 13 \cry_in
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 14 \inv_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 15 \inv_out
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 16 \cry_out
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 17 \br
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 18 \sgn_ext
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 output 19 \rsrv
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 output 20 \is_32b
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 output 21 \sgn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 output 22 \lk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 output 23 \sgl_pipe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
wire width 8 output 24 \asmcode
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:257"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:267"
wire width 5 \opcode_switch
process $group_0
assign \opcode_switch 5'00000
end
process $group_1
assign \function_unit 11'00000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \function_unit 11'00001000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \function_unit 11'00010000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01010
assign \function_unit 11'10000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01110
assign \function_unit 11'10000000000
end
end
process $group_2
assign \form 5'00000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \form 5'01010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \form 5'01000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01010
assign \form 5'01010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01110
assign \form 5'01010
end
end
process $group_3
assign \internal_op 7'0000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \internal_op 7'0101101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \internal_op 7'1000111
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01010
assign \internal_op 7'0101110
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01110
assign \internal_op 7'0110001
end
end
process $group_4
assign \in1_sel 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \in1_sel 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \in1_sel 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01010
assign \in1_sel 3'011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01110
assign \in1_sel 3'100
end
end
process $group_5
assign \in2_sel 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \in2_sel 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \in2_sel 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01010
assign \in2_sel 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01110
assign \in2_sel 4'0000
end
end
process $group_6
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01010
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01110
assign \in3_sel 2'00
end
end
process $group_7
assign \out_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \out_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \out_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01010
assign \out_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01110
assign \out_sel 2'11
end
end
process $group_8
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \cr_in 3'110
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01010
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01110
assign \cr_in 3'000
end
end
process $group_9
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01010
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01110
assign \cr_out 3'000
end
end
process $group_10
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01010
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01110
assign \ldst_len 4'0000
end
sync init
end
process $group_11
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+ switch \opcode_switch
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00000
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00010
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01010
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01110
+ assign \upd 2'00
+ end
+ sync init
+ end
+ process $group_12
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01010
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01110
assign \rc_sel 2'00
end
sync init
end
- process $group_12
+ process $group_13
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01010
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01110
assign \cry_in 2'00
end
sync init
end
- process $group_13
+ process $group_14
assign \asmcode 8'00000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \asmcode 8'01101101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \asmcode 8'01101110
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01010
assign \asmcode 8'01101111
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01110
- assign \asmcode 8'01110110
+ assign \asmcode 8'01110111
end
sync init
end
- process $group_14
+ process $group_15
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01010
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01110
assign \inv_a 1'0
end
sync init
end
- process $group_15
+ process $group_16
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01010
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01110
assign \inv_out 1'0
end
sync init
end
- process $group_16
+ process $group_17
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01010
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01110
assign \cry_out 1'0
end
sync init
end
- process $group_17
+ process $group_18
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01010
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01110
assign \br 1'0
end
sync init
end
- process $group_18
+ process $group_19
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01010
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01110
assign \sgn_ext 1'0
end
sync init
end
- process $group_19
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
- switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00000
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00010
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01010
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01110
- assign \upd 1'0
- end
- sync init
- end
process $group_20
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01010
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01110
assign \rsrv 1'0
end
end
process $group_21
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01010
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01110
assign \is_32b 1'0
end
end
process $group_22
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01010
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01110
assign \sgn 1'0
end
end
process $group_23
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01010
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01110
assign \lk 1'0
end
end
process $group_24
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \sgl_pipe 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01010
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01110
assign \sgl_pipe 1'0
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "test_issuer.core.pdecode2.dec.dec31.dec_sub22"
module \dec_sub22
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:229"
wire width 32 input 0 \opcode_in
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_11100 "Z23"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
wire width 5 output 2 \form
- attribute \enum_base_type "InternalOp"
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
+ attribute \enum_value_1001010 "OP_MTMSR"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
wire width 7 output 3 \internal_op
attribute \enum_base_type "In1Sel"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "RC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
wire width 2 output 10 \rc_sel
attribute \enum_base_type "LdstLen"
attribute \enum_value_0000 "NONE"
attribute \enum_value_1000 "is8B"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
wire width 4 output 11 \ldst_len
+ attribute \enum_base_type "LDSTMode"
+ attribute \enum_value_00 "NONE"
+ attribute \enum_value_01 "update"
+ attribute \enum_value_10 "cix"
+ attribute \enum_value_11 "cx"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+ wire width 2 output 12 \upd
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
- wire width 2 output 12 \cry_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 13 \inv_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 14 \inv_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 15 \cry_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 16 \br
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 17 \sgn_ext
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 18 \upd
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
+ wire width 2 output 13 \cry_in
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 14 \inv_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 15 \inv_out
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 16 \cry_out
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 17 \br
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 18 \sgn_ext
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 output 19 \rsrv
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 output 20 \is_32b
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 output 21 \sgn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 output 22 \lk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 output 23 \sgl_pipe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
wire width 8 output 24 \asmcode
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:257"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:267"
wire width 5 \opcode_switch
process $group_0
assign \opcode_switch 5'00000
end
process $group_1
assign \function_unit 11'00000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \function_unit 11'00000000010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \function_unit 11'00000000010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \function_unit 11'00000000010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \function_unit 11'00000000010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11110
assign \function_unit 11'00000000010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \function_unit 11'00000000010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \function_unit 11'00000000100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \function_unit 11'00000000100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10101
assign \function_unit 11'00000000100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00110
assign \function_unit 11'00000000100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11100
assign \function_unit 11'00000000100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10110
assign \function_unit 11'00000000100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10100
assign \function_unit 11'00000000100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \function_unit 11'00000000100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10010
assign \function_unit 11'00000000010
end
end
process $group_2
assign \form 5'00000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \form 5'01000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \form 5'01000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \form 5'01000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \form 5'01000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11110
assign \form 5'01000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \form 5'01000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \form 5'01000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \form 5'01000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10101
assign \form 5'01000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00110
assign \form 5'01000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11100
assign \form 5'01000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10110
assign \form 5'01000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10100
assign \form 5'01000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \form 5'01000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10010
assign \form 5'01000
end
end
process $group_3
assign \internal_op 7'0000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \internal_op 7'0000001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \internal_op 7'0000001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \internal_op 7'0000001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \internal_op 7'0000001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11110
assign \internal_op 7'0100001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \internal_op 7'0000001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \internal_op 7'0100101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \internal_op 7'0100101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10101
assign \internal_op 7'0100110
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00110
assign \internal_op 7'0100110
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11100
assign \internal_op 7'0100110
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10110
assign \internal_op 7'0100110
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10100
assign \internal_op 7'0100110
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \internal_op 7'0100110
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10010
assign \internal_op 7'0000001
end
end
process $group_4
assign \in1_sel 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \in1_sel 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \in1_sel 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \in1_sel 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \in1_sel 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11110
assign \in1_sel 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \in1_sel 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \in1_sel 3'010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \in1_sel 3'010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10101
assign \in1_sel 3'010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00110
assign \in1_sel 3'010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11100
assign \in1_sel 3'010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10110
assign \in1_sel 3'010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10100
assign \in1_sel 3'010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \in1_sel 3'010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10010
assign \in1_sel 3'000
end
end
process $group_5
assign \in2_sel 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \in2_sel 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \in2_sel 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \in2_sel 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \in2_sel 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11110
assign \in2_sel 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \in2_sel 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \in2_sel 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \in2_sel 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10101
assign \in2_sel 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00110
assign \in2_sel 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11100
assign \in2_sel 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10110
assign \in2_sel 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10100
assign \in2_sel 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \in2_sel 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10010
assign \in2_sel 4'0000
end
end
process $group_6
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11110
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10101
assign \in3_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00110
assign \in3_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11100
assign \in3_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10110
assign \in3_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10100
assign \in3_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \in3_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10010
assign \in3_sel 2'00
end
end
process $group_7
assign \out_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \out_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \out_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \out_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \out_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11110
assign \out_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \out_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \out_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \out_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10101
assign \out_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00110
assign \out_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11100
assign \out_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10110
assign \out_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10100
assign \out_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \out_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10010
assign \out_sel 2'00
end
end
process $group_8
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11110
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10101
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00110
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11100
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10110
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10100
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10010
assign \cr_in 3'000
end
end
process $group_9
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11110
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10101
assign \cr_out 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00110
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11100
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10110
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10100
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10010
assign \cr_out 3'000
end
end
process $group_10
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11110
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \ldst_len 4'0010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \ldst_len 4'0100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10101
assign \ldst_len 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00110
assign \ldst_len 4'1000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11100
assign \ldst_len 4'0010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10110
assign \ldst_len 4'0010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10100
assign \ldst_len 4'0100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \ldst_len 4'0100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10010
assign \ldst_len 4'0000
end
sync init
end
process $group_11
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+ switch \opcode_switch
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00010
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00001
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01000
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00111
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11110
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00000
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11000
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'10000
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'10101
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00110
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11100
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'10110
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'10100
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00100
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'10010
+ assign \upd 2'00
+ end
+ sync init
+ end
+ process $group_12
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11110
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10101
assign \rc_sel 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00110
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11100
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10110
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10100
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10010
assign \rc_sel 2'00
end
sync init
end
- process $group_12
+ process $group_13
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11110
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10101
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00110
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11100
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10110
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10100
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10010
assign \cry_in 2'00
end
sync init
end
- process $group_13
+ process $group_14
assign \asmcode 8'00000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \asmcode 8'00101110
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \asmcode 8'00101111
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \asmcode 8'00110000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \asmcode 8'00110001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11110
assign \asmcode 8'01001000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \asmcode 8'01001001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \asmcode 8'01011100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \asmcode 8'01100101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10101
- assign \asmcode 8'10100011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ assign \asmcode 8'10100100
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00110
- assign \asmcode 8'10101001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ assign \asmcode 8'10101010
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11100
- assign \asmcode 8'10101110
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'10110
assign \asmcode 8'10101111
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'10110
+ assign \asmcode 8'10110000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10100
- assign \asmcode 8'10110100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00100
assign \asmcode 8'10110101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00100
+ assign \asmcode 8'10110110
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10010
- assign \asmcode 8'11000100
+ assign \asmcode 8'11000101
end
sync init
end
- process $group_14
+ process $group_15
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11110
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10101
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00110
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11100
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10110
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10100
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10010
assign \inv_a 1'0
end
sync init
end
- process $group_15
+ process $group_16
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11110
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10101
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00110
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11100
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10110
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10100
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10010
assign \inv_out 1'0
end
sync init
end
- process $group_16
+ process $group_17
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11110
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10101
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00110
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11100
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10110
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10100
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10010
assign \cry_out 1'0
end
sync init
end
- process $group_17
+ process $group_18
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11110
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \br 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \br 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10101
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00110
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11100
assign \br 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10110
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10100
assign \br 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10010
assign \br 1'0
end
sync init
end
- process $group_18
+ process $group_19
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11110
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10101
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00110
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11100
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10110
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10100
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10010
assign \sgn_ext 1'0
end
sync init
end
- process $group_19
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
- switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00010
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00001
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01000
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00111
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'11110
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00000
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'11000
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'10000
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'10101
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00110
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'11100
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'10110
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'10100
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00100
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'10010
- assign \upd 1'0
- end
- sync init
- end
process $group_20
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11110
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10101
assign \rsrv 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00110
assign \rsrv 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11100
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10110
assign \rsrv 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10100
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \rsrv 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10010
assign \rsrv 1'0
end
end
process $group_21
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11110
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10101
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00110
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11100
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10110
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10100
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10010
assign \is_32b 1'0
end
end
process $group_22
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11110
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10101
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00110
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11100
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10110
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10100
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10010
assign \sgn 1'0
end
end
process $group_23
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11110
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10101
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00110
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11100
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10110
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10100
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10010
assign \lk 1'0
end
end
process $group_24
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \sgl_pipe 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \sgl_pipe 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \sgl_pipe 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \sgl_pipe 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11110
assign \sgl_pipe 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \sgl_pipe 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \sgl_pipe 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \sgl_pipe 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10101
assign \sgl_pipe 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00110
assign \sgl_pipe 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11100
assign \sgl_pipe 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10110
assign \sgl_pipe 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10100
assign \sgl_pipe 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \sgl_pipe 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10010
assign \sgl_pipe 1'1
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "test_issuer.core.pdecode2.dec.dec31.dec_sub9"
module \dec_sub9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:229"
wire width 32 input 0 \opcode_in
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_11100 "Z23"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
wire width 5 output 2 \form
- attribute \enum_base_type "InternalOp"
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
+ attribute \enum_value_1001010 "OP_MTMSR"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
wire width 7 output 3 \internal_op
attribute \enum_base_type "In1Sel"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "RC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
wire width 2 output 10 \rc_sel
attribute \enum_base_type "LdstLen"
attribute \enum_value_0000 "NONE"
attribute \enum_value_1000 "is8B"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
wire width 4 output 11 \ldst_len
+ attribute \enum_base_type "LDSTMode"
+ attribute \enum_value_00 "NONE"
+ attribute \enum_value_01 "update"
+ attribute \enum_value_10 "cix"
+ attribute \enum_value_11 "cx"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+ wire width 2 output 12 \upd
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
- wire width 2 output 12 \cry_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 13 \inv_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 14 \inv_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 15 \cry_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 16 \br
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 17 \sgn_ext
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 18 \upd
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
+ wire width 2 output 13 \cry_in
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 14 \inv_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 15 \inv_out
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 16 \cry_out
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 17 \br
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 18 \sgn_ext
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 output 19 \rsrv
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 output 20 \is_32b
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 output 21 \sgn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 output 22 \lk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 output 23 \sgl_pipe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
wire width 8 output 24 \asmcode
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:257"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:267"
wire width 5 \opcode_switch
process $group_0
assign \opcode_switch 5'00000
end
process $group_1
assign \function_unit 11'00000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01100
assign \function_unit 11'01000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11100
assign \function_unit 11'01000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01101
assign \function_unit 11'01000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11101
assign \function_unit 11'01000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01110
assign \function_unit 11'01000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11110
assign \function_unit 11'01000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01111
assign \function_unit 11'01000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11111
assign \function_unit 11'01000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \function_unit 11'01000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \function_unit 11'01000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \function_unit 11'00100000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \function_unit 11'00100000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10010
assign \function_unit 11'00100000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \function_unit 11'00100000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \function_unit 11'00100000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10111
assign \function_unit 11'00100000000
end
end
process $group_2
assign \form 5'00000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01100
assign \form 5'10001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11100
assign \form 5'10001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01101
assign \form 5'10001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11101
assign \form 5'10001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01110
assign \form 5'10001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11110
assign \form 5'10001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01111
assign \form 5'10001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11111
assign \form 5'10001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \form 5'01000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \form 5'01000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \form 5'10001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \form 5'10001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10010
assign \form 5'10001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \form 5'10001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \form 5'10001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10111
assign \form 5'10001
end
end
process $group_3
assign \internal_op 7'0000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01100
assign \internal_op 7'0011110
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11100
assign \internal_op 7'0011110
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01101
assign \internal_op 7'0011110
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11101
assign \internal_op 7'0011110
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01110
assign \internal_op 7'0011101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11110
assign \internal_op 7'0011101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01111
assign \internal_op 7'0011101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11111
assign \internal_op 7'0011101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \internal_op 7'0101111
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \internal_op 7'0101111
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \internal_op 7'0110011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \internal_op 7'0110011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10010
assign \internal_op 7'0110011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \internal_op 7'0110011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \internal_op 7'0110010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10111
assign \internal_op 7'0110010
end
end
process $group_4
assign \in1_sel 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01100
assign \in1_sel 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11100
assign \in1_sel 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01101
assign \in1_sel 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11101
assign \in1_sel 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01110
assign \in1_sel 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11110
assign \in1_sel 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01111
assign \in1_sel 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11111
assign \in1_sel 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \in1_sel 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \in1_sel 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \in1_sel 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \in1_sel 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10010
assign \in1_sel 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \in1_sel 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \in1_sel 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10111
assign \in1_sel 3'001
end
end
process $group_5
assign \in2_sel 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01100
assign \in2_sel 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11100
assign \in2_sel 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01101
assign \in2_sel 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11101
assign \in2_sel 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01110
assign \in2_sel 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11110
assign \in2_sel 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01111
assign \in2_sel 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11111
assign \in2_sel 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \in2_sel 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \in2_sel 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \in2_sel 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \in2_sel 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10010
assign \in2_sel 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \in2_sel 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \in2_sel 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10111
assign \in2_sel 4'0001
end
end
process $group_6
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01100
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11100
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01101
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11101
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01110
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11110
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01111
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11111
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10010
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10111
assign \in3_sel 2'00
end
end
process $group_7
assign \out_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01100
assign \out_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11100
assign \out_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01101
assign \out_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11101
assign \out_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01110
assign \out_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11110
assign \out_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01111
assign \out_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11111
assign \out_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \out_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \out_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \out_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \out_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10010
assign \out_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \out_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \out_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10111
assign \out_sel 2'01
end
end
process $group_8
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01100
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11100
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01101
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11101
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01110
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11110
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01111
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11111
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10010
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10111
assign \cr_in 3'000
end
end
process $group_9
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01100
assign \cr_out 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11100
assign \cr_out 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01101
assign \cr_out 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11101
assign \cr_out 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01110
assign \cr_out 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11110
assign \cr_out 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01111
assign \cr_out 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11111
assign \cr_out 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \cr_out 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \cr_out 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10010
assign \cr_out 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \cr_out 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \cr_out 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10111
assign \cr_out 3'001
end
end
process $group_10
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01100
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11100
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01101
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11101
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01110
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11110
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01111
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11111
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10010
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10111
assign \ldst_len 4'0000
end
sync init
end
process $group_11
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+ switch \opcode_switch
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01100
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11100
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01101
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11101
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01110
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11110
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01111
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11111
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01000
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11000
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00010
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00000
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'10010
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'10000
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00111
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'10111
+ assign \upd 2'00
+ end
+ sync init
+ end
+ process $group_12
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01100
assign \rc_sel 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11100
assign \rc_sel 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01101
assign \rc_sel 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11101
assign \rc_sel 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01110
assign \rc_sel 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11110
assign \rc_sel 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01111
assign \rc_sel 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11111
assign \rc_sel 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \rc_sel 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \rc_sel 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10010
assign \rc_sel 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \rc_sel 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \rc_sel 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10111
assign \rc_sel 2'10
end
sync init
end
- process $group_12
+ process $group_13
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01100
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11100
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01101
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11101
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01110
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11110
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01111
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11111
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10010
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10111
assign \cry_in 2'00
end
sync init
end
- process $group_13
+ process $group_14
assign \asmcode 8'00000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01100
assign \asmcode 8'00110110
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11100
assign \asmcode 8'00110111
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01101
assign \asmcode 8'00110100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11101
assign \asmcode 8'00110101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01110
assign \asmcode 8'00111001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11110
assign \asmcode 8'00111010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01111
assign \asmcode 8'00110011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11111
assign \asmcode 8'00111000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \asmcode 8'01110010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \asmcode 8'01110000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
- assign \asmcode 8'01110111
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00000
assign \asmcode 8'01111000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00000
+ assign \asmcode 8'01111001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10010
- assign \asmcode 8'01110111
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'10000
assign \asmcode 8'01111000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'10000
+ assign \asmcode 8'01111001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
- assign \asmcode 8'01111011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'10111
assign \asmcode 8'01111100
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'10111
+ assign \asmcode 8'01111101
end
sync init
end
- process $group_14
+ process $group_15
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01100
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11100
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01101
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11101
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01110
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11110
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01111
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11111
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10010
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10111
assign \inv_a 1'0
end
sync init
end
- process $group_15
+ process $group_16
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01100
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11100
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01101
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11101
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01110
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11110
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01111
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11111
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10010
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10111
assign \inv_out 1'0
end
sync init
end
- process $group_16
+ process $group_17
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01100
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11100
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01101
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11101
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01110
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11110
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01111
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11111
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10010
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10111
assign \cry_out 1'0
end
sync init
end
- process $group_17
+ process $group_18
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01100
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11100
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01101
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11101
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01110
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11110
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01111
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11111
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10010
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10111
assign \br 1'0
end
sync init
end
- process $group_18
+ process $group_19
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01100
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11100
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01101
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11101
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01110
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11110
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01111
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11111
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10010
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10111
assign \sgn_ext 1'0
end
sync init
end
- process $group_19
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
- switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01100
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'11100
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01101
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'11101
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01110
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'11110
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01111
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'11111
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01000
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'11000
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00010
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00000
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'10010
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'10000
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00111
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'10111
- assign \upd 1'0
- end
- sync init
- end
process $group_20
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01100
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11100
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01101
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11101
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01110
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11110
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01111
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11111
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10010
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10111
assign \rsrv 1'0
end
end
process $group_21
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01100
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11100
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01101
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11101
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01110
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11110
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01111
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11111
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10010
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10111
assign \is_32b 1'0
end
end
process $group_22
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01100
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11100
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01101
assign \sgn 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11101
assign \sgn 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01110
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11110
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01111
assign \sgn 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11111
assign \sgn 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \sgn 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \sgn 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10010
assign \sgn 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \sgn 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10111
assign \sgn 1'1
end
end
process $group_23
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01100
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11100
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01101
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11101
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01110
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11110
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01111
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11111
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10010
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10111
assign \lk 1'0
end
end
process $group_24
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01100
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11100
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01101
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11101
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01110
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11110
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01111
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11111
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10010
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10111
assign \sgl_pipe 1'0
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "test_issuer.core.pdecode2.dec.dec31.dec_sub11"
module \dec_sub11
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:229"
wire width 32 input 0 \opcode_in
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_11100 "Z23"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
wire width 5 output 2 \form
- attribute \enum_base_type "InternalOp"
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
+ attribute \enum_value_1001010 "OP_MTMSR"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
wire width 7 output 3 \internal_op
attribute \enum_base_type "In1Sel"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "RC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
wire width 2 output 10 \rc_sel
attribute \enum_base_type "LdstLen"
attribute \enum_value_0000 "NONE"
attribute \enum_value_1000 "is8B"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
wire width 4 output 11 \ldst_len
+ attribute \enum_base_type "LDSTMode"
+ attribute \enum_value_00 "NONE"
+ attribute \enum_value_01 "update"
+ attribute \enum_value_10 "cix"
+ attribute \enum_value_11 "cx"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+ wire width 2 output 12 \upd
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
- wire width 2 output 12 \cry_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 13 \inv_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 14 \inv_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 15 \cry_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 16 \br
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 17 \sgn_ext
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 18 \upd
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
+ wire width 2 output 13 \cry_in
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 14 \inv_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 15 \inv_out
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 16 \cry_out
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 17 \br
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 18 \sgn_ext
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 output 19 \rsrv
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 output 20 \is_32b
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 output 21 \sgn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 output 22 \lk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 output 23 \sgl_pipe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
wire width 8 output 24 \asmcode
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:257"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:267"
wire width 5 \opcode_switch
process $group_0
assign \opcode_switch 5'00000
end
process $group_1
assign \function_unit 11'00000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01100
assign \function_unit 11'01000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11100
assign \function_unit 11'01000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01101
assign \function_unit 11'01000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11101
assign \function_unit 11'01000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01110
assign \function_unit 11'01000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11110
assign \function_unit 11'01000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01111
assign \function_unit 11'01000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11111
assign \function_unit 11'01000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \function_unit 11'01000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \function_unit 11'01000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \function_unit 11'00100000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \function_unit 11'00100000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10010
assign \function_unit 11'00100000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \function_unit 11'00100000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \function_unit 11'00100000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10111
assign \function_unit 11'00100000000
end
end
process $group_2
assign \form 5'00000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01100
assign \form 5'10001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11100
assign \form 5'10001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01101
assign \form 5'10001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11101
assign \form 5'10001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01110
assign \form 5'10001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11110
assign \form 5'10001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01111
assign \form 5'10001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11111
assign \form 5'10001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \form 5'01000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \form 5'01000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \form 5'10001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \form 5'10001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10010
assign \form 5'10001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \form 5'10001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \form 5'10001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10111
assign \form 5'10001
end
end
process $group_3
assign \internal_op 7'0000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01100
assign \internal_op 7'0011110
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11100
assign \internal_op 7'0011110
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01101
assign \internal_op 7'0011110
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11101
assign \internal_op 7'0011110
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01110
assign \internal_op 7'0011101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11110
assign \internal_op 7'0011101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01111
assign \internal_op 7'0011101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11111
assign \internal_op 7'0011101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \internal_op 7'0101111
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \internal_op 7'0101111
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \internal_op 7'0110100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \internal_op 7'0110100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10010
assign \internal_op 7'0110100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \internal_op 7'0110100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \internal_op 7'0110010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10111
assign \internal_op 7'0110010
end
end
process $group_4
assign \in1_sel 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01100
assign \in1_sel 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11100
assign \in1_sel 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01101
assign \in1_sel 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11101
assign \in1_sel 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01110
assign \in1_sel 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11110
assign \in1_sel 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01111
assign \in1_sel 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11111
assign \in1_sel 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \in1_sel 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \in1_sel 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \in1_sel 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \in1_sel 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10010
assign \in1_sel 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \in1_sel 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \in1_sel 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10111
assign \in1_sel 3'001
end
end
process $group_5
assign \in2_sel 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01100
assign \in2_sel 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11100
assign \in2_sel 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01101
assign \in2_sel 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11101
assign \in2_sel 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01110
assign \in2_sel 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11110
assign \in2_sel 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01111
assign \in2_sel 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11111
assign \in2_sel 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \in2_sel 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \in2_sel 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \in2_sel 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \in2_sel 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10010
assign \in2_sel 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \in2_sel 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \in2_sel 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10111
assign \in2_sel 4'0001
end
end
process $group_6
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01100
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11100
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01101
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11101
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01110
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11110
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01111
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11111
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10010
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10111
assign \in3_sel 2'00
end
end
process $group_7
assign \out_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01100
assign \out_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11100
assign \out_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01101
assign \out_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11101
assign \out_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01110
assign \out_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11110
assign \out_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01111
assign \out_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11111
assign \out_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \out_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \out_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \out_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \out_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10010
assign \out_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \out_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \out_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10111
assign \out_sel 2'01
end
end
process $group_8
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01100
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11100
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01101
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11101
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01110
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11110
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01111
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11111
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10010
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10111
assign \cr_in 3'000
end
end
process $group_9
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01100
assign \cr_out 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11100
assign \cr_out 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01101
assign \cr_out 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11101
assign \cr_out 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01110
assign \cr_out 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11110
assign \cr_out 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01111
assign \cr_out 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11111
assign \cr_out 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \cr_out 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \cr_out 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10010
assign \cr_out 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \cr_out 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \cr_out 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10111
assign \cr_out 3'001
end
end
process $group_10
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01100
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11100
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01101
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11101
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01110
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11110
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01111
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11111
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10010
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10111
assign \ldst_len 4'0000
end
sync init
end
process $group_11
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+ switch \opcode_switch
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01100
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11100
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01101
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11101
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01110
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11110
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01111
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11111
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01000
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11000
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00010
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00000
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'10010
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'10000
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00111
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'10111
+ assign \upd 2'00
+ end
+ sync init
+ end
+ process $group_12
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01100
assign \rc_sel 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11100
assign \rc_sel 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01101
assign \rc_sel 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11101
assign \rc_sel 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01110
assign \rc_sel 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11110
assign \rc_sel 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01111
assign \rc_sel 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11111
assign \rc_sel 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \rc_sel 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \rc_sel 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10010
assign \rc_sel 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \rc_sel 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \rc_sel 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10111
assign \rc_sel 2'10
end
sync init
end
- process $group_12
+ process $group_13
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01100
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11100
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01101
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11101
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01110
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11110
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01111
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11111
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10010
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10111
assign \cry_in 2'00
end
sync init
end
- process $group_13
+ process $group_14
assign \asmcode 8'00000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01100
assign \asmcode 8'00111110
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11100
assign \asmcode 8'00111111
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01101
assign \asmcode 8'00111100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11101
assign \asmcode 8'00111101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01110
assign \asmcode 8'01000001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11110
assign \asmcode 8'01000010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01111
assign \asmcode 8'00111011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11111
assign \asmcode 8'01000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \asmcode 8'01110011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \asmcode 8'01110001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
- assign \asmcode 8'01111001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00000
assign \asmcode 8'01111010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00000
+ assign \asmcode 8'01111011
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10010
- assign \asmcode 8'01111001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'10000
assign \asmcode 8'01111010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'10000
+ assign \asmcode 8'01111011
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
- assign \asmcode 8'01111110
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'10111
assign \asmcode 8'01111111
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'10111
+ assign \asmcode 8'10000000
end
sync init
end
- process $group_14
+ process $group_15
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01100
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11100
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01101
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11101
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01110
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11110
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01111
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11111
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10010
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10111
assign \inv_a 1'0
end
sync init
end
- process $group_15
+ process $group_16
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01100
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11100
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01101
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11101
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01110
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11110
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01111
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11111
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10010
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10111
assign \inv_out 1'0
end
sync init
end
- process $group_16
+ process $group_17
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01100
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11100
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01101
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11101
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01110
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11110
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01111
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11111
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10010
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10111
assign \cry_out 1'0
end
sync init
end
- process $group_17
+ process $group_18
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01100
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11100
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01101
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11101
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01110
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11110
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01111
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11111
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10010
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10111
assign \br 1'0
end
sync init
end
- process $group_18
+ process $group_19
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01100
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11100
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01101
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11101
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01110
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11110
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01111
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11111
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10010
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10111
assign \sgn_ext 1'0
end
sync init
end
- process $group_19
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
- switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01100
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'11100
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01101
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'11101
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01110
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'11110
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01111
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'11111
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01000
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'11000
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00010
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00000
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'10010
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'10000
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00111
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'10111
- assign \upd 1'0
- end
- sync init
- end
process $group_20
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01100
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11100
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01101
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11101
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01110
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11110
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01111
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11111
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10010
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10111
assign \rsrv 1'0
end
end
process $group_21
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01100
assign \is_32b 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11100
assign \is_32b 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01101
assign \is_32b 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11101
assign \is_32b 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01110
assign \is_32b 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11110
assign \is_32b 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01111
assign \is_32b 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11111
assign \is_32b 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \is_32b 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \is_32b 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \is_32b 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \is_32b 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10010
assign \is_32b 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \is_32b 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \is_32b 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10111
assign \is_32b 1'1
end
end
process $group_22
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01100
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11100
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01101
assign \sgn 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11101
assign \sgn 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01110
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11110
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01111
assign \sgn 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11111
assign \sgn 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \sgn 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \sgn 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10010
assign \sgn 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \sgn 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10111
assign \sgn 1'1
end
end
process $group_23
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01100
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11100
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01101
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11101
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01110
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11110
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01111
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11111
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10010
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10111
assign \lk 1'0
end
end
process $group_24
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01100
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11100
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01101
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11101
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01110
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11110
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01111
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11111
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10010
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10111
assign \sgl_pipe 1'0
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "test_issuer.core.pdecode2.dec.dec31.dec_sub27"
module \dec_sub27
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:229"
wire width 32 input 0 \opcode_in
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_11100 "Z23"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
wire width 5 output 2 \form
- attribute \enum_base_type "InternalOp"
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
+ attribute \enum_value_1001010 "OP_MTMSR"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
wire width 7 output 3 \internal_op
attribute \enum_base_type "In1Sel"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "RC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
wire width 2 output 10 \rc_sel
attribute \enum_base_type "LdstLen"
attribute \enum_value_0000 "NONE"
attribute \enum_value_1000 "is8B"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
wire width 4 output 11 \ldst_len
+ attribute \enum_base_type "LDSTMode"
+ attribute \enum_value_00 "NONE"
+ attribute \enum_value_01 "update"
+ attribute \enum_value_10 "cix"
+ attribute \enum_value_11 "cx"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+ wire width 2 output 12 \upd
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
- wire width 2 output 12 \cry_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 13 \inv_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 14 \inv_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 15 \cry_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 16 \br
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 17 \sgn_ext
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 18 \upd
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
+ wire width 2 output 13 \cry_in
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 14 \inv_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 15 \inv_out
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 16 \cry_out
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 17 \br
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 18 \sgn_ext
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 output 19 \rsrv
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 output 20 \is_32b
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 output 21 \sgn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 output 22 \lk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 output 23 \sgl_pipe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
wire width 8 output 24 \asmcode
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:257"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:267"
wire width 5 \opcode_switch
process $group_0
assign \opcode_switch 5'00000
end
process $group_1
assign \function_unit 11'00000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11011
+ assign \function_unit 11'00000001000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \function_unit 11'00000001000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11001
assign \function_unit 11'00000001000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \function_unit 11'00000001000
end
end
process $group_2
assign \form 5'00000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11011
+ assign \form 5'10000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \form 5'01000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11001
assign \form 5'10000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \form 5'01000
end
end
process $group_3
assign \internal_op 7'0000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11011
+ assign \internal_op 7'0100000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \internal_op 7'0111100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11001
assign \internal_op 7'0111101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \internal_op 7'0111101
end
end
process $group_4
assign \in1_sel 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11011
+ assign \in1_sel 3'000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \in1_sel 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11001
assign \in1_sel 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \in1_sel 3'000
end
end
process $group_5
assign \in2_sel 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11011
+ assign \in2_sel 4'1010
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \in2_sel 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11001
assign \in2_sel 4'1010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \in2_sel 4'0001
end
end
process $group_6
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11011
+ assign \in3_sel 2'01
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \in3_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11001
assign \in3_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \in3_sel 2'01
end
end
process $group_7
assign \out_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11011
+ assign \out_sel 2'10
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \out_sel 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11001
assign \out_sel 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \out_sel 2'10
end
end
process $group_8
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11011
+ assign \cr_in 3'000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11001
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \cr_in 3'000
end
end
process $group_9
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11011
+ assign \cr_out 3'001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \cr_out 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11001
assign \cr_out 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \cr_out 3'001
end
end
process $group_10
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11011
+ assign \ldst_len 4'0000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11001
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \ldst_len 4'0000
end
sync init
end
process $group_11
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+ switch \opcode_switch
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11011
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00000
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11001
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'10000
+ assign \upd 2'00
+ end
+ sync init
+ end
+ process $group_12
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11011
+ assign \rc_sel 2'10
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \rc_sel 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11001
assign \rc_sel 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \rc_sel 2'10
end
sync init
end
- process $group_12
+ process $group_13
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11011
+ assign \cry_in 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11001
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \cry_in 2'00
end
sync init
end
- process $group_13
+ process $group_14
assign \asmcode 8'00000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11011
+ assign \asmcode 8'01000111
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
- assign \asmcode 8'10011010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ assign \asmcode 8'10011011
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11001
- assign \asmcode 8'10011101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ assign \asmcode 8'10011110
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
- assign \asmcode 8'10100000
+ assign \asmcode 8'10100001
end
sync init
end
- process $group_14
+ process $group_15
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11011
+ assign \inv_a 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11001
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \inv_a 1'0
end
sync init
end
- process $group_15
+ process $group_16
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11011
+ assign \inv_out 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11001
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \inv_out 1'0
end
sync init
end
- process $group_16
+ process $group_17
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11011
+ assign \cry_out 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11001
assign \cry_out 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \cry_out 1'0
end
sync init
end
- process $group_17
+ process $group_18
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11011
+ assign \br 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11001
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \br 1'0
end
sync init
end
- process $group_18
+ process $group_19
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11011
+ assign \sgn_ext 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11001
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \sgn_ext 1'0
end
sync init
end
- process $group_19
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
- switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00000
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'11001
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'10000
- assign \upd 1'0
- end
- sync init
- end
process $group_20
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11011
+ assign \rsrv 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11001
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \rsrv 1'0
end
end
process $group_21
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11011
+ assign \is_32b 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11001
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \is_32b 1'0
end
end
process $group_22
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11011
+ assign \sgn 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11001
assign \sgn 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \sgn 1'0
end
end
process $group_23
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11011
+ assign \lk 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11001
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \lk 1'0
end
end
process $group_24
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11011
+ assign \sgl_pipe 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11001
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \sgl_pipe 1'0
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "test_issuer.core.pdecode2.dec.dec31.dec_sub15"
module \dec_sub15
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:229"
wire width 32 input 0 \opcode_in
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_11100 "Z23"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
wire width 5 output 2 \form
- attribute \enum_base_type "InternalOp"
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
+ attribute \enum_value_1001010 "OP_MTMSR"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
wire width 7 output 3 \internal_op
attribute \enum_base_type "In1Sel"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "RC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
wire width 2 output 10 \rc_sel
attribute \enum_base_type "LdstLen"
attribute \enum_value_0000 "NONE"
attribute \enum_value_1000 "is8B"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
wire width 4 output 11 \ldst_len
+ attribute \enum_base_type "LDSTMode"
+ attribute \enum_value_00 "NONE"
+ attribute \enum_value_01 "update"
+ attribute \enum_value_10 "cix"
+ attribute \enum_value_11 "cx"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+ wire width 2 output 12 \upd
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
- wire width 2 output 12 \cry_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 13 \inv_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 14 \inv_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 15 \cry_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 16 \br
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 17 \sgn_ext
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 18 \upd
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
+ wire width 2 output 13 \cry_in
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 14 \inv_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 15 \inv_out
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 16 \cry_out
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 17 \br
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 18 \sgn_ext
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 output 19 \rsrv
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 output 20 \is_32b
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 output 21 \sgn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 output 22 \lk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 output 23 \sgl_pipe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
wire width 8 output 24 \asmcode
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:257"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:267"
wire width 5 \opcode_switch
process $group_0
assign \opcode_switch 5'00000
end
process $group_1
assign \function_unit 11'00000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \function_unit 11'00001000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \function_unit 11'00001000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \function_unit 11'00001000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00011
assign \function_unit 11'00001000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \function_unit 11'00001000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00101
assign \function_unit 11'00001000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00110
assign \function_unit 11'00001000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \function_unit 11'00001000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \function_unit 11'00001000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01001
assign \function_unit 11'00001000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01010
assign \function_unit 11'00001000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01011
assign \function_unit 11'00001000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01100
assign \function_unit 11'00001000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01101
assign \function_unit 11'00001000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01110
assign \function_unit 11'00001000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01111
assign \function_unit 11'00001000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \function_unit 11'00001000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10001
assign \function_unit 11'00001000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10010
assign \function_unit 11'00001000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10011
assign \function_unit 11'00001000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10100
assign \function_unit 11'00001000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10101
assign \function_unit 11'00001000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10110
assign \function_unit 11'00001000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10111
assign \function_unit 11'00001000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \function_unit 11'00001000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11001
assign \function_unit 11'00001000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11010
assign \function_unit 11'00001000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11011
assign \function_unit 11'00001000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11100
assign \function_unit 11'00001000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11101
assign \function_unit 11'00001000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11110
assign \function_unit 11'00001000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11111
assign \function_unit 11'00001000000
end
end
process $group_2
assign \form 5'00000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \form 5'10010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \form 5'10010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \form 5'10010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00011
assign \form 5'10010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \form 5'10010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00101
assign \form 5'10010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00110
assign \form 5'10010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \form 5'10010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \form 5'10010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01001
assign \form 5'10010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01010
assign \form 5'10010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01011
assign \form 5'10010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01100
assign \form 5'10010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01101
assign \form 5'10010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01110
assign \form 5'10010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01111
assign \form 5'10010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \form 5'10010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10001
assign \form 5'10010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10010
assign \form 5'10010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10011
assign \form 5'10010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10100
assign \form 5'10010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10101
assign \form 5'10010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10110
assign \form 5'10010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10111
assign \form 5'10010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \form 5'10010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11001
assign \form 5'10010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11010
assign \form 5'10010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11011
assign \form 5'10010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11100
assign \form 5'10010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11101
assign \form 5'10010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11110
assign \form 5'10010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11111
assign \form 5'10010
end
end
process $group_3
assign \internal_op 7'0000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \internal_op 7'0100011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \internal_op 7'0100011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \internal_op 7'0100011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00011
assign \internal_op 7'0100011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \internal_op 7'0100011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00101
assign \internal_op 7'0100011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00110
assign \internal_op 7'0100011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \internal_op 7'0100011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \internal_op 7'0100011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01001
assign \internal_op 7'0100011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01010
assign \internal_op 7'0100011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01011
assign \internal_op 7'0100011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01100
assign \internal_op 7'0100011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01101
assign \internal_op 7'0100011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01110
assign \internal_op 7'0100011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01111
assign \internal_op 7'0100011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \internal_op 7'0100011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10001
assign \internal_op 7'0100011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10010
assign \internal_op 7'0100011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10011
assign \internal_op 7'0100011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10100
assign \internal_op 7'0100011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10101
assign \internal_op 7'0100011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10110
assign \internal_op 7'0100011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10111
assign \internal_op 7'0100011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \internal_op 7'0100011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11001
assign \internal_op 7'0100011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11010
assign \internal_op 7'0100011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11011
assign \internal_op 7'0100011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11100
assign \internal_op 7'0100011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11101
assign \internal_op 7'0100011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11110
assign \internal_op 7'0100011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11111
assign \internal_op 7'0100011
end
end
process $group_4
assign \in1_sel 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \in1_sel 3'010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \in1_sel 3'010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \in1_sel 3'010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00011
assign \in1_sel 3'010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \in1_sel 3'010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00101
assign \in1_sel 3'010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00110
assign \in1_sel 3'010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \in1_sel 3'010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \in1_sel 3'010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01001
assign \in1_sel 3'010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01010
assign \in1_sel 3'010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01011
assign \in1_sel 3'010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01100
assign \in1_sel 3'010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01101
assign \in1_sel 3'010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01110
assign \in1_sel 3'010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01111
assign \in1_sel 3'010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \in1_sel 3'010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10001
assign \in1_sel 3'010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10010
assign \in1_sel 3'010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10011
assign \in1_sel 3'010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10100
assign \in1_sel 3'010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10101
assign \in1_sel 3'010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10110
assign \in1_sel 3'010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10111
assign \in1_sel 3'010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \in1_sel 3'010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11001
assign \in1_sel 3'010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11010
assign \in1_sel 3'010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11011
assign \in1_sel 3'010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11100
assign \in1_sel 3'010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11101
assign \in1_sel 3'010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11110
assign \in1_sel 3'010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11111
assign \in1_sel 3'010
end
end
process $group_5
assign \in2_sel 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \in2_sel 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \in2_sel 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \in2_sel 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00011
assign \in2_sel 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \in2_sel 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00101
assign \in2_sel 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00110
assign \in2_sel 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \in2_sel 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \in2_sel 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01001
assign \in2_sel 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01010
assign \in2_sel 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01011
assign \in2_sel 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01100
assign \in2_sel 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01101
assign \in2_sel 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01110
assign \in2_sel 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01111
assign \in2_sel 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \in2_sel 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10001
assign \in2_sel 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10010
assign \in2_sel 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10011
assign \in2_sel 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10100
assign \in2_sel 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10101
assign \in2_sel 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10110
assign \in2_sel 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10111
assign \in2_sel 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \in2_sel 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11001
assign \in2_sel 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11010
assign \in2_sel 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11011
assign \in2_sel 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11100
assign \in2_sel 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11101
assign \in2_sel 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11110
assign \in2_sel 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11111
assign \in2_sel 4'0001
end
end
process $group_6
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00011
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00101
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00110
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01001
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01010
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01011
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01100
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01101
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01110
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01111
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10001
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10010
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10011
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10100
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10101
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10110
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10111
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11001
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11010
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11011
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11100
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11101
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11110
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11111
assign \in3_sel 2'00
end
end
process $group_7
assign \out_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \out_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \out_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \out_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00011
assign \out_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \out_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00101
assign \out_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00110
assign \out_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \out_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \out_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01001
assign \out_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01010
assign \out_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01011
assign \out_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01100
assign \out_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01101
assign \out_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01110
assign \out_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01111
assign \out_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \out_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10001
assign \out_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10010
assign \out_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10011
assign \out_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10100
assign \out_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10101
assign \out_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10110
assign \out_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10111
assign \out_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \out_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11001
assign \out_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11010
assign \out_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11011
assign \out_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11100
assign \out_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11101
assign \out_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11110
assign \out_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11111
assign \out_sel 2'01
end
end
process $group_8
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \cr_in 3'101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \cr_in 3'101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \cr_in 3'101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00011
assign \cr_in 3'101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \cr_in 3'101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00101
assign \cr_in 3'101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00110
assign \cr_in 3'101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \cr_in 3'101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \cr_in 3'101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01001
assign \cr_in 3'101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01010
assign \cr_in 3'101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01011
assign \cr_in 3'101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01100
assign \cr_in 3'101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01101
assign \cr_in 3'101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01110
assign \cr_in 3'101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01111
assign \cr_in 3'101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \cr_in 3'101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10001
assign \cr_in 3'101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10010
assign \cr_in 3'101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10011
assign \cr_in 3'101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10100
assign \cr_in 3'101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10101
assign \cr_in 3'101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10110
assign \cr_in 3'101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10111
assign \cr_in 3'101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \cr_in 3'101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11001
assign \cr_in 3'101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11010
assign \cr_in 3'101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11011
assign \cr_in 3'101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11100
assign \cr_in 3'101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11101
assign \cr_in 3'101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11110
assign \cr_in 3'101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11111
assign \cr_in 3'101
end
end
process $group_9
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00011
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00101
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00110
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01001
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01010
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01011
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01100
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01101
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01110
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01111
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10001
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10010
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10011
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10100
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10101
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10110
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10111
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11001
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11010
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11011
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11100
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11101
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11110
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11111
assign \cr_out 3'000
end
end
process $group_10
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00011
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00101
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00110
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01001
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01010
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01011
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01100
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01101
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01110
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01111
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10001
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10010
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10011
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10100
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10101
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10110
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10111
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11001
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11010
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11011
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11100
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11101
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11110
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11111
assign \ldst_len 4'0000
end
sync init
end
process $group_11
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+ switch \opcode_switch
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00000
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00001
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00010
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00011
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00100
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00101
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00110
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00111
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01000
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01001
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01010
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01011
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01100
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01101
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01110
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01111
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'10000
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'10001
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'10010
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'10011
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'10100
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'10101
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'10110
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'10111
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11000
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11001
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11010
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11011
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11100
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11101
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11110
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11111
+ assign \upd 2'00
+ end
+ sync init
+ end
+ process $group_12
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00011
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00101
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00110
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01001
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01010
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01011
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01100
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01101
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01110
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01111
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10001
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10010
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10011
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10100
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10101
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10110
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10111
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11001
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11010
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11011
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11100
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11101
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11110
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11111
assign \rc_sel 2'00
end
sync init
end
- process $group_12
+ process $group_13
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00011
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00101
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00110
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01001
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01010
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01011
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01100
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01101
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01110
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01111
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10001
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10010
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10011
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10100
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10101
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10110
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10111
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11001
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11010
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11011
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11100
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11101
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11110
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11111
assign \cry_in 2'00
end
sync init
end
- process $group_13
+ process $group_14
assign \asmcode 8'00000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \asmcode 8'01001010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \asmcode 8'01001010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \asmcode 8'01001010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00011
assign \asmcode 8'01001010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \asmcode 8'01001010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00101
assign \asmcode 8'01001010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00110
assign \asmcode 8'01001010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \asmcode 8'01001010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \asmcode 8'01001010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01001
assign \asmcode 8'01001010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01010
assign \asmcode 8'01001010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01011
assign \asmcode 8'01001010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01100
assign \asmcode 8'01001010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01101
assign \asmcode 8'01001010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01110
assign \asmcode 8'01001010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01111
assign \asmcode 8'01001010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \asmcode 8'01001010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10001
assign \asmcode 8'01001010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10010
assign \asmcode 8'01001010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10011
assign \asmcode 8'01001010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10100
assign \asmcode 8'01001010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10101
assign \asmcode 8'01001010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10110
assign \asmcode 8'01001010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10111
assign \asmcode 8'01001010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \asmcode 8'01001010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11001
assign \asmcode 8'01001010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11010
assign \asmcode 8'01001010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11011
assign \asmcode 8'01001010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11100
assign \asmcode 8'01001010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11101
assign \asmcode 8'01001010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11110
assign \asmcode 8'01001010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11111
assign \asmcode 8'01001010
end
sync init
end
- process $group_14
+ process $group_15
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00011
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00101
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00110
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01001
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01010
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01011
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01100
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01101
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01110
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01111
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10001
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10010
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10011
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10100
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10101
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10110
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10111
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11001
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11010
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11011
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11100
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11101
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11110
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11111
assign \inv_a 1'0
end
sync init
end
- process $group_15
+ process $group_16
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00011
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00101
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00110
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01001
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01010
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01011
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01100
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01101
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01110
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01111
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10001
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10010
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10011
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10100
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10101
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10110
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10111
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11001
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11010
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11011
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11100
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11101
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11110
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11111
assign \inv_out 1'0
end
sync init
end
- process $group_16
+ process $group_17
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00011
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00101
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00110
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01001
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01010
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01011
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01100
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01101
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01110
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01111
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10001
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10010
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10011
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10100
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10101
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10110
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10111
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11001
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11010
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11011
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11100
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11101
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11110
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11111
assign \cry_out 1'0
end
sync init
end
- process $group_17
+ process $group_18
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00011
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00101
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00110
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01001
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01010
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01011
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01100
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01101
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01110
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01111
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10001
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10010
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10011
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10100
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10101
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10110
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10111
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11001
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11010
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11011
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11100
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11101
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11110
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11111
assign \br 1'0
end
sync init
end
- process $group_18
+ process $group_19
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00011
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00101
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00110
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01001
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01010
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01011
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01100
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01101
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01110
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01111
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10001
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10010
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10011
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10100
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10101
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10110
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10111
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11001
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11010
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11011
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11100
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11101
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11110
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11111
assign \sgn_ext 1'0
end
sync init
end
- process $group_19
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
- switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00000
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00001
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00010
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00011
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00100
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00101
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00110
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00111
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01000
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01001
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01010
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01011
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01100
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01101
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01110
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01111
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'10000
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'10001
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'10010
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'10011
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'10100
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'10101
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'10110
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'10111
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'11000
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'11001
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'11010
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'11011
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'11100
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'11101
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'11110
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'11111
- assign \upd 1'0
- end
- sync init
- end
process $group_20
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00011
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00101
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00110
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01001
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01010
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01011
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01100
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01101
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01110
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01111
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10001
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10010
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10011
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10100
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10101
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10110
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10111
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11001
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11010
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11011
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11100
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11101
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11110
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11111
assign \rsrv 1'0
end
end
process $group_21
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00011
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00101
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00110
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01001
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01010
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01011
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01100
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01101
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01110
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01111
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10001
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10010
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10011
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10100
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10101
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10110
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10111
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11001
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11010
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11011
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11100
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11101
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11110
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11111
assign \is_32b 1'0
end
end
process $group_22
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00011
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00101
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00110
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01001
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01010
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01011
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01100
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01101
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01110
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01111
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10001
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10010
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10011
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10100
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10101
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10110
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10111
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11001
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11010
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11011
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11100
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11101
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11110
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11111
assign \sgn 1'0
end
end
process $group_23
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00011
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00101
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00110
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01001
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01010
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01011
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01100
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01101
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01110
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01111
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10001
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10010
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10011
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10100
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10101
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10110
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10111
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11001
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11010
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11011
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11100
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11101
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11110
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11111
assign \lk 1'0
end
end
process $group_24
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \sgl_pipe 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \sgl_pipe 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \sgl_pipe 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00011
assign \sgl_pipe 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \sgl_pipe 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00101
assign \sgl_pipe 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00110
assign \sgl_pipe 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \sgl_pipe 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01000
assign \sgl_pipe 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01001
assign \sgl_pipe 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01010
assign \sgl_pipe 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01011
assign \sgl_pipe 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01100
assign \sgl_pipe 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01101
assign \sgl_pipe 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01110
assign \sgl_pipe 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01111
assign \sgl_pipe 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \sgl_pipe 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10001
assign \sgl_pipe 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10010
assign \sgl_pipe 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10011
assign \sgl_pipe 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10100
assign \sgl_pipe 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10101
assign \sgl_pipe 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10110
assign \sgl_pipe 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10111
assign \sgl_pipe 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \sgl_pipe 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11001
assign \sgl_pipe 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11010
assign \sgl_pipe 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11011
assign \sgl_pipe 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11100
assign \sgl_pipe 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11101
assign \sgl_pipe 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11110
assign \sgl_pipe 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11111
assign \sgl_pipe 1'1
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "test_issuer.core.pdecode2.dec.dec31.dec_sub20"
module \dec_sub20
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:229"
wire width 32 input 0 \opcode_in
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_11100 "Z23"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
wire width 5 output 2 \form
- attribute \enum_base_type "InternalOp"
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
+ attribute \enum_value_1001010 "OP_MTMSR"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
wire width 7 output 3 \internal_op
attribute \enum_base_type "In1Sel"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "RC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
wire width 2 output 10 \rc_sel
attribute \enum_base_type "LdstLen"
attribute \enum_value_0000 "NONE"
attribute \enum_value_1000 "is8B"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
wire width 4 output 11 \ldst_len
+ attribute \enum_base_type "LDSTMode"
+ attribute \enum_value_00 "NONE"
+ attribute \enum_value_01 "update"
+ attribute \enum_value_10 "cix"
+ attribute \enum_value_11 "cx"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+ wire width 2 output 12 \upd
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
- wire width 2 output 12 \cry_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 13 \inv_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 14 \inv_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 15 \cry_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 16 \br
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 17 \sgn_ext
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 18 \upd
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
+ wire width 2 output 13 \cry_in
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 14 \inv_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 15 \inv_out
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 16 \cry_out
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 17 \br
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 18 \sgn_ext
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 output 19 \rsrv
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 output 20 \is_32b
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 output 21 \sgn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 output 22 \lk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 output 23 \sgl_pipe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
wire width 8 output 24 \asmcode
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:257"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:267"
wire width 5 \opcode_switch
process $group_0
assign \opcode_switch 5'00000
end
process $group_1
assign \function_unit 11'00000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \function_unit 11'00000000100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \function_unit 11'00000000100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \function_unit 11'00000000100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00011
assign \function_unit 11'00000000100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \function_unit 11'00000000100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10100
assign \function_unit 11'00000000100
end
end
process $group_2
assign \form 5'00000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \form 5'01000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \form 5'01000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \form 5'01000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00011
assign \form 5'01000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \form 5'01000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10100
assign \form 5'01000
end
end
process $group_3
assign \internal_op 7'0000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \internal_op 7'0100101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \internal_op 7'0100101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \internal_op 7'0100101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00011
assign \internal_op 7'0100101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \internal_op 7'0100101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10100
assign \internal_op 7'0100110
end
end
process $group_4
assign \in1_sel 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \in1_sel 3'010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \in1_sel 3'010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \in1_sel 3'010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00011
assign \in1_sel 3'010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \in1_sel 3'010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10100
assign \in1_sel 3'010
end
end
process $group_5
assign \in2_sel 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \in2_sel 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \in2_sel 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \in2_sel 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00011
assign \in2_sel 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \in2_sel 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10100
assign \in2_sel 4'0001
end
end
process $group_6
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00011
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10100
assign \in3_sel 2'01
end
end
process $group_7
assign \out_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \out_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \out_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \out_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00011
assign \out_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \out_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10100
assign \out_sel 2'00
end
end
process $group_8
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00011
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10100
assign \cr_in 3'000
end
end
process $group_9
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00011
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10100
assign \cr_out 3'000
end
end
process $group_10
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \ldst_len 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \ldst_len 4'1000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \ldst_len 4'1000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00011
assign \ldst_len 4'0010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \ldst_len 4'0100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10100
assign \ldst_len 4'1000
end
sync init
end
process $group_11
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+ switch \opcode_switch
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00001
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00010
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'10000
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00011
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00000
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'10100
+ assign \upd 2'00
+ end
+ sync init
+ end
+ process $group_12
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00011
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10100
assign \rc_sel 2'00
end
sync init
end
- process $group_12
+ process $group_13
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00011
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10100
assign \cry_in 2'00
end
sync init
end
- process $group_13
+ process $group_14
assign \asmcode 8'00000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \asmcode 8'01001100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \asmcode 8'01010010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \asmcode 8'01010011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00011
assign \asmcode 8'01011000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \asmcode 8'01100010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10100
- assign \asmcode 8'10101000
+ assign \asmcode 8'10101001
end
sync init
end
- process $group_14
+ process $group_15
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00011
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10100
assign \inv_a 1'0
end
sync init
end
- process $group_15
+ process $group_16
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00011
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10100
assign \inv_out 1'0
end
sync init
end
- process $group_16
+ process $group_17
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00011
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10100
assign \cry_out 1'0
end
sync init
end
- process $group_17
+ process $group_18
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \br 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00011
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10100
assign \br 1'1
end
sync init
end
- process $group_18
+ process $group_19
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00011
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10100
assign \sgn_ext 1'0
end
sync init
end
- process $group_19
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
- switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00001
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00010
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'10000
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00011
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00000
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'10100
- assign \upd 1'0
- end
- sync init
- end
process $group_20
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \rsrv 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \rsrv 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00011
assign \rsrv 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \rsrv 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10100
assign \rsrv 1'0
end
end
process $group_21
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00011
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10100
assign \is_32b 1'0
end
end
process $group_22
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00011
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10100
assign \sgn 1'0
end
end
process $group_23
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00011
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10100
assign \lk 1'0
end
end
process $group_24
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \sgl_pipe 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \sgl_pipe 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \sgl_pipe 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00011
assign \sgl_pipe 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \sgl_pipe 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10100
assign \sgl_pipe 1'1
end
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.pdecode2.dec.dec31.dec_sub23"
-module \dec_sub23
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219"
+attribute \nmigen.hierarchy "test_issuer.core.pdecode2.dec.dec31.dec_sub21"
+module \dec_sub21
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:229"
wire width 32 input 0 \opcode_in
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_11100 "Z23"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
wire width 5 output 2 \form
- attribute \enum_base_type "InternalOp"
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
+ attribute \enum_value_1001010 "OP_MTMSR"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
wire width 7 output 3 \internal_op
attribute \enum_base_type "In1Sel"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "RC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
wire width 2 output 10 \rc_sel
attribute \enum_base_type "LdstLen"
attribute \enum_value_0000 "NONE"
attribute \enum_value_1000 "is8B"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
wire width 4 output 11 \ldst_len
+ attribute \enum_base_type "LDSTMode"
+ attribute \enum_value_00 "NONE"
+ attribute \enum_value_01 "update"
+ attribute \enum_value_10 "cix"
+ attribute \enum_value_11 "cx"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+ wire width 2 output 12 \upd
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
- wire width 2 output 12 \cry_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 13 \inv_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 14 \inv_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 15 \cry_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 16 \br
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 17 \sgn_ext
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 18 \upd
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
+ wire width 2 output 13 \cry_in
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 14 \inv_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 15 \inv_out
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 16 \cry_out
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 17 \br
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 18 \sgn_ext
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 output 19 \rsrv
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 output 20 \is_32b
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 output 21 \sgn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 output 22 \lk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 output 23 \sgl_pipe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
wire width 8 output 24 \asmcode
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:257"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:267"
wire width 5 \opcode_switch
process $group_0
assign \opcode_switch 5'00000
end
process $group_1
assign \function_unit 11'00000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00011
- assign \function_unit 11'00000000100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00010
- assign \function_unit 11'00000000100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01011
- assign \function_unit 11'00000000100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01010
- assign \function_unit 11'00000000100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11010
assign \function_unit 11'00000000100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11011
assign \function_unit 11'00000000100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \function_unit 11'00000000100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \function_unit 11'00000000100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00111
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11001
assign \function_unit 11'00000000100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00110
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01011
assign \function_unit 11'00000000100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01010
assign \function_unit 11'00000000100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01100
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11110
+ assign \function_unit 11'00000000100
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11111
assign \function_unit 11'00000000100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00101
assign \function_unit 11'00000000100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \function_unit 11'00000000100
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11101
+ assign \function_unit 11'00000000100
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11100
+ assign \function_unit 11'00000000100
end
sync init
end
process $group_2
assign \form 5'00000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00011
- assign \form 5'01000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00010
- assign \form 5'01000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01011
- assign \form 5'01000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01010
- assign \form 5'01000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11010
assign \form 5'01000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11011
assign \form 5'01000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \form 5'01000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \form 5'01000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00111
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11001
assign \form 5'01000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00110
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01011
assign \form 5'01000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01010
assign \form 5'01000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01100
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11110
+ assign \form 5'01000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11111
assign \form 5'01000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00101
assign \form 5'01000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \form 5'01000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11101
+ assign \form 5'01000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11100
+ assign \form 5'01000
end
sync init
end
process $group_3
assign \internal_op 7'0000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00011
- assign \internal_op 7'0100101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00010
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11010
assign \internal_op 7'0100101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01011
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11011
assign \internal_op 7'0100101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01010
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00001
assign \internal_op 7'0100101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00000
assign \internal_op 7'0100101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11001
assign \internal_op 7'0100101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01011
assign \internal_op 7'0100101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01010
assign \internal_op 7'0100101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00111
- assign \internal_op 7'0100110
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00110
- assign \internal_op 7'0100110
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11110
assign \internal_op 7'0100110
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01100
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11111
assign \internal_op 7'0100110
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00101
assign \internal_op 7'0100110
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \internal_op 7'0100110
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11101
+ assign \internal_op 7'0100110
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11100
+ assign \internal_op 7'0100110
end
sync init
end
process $group_4
assign \in1_sel 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00011
- assign \in1_sel 3'010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00010
- assign \in1_sel 3'010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01011
- assign \in1_sel 3'010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01010
- assign \in1_sel 3'010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11010
assign \in1_sel 3'010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11011
assign \in1_sel 3'010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \in1_sel 3'010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \in1_sel 3'010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00111
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11001
assign \in1_sel 3'010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00110
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01011
assign \in1_sel 3'010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01010
assign \in1_sel 3'010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01100
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11110
+ assign \in1_sel 3'010
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11111
assign \in1_sel 3'010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00101
assign \in1_sel 3'010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \in1_sel 3'010
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11101
+ assign \in1_sel 3'010
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11100
+ assign \in1_sel 3'010
end
sync init
end
process $group_5
assign \in2_sel 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00011
- assign \in2_sel 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00010
- assign \in2_sel 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01011
- assign \in2_sel 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01010
- assign \in2_sel 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11010
assign \in2_sel 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11011
assign \in2_sel 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \in2_sel 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \in2_sel 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00111
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11001
assign \in2_sel 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00110
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01011
assign \in2_sel 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01010
assign \in2_sel 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01100
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11110
+ assign \in2_sel 4'0001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11111
assign \in2_sel 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00101
assign \in2_sel 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \in2_sel 4'0001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11101
+ assign \in2_sel 4'0001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11100
+ assign \in2_sel 4'0001
end
sync init
end
process $group_6
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00011
- assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00010
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11010
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01011
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11011
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01010
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00001
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00000
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11001
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01011
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01010
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00111
- assign \in3_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00110
- assign \in3_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11110
assign \in3_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01100
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11111
assign \in3_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00101
assign \in3_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \in3_sel 2'01
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11101
+ assign \in3_sel 2'01
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11100
+ assign \in3_sel 2'01
end
sync init
end
process $group_7
assign \out_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00011
- assign \out_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00010
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11010
assign \out_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01011
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11011
assign \out_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01010
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00001
assign \out_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00000
assign \out_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11001
assign \out_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01011
assign \out_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01010
assign \out_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00111
- assign \out_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00110
- assign \out_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11110
assign \out_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01100
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11111
assign \out_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00101
assign \out_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \out_sel 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11101
+ assign \out_sel 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11100
+ assign \out_sel 2'00
end
sync init
end
process $group_8
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00011
- assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00010
- assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01011
- assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01010
- assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11010
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11011
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00111
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11001
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00110
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01011
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01010
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01100
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11110
+ assign \cr_in 3'000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11111
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00101
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \cr_in 3'000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11101
+ assign \cr_in 3'000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11100
+ assign \cr_in 3'000
end
sync init
end
process $group_9
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00011
- assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00010
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11010
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01011
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11011
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01010
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00001
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00000
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11001
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01011
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01010
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00111
- assign \cr_out 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00110
- assign \cr_out 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11110
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01100
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11111
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00101
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \cr_out 3'000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11101
+ assign \cr_out 3'000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11100
+ assign \cr_out 3'000
end
sync init
end
process $group_10
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00011
- assign \ldst_len 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00010
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11010
assign \ldst_len 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01011
- assign \ldst_len 4'0010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01010
- assign \ldst_len 4'0010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01001
- assign \ldst_len 4'0010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01000
- assign \ldst_len 4'0010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11011
+ assign \ldst_len 4'1000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
- assign \ldst_len 4'0100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ assign \ldst_len 4'1000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
+ assign \ldst_len 4'1000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11001
assign \ldst_len 4'0100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00111
- assign \ldst_len 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00110
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01011
+ assign \ldst_len 4'0100
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01010
+ assign \ldst_len 4'0100
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11110
assign \ldst_len 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01101
- assign \ldst_len 4'0010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01100
- assign \ldst_len 4'0010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11111
+ assign \ldst_len 4'1000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00101
- assign \ldst_len 4'0100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ assign \ldst_len 4'1000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
+ assign \ldst_len 4'1000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11101
+ assign \ldst_len 4'0010
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11100
assign \ldst_len 4'0100
end
sync init
end
process $group_11
- assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00011
- assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00010
- assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11010
+ assign \upd 2'10
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11011
+ assign \upd 2'10
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00001
+ assign \upd 2'01
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00000
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11001
+ assign \upd 2'10
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01011
- assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ assign \upd 2'01
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01010
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11110
+ assign \upd 2'10
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11111
+ assign \upd 2'10
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00101
+ assign \upd 2'01
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00100
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11101
+ assign \upd 2'10
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11100
+ assign \upd 2'10
+ end
+ sync init
+ end
+ process $group_12
+ assign \rc_sel 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+ switch \opcode_switch
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11010
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01001
- assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11011
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00111
- assign \rc_sel 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00110
- assign \rc_sel 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11001
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01100
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01011
+ assign \rc_sel 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01010
+ assign \rc_sel 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11110
+ assign \rc_sel 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11111
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00101
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \rc_sel 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11101
+ assign \rc_sel 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11100
+ assign \rc_sel 2'00
end
sync init
end
- process $group_12
+ process $group_13
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00011
- assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00010
- assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01011
- assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01010
- assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11010
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11011
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00111
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11001
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00110
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01011
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01010
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01100
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11110
+ assign \cry_in 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11111
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00101
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \cry_in 2'00
- end
- sync init
- end
- process $group_13
- assign \asmcode 8'00000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
- switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00011
- assign \asmcode 8'01001111
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00010
- assign \asmcode 8'01010000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01011
- assign \asmcode 8'01011010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01010
- assign \asmcode 8'01011011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01001
- assign \asmcode 8'01011111
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01000
- assign \asmcode 8'01100000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00001
- assign \asmcode 8'01101000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00000
- assign \asmcode 8'01101001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00111
- assign \asmcode 8'10100101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00110
- assign \asmcode 8'10100110
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01101
- assign \asmcode 8'10110001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01100
- assign \asmcode 8'10110010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00101
- assign \asmcode 8'10110111
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00100
- assign \asmcode 8'10111000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11101
+ assign \cry_in 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11100
+ assign \cry_in 2'00
end
sync init
end
process $group_14
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00011
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11010
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00010
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11011
+ assign \inv_a 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00001
+ assign \inv_a 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00000
+ assign \inv_a 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11001
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01011
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01010
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11110
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11111
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00001
- assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00000
- assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00111
- assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00110
- assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01101
- assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01100
- assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00101
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \inv_a 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11101
+ assign \inv_a 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11100
+ assign \inv_a 1'0
end
sync init
end
process $group_15
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00011
- assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00010
- assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01011
- assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01010
- assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11010
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11011
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00111
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11001
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00110
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01011
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01010
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01100
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11110
+ assign \inv_out 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11111
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00101
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \inv_out 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11101
+ assign \inv_out 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11100
+ assign \inv_out 1'0
end
sync init
end
process $group_16
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00011
- assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00010
- assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01011
- assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01010
- assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11010
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11011
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00111
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11001
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00110
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01011
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01010
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01100
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11110
+ assign \cry_out 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11111
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00101
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \cry_out 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11101
+ assign \cry_out 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11100
+ assign \cry_out 1'0
end
sync init
end
process $group_17
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00011
- assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00010
- assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01011
- assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01010
- assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11010
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11011
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00111
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11001
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00110
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01011
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01010
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01100
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11110
+ assign \br 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11111
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00101
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \br 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11101
+ assign \br 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11100
+ assign \br 1'0
end
sync init
end
process $group_18
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00011
- assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00010
- assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01011
- assign \sgn_ext 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01010
- assign \sgn_ext 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11010
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11011
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00111
- assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00110
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11001
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01011
+ assign \sgn_ext 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01010
+ assign \sgn_ext 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11110
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01100
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11111
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00101
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \sgn_ext 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11101
+ assign \sgn_ext 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11100
+ assign \sgn_ext 1'0
end
sync init
end
process $group_19
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
- switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00011
- assign \upd 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00010
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01011
- assign \upd 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01010
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01001
- assign \upd 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01000
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00001
- assign \upd 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00000
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00111
- assign \upd 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00110
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01101
- assign \upd 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01100
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00101
- assign \upd 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00100
- assign \upd 1'0
- end
- sync init
- end
- process $group_20
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00011
- assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00010
- assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01011
- assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01010
- assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11010
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11011
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00111
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11001
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00110
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01011
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01010
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01100
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11110
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11111
+ assign \rsrv 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00101
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \rsrv 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11101
+ assign \rsrv 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11100
+ assign \rsrv 1'0
end
sync init
end
- process $group_21
+ process $group_20
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00011
- assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00010
- assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01011
- assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01010
- assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11010
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11011
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00111
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11001
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00110
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01011
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01010
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01100
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11110
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11111
+ assign \is_32b 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00101
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \is_32b 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11101
+ assign \is_32b 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11100
+ assign \is_32b 1'0
end
sync init
end
- process $group_22
+ process $group_21
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00011
- assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00010
- assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01011
- assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01010
- assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11010
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11011
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00111
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11001
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00110
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01011
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01010
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01100
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11110
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11111
+ assign \sgn 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00101
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \sgn 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11101
+ assign \sgn 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11100
+ assign \sgn 1'0
end
sync init
end
- process $group_23
+ process $group_22
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00011
- assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00010
- assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01011
- assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01010
- assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11010
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11011
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00111
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11001
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00110
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01011
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01010
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01100
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11110
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11111
+ assign \lk 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00101
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \lk 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11101
+ assign \lk 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11100
+ assign \lk 1'0
end
sync init
end
- process $group_24
+ process $group_23
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00011
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11010
+ assign \sgl_pipe 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11011
+ assign \sgl_pipe 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00001
assign \sgl_pipe 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00010
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00000
assign \sgl_pipe 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11001
+ assign \sgl_pipe 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01011
assign \sgl_pipe 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01010
assign \sgl_pipe 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01001
- assign \sgl_pipe 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01000
- assign \sgl_pipe 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11110
assign \sgl_pipe 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11111
assign \sgl_pipe 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00111
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00101
assign \sgl_pipe 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00110
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00100
assign \sgl_pipe 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11101
assign \sgl_pipe 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01100
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11100
assign \sgl_pipe 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ end
+ sync init
+ end
+ process $group_24
+ assign \asmcode 8'00000000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+ switch \opcode_switch
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11010
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11011
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00001
+ assign \asmcode 8'01010101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00000
+ assign \asmcode 8'01010110
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01011
+ assign \asmcode 8'01100011
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01010
+ assign \asmcode 8'01100100
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11110
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11111
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00101
- assign \sgl_pipe 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ assign \asmcode 8'10101100
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
- assign \sgl_pipe 1'1
+ assign \asmcode 8'10101101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11100
end
sync init
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.pdecode2.dec.dec31.dec_sub21"
-module \dec_sub21
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219"
+attribute \nmigen.hierarchy "test_issuer.core.pdecode2.dec.dec31.dec_sub23"
+module \dec_sub23
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:229"
wire width 32 input 0 \opcode_in
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_11100 "Z23"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
wire width 5 output 2 \form
- attribute \enum_base_type "InternalOp"
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
+ attribute \enum_value_1001010 "OP_MTMSR"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
wire width 7 output 3 \internal_op
attribute \enum_base_type "In1Sel"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "RC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
wire width 2 output 10 \rc_sel
attribute \enum_base_type "LdstLen"
attribute \enum_value_0000 "NONE"
attribute \enum_value_1000 "is8B"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
wire width 4 output 11 \ldst_len
+ attribute \enum_base_type "LDSTMode"
+ attribute \enum_value_00 "NONE"
+ attribute \enum_value_01 "update"
+ attribute \enum_value_10 "cix"
+ attribute \enum_value_11 "cx"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+ wire width 2 output 12 \upd
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
- wire width 2 output 12 \cry_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 13 \inv_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 14 \inv_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 15 \cry_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 16 \br
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 17 \sgn_ext
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 18 \upd
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
+ wire width 2 output 13 \cry_in
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 14 \inv_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 15 \inv_out
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 16 \cry_out
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 17 \br
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 18 \sgn_ext
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 output 19 \rsrv
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 output 20 \is_32b
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 output 21 \sgn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 output 22 \lk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 output 23 \sgl_pipe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
wire width 8 output 24 \asmcode
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:257"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:267"
wire width 5 \opcode_switch
process $group_0
assign \opcode_switch 5'00000
end
process $group_1
assign \function_unit 11'00000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00011
assign \function_unit 11'00000000100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00010
assign \function_unit 11'00000000100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01011
assign \function_unit 11'00000000100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01010
assign \function_unit 11'00000000100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01001
+ assign \function_unit 11'00000000100
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01000
+ assign \function_unit 11'00000000100
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00001
+ assign \function_unit 11'00000000100
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00000
+ assign \function_unit 11'00000000100
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00111
+ assign \function_unit 11'00000000100
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00110
+ assign \function_unit 11'00000000100
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01101
+ assign \function_unit 11'00000000100
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01100
+ assign \function_unit 11'00000000100
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00101
assign \function_unit 11'00000000100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \function_unit 11'00000000100
end
end
process $group_2
assign \form 5'00000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00011
assign \form 5'01000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00010
assign \form 5'01000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01011
assign \form 5'01000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01010
assign \form 5'01000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01001
+ assign \form 5'01000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01000
+ assign \form 5'01000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00001
+ assign \form 5'01000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00000
+ assign \form 5'01000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00111
+ assign \form 5'01000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00110
+ assign \form 5'01000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01101
+ assign \form 5'01000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01100
+ assign \form 5'01000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00101
assign \form 5'01000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \form 5'01000
end
end
process $group_3
assign \internal_op 7'0000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00011
assign \internal_op 7'0100101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00010
assign \internal_op 7'0100101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01011
assign \internal_op 7'0100101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01010
assign \internal_op 7'0100101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01001
+ assign \internal_op 7'0100101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01000
+ assign \internal_op 7'0100101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00001
+ assign \internal_op 7'0100101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00000
+ assign \internal_op 7'0100101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00111
+ assign \internal_op 7'0100110
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00110
+ assign \internal_op 7'0100110
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01101
+ assign \internal_op 7'0100110
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01100
+ assign \internal_op 7'0100110
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00101
assign \internal_op 7'0100110
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \internal_op 7'0100110
end
end
process $group_4
assign \in1_sel 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00011
assign \in1_sel 3'010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00010
assign \in1_sel 3'010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01011
assign \in1_sel 3'010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01010
assign \in1_sel 3'010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01001
+ assign \in1_sel 3'010
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01000
+ assign \in1_sel 3'010
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00001
+ assign \in1_sel 3'010
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00000
+ assign \in1_sel 3'010
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00111
+ assign \in1_sel 3'010
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00110
+ assign \in1_sel 3'010
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01101
+ assign \in1_sel 3'010
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01100
+ assign \in1_sel 3'010
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00101
assign \in1_sel 3'010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \in1_sel 3'010
end
end
process $group_5
assign \in2_sel 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00011
assign \in2_sel 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00010
assign \in2_sel 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01011
assign \in2_sel 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01010
assign \in2_sel 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01001
+ assign \in2_sel 4'0001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01000
+ assign \in2_sel 4'0001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00001
+ assign \in2_sel 4'0001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00000
+ assign \in2_sel 4'0001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00111
+ assign \in2_sel 4'0001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00110
+ assign \in2_sel 4'0001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01101
+ assign \in2_sel 4'0001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01100
+ assign \in2_sel 4'0001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00101
assign \in2_sel 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \in2_sel 4'0001
end
end
process $group_6
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00011
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00010
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01011
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01010
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01001
+ assign \in3_sel 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01000
+ assign \in3_sel 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00001
+ assign \in3_sel 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00000
+ assign \in3_sel 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00111
+ assign \in3_sel 2'01
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00110
+ assign \in3_sel 2'01
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01101
+ assign \in3_sel 2'01
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01100
+ assign \in3_sel 2'01
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00101
assign \in3_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \in3_sel 2'01
end
end
process $group_7
assign \out_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00011
assign \out_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00010
assign \out_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01011
assign \out_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01010
assign \out_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01001
+ assign \out_sel 2'01
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01000
+ assign \out_sel 2'01
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00001
+ assign \out_sel 2'01
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00000
+ assign \out_sel 2'01
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00111
+ assign \out_sel 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00110
+ assign \out_sel 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01101
+ assign \out_sel 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01100
+ assign \out_sel 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00101
assign \out_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \out_sel 2'00
end
end
process $group_8
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00011
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00010
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01011
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01010
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01001
+ assign \cr_in 3'000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01000
+ assign \cr_in 3'000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00001
+ assign \cr_in 3'000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00000
+ assign \cr_in 3'000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00111
+ assign \cr_in 3'000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00110
+ assign \cr_in 3'000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01101
+ assign \cr_in 3'000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01100
+ assign \cr_in 3'000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00101
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \cr_in 3'000
end
end
process $group_9
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00011
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00010
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01011
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01010
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01001
+ assign \cr_out 3'000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01000
+ assign \cr_out 3'000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00001
+ assign \cr_out 3'000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00000
+ assign \cr_out 3'000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00111
+ assign \cr_out 3'001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00110
+ assign \cr_out 3'001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01101
+ assign \cr_out 3'000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01100
+ assign \cr_out 3'000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00101
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \cr_out 3'000
end
end
process $group_10
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00001
- assign \ldst_len 4'1000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00000
- assign \ldst_len 4'1000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00011
+ assign \ldst_len 4'0001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00010
+ assign \ldst_len 4'0001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01011
- assign \ldst_len 4'0100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ assign \ldst_len 4'0010
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01010
+ assign \ldst_len 4'0010
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01001
+ assign \ldst_len 4'0010
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01000
+ assign \ldst_len 4'0010
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00001
assign \ldst_len 4'0100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00101
- assign \ldst_len 4'1000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00000
+ assign \ldst_len 4'0100
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00111
+ assign \ldst_len 4'0001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00110
+ assign \ldst_len 4'0001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01101
+ assign \ldst_len 4'0010
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01100
+ assign \ldst_len 4'0010
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00101
+ assign \ldst_len 4'0100
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
- assign \ldst_len 4'1000
+ assign \ldst_len 4'0100
end
sync init
end
process $group_11
- assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00011
+ assign \upd 2'01
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00010
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01011
+ assign \upd 2'01
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01010
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01001
+ assign \upd 2'01
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01000
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
- assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ assign \upd 2'01
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00111
+ assign \upd 2'01
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00110
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01101
+ assign \upd 2'01
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01100
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00101
+ assign \upd 2'01
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00100
+ assign \upd 2'00
+ end
+ sync init
+ end
+ process $group_12
+ assign \rc_sel 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+ switch \opcode_switch
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00011
+ assign \rc_sel 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00010
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01011
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01010
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01001
+ assign \rc_sel 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01000
+ assign \rc_sel 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00001
+ assign \rc_sel 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00000
+ assign \rc_sel 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00111
+ assign \rc_sel 2'10
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00110
+ assign \rc_sel 2'10
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01101
+ assign \rc_sel 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01100
+ assign \rc_sel 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00101
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \rc_sel 2'00
end
sync init
end
- process $group_12
+ process $group_13
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00011
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00010
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01011
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01010
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01001
+ assign \cry_in 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01000
+ assign \cry_in 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00001
+ assign \cry_in 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00000
+ assign \cry_in 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00111
+ assign \cry_in 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00110
+ assign \cry_in 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01101
+ assign \cry_in 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01100
+ assign \cry_in 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00101
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \cry_in 2'00
end
sync init
end
- process $group_13
+ process $group_14
assign \asmcode 8'00000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00001
- assign \asmcode 8'01010101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00000
- assign \asmcode 8'01010110
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00011
+ assign \asmcode 8'01001111
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00010
+ assign \asmcode 8'01010000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01011
- assign \asmcode 8'01100011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ assign \asmcode 8'01011010
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01010
- assign \asmcode 8'01100100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ assign \asmcode 8'01011011
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01001
+ assign \asmcode 8'01011111
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01000
+ assign \asmcode 8'01100000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00001
+ assign \asmcode 8'01101000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00000
+ assign \asmcode 8'01101001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00111
+ assign \asmcode 8'10100110
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00110
+ assign \asmcode 8'10100111
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01101
+ assign \asmcode 8'10110010
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01100
+ assign \asmcode 8'10110011
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00101
- assign \asmcode 8'10101011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ assign \asmcode 8'10111000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
- assign \asmcode 8'10101100
+ assign \asmcode 8'10111001
end
sync init
end
- process $group_14
+ process $group_15
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00011
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00010
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01011
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01010
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01001
+ assign \inv_a 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01000
+ assign \inv_a 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00001
+ assign \inv_a 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00000
+ assign \inv_a 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00111
+ assign \inv_a 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00110
+ assign \inv_a 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01101
+ assign \inv_a 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01100
+ assign \inv_a 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00101
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \inv_a 1'0
end
sync init
end
- process $group_15
+ process $group_16
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00011
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00010
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01011
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01010
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01001
+ assign \inv_out 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01000
+ assign \inv_out 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00001
+ assign \inv_out 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00000
+ assign \inv_out 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00111
+ assign \inv_out 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00110
+ assign \inv_out 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01101
+ assign \inv_out 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01100
+ assign \inv_out 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00101
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \inv_out 1'0
end
sync init
end
- process $group_16
+ process $group_17
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00011
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00010
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01011
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01010
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01001
+ assign \cry_out 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01000
+ assign \cry_out 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00001
+ assign \cry_out 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00000
+ assign \cry_out 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00111
+ assign \cry_out 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00110
+ assign \cry_out 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01101
+ assign \cry_out 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01100
+ assign \cry_out 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00101
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \cry_out 1'0
end
sync init
end
- process $group_17
+ process $group_18
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00011
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00010
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01011
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01010
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01001
+ assign \br 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01000
+ assign \br 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00001
+ assign \br 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00000
+ assign \br 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00111
+ assign \br 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00110
+ assign \br 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01101
+ assign \br 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01100
+ assign \br 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00101
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \br 1'0
end
sync init
end
- process $group_18
+ process $group_19
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00011
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00010
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01011
assign \sgn_ext 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01010
assign \sgn_ext 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01001
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00100
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01000
assign \sgn_ext 1'0
- end
- sync init
- end
- process $group_19
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
- switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
- assign \upd 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ assign \sgn_ext 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01011
- assign \upd 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'01010
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ assign \sgn_ext 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00111
+ assign \sgn_ext 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00110
+ assign \sgn_ext 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01101
+ assign \sgn_ext 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01100
+ assign \sgn_ext 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00101
- assign \upd 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ assign \sgn_ext 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
- assign \upd 1'0
+ assign \sgn_ext 1'0
end
sync init
end
process $group_20
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00011
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00010
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01011
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01010
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01001
+ assign \rsrv 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01000
+ assign \rsrv 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00001
+ assign \rsrv 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00000
+ assign \rsrv 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00111
+ assign \rsrv 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00110
+ assign \rsrv 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01101
+ assign \rsrv 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01100
+ assign \rsrv 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00101
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \rsrv 1'0
end
end
process $group_21
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00011
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00010
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01011
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01010
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01001
+ assign \is_32b 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01000
+ assign \is_32b 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00001
+ assign \is_32b 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00000
+ assign \is_32b 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00111
+ assign \is_32b 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00110
+ assign \is_32b 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01101
+ assign \is_32b 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01100
+ assign \is_32b 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00101
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \is_32b 1'0
end
end
process $group_22
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00011
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00010
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01011
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01010
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01001
+ assign \sgn 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01000
+ assign \sgn 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00001
+ assign \sgn 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00000
+ assign \sgn 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00111
+ assign \sgn 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00110
+ assign \sgn 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01101
+ assign \sgn 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01100
+ assign \sgn 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00101
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \sgn 1'0
end
end
process $group_23
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00011
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00010
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01011
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01010
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01001
+ assign \lk 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01000
+ assign \lk 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00001
+ assign \lk 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00000
+ assign \lk 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00111
+ assign \lk 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00110
+ assign \lk 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01101
+ assign \lk 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01100
+ assign \lk 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00101
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \lk 1'0
end
end
process $group_24
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00011
assign \sgl_pipe 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00010
assign \sgl_pipe 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01011
assign \sgl_pipe 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'01010
assign \sgl_pipe 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01001
+ assign \sgl_pipe 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01000
+ assign \sgl_pipe 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00001
+ assign \sgl_pipe 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00000
+ assign \sgl_pipe 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00111
+ assign \sgl_pipe 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00110
+ assign \sgl_pipe 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01101
+ assign \sgl_pipe 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'01100
+ assign \sgl_pipe 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00101
assign \sgl_pipe 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \sgl_pipe 1'1
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "test_issuer.core.pdecode2.dec.dec31.dec_sub16"
module \dec_sub16
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:229"
wire width 32 input 0 \opcode_in
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_11100 "Z23"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
wire width 5 output 2 \form
- attribute \enum_base_type "InternalOp"
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
+ attribute \enum_value_1001010 "OP_MTMSR"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
wire width 7 output 3 \internal_op
attribute \enum_base_type "In1Sel"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "RC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
wire width 2 output 10 \rc_sel
attribute \enum_base_type "LdstLen"
attribute \enum_value_0000 "NONE"
attribute \enum_value_1000 "is8B"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
wire width 4 output 11 \ldst_len
+ attribute \enum_base_type "LDSTMode"
+ attribute \enum_value_00 "NONE"
+ attribute \enum_value_01 "update"
+ attribute \enum_value_10 "cix"
+ attribute \enum_value_11 "cx"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+ wire width 2 output 12 \upd
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
- wire width 2 output 12 \cry_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 13 \inv_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 14 \inv_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 15 \cry_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 16 \br
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 17 \sgn_ext
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 18 \upd
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
+ wire width 2 output 13 \cry_in
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 14 \inv_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 15 \inv_out
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 16 \cry_out
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 17 \br
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 18 \sgn_ext
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 output 19 \rsrv
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 output 20 \is_32b
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 output 21 \sgn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 output 22 \lk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 output 23 \sgl_pipe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
wire width 8 output 24 \asmcode
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:257"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:267"
wire width 5 \opcode_switch
process $group_0
assign \opcode_switch 5'00000
end
process $group_1
assign \function_unit 11'00000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \function_unit 11'00001000000
end
end
process $group_2
assign \form 5'00000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \form 5'01010
end
end
process $group_3
assign \internal_op 7'0000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \internal_op 7'0110000
end
end
process $group_4
assign \in1_sel 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \in1_sel 3'100
end
end
process $group_5
assign \in2_sel 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \in2_sel 4'0000
end
end
process $group_6
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \in3_sel 2'00
end
end
process $group_7
assign \out_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \out_sel 2'00
end
end
process $group_8
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \cr_in 3'110
end
end
process $group_9
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \cr_out 3'100
end
end
process $group_10
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \ldst_len 4'0000
end
sync init
end
process $group_11
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+ switch \opcode_switch
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00100
+ assign \upd 2'00
+ end
+ sync init
+ end
+ process $group_12
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \rc_sel 2'00
end
sync init
end
- process $group_12
+ process $group_13
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \cry_in 2'00
end
sync init
end
- process $group_13
+ process $group_14
assign \asmcode 8'00000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \asmcode 8'01110100
end
sync init
end
- process $group_14
+ process $group_15
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \inv_a 1'0
end
sync init
end
- process $group_15
+ process $group_16
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \inv_out 1'0
end
sync init
end
- process $group_16
+ process $group_17
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \cry_out 1'0
end
sync init
end
- process $group_17
+ process $group_18
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \br 1'0
end
sync init
end
- process $group_18
+ process $group_19
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \sgn_ext 1'0
end
sync init
end
- process $group_19
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
- switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00100
- assign \upd 1'0
- end
- sync init
- end
process $group_20
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \rsrv 1'0
end
end
process $group_21
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \is_32b 1'0
end
end
process $group_22
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \sgn 1'0
end
end
process $group_23
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \lk 1'0
end
end
process $group_24
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \sgl_pipe 1'0
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "test_issuer.core.pdecode2.dec.dec31.dec_sub18"
module \dec_sub18
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:229"
wire width 32 input 0 \opcode_in
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_11100 "Z23"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
wire width 5 output 2 \form
- attribute \enum_base_type "InternalOp"
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
+ attribute \enum_value_1001010 "OP_MTMSR"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
wire width 7 output 3 \internal_op
attribute \enum_base_type "In1Sel"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "RC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
wire width 2 output 10 \rc_sel
attribute \enum_base_type "LdstLen"
attribute \enum_value_0000 "NONE"
attribute \enum_value_1000 "is8B"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
wire width 4 output 11 \ldst_len
+ attribute \enum_base_type "LDSTMode"
+ attribute \enum_value_00 "NONE"
+ attribute \enum_value_01 "update"
+ attribute \enum_value_10 "cix"
+ attribute \enum_value_11 "cx"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+ wire width 2 output 12 \upd
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
- wire width 2 output 12 \cry_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 13 \inv_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 14 \inv_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 15 \cry_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 16 \br
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 17 \sgn_ext
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 18 \upd
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
+ wire width 2 output 13 \cry_in
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 14 \inv_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 15 \inv_out
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 16 \cry_out
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 17 \br
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 18 \sgn_ext
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 output 19 \rsrv
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 output 20 \is_32b
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 output 21 \sgn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 output 22 \lk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 output 23 \sgl_pipe
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:257"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
+ wire width 8 output 24 \asmcode
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:267"
wire width 5 \opcode_switch
process $group_0
assign \opcode_switch 5'00000
end
process $group_1
assign \function_unit 11'00000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00101
assign \function_unit 11'00010000000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00100
+ assign \function_unit 11'00010000000
end
sync init
end
process $group_2
assign \form 5'00000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00101
assign \form 5'01000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00100
+ assign \form 5'01000
end
sync init
end
process $group_3
assign \internal_op 7'0000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00101
assign \internal_op 7'1001000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00100
+ assign \internal_op 7'1001010
end
sync init
end
process $group_4
assign \in1_sel 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00101
assign \in1_sel 3'100
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00100
+ assign \in1_sel 3'100
end
sync init
end
process $group_5
assign \in2_sel 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00101
assign \in2_sel 4'0000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00100
+ assign \in2_sel 4'0000
end
sync init
end
process $group_6
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00101
assign \in3_sel 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00100
+ assign \in3_sel 2'00
end
sync init
end
process $group_7
assign \out_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00101
assign \out_sel 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00100
+ assign \out_sel 2'00
end
sync init
end
process $group_8
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00101
assign \cr_in 3'000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00100
+ assign \cr_in 3'000
end
sync init
end
process $group_9
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00101
assign \cr_out 3'000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00100
+ assign \cr_out 3'000
end
sync init
end
process $group_10
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00101
assign \ldst_len 4'0000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00100
+ assign \ldst_len 4'0000
end
sync init
end
process $group_11
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+ switch \opcode_switch
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00101
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00100
+ assign \upd 2'00
+ end
+ sync init
+ end
+ process $group_12
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00101
assign \rc_sel 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00100
+ assign \rc_sel 2'00
end
sync init
end
- process $group_12
+ process $group_13
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00101
assign \cry_in 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00100
+ assign \cry_in 2'00
end
sync init
end
- process $group_13
+ process $group_14
+ assign \asmcode 8'00000000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+ switch \opcode_switch
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00101
+ assign \asmcode 8'01110110
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00100
+ assign \asmcode 8'01110101
+ end
+ sync init
+ end
+ process $group_15
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00101
assign \inv_a 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00100
+ assign \inv_a 1'0
end
sync init
end
- process $group_14
+ process $group_16
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00101
assign \inv_out 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00100
+ assign \inv_out 1'0
end
sync init
end
- process $group_15
+ process $group_17
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00101
assign \cry_out 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00100
+ assign \cry_out 1'0
end
sync init
end
- process $group_16
+ process $group_18
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00101
assign \br 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00100
+ assign \br 1'0
end
sync init
end
- process $group_17
+ process $group_19
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00101
assign \sgn_ext 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00100
+ assign \sgn_ext 1'0
end
sync init
end
- process $group_18
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
- switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00101
- assign \upd 1'0
- end
- sync init
- end
- process $group_19
+ process $group_20
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00101
assign \rsrv 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00100
+ assign \rsrv 1'0
end
sync init
end
- process $group_20
+ process $group_21
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00101
assign \is_32b 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00100
+ assign \is_32b 1'0
end
sync init
end
- process $group_21
+ process $group_22
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00101
assign \sgn 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00100
+ assign \sgn 1'0
end
sync init
end
- process $group_22
+ process $group_23
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00101
assign \lk 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00100
+ assign \lk 1'0
end
sync init
end
- process $group_23
+ process $group_24
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00101
assign \sgl_pipe 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00100
+ assign \sgl_pipe 1'1
end
sync init
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "test_issuer.core.pdecode2.dec.dec31.dec_sub8"
module \dec_sub8
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:229"
wire width 32 input 0 \opcode_in
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_11100 "Z23"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
wire width 5 output 2 \form
- attribute \enum_base_type "InternalOp"
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
+ attribute \enum_value_1001010 "OP_MTMSR"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
wire width 7 output 3 \internal_op
attribute \enum_base_type "In1Sel"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "RC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
wire width 2 output 10 \rc_sel
attribute \enum_base_type "LdstLen"
attribute \enum_value_0000 "NONE"
attribute \enum_value_1000 "is8B"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
wire width 4 output 11 \ldst_len
+ attribute \enum_base_type "LDSTMode"
+ attribute \enum_value_00 "NONE"
+ attribute \enum_value_01 "update"
+ attribute \enum_value_10 "cix"
+ attribute \enum_value_11 "cx"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+ wire width 2 output 12 \upd
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
- wire width 2 output 12 \cry_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 13 \inv_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 14 \inv_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 15 \cry_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 16 \br
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 17 \sgn_ext
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 18 \upd
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
+ wire width 2 output 13 \cry_in
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 14 \inv_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 15 \inv_out
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 16 \cry_out
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 17 \br
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 18 \sgn_ext
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 output 19 \rsrv
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 output 20 \is_32b
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 output 21 \sgn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 output 22 \lk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 output 23 \sgl_pipe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
wire width 8 output 24 \asmcode
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:257"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:267"
wire width 5 \opcode_switch
process $group_0
assign \opcode_switch 5'00000
end
process $group_1
assign \function_unit 11'00000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00011
assign \function_unit 11'00000000010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10011
assign \function_unit 11'00000000010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \function_unit 11'00000000010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10001
assign \function_unit 11'00000000010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \function_unit 11'00000000010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \function_unit 11'00000000010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \function_unit 11'00000000010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10100
assign \function_unit 11'00000000010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \function_unit 11'00000000010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10111
assign \function_unit 11'00000000010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00110
assign \function_unit 11'00000000010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10110
assign \function_unit 11'00000000010
end
end
process $group_2
assign \form 5'00000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00011
assign \form 5'10001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10011
assign \form 5'10001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \form 5'10001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10001
assign \form 5'10001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \form 5'10001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \form 5'10001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \form 5'10001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10100
assign \form 5'10001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \form 5'10001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10111
assign \form 5'10001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00110
assign \form 5'10001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10110
assign \form 5'10001
end
end
process $group_3
assign \internal_op 7'0000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00011
assign \internal_op 7'0000010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10011
assign \internal_op 7'0000010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \internal_op 7'0000010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10001
assign \internal_op 7'0000010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \internal_op 7'0000010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \internal_op 7'0000010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \internal_op 7'0000010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10100
assign \internal_op 7'0000010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \internal_op 7'0000010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10111
assign \internal_op 7'0000010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00110
assign \internal_op 7'0000010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10110
assign \internal_op 7'0000010
end
end
process $group_4
assign \in1_sel 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00011
assign \in1_sel 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10011
assign \in1_sel 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \in1_sel 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10001
assign \in1_sel 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \in1_sel 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \in1_sel 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \in1_sel 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10100
assign \in1_sel 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \in1_sel 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10111
assign \in1_sel 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00110
assign \in1_sel 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10110
assign \in1_sel 3'001
end
end
process $group_5
assign \in2_sel 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00011
assign \in2_sel 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10011
assign \in2_sel 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \in2_sel 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10001
assign \in2_sel 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \in2_sel 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \in2_sel 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \in2_sel 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10100
assign \in2_sel 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \in2_sel 4'1001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10111
assign \in2_sel 4'1001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00110
assign \in2_sel 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10110
assign \in2_sel 4'0000
end
end
process $group_6
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00011
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10011
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10001
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10100
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10111
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00110
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10110
assign \in3_sel 2'00
end
end
process $group_7
assign \out_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00011
assign \out_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10011
assign \out_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \out_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10001
assign \out_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \out_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \out_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \out_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10100
assign \out_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \out_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10111
assign \out_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00110
assign \out_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10110
assign \out_sel 2'01
end
end
process $group_8
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00011
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10011
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10001
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10100
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10111
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00110
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10110
assign \cr_in 3'000
end
end
process $group_9
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00011
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10011
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \cr_out 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10001
assign \cr_out 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \cr_out 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \cr_out 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \cr_out 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10100
assign \cr_out 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \cr_out 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10111
assign \cr_out 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00110
assign \cr_out 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10110
assign \cr_out 3'001
end
end
process $group_10
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00011
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10011
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10001
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10100
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10111
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00110
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10110
assign \ldst_len 4'0000
end
sync init
end
process $group_11
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+ switch \opcode_switch
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00011
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'10011
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00001
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'10001
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00000
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'10000
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00100
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'10100
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00111
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'10111
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00110
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'10110
+ assign \upd 2'00
+ end
+ sync init
+ end
+ process $group_12
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00011
assign \rc_sel 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10011
assign \rc_sel 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \rc_sel 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10001
assign \rc_sel 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \rc_sel 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \rc_sel 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \rc_sel 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10100
assign \rc_sel 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \rc_sel 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10111
assign \rc_sel 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00110
assign \rc_sel 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10110
assign \rc_sel 2'10
end
sync init
end
- process $group_12
+ process $group_13
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00011
assign \cry_in 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10011
assign \cry_in 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \cry_in 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10001
assign \cry_in 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \cry_in 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \cry_in 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \cry_in 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10100
assign \cry_in 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \cry_in 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10111
assign \cry_in 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00110
assign \cry_in 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10110
assign \cry_in 2'10
end
sync init
end
- process $group_13
+ process $group_14
assign \asmcode 8'00000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00011
- assign \asmcode 8'10000001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'10011
assign \asmcode 8'10000010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'10011
+ assign \asmcode 8'10000011
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
- assign \asmcode 8'10111001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ assign \asmcode 8'10111010
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10001
- assign \asmcode 8'11000001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ assign \asmcode 8'11000010
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
- assign \asmcode 8'10111010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'10000
assign \asmcode 8'10111011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00100
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'10000
assign \asmcode 8'10111100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'10100
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00100
assign \asmcode 8'10111101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'10100
+ assign \asmcode 8'10111110
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
- assign \asmcode 8'10111111
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'10111
assign \asmcode 8'11000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'10111
+ assign \asmcode 8'11000001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00110
- assign \asmcode 8'11000010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'10110
assign \asmcode 8'11000011
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'10110
+ assign \asmcode 8'11000100
end
sync init
end
- process $group_14
+ process $group_15
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00011
assign \inv_a 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10011
assign \inv_a 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \inv_a 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10001
assign \inv_a 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \inv_a 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \inv_a 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \inv_a 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10100
assign \inv_a 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \inv_a 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10111
assign \inv_a 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00110
assign \inv_a 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10110
assign \inv_a 1'1
end
sync init
end
- process $group_15
+ process $group_16
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00011
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10011
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10001
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10100
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10111
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00110
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10110
assign \inv_out 1'0
end
sync init
end
- process $group_16
+ process $group_17
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00011
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10011
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10001
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \cry_out 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \cry_out 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \cry_out 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10100
assign \cry_out 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \cry_out 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10111
assign \cry_out 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00110
assign \cry_out 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10110
assign \cry_out 1'1
end
sync init
end
- process $group_17
+ process $group_18
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00011
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10011
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10001
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10100
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10111
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00110
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10110
assign \br 1'0
end
sync init
end
- process $group_18
+ process $group_19
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00011
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10011
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10001
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10100
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10111
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00110
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10110
assign \sgn_ext 1'0
end
sync init
end
- process $group_19
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
- switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00011
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'10011
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00001
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'10001
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00000
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'10000
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00100
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'10100
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00111
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'10111
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00110
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'10110
- assign \upd 1'0
- end
- sync init
- end
process $group_20
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00011
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10011
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10001
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10100
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10111
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00110
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10110
assign \rsrv 1'0
end
end
process $group_21
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00011
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10011
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10001
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10100
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10111
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00110
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10110
assign \is_32b 1'0
end
end
process $group_22
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00011
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10011
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10001
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10100
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10111
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00110
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10110
assign \sgn 1'0
end
end
process $group_23
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00011
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10011
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10001
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10100
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10111
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00110
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10110
assign \lk 1'0
end
end
process $group_24
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00011
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10011
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00001
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10001
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00100
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10100
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00111
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10111
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00110
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10110
assign \sgl_pipe 1'0
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "test_issuer.core.pdecode2.dec.dec31.dec_sub24"
module \dec_sub24
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:229"
wire width 32 input 0 \opcode_in
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_11100 "Z23"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
wire width 5 output 2 \form
- attribute \enum_base_type "InternalOp"
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
+ attribute \enum_value_1001010 "OP_MTMSR"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
wire width 7 output 3 \internal_op
attribute \enum_base_type "In1Sel"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "RC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
wire width 2 output 10 \rc_sel
attribute \enum_base_type "LdstLen"
attribute \enum_value_0000 "NONE"
attribute \enum_value_1000 "is8B"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
wire width 4 output 11 \ldst_len
+ attribute \enum_base_type "LDSTMode"
+ attribute \enum_value_00 "NONE"
+ attribute \enum_value_01 "update"
+ attribute \enum_value_10 "cix"
+ attribute \enum_value_11 "cx"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+ wire width 2 output 12 \upd
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
- wire width 2 output 12 \cry_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 13 \inv_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 14 \inv_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 15 \cry_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 16 \br
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 17 \sgn_ext
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 18 \upd
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
+ wire width 2 output 13 \cry_in
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 14 \inv_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 15 \inv_out
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 16 \cry_out
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 17 \br
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 18 \sgn_ext
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 output 19 \rsrv
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 output 20 \is_32b
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 output 21 \sgn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 output 22 \lk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 output 23 \sgl_pipe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
wire width 8 output 24 \asmcode
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:257"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:267"
wire width 5 \opcode_switch
process $group_0
assign \opcode_switch 5'00000
end
process $group_1
assign \function_unit 11'00000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \function_unit 11'00000001000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \function_unit 11'00000001000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11001
assign \function_unit 11'00000001000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \function_unit 11'00000001000
end
end
process $group_2
assign \form 5'00000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \form 5'01000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \form 5'01000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11001
assign \form 5'01000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \form 5'01000
end
end
process $group_3
assign \internal_op 7'0000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \internal_op 7'0111100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \internal_op 7'0111101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11001
assign \internal_op 7'0111101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \internal_op 7'0111101
end
end
process $group_4
assign \in1_sel 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \in1_sel 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \in1_sel 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11001
assign \in1_sel 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \in1_sel 3'000
end
end
process $group_5
assign \in2_sel 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \in2_sel 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \in2_sel 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11001
assign \in2_sel 4'1011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \in2_sel 4'0001
end
end
process $group_6
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \in3_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \in3_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11001
assign \in3_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \in3_sel 2'01
end
end
process $group_7
assign \out_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \out_sel 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \out_sel 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11001
assign \out_sel 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \out_sel 2'10
end
end
process $group_8
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11001
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \cr_in 3'000
end
end
process $group_9
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \cr_out 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \cr_out 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11001
assign \cr_out 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \cr_out 3'001
end
end
process $group_10
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11001
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \ldst_len 4'0000
end
sync init
end
process $group_11
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+ switch \opcode_switch
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00000
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11000
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11001
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'10000
+ assign \upd 2'00
+ end
+ sync init
+ end
+ process $group_12
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \rc_sel 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \rc_sel 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11001
assign \rc_sel 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \rc_sel 2'10
end
sync init
end
- process $group_12
+ process $group_13
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11001
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \cry_in 2'00
end
sync init
end
- process $group_13
+ process $group_14
assign \asmcode 8'00000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
- assign \asmcode 8'10011011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ assign \asmcode 8'10011100
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
- assign \asmcode 8'10011110
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'11001
assign \asmcode 8'10011111
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'11001
+ assign \asmcode 8'10100000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
- assign \asmcode 8'10100001
+ assign \asmcode 8'10100010
end
sync init
end
- process $group_14
+ process $group_15
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11001
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \inv_a 1'0
end
sync init
end
- process $group_15
+ process $group_16
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11001
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \inv_out 1'0
end
sync init
end
- process $group_16
+ process $group_17
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \cry_out 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11001
assign \cry_out 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \cry_out 1'0
end
sync init
end
- process $group_17
+ process $group_18
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11001
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \br 1'0
end
sync init
end
- process $group_18
+ process $group_19
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11001
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \sgn_ext 1'0
end
sync init
end
- process $group_19
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
- switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00000
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'11000
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'11001
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'10000
- assign \upd 1'0
- end
- sync init
- end
process $group_20
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11001
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \rsrv 1'0
end
end
process $group_21
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \is_32b 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \is_32b 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11001
assign \is_32b 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \is_32b 1'1
end
end
process $group_22
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \sgn 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11001
assign \sgn 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \sgn 1'0
end
end
process $group_23
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11001
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \lk 1'0
end
end
process $group_24
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11000
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'11001
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'10000
assign \sgl_pipe 1'0
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "test_issuer.core.pdecode2.dec.dec31.dec_sub4"
module \dec_sub4
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:229"
wire width 32 input 0 \opcode_in
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_11100 "Z23"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
wire width 5 output 2 \form
- attribute \enum_base_type "InternalOp"
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
+ attribute \enum_value_1001010 "OP_MTMSR"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
wire width 7 output 3 \internal_op
attribute \enum_base_type "In1Sel"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "RC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
wire width 2 output 10 \rc_sel
attribute \enum_base_type "LdstLen"
attribute \enum_value_0000 "NONE"
attribute \enum_value_1000 "is8B"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
wire width 4 output 11 \ldst_len
+ attribute \enum_base_type "LDSTMode"
+ attribute \enum_value_00 "NONE"
+ attribute \enum_value_01 "update"
+ attribute \enum_value_10 "cix"
+ attribute \enum_value_11 "cx"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+ wire width 2 output 12 \upd
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
- wire width 2 output 12 \cry_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 13 \inv_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 14 \inv_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 15 \cry_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 16 \br
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 17 \sgn_ext
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 18 \upd
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
+ wire width 2 output 13 \cry_in
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 14 \inv_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 15 \inv_out
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 16 \cry_out
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 17 \br
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 18 \sgn_ext
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 output 19 \rsrv
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 output 20 \is_32b
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 output 21 \sgn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 output 22 \lk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 output 23 \sgl_pipe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
wire width 8 output 24 \asmcode
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:257"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:267"
wire width 5 \opcode_switch
process $group_0
assign \opcode_switch 5'00000
end
process $group_1
assign \function_unit 11'00000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \function_unit 11'00010000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \function_unit 11'00010000000
end
end
process $group_2
assign \form 5'00000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \form 5'01000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \form 5'01000
end
end
process $group_3
assign \internal_op 7'0000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \internal_op 7'0111111
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \internal_op 7'0111111
end
end
process $group_4
assign \in1_sel 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \in1_sel 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \in1_sel 3'001
end
end
process $group_5
assign \in2_sel 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \in2_sel 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \in2_sel 4'0001
end
end
process $group_6
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \in3_sel 2'00
end
end
process $group_7
assign \out_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \out_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \out_sel 2'00
end
end
process $group_8
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \cr_in 3'000
end
end
process $group_9
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \cr_out 3'000
end
end
process $group_10
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \ldst_len 4'0000
end
sync init
end
process $group_11
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+ switch \opcode_switch
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00010
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 5'00000
+ assign \upd 2'00
+ end
+ sync init
+ end
+ process $group_12
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \rc_sel 2'00
end
sync init
end
- process $group_12
+ process $group_13
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \cry_in 2'00
end
sync init
end
- process $group_13
+ process $group_14
assign \asmcode 8'00000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
- assign \asmcode 8'11000101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ assign \asmcode 8'11000110
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
- assign \asmcode 8'11000111
+ assign \asmcode 8'11001000
end
sync init
end
- process $group_14
+ process $group_15
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \inv_a 1'0
end
sync init
end
- process $group_15
+ process $group_16
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \inv_out 1'0
end
sync init
end
- process $group_16
+ process $group_17
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \cry_out 1'0
end
sync init
end
- process $group_17
+ process $group_18
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \br 1'0
end
sync init
end
- process $group_18
+ process $group_19
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \sgn_ext 1'0
end
sync init
end
- process $group_19
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
- switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00010
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 5'00000
- assign \upd 1'0
- end
- sync init
- end
process $group_20
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \rsrv 1'0
end
end
process $group_21
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \is_32b 1'1
end
end
process $group_22
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \sgn 1'0
end
end
process $group_23
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \lk 1'0
end
end
process $group_24
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00010
assign \sgl_pipe 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 5'00000
assign \sgl_pipe 1'1
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "test_issuer.core.pdecode2.dec.dec31"
module \dec31
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:229"
wire width 32 input 0 \opcode_in
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_11100 "Z23"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
wire width 5 output 2 \form
- attribute \enum_base_type "InternalOp"
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
+ attribute \enum_value_1001010 "OP_MTMSR"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
wire width 7 output 3 \internal_op
attribute \enum_base_type "In1Sel"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "RC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
wire width 2 output 10 \rc_sel
attribute \enum_base_type "LdstLen"
attribute \enum_value_0000 "NONE"
attribute \enum_value_1000 "is8B"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
wire width 4 output 11 \ldst_len
+ attribute \enum_base_type "LDSTMode"
+ attribute \enum_value_00 "NONE"
+ attribute \enum_value_01 "update"
+ attribute \enum_value_10 "cix"
+ attribute \enum_value_11 "cx"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+ wire width 2 output 12 \upd
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
- wire width 2 output 12 \cry_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 13 \inv_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 14 \inv_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 15 \cry_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 16 \br
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 17 \sgn_ext
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 18 \upd
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
+ wire width 2 output 13 \cry_in
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 14 \inv_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 15 \inv_out
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 16 \cry_out
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 17 \br
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 18 \sgn_ext
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 output 19 \rsrv
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 output 20 \is_32b
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 output 21 \sgn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 output 22 \lk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 output 23 \sgl_pipe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
wire width 8 output 24 \asmcode
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:229"
wire width 32 \dec_sub10_opcode_in
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_11100 "Z23"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
wire width 5 \dec_sub10_form
- attribute \enum_base_type "InternalOp"
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
+ attribute \enum_value_1001010 "OP_MTMSR"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
wire width 7 \dec_sub10_internal_op
attribute \enum_base_type "In1Sel"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "RC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
wire width 2 \dec_sub10_rc_sel
attribute \enum_base_type "LdstLen"
attribute \enum_value_0000 "NONE"
attribute \enum_value_1000 "is8B"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
wire width 4 \dec_sub10_ldst_len
+ attribute \enum_base_type "LDSTMode"
+ attribute \enum_value_00 "NONE"
+ attribute \enum_value_01 "update"
+ attribute \enum_value_10 "cix"
+ attribute \enum_value_11 "cx"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+ wire width 2 \dec_sub10_upd
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
wire width 2 \dec_sub10_cry_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub10_inv_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub10_inv_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub10_cry_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub10_br
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub10_sgn_ext
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 \dec_sub10_upd
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub10_rsrv
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub10_is_32b
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub10_sgn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub10_lk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub10_sgl_pipe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
wire width 8 \dec_sub10_asmcode
connect \cr_out \dec_sub10_cr_out
connect \rc_sel \dec_sub10_rc_sel
connect \ldst_len \dec_sub10_ldst_len
+ connect \upd \dec_sub10_upd
connect \cry_in \dec_sub10_cry_in
connect \inv_a \dec_sub10_inv_a
connect \inv_out \dec_sub10_inv_out
connect \cry_out \dec_sub10_cry_out
connect \br \dec_sub10_br
connect \sgn_ext \dec_sub10_sgn_ext
- connect \upd \dec_sub10_upd
connect \rsrv \dec_sub10_rsrv
connect \is_32b \dec_sub10_is_32b
connect \sgn \dec_sub10_sgn
connect \sgl_pipe \dec_sub10_sgl_pipe
connect \asmcode \dec_sub10_asmcode
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:229"
wire width 32 \dec_sub28_opcode_in
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_11100 "Z23"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
wire width 5 \dec_sub28_form
- attribute \enum_base_type "InternalOp"
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
+ attribute \enum_value_1001010 "OP_MTMSR"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
wire width 7 \dec_sub28_internal_op
attribute \enum_base_type "In1Sel"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "RC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
wire width 2 \dec_sub28_rc_sel
attribute \enum_base_type "LdstLen"
attribute \enum_value_0000 "NONE"
attribute \enum_value_1000 "is8B"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
wire width 4 \dec_sub28_ldst_len
+ attribute \enum_base_type "LDSTMode"
+ attribute \enum_value_00 "NONE"
+ attribute \enum_value_01 "update"
+ attribute \enum_value_10 "cix"
+ attribute \enum_value_11 "cx"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+ wire width 2 \dec_sub28_upd
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
wire width 2 \dec_sub28_cry_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub28_inv_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub28_inv_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub28_cry_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub28_br
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub28_sgn_ext
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 \dec_sub28_upd
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub28_rsrv
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub28_is_32b
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub28_sgn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub28_lk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub28_sgl_pipe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
wire width 8 \dec_sub28_asmcode
connect \cr_out \dec_sub28_cr_out
connect \rc_sel \dec_sub28_rc_sel
connect \ldst_len \dec_sub28_ldst_len
+ connect \upd \dec_sub28_upd
connect \cry_in \dec_sub28_cry_in
connect \inv_a \dec_sub28_inv_a
connect \inv_out \dec_sub28_inv_out
connect \cry_out \dec_sub28_cry_out
connect \br \dec_sub28_br
connect \sgn_ext \dec_sub28_sgn_ext
- connect \upd \dec_sub28_upd
connect \rsrv \dec_sub28_rsrv
connect \is_32b \dec_sub28_is_32b
connect \sgn \dec_sub28_sgn
connect \sgl_pipe \dec_sub28_sgl_pipe
connect \asmcode \dec_sub28_asmcode
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:229"
wire width 32 \dec_sub0_opcode_in
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_11100 "Z23"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
wire width 5 \dec_sub0_form
- attribute \enum_base_type "InternalOp"
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
+ attribute \enum_value_1001010 "OP_MTMSR"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
wire width 7 \dec_sub0_internal_op
attribute \enum_base_type "In1Sel"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "RC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
wire width 2 \dec_sub0_rc_sel
attribute \enum_base_type "LdstLen"
attribute \enum_value_0000 "NONE"
attribute \enum_value_1000 "is8B"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
wire width 4 \dec_sub0_ldst_len
+ attribute \enum_base_type "LDSTMode"
+ attribute \enum_value_00 "NONE"
+ attribute \enum_value_01 "update"
+ attribute \enum_value_10 "cix"
+ attribute \enum_value_11 "cx"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+ wire width 2 \dec_sub0_upd
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
wire width 2 \dec_sub0_cry_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub0_inv_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub0_inv_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub0_cry_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub0_br
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub0_sgn_ext
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 \dec_sub0_upd
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub0_rsrv
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub0_is_32b
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub0_sgn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub0_lk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub0_sgl_pipe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
wire width 8 \dec_sub0_asmcode
connect \cr_out \dec_sub0_cr_out
connect \rc_sel \dec_sub0_rc_sel
connect \ldst_len \dec_sub0_ldst_len
+ connect \upd \dec_sub0_upd
connect \cry_in \dec_sub0_cry_in
connect \inv_a \dec_sub0_inv_a
connect \inv_out \dec_sub0_inv_out
connect \cry_out \dec_sub0_cry_out
connect \br \dec_sub0_br
connect \sgn_ext \dec_sub0_sgn_ext
- connect \upd \dec_sub0_upd
connect \rsrv \dec_sub0_rsrv
connect \is_32b \dec_sub0_is_32b
connect \sgn \dec_sub0_sgn
connect \sgl_pipe \dec_sub0_sgl_pipe
connect \asmcode \dec_sub0_asmcode
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:229"
wire width 32 \dec_sub26_opcode_in
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_11100 "Z23"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
wire width 5 \dec_sub26_form
- attribute \enum_base_type "InternalOp"
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
+ attribute \enum_value_1001010 "OP_MTMSR"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
wire width 7 \dec_sub26_internal_op
attribute \enum_base_type "In1Sel"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "RC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
wire width 2 \dec_sub26_rc_sel
attribute \enum_base_type "LdstLen"
attribute \enum_value_0000 "NONE"
attribute \enum_value_1000 "is8B"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
wire width 4 \dec_sub26_ldst_len
+ attribute \enum_base_type "LDSTMode"
+ attribute \enum_value_00 "NONE"
+ attribute \enum_value_01 "update"
+ attribute \enum_value_10 "cix"
+ attribute \enum_value_11 "cx"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+ wire width 2 \dec_sub26_upd
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
wire width 2 \dec_sub26_cry_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub26_inv_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub26_inv_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub26_cry_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub26_br
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub26_sgn_ext
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 \dec_sub26_upd
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub26_rsrv
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub26_is_32b
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub26_sgn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub26_lk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub26_sgl_pipe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
wire width 8 \dec_sub26_asmcode
connect \cr_out \dec_sub26_cr_out
connect \rc_sel \dec_sub26_rc_sel
connect \ldst_len \dec_sub26_ldst_len
+ connect \upd \dec_sub26_upd
connect \cry_in \dec_sub26_cry_in
connect \inv_a \dec_sub26_inv_a
connect \inv_out \dec_sub26_inv_out
connect \cry_out \dec_sub26_cry_out
connect \br \dec_sub26_br
connect \sgn_ext \dec_sub26_sgn_ext
- connect \upd \dec_sub26_upd
connect \rsrv \dec_sub26_rsrv
connect \is_32b \dec_sub26_is_32b
connect \sgn \dec_sub26_sgn
connect \sgl_pipe \dec_sub26_sgl_pipe
connect \asmcode \dec_sub26_asmcode
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:229"
wire width 32 \dec_sub19_opcode_in
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_11100 "Z23"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
wire width 5 \dec_sub19_form
- attribute \enum_base_type "InternalOp"
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
+ attribute \enum_value_1001010 "OP_MTMSR"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
wire width 7 \dec_sub19_internal_op
attribute \enum_base_type "In1Sel"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "RC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
wire width 2 \dec_sub19_rc_sel
attribute \enum_base_type "LdstLen"
attribute \enum_value_0000 "NONE"
attribute \enum_value_1000 "is8B"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
wire width 4 \dec_sub19_ldst_len
+ attribute \enum_base_type "LDSTMode"
+ attribute \enum_value_00 "NONE"
+ attribute \enum_value_01 "update"
+ attribute \enum_value_10 "cix"
+ attribute \enum_value_11 "cx"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+ wire width 2 \dec_sub19_upd
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
wire width 2 \dec_sub19_cry_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub19_inv_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub19_inv_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub19_cry_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub19_br
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub19_sgn_ext
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 \dec_sub19_upd
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub19_rsrv
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub19_is_32b
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub19_sgn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub19_lk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub19_sgl_pipe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
wire width 8 \dec_sub19_asmcode
connect \cr_out \dec_sub19_cr_out
connect \rc_sel \dec_sub19_rc_sel
connect \ldst_len \dec_sub19_ldst_len
+ connect \upd \dec_sub19_upd
connect \cry_in \dec_sub19_cry_in
connect \inv_a \dec_sub19_inv_a
connect \inv_out \dec_sub19_inv_out
connect \cry_out \dec_sub19_cry_out
connect \br \dec_sub19_br
connect \sgn_ext \dec_sub19_sgn_ext
- connect \upd \dec_sub19_upd
connect \rsrv \dec_sub19_rsrv
connect \is_32b \dec_sub19_is_32b
connect \sgn \dec_sub19_sgn
connect \sgl_pipe \dec_sub19_sgl_pipe
connect \asmcode \dec_sub19_asmcode
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:229"
wire width 32 \dec_sub22_opcode_in
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_11100 "Z23"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
wire width 5 \dec_sub22_form
- attribute \enum_base_type "InternalOp"
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
+ attribute \enum_value_1001010 "OP_MTMSR"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
wire width 7 \dec_sub22_internal_op
attribute \enum_base_type "In1Sel"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "RC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
wire width 2 \dec_sub22_rc_sel
attribute \enum_base_type "LdstLen"
attribute \enum_value_0000 "NONE"
attribute \enum_value_1000 "is8B"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
wire width 4 \dec_sub22_ldst_len
+ attribute \enum_base_type "LDSTMode"
+ attribute \enum_value_00 "NONE"
+ attribute \enum_value_01 "update"
+ attribute \enum_value_10 "cix"
+ attribute \enum_value_11 "cx"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+ wire width 2 \dec_sub22_upd
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
wire width 2 \dec_sub22_cry_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub22_inv_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub22_inv_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub22_cry_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub22_br
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub22_sgn_ext
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 \dec_sub22_upd
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub22_rsrv
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub22_is_32b
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub22_sgn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub22_lk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub22_sgl_pipe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
wire width 8 \dec_sub22_asmcode
connect \cr_out \dec_sub22_cr_out
connect \rc_sel \dec_sub22_rc_sel
connect \ldst_len \dec_sub22_ldst_len
+ connect \upd \dec_sub22_upd
connect \cry_in \dec_sub22_cry_in
connect \inv_a \dec_sub22_inv_a
connect \inv_out \dec_sub22_inv_out
connect \cry_out \dec_sub22_cry_out
connect \br \dec_sub22_br
connect \sgn_ext \dec_sub22_sgn_ext
- connect \upd \dec_sub22_upd
connect \rsrv \dec_sub22_rsrv
connect \is_32b \dec_sub22_is_32b
connect \sgn \dec_sub22_sgn
connect \sgl_pipe \dec_sub22_sgl_pipe
connect \asmcode \dec_sub22_asmcode
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:229"
wire width 32 \dec_sub9_opcode_in
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_11100 "Z23"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
wire width 5 \dec_sub9_form
- attribute \enum_base_type "InternalOp"
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
+ attribute \enum_value_1001010 "OP_MTMSR"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
wire width 7 \dec_sub9_internal_op
attribute \enum_base_type "In1Sel"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "RC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
wire width 2 \dec_sub9_rc_sel
attribute \enum_base_type "LdstLen"
attribute \enum_value_0000 "NONE"
attribute \enum_value_1000 "is8B"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
wire width 4 \dec_sub9_ldst_len
+ attribute \enum_base_type "LDSTMode"
+ attribute \enum_value_00 "NONE"
+ attribute \enum_value_01 "update"
+ attribute \enum_value_10 "cix"
+ attribute \enum_value_11 "cx"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+ wire width 2 \dec_sub9_upd
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
wire width 2 \dec_sub9_cry_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub9_inv_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub9_inv_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub9_cry_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub9_br
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub9_sgn_ext
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 \dec_sub9_upd
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub9_rsrv
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub9_is_32b
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub9_sgn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub9_lk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub9_sgl_pipe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
wire width 8 \dec_sub9_asmcode
connect \cr_out \dec_sub9_cr_out
connect \rc_sel \dec_sub9_rc_sel
connect \ldst_len \dec_sub9_ldst_len
+ connect \upd \dec_sub9_upd
connect \cry_in \dec_sub9_cry_in
connect \inv_a \dec_sub9_inv_a
connect \inv_out \dec_sub9_inv_out
connect \cry_out \dec_sub9_cry_out
connect \br \dec_sub9_br
connect \sgn_ext \dec_sub9_sgn_ext
- connect \upd \dec_sub9_upd
connect \rsrv \dec_sub9_rsrv
connect \is_32b \dec_sub9_is_32b
connect \sgn \dec_sub9_sgn
connect \sgl_pipe \dec_sub9_sgl_pipe
connect \asmcode \dec_sub9_asmcode
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:229"
wire width 32 \dec_sub11_opcode_in
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_11100 "Z23"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
wire width 5 \dec_sub11_form
- attribute \enum_base_type "InternalOp"
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
+ attribute \enum_value_1001010 "OP_MTMSR"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
wire width 7 \dec_sub11_internal_op
attribute \enum_base_type "In1Sel"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "RC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
wire width 2 \dec_sub11_rc_sel
attribute \enum_base_type "LdstLen"
attribute \enum_value_0000 "NONE"
attribute \enum_value_1000 "is8B"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
wire width 4 \dec_sub11_ldst_len
+ attribute \enum_base_type "LDSTMode"
+ attribute \enum_value_00 "NONE"
+ attribute \enum_value_01 "update"
+ attribute \enum_value_10 "cix"
+ attribute \enum_value_11 "cx"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+ wire width 2 \dec_sub11_upd
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
wire width 2 \dec_sub11_cry_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub11_inv_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub11_inv_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub11_cry_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub11_br
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub11_sgn_ext
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 \dec_sub11_upd
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub11_rsrv
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub11_is_32b
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub11_sgn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub11_lk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub11_sgl_pipe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
wire width 8 \dec_sub11_asmcode
connect \cr_out \dec_sub11_cr_out
connect \rc_sel \dec_sub11_rc_sel
connect \ldst_len \dec_sub11_ldst_len
+ connect \upd \dec_sub11_upd
connect \cry_in \dec_sub11_cry_in
connect \inv_a \dec_sub11_inv_a
connect \inv_out \dec_sub11_inv_out
connect \cry_out \dec_sub11_cry_out
connect \br \dec_sub11_br
connect \sgn_ext \dec_sub11_sgn_ext
- connect \upd \dec_sub11_upd
connect \rsrv \dec_sub11_rsrv
connect \is_32b \dec_sub11_is_32b
connect \sgn \dec_sub11_sgn
connect \sgl_pipe \dec_sub11_sgl_pipe
connect \asmcode \dec_sub11_asmcode
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:229"
wire width 32 \dec_sub27_opcode_in
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_11100 "Z23"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
wire width 5 \dec_sub27_form
- attribute \enum_base_type "InternalOp"
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
+ attribute \enum_value_1001010 "OP_MTMSR"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
wire width 7 \dec_sub27_internal_op
attribute \enum_base_type "In1Sel"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "RC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
wire width 2 \dec_sub27_rc_sel
attribute \enum_base_type "LdstLen"
attribute \enum_value_0000 "NONE"
attribute \enum_value_1000 "is8B"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
wire width 4 \dec_sub27_ldst_len
+ attribute \enum_base_type "LDSTMode"
+ attribute \enum_value_00 "NONE"
+ attribute \enum_value_01 "update"
+ attribute \enum_value_10 "cix"
+ attribute \enum_value_11 "cx"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+ wire width 2 \dec_sub27_upd
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
wire width 2 \dec_sub27_cry_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub27_inv_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub27_inv_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub27_cry_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub27_br
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub27_sgn_ext
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 \dec_sub27_upd
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub27_rsrv
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub27_is_32b
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub27_sgn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub27_lk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub27_sgl_pipe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
wire width 8 \dec_sub27_asmcode
connect \cr_out \dec_sub27_cr_out
connect \rc_sel \dec_sub27_rc_sel
connect \ldst_len \dec_sub27_ldst_len
+ connect \upd \dec_sub27_upd
connect \cry_in \dec_sub27_cry_in
connect \inv_a \dec_sub27_inv_a
connect \inv_out \dec_sub27_inv_out
connect \cry_out \dec_sub27_cry_out
connect \br \dec_sub27_br
connect \sgn_ext \dec_sub27_sgn_ext
- connect \upd \dec_sub27_upd
connect \rsrv \dec_sub27_rsrv
connect \is_32b \dec_sub27_is_32b
connect \sgn \dec_sub27_sgn
connect \sgl_pipe \dec_sub27_sgl_pipe
connect \asmcode \dec_sub27_asmcode
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:229"
wire width 32 \dec_sub15_opcode_in
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_11100 "Z23"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
wire width 5 \dec_sub15_form
- attribute \enum_base_type "InternalOp"
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
+ attribute \enum_value_1001010 "OP_MTMSR"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
wire width 7 \dec_sub15_internal_op
attribute \enum_base_type "In1Sel"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "RC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
wire width 2 \dec_sub15_rc_sel
attribute \enum_base_type "LdstLen"
attribute \enum_value_0000 "NONE"
attribute \enum_value_1000 "is8B"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
wire width 4 \dec_sub15_ldst_len
+ attribute \enum_base_type "LDSTMode"
+ attribute \enum_value_00 "NONE"
+ attribute \enum_value_01 "update"
+ attribute \enum_value_10 "cix"
+ attribute \enum_value_11 "cx"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+ wire width 2 \dec_sub15_upd
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
wire width 2 \dec_sub15_cry_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub15_inv_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub15_inv_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub15_cry_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub15_br
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub15_sgn_ext
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 \dec_sub15_upd
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub15_rsrv
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub15_is_32b
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub15_sgn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub15_lk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub15_sgl_pipe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
wire width 8 \dec_sub15_asmcode
connect \cr_out \dec_sub15_cr_out
connect \rc_sel \dec_sub15_rc_sel
connect \ldst_len \dec_sub15_ldst_len
+ connect \upd \dec_sub15_upd
connect \cry_in \dec_sub15_cry_in
connect \inv_a \dec_sub15_inv_a
connect \inv_out \dec_sub15_inv_out
connect \cry_out \dec_sub15_cry_out
connect \br \dec_sub15_br
connect \sgn_ext \dec_sub15_sgn_ext
- connect \upd \dec_sub15_upd
connect \rsrv \dec_sub15_rsrv
connect \is_32b \dec_sub15_is_32b
connect \sgn \dec_sub15_sgn
connect \sgl_pipe \dec_sub15_sgl_pipe
connect \asmcode \dec_sub15_asmcode
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:229"
wire width 32 \dec_sub20_opcode_in
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_11100 "Z23"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
wire width 5 \dec_sub20_form
- attribute \enum_base_type "InternalOp"
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
+ attribute \enum_value_1001010 "OP_MTMSR"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
wire width 7 \dec_sub20_internal_op
attribute \enum_base_type "In1Sel"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "RC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
wire width 2 \dec_sub20_rc_sel
attribute \enum_base_type "LdstLen"
attribute \enum_value_0000 "NONE"
attribute \enum_value_1000 "is8B"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
wire width 4 \dec_sub20_ldst_len
+ attribute \enum_base_type "LDSTMode"
+ attribute \enum_value_00 "NONE"
+ attribute \enum_value_01 "update"
+ attribute \enum_value_10 "cix"
+ attribute \enum_value_11 "cx"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+ wire width 2 \dec_sub20_upd
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
wire width 2 \dec_sub20_cry_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub20_inv_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub20_inv_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub20_cry_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub20_br
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub20_sgn_ext
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 \dec_sub20_upd
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub20_rsrv
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub20_is_32b
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub20_sgn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub20_lk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub20_sgl_pipe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
wire width 8 \dec_sub20_asmcode
connect \cr_out \dec_sub20_cr_out
connect \rc_sel \dec_sub20_rc_sel
connect \ldst_len \dec_sub20_ldst_len
+ connect \upd \dec_sub20_upd
connect \cry_in \dec_sub20_cry_in
connect \inv_a \dec_sub20_inv_a
connect \inv_out \dec_sub20_inv_out
connect \cry_out \dec_sub20_cry_out
connect \br \dec_sub20_br
connect \sgn_ext \dec_sub20_sgn_ext
- connect \upd \dec_sub20_upd
connect \rsrv \dec_sub20_rsrv
connect \is_32b \dec_sub20_is_32b
connect \sgn \dec_sub20_sgn
connect \sgl_pipe \dec_sub20_sgl_pipe
connect \asmcode \dec_sub20_asmcode
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219"
- wire width 32 \dec_sub23_opcode_in
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:229"
+ wire width 32 \dec_sub21_opcode_in
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00000000010 "ALU"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119"
- wire width 11 \dec_sub23_function_unit
+ wire width 11 \dec_sub21_function_unit
attribute \enum_base_type "Form"
attribute \enum_value_00000 "NONE"
attribute \enum_value_00001 "I"
attribute \enum_value_11011 "Z22"
attribute \enum_value_11100 "Z23"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
- wire width 5 \dec_sub23_form
- attribute \enum_base_type "InternalOp"
+ wire width 5 \dec_sub21_form
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
+ attribute \enum_value_1001010 "OP_MTMSR"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
- wire width 7 \dec_sub23_internal_op
+ wire width 7 \dec_sub21_internal_op
attribute \enum_base_type "In1Sel"
attribute \enum_value_000 "NONE"
attribute \enum_value_001 "RA"
attribute \enum_value_011 "SPR"
attribute \enum_value_100 "RS"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
- wire width 3 \dec_sub23_in1_sel
+ wire width 3 \dec_sub21_in1_sel
attribute \enum_base_type "In2Sel"
attribute \enum_value_0000 "NONE"
attribute \enum_value_0001 "RB"
attribute \enum_value_1100 "SPR"
attribute \enum_value_1101 "RS"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
- wire width 4 \dec_sub23_in2_sel
+ wire width 4 \dec_sub21_in2_sel
attribute \enum_base_type "In3Sel"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "RS"
attribute \enum_value_10 "RB"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
- wire width 2 \dec_sub23_in3_sel
+ wire width 2 \dec_sub21_in3_sel
attribute \enum_base_type "OutSel"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "RT"
attribute \enum_value_10 "RA"
attribute \enum_value_11 "SPR"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
- wire width 2 \dec_sub23_out_sel
+ wire width 2 \dec_sub21_out_sel
attribute \enum_base_type "CRInSel"
attribute \enum_value_000 "NONE"
attribute \enum_value_001 "CR0"
attribute \enum_value_101 "BC"
attribute \enum_value_110 "WHOLE_REG"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
- wire width 3 \dec_sub23_cr_in
+ wire width 3 \dec_sub21_cr_in
attribute \enum_base_type "CROutSel"
attribute \enum_value_000 "NONE"
attribute \enum_value_001 "CR0"
attribute \enum_value_011 "BT"
attribute \enum_value_100 "WHOLE_REG"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
- wire width 3 \dec_sub23_cr_out
+ wire width 3 \dec_sub21_cr_out
attribute \enum_base_type "RC"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "RC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
- wire width 2 \dec_sub23_rc_sel
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
+ wire width 2 \dec_sub21_rc_sel
attribute \enum_base_type "LdstLen"
attribute \enum_value_0000 "NONE"
attribute \enum_value_0001 "is1B"
attribute \enum_value_0100 "is4B"
attribute \enum_value_1000 "is8B"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
- wire width 4 \dec_sub23_ldst_len
+ wire width 4 \dec_sub21_ldst_len
+ attribute \enum_base_type "LDSTMode"
+ attribute \enum_value_00 "NONE"
+ attribute \enum_value_01 "update"
+ attribute \enum_value_10 "cix"
+ attribute \enum_value_11 "cx"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+ wire width 2 \dec_sub21_upd
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
- wire width 2 \dec_sub23_cry_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 \dec_sub23_inv_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 \dec_sub23_inv_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 \dec_sub23_cry_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 \dec_sub23_br
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 \dec_sub23_sgn_ext
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 \dec_sub23_upd
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 \dec_sub23_rsrv
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 \dec_sub23_is_32b
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 \dec_sub23_sgn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 \dec_sub23_lk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 \dec_sub23_sgl_pipe
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
+ wire width 2 \dec_sub21_cry_in
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 \dec_sub21_inv_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 \dec_sub21_inv_out
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 \dec_sub21_cry_out
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 \dec_sub21_br
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 \dec_sub21_sgn_ext
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 \dec_sub21_rsrv
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 \dec_sub21_is_32b
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 \dec_sub21_sgn
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 \dec_sub21_lk
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 \dec_sub21_sgl_pipe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
- wire width 8 \dec_sub23_asmcode
- cell \dec_sub23 \dec_sub23
- connect \opcode_in \dec_sub23_opcode_in
- connect \function_unit \dec_sub23_function_unit
- connect \form \dec_sub23_form
- connect \internal_op \dec_sub23_internal_op
- connect \in1_sel \dec_sub23_in1_sel
- connect \in2_sel \dec_sub23_in2_sel
- connect \in3_sel \dec_sub23_in3_sel
- connect \out_sel \dec_sub23_out_sel
- connect \cr_in \dec_sub23_cr_in
- connect \cr_out \dec_sub23_cr_out
- connect \rc_sel \dec_sub23_rc_sel
- connect \ldst_len \dec_sub23_ldst_len
- connect \cry_in \dec_sub23_cry_in
- connect \inv_a \dec_sub23_inv_a
- connect \inv_out \dec_sub23_inv_out
- connect \cry_out \dec_sub23_cry_out
- connect \br \dec_sub23_br
- connect \sgn_ext \dec_sub23_sgn_ext
- connect \upd \dec_sub23_upd
- connect \rsrv \dec_sub23_rsrv
- connect \is_32b \dec_sub23_is_32b
- connect \sgn \dec_sub23_sgn
- connect \lk \dec_sub23_lk
- connect \sgl_pipe \dec_sub23_sgl_pipe
- connect \asmcode \dec_sub23_asmcode
+ wire width 8 \dec_sub21_asmcode
+ cell \dec_sub21 \dec_sub21
+ connect \opcode_in \dec_sub21_opcode_in
+ connect \function_unit \dec_sub21_function_unit
+ connect \form \dec_sub21_form
+ connect \internal_op \dec_sub21_internal_op
+ connect \in1_sel \dec_sub21_in1_sel
+ connect \in2_sel \dec_sub21_in2_sel
+ connect \in3_sel \dec_sub21_in3_sel
+ connect \out_sel \dec_sub21_out_sel
+ connect \cr_in \dec_sub21_cr_in
+ connect \cr_out \dec_sub21_cr_out
+ connect \rc_sel \dec_sub21_rc_sel
+ connect \ldst_len \dec_sub21_ldst_len
+ connect \upd \dec_sub21_upd
+ connect \cry_in \dec_sub21_cry_in
+ connect \inv_a \dec_sub21_inv_a
+ connect \inv_out \dec_sub21_inv_out
+ connect \cry_out \dec_sub21_cry_out
+ connect \br \dec_sub21_br
+ connect \sgn_ext \dec_sub21_sgn_ext
+ connect \rsrv \dec_sub21_rsrv
+ connect \is_32b \dec_sub21_is_32b
+ connect \sgn \dec_sub21_sgn
+ connect \lk \dec_sub21_lk
+ connect \sgl_pipe \dec_sub21_sgl_pipe
+ connect \asmcode \dec_sub21_asmcode
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219"
- wire width 32 \dec_sub21_opcode_in
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:229"
+ wire width 32 \dec_sub23_opcode_in
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00000000010 "ALU"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119"
- wire width 11 \dec_sub21_function_unit
+ wire width 11 \dec_sub23_function_unit
attribute \enum_base_type "Form"
attribute \enum_value_00000 "NONE"
attribute \enum_value_00001 "I"
attribute \enum_value_11011 "Z22"
attribute \enum_value_11100 "Z23"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
- wire width 5 \dec_sub21_form
- attribute \enum_base_type "InternalOp"
+ wire width 5 \dec_sub23_form
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
+ attribute \enum_value_1001010 "OP_MTMSR"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
- wire width 7 \dec_sub21_internal_op
+ wire width 7 \dec_sub23_internal_op
attribute \enum_base_type "In1Sel"
attribute \enum_value_000 "NONE"
attribute \enum_value_001 "RA"
attribute \enum_value_011 "SPR"
attribute \enum_value_100 "RS"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
- wire width 3 \dec_sub21_in1_sel
+ wire width 3 \dec_sub23_in1_sel
attribute \enum_base_type "In2Sel"
attribute \enum_value_0000 "NONE"
attribute \enum_value_0001 "RB"
attribute \enum_value_1100 "SPR"
attribute \enum_value_1101 "RS"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
- wire width 4 \dec_sub21_in2_sel
+ wire width 4 \dec_sub23_in2_sel
attribute \enum_base_type "In3Sel"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "RS"
attribute \enum_value_10 "RB"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
- wire width 2 \dec_sub21_in3_sel
+ wire width 2 \dec_sub23_in3_sel
attribute \enum_base_type "OutSel"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "RT"
attribute \enum_value_10 "RA"
attribute \enum_value_11 "SPR"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
- wire width 2 \dec_sub21_out_sel
+ wire width 2 \dec_sub23_out_sel
attribute \enum_base_type "CRInSel"
attribute \enum_value_000 "NONE"
attribute \enum_value_001 "CR0"
attribute \enum_value_101 "BC"
attribute \enum_value_110 "WHOLE_REG"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
- wire width 3 \dec_sub21_cr_in
+ wire width 3 \dec_sub23_cr_in
attribute \enum_base_type "CROutSel"
attribute \enum_value_000 "NONE"
attribute \enum_value_001 "CR0"
attribute \enum_value_011 "BT"
attribute \enum_value_100 "WHOLE_REG"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
- wire width 3 \dec_sub21_cr_out
+ wire width 3 \dec_sub23_cr_out
attribute \enum_base_type "RC"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "RC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
- wire width 2 \dec_sub21_rc_sel
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
+ wire width 2 \dec_sub23_rc_sel
attribute \enum_base_type "LdstLen"
attribute \enum_value_0000 "NONE"
attribute \enum_value_0001 "is1B"
attribute \enum_value_0100 "is4B"
attribute \enum_value_1000 "is8B"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
- wire width 4 \dec_sub21_ldst_len
+ wire width 4 \dec_sub23_ldst_len
+ attribute \enum_base_type "LDSTMode"
+ attribute \enum_value_00 "NONE"
+ attribute \enum_value_01 "update"
+ attribute \enum_value_10 "cix"
+ attribute \enum_value_11 "cx"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+ wire width 2 \dec_sub23_upd
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
- wire width 2 \dec_sub21_cry_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 \dec_sub21_inv_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 \dec_sub21_inv_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 \dec_sub21_cry_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 \dec_sub21_br
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 \dec_sub21_sgn_ext
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 \dec_sub21_upd
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 \dec_sub21_rsrv
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 \dec_sub21_is_32b
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 \dec_sub21_sgn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 \dec_sub21_lk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 \dec_sub21_sgl_pipe
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
+ wire width 2 \dec_sub23_cry_in
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 \dec_sub23_inv_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 \dec_sub23_inv_out
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 \dec_sub23_cry_out
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 \dec_sub23_br
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 \dec_sub23_sgn_ext
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 \dec_sub23_rsrv
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 \dec_sub23_is_32b
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 \dec_sub23_sgn
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 \dec_sub23_lk
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 \dec_sub23_sgl_pipe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
- wire width 8 \dec_sub21_asmcode
- cell \dec_sub21 \dec_sub21
- connect \opcode_in \dec_sub21_opcode_in
- connect \function_unit \dec_sub21_function_unit
- connect \form \dec_sub21_form
- connect \internal_op \dec_sub21_internal_op
- connect \in1_sel \dec_sub21_in1_sel
- connect \in2_sel \dec_sub21_in2_sel
- connect \in3_sel \dec_sub21_in3_sel
- connect \out_sel \dec_sub21_out_sel
- connect \cr_in \dec_sub21_cr_in
- connect \cr_out \dec_sub21_cr_out
- connect \rc_sel \dec_sub21_rc_sel
- connect \ldst_len \dec_sub21_ldst_len
- connect \cry_in \dec_sub21_cry_in
- connect \inv_a \dec_sub21_inv_a
- connect \inv_out \dec_sub21_inv_out
- connect \cry_out \dec_sub21_cry_out
- connect \br \dec_sub21_br
- connect \sgn_ext \dec_sub21_sgn_ext
- connect \upd \dec_sub21_upd
- connect \rsrv \dec_sub21_rsrv
- connect \is_32b \dec_sub21_is_32b
- connect \sgn \dec_sub21_sgn
- connect \lk \dec_sub21_lk
- connect \sgl_pipe \dec_sub21_sgl_pipe
- connect \asmcode \dec_sub21_asmcode
+ wire width 8 \dec_sub23_asmcode
+ cell \dec_sub23 \dec_sub23
+ connect \opcode_in \dec_sub23_opcode_in
+ connect \function_unit \dec_sub23_function_unit
+ connect \form \dec_sub23_form
+ connect \internal_op \dec_sub23_internal_op
+ connect \in1_sel \dec_sub23_in1_sel
+ connect \in2_sel \dec_sub23_in2_sel
+ connect \in3_sel \dec_sub23_in3_sel
+ connect \out_sel \dec_sub23_out_sel
+ connect \cr_in \dec_sub23_cr_in
+ connect \cr_out \dec_sub23_cr_out
+ connect \rc_sel \dec_sub23_rc_sel
+ connect \ldst_len \dec_sub23_ldst_len
+ connect \upd \dec_sub23_upd
+ connect \cry_in \dec_sub23_cry_in
+ connect \inv_a \dec_sub23_inv_a
+ connect \inv_out \dec_sub23_inv_out
+ connect \cry_out \dec_sub23_cry_out
+ connect \br \dec_sub23_br
+ connect \sgn_ext \dec_sub23_sgn_ext
+ connect \rsrv \dec_sub23_rsrv
+ connect \is_32b \dec_sub23_is_32b
+ connect \sgn \dec_sub23_sgn
+ connect \lk \dec_sub23_lk
+ connect \sgl_pipe \dec_sub23_sgl_pipe
+ connect \asmcode \dec_sub23_asmcode
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:229"
wire width 32 \dec_sub16_opcode_in
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_11100 "Z23"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
wire width 5 \dec_sub16_form
- attribute \enum_base_type "InternalOp"
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
+ attribute \enum_value_1001010 "OP_MTMSR"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
wire width 7 \dec_sub16_internal_op
attribute \enum_base_type "In1Sel"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "RC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
wire width 2 \dec_sub16_rc_sel
attribute \enum_base_type "LdstLen"
attribute \enum_value_0000 "NONE"
attribute \enum_value_1000 "is8B"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
wire width 4 \dec_sub16_ldst_len
+ attribute \enum_base_type "LDSTMode"
+ attribute \enum_value_00 "NONE"
+ attribute \enum_value_01 "update"
+ attribute \enum_value_10 "cix"
+ attribute \enum_value_11 "cx"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+ wire width 2 \dec_sub16_upd
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
wire width 2 \dec_sub16_cry_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub16_inv_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub16_inv_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub16_cry_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub16_br
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub16_sgn_ext
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 \dec_sub16_upd
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub16_rsrv
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub16_is_32b
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub16_sgn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub16_lk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub16_sgl_pipe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
wire width 8 \dec_sub16_asmcode
connect \cr_out \dec_sub16_cr_out
connect \rc_sel \dec_sub16_rc_sel
connect \ldst_len \dec_sub16_ldst_len
+ connect \upd \dec_sub16_upd
connect \cry_in \dec_sub16_cry_in
connect \inv_a \dec_sub16_inv_a
connect \inv_out \dec_sub16_inv_out
connect \cry_out \dec_sub16_cry_out
connect \br \dec_sub16_br
connect \sgn_ext \dec_sub16_sgn_ext
- connect \upd \dec_sub16_upd
connect \rsrv \dec_sub16_rsrv
connect \is_32b \dec_sub16_is_32b
connect \sgn \dec_sub16_sgn
connect \sgl_pipe \dec_sub16_sgl_pipe
connect \asmcode \dec_sub16_asmcode
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:229"
wire width 32 \dec_sub18_opcode_in
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_11100 "Z23"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
wire width 5 \dec_sub18_form
- attribute \enum_base_type "InternalOp"
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
+ attribute \enum_value_1001010 "OP_MTMSR"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
wire width 7 \dec_sub18_internal_op
attribute \enum_base_type "In1Sel"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "RC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
wire width 2 \dec_sub18_rc_sel
attribute \enum_base_type "LdstLen"
attribute \enum_value_0000 "NONE"
attribute \enum_value_1000 "is8B"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
wire width 4 \dec_sub18_ldst_len
+ attribute \enum_base_type "LDSTMode"
+ attribute \enum_value_00 "NONE"
+ attribute \enum_value_01 "update"
+ attribute \enum_value_10 "cix"
+ attribute \enum_value_11 "cx"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+ wire width 2 \dec_sub18_upd
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
wire width 2 \dec_sub18_cry_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub18_inv_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub18_inv_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub18_cry_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub18_br
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub18_sgn_ext
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 \dec_sub18_upd
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub18_rsrv
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub18_is_32b
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub18_sgn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub18_lk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub18_sgl_pipe
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
+ wire width 8 \dec_sub18_asmcode
cell \dec_sub18 \dec_sub18
connect \opcode_in \dec_sub18_opcode_in
connect \function_unit \dec_sub18_function_unit
connect \cr_out \dec_sub18_cr_out
connect \rc_sel \dec_sub18_rc_sel
connect \ldst_len \dec_sub18_ldst_len
+ connect \upd \dec_sub18_upd
connect \cry_in \dec_sub18_cry_in
connect \inv_a \dec_sub18_inv_a
connect \inv_out \dec_sub18_inv_out
connect \cry_out \dec_sub18_cry_out
connect \br \dec_sub18_br
connect \sgn_ext \dec_sub18_sgn_ext
- connect \upd \dec_sub18_upd
connect \rsrv \dec_sub18_rsrv
connect \is_32b \dec_sub18_is_32b
connect \sgn \dec_sub18_sgn
connect \lk \dec_sub18_lk
connect \sgl_pipe \dec_sub18_sgl_pipe
+ connect \asmcode \dec_sub18_asmcode
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:229"
wire width 32 \dec_sub8_opcode_in
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_11100 "Z23"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
wire width 5 \dec_sub8_form
- attribute \enum_base_type "InternalOp"
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
+ attribute \enum_value_1001010 "OP_MTMSR"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
wire width 7 \dec_sub8_internal_op
attribute \enum_base_type "In1Sel"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "RC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
wire width 2 \dec_sub8_rc_sel
attribute \enum_base_type "LdstLen"
attribute \enum_value_0000 "NONE"
attribute \enum_value_1000 "is8B"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
wire width 4 \dec_sub8_ldst_len
+ attribute \enum_base_type "LDSTMode"
+ attribute \enum_value_00 "NONE"
+ attribute \enum_value_01 "update"
+ attribute \enum_value_10 "cix"
+ attribute \enum_value_11 "cx"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+ wire width 2 \dec_sub8_upd
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
wire width 2 \dec_sub8_cry_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub8_inv_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub8_inv_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub8_cry_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub8_br
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub8_sgn_ext
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 \dec_sub8_upd
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub8_rsrv
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub8_is_32b
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub8_sgn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub8_lk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub8_sgl_pipe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
wire width 8 \dec_sub8_asmcode
connect \cr_out \dec_sub8_cr_out
connect \rc_sel \dec_sub8_rc_sel
connect \ldst_len \dec_sub8_ldst_len
+ connect \upd \dec_sub8_upd
connect \cry_in \dec_sub8_cry_in
connect \inv_a \dec_sub8_inv_a
connect \inv_out \dec_sub8_inv_out
connect \cry_out \dec_sub8_cry_out
connect \br \dec_sub8_br
connect \sgn_ext \dec_sub8_sgn_ext
- connect \upd \dec_sub8_upd
connect \rsrv \dec_sub8_rsrv
connect \is_32b \dec_sub8_is_32b
connect \sgn \dec_sub8_sgn
connect \sgl_pipe \dec_sub8_sgl_pipe
connect \asmcode \dec_sub8_asmcode
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:229"
wire width 32 \dec_sub24_opcode_in
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_11100 "Z23"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
wire width 5 \dec_sub24_form
- attribute \enum_base_type "InternalOp"
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
+ attribute \enum_value_1001010 "OP_MTMSR"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
wire width 7 \dec_sub24_internal_op
attribute \enum_base_type "In1Sel"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "RC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
wire width 2 \dec_sub24_rc_sel
attribute \enum_base_type "LdstLen"
attribute \enum_value_0000 "NONE"
attribute \enum_value_1000 "is8B"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
wire width 4 \dec_sub24_ldst_len
+ attribute \enum_base_type "LDSTMode"
+ attribute \enum_value_00 "NONE"
+ attribute \enum_value_01 "update"
+ attribute \enum_value_10 "cix"
+ attribute \enum_value_11 "cx"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+ wire width 2 \dec_sub24_upd
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
wire width 2 \dec_sub24_cry_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub24_inv_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub24_inv_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub24_cry_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub24_br
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub24_sgn_ext
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 \dec_sub24_upd
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub24_rsrv
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub24_is_32b
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub24_sgn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub24_lk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub24_sgl_pipe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
wire width 8 \dec_sub24_asmcode
connect \cr_out \dec_sub24_cr_out
connect \rc_sel \dec_sub24_rc_sel
connect \ldst_len \dec_sub24_ldst_len
+ connect \upd \dec_sub24_upd
connect \cry_in \dec_sub24_cry_in
connect \inv_a \dec_sub24_inv_a
connect \inv_out \dec_sub24_inv_out
connect \cry_out \dec_sub24_cry_out
connect \br \dec_sub24_br
connect \sgn_ext \dec_sub24_sgn_ext
- connect \upd \dec_sub24_upd
connect \rsrv \dec_sub24_rsrv
connect \is_32b \dec_sub24_is_32b
connect \sgn \dec_sub24_sgn
connect \sgl_pipe \dec_sub24_sgl_pipe
connect \asmcode \dec_sub24_asmcode
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:229"
wire width 32 \dec_sub4_opcode_in
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_11100 "Z23"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
wire width 5 \dec_sub4_form
- attribute \enum_base_type "InternalOp"
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
+ attribute \enum_value_1001010 "OP_MTMSR"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
wire width 7 \dec_sub4_internal_op
attribute \enum_base_type "In1Sel"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "RC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
wire width 2 \dec_sub4_rc_sel
attribute \enum_base_type "LdstLen"
attribute \enum_value_0000 "NONE"
attribute \enum_value_1000 "is8B"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
wire width 4 \dec_sub4_ldst_len
+ attribute \enum_base_type "LDSTMode"
+ attribute \enum_value_00 "NONE"
+ attribute \enum_value_01 "update"
+ attribute \enum_value_10 "cix"
+ attribute \enum_value_11 "cx"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+ wire width 2 \dec_sub4_upd
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
wire width 2 \dec_sub4_cry_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub4_inv_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub4_inv_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub4_cry_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub4_br
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub4_sgn_ext
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 \dec_sub4_upd
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub4_rsrv
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub4_is_32b
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub4_sgn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub4_lk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec_sub4_sgl_pipe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
wire width 8 \dec_sub4_asmcode
connect \cr_out \dec_sub4_cr_out
connect \rc_sel \dec_sub4_rc_sel
connect \ldst_len \dec_sub4_ldst_len
+ connect \upd \dec_sub4_upd
connect \cry_in \dec_sub4_cry_in
connect \inv_a \dec_sub4_inv_a
connect \inv_out \dec_sub4_inv_out
connect \cry_out \dec_sub4_cry_out
connect \br \dec_sub4_br
connect \sgn_ext \dec_sub4_sgn_ext
- connect \upd \dec_sub4_upd
connect \rsrv \dec_sub4_rsrv
connect \is_32b \dec_sub4_is_32b
connect \sgn \dec_sub4_sgn
connect \sgl_pipe \dec_sub4_sgl_pipe
connect \asmcode \dec_sub4_asmcode
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:257"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:267"
wire width 10 \opcode_switch
process $group_0
assign \opcode_switch 10'0000000000
assign \opcode_switch \opcode_in [10:1]
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:261"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:271"
wire width 5 \opc_in
process $group_1
assign \opc_in 5'00000
sync init
end
process $group_13
- assign \dec_sub23_opcode_in 32'00000000000000000000000000000000
- assign \dec_sub23_opcode_in \opcode_in
+ assign \dec_sub21_opcode_in 32'00000000000000000000000000000000
+ assign \dec_sub21_opcode_in \opcode_in
sync init
end
process $group_14
- assign \dec_sub21_opcode_in 32'00000000000000000000000000000000
- assign \dec_sub21_opcode_in \opcode_in
+ assign \dec_sub23_opcode_in 32'00000000000000000000000000000000
+ assign \dec_sub23_opcode_in \opcode_in
sync init
end
process $group_15
end
process $group_20
assign \function_unit 11'00000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:264"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
switch \opc_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'01010
assign \function_unit \dec_sub10_function_unit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'11100
assign \function_unit \dec_sub28_function_unit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'00000
assign \function_unit \dec_sub0_function_unit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'11010
assign \function_unit \dec_sub26_function_unit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10011
assign \function_unit \dec_sub19_function_unit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10110
assign \function_unit \dec_sub22_function_unit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'01001
assign \function_unit \dec_sub9_function_unit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'01011
assign \function_unit \dec_sub11_function_unit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'11011
assign \function_unit \dec_sub27_function_unit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'01111
assign \function_unit \dec_sub15_function_unit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10100
assign \function_unit \dec_sub20_function_unit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
- case 5'10111
- assign \function_unit \dec_sub23_function_unit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10101
assign \function_unit \dec_sub21_function_unit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+ case 5'10111
+ assign \function_unit \dec_sub23_function_unit
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10000
assign \function_unit \dec_sub16_function_unit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10010
assign \function_unit \dec_sub18_function_unit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'01000
assign \function_unit \dec_sub8_function_unit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'11000
assign \function_unit \dec_sub24_function_unit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'00100
assign \function_unit \dec_sub4_function_unit
end
end
process $group_21
assign \form 5'00000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:264"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
switch \opc_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'01010
assign \form \dec_sub10_form
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'11100
assign \form \dec_sub28_form
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'00000
assign \form \dec_sub0_form
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'11010
assign \form \dec_sub26_form
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10011
assign \form \dec_sub19_form
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10110
assign \form \dec_sub22_form
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'01001
assign \form \dec_sub9_form
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'01011
assign \form \dec_sub11_form
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'11011
assign \form \dec_sub27_form
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'01111
assign \form \dec_sub15_form
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10100
assign \form \dec_sub20_form
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
- case 5'10111
- assign \form \dec_sub23_form
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10101
assign \form \dec_sub21_form
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+ case 5'10111
+ assign \form \dec_sub23_form
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10000
assign \form \dec_sub16_form
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10010
assign \form \dec_sub18_form
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'01000
assign \form \dec_sub8_form
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'11000
assign \form \dec_sub24_form
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'00100
assign \form \dec_sub4_form
end
end
process $group_22
assign \internal_op 7'0000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:264"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
switch \opc_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'01010
assign \internal_op \dec_sub10_internal_op
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'11100
assign \internal_op \dec_sub28_internal_op
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'00000
assign \internal_op \dec_sub0_internal_op
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'11010
assign \internal_op \dec_sub26_internal_op
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10011
assign \internal_op \dec_sub19_internal_op
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10110
assign \internal_op \dec_sub22_internal_op
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'01001
assign \internal_op \dec_sub9_internal_op
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'01011
assign \internal_op \dec_sub11_internal_op
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'11011
assign \internal_op \dec_sub27_internal_op
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'01111
assign \internal_op \dec_sub15_internal_op
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10100
assign \internal_op \dec_sub20_internal_op
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
- case 5'10111
- assign \internal_op \dec_sub23_internal_op
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10101
assign \internal_op \dec_sub21_internal_op
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+ case 5'10111
+ assign \internal_op \dec_sub23_internal_op
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10000
assign \internal_op \dec_sub16_internal_op
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10010
assign \internal_op \dec_sub18_internal_op
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'01000
assign \internal_op \dec_sub8_internal_op
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'11000
assign \internal_op \dec_sub24_internal_op
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'00100
assign \internal_op \dec_sub4_internal_op
end
end
process $group_23
assign \in1_sel 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:264"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
switch \opc_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'01010
assign \in1_sel \dec_sub10_in1_sel
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'11100
assign \in1_sel \dec_sub28_in1_sel
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'00000
assign \in1_sel \dec_sub0_in1_sel
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'11010
assign \in1_sel \dec_sub26_in1_sel
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10011
assign \in1_sel \dec_sub19_in1_sel
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10110
assign \in1_sel \dec_sub22_in1_sel
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'01001
assign \in1_sel \dec_sub9_in1_sel
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'01011
assign \in1_sel \dec_sub11_in1_sel
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'11011
assign \in1_sel \dec_sub27_in1_sel
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'01111
assign \in1_sel \dec_sub15_in1_sel
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10100
assign \in1_sel \dec_sub20_in1_sel
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
- case 5'10111
- assign \in1_sel \dec_sub23_in1_sel
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10101
assign \in1_sel \dec_sub21_in1_sel
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+ case 5'10111
+ assign \in1_sel \dec_sub23_in1_sel
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10000
assign \in1_sel \dec_sub16_in1_sel
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10010
assign \in1_sel \dec_sub18_in1_sel
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'01000
assign \in1_sel \dec_sub8_in1_sel
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'11000
assign \in1_sel \dec_sub24_in1_sel
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'00100
assign \in1_sel \dec_sub4_in1_sel
end
end
process $group_24
assign \in2_sel 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:264"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
switch \opc_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'01010
assign \in2_sel \dec_sub10_in2_sel
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'11100
assign \in2_sel \dec_sub28_in2_sel
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'00000
assign \in2_sel \dec_sub0_in2_sel
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'11010
assign \in2_sel \dec_sub26_in2_sel
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10011
assign \in2_sel \dec_sub19_in2_sel
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10110
assign \in2_sel \dec_sub22_in2_sel
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'01001
assign \in2_sel \dec_sub9_in2_sel
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'01011
assign \in2_sel \dec_sub11_in2_sel
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'11011
assign \in2_sel \dec_sub27_in2_sel
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'01111
assign \in2_sel \dec_sub15_in2_sel
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10100
assign \in2_sel \dec_sub20_in2_sel
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
- case 5'10111
- assign \in2_sel \dec_sub23_in2_sel
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10101
assign \in2_sel \dec_sub21_in2_sel
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+ case 5'10111
+ assign \in2_sel \dec_sub23_in2_sel
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10000
assign \in2_sel \dec_sub16_in2_sel
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10010
assign \in2_sel \dec_sub18_in2_sel
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'01000
assign \in2_sel \dec_sub8_in2_sel
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'11000
assign \in2_sel \dec_sub24_in2_sel
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'00100
assign \in2_sel \dec_sub4_in2_sel
end
end
process $group_25
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:264"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
switch \opc_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'01010
assign \in3_sel \dec_sub10_in3_sel
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'11100
assign \in3_sel \dec_sub28_in3_sel
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'00000
assign \in3_sel \dec_sub0_in3_sel
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'11010
assign \in3_sel \dec_sub26_in3_sel
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10011
assign \in3_sel \dec_sub19_in3_sel
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10110
assign \in3_sel \dec_sub22_in3_sel
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'01001
assign \in3_sel \dec_sub9_in3_sel
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'01011
assign \in3_sel \dec_sub11_in3_sel
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'11011
assign \in3_sel \dec_sub27_in3_sel
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'01111
assign \in3_sel \dec_sub15_in3_sel
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10100
assign \in3_sel \dec_sub20_in3_sel
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
- case 5'10111
- assign \in3_sel \dec_sub23_in3_sel
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10101
assign \in3_sel \dec_sub21_in3_sel
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+ case 5'10111
+ assign \in3_sel \dec_sub23_in3_sel
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10000
assign \in3_sel \dec_sub16_in3_sel
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10010
assign \in3_sel \dec_sub18_in3_sel
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'01000
assign \in3_sel \dec_sub8_in3_sel
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'11000
assign \in3_sel \dec_sub24_in3_sel
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'00100
assign \in3_sel \dec_sub4_in3_sel
end
end
process $group_26
assign \out_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:264"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
switch \opc_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'01010
assign \out_sel \dec_sub10_out_sel
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'11100
assign \out_sel \dec_sub28_out_sel
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'00000
assign \out_sel \dec_sub0_out_sel
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'11010
assign \out_sel \dec_sub26_out_sel
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10011
assign \out_sel \dec_sub19_out_sel
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10110
assign \out_sel \dec_sub22_out_sel
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'01001
assign \out_sel \dec_sub9_out_sel
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'01011
assign \out_sel \dec_sub11_out_sel
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'11011
assign \out_sel \dec_sub27_out_sel
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'01111
assign \out_sel \dec_sub15_out_sel
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10100
assign \out_sel \dec_sub20_out_sel
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
- case 5'10111
- assign \out_sel \dec_sub23_out_sel
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10101
assign \out_sel \dec_sub21_out_sel
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+ case 5'10111
+ assign \out_sel \dec_sub23_out_sel
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10000
assign \out_sel \dec_sub16_out_sel
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10010
assign \out_sel \dec_sub18_out_sel
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'01000
assign \out_sel \dec_sub8_out_sel
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'11000
assign \out_sel \dec_sub24_out_sel
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'00100
assign \out_sel \dec_sub4_out_sel
end
end
process $group_27
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:264"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
switch \opc_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'01010
assign \cr_in \dec_sub10_cr_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'11100
assign \cr_in \dec_sub28_cr_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'00000
assign \cr_in \dec_sub0_cr_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'11010
assign \cr_in \dec_sub26_cr_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10011
assign \cr_in \dec_sub19_cr_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10110
assign \cr_in \dec_sub22_cr_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'01001
assign \cr_in \dec_sub9_cr_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'01011
assign \cr_in \dec_sub11_cr_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'11011
assign \cr_in \dec_sub27_cr_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'01111
assign \cr_in \dec_sub15_cr_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10100
assign \cr_in \dec_sub20_cr_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
- case 5'10111
- assign \cr_in \dec_sub23_cr_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10101
assign \cr_in \dec_sub21_cr_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+ case 5'10111
+ assign \cr_in \dec_sub23_cr_in
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10000
assign \cr_in \dec_sub16_cr_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10010
assign \cr_in \dec_sub18_cr_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'01000
assign \cr_in \dec_sub8_cr_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'11000
assign \cr_in \dec_sub24_cr_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'00100
assign \cr_in \dec_sub4_cr_in
end
end
process $group_28
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:264"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
switch \opc_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'01010
assign \cr_out \dec_sub10_cr_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'11100
assign \cr_out \dec_sub28_cr_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'00000
assign \cr_out \dec_sub0_cr_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'11010
assign \cr_out \dec_sub26_cr_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10011
assign \cr_out \dec_sub19_cr_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10110
assign \cr_out \dec_sub22_cr_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'01001
assign \cr_out \dec_sub9_cr_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'01011
assign \cr_out \dec_sub11_cr_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'11011
assign \cr_out \dec_sub27_cr_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'01111
assign \cr_out \dec_sub15_cr_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10100
assign \cr_out \dec_sub20_cr_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
- case 5'10111
- assign \cr_out \dec_sub23_cr_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10101
assign \cr_out \dec_sub21_cr_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+ case 5'10111
+ assign \cr_out \dec_sub23_cr_out
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10000
assign \cr_out \dec_sub16_cr_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10010
assign \cr_out \dec_sub18_cr_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'01000
assign \cr_out \dec_sub8_cr_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'11000
assign \cr_out \dec_sub24_cr_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'00100
assign \cr_out \dec_sub4_cr_out
end
end
process $group_29
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:264"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
switch \opc_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'01010
assign \rc_sel \dec_sub10_rc_sel
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'11100
assign \rc_sel \dec_sub28_rc_sel
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'00000
assign \rc_sel \dec_sub0_rc_sel
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'11010
assign \rc_sel \dec_sub26_rc_sel
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10011
assign \rc_sel \dec_sub19_rc_sel
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10110
assign \rc_sel \dec_sub22_rc_sel
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'01001
assign \rc_sel \dec_sub9_rc_sel
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'01011
assign \rc_sel \dec_sub11_rc_sel
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'11011
assign \rc_sel \dec_sub27_rc_sel
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'01111
assign \rc_sel \dec_sub15_rc_sel
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10100
assign \rc_sel \dec_sub20_rc_sel
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
- case 5'10111
- assign \rc_sel \dec_sub23_rc_sel
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10101
assign \rc_sel \dec_sub21_rc_sel
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+ case 5'10111
+ assign \rc_sel \dec_sub23_rc_sel
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10000
assign \rc_sel \dec_sub16_rc_sel
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10010
assign \rc_sel \dec_sub18_rc_sel
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'01000
assign \rc_sel \dec_sub8_rc_sel
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'11000
assign \rc_sel \dec_sub24_rc_sel
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'00100
assign \rc_sel \dec_sub4_rc_sel
end
end
process $group_30
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:264"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
switch \opc_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'01010
assign \ldst_len \dec_sub10_ldst_len
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'11100
assign \ldst_len \dec_sub28_ldst_len
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'00000
assign \ldst_len \dec_sub0_ldst_len
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'11010
assign \ldst_len \dec_sub26_ldst_len
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10011
assign \ldst_len \dec_sub19_ldst_len
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10110
assign \ldst_len \dec_sub22_ldst_len
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'01001
assign \ldst_len \dec_sub9_ldst_len
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'01011
assign \ldst_len \dec_sub11_ldst_len
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'11011
assign \ldst_len \dec_sub27_ldst_len
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'01111
assign \ldst_len \dec_sub15_ldst_len
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10100
assign \ldst_len \dec_sub20_ldst_len
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
- case 5'10111
- assign \ldst_len \dec_sub23_ldst_len
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10101
assign \ldst_len \dec_sub21_ldst_len
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+ case 5'10111
+ assign \ldst_len \dec_sub23_ldst_len
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10000
assign \ldst_len \dec_sub16_ldst_len
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10010
assign \ldst_len \dec_sub18_ldst_len
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'01000
assign \ldst_len \dec_sub8_ldst_len
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'11000
assign \ldst_len \dec_sub24_ldst_len
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'00100
assign \ldst_len \dec_sub4_ldst_len
end
sync init
end
process $group_31
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ switch \opc_in
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+ case 5'01010
+ assign \upd \dec_sub10_upd
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+ case 5'11100
+ assign \upd \dec_sub28_upd
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+ case 5'00000
+ assign \upd \dec_sub0_upd
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+ case 5'11010
+ assign \upd \dec_sub26_upd
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+ case 5'10011
+ assign \upd \dec_sub19_upd
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+ case 5'10110
+ assign \upd \dec_sub22_upd
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+ case 5'01001
+ assign \upd \dec_sub9_upd
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+ case 5'01011
+ assign \upd \dec_sub11_upd
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+ case 5'11011
+ assign \upd \dec_sub27_upd
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+ case 5'01111
+ assign \upd \dec_sub15_upd
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+ case 5'10100
+ assign \upd \dec_sub20_upd
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+ case 5'10101
+ assign \upd \dec_sub21_upd
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+ case 5'10111
+ assign \upd \dec_sub23_upd
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+ case 5'10000
+ assign \upd \dec_sub16_upd
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+ case 5'10010
+ assign \upd \dec_sub18_upd
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+ case 5'01000
+ assign \upd \dec_sub8_upd
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+ case 5'11000
+ assign \upd \dec_sub24_upd
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+ case 5'00100
+ assign \upd \dec_sub4_upd
+ end
+ sync init
+ end
+ process $group_32
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:264"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
switch \opc_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'01010
assign \cry_in \dec_sub10_cry_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'11100
assign \cry_in \dec_sub28_cry_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'00000
assign \cry_in \dec_sub0_cry_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'11010
assign \cry_in \dec_sub26_cry_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10011
assign \cry_in \dec_sub19_cry_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10110
assign \cry_in \dec_sub22_cry_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'01001
assign \cry_in \dec_sub9_cry_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'01011
assign \cry_in \dec_sub11_cry_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'11011
assign \cry_in \dec_sub27_cry_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'01111
assign \cry_in \dec_sub15_cry_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10100
assign \cry_in \dec_sub20_cry_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
- case 5'10111
- assign \cry_in \dec_sub23_cry_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10101
assign \cry_in \dec_sub21_cry_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+ case 5'10111
+ assign \cry_in \dec_sub23_cry_in
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10000
assign \cry_in \dec_sub16_cry_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10010
assign \cry_in \dec_sub18_cry_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'01000
assign \cry_in \dec_sub8_cry_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'11000
assign \cry_in \dec_sub24_cry_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'00100
assign \cry_in \dec_sub4_cry_in
end
sync init
end
- process $group_32
+ process $group_33
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:264"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
switch \opc_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'01010
assign \inv_a \dec_sub10_inv_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'11100
assign \inv_a \dec_sub28_inv_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'00000
assign \inv_a \dec_sub0_inv_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'11010
assign \inv_a \dec_sub26_inv_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10011
assign \inv_a \dec_sub19_inv_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10110
assign \inv_a \dec_sub22_inv_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'01001
assign \inv_a \dec_sub9_inv_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'01011
assign \inv_a \dec_sub11_inv_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'11011
assign \inv_a \dec_sub27_inv_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'01111
assign \inv_a \dec_sub15_inv_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10100
assign \inv_a \dec_sub20_inv_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
- case 5'10111
- assign \inv_a \dec_sub23_inv_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10101
assign \inv_a \dec_sub21_inv_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+ case 5'10111
+ assign \inv_a \dec_sub23_inv_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10000
assign \inv_a \dec_sub16_inv_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10010
assign \inv_a \dec_sub18_inv_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'01000
assign \inv_a \dec_sub8_inv_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'11000
assign \inv_a \dec_sub24_inv_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'00100
assign \inv_a \dec_sub4_inv_a
end
sync init
end
- process $group_33
+ process $group_34
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:264"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
switch \opc_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'01010
assign \inv_out \dec_sub10_inv_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'11100
assign \inv_out \dec_sub28_inv_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'00000
assign \inv_out \dec_sub0_inv_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'11010
assign \inv_out \dec_sub26_inv_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10011
assign \inv_out \dec_sub19_inv_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10110
assign \inv_out \dec_sub22_inv_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'01001
assign \inv_out \dec_sub9_inv_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'01011
assign \inv_out \dec_sub11_inv_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'11011
assign \inv_out \dec_sub27_inv_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'01111
assign \inv_out \dec_sub15_inv_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10100
assign \inv_out \dec_sub20_inv_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
- case 5'10111
- assign \inv_out \dec_sub23_inv_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10101
assign \inv_out \dec_sub21_inv_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+ case 5'10111
+ assign \inv_out \dec_sub23_inv_out
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10000
assign \inv_out \dec_sub16_inv_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10010
assign \inv_out \dec_sub18_inv_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'01000
assign \inv_out \dec_sub8_inv_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'11000
assign \inv_out \dec_sub24_inv_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'00100
assign \inv_out \dec_sub4_inv_out
end
sync init
end
- process $group_34
+ process $group_35
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:264"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
switch \opc_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'01010
assign \cry_out \dec_sub10_cry_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'11100
assign \cry_out \dec_sub28_cry_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'00000
assign \cry_out \dec_sub0_cry_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'11010
assign \cry_out \dec_sub26_cry_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10011
assign \cry_out \dec_sub19_cry_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10110
assign \cry_out \dec_sub22_cry_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'01001
assign \cry_out \dec_sub9_cry_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'01011
assign \cry_out \dec_sub11_cry_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'11011
assign \cry_out \dec_sub27_cry_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'01111
assign \cry_out \dec_sub15_cry_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10100
assign \cry_out \dec_sub20_cry_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
- case 5'10111
- assign \cry_out \dec_sub23_cry_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10101
assign \cry_out \dec_sub21_cry_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+ case 5'10111
+ assign \cry_out \dec_sub23_cry_out
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10000
assign \cry_out \dec_sub16_cry_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10010
assign \cry_out \dec_sub18_cry_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'01000
assign \cry_out \dec_sub8_cry_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'11000
assign \cry_out \dec_sub24_cry_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'00100
assign \cry_out \dec_sub4_cry_out
end
sync init
end
- process $group_35
+ process $group_36
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:264"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
switch \opc_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'01010
assign \br \dec_sub10_br
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'11100
assign \br \dec_sub28_br
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'00000
assign \br \dec_sub0_br
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'11010
assign \br \dec_sub26_br
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10011
assign \br \dec_sub19_br
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10110
assign \br \dec_sub22_br
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'01001
assign \br \dec_sub9_br
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'01011
assign \br \dec_sub11_br
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'11011
assign \br \dec_sub27_br
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'01111
assign \br \dec_sub15_br
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10100
assign \br \dec_sub20_br
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
- case 5'10111
- assign \br \dec_sub23_br
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10101
assign \br \dec_sub21_br
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+ case 5'10111
+ assign \br \dec_sub23_br
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10000
assign \br \dec_sub16_br
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10010
assign \br \dec_sub18_br
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'01000
assign \br \dec_sub8_br
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'11000
assign \br \dec_sub24_br
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'00100
assign \br \dec_sub4_br
end
sync init
end
- process $group_36
+ process $group_37
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:264"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
switch \opc_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'01010
assign \sgn_ext \dec_sub10_sgn_ext
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'11100
assign \sgn_ext \dec_sub28_sgn_ext
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'00000
assign \sgn_ext \dec_sub0_sgn_ext
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'11010
assign \sgn_ext \dec_sub26_sgn_ext
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10011
assign \sgn_ext \dec_sub19_sgn_ext
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10110
assign \sgn_ext \dec_sub22_sgn_ext
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'01001
assign \sgn_ext \dec_sub9_sgn_ext
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'01011
assign \sgn_ext \dec_sub11_sgn_ext
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'11011
assign \sgn_ext \dec_sub27_sgn_ext
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'01111
assign \sgn_ext \dec_sub15_sgn_ext
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10100
assign \sgn_ext \dec_sub20_sgn_ext
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
- case 5'10111
- assign \sgn_ext \dec_sub23_sgn_ext
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10101
assign \sgn_ext \dec_sub21_sgn_ext
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+ case 5'10111
+ assign \sgn_ext \dec_sub23_sgn_ext
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10000
assign \sgn_ext \dec_sub16_sgn_ext
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10010
assign \sgn_ext \dec_sub18_sgn_ext
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'01000
assign \sgn_ext \dec_sub8_sgn_ext
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'11000
assign \sgn_ext \dec_sub24_sgn_ext
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'00100
assign \sgn_ext \dec_sub4_sgn_ext
end
sync init
end
- process $group_37
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:264"
- switch \opc_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
- case 5'01010
- assign \upd \dec_sub10_upd
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
- case 5'11100
- assign \upd \dec_sub28_upd
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
- case 5'00000
- assign \upd \dec_sub0_upd
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
- case 5'11010
- assign \upd \dec_sub26_upd
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
- case 5'10011
- assign \upd \dec_sub19_upd
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
- case 5'10110
- assign \upd \dec_sub22_upd
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
- case 5'01001
- assign \upd \dec_sub9_upd
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
- case 5'01011
- assign \upd \dec_sub11_upd
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
- case 5'11011
- assign \upd \dec_sub27_upd
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
- case 5'01111
- assign \upd \dec_sub15_upd
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
- case 5'10100
- assign \upd \dec_sub20_upd
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
- case 5'10111
- assign \upd \dec_sub23_upd
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
- case 5'10101
- assign \upd \dec_sub21_upd
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
- case 5'10000
- assign \upd \dec_sub16_upd
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
- case 5'10010
- assign \upd \dec_sub18_upd
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
- case 5'01000
- assign \upd \dec_sub8_upd
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
- case 5'11000
- assign \upd \dec_sub24_upd
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
- case 5'00100
- assign \upd \dec_sub4_upd
- end
- sync init
- end
process $group_38
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:264"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
switch \opc_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'01010
assign \rsrv \dec_sub10_rsrv
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'11100
assign \rsrv \dec_sub28_rsrv
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'00000
assign \rsrv \dec_sub0_rsrv
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'11010
assign \rsrv \dec_sub26_rsrv
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10011
assign \rsrv \dec_sub19_rsrv
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10110
assign \rsrv \dec_sub22_rsrv
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'01001
assign \rsrv \dec_sub9_rsrv
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'01011
assign \rsrv \dec_sub11_rsrv
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'11011
assign \rsrv \dec_sub27_rsrv
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'01111
assign \rsrv \dec_sub15_rsrv
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10100
assign \rsrv \dec_sub20_rsrv
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
- case 5'10111
- assign \rsrv \dec_sub23_rsrv
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10101
assign \rsrv \dec_sub21_rsrv
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+ case 5'10111
+ assign \rsrv \dec_sub23_rsrv
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10000
assign \rsrv \dec_sub16_rsrv
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10010
assign \rsrv \dec_sub18_rsrv
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'01000
assign \rsrv \dec_sub8_rsrv
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'11000
assign \rsrv \dec_sub24_rsrv
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'00100
assign \rsrv \dec_sub4_rsrv
end
end
process $group_39
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:264"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
switch \opc_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'01010
assign \is_32b \dec_sub10_is_32b
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'11100
assign \is_32b \dec_sub28_is_32b
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'00000
assign \is_32b \dec_sub0_is_32b
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'11010
assign \is_32b \dec_sub26_is_32b
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10011
assign \is_32b \dec_sub19_is_32b
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10110
assign \is_32b \dec_sub22_is_32b
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'01001
assign \is_32b \dec_sub9_is_32b
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'01011
assign \is_32b \dec_sub11_is_32b
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'11011
assign \is_32b \dec_sub27_is_32b
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'01111
assign \is_32b \dec_sub15_is_32b
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10100
assign \is_32b \dec_sub20_is_32b
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
- case 5'10111
- assign \is_32b \dec_sub23_is_32b
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10101
assign \is_32b \dec_sub21_is_32b
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+ case 5'10111
+ assign \is_32b \dec_sub23_is_32b
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10000
assign \is_32b \dec_sub16_is_32b
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10010
assign \is_32b \dec_sub18_is_32b
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'01000
assign \is_32b \dec_sub8_is_32b
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'11000
assign \is_32b \dec_sub24_is_32b
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'00100
assign \is_32b \dec_sub4_is_32b
end
end
process $group_40
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:264"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
switch \opc_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'01010
assign \sgn \dec_sub10_sgn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'11100
assign \sgn \dec_sub28_sgn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'00000
assign \sgn \dec_sub0_sgn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'11010
assign \sgn \dec_sub26_sgn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10011
assign \sgn \dec_sub19_sgn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10110
assign \sgn \dec_sub22_sgn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'01001
assign \sgn \dec_sub9_sgn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'01011
assign \sgn \dec_sub11_sgn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'11011
assign \sgn \dec_sub27_sgn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'01111
assign \sgn \dec_sub15_sgn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10100
assign \sgn \dec_sub20_sgn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
- case 5'10111
- assign \sgn \dec_sub23_sgn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10101
assign \sgn \dec_sub21_sgn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+ case 5'10111
+ assign \sgn \dec_sub23_sgn
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10000
assign \sgn \dec_sub16_sgn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10010
assign \sgn \dec_sub18_sgn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'01000
assign \sgn \dec_sub8_sgn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'11000
assign \sgn \dec_sub24_sgn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'00100
assign \sgn \dec_sub4_sgn
end
end
process $group_41
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:264"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
switch \opc_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'01010
assign \lk \dec_sub10_lk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'11100
assign \lk \dec_sub28_lk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'00000
assign \lk \dec_sub0_lk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'11010
assign \lk \dec_sub26_lk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10011
assign \lk \dec_sub19_lk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10110
assign \lk \dec_sub22_lk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'01001
assign \lk \dec_sub9_lk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'01011
assign \lk \dec_sub11_lk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'11011
assign \lk \dec_sub27_lk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'01111
assign \lk \dec_sub15_lk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10100
assign \lk \dec_sub20_lk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
- case 5'10111
- assign \lk \dec_sub23_lk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10101
assign \lk \dec_sub21_lk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+ case 5'10111
+ assign \lk \dec_sub23_lk
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10000
assign \lk \dec_sub16_lk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10010
assign \lk \dec_sub18_lk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'01000
assign \lk \dec_sub8_lk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'11000
assign \lk \dec_sub24_lk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'00100
assign \lk \dec_sub4_lk
end
end
process $group_42
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:264"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
switch \opc_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'01010
assign \sgl_pipe \dec_sub10_sgl_pipe
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'11100
assign \sgl_pipe \dec_sub28_sgl_pipe
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'00000
assign \sgl_pipe \dec_sub0_sgl_pipe
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'11010
assign \sgl_pipe \dec_sub26_sgl_pipe
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10011
assign \sgl_pipe \dec_sub19_sgl_pipe
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10110
assign \sgl_pipe \dec_sub22_sgl_pipe
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'01001
assign \sgl_pipe \dec_sub9_sgl_pipe
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'01011
assign \sgl_pipe \dec_sub11_sgl_pipe
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'11011
assign \sgl_pipe \dec_sub27_sgl_pipe
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'01111
assign \sgl_pipe \dec_sub15_sgl_pipe
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10100
assign \sgl_pipe \dec_sub20_sgl_pipe
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
- case 5'10111
- assign \sgl_pipe \dec_sub23_sgl_pipe
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10101
assign \sgl_pipe \dec_sub21_sgl_pipe
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+ case 5'10111
+ assign \sgl_pipe \dec_sub23_sgl_pipe
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10000
assign \sgl_pipe \dec_sub16_sgl_pipe
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10010
assign \sgl_pipe \dec_sub18_sgl_pipe
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'01000
assign \sgl_pipe \dec_sub8_sgl_pipe
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'11000
assign \sgl_pipe \dec_sub24_sgl_pipe
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'00100
assign \sgl_pipe \dec_sub4_sgl_pipe
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
- wire width 8 \asmcode$1
process $group_43
assign \asmcode 8'00000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:264"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
switch \opc_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'01010
assign \asmcode \dec_sub10_asmcode
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'11100
assign \asmcode \dec_sub28_asmcode
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'00000
assign \asmcode \dec_sub0_asmcode
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'11010
assign \asmcode \dec_sub26_asmcode
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10011
assign \asmcode \dec_sub19_asmcode
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10110
assign \asmcode \dec_sub22_asmcode
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'01001
assign \asmcode \dec_sub9_asmcode
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'01011
assign \asmcode \dec_sub11_asmcode
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'11011
assign \asmcode \dec_sub27_asmcode
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'01111
assign \asmcode \dec_sub15_asmcode
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10100
assign \asmcode \dec_sub20_asmcode
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
- case 5'10111
- assign \asmcode \dec_sub23_asmcode
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10101
assign \asmcode \dec_sub21_asmcode
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
+ case 5'10111
+ assign \asmcode \dec_sub23_asmcode
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10000
assign \asmcode \dec_sub16_asmcode
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'10010
- assign \asmcode \asmcode$1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ assign \asmcode \dec_sub18_asmcode
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'01000
assign \asmcode \dec_sub8_asmcode
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'11000
assign \asmcode \dec_sub24_asmcode
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:274"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:284"
case 5'00100
assign \asmcode \dec_sub4_asmcode
end
sync init
end
- connect \asmcode$1 8'00000000
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "test_issuer.core.pdecode2.dec.dec58"
module \dec58
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:229"
wire width 32 input 0 \opcode_in
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_11100 "Z23"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
wire width 5 output 2 \form
- attribute \enum_base_type "InternalOp"
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
+ attribute \enum_value_1001010 "OP_MTMSR"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
wire width 7 output 3 \internal_op
attribute \enum_base_type "In1Sel"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "RC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
wire width 2 output 10 \rc_sel
attribute \enum_base_type "LdstLen"
attribute \enum_value_0000 "NONE"
attribute \enum_value_1000 "is8B"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
wire width 4 output 11 \ldst_len
+ attribute \enum_base_type "LDSTMode"
+ attribute \enum_value_00 "NONE"
+ attribute \enum_value_01 "update"
+ attribute \enum_value_10 "cix"
+ attribute \enum_value_11 "cx"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+ wire width 2 output 12 \upd
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
- wire width 2 output 12 \cry_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 13 \inv_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 14 \inv_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 15 \cry_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 16 \br
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 17 \sgn_ext
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 18 \upd
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
+ wire width 2 output 13 \cry_in
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 14 \inv_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 15 \inv_out
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 16 \cry_out
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 17 \br
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 18 \sgn_ext
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 output 19 \rsrv
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 output 20 \is_32b
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 output 21 \sgn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 output 22 \lk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 output 23 \sgl_pipe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
wire width 8 output 24 \asmcode
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:257"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:267"
wire width 2 \opcode_switch
process $group_0
assign \opcode_switch 2'00
end
process $group_1
assign \function_unit 11'00000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 2'00
assign \function_unit 11'00000000100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 2'01
assign \function_unit 11'00000000100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 2'10
assign \function_unit 11'00000000100
end
end
process $group_2
assign \form 5'00000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 2'00
assign \form 5'00101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 2'01
assign \form 5'00101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 2'10
assign \form 5'00101
end
end
process $group_3
assign \internal_op 7'0000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 2'00
assign \internal_op 7'0100101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 2'01
assign \internal_op 7'0100101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 2'10
assign \internal_op 7'0100101
end
end
process $group_4
assign \in1_sel 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 2'00
assign \in1_sel 3'010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 2'01
assign \in1_sel 3'010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 2'10
assign \in1_sel 3'010
end
end
process $group_5
assign \in2_sel 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 2'00
assign \in2_sel 4'1000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 2'01
assign \in2_sel 4'1000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 2'10
assign \in2_sel 4'1000
end
end
process $group_6
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 2'00
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 2'01
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 2'10
assign \in3_sel 2'00
end
end
process $group_7
assign \out_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 2'00
assign \out_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 2'01
assign \out_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 2'10
assign \out_sel 2'01
end
end
process $group_8
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 2'00
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 2'01
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 2'10
assign \cr_in 3'000
end
end
process $group_9
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 2'00
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 2'01
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 2'10
assign \cr_out 3'000
end
end
process $group_10
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 2'00
assign \ldst_len 4'1000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 2'01
assign \ldst_len 4'1000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 2'10
assign \ldst_len 4'0100
end
sync init
end
process $group_11
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+ switch \opcode_switch
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 2'00
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 2'01
+ assign \upd 2'01
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 2'10
+ assign \upd 2'00
+ end
+ sync init
+ end
+ process $group_12
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 2'00
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 2'01
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 2'10
assign \rc_sel 2'00
end
sync init
end
- process $group_12
+ process $group_13
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 2'00
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 2'01
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 2'10
assign \cry_in 2'00
end
sync init
end
- process $group_13
+ process $group_14
assign \asmcode 8'00000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 2'00
assign \asmcode 8'01010001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 2'01
assign \asmcode 8'01010100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 2'10
assign \asmcode 8'01100001
end
sync init
end
- process $group_14
+ process $group_15
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 2'00
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 2'01
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 2'10
assign \inv_a 1'0
end
sync init
end
- process $group_15
+ process $group_16
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 2'00
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 2'01
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 2'10
assign \inv_out 1'0
end
sync init
end
- process $group_16
+ process $group_17
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 2'00
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 2'01
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 2'10
assign \cry_out 1'0
end
sync init
end
- process $group_17
+ process $group_18
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 2'00
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 2'01
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 2'10
assign \br 1'0
end
sync init
end
- process $group_18
+ process $group_19
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 2'00
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 2'01
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 2'10
assign \sgn_ext 1'1
end
sync init
end
- process $group_19
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
- switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 2'00
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 2'01
- assign \upd 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 2'10
- assign \upd 1'0
- end
- sync init
- end
process $group_20
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 2'00
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 2'01
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 2'10
assign \rsrv 1'0
end
end
process $group_21
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 2'00
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 2'01
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 2'10
assign \is_32b 1'0
end
end
process $group_22
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 2'00
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 2'01
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 2'10
assign \sgn 1'0
end
end
process $group_23
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 2'00
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 2'01
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 2'10
assign \lk 1'0
end
end
process $group_24
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 2'00
assign \sgl_pipe 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 2'01
assign \sgl_pipe 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 2'10
assign \sgl_pipe 1'1
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "test_issuer.core.pdecode2.dec.dec62"
module \dec62
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:229"
wire width 32 input 0 \opcode_in
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_11100 "Z23"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
wire width 5 output 2 \form
- attribute \enum_base_type "InternalOp"
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
+ attribute \enum_value_1001010 "OP_MTMSR"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
wire width 7 output 3 \internal_op
attribute \enum_base_type "In1Sel"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "RC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
wire width 2 output 10 \rc_sel
attribute \enum_base_type "LdstLen"
attribute \enum_value_0000 "NONE"
attribute \enum_value_1000 "is8B"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
wire width 4 output 11 \ldst_len
+ attribute \enum_base_type "LDSTMode"
+ attribute \enum_value_00 "NONE"
+ attribute \enum_value_01 "update"
+ attribute \enum_value_10 "cix"
+ attribute \enum_value_11 "cx"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+ wire width 2 output 12 \upd
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
- wire width 2 output 12 \cry_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 13 \inv_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 14 \inv_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 15 \cry_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 16 \br
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 17 \sgn_ext
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 18 \upd
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
+ wire width 2 output 13 \cry_in
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 14 \inv_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 15 \inv_out
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 16 \cry_out
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 17 \br
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 18 \sgn_ext
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 output 19 \rsrv
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 output 20 \is_32b
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 output 21 \sgn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 output 22 \lk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 output 23 \sgl_pipe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
wire width 8 output 24 \asmcode
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:257"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:267"
wire width 2 \opcode_switch
process $group_0
assign \opcode_switch 2'00
end
process $group_1
assign \function_unit 11'00000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 2'00
assign \function_unit 11'00000000100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 2'01
assign \function_unit 11'00000000100
end
end
process $group_2
assign \form 5'00000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 2'00
assign \form 5'00101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 2'01
assign \form 5'00101
end
end
process $group_3
assign \internal_op 7'0000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 2'00
assign \internal_op 7'0100110
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 2'01
assign \internal_op 7'0100110
end
end
process $group_4
assign \in1_sel 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 2'00
assign \in1_sel 3'010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 2'01
assign \in1_sel 3'010
end
end
process $group_5
assign \in2_sel 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 2'00
assign \in2_sel 4'1000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 2'01
assign \in2_sel 4'1000
end
end
process $group_6
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 2'00
assign \in3_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 2'01
assign \in3_sel 2'01
end
end
process $group_7
assign \out_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 2'00
assign \out_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 2'01
assign \out_sel 2'00
end
end
process $group_8
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 2'00
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 2'01
assign \cr_in 3'000
end
end
process $group_9
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 2'00
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 2'01
assign \cr_out 3'000
end
end
process $group_10
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 2'00
assign \ldst_len 4'1000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 2'01
assign \ldst_len 4'1000
end
sync init
end
process $group_11
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+ switch \opcode_switch
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 2'00
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 2'01
+ assign \upd 2'01
+ end
+ sync init
+ end
+ process $group_12
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 2'00
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 2'01
assign \rc_sel 2'00
end
sync init
end
- process $group_12
+ process $group_13
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 2'00
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 2'01
assign \cry_in 2'00
end
sync init
end
- process $group_13
+ process $group_14
assign \asmcode 8'00000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 2'00
- assign \asmcode 8'10100111
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ assign \asmcode 8'10101000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 2'01
- assign \asmcode 8'10101010
+ assign \asmcode 8'10101011
end
sync init
end
- process $group_14
+ process $group_15
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 2'00
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 2'01
assign \inv_a 1'0
end
sync init
end
- process $group_15
+ process $group_16
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 2'00
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 2'01
assign \inv_out 1'0
end
sync init
end
- process $group_16
+ process $group_17
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 2'00
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 2'01
assign \cry_out 1'0
end
sync init
end
- process $group_17
+ process $group_18
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 2'00
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 2'01
assign \br 1'0
end
sync init
end
- process $group_18
+ process $group_19
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 2'00
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 2'01
assign \sgn_ext 1'0
end
sync init
end
- process $group_19
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
- switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 2'00
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 2'01
- assign \upd 1'1
- end
- sync init
- end
process $group_20
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 2'00
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 2'01
assign \rsrv 1'0
end
end
process $group_21
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 2'00
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 2'01
assign \is_32b 1'0
end
end
process $group_22
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 2'00
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 2'01
assign \sgn 1'0
end
end
process $group_23
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 2'00
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 2'01
assign \lk 1'0
end
end
process $group_24
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 2'00
assign \sgl_pipe 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 2'01
assign \sgl_pipe 1'1
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "test_issuer.core.pdecode2.dec"
module \dec
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:319"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:329"
wire width 1 input 0 \bigendian
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:328"
wire width 32 input 1 \raw_opcode_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:229"
wire width 32 output 2 \opcode_in
attribute \enum_base_type "In1Sel"
attribute \enum_value_000 "NONE"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "RC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
wire width 2 output 7 \rc_sel
attribute \enum_base_type "CRInSel"
attribute \enum_value_000 "NONE"
attribute \enum_value_100 "WHOLE_REG"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
wire width 3 output 9 \cr_out
- attribute \enum_base_type "Function"
- attribute \enum_value_00000000000 "NONE"
- attribute \enum_value_00000000010 "ALU"
- attribute \enum_value_00000000100 "LDST"
- attribute \enum_value_00000001000 "SHIFT_ROT"
- attribute \enum_value_00000010000 "LOGICAL"
- attribute \enum_value_00000100000 "BRANCH"
- attribute \enum_value_00001000000 "CR"
- attribute \enum_value_00010000000 "TRAP"
- attribute \enum_value_00100000000 "MUL"
- attribute \enum_value_01000000000 "DIV"
- attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119"
- wire width 11 output 10 \function_unit
- attribute \enum_base_type "InternalOp"
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
+ attribute \enum_value_1001010 "OP_MTMSR"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
- wire width 7 output 11 \internal_op
+ wire width 7 output 10 \internal_op
+ attribute \enum_base_type "Function"
+ attribute \enum_value_00000000000 "NONE"
+ attribute \enum_value_00000000010 "ALU"
+ attribute \enum_value_00000000100 "LDST"
+ attribute \enum_value_00000001000 "SHIFT_ROT"
+ attribute \enum_value_00000010000 "LOGICAL"
+ attribute \enum_value_00000100000 "BRANCH"
+ attribute \enum_value_00001000000 "CR"
+ attribute \enum_value_00010000000 "TRAP"
+ attribute \enum_value_00100000000 "MUL"
+ attribute \enum_value_01000000000 "DIV"
+ attribute \enum_value_10000000000 "SPR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119"
+ wire width 11 output 11 \function_unit
attribute \enum_base_type "LdstLen"
attribute \enum_value_0000 "NONE"
attribute \enum_value_0001 "is1B"
attribute \enum_value_1000 "is8B"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
wire width 4 output 12 \ldst_len
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 output 13 \inv_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 output 14 \inv_out
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
wire width 2 output 15 \cry_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 output 16 \cry_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 output 17 \is_32b
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 output 18 \sgn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 output 19 \lk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
wire width 1 output 20 \LK
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 output 21 \br
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 output 22 \sgn_ext
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 23 \upd
+ attribute \enum_base_type "LDSTMode"
+ attribute \enum_value_00 "NONE"
+ attribute \enum_value_01 "update"
+ attribute \enum_value_10 "cix"
+ attribute \enum_value_11 "cx"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+ wire width 2 output 23 \upd
attribute \enum_base_type "Form"
attribute \enum_value_00000 "NONE"
attribute \enum_value_00001 "I"
attribute \enum_value_11100 "Z23"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
wire width 5 output 24 \form
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 output 25 \rsrv
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 output 26 \sgl_pipe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
wire width 8 output 27 \asmcode
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
wire width 5 output 28 \RS
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
wire width 5 output 29 \RT
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
wire width 5 output 30 \RA
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
wire width 5 output 31 \RB
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
wire width 16 output 32 \SI
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
wire width 16 output 33 \UI
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
wire width 5 output 34 \SH32
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
wire width 6 output 35 \sh
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
wire width 24 output 36 \LI
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
wire width 1 output 37 \Rc
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
wire width 1 output 38 \OE
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
wire width 14 output 39 \BD
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
wire width 5 output 40 \BB
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
wire width 5 output 41 \BA
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
wire width 5 output 42 \BT
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
wire width 5 output 43 \BO
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
wire width 5 output 44 \BI
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
wire width 14 output 45 \DS
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
wire width 5 output 46 \BC
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
wire width 10 output 47 \SPR
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 3 output 48 \X_BF
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 3 output 49 \X_BFA
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 output 50 \XL_BT
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 10 output 51 \XL_XO
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:229"
wire width 32 \dec19_opcode_in
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_11100 "Z23"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
wire width 5 \dec19_form
- attribute \enum_base_type "InternalOp"
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
+ attribute \enum_value_1001010 "OP_MTMSR"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
wire width 7 \dec19_internal_op
attribute \enum_base_type "In1Sel"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "RC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
wire width 2 \dec19_rc_sel
attribute \enum_base_type "LdstLen"
attribute \enum_value_0000 "NONE"
attribute \enum_value_1000 "is8B"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
wire width 4 \dec19_ldst_len
+ attribute \enum_base_type "LDSTMode"
+ attribute \enum_value_00 "NONE"
+ attribute \enum_value_01 "update"
+ attribute \enum_value_10 "cix"
+ attribute \enum_value_11 "cx"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+ wire width 2 \dec19_upd
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
wire width 2 \dec19_cry_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec19_inv_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec19_inv_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec19_cry_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec19_br
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec19_sgn_ext
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- wire width 1 \dec19_upd
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec19_rsrv
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec19_is_32b
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec19_sgn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec19_lk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec19_sgl_pipe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
wire width 8 \dec19_asmcode
connect \cr_out \dec19_cr_out
connect \rc_sel \dec19_rc_sel
connect \ldst_len \dec19_ldst_len
+ connect \upd \dec19_upd
connect \cry_in \dec19_cry_in
connect \inv_a \dec19_inv_a
connect \inv_out \dec19_inv_out
connect \cry_out \dec19_cry_out
connect \br \dec19_br
connect \sgn_ext \dec19_sgn_ext
- connect \upd \dec19_upd
connect \rsrv \dec19_rsrv
connect \is_32b \dec19_is_32b
connect \sgn \dec19_sgn
connect \sgl_pipe \dec19_sgl_pipe
connect \asmcode \dec19_asmcode
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:229"
wire width 32 \dec30_opcode_in
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
wire width 5 \dec30_form
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+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
wire width 7 \dec30_internal_op
attribute \enum_base_type "In1Sel"
attribute \enum_value_00 "NONE"
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wire width 2 \dec30_rc_sel
attribute \enum_base_type "LdstLen"
attribute \enum_value_0000 "NONE"
attribute \enum_value_1000 "is8B"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
wire width 4 \dec30_ldst_len
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attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
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wire width 2 \dec30_cry_in
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wire width 1 \dec30_inv_a
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wire width 1 \dec30_inv_out
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wire width 1 \dec30_cry_out
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wire width 1 \dec30_br
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wire width 1 \dec30_sgn_ext
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- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
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wire width 1 \dec30_rsrv
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
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wire width 1 \dec30_is_32b
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
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wire width 1 \dec30_sgn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
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wire width 1 \dec30_lk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
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wire width 1 \dec30_sgl_pipe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
wire width 8 \dec30_asmcode
connect \cr_out \dec30_cr_out
connect \rc_sel \dec30_rc_sel
connect \ldst_len \dec30_ldst_len
+ connect \upd \dec30_upd
connect \cry_in \dec30_cry_in
connect \inv_a \dec30_inv_a
connect \inv_out \dec30_inv_out
connect \cry_out \dec30_cry_out
connect \br \dec30_br
connect \sgn_ext \dec30_sgn_ext
- connect \upd \dec30_upd
connect \rsrv \dec30_rsrv
connect \is_32b \dec30_is_32b
connect \sgn \dec30_sgn
connect \sgl_pipe \dec30_sgl_pipe
connect \asmcode \dec30_asmcode
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219"
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wire width 32 \dec31_opcode_in
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_11100 "Z23"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
wire width 5 \dec31_form
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attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
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attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
wire width 7 \dec31_internal_op
attribute \enum_base_type "In1Sel"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "RC"
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wire width 2 \dec31_rc_sel
attribute \enum_base_type "LdstLen"
attribute \enum_value_0000 "NONE"
attribute \enum_value_1000 "is8B"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
wire width 4 \dec31_ldst_len
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+ attribute \enum_value_10 "cix"
+ attribute \enum_value_11 "cx"
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attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
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wire width 2 \dec31_cry_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
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wire width 1 \dec31_inv_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
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wire width 1 \dec31_inv_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
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wire width 1 \dec31_cry_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
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wire width 1 \dec31_br
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
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wire width 1 \dec31_sgn_ext
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- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
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wire width 1 \dec31_rsrv
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
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wire width 1 \dec31_is_32b
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
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wire width 1 \dec31_sgn
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wire width 1 \dec31_lk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
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wire width 1 \dec31_sgl_pipe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
wire width 8 \dec31_asmcode
connect \cr_out \dec31_cr_out
connect \rc_sel \dec31_rc_sel
connect \ldst_len \dec31_ldst_len
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connect \cry_in \dec31_cry_in
connect \inv_a \dec31_inv_a
connect \inv_out \dec31_inv_out
connect \cry_out \dec31_cry_out
connect \br \dec31_br
connect \sgn_ext \dec31_sgn_ext
- connect \upd \dec31_upd
connect \rsrv \dec31_rsrv
connect \is_32b \dec31_is_32b
connect \sgn \dec31_sgn
connect \sgl_pipe \dec31_sgl_pipe
connect \asmcode \dec31_asmcode
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219"
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wire width 32 \dec58_opcode_in
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
wire width 5 \dec58_form
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attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
wire width 7 \dec58_internal_op
attribute \enum_base_type "In1Sel"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "ONE"
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wire width 2 \dec58_rc_sel
attribute \enum_base_type "LdstLen"
attribute \enum_value_0000 "NONE"
attribute \enum_value_1000 "is8B"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
wire width 4 \dec58_ldst_len
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attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
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wire width 2 \dec58_cry_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
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wire width 1 \dec58_inv_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
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wire width 1 \dec58_inv_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
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wire width 1 \dec58_cry_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
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wire width 1 \dec58_br
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wire width 1 \dec58_sgn_ext
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- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
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wire width 1 \dec58_rsrv
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
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wire width 1 \dec58_is_32b
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
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wire width 1 \dec58_sgn
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wire width 1 \dec58_lk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
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wire width 1 \dec58_sgl_pipe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
wire width 8 \dec58_asmcode
connect \cr_out \dec58_cr_out
connect \rc_sel \dec58_rc_sel
connect \ldst_len \dec58_ldst_len
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connect \cry_in \dec58_cry_in
connect \inv_a \dec58_inv_a
connect \inv_out \dec58_inv_out
connect \cry_out \dec58_cry_out
connect \br \dec58_br
connect \sgn_ext \dec58_sgn_ext
- connect \upd \dec58_upd
connect \rsrv \dec58_rsrv
connect \is_32b \dec58_is_32b
connect \sgn \dec58_sgn
connect \sgl_pipe \dec58_sgl_pipe
connect \asmcode \dec58_asmcode
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219"
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wire width 32 \dec62_opcode_in
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_11100 "Z23"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
wire width 5 \dec62_form
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attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
wire width 7 \dec62_internal_op
attribute \enum_base_type "In1Sel"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "RC"
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wire width 2 \dec62_rc_sel
attribute \enum_base_type "LdstLen"
attribute \enum_value_0000 "NONE"
attribute \enum_value_1000 "is8B"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
wire width 4 \dec62_ldst_len
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attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
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wire width 2 \dec62_cry_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
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wire width 1 \dec62_inv_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
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wire width 1 \dec62_inv_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
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wire width 1 \dec62_cry_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
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wire width 1 \dec62_br
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
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wire width 1 \dec62_sgn_ext
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- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
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wire width 1 \dec62_rsrv
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
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wire width 1 \dec62_is_32b
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
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wire width 1 \dec62_sgn
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wire width 1 \dec62_lk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
wire width 1 \dec62_sgl_pipe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
wire width 8 \dec62_asmcode
connect \cr_out \dec62_cr_out
connect \rc_sel \dec62_rc_sel
connect \ldst_len \dec62_ldst_len
+ connect \upd \dec62_upd
connect \cry_in \dec62_cry_in
connect \inv_a \dec62_inv_a
connect \inv_out \dec62_inv_out
connect \cry_out \dec62_cry_out
connect \br \dec62_br
connect \sgn_ext \dec62_sgn_ext
- connect \upd \dec62_upd
connect \rsrv \dec62_rsrv
connect \is_32b \dec62_is_32b
connect \sgn \dec62_sgn
connect \sgl_pipe \dec62_sgl_pipe
connect \asmcode \dec62_asmcode
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:257"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:267"
wire width 6 \opcode_switch
process $group_0
assign \opcode_switch 6'000000
assign \dec62_opcode_in \opcode_in
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:257"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:267"
wire width 32 \opcode_switch$1
process $group_6
assign \function_unit 11'00000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
case 6'010011
assign \function_unit \dec19_function_unit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
case 6'011110
assign \function_unit \dec30_function_unit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
case 6'011111
assign \function_unit \dec31_function_unit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
case 6'111010
assign \function_unit \dec58_function_unit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
case 6'111110
assign \function_unit \dec62_function_unit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001100
assign \function_unit 11'00000000010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001101
assign \function_unit 11'00000000010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001110
assign \function_unit 11'00000000010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001111
assign \function_unit 11'00000000010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010001
assign \function_unit 11'00010000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011100
assign \function_unit 11'00000010000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011101
assign \function_unit 11'00000010000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010010
assign \function_unit 11'00000100000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010000
assign \function_unit 11'00000100000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001011
assign \function_unit 11'00000000010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001010
assign \function_unit 11'00000000010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100010
assign \function_unit 11'00000000100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100011
assign \function_unit 11'00000000100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101010
assign \function_unit 11'00000000100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101011
assign \function_unit 11'00000000100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101000
assign \function_unit 11'00000000100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101001
assign \function_unit 11'00000000100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100000
assign \function_unit 11'00000000100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100001
assign \function_unit 11'00000000100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'000111
assign \function_unit 11'00100000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011000
assign \function_unit 11'00000010000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011001
assign \function_unit 11'00000010000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010100
assign \function_unit 11'00000001000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010101
assign \function_unit 11'00000001000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010111
assign \function_unit 11'00000001000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100110
assign \function_unit 11'00000000100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100111
assign \function_unit 11'00000000100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101100
assign \function_unit 11'00000000100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101101
assign \function_unit 11'00000000100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100100
assign \function_unit 11'00000000100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100101
assign \function_unit 11'00000000100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001000
assign \function_unit 11'00000000010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'000010
assign \function_unit 11'00010000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'000011
assign \function_unit 11'00010000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011010
assign \function_unit 11'00000010000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011011
assign \function_unit 11'00000010000
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch$1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 32'000000---------------0100000000-
- assign \function_unit 11'00000000010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ assign \function_unit 11'00000000000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 32'01100000000000000000000000000000
- assign \function_unit 11'00000000010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ assign \function_unit 11'00000000000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 32'000001---------------0000000011-
- assign \function_unit 11'00000000010
+ assign \function_unit 11'00000000000
end
sync init
end
process $group_7
assign \form 5'00000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
case 6'010011
assign \form \dec19_form
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
case 6'011110
assign \form \dec30_form
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
case 6'011111
assign \form \dec31_form
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
case 6'111010
assign \form \dec58_form
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
case 6'111110
assign \form \dec62_form
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001100
assign \form 5'00100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001101
assign \form 5'00100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001110
assign \form 5'00100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001111
assign \form 5'00100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010001
assign \form 5'00011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011100
assign \form 5'00010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011101
assign \form 5'00010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010010
assign \form 5'00001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010000
assign \form 5'00010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001011
assign \form 5'00100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001010
assign \form 5'00100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100010
assign \form 5'00100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100011
assign \form 5'00100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101010
assign \form 5'00100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101011
assign \form 5'00100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101000
assign \form 5'00100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101001
assign \form 5'00100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100000
assign \form 5'00100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100001
assign \form 5'00100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'000111
assign \form 5'00100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011000
assign \form 5'00100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011001
assign \form 5'00100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010100
assign \form 5'10011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010101
assign \form 5'10011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010111
assign \form 5'10011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100110
assign \form 5'00100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100111
assign \form 5'00100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101100
assign \form 5'00100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101101
assign \form 5'00100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100100
assign \form 5'00100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100101
assign \form 5'00100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001000
assign \form 5'00100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'000010
assign \form 5'00100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'000011
assign \form 5'00100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011010
assign \form 5'00100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011011
assign \form 5'00100
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch$1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 32'000000---------------0100000000-
assign \form 5'00000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 32'01100000000000000000000000000000
assign \form 5'00100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 32'000001---------------0000000011-
assign \form 5'00000
end
end
process $group_8
assign \internal_op 7'0000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
case 6'010011
assign \internal_op \dec19_internal_op
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
case 6'011110
assign \internal_op \dec30_internal_op
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
case 6'011111
assign \internal_op \dec31_internal_op
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
case 6'111010
assign \internal_op \dec58_internal_op
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
case 6'111110
assign \internal_op \dec62_internal_op
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001100
assign \internal_op 7'0000010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001101
assign \internal_op 7'0000010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001110
assign \internal_op 7'0000010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001111
assign \internal_op 7'0000010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010001
assign \internal_op 7'1001001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011100
assign \internal_op 7'0000100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011101
assign \internal_op 7'0000100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010010
assign \internal_op 7'0000110
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010000
assign \internal_op 7'0000111
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001011
assign \internal_op 7'0001010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001010
assign \internal_op 7'0001010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100010
assign \internal_op 7'0100101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100011
assign \internal_op 7'0100101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101010
assign \internal_op 7'0100101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101011
assign \internal_op 7'0100101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101000
assign \internal_op 7'0100101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101001
assign \internal_op 7'0100101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100000
assign \internal_op 7'0100101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100001
assign \internal_op 7'0100101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'000111
assign \internal_op 7'0110010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011000
assign \internal_op 7'0110101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011001
assign \internal_op 7'0110101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010100
assign \internal_op 7'0111000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010101
assign \internal_op 7'0111000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010111
assign \internal_op 7'0111000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100110
assign \internal_op 7'0100110
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100111
assign \internal_op 7'0100110
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101100
assign \internal_op 7'0100110
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101101
assign \internal_op 7'0100110
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100100
assign \internal_op 7'0100110
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100101
assign \internal_op 7'0100110
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001000
assign \internal_op 7'0000010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'000010
assign \internal_op 7'0111111
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'000011
assign \internal_op 7'0111111
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011010
assign \internal_op 7'1000011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011011
assign \internal_op 7'1000011
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch$1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 32'000000---------------0100000000-
- assign \internal_op 7'0000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ assign \internal_op 7'0000101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 32'01100000000000000000000000000000
assign \internal_op 7'0000001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 32'000001---------------0000000011-
assign \internal_op 7'1000100
end
end
process $group_9
assign \in1_sel 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
case 6'010011
assign \in1_sel \dec19_in1_sel
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
case 6'011110
assign \in1_sel \dec30_in1_sel
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
case 6'011111
assign \in1_sel \dec31_in1_sel
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
case 6'111010
assign \in1_sel \dec58_in1_sel
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
case 6'111110
assign \in1_sel \dec62_in1_sel
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001100
assign \in1_sel 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001101
assign \in1_sel 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001110
assign \in1_sel 3'010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001111
assign \in1_sel 3'010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010001
assign \in1_sel 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011100
assign \in1_sel 3'100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011101
assign \in1_sel 3'100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010010
assign \in1_sel 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010000
assign \in1_sel 3'011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001011
assign \in1_sel 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001010
assign \in1_sel 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100010
assign \in1_sel 3'010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100011
assign \in1_sel 3'010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101010
assign \in1_sel 3'010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101011
assign \in1_sel 3'010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101000
assign \in1_sel 3'010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101001
assign \in1_sel 3'010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100000
assign \in1_sel 3'010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100001
assign \in1_sel 3'010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'000111
assign \in1_sel 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011000
assign \in1_sel 3'100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011001
assign \in1_sel 3'100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010100
assign \in1_sel 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010101
assign \in1_sel 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010111
assign \in1_sel 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100110
assign \in1_sel 3'010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100111
assign \in1_sel 3'010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101100
assign \in1_sel 3'010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101101
assign \in1_sel 3'010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100100
assign \in1_sel 3'010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100101
assign \in1_sel 3'010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001000
assign \in1_sel 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'000010
assign \in1_sel 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'000011
assign \in1_sel 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011010
assign \in1_sel 3'100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011011
assign \in1_sel 3'100
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch$1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 32'000000---------------0100000000-
assign \in1_sel 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 32'01100000000000000000000000000000
assign \in1_sel 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 32'000001---------------0000000011-
assign \in1_sel 3'000
end
end
process $group_10
assign \in2_sel 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
case 6'010011
assign \in2_sel \dec19_in2_sel
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
case 6'011110
assign \in2_sel \dec30_in2_sel
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
case 6'011111
assign \in2_sel \dec31_in2_sel
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
case 6'111010
assign \in2_sel \dec58_in2_sel
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
case 6'111110
assign \in2_sel \dec62_in2_sel
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001100
assign \in2_sel 4'0011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001101
assign \in2_sel 4'0011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001110
assign \in2_sel 4'0011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001111
assign \in2_sel 4'0101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010001
assign \in2_sel 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011100
assign \in2_sel 4'0010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011101
assign \in2_sel 4'0100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010010
assign \in2_sel 4'0110
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010000
assign \in2_sel 4'0111
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001011
assign \in2_sel 4'0011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001010
assign \in2_sel 4'0010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100010
assign \in2_sel 4'0011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100011
assign \in2_sel 4'0011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101010
assign \in2_sel 4'0011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101011
assign \in2_sel 4'0011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101000
assign \in2_sel 4'0011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101001
assign \in2_sel 4'0011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100000
assign \in2_sel 4'0011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100001
assign \in2_sel 4'0011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'000111
assign \in2_sel 4'0011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011000
assign \in2_sel 4'0010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011001
assign \in2_sel 4'0100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010100
assign \in2_sel 4'1011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010101
assign \in2_sel 4'1011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010111
assign \in2_sel 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100110
assign \in2_sel 4'0011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100111
assign \in2_sel 4'0011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101100
assign \in2_sel 4'0011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101101
assign \in2_sel 4'0011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100100
assign \in2_sel 4'0011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100101
assign \in2_sel 4'0011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001000
assign \in2_sel 4'0011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'000010
assign \in2_sel 4'0011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'000011
assign \in2_sel 4'0011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011010
assign \in2_sel 4'0010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011011
assign \in2_sel 4'0100
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch$1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 32'000000---------------0100000000-
assign \in2_sel 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 32'01100000000000000000000000000000
assign \in2_sel 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 32'000001---------------0000000011-
assign \in2_sel 4'0000
end
end
process $group_11
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
case 6'010011
assign \in3_sel \dec19_in3_sel
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
case 6'011110
assign \in3_sel \dec30_in3_sel
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
case 6'011111
assign \in3_sel \dec31_in3_sel
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
case 6'111010
assign \in3_sel \dec58_in3_sel
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
case 6'111110
assign \in3_sel \dec62_in3_sel
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001100
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001101
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001110
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001111
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010001
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011100
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011101
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010010
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010000
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001011
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001010
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100010
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100011
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101010
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101011
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101000
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101001
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100000
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100001
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'000111
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011000
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011001
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010100
assign \in3_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010101
assign \in3_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010111
assign \in3_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100110
assign \in3_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100111
assign \in3_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101100
assign \in3_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101101
assign \in3_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100100
assign \in3_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100101
assign \in3_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001000
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'000010
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'000011
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011010
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011011
assign \in3_sel 2'00
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch$1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 32'000000---------------0100000000-
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 32'01100000000000000000000000000000
assign \in3_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 32'000001---------------0000000011-
assign \in3_sel 2'00
end
end
process $group_12
assign \out_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
case 6'010011
assign \out_sel \dec19_out_sel
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
case 6'011110
assign \out_sel \dec30_out_sel
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
case 6'011111
assign \out_sel \dec31_out_sel
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
case 6'111010
assign \out_sel \dec58_out_sel
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
case 6'111110
assign \out_sel \dec62_out_sel
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001100
assign \out_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001101
assign \out_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001110
assign \out_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001111
assign \out_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010001
assign \out_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011100
assign \out_sel 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011101
assign \out_sel 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010010
assign \out_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010000
assign \out_sel 2'11
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001011
assign \out_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001010
assign \out_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100010
assign \out_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100011
assign \out_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101010
assign \out_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101011
assign \out_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101000
assign \out_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101001
assign \out_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100000
assign \out_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100001
assign \out_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'000111
assign \out_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011000
assign \out_sel 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011001
assign \out_sel 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010100
assign \out_sel 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010101
assign \out_sel 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010111
assign \out_sel 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100110
assign \out_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100111
assign \out_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101100
assign \out_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101101
assign \out_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100100
assign \out_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100101
assign \out_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001000
assign \out_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'000010
assign \out_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'000011
assign \out_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011010
assign \out_sel 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011011
assign \out_sel 2'10
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch$1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 32'000000---------------0100000000-
assign \out_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 32'01100000000000000000000000000000
assign \out_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 32'000001---------------0000000011-
assign \out_sel 2'01
end
end
process $group_13
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
case 6'010011
assign \cr_in \dec19_cr_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
case 6'011110
assign \cr_in \dec30_cr_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
case 6'011111
assign \cr_in \dec31_cr_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
case 6'111010
assign \cr_in \dec58_cr_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
case 6'111110
assign \cr_in \dec62_cr_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001100
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001101
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001110
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001111
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010001
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011100
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011101
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010010
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010000
assign \cr_in 3'010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001011
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001010
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100010
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100011
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101010
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101011
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101000
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101001
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100000
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100001
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'000111
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011000
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011001
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010100
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010101
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010111
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100110
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100111
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101100
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101101
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100100
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100101
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001000
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'000010
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'000011
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011010
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011011
assign \cr_in 3'000
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch$1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 32'000000---------------0100000000-
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 32'01100000000000000000000000000000
assign \cr_in 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 32'000001---------------0000000011-
assign \cr_in 3'000
end
end
process $group_14
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
case 6'010011
assign \cr_out \dec19_cr_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
case 6'011110
assign \cr_out \dec30_cr_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
case 6'011111
assign \cr_out \dec31_cr_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
case 6'111010
assign \cr_out \dec58_cr_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
case 6'111110
assign \cr_out \dec62_cr_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001100
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001101
assign \cr_out 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001110
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001111
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010001
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011100
assign \cr_out 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011101
assign \cr_out 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010010
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010000
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001011
assign \cr_out 3'010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001010
assign \cr_out 3'010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100010
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100011
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101010
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101011
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101000
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101001
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100000
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100001
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'000111
assign \cr_out 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011000
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011001
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010100
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010101
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010111
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100110
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100111
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101100
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101101
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100100
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100101
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001000
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'000010
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'000011
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011010
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011011
assign \cr_out 3'000
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch$1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 32'000000---------------0100000000-
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 32'01100000000000000000000000000000
assign \cr_out 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 32'000001---------------0000000011-
assign \cr_out 3'000
end
end
process $group_15
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
case 6'010011
assign \rc_sel \dec19_rc_sel
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
case 6'011110
assign \rc_sel \dec30_rc_sel
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
case 6'011111
assign \rc_sel \dec31_rc_sel
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
case 6'111010
assign \rc_sel \dec58_rc_sel
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
case 6'111110
assign \rc_sel \dec62_rc_sel
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001100
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001101
assign \rc_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001110
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001111
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010001
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011100
assign \rc_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011101
assign \rc_sel 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010010
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010000
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001011
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001010
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100010
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100011
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101010
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101011
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101000
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101001
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100000
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100001
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'000111
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011000
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011001
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010100
assign \rc_sel 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010101
assign \rc_sel 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010111
assign \rc_sel 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100110
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100111
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101100
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101101
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100100
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100101
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001000
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'000010
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'000011
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011010
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011011
assign \rc_sel 2'00
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch$1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 32'000000---------------0100000000-
assign \rc_sel 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 32'01100000000000000000000000000000
assign \rc_sel 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 32'000001---------------0000000011-
assign \rc_sel 2'00
end
end
process $group_16
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
case 6'010011
assign \ldst_len \dec19_ldst_len
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
case 6'011110
assign \ldst_len \dec30_ldst_len
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
case 6'011111
assign \ldst_len \dec31_ldst_len
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
case 6'111010
assign \ldst_len \dec58_ldst_len
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
case 6'111110
assign \ldst_len \dec62_ldst_len
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001100
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001101
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001110
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001111
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010001
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011100
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011101
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010010
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010000
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001011
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001010
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100010
assign \ldst_len 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100011
assign \ldst_len 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101010
assign \ldst_len 4'0010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101011
assign \ldst_len 4'0010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101000
assign \ldst_len 4'0010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101001
assign \ldst_len 4'0010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100000
assign \ldst_len 4'0100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100001
assign \ldst_len 4'0100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'000111
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011000
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011001
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010100
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010101
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010111
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100110
assign \ldst_len 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100111
assign \ldst_len 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101100
assign \ldst_len 4'0010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101101
assign \ldst_len 4'0010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100100
assign \ldst_len 4'0100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100101
assign \ldst_len 4'0100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001000
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'000010
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'000011
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011010
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011011
assign \ldst_len 4'0000
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch$1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 32'000000---------------0100000000-
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 32'01100000000000000000000000000000
assign \ldst_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 32'000001---------------0000000011-
assign \ldst_len 4'0000
end
sync init
end
process $group_17
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+ switch \opcode_switch
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
+ case 6'010011
+ assign \upd \dec19_upd
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
+ case 6'011110
+ assign \upd \dec30_upd
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
+ case 6'011111
+ assign \upd \dec31_upd
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
+ case 6'111010
+ assign \upd \dec58_upd
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
+ case 6'111110
+ assign \upd \dec62_upd
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 6'001100
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 6'001101
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 6'001110
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 6'001111
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 6'010001
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 6'011100
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 6'011101
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 6'010010
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 6'010000
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 6'001011
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 6'001010
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 6'100010
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 6'100011
+ assign \upd 2'01
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 6'101010
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 6'101011
+ assign \upd 2'01
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 6'101000
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 6'101001
+ assign \upd 2'01
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 6'100000
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 6'100001
+ assign \upd 2'01
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 6'000111
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 6'011000
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 6'011001
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 6'010100
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 6'010101
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 6'010111
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 6'100110
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 6'100111
+ assign \upd 2'01
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 6'101100
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 6'101101
+ assign \upd 2'01
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 6'100100
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 6'100101
+ assign \upd 2'01
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 6'001000
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 6'000010
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 6'000011
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 6'011010
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 6'011011
+ assign \upd 2'00
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
+ switch \opcode_switch$1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 32'000000---------------0100000000-
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 32'01100000000000000000000000000000
+ assign \upd 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 32'000001---------------0000000011-
+ assign \upd 2'00
+ end
+ sync init
+ end
+ process $group_18
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
case 6'010011
assign \cry_in \dec19_cry_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
case 6'011110
assign \cry_in \dec30_cry_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
case 6'011111
assign \cry_in \dec31_cry_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
case 6'111010
assign \cry_in \dec58_cry_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
case 6'111110
assign \cry_in \dec62_cry_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001100
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001101
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001110
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001111
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010001
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011100
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011101
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010010
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010000
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001011
assign \cry_in 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001010
assign \cry_in 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100010
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100011
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101010
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101011
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101000
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101001
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100000
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100001
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'000111
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011000
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011001
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010100
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010101
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010111
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100110
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100111
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101100
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101101
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100100
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100101
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001000
assign \cry_in 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'000010
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'000011
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011010
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011011
assign \cry_in 2'00
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch$1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 32'000000---------------0100000000-
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 32'01100000000000000000000000000000
assign \cry_in 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 32'000001---------------0000000011-
assign \cry_in 2'00
end
sync init
end
- process $group_18
+ process $group_19
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
case 6'010011
assign \inv_a \dec19_inv_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
case 6'011110
assign \inv_a \dec30_inv_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
case 6'011111
assign \inv_a \dec31_inv_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
case 6'111010
assign \inv_a \dec58_inv_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
case 6'111110
assign \inv_a \dec62_inv_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001100
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001101
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001110
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001111
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010001
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011100
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011101
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010010
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010000
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001011
assign \inv_a 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001010
assign \inv_a 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100010
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100011
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101010
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101011
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101000
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101001
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100000
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100001
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'000111
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011000
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011001
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010100
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010101
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010111
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100110
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100111
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101100
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101101
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100100
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100101
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001000
assign \inv_a 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'000010
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'000011
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011010
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011011
assign \inv_a 1'0
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch$1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 32'000000---------------0100000000-
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 32'01100000000000000000000000000000
assign \inv_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 32'000001---------------0000000011-
assign \inv_a 1'0
end
sync init
end
- process $group_19
+ process $group_20
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
case 6'010011
assign \inv_out \dec19_inv_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
case 6'011110
assign \inv_out \dec30_inv_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
case 6'011111
assign \inv_out \dec31_inv_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
case 6'111010
assign \inv_out \dec58_inv_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
case 6'111110
assign \inv_out \dec62_inv_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001100
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001101
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001110
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001111
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010001
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011100
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011101
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010010
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010000
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001011
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001010
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100010
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100011
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101010
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101011
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101000
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101001
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100000
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100001
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'000111
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011000
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011001
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010100
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010101
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010111
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100110
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100111
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101100
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101101
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100100
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100101
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001000
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'000010
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'000011
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011010
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011011
assign \inv_out 1'0
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch$1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 32'000000---------------0100000000-
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 32'01100000000000000000000000000000
assign \inv_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 32'000001---------------0000000011-
assign \inv_out 1'0
end
sync init
end
- process $group_20
+ process $group_21
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
case 6'010011
assign \cry_out \dec19_cry_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
case 6'011110
assign \cry_out \dec30_cry_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
case 6'011111
assign \cry_out \dec31_cry_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
case 6'111010
assign \cry_out \dec58_cry_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
case 6'111110
assign \cry_out \dec62_cry_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001100
assign \cry_out 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001101
assign \cry_out 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001110
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001111
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010001
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011100
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011101
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010010
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010000
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001011
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001010
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100010
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100011
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101010
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101011
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101000
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101001
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100000
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100001
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'000111
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011000
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011001
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010100
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010101
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010111
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100110
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100111
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101100
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101101
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100100
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100101
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001000
assign \cry_out 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'000010
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'000011
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011010
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011011
assign \cry_out 1'0
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch$1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 32'000000---------------0100000000-
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 32'01100000000000000000000000000000
assign \cry_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 32'000001---------------0000000011-
assign \cry_out 1'0
end
sync init
end
- process $group_21
+ process $group_22
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
case 6'010011
assign \br \dec19_br
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
case 6'011110
assign \br \dec30_br
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
case 6'011111
assign \br \dec31_br
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
case 6'111010
assign \br \dec58_br
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
case 6'111110
assign \br \dec62_br
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001100
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001101
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001110
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001111
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010001
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011100
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011101
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010010
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010000
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001011
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001010
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100010
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100011
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101010
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101011
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101000
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101001
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100000
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100001
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'000111
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011000
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011001
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010100
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010101
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010111
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100110
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100111
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101100
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101101
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100100
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100101
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001000
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'000010
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'000011
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011010
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011011
assign \br 1'0
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch$1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 32'000000---------------0100000000-
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 32'01100000000000000000000000000000
assign \br 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 32'000001---------------0000000011-
assign \br 1'0
end
sync init
end
- process $group_22
+ process $group_23
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
case 6'010011
assign \sgn_ext \dec19_sgn_ext
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
case 6'011110
assign \sgn_ext \dec30_sgn_ext
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
case 6'011111
assign \sgn_ext \dec31_sgn_ext
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
case 6'111010
assign \sgn_ext \dec58_sgn_ext
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
case 6'111110
assign \sgn_ext \dec62_sgn_ext
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001100
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001101
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001110
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001111
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010001
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011100
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011101
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010010
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010000
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001011
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001010
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100010
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100011
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101010
assign \sgn_ext 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101011
assign \sgn_ext 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101000
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101001
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100000
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100001
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'000111
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011000
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011001
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010100
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010101
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010111
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100110
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100111
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101100
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101101
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100100
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100101
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001000
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'000010
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'000011
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011010
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011011
assign \sgn_ext 1'0
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch$1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 32'000000---------------0100000000-
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 32'01100000000000000000000000000000
assign \sgn_ext 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 32'000001---------------0000000011-
assign \sgn_ext 1'0
end
sync init
end
- process $group_23
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
- switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
- case 6'010011
- assign \upd \dec19_upd
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
- case 6'011110
- assign \upd \dec30_upd
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
- case 6'011111
- assign \upd \dec31_upd
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
- case 6'111010
- assign \upd \dec58_upd
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
- case 6'111110
- assign \upd \dec62_upd
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 6'001100
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 6'001101
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 6'001110
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 6'001111
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 6'010001
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 6'011100
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 6'011101
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 6'010010
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 6'010000
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 6'001011
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 6'001010
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 6'100010
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 6'100011
- assign \upd 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 6'101010
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 6'101011
- assign \upd 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 6'101000
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 6'101001
- assign \upd 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 6'100000
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 6'100001
- assign \upd 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 6'000111
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 6'011000
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 6'011001
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 6'010100
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 6'010101
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 6'010111
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 6'100110
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 6'100111
- assign \upd 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 6'101100
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 6'101101
- assign \upd 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 6'100100
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 6'100101
- assign \upd 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 6'001000
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 6'000010
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 6'000011
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 6'011010
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 6'011011
- assign \upd 1'0
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
- switch \opcode_switch$1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 32'000000---------------0100000000-
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 32'01100000000000000000000000000000
- assign \upd 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 32'000001---------------0000000011-
- assign \upd 1'0
- end
- sync init
- end
process $group_24
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
case 6'010011
assign \rsrv \dec19_rsrv
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
case 6'011110
assign \rsrv \dec30_rsrv
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
case 6'011111
assign \rsrv \dec31_rsrv
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
case 6'111010
assign \rsrv \dec58_rsrv
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
case 6'111110
assign \rsrv \dec62_rsrv
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001100
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001101
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001110
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001111
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010001
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011100
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011101
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010010
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010000
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001011
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001010
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100010
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100011
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101010
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101011
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101000
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101001
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100000
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100001
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'000111
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011000
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011001
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010100
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010101
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010111
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100110
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100111
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101100
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101101
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100100
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100101
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001000
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'000010
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'000011
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011010
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011011
assign \rsrv 1'0
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch$1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 32'000000---------------0100000000-
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 32'01100000000000000000000000000000
assign \rsrv 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 32'000001---------------0000000011-
assign \rsrv 1'0
end
end
process $group_25
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
case 6'010011
assign \is_32b \dec19_is_32b
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
case 6'011110
assign \is_32b \dec30_is_32b
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
case 6'011111
assign \is_32b \dec31_is_32b
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
case 6'111010
assign \is_32b \dec58_is_32b
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
case 6'111110
assign \is_32b \dec62_is_32b
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001100
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001101
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001110
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001111
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010001
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011100
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011101
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010010
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010000
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001011
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001010
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100010
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100011
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101010
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101011
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101000
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101001
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100000
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100001
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'000111
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011000
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011001
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010100
assign \is_32b 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010101
assign \is_32b 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010111
assign \is_32b 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100110
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100111
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101100
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101101
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100100
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100101
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001000
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'000010
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'000011
assign \is_32b 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011010
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011011
assign \is_32b 1'0
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch$1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 32'000000---------------0100000000-
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 32'01100000000000000000000000000000
assign \is_32b 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 32'000001---------------0000000011-
assign \is_32b 1'0
end
end
process $group_26
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
case 6'010011
assign \sgn \dec19_sgn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
case 6'011110
assign \sgn \dec30_sgn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
case 6'011111
assign \sgn \dec31_sgn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
case 6'111010
assign \sgn \dec58_sgn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
case 6'111110
assign \sgn \dec62_sgn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001100
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001101
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001110
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001111
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010001
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011100
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011101
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010010
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010000
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001011
assign \sgn 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001010
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100010
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100011
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101010
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101011
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101000
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101001
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100000
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100001
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'000111
assign \sgn 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011000
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011001
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010100
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010101
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010111
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100110
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100111
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101100
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101101
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100100
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100101
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001000
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'000010
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'000011
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011010
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011011
assign \sgn 1'0
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch$1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 32'000000---------------0100000000-
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 32'01100000000000000000000000000000
assign \sgn 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 32'000001---------------0000000011-
assign \sgn 1'0
end
end
process $group_27
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
case 6'010011
assign \lk \dec19_lk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
case 6'011110
assign \lk \dec30_lk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
case 6'011111
assign \lk \dec31_lk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
case 6'111010
assign \lk \dec58_lk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
case 6'111110
assign \lk \dec62_lk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001100
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001101
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001110
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001111
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010001
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011100
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011101
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010010
assign \lk 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010000
assign \lk 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001011
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001010
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100010
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100011
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101010
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101011
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101000
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101001
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100000
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100001
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'000111
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011000
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011001
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010100
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010101
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010111
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100110
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100111
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101100
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101101
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100100
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100101
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001000
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'000010
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'000011
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011010
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011011
assign \lk 1'0
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch$1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 32'000000---------------0100000000-
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 32'01100000000000000000000000000000
assign \lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 32'000001---------------0000000011-
assign \lk 1'0
end
end
process $group_28
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
case 6'010011
assign \sgl_pipe \dec19_sgl_pipe
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
case 6'011110
assign \sgl_pipe \dec30_sgl_pipe
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
case 6'011111
assign \sgl_pipe \dec31_sgl_pipe
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
case 6'111010
assign \sgl_pipe \dec58_sgl_pipe
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
case 6'111110
assign \sgl_pipe \dec62_sgl_pipe
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001100
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001101
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001110
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001111
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010001
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011100
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011101
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010010
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010000
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001011
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001010
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100010
assign \sgl_pipe 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100011
assign \sgl_pipe 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101010
assign \sgl_pipe 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101011
assign \sgl_pipe 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101000
assign \sgl_pipe 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101001
assign \sgl_pipe 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100000
assign \sgl_pipe 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100001
assign \sgl_pipe 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'000111
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011000
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011001
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010100
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010101
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010111
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100110
assign \sgl_pipe 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100111
assign \sgl_pipe 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101100
assign \sgl_pipe 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101101
assign \sgl_pipe 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100100
assign \sgl_pipe 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100101
assign \sgl_pipe 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001000
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'000010
assign \sgl_pipe 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'000011
assign \sgl_pipe 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011010
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011011
assign \sgl_pipe 1'0
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch$1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 32'000000---------------0100000000-
assign \sgl_pipe 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 32'01100000000000000000000000000000
assign \sgl_pipe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 32'000001---------------0000000011-
assign \sgl_pipe 1'1
end
end
process $group_29
assign \asmcode 8'00000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
case 6'010011
assign \asmcode \dec19_asmcode
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
case 6'011110
assign \asmcode \dec30_asmcode
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
case 6'011111
assign \asmcode \dec31_asmcode
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
case 6'111010
assign \asmcode \dec58_asmcode
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:309"
case 6'111110
assign \asmcode \dec62_asmcode
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001100
assign \asmcode 8'00000111
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001101
assign \asmcode 8'00001000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001110
assign \asmcode 8'00000110
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001111
assign \asmcode 8'00001001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011100
assign \asmcode 8'00010001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011101
assign \asmcode 8'00010010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010010
assign \asmcode 8'00010100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010000
assign \asmcode 8'00010101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001011
assign \asmcode 8'00011101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001010
assign \asmcode 8'00011111
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100010
assign \asmcode 8'01001101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100011
assign \asmcode 8'01001110
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101010
assign \asmcode 8'01010111
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101011
assign \asmcode 8'01011001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101000
assign \asmcode 8'01011101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101001
assign \asmcode 8'01011110
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100000
assign \asmcode 8'01100110
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100001
assign \asmcode 8'01100111
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'000111
- assign \asmcode 8'01111101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ assign \asmcode 8'01111110
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011000
- assign \asmcode 8'10000111
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 6'011001
assign \asmcode 8'10001000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 6'011001
+ assign \asmcode 8'10001001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'010100
- assign \asmcode 8'10010101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 6'010101
assign \asmcode 8'10010110
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 6'010111
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 6'010101
assign \asmcode 8'10010111
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 6'010111
+ assign \asmcode 8'10011000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100110
- assign \asmcode 8'10100010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ assign \asmcode 8'10100011
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100111
- assign \asmcode 8'10100100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ assign \asmcode 8'10100101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101100
- assign \asmcode 8'10101101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ assign \asmcode 8'10101110
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'101101
- assign \asmcode 8'10110000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ assign \asmcode 8'10110001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100100
- assign \asmcode 8'10110011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ assign \asmcode 8'10110100
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'100101
- assign \asmcode 8'10110110
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ assign \asmcode 8'10110111
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'001000
- assign \asmcode 8'10111110
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ assign \asmcode 8'10111111
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'000010
- assign \asmcode 8'11000110
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ assign \asmcode 8'11000111
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'000011
- assign \asmcode 8'11001000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ assign \asmcode 8'11001001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 6'011010
- assign \asmcode 8'11001010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
- case 6'011011
assign \asmcode 8'11001011
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
+ case 6'011011
+ assign \asmcode 8'11001100
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:279"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:289"
switch \opcode_switch$1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 32'000000---------------0100000000-
assign \asmcode 8'00010011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 32'01100000000000000000000000000000
- assign \asmcode 8'10000011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:288"
+ assign \asmcode 8'10000100
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:298"
case 32'000001---------------0000000011-
- assign \asmcode 8'10011001
+ assign \asmcode 8'10011010
end
sync init
end
assign \opcode_switch$1 \opcode_in
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:361"
wire width 32 $2
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:361"
cell $mux $3
parameter \WIDTH 32
- connect \A { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] }
- connect \B \raw_opcode_in
+ connect \A \raw_opcode_in
+ connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] }
connect \S \bigendian
connect \Y $2
end
assign \UI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
wire width 1 \L
process $group_38
assign \L 1'0
assign \sh { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
wire width 5 \MB32
process $group_41
assign \MB32 5'00000
assign \MB32 { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
wire width 5 \ME32
process $group_42
assign \ME32 5'00000
assign \LK { \opcode_in [0] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
wire width 1 \AA
process $group_45
assign \AA 1'0
assign \BD { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
wire width 3 \BF
process $group_49
assign \BF 3'000
assign \BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
wire width 10 \CR
process $group_50
assign \CR 10'0000000000
assign \BT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
wire width 8 \FXM
process $group_54
assign \FXM 8'00000000
assign \BI { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
wire width 2 \BH
process $group_57
assign \BH 2'00
assign \BH { \opcode_in [12] \opcode_in [11] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
wire width 16 \D
process $group_58
assign \D 16'0000000000000000
assign \DS { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
wire width 5 \TO
process $group_60
assign \TO 5'00000
assign \BC { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
wire width 5 \SH
process $group_62
assign \SH 5'00000
assign \SH { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
wire width 5 \ME
process $group_63
assign \ME 5'00000
assign \ME { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
wire width 5 \MB
process $group_64
assign \MB 5'00000
assign \SPR { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 1 \X_A
process $group_66
assign \X_A 1'0
assign \X_BFA { \opcode_in [20] \opcode_in [19] \opcode_in [18] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 \X_BO
process $group_69
assign \X_BO 5'00000
assign \X_BO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 4 \X_CT
process $group_70
assign \X_CT 4'0000
assign \X_CT { \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 7 \X_DCMX
process $group_71
assign \X_DCMX 7'0000000
assign \X_DCMX { \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 3 \X_DRM
process $group_72
assign \X_DRM 3'000
assign \X_DRM { \opcode_in [13] \opcode_in [12] \opcode_in [11] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 1 \X_E
process $group_73
assign \X_E 1'0
assign \X_E { \opcode_in [15] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 4 \X_E_1
process $group_74
assign \X_E_1 4'0000
assign \X_E_1 { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 2 \X_EO
process $group_75
assign \X_EO 2'00
assign \X_EO { \opcode_in [20] \opcode_in [19] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 \X_EO_1
process $group_76
assign \X_EO_1 5'00000
assign \X_EO_1 { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 1 \X_EX
process $group_77
assign \X_EX 1'0
assign \X_EX { \opcode_in [0] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 \X_FC
process $group_78
assign \X_FC 5'00000
assign \X_FC { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 \X_FRA
process $group_79
assign \X_FRA 5'00000
assign \X_FRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 \X_FRAp
process $group_80
assign \X_FRAp 5'00000
assign \X_FRAp { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 \X_FRB
process $group_81
assign \X_FRB 5'00000
assign \X_FRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 \X_FRBp
process $group_82
assign \X_FRBp 5'00000
assign \X_FRBp { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 \X_FRS
process $group_83
assign \X_FRS 5'00000
assign \X_FRS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 \X_FRSp
process $group_84
assign \X_FRSp 5'00000
assign \X_FRSp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 \X_FRT
process $group_85
assign \X_FRT 5'00000
assign \X_FRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 \X_FRTp
process $group_86
assign \X_FRTp 5'00000
assign \X_FRTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 3 \X_IH
process $group_87
assign \X_IH 3'000
assign \X_IH { \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 8 \X_IMM8
process $group_88
assign \X_IMM8 8'00000000
assign \X_IMM8 { \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 2 \X_L
process $group_89
assign \X_L 2'00
assign \X_L { \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 1 \X_L_1
process $group_90
assign \X_L_1 1'0
assign \X_L_1 { \opcode_in [21] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 1 \X_L_2
process $group_91
assign \X_L_2 1'0
assign \X_L_2 { \opcode_in [16] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 2 \X_L_3
process $group_92
assign \X_L_3 2'00
assign \X_L_3 { \opcode_in [17] \opcode_in [16] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 \X_MO
process $group_93
assign \X_MO 5'00000
assign \X_MO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 \X_NB
process $group_94
assign \X_NB 5'00000
assign \X_NB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 1 \X_PRS
process $group_95
assign \X_PRS 1'0
assign \X_PRS { \opcode_in [17] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 1 \X_R
process $group_96
assign \X_R 1'0
assign \X_R { \opcode_in [21] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 1 \X_R_1
process $group_97
assign \X_R_1 1'0
assign \X_R_1 { \opcode_in [16] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 \X_RA
process $group_98
assign \X_RA 5'00000
assign \X_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 \X_RB
process $group_99
assign \X_RB 5'00000
assign \X_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 1 \X_Rc
process $group_100
assign \X_Rc 1'0
assign \X_Rc { \opcode_in [0] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 2 \X_RIC
process $group_101
assign \X_RIC 2'00
assign \X_RIC { \opcode_in [19] \opcode_in [18] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 2 \X_RM
process $group_102
assign \X_RM 2'00
assign \X_RM { \opcode_in [12] \opcode_in [11] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 1 \X_RO
process $group_103
assign \X_RO 1'0
assign \X_RO { \opcode_in [0] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 \X_RS
process $group_104
assign \X_RS 5'00000
assign \X_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 \X_RSp
process $group_105
assign \X_RSp 5'00000
assign \X_RSp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 \X_RT
process $group_106
assign \X_RT 5'00000
assign \X_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 \X_RTp
process $group_107
assign \X_RTp 5'00000
assign \X_RTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 \X_S
process $group_108
assign \X_S 5'00000
assign \X_S { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 \X_SH
process $group_109
assign \X_SH 5'00000
assign \X_SH { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 \X_SI
process $group_110
assign \X_SI 5'00000
assign \X_SI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 2 \X_SP
process $group_111
assign \X_SP 2'00
assign \X_SP { \opcode_in [20] \opcode_in [19] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 4 \X_SR
process $group_112
assign \X_SR 4'0000
assign \X_SR { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 1 \X_SX
process $group_113
assign \X_SX 1'0
assign \X_SX { \opcode_in [0] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 6 \X_SX_S
process $group_114
assign \X_SX_S 6'000000
assign \X_SX_S { \opcode_in [0] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 \X_T
process $group_115
assign \X_T 5'00000
assign \X_T { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 10 \X_TBR
process $group_116
assign \X_TBR 10'0000000000
assign \X_TBR { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 \X_TH
process $group_117
assign \X_TH 5'00000
assign \X_TH { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 \X_TO
process $group_118
assign \X_TO 5'00000
assign \X_TO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 1 \X_TX
process $group_119
assign \X_TX 1'0
assign \X_TX { \opcode_in [0] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 6 \X_TX_T
process $group_120
assign \X_TX_T 6'000000
assign \X_TX_T { \opcode_in [0] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 4 \X_U
process $group_121
assign \X_U 4'0000
assign \X_U { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 \X_UIM
process $group_122
assign \X_UIM 5'00000
assign \X_UIM { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 \X_VRS
process $group_123
assign \X_VRS 5'00000
assign \X_VRS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 \X_VRT
process $group_124
assign \X_VRT 5'00000
assign \X_VRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 1 \X_W
process $group_125
assign \X_W 1'0
assign \X_W { \opcode_in [16] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 2 \X_WC
process $group_126
assign \X_WC 2'00
assign \X_WC { \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 10 \X_XO
process $group_127
assign \X_XO 10'0000000000
assign \X_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 8 \X_XO_1
process $group_128
assign \X_XO_1 8'00000000
assign \X_XO_1 { \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 1 \B_AA
process $group_129
assign \B_AA 1'0
assign \B_AA { \opcode_in [1] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 14 \B_BD
process $group_130
assign \B_BD 14'00000000000000
assign \B_BD { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 \B_BI
process $group_131
assign \B_BI 5'00000
assign \B_BI { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 \B_BO
process $group_132
assign \B_BO 5'00000
assign \B_BO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 1 \B_LK
process $group_133
assign \B_LK 1'0
assign \B_LK { \opcode_in [0] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 1 \I_AA
process $group_134
assign \I_AA 1'0
assign \I_AA { \opcode_in [1] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 24 \I_LI
process $group_135
assign \I_LI 24'000000000000000000000000
assign \I_LI { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 1 \I_LK
process $group_136
assign \I_LK 1'0
assign \I_LK { \opcode_in [0] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 1 \XX3_AX
process $group_137
assign \XX3_AX 1'0
assign \XX3_AX { \opcode_in [2] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 \XX3_A
process $group_138
assign \XX3_A 5'00000
assign \XX3_A { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 6 \XX3_AX_A
process $group_139
assign \XX3_AX_A 6'000000
assign \XX3_AX_A { \opcode_in [2] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 3 \XX3_BF
process $group_140
assign \XX3_BF 3'000
assign \XX3_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 1 \XX3_BX
process $group_141
assign \XX3_BX 1'0
assign \XX3_BX { \opcode_in [1] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 \XX3_B
process $group_142
assign \XX3_B 5'00000
assign \XX3_B { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 6 \XX3_BX_B
process $group_143
assign \XX3_BX_B 6'000000
assign \XX3_BX_B { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 2 \XX3_DM
process $group_144
assign \XX3_DM 2'00
assign \XX3_DM { \opcode_in [9] \opcode_in [8] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 1 \XX3_Rc
process $group_145
assign \XX3_Rc 1'0
assign \XX3_Rc { \opcode_in [10] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 2 \XX3_SHW
process $group_146
assign \XX3_SHW 2'00
assign \XX3_SHW { \opcode_in [9] \opcode_in [8] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 1 \XX3_TX
process $group_147
assign \XX3_TX 1'0
assign \XX3_TX { \opcode_in [0] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 \XX3_T
process $group_148
assign \XX3_T 5'00000
assign \XX3_T { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 6 \XX3_TX_T
process $group_149
assign \XX3_TX_T 6'000000
assign \XX3_TX_T { \opcode_in [0] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 4 \XX3_XO
process $group_150
assign \XX3_XO 4'0000
assign \XX3_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 8 \XX3_XO_1
process $group_151
assign \XX3_XO_1 8'00000000
assign \XX3_XO_1 { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 9 \XX3_XO_2
process $group_152
assign \XX3_XO_2 9'000000000
assign \XX3_XO_2 { \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 1 \XX4_AX
process $group_153
assign \XX4_AX 1'0
assign \XX4_AX { \opcode_in [2] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 \XX4_A
process $group_154
assign \XX4_A 5'00000
assign \XX4_A { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 6 \XX4_AX_A
process $group_155
assign \XX4_AX_A 6'000000
assign \XX4_AX_A { \opcode_in [2] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 1 \XX4_BX
process $group_156
assign \XX4_BX 1'0
assign \XX4_BX { \opcode_in [1] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 \XX4_B
process $group_157
assign \XX4_B 5'00000
assign \XX4_B { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 6 \XX4_BX_B
process $group_158
assign \XX4_BX_B 6'000000
assign \XX4_BX_B { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 1 \XX4_CX
process $group_159
assign \XX4_CX 1'0
assign \XX4_CX { \opcode_in [3] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 \XX4_C
process $group_160
assign \XX4_C 5'00000
assign \XX4_C { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 6 \XX4_CX_C
process $group_161
assign \XX4_CX_C 6'000000
assign \XX4_CX_C { \opcode_in [3] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 1 \XX4_TX
process $group_162
assign \XX4_TX 1'0
assign \XX4_TX { \opcode_in [0] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 \XX4_T
process $group_163
assign \XX4_T 5'00000
assign \XX4_T { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 6 \XX4_TX_T
process $group_164
assign \XX4_TX_T 6'000000
assign \XX4_TX_T { \opcode_in [0] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 2 \XX4_XO
process $group_165
assign \XX4_XO 2'00
assign \XX4_XO { \opcode_in [5] \opcode_in [4] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 \XL_BA
process $group_166
assign \XL_BA 5'00000
assign \XL_BA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 \XL_BB
process $group_167
assign \XL_BB 5'00000
assign \XL_BB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 3 \XL_BF
process $group_168
assign \XL_BF 3'000
assign \XL_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 3 \XL_BFA
process $group_169
assign \XL_BFA 3'000
assign \XL_BFA { \opcode_in [20] \opcode_in [19] \opcode_in [18] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 2 \XL_BH
process $group_170
assign \XL_BH 2'00
assign \XL_BH { \opcode_in [12] \opcode_in [11] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 \XL_BI
process $group_171
assign \XL_BI 5'00000
assign \XL_BI { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 \XL_BO
process $group_172
assign \XL_BO 5'00000
assign \XL_BO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 \XL_BO_1
process $group_173
assign \XL_BO_1 5'00000
assign \XL_BT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 1 \XL_LK
process $group_175
assign \XL_LK 1'0
assign \XL_LK { \opcode_in [0] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 15 \XL_OC
process $group_176
assign \XL_OC 15'000000000000000
assign \XL_OC { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 1 \XL_S
process $group_177
assign \XL_S 1'0
assign \XL_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 \A_BC
process $group_179
assign \A_BC 5'00000
assign \A_BC { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 \A_FRA
process $group_180
assign \A_FRA 5'00000
assign \A_FRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 \A_FRB
process $group_181
assign \A_FRB 5'00000
assign \A_FRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 \A_FRC
process $group_182
assign \A_FRC 5'00000
assign \A_FRC { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 \A_FRT
process $group_183
assign \A_FRT 5'00000
assign \A_FRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 \A_RA
process $group_184
assign \A_RA 5'00000
assign \A_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 \A_RB
process $group_185
assign \A_RB 5'00000
assign \A_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 1 \A_Rc
process $group_186
assign \A_Rc 1'0
assign \A_Rc { \opcode_in [0] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 \A_RT
process $group_187
assign \A_RT 5'00000
assign \A_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 \A_XO
process $group_188
assign \A_XO 5'00000
assign \A_XO { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 3 \D_BF
process $group_189
assign \D_BF 3'000
assign \D_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 16 \D_D
process $group_190
assign \D_D 16'0000000000000000
assign \D_D { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 \D_FRS
process $group_191
assign \D_FRS 5'00000
assign \D_FRS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 \D_FRT
process $group_192
assign \D_FRT 5'00000
assign \D_FRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 1 \D_L
process $group_193
assign \D_L 1'0
assign \D_L { \opcode_in [21] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 \D_RA
process $group_194
assign \D_RA 5'00000
assign \D_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 \D_RS
process $group_195
assign \D_RS 5'00000
assign \D_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 \D_RT
process $group_196
assign \D_RT 5'00000
assign \D_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 16 \D_SI
process $group_197
assign \D_SI 16'0000000000000000
assign \D_SI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 \D_TO
process $group_198
assign \D_TO 5'00000
assign \D_TO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 16 \D_UI
process $group_199
assign \D_UI 16'0000000000000000
assign \D_UI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 3 \XX2_BF
process $group_200
assign \XX2_BF 3'000
assign \XX2_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 1 \XX2_BX
process $group_201
assign \XX2_BX 1'0
assign \XX2_BX { \opcode_in [1] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 \XX2_B
process $group_202
assign \XX2_B 5'00000
assign \XX2_B { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 6 \XX2_BX_B
process $group_203
assign \XX2_BX_B 6'000000
assign \XX2_BX_B { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 1 \XX2_dc
process $group_204
assign \XX2_dc 1'0
assign \XX2_dc { \opcode_in [6] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 1 \XX2_dm
process $group_205
assign \XX2_dm 1'0
assign \XX2_dm { \opcode_in [2] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 \XX2_dx
process $group_206
assign \XX2_dx 5'00000
assign \XX2_dx { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 7 \XX2_dc_dm_dx
process $group_207
assign \XX2_dc_dm_dx 7'0000000
assign \XX2_dc_dm_dx { \opcode_in [6] \opcode_in [2] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 7 \XX2_DCMX
process $group_208
assign \XX2_DCMX 7'0000000
assign \XX2_DCMX { \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 \XX2_EO
process $group_209
assign \XX2_EO 5'00000
assign \XX2_EO { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 \XX2_RT
process $group_210
assign \XX2_RT 5'00000
assign \XX2_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 1 \XX2_TX
process $group_211
assign \XX2_TX 1'0
assign \XX2_TX { \opcode_in [0] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 \XX2_T
process $group_212
assign \XX2_T 5'00000
assign \XX2_T { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 6 \XX2_TX_T
process $group_213
assign \XX2_TX_T 6'000000
assign \XX2_TX_T { \opcode_in [0] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 4 \XX2_UIM
process $group_214
assign \XX2_UIM 4'0000
assign \XX2_UIM { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 2 \XX2_UIM_1
process $group_215
assign \XX2_UIM_1 2'00
assign \XX2_UIM_1 { \opcode_in [17] \opcode_in [16] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 7 \XX2_XO
process $group_216
assign \XX2_XO 7'0000000
assign \XX2_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [5] \opcode_in [4] \opcode_in [3] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 9 \XX2_XO_1
process $group_217
assign \XX2_XO_1 9'000000000
assign \XX2_XO_1 { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 3 \Z22_BF
process $group_218
assign \Z22_BF 3'000
assign \Z22_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 6 \Z22_DCM
process $group_219
assign \Z22_DCM 6'000000
assign \Z22_DCM { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 6 \Z22_DGM
process $group_220
assign \Z22_DGM 6'000000
assign \Z22_DGM { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 \Z22_FRA
process $group_221
assign \Z22_FRA 5'00000
assign \Z22_FRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 \Z22_FRAp
process $group_222
assign \Z22_FRAp 5'00000
assign \Z22_FRAp { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 \Z22_FRT
process $group_223
assign \Z22_FRT 5'00000
assign \Z22_FRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 \Z22_FRTp
process $group_224
assign \Z22_FRTp 5'00000
assign \Z22_FRTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 1 \Z22_Rc
process $group_225
assign \Z22_Rc 1'0
assign \Z22_Rc { \opcode_in [0] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 6 \Z22_SH
process $group_226
assign \Z22_SH 6'000000
assign \Z22_SH { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 9 \Z22_XO
process $group_227
assign \Z22_XO 9'000000000
assign \Z22_XO { \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 3 \EVS_BFA
process $group_228
assign \EVS_BFA 3'000
assign \EVS_BFA { \opcode_in [2] \opcode_in [1] \opcode_in [0] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 10 \XFX_BHRBE
process $group_229
assign \XFX_BHRBE 10'0000000000
assign \XFX_BHRBE { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 \XFX_DUI
process $group_230
assign \XFX_DUI 5'00000
assign \XFX_DUI { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 10 \XFX_DUIS
process $group_231
assign \XFX_DUIS 10'0000000000
assign \XFX_DUIS { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 8 \XFX_FXM
process $group_232
assign \XFX_FXM 8'00000000
assign \XFX_FXM { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 \XFX_RS
process $group_233
assign \XFX_RS 5'00000
assign \XFX_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 \XFX_RT
process $group_234
assign \XFX_RT 5'00000
assign \XFX_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 10 \XFX_SPR
process $group_235
assign \XFX_SPR 10'0000000000
assign \XFX_SPR { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 10 \XFX_XO
process $group_236
assign \XFX_XO 10'0000000000
assign \XFX_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 10 \DX_d0
process $group_237
assign \DX_d0 10'0000000000
assign \DX_d0 { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 \DX_d1
process $group_238
assign \DX_d1 5'00000
assign \DX_d1 { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 1 \DX_d2
process $group_239
assign \DX_d2 1'0
assign \DX_d2 { \opcode_in [0] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 16 \DX_d0_d1_d2
process $group_240
assign \DX_d0_d1_d2 16'0000000000000000
assign \DX_d0_d1_d2 { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [0] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 \DX_RT
process $group_241
assign \DX_RT 5'00000
assign \DX_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 \DX_XO
process $group_242
assign \DX_XO 5'00000
assign \DX_XO { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 12 \DQ_DQ
process $group_243
assign \DQ_DQ 12'000000000000
assign \DQ_DQ { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 4 \DQ_PT
process $group_244
assign \DQ_PT 4'0000
assign \DQ_PT { \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 \DQ_RA
process $group_245
assign \DQ_RA 5'00000
assign \DQ_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 \DQ_RTp
process $group_246
assign \DQ_RTp 5'00000
assign \DQ_RTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 1 \DQ_SX
process $group_247
assign \DQ_SX 1'0
assign \DQ_SX { \opcode_in [3] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 \DQ_S
process $group_248
assign \DQ_S 5'00000
assign \DQ_S { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 6 \DQ_SX_S
process $group_249
assign \DQ_SX_S 6'000000
assign \DQ_SX_S { \opcode_in [3] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 1 \DQ_TX
process $group_250
assign \DQ_TX 1'0
assign \DQ_TX { \opcode_in [3] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 \DQ_T
process $group_251
assign \DQ_T 5'00000
assign \DQ_T { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 6 \DQ_TX_T
process $group_252
assign \DQ_TX_T 6'000000
assign \DQ_TX_T { \opcode_in [3] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 3 \DQ_XO
process $group_253
assign \DQ_XO 3'000
assign \DQ_XO { \opcode_in [2] \opcode_in [1] \opcode_in [0] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 14 \DS_DS
process $group_254
assign \DS_DS 14'00000000000000
assign \DS_DS { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 \DS_FRSp
process $group_255
assign \DS_FRSp 5'00000
assign \DS_FRSp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 \DS_FRTp
process $group_256
assign \DS_FRTp 5'00000
assign \DS_FRTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 \DS_RA
process $group_257
assign \DS_RA 5'00000
assign \DS_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 \DS_RS
process $group_258
assign \DS_RS 5'00000
assign \DS_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 \DS_RSp
process $group_259
assign \DS_RSp 5'00000
assign \DS_RSp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 \DS_RT
process $group_260
assign \DS_RT 5'00000
assign \DS_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 \DS_VRS
process $group_261
assign \DS_VRS 5'00000
assign \DS_VRS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 \DS_VRT
process $group_262
assign \DS_VRT 5'00000
assign \DS_VRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 2 \DS_XO
process $group_263
assign \DS_XO 2'00
assign \DS_XO { \opcode_in [1] \opcode_in [0] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 \VX_EO
process $group_264
assign \VX_EO 5'00000
assign \VX_EO { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 1 \VX_PS
process $group_265
assign \VX_PS 1'0
assign \VX_PS { \opcode_in [9] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 \VX_RA
process $group_266
assign \VX_RA 5'00000
assign \VX_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 \VX_RT
process $group_267
assign \VX_RT 5'00000
assign \VX_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 \VX_SIM
process $group_268
assign \VX_SIM 5'00000
assign \VX_SIM { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 \VX_UIM
process $group_269
assign \VX_UIM 5'00000
assign \VX_UIM { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 4 \VX_UIM_1
process $group_270
assign \VX_UIM_1 4'0000
assign \VX_UIM_1 { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 3 \VX_UIM_2
process $group_271
assign \VX_UIM_2 3'000
assign \VX_UIM_2 { \opcode_in [18] \opcode_in [17] \opcode_in [16] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 2 \VX_UIM_3
process $group_272
assign \VX_UIM_3 2'00
assign \VX_UIM_3 { \opcode_in [17] \opcode_in [16] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 \VX_VRA
process $group_273
assign \VX_VRA 5'00000
assign \VX_VRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 \VX_VRB
process $group_274
assign \VX_VRB 5'00000
assign \VX_VRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 \VX_VRT
process $group_275
assign \VX_VRT 5'00000
assign \VX_VRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 10 \VX_XO
process $group_276
assign \VX_XO 10'0000000000
assign \VX_XO { \opcode_in [10] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 11 \VX_XO_1
process $group_277
assign \VX_XO_1 11'00000000000
assign \VX_XO_1 { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 8 \XFL_FLM
process $group_278
assign \XFL_FLM 8'00000000
assign \XFL_FLM { \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 \XFL_FRB
process $group_279
assign \XFL_FRB 5'00000
assign \XFL_FRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 1 \XFL_L
process $group_280
assign \XFL_L 1'0
assign \XFL_L { \opcode_in [25] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 1 \XFL_Rc
process $group_281
assign \XFL_Rc 1'0
assign \XFL_Rc { \opcode_in [0] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 1 \XFL_W
process $group_282
assign \XFL_W 1'0
assign \XFL_W { \opcode_in [16] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 10 \XFL_XO
process $group_283
assign \XFL_XO 10'0000000000
assign \XFL_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 \Z23_FRA
process $group_284
assign \Z23_FRA 5'00000
assign \Z23_FRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 \Z23_FRAp
process $group_285
assign \Z23_FRAp 5'00000
assign \Z23_FRAp { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 \Z23_FRB
process $group_286
assign \Z23_FRB 5'00000
assign \Z23_FRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 \Z23_FRBp
process $group_287
assign \Z23_FRBp 5'00000
assign \Z23_FRBp { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 \Z23_FRT
process $group_288
assign \Z23_FRT 5'00000
assign \Z23_FRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 \Z23_FRTp
process $group_289
assign \Z23_FRTp 5'00000
assign \Z23_FRTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 1 \Z23_R
process $group_290
assign \Z23_R 1'0
assign \Z23_R { \opcode_in [16] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 1 \Z23_Rc
process $group_291
assign \Z23_Rc 1'0
assign \Z23_Rc { \opcode_in [0] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 2 \Z23_RMC
process $group_292
assign \Z23_RMC 2'00
assign \Z23_RMC { \opcode_in [10] \opcode_in [9] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 \Z23_TE
process $group_293
assign \Z23_TE 5'00000
assign \Z23_TE { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 8 \Z23_XO
process $group_294
assign \Z23_XO 8'00000000
assign \Z23_XO { \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 \MDS_IB
process $group_295
assign \MDS_IB 5'00000
assign \MDS_IB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 \MDS_IS
process $group_296
assign \MDS_IS 5'00000
assign \MDS_IS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 6 \MDS_mb
process $group_297
assign \MDS_mb 6'000000
assign \MDS_mb { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 6 \MDS_me
process $group_298
assign \MDS_me 6'000000
assign \MDS_me { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 \MDS_RA
process $group_299
assign \MDS_RA 5'00000
assign \MDS_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 \MDS_RB
process $group_300
assign \MDS_RB 5'00000
assign \MDS_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 1 \MDS_Rc
process $group_301
assign \MDS_Rc 1'0
assign \MDS_Rc { \opcode_in [0] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 \MDS_RS
process $group_302
assign \MDS_RS 5'00000
assign \MDS_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 4 \MDS_XBI
process $group_303
assign \MDS_XBI 4'0000
assign \MDS_XBI { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 4 \MDS_XBI_1
process $group_304
assign \MDS_XBI_1 4'0000
assign \MDS_XBI_1 { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 4 \MDS_XO
process $group_305
assign \MDS_XO 4'0000
assign \MDS_XO { \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 7 \SC_LEV
process $group_306
assign \SC_LEV 7'0000000
assign \SC_LEV { \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 1 \SC_XO
process $group_307
assign \SC_XO 1'0
assign \SC_XO { \opcode_in [1] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 2 \SC_XO_1
process $group_308
assign \SC_XO_1 2'00
assign \SC_XO_1 { \opcode_in [1] \opcode_in [0] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 \M_MB
process $group_309
assign \M_MB 5'00000
assign \M_MB { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 \M_ME
process $group_310
assign \M_ME 5'00000
assign \M_ME { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 \M_RA
process $group_311
assign \M_RA 5'00000
assign \M_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 \M_RB
process $group_312
assign \M_RB 5'00000
assign \M_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 1 \M_Rc
process $group_313
assign \M_Rc 1'0
assign \M_Rc { \opcode_in [0] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 \M_RS
process $group_314
assign \M_RS 5'00000
assign \M_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 \M_SH
process $group_315
assign \M_SH 5'00000
assign \M_SH { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 6 \MD_mb
process $group_316
assign \MD_mb 6'000000
assign \MD_mb { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 6 \MD_me
process $group_317
assign \MD_me 6'000000
assign \MD_me { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 \MD_RA
process $group_318
assign \MD_RA 5'00000
assign \MD_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 1 \MD_Rc
process $group_319
assign \MD_Rc 1'0
assign \MD_Rc { \opcode_in [0] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 \MD_RS
process $group_320
assign \MD_RS 5'00000
assign \MD_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 6 \MD_sh
process $group_321
assign \MD_sh 6'000000
assign \MD_sh { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 3 \MD_XO
process $group_322
assign \MD_XO 3'000
assign \MD_XO { \opcode_in [4] \opcode_in [3] \opcode_in [2] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 6 \all_OPCD
process $group_323
assign \all_OPCD 6'000000
assign \all_OPCD { \opcode_in [31] \opcode_in [30] \opcode_in [29] \opcode_in [28] \opcode_in [27] \opcode_in [26] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 6 \all_PO
process $group_324
assign \all_PO 6'000000
assign \all_PO { \opcode_in [31] \opcode_in [30] \opcode_in [29] \opcode_in [28] \opcode_in [27] \opcode_in [26] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 1 \XO_OE
process $group_325
assign \XO_OE 1'0
assign \XO_OE { \opcode_in [10] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 \XO_RA
process $group_326
assign \XO_RA 5'00000
assign \XO_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 \XO_RB
process $group_327
assign \XO_RB 5'00000
assign \XO_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 1 \XO_Rc
process $group_328
assign \XO_Rc 1'0
assign \XO_Rc { \opcode_in [0] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 \XO_RT
process $group_329
assign \XO_RT 5'00000
assign \XO_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 9 \XO_XO
process $group_330
assign \XO_XO 9'000000000
assign \XO_XO { \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 \DQE_RA
process $group_331
assign \DQE_RA 5'00000
assign \DQE_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 \DQE_RT
process $group_332
assign \DQE_RT 5'00000
assign \DQE_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 2 \DQE_XO
process $group_333
assign \DQE_XO 2'00
assign \DQE_XO { \opcode_in [1] \opcode_in [0] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 \TX_RA
process $group_334
assign \TX_RA 5'00000
assign \TX_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 \TX_UI
process $group_335
assign \TX_UI 5'00000
assign \TX_UI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 4 \TX_XBI
process $group_336
assign \TX_XBI 4'0000
assign \TX_XBI { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 6 \TX_XO
process $group_337
assign \TX_XO 6'000000
assign \TX_XO { \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 \VA_RA
process $group_338
assign \VA_RA 5'00000
assign \VA_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 \VA_RB
process $group_339
assign \VA_RB 5'00000
assign \VA_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 \VA_RC
process $group_340
assign \VA_RC 5'00000
assign \VA_RC { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 \VA_RT
process $group_341
assign \VA_RT 5'00000
assign \VA_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 4 \VA_SHB
process $group_342
assign \VA_SHB 4'0000
assign \VA_SHB { \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 \VA_VRA
process $group_343
assign \VA_VRA 5'00000
assign \VA_VRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 \VA_VRB
process $group_344
assign \VA_VRB 5'00000
assign \VA_VRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 \VA_VRC
process $group_345
assign \VA_VRC 5'00000
assign \VA_VRC { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 \VA_VRT
process $group_346
assign \VA_VRT 5'00000
assign \VA_VRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 6 \VA_XO
process $group_347
assign \VA_XO 6'000000
assign \VA_XO { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 \XS_RA
process $group_348
assign \XS_RA 5'00000
assign \XS_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 1 \XS_Rc
process $group_349
assign \XS_Rc 1'0
assign \XS_Rc { \opcode_in [0] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 \XS_RS
process $group_350
assign \XS_RS 5'00000
assign \XS_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 6 \XS_sh
process $group_351
assign \XS_sh 6'000000
assign \XS_sh { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 9 \XS_XO
process $group_352
assign \XS_XO 9'000000000
assign \XS_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 1 \VC_Rc
process $group_353
assign \VC_Rc 1'0
assign \VC_Rc { \opcode_in [10] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 \VC_VRA
process $group_354
assign \VC_VRA 5'00000
assign \VC_VRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 \VC_VRB
process $group_355
assign \VC_VRB 5'00000
assign \VC_VRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 \VC_VRT
process $group_356
assign \VC_VRT 5'00000
assign \VC_VRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 10 \VC_XO
process $group_357
assign \VC_XO 10'0000000000
attribute \generator "nMigen"
attribute \nmigen.hierarchy "test_issuer.core.pdecode2.dec_a.sprmap"
module \sprmap
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:54"
wire width 10 input 0 \spr_i
attribute \enum_base_type "SPR"
attribute \enum_value_0000000001 "XER"
attribute \enum_value_1110000000 "PPR"
attribute \enum_value_1110000010 "PPR32"
attribute \enum_value_1111111111 "PIR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:60"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:55"
wire width 10 output 1 \spr_o
process $group_0
assign \spr_o 10'0000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:59"
switch \spr_i
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'0000000001
assign \spr_o 10'0000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'0000000011
assign \spr_o 10'0000000001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'0000001000
assign \spr_o 10'0000000010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'0000001001
assign \spr_o 10'0000000011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'0000001101
assign \spr_o 10'0000000100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'0000010001
assign \spr_o 10'0000000101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'0000010010
assign \spr_o 10'0000000110
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'0000010011
assign \spr_o 10'0000000111
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'0000010110
assign \spr_o 10'0000001000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'0000011010
assign \spr_o 10'0000001001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'0000011011
assign \spr_o 10'0000001010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'0000011100
assign \spr_o 10'0000001011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'0000011101
assign \spr_o 10'0000001100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'0000110000
assign \spr_o 10'0000001101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'0000111101
assign \spr_o 10'0000001110
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'0010000000
assign \spr_o 10'0000001111
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'0010000001
assign \spr_o 10'0000010000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'0010000010
assign \spr_o 10'0000010001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'0010000011
assign \spr_o 10'0000010010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'0010001000
assign \spr_o 10'0000010011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'0010010000
assign \spr_o 10'0000010100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'0010011000
assign \spr_o 10'0000010101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'0010011001
assign \spr_o 10'0000010110
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'0010011101
assign \spr_o 10'0000010111
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'0010011110
assign \spr_o 10'0000011000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'0010011111
assign \spr_o 10'0000011001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'0010110000
assign \spr_o 10'0000011010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'0010110100
assign \spr_o 10'0000011011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'0010111010
assign \spr_o 10'0000011100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'0010111011
assign \spr_o 10'0000011101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'0010111100
assign \spr_o 10'0000011110
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'0010111110
assign \spr_o 10'0000011111
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'0100000000
assign \spr_o 10'0000100000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'0100000011
assign \spr_o 10'0000100001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'0100001100
assign \spr_o 10'0000100010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'0100001101
assign \spr_o 10'0000100011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'0100010000
assign \spr_o 10'0000100100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'0100010001
assign \spr_o 10'0000100101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'0100010010
assign \spr_o 10'0000100110
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'0100010011
assign \spr_o 10'0000100111
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'0100011011
assign \spr_o 10'0000101000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'0100011100
assign \spr_o 10'0000101001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'0100011101
assign \spr_o 10'0000101010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'0100011110
assign \spr_o 10'0000101011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'0100011111
assign \spr_o 10'0000101100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'0100110000
assign \spr_o 10'0000101101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'0100110001
assign \spr_o 10'0000101110
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'0100110010
assign \spr_o 10'0000101111
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'0100110011
assign \spr_o 10'0000110000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'0100110100
assign \spr_o 10'0000110001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'0100110101
assign \spr_o 10'0000110010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'0100110110
assign \spr_o 10'0000110011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'0100111001
assign \spr_o 10'0000110100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'0100111010
assign \spr_o 10'0000110101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'0100111011
assign \spr_o 10'0000110110
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'0100111110
assign \spr_o 10'0000110111
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'0100111111
assign \spr_o 10'0000111000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'0101010000
assign \spr_o 10'0000111001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'0101010001
assign \spr_o 10'0000111010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'0101010010
assign \spr_o 10'0000111011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'0101010011
assign \spr_o 10'0000111100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'0101011101
assign \spr_o 10'0000111101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'0110111110
assign \spr_o 10'0000111110
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'0111010000
assign \spr_o 10'0000111111
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'1100000000
assign \spr_o 10'0001000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'1100000001
assign \spr_o 10'0001000001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'1100000010
assign \spr_o 10'0001000010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'1100000011
assign \spr_o 10'0001000011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'1100000100
assign \spr_o 10'0001000100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'1100000101
assign \spr_o 10'0001000101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'1100000110
assign \spr_o 10'0001000110
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'1100000111
assign \spr_o 10'0001000111
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'1100001000
assign \spr_o 10'0001001000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'1100001011
assign \spr_o 10'0001001001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'1100001100
assign \spr_o 10'0001001010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'1100001101
assign \spr_o 10'0001001011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'1100001110
assign \spr_o 10'0001001100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'1100010000
assign \spr_o 10'0001001101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'1100010001
assign \spr_o 10'0001001110
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'1100010010
assign \spr_o 10'0001001111
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'1100010011
assign \spr_o 10'0001010000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'1100010100
assign \spr_o 10'0001010001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'1100010101
assign \spr_o 10'0001010010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'1100010110
assign \spr_o 10'0001010011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'1100010111
assign \spr_o 10'0001010100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'1100011000
assign \spr_o 10'0001010101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'1100011011
assign \spr_o 10'0001010110
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'1100011100
assign \spr_o 10'0001010111
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'1100011101
assign \spr_o 10'0001011000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'1100011110
assign \spr_o 10'0001011001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'1100100000
assign \spr_o 10'0001011010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'1100100001
assign \spr_o 10'0001011011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'1100100010
assign \spr_o 10'0001011100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'1100100011
assign \spr_o 10'0001011101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'1100100100
assign \spr_o 10'0001011110
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'1100100101
assign \spr_o 10'0001011111
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'1100100110
assign \spr_o 10'0001100000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'1100101000
assign \spr_o 10'0001100001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'1100101001
assign \spr_o 10'0001100010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'1100101010
assign \spr_o 10'0001100011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'1100101011
assign \spr_o 10'0001100100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'1100101111
assign \spr_o 10'0001100101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'1100110000
assign \spr_o 10'0001100110
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'1100110111
assign \spr_o 10'0001100111
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'1101010000
assign \spr_o 10'0001101000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'1101010001
assign \spr_o 10'0001101001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'1101010111
assign \spr_o 10'0001101010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'1110000000
assign \spr_o 10'0001101011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'1110000010
assign \spr_o 10'0001101100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'1111111111
assign \spr_o 10'0001101101
end
attribute \enum_value_010 "RA_OR_ZERO"
attribute \enum_value_011 "SPR"
attribute \enum_value_100 "RS"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:80"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:75"
wire width 3 input 0 \sel_in
- attribute \enum_base_type "InternalOp"
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
+ attribute \enum_value_1001010 "OP_MTMSR"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
wire width 7 input 1 \internal_op
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 5 output 2 \reg_a
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 3 \reg_a_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:83"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:78"
wire width 1 output 4 \immz_out
attribute \enum_base_type "SPR"
attribute \enum_value_0000000001 "XER"
wire width 3 output 7 \fast_a
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 8 \fast_a_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
wire width 5 input 9 \RS
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
wire width 5 input 10 \RA
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
wire width 5 input 11 \BO
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
wire width 10 input 12 \SPR
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 10 input 13 \XL_XO
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:54"
wire width 10 \sprmap_spr_i
attribute \enum_base_type "SPR"
attribute \enum_value_0000000001 "XER"
attribute \enum_value_1110000000 "PPR"
attribute \enum_value_1110000010 "PPR32"
attribute \enum_value_1111111111 "PIR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:60"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:55"
wire width 10 \sprmap_spr_o
cell \sprmap \sprmap
connect \spr_i \sprmap_spr_i
connect \spr_o \sprmap_spr_o
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:93"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:88"
wire width 5 \ra
process $group_0
assign \ra 5'00000
assign \ra \RA
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:95"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:90"
wire width 1 $1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:95"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:90"
cell $eq $2
parameter \A_SIGNED 0
parameter \A_WIDTH 3
connect \B 3'001
connect \Y $1
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:96"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:91"
wire width 1 $3
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:96"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:91"
cell $eq $4
parameter \A_SIGNED 0
parameter \A_WIDTH 3
connect \B 3'010
connect \Y $3
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:97"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92"
wire width 1 $5
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:97"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92"
cell $ne $6
parameter \A_SIGNED 0
parameter \A_WIDTH 5
connect \B 5'00000
connect \Y $5
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:97"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92"
wire width 1 $7
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:97"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92"
cell $and $8
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B $5
connect \Y $7
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:97"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92"
wire width 1 $9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:97"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92"
cell $or $10
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B $7
connect \Y $9
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:107"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:102"
wire width 1 $11
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:107"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:102"
cell $eq $12
parameter \A_SIGNED 0
parameter \A_WIDTH 3
end
process $group_1
assign \reg_a 5'00000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:97"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92"
switch { $9 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:97"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92"
case 1'1
assign \reg_a \ra
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:107"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:102"
switch { $11 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:107"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:102"
case 1'1
assign \reg_a \RS
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:95"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:90"
wire width 1 $13
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:95"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:90"
cell $eq $14
parameter \A_SIGNED 0
parameter \A_WIDTH 3
connect \B 3'001
connect \Y $13
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:96"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:91"
wire width 1 $15
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:96"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:91"
cell $eq $16
parameter \A_SIGNED 0
parameter \A_WIDTH 3
connect \B 3'010
connect \Y $15
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:97"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92"
wire width 1 $17
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:97"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92"
cell $ne $18
parameter \A_SIGNED 0
parameter \A_WIDTH 5
connect \B 5'00000
connect \Y $17
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:97"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92"
wire width 1 $19
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:97"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92"
cell $and $20
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B $17
connect \Y $19
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:97"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92"
wire width 1 $21
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:97"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92"
cell $or $22
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B $19
connect \Y $21
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:107"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:102"
wire width 1 $23
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:107"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:102"
cell $eq $24
parameter \A_SIGNED 0
parameter \A_WIDTH 3
end
process $group_2
assign \reg_a_ok 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:97"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92"
switch { $21 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:97"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92"
case 1'1
assign \reg_a_ok 1'1
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:107"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:102"
switch { $23 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:107"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:102"
case 1'1
assign \reg_a_ok 1'1
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:102"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:97"
wire width 1 $25
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:102"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:97"
cell $eq $26
parameter \A_SIGNED 0
parameter \A_WIDTH 3
connect \B 3'010
connect \Y $25
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:103"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:98"
wire width 1 $27
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:103"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:98"
cell $eq $28
parameter \A_SIGNED 0
parameter \A_WIDTH 5
connect \B 5'00000
connect \Y $27
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:103"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:98"
wire width 1 $29
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:103"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:98"
cell $and $30
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_3
assign \immz_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:103"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:98"
switch { $29 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:103"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:98"
case 1'1
assign \immz_out 1'1
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112"
wire width 1 $31
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114"
- cell $eq $32
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112"
+ cell $not $32
parameter \A_SIGNED 0
- parameter \A_WIDTH 7
- parameter \B_SIGNED 0
- parameter \B_WIDTH 7
+ parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \internal_op
- connect \B 7'0000111
+ connect \A \BO [2]
connect \Y $31
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:118"
wire width 1 $33
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:118"
- cell $eq $34
- parameter \A_SIGNED 0
- parameter \A_WIDTH 7
- parameter \B_SIGNED 0
- parameter \B_WIDTH 7
- parameter \Y_WIDTH 1
- connect \A \internal_op
- connect \B 7'0001000
- connect \Y $33
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:115"
- wire width 1 $35
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:115"
- cell $not $36
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \BO [2]
- connect \Y $35
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:121"
- wire width 1 $37
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:121"
- cell $not $38
+ cell $not $34
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \XL_XO [5]
- connect \Y $37
+ connect \Y $33
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:121"
- wire width 1 $39
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:121"
- cell $and $40
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:118"
+ wire width 1 $35
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:118"
+ cell $and $36
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \XL_XO [9]
- connect \B $37
- connect \Y $39
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:126"
- wire width 1 $41
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:126"
- cell $eq $42
- parameter \A_SIGNED 0
- parameter \A_WIDTH 7
- parameter \B_SIGNED 0
- parameter \B_WIDTH 7
- parameter \Y_WIDTH 1
- connect \A \internal_op
- connect \B 7'0101110
- connect \Y $41
+ connect \B $33
+ connect \Y $35
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:127"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:124"
wire width 10 \spr
process $group_4
assign \fast_a 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114"
- switch { $33 $31 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114"
- case 2'-1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:115"
- switch { $35 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:115"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:108"
+ switch \internal_op
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:111"
+ attribute \nmigen.decoding "OP_BC/7"
+ case 7'0000111
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112"
+ switch { $31 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112"
case 1'1
assign \fast_a 3'010
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:118"
- case 2'1-
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:121"
- switch { $39 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:121"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:115"
+ attribute \nmigen.decoding "OP_BCREG/8"
+ case 7'0001000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:118"
+ switch { $35 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:118"
case 1'1
assign \fast_a 3'010
end
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:126"
- switch { $41 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:126"
- case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:129"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:123"
+ attribute \nmigen.decoding "OP_MFSPR/46"
+ case 7'0101110
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:126"
switch \spr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:131"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:128"
case 10'0000001001
assign \fast_a 3'010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:134"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:131"
case 10'0000001000
assign \fast_a 3'011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:137"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:134"
case 10'1100101111
assign \fast_a 3'100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:140"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:137"
case 10'0000011010
assign \fast_a 3'101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:143"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:140"
case 10'0000011011
assign \fast_a 3'110
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:146"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:143"
case 10'0000000001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:150"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:147"
case
end
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114"
- wire width 1 $43
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114"
- cell $eq $44
- parameter \A_SIGNED 0
- parameter \A_WIDTH 7
- parameter \B_SIGNED 0
- parameter \B_WIDTH 7
- parameter \Y_WIDTH 1
- connect \A \internal_op
- connect \B 7'0000111
- connect \Y $43
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:118"
- wire width 1 $45
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:118"
- cell $eq $46
- parameter \A_SIGNED 0
- parameter \A_WIDTH 7
- parameter \B_SIGNED 0
- parameter \B_WIDTH 7
- parameter \Y_WIDTH 1
- connect \A \internal_op
- connect \B 7'0001000
- connect \Y $45
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:115"
- wire width 1 $47
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:115"
- cell $not $48
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112"
+ wire width 1 $37
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112"
+ cell $not $38
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \BO [2]
- connect \Y $47
+ connect \Y $37
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:121"
- wire width 1 $49
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:121"
- cell $not $50
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:118"
+ wire width 1 $39
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:118"
+ cell $not $40
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \XL_XO [5]
- connect \Y $49
+ connect \Y $39
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:121"
- wire width 1 $51
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:121"
- cell $and $52
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:118"
+ wire width 1 $41
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:118"
+ cell $and $42
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \XL_XO [9]
- connect \B $49
- connect \Y $51
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:126"
- wire width 1 $53
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:126"
- cell $eq $54
- parameter \A_SIGNED 0
- parameter \A_WIDTH 7
- parameter \B_SIGNED 0
- parameter \B_WIDTH 7
- parameter \Y_WIDTH 1
- connect \A \internal_op
- connect \B 7'0101110
- connect \Y $53
+ connect \B $39
+ connect \Y $41
end
process $group_5
assign \fast_a_ok 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114"
- switch { $45 $43 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114"
- case 2'-1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:115"
- switch { $47 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:115"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:108"
+ switch \internal_op
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:111"
+ attribute \nmigen.decoding "OP_BC/7"
+ case 7'0000111
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112"
+ switch { $37 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112"
case 1'1
assign \fast_a_ok 1'1
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:118"
- case 2'1-
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:121"
- switch { $51 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:121"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:115"
+ attribute \nmigen.decoding "OP_BCREG/8"
+ case 7'0001000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:118"
+ switch { $41 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:118"
case 1'1
assign \fast_a_ok 1'1
end
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:126"
- switch { $53 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:126"
- case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:129"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:123"
+ attribute \nmigen.decoding "OP_MFSPR/46"
+ case 7'0101110
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:126"
switch \spr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:131"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:128"
case 10'0000001001
assign \fast_a_ok 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:134"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:131"
case 10'0000001000
assign \fast_a_ok 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:137"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:134"
case 10'1100101111
assign \fast_a_ok 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:140"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:137"
case 10'0000011010
assign \fast_a_ok 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:143"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:140"
case 10'0000011011
assign \fast_a_ok 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:146"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:143"
case 10'0000000001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:150"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:147"
case
end
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:126"
- wire width 1 $55
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:126"
- cell $eq $56
- parameter \A_SIGNED 0
- parameter \A_WIDTH 7
- parameter \B_SIGNED 0
- parameter \B_WIDTH 7
- parameter \Y_WIDTH 1
- connect \A \internal_op
- connect \B 7'0101110
- connect \Y $55
- end
process $group_6
assign \spr 10'0000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:126"
- switch { $55 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:126"
- case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:108"
+ switch \internal_op
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:111"
+ attribute \nmigen.decoding "OP_BC/7"
+ case 7'0000111
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:115"
+ attribute \nmigen.decoding "OP_BCREG/8"
+ case 7'0001000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:123"
+ attribute \nmigen.decoding "OP_MFSPR/46"
+ case 7'0101110
assign \spr { \SPR [4:0] \SPR [9:5] }
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:126"
- wire width 1 $57
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:126"
- cell $eq $58
- parameter \A_SIGNED 0
- parameter \A_WIDTH 7
- parameter \B_SIGNED 0
- parameter \B_WIDTH 7
- parameter \Y_WIDTH 1
- connect \A \internal_op
- connect \B 7'0101110
- connect \Y $57
- end
process $group_7
assign \sprmap_spr_i 10'0000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:126"
- switch { $57 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:126"
- case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:129"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:108"
+ switch \internal_op
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:111"
+ attribute \nmigen.decoding "OP_BC/7"
+ case 7'0000111
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:115"
+ attribute \nmigen.decoding "OP_BCREG/8"
+ case 7'0001000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:123"
+ attribute \nmigen.decoding "OP_MFSPR/46"
+ case 7'0101110
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:126"
switch \spr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:131"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:128"
case 10'0000001001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:134"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:131"
case 10'0000001000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:137"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:134"
case 10'1100101111
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:140"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:137"
case 10'0000011010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:143"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:140"
case 10'0000011011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:146"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:143"
case 10'0000000001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:150"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:147"
case
assign \sprmap_spr_i \spr
end
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:126"
- wire width 1 $59
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:126"
- cell $eq $60
- parameter \A_SIGNED 0
- parameter \A_WIDTH 7
- parameter \B_SIGNED 0
- parameter \B_WIDTH 7
- parameter \Y_WIDTH 1
- connect \A \internal_op
- connect \B 7'0101110
- connect \Y $59
- end
process $group_8
assign \spr_a 10'0000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:126"
- switch { $59 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:126"
- case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:129"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:108"
+ switch \internal_op
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:111"
+ attribute \nmigen.decoding "OP_BC/7"
+ case 7'0000111
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:115"
+ attribute \nmigen.decoding "OP_BCREG/8"
+ case 7'0001000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:123"
+ attribute \nmigen.decoding "OP_MFSPR/46"
+ case 7'0101110
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:126"
switch \spr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:131"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:128"
case 10'0000001001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:134"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:131"
case 10'0000001000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:137"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:134"
case 10'1100101111
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:140"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:137"
case 10'0000011010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:143"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:140"
case 10'0000011011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:146"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:143"
case 10'0000000001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:150"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:147"
case
assign \spr_a \sprmap_spr_o
end
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:126"
- wire width 1 $61
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:126"
- cell $eq $62
- parameter \A_SIGNED 0
- parameter \A_WIDTH 7
- parameter \B_SIGNED 0
- parameter \B_WIDTH 7
- parameter \Y_WIDTH 1
- connect \A \internal_op
- connect \B 7'0101110
- connect \Y $61
- end
process $group_9
assign \spr_a_ok 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:126"
- switch { $61 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:126"
- case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:129"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:108"
+ switch \internal_op
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:111"
+ attribute \nmigen.decoding "OP_BC/7"
+ case 7'0000111
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:115"
+ attribute \nmigen.decoding "OP_BCREG/8"
+ case 7'0001000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:123"
+ attribute \nmigen.decoding "OP_MFSPR/46"
+ case 7'0101110
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:126"
switch \spr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:131"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:128"
case 10'0000001001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:134"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:131"
case 10'0000001000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:137"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:134"
case 10'1100101111
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:140"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:137"
case 10'0000011010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:143"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:140"
case 10'0000011011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:146"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:143"
case 10'0000000001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:150"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:147"
case
assign \spr_a_ok 1'1
end
attribute \enum_value_1011 "CONST_SH32"
attribute \enum_value_1100 "SPR"
attribute \enum_value_1101 "RS"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:170"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:166"
wire width 4 input 0 \sel_in
- attribute \enum_base_type "InternalOp"
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
+ attribute \enum_value_1001010 "OP_MTMSR"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
wire width 7 input 1 \internal_op
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 3 output 6 \fast_b
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 7 \fast_b_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
wire width 5 input 8 \RS
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
wire width 5 input 9 \RB
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
wire width 16 input 10 \SI
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
wire width 16 input 11 \UI
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
wire width 5 input 12 \SH32
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
wire width 6 input 13 \sh
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
wire width 24 input 14 \LI
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
wire width 14 input 15 \BD
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
wire width 14 input 16 \DS
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 10 input 17 \XL_XO
process $group_0
assign \reg_b 5'00000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:181"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:177"
switch \sel_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:182"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:178"
attribute \nmigen.decoding "RB/1"
case 4'0001
assign \reg_b \RB
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:185"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:181"
attribute \nmigen.decoding "RS/13"
case 4'1101
assign \reg_b \RS
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:188"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:184"
attribute \nmigen.decoding "CONST_UI/2"
case 4'0010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:187"
attribute \nmigen.decoding "CONST_SI/3"
case 4'0011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:195"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191"
attribute \nmigen.decoding "CONST_UI_HI/4"
case 4'0100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:198"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:194"
attribute \nmigen.decoding "CONST_SI_HI/5"
case 4'0101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:203"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:199"
attribute \nmigen.decoding "CONST_LI/6"
case 4'0110
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:206"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:202"
attribute \nmigen.decoding "CONST_BD/7"
case 4'0111
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:209"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:205"
attribute \nmigen.decoding "CONST_DS/8"
case 4'1000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:212"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:208"
attribute \nmigen.decoding "CONST_M1/9"
case 4'1001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:215"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:211"
attribute \nmigen.decoding "CONST_SH/10"
case 4'1010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:218"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:214"
attribute \nmigen.decoding "CONST_SH32/11"
case 4'1011
end
end
process $group_1
assign \reg_b_ok 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:181"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:177"
switch \sel_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:182"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:178"
attribute \nmigen.decoding "RB/1"
case 4'0001
assign \reg_b_ok 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:185"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:181"
attribute \nmigen.decoding "RS/13"
case 4'1101
assign \reg_b_ok 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:188"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:184"
attribute \nmigen.decoding "CONST_UI/2"
case 4'0010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:187"
attribute \nmigen.decoding "CONST_SI/3"
case 4'0011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:195"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191"
attribute \nmigen.decoding "CONST_UI_HI/4"
case 4'0100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:198"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:194"
attribute \nmigen.decoding "CONST_SI_HI/5"
case 4'0101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:203"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:199"
attribute \nmigen.decoding "CONST_LI/6"
case 4'0110
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:206"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:202"
attribute \nmigen.decoding "CONST_BD/7"
case 4'0111
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:197"
cell $sshl $88
parameter \A_SIGNED 0
parameter \A_WIDTH 16
connect \Y $87
end
connect $86 $87
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:197"
wire width 47 $89
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:197"
wire width 47 $90
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:197"
cell $sshl $91
parameter \A_SIGNED 0
parameter \A_WIDTH 16
connect \Y $90
end
connect $89 $90
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:197"
wire width 47 $92
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:197"
wire width 47 $93
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:197"
cell $sshl $94
parameter \A_SIGNED 0
parameter \A_WIDTH 16
connect \Y $93
end
connect $92 $93
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:197"
wire width 47 $95
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:197"
wire width 47 $96
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:197"
cell $sshl $97
parameter \A_SIGNED 0
parameter \A_WIDTH 16
connect \Y $96
end
connect $95 $96
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:197"
wire width 47 $98
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:197"
wire width 47 $99
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:197"
cell $sshl $100
parameter \A_SIGNED 0
parameter \A_WIDTH 16
connect \Y $99
end
connect $98 $99
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:197"
wire width 47 $101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:197"
wire width 47 $102
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:197"
cell $sshl $103
parameter \A_SIGNED 0
parameter \A_WIDTH 16
connect \Y $102
end
connect $101 $102
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:197"
wire width 47 $104
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:197"
wire width 47 $105
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:197"
cell $sshl $106
parameter \A_SIGNED 0
parameter \A_WIDTH 16
connect \Y $105
end
connect $104 $105
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:197"
wire width 47 $107
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:197"
wire width 47 $108
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:197"
cell $sshl $109
parameter \A_SIGNED 0
parameter \A_WIDTH 16
connect \Y $108
end
connect $107 $108
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:204"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:200"
wire width 64 $110
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:204"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:200"
wire width 27 $111
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:204"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:200"
cell $sshl $112
parameter \A_SIGNED 0
parameter \A_WIDTH 24
connect \B 2'10
connect \Y $111
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:204"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:200"
cell $pos $113
parameter \A_SIGNED 0
parameter \A_WIDTH 27
connect \A $111
connect \Y $110
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:207"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:203"
wire width 64 $114
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:207"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:203"
wire width 17 $115
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:207"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:203"
cell $sshl $116
parameter \A_SIGNED 0
parameter \A_WIDTH 14
connect \B 2'10
connect \Y $115
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:207"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:203"
cell $pos $117
parameter \A_SIGNED 0
parameter \A_WIDTH 17
connect \A $115
connect \Y $114
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:210"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:206"
wire width 64 $118
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:210"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:206"
wire width 17 $119
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:210"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:206"
cell $sshl $120
parameter \A_SIGNED 0
parameter \A_WIDTH 14
connect \B 2'10
connect \Y $119
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:210"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:206"
cell $pos $121
parameter \A_SIGNED 0
parameter \A_WIDTH 17
connect \A $119
connect \Y $118
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:213"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:209"
wire width 64 $122
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:213"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:209"
cell $not $123
parameter \A_SIGNED 0
parameter \A_WIDTH 64
connect \A 64'0000000000000000000000000000000000000000000000000000000000000000
connect \Y $122
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
wire width 64 $124
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
cell $pos $125
parameter \A_SIGNED 0
parameter \A_WIDTH 6
connect \A \sh
connect \Y $124
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
wire width 64 $126
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
cell $pos $127
parameter \A_SIGNED 0
parameter \A_WIDTH 5
end
process $group_2
assign \imm_b 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:181"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:177"
switch \sel_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:182"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:178"
attribute \nmigen.decoding "RB/1"
case 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:185"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:181"
attribute \nmigen.decoding "RS/13"
case 4'1101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:188"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:184"
attribute \nmigen.decoding "CONST_UI/2"
case 4'0010
assign \imm_b $1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:187"
attribute \nmigen.decoding "CONST_SI/3"
case 4'0011
assign \imm_b { { \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] } \SI }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:195"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191"
attribute \nmigen.decoding "CONST_UI_HI/4"
case 4'0100
assign \imm_b $3
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:198"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:194"
attribute \nmigen.decoding "CONST_SI_HI/5"
case 4'0101
assign \imm_b $7
assign \imm_b { { $14 [31:0] [31] $17 [31:0] [31] $20 [31:0] [31] $23 [31:0] [31] $26 [31:0] [31] $29 [31:0] [31] $32 [31:0] [31] $35 [31:0] [31] $38 [31:0] [31] $41 [31:0] [31] $44 [31:0] [31] $47 [31:0] [31] $50 [31:0] [31] $53 [31:0] [31] $56 [31:0] [31] $59 [31:0] [31] $62 [31:0] [31] $65 [31:0] [31] $68 [31:0] [31] $71 [31:0] [31] $74 [31:0] [31] $77 [31:0] [31] $80 [31:0] [31] $83 [31:0] [31] $86 [31:0] [31] $89 [31:0] [31] $92 [31:0] [31] $95 [31:0] [31] $98 [31:0] [31] $101 [31:0] [31] $104 [31:0] [31] $107 [31:0] [31] } $11 [31:0] }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:203"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:199"
attribute \nmigen.decoding "CONST_LI/6"
case 4'0110
assign \imm_b $110
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:206"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:202"
attribute \nmigen.decoding "CONST_BD/7"
case 4'0111
assign \imm_b $114
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:209"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:205"
attribute \nmigen.decoding "CONST_DS/8"
case 4'1000
assign \imm_b $118
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:212"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:208"
attribute \nmigen.decoding "CONST_M1/9"
case 4'1001
assign \imm_b $122
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:215"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:211"
attribute \nmigen.decoding "CONST_SH/10"
case 4'1010
assign \imm_b $124
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:218"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:214"
attribute \nmigen.decoding "CONST_SH32/11"
case 4'1011
assign \imm_b $126
end
process $group_3
assign \imm_b_ok 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:181"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:177"
switch \sel_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:182"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:178"
attribute \nmigen.decoding "RB/1"
case 4'0001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:185"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:181"
attribute \nmigen.decoding "RS/13"
case 4'1101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:188"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:184"
attribute \nmigen.decoding "CONST_UI/2"
case 4'0010
assign \imm_b_ok 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:187"
attribute \nmigen.decoding "CONST_SI/3"
case 4'0011
assign \imm_b_ok 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:195"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191"
attribute \nmigen.decoding "CONST_UI_HI/4"
case 4'0100
assign \imm_b_ok 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:198"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:194"
attribute \nmigen.decoding "CONST_SI_HI/5"
case 4'0101
assign \imm_b_ok 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:203"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:199"
attribute \nmigen.decoding "CONST_LI/6"
case 4'0110
assign \imm_b_ok 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:206"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:202"
attribute \nmigen.decoding "CONST_BD/7"
case 4'0111
assign \imm_b_ok 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:209"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:205"
attribute \nmigen.decoding "CONST_DS/8"
case 4'1000
assign \imm_b_ok 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:212"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:208"
attribute \nmigen.decoding "CONST_M1/9"
case 4'1001
assign \imm_b_ok 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:215"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:211"
attribute \nmigen.decoding "CONST_SH/10"
case 4'1010
assign \imm_b_ok 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:218"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:214"
attribute \nmigen.decoding "CONST_SH32/11"
case 4'1011
assign \imm_b_ok 1'1
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:226"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:222"
wire width 1 $128
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:226"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:222"
cell $eq $129
parameter \A_SIGNED 0
parameter \A_WIDTH 7
connect \B 7'0001000
connect \Y $128
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:229"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225"
wire width 1 $130
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:229"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225"
cell $not $131
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_4
assign \fast_b 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:226"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:222"
switch { $128 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:226"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:222"
case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:229"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225"
switch { \XL_XO [5] $130 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:229"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225"
case 2'-1
assign \fast_b 3'011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:232"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228"
case 2'1-
assign \fast_b 3'100
end
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:226"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:222"
wire width 1 $132
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:226"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:222"
cell $eq $133
parameter \A_SIGNED 0
parameter \A_WIDTH 7
connect \B 7'0001000
connect \Y $132
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:229"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225"
wire width 1 $134
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:229"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225"
cell $not $135
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
process $group_5
assign \fast_b_ok 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:226"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:222"
switch { $132 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:226"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:222"
case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:229"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225"
switch { \XL_XO [5] $134 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:229"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225"
case 2'-1
assign \fast_b_ok 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:232"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228"
case 2'1-
assign \fast_b_ok 1'1
end
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "RS"
attribute \enum_value_10 "RB"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:247"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243"
wire width 2 input 0 \sel_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 5 output 1 \reg_c
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 2 \reg_c_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
wire width 5 input 3 \RS
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
wire width 5 input 4 \RB
process $group_0
assign \reg_c 5'00000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:256"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:252"
switch \sel_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:257"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253"
attribute \nmigen.decoding "RB/2"
case 2'10
assign \reg_c \RB
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:256"
attribute \nmigen.decoding "RS/1"
case 2'01
assign \reg_c \RS
end
process $group_1
assign \reg_c_ok 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:256"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:252"
switch \sel_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:257"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253"
attribute \nmigen.decoding "RB/2"
case 2'10
assign \reg_c_ok 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:260"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:256"
attribute \nmigen.decoding "RS/1"
case 2'01
assign \reg_c_ok 1'1
attribute \generator "nMigen"
attribute \nmigen.hierarchy "test_issuer.core.pdecode2.dec_o.sprmap"
module \sprmap$1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:54"
wire width 10 input 0 \spr_i
attribute \enum_base_type "SPR"
attribute \enum_value_0000000001 "XER"
attribute \enum_value_1110000000 "PPR"
attribute \enum_value_1110000010 "PPR32"
attribute \enum_value_1111111111 "PIR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:60"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:55"
wire width 10 output 1 \spr_o
process $group_0
assign \spr_o 10'0000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:59"
switch \spr_i
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'0000000001
assign \spr_o 10'0000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'0000000011
assign \spr_o 10'0000000001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'0000001000
assign \spr_o 10'0000000010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'0000001001
assign \spr_o 10'0000000011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'0000001101
assign \spr_o 10'0000000100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'0000010001
assign \spr_o 10'0000000101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'0000010010
assign \spr_o 10'0000000110
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'0000010011
assign \spr_o 10'0000000111
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'0000010110
assign \spr_o 10'0000001000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'0000011010
assign \spr_o 10'0000001001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'0000011011
assign \spr_o 10'0000001010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'0000011100
assign \spr_o 10'0000001011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'0000011101
assign \spr_o 10'0000001100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'0000110000
assign \spr_o 10'0000001101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'0000111101
assign \spr_o 10'0000001110
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'0010000000
assign \spr_o 10'0000001111
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'0010000001
assign \spr_o 10'0000010000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'0010000010
assign \spr_o 10'0000010001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'0010000011
assign \spr_o 10'0000010010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'0010001000
assign \spr_o 10'0000010011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'0010010000
assign \spr_o 10'0000010100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'0010011000
assign \spr_o 10'0000010101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'0010011001
assign \spr_o 10'0000010110
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'0010011101
assign \spr_o 10'0000010111
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'0010011110
assign \spr_o 10'0000011000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'0010011111
assign \spr_o 10'0000011001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'0010110000
assign \spr_o 10'0000011010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'0010110100
assign \spr_o 10'0000011011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'0010111010
assign \spr_o 10'0000011100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'0010111011
assign \spr_o 10'0000011101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'0010111100
assign \spr_o 10'0000011110
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'0010111110
assign \spr_o 10'0000011111
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'0100000000
assign \spr_o 10'0000100000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'0100000011
assign \spr_o 10'0000100001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'0100001100
assign \spr_o 10'0000100010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'0100001101
assign \spr_o 10'0000100011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'0100010000
assign \spr_o 10'0000100100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'0100010001
assign \spr_o 10'0000100101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'0100010010
assign \spr_o 10'0000100110
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'0100010011
assign \spr_o 10'0000100111
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'0100011011
assign \spr_o 10'0000101000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'0100011100
assign \spr_o 10'0000101001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'0100011101
assign \spr_o 10'0000101010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'0100011110
assign \spr_o 10'0000101011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'0100011111
assign \spr_o 10'0000101100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'0100110000
assign \spr_o 10'0000101101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'0100110001
assign \spr_o 10'0000101110
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'0100110010
assign \spr_o 10'0000101111
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'0100110011
assign \spr_o 10'0000110000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'0100110100
assign \spr_o 10'0000110001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'0100110101
assign \spr_o 10'0000110010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'0100110110
assign \spr_o 10'0000110011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'0100111001
assign \spr_o 10'0000110100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'0100111010
assign \spr_o 10'0000110101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'0100111011
assign \spr_o 10'0000110110
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'0100111110
assign \spr_o 10'0000110111
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'0100111111
assign \spr_o 10'0000111000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'0101010000
assign \spr_o 10'0000111001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'0101010001
assign \spr_o 10'0000111010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'0101010010
assign \spr_o 10'0000111011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'0101010011
assign \spr_o 10'0000111100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'0101011101
assign \spr_o 10'0000111101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'0110111110
assign \spr_o 10'0000111110
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'0111010000
assign \spr_o 10'0000111111
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'1100000000
assign \spr_o 10'0001000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'1100000001
assign \spr_o 10'0001000001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'1100000010
assign \spr_o 10'0001000010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'1100000011
assign \spr_o 10'0001000011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'1100000100
assign \spr_o 10'0001000100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'1100000101
assign \spr_o 10'0001000101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'1100000110
assign \spr_o 10'0001000110
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'1100000111
assign \spr_o 10'0001000111
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'1100001000
assign \spr_o 10'0001001000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'1100001011
assign \spr_o 10'0001001001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'1100001100
assign \spr_o 10'0001001010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'1100001101
assign \spr_o 10'0001001011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'1100001110
assign \spr_o 10'0001001100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'1100010000
assign \spr_o 10'0001001101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'1100010001
assign \spr_o 10'0001001110
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'1100010010
assign \spr_o 10'0001001111
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'1100010011
assign \spr_o 10'0001010000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'1100010100
assign \spr_o 10'0001010001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'1100010101
assign \spr_o 10'0001010010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'1100010110
assign \spr_o 10'0001010011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'1100010111
assign \spr_o 10'0001010100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'1100011000
assign \spr_o 10'0001010101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'1100011011
assign \spr_o 10'0001010110
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'1100011100
assign \spr_o 10'0001010111
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'1100011101
assign \spr_o 10'0001011000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'1100011110
assign \spr_o 10'0001011001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'1100100000
assign \spr_o 10'0001011010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'1100100001
assign \spr_o 10'0001011011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'1100100010
assign \spr_o 10'0001011100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'1100100011
assign \spr_o 10'0001011101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'1100100100
assign \spr_o 10'0001011110
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'1100100101
assign \spr_o 10'0001011111
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'1100100110
assign \spr_o 10'0001100000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'1100101000
assign \spr_o 10'0001100001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'1100101001
assign \spr_o 10'0001100010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'1100101010
assign \spr_o 10'0001100011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'1100101011
assign \spr_o 10'0001100100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'1100101111
assign \spr_o 10'0001100101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'1100110000
assign \spr_o 10'0001100110
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'1100110111
assign \spr_o 10'0001100111
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'1101010000
assign \spr_o 10'0001101000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'1101010001
assign \spr_o 10'0001101001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'1101010111
assign \spr_o 10'0001101010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'1110000000
assign \spr_o 10'0001101011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'1110000010
assign \spr_o 10'0001101100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:66"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
case 10'1111111111
assign \spr_o 10'0001101101
end
attribute \enum_value_01 "RT"
attribute \enum_value_10 "RA"
attribute \enum_value_11 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271"
wire width 2 input 0 \sel_in
- attribute \enum_base_type "InternalOp"
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
+ attribute \enum_value_1001010 "OP_MTMSR"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
wire width 7 input 1 \internal_op
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 3 output 6 \fast_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 7 \fast_o_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
wire width 5 input 8 \RT
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
wire width 5 input 9 \RA
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
wire width 5 input 10 \BO
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
wire width 10 input 11 \SPR
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:59"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:54"
wire width 10 \sprmap_spr_i
attribute \enum_base_type "SPR"
attribute \enum_value_0000000001 "XER"
attribute \enum_value_1110000000 "PPR"
attribute \enum_value_1110000010 "PPR32"
attribute \enum_value_1111111111 "PIR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:60"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:55"
wire width 10 \sprmap_spr_o
cell \sprmap$1 \sprmap
connect \spr_i \sprmap_spr_i
end
process $group_0
assign \reg_o 5'00000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:284"
switch \sel_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:289"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:285"
attribute \nmigen.decoding "RT/1"
case 2'01
assign \reg_o \RT
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:292"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:288"
attribute \nmigen.decoding "RA/2"
case 2'10
assign \reg_o \RA
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291"
attribute \nmigen.decoding "SPR/3"
case 2'11
end
end
process $group_1
assign \reg_o_ok 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:284"
switch \sel_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:289"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:285"
attribute \nmigen.decoding "RT/1"
case 2'01
assign \reg_o_ok 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:292"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:288"
attribute \nmigen.decoding "RA/2"
case 2'10
assign \reg_o_ok 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291"
attribute \nmigen.decoding "SPR/3"
case 2'11
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:296"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:292"
wire width 10 \spr
process $group_2
assign \spr 10'0000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:284"
switch \sel_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:289"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:285"
attribute \nmigen.decoding "RT/1"
case 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:292"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:288"
attribute \nmigen.decoding "RA/2"
case 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291"
attribute \nmigen.decoding "SPR/3"
case 2'11
assign \spr { \SPR [4:0] \SPR [9:5] }
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295"
wire width 1 $1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295"
cell $eq $2
parameter \A_SIGNED 0
parameter \A_WIDTH 7
connect \B 7'0110001
connect \Y $1
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:328"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:326"
wire width 1 $3
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:328"
- cell $eq $4
- parameter \A_SIGNED 0
- parameter \A_WIDTH 7
- parameter \B_SIGNED 0
- parameter \B_WIDTH 7
- parameter \Y_WIDTH 1
- connect \A \internal_op
- connect \B 7'0000111
- connect \Y $3
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:329"
- wire width 1 $5
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:329"
- cell $eq $6
- parameter \A_SIGNED 0
- parameter \A_WIDTH 7
- parameter \B_SIGNED 0
- parameter \B_WIDTH 7
- parameter \Y_WIDTH 1
- connect \A \internal_op
- connect \B 7'0001000
- connect \Y $5
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:329"
- wire width 1 $7
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:329"
- cell $or $8
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A $3
- connect \B $5
- connect \Y $7
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:330"
- wire width 1 $9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:330"
- cell $not $10
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:326"
+ cell $not $4
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \BO [2]
- connect \Y $9
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:335"
- wire width 1 $11
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:335"
- cell $eq $12
- parameter \A_SIGNED 0
- parameter \A_WIDTH 7
- parameter \B_SIGNED 0
- parameter \B_WIDTH 7
- parameter \Y_WIDTH 1
- connect \A \internal_op
- connect \B 7'1000110
- connect \Y $11
+ connect \Y $3
end
process $group_3
assign \fast_o 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:284"
switch \sel_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:289"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:285"
attribute \nmigen.decoding "RT/1"
case 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:292"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:288"
attribute \nmigen.decoding "RA/2"
case 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291"
attribute \nmigen.decoding "SPR/3"
case 2'11
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295"
switch { $1 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295"
case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:300"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:296"
switch \spr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:302"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:298"
case 10'0000001001
assign \fast_o 3'010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:305"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:301"
case 10'0000001000
assign \fast_o 3'011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:308"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:304"
case 10'1100101111
assign \fast_o 3'100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:311"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:307"
case 10'0000011010
assign \fast_o 3'101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:314"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:310"
case 10'0000011011
assign \fast_o 3'110
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:317"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:313"
case 10'0000000001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:321"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:317"
case
end
end
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:329"
- switch { $7 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:329"
- case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:330"
- switch { $9 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:330"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:322"
+ switch \internal_op
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:325"
+ attribute \nmigen.decoding "OP_BC/7|OP_BCREG/8"
+ case 7'0000111, 7'0001000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:326"
+ switch { $3 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:326"
case 1'1
assign \fast_o 3'010
end
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:335"
- switch { $11 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:335"
- case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:331"
+ attribute \nmigen.decoding "OP_RFID/70"
+ case 7'1000110
assign \fast_o 3'101
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:299"
- wire width 1 $13
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:299"
- cell $eq $14
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295"
+ wire width 1 $5
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295"
+ cell $eq $6
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \internal_op
connect \B 7'0110001
- connect \Y $13
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:328"
- wire width 1 $15
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:328"
- cell $eq $16
- parameter \A_SIGNED 0
- parameter \A_WIDTH 7
- parameter \B_SIGNED 0
- parameter \B_WIDTH 7
- parameter \Y_WIDTH 1
- connect \A \internal_op
- connect \B 7'0000111
- connect \Y $15
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:329"
- wire width 1 $17
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:329"
- cell $eq $18
- parameter \A_SIGNED 0
- parameter \A_WIDTH 7
- parameter \B_SIGNED 0
- parameter \B_WIDTH 7
- parameter \Y_WIDTH 1
- connect \A \internal_op
- connect \B 7'0001000
- connect \Y $17
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:329"
- wire width 1 $19
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:329"
- cell $or $20
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A $15
- connect \B $17
- connect \Y $19
+ connect \Y $5
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:330"
- wire width 1 $21
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:330"
- cell $not $22
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:326"
+ wire width 1 $7
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:326"
+ cell $not $8
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \BO [2]
- connect \Y $21
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:335"
- wire width 1 $23
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:335"
- cell $eq $24
- parameter \A_SIGNED 0
- parameter \A_WIDTH 7
- parameter \B_SIGNED 0
- parameter \B_WIDTH 7
- parameter \Y_WIDTH 1
- connect \A \internal_op
- connect \B 7'1000110
- connect \Y $23
+ connect \Y $7
end
process $group_4
assign \fast_o_ok 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:284"
switch \sel_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:289"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:285"
attribute \nmigen.decoding "RT/1"
case 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:292"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:288"
attribute \nmigen.decoding "RA/2"
case 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291"
attribute \nmigen.decoding "SPR/3"
case 2'11
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:299"
- switch { $13 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295"
+ switch { $5 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295"
case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:300"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:296"
switch \spr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:302"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:298"
case 10'0000001001
assign \fast_o_ok 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:305"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:301"
case 10'0000001000
assign \fast_o_ok 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:308"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:304"
case 10'1100101111
assign \fast_o_ok 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:311"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:307"
case 10'0000011010
assign \fast_o_ok 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:314"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:310"
case 10'0000011011
assign \fast_o_ok 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:317"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:313"
case 10'0000000001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:321"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:317"
case
end
end
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:329"
- switch { $19 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:329"
- case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:330"
- switch { $21 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:330"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:322"
+ switch \internal_op
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:325"
+ attribute \nmigen.decoding "OP_BC/7|OP_BCREG/8"
+ case 7'0000111, 7'0001000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:326"
+ switch { $7 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:326"
case 1'1
assign \fast_o_ok 1'1
end
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:335"
- switch { $23 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:335"
- case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:331"
+ attribute \nmigen.decoding "OP_RFID/70"
+ case 7'1000110
assign \fast_o_ok 1'1
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:299"
- wire width 1 $25
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:299"
- cell $eq $26
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295"
+ wire width 1 $9
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295"
+ cell $eq $10
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \internal_op
connect \B 7'0110001
- connect \Y $25
+ connect \Y $9
end
process $group_5
assign \sprmap_spr_i 10'0000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:284"
switch \sel_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:289"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:285"
attribute \nmigen.decoding "RT/1"
case 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:292"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:288"
attribute \nmigen.decoding "RA/2"
case 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291"
attribute \nmigen.decoding "SPR/3"
case 2'11
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:299"
- switch { $25 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295"
+ switch { $9 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295"
case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:300"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:296"
switch \spr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:302"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:298"
case 10'0000001001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:305"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:301"
case 10'0000001000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:308"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:304"
case 10'1100101111
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:311"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:307"
case 10'0000011010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:314"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:310"
case 10'0000011011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:317"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:313"
case 10'0000000001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:321"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:317"
case
assign \sprmap_spr_i \spr
end
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:299"
- wire width 1 $27
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:299"
- cell $eq $28
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295"
+ wire width 1 $11
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295"
+ cell $eq $12
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \internal_op
connect \B 7'0110001
- connect \Y $27
+ connect \Y $11
end
process $group_6
assign \spr_o 10'0000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:284"
switch \sel_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:289"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:285"
attribute \nmigen.decoding "RT/1"
case 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:292"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:288"
attribute \nmigen.decoding "RA/2"
case 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291"
attribute \nmigen.decoding "SPR/3"
case 2'11
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:299"
- switch { $27 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295"
+ switch { $11 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295"
case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:300"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:296"
switch \spr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:302"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:298"
case 10'0000001001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:305"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:301"
case 10'0000001000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:308"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:304"
case 10'1100101111
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:311"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:307"
case 10'0000011010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:314"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:310"
case 10'0000011011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:317"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:313"
case 10'0000000001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:321"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:317"
case
assign \spr_o \sprmap_spr_o
end
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:299"
- wire width 1 $29
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:299"
- cell $eq $30
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295"
+ wire width 1 $13
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295"
+ cell $eq $14
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \internal_op
connect \B 7'0110001
- connect \Y $29
+ connect \Y $13
end
process $group_7
assign \spr_o_ok 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:288"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:284"
switch \sel_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:289"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:285"
attribute \nmigen.decoding "RT/1"
case 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:292"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:288"
attribute \nmigen.decoding "RA/2"
case 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:291"
attribute \nmigen.decoding "SPR/3"
case 2'11
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:299"
- switch { $29 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:299"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295"
+ switch { $13 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:295"
case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:300"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:296"
switch \spr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:302"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:298"
case 10'0000001001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:305"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:301"
case 10'0000001000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:308"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:304"
case 10'1100101111
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:311"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:307"
case 10'0000011010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:314"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:310"
case 10'0000011011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:317"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:313"
case 10'0000000001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:321"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:317"
case
assign \spr_o_ok 1'1
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "test_issuer.core.pdecode2.dec_o2"
module \dec_o2
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:351"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:347"
wire width 1 input 0 \lk
- attribute \enum_base_type "InternalOp"
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
+ attribute \enum_value_1001010 "OP_MTMSR"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
wire width 7 input 1 \internal_op
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 3 output 4 \fast_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 5 \fast_o_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 input 6 \upd
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \enum_base_type "LDSTMode"
+ attribute \enum_value_00 "NONE"
+ attribute \enum_value_01 "update"
+ attribute \enum_value_10 "cix"
+ attribute \enum_value_11 "cx"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+ wire width 2 input 6 \upd
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
wire width 5 input 7 \RA
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
- wire width 6 $1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
- cell $pos $2
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:357"
+ wire width 1 $1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:357"
+ cell $eq $2
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 2
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 2
+ parameter \Y_WIDTH 1
+ connect \A \upd
+ connect \B 2'01
+ connect \Y $1
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
+ wire width 6 $3
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
+ cell $pos $4
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \Y_WIDTH 6
connect \A \RA
- connect \Y $1
+ connect \Y $3
end
process $group_0
assign \reg_o 5'00000
assign \reg_o_ok 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:361"
- switch { \upd }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:361"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:357"
+ switch { $1 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:357"
case 1'1
- assign { \reg_o_ok \reg_o } $1
+ assign { \reg_o_ok \reg_o } $3
assign \reg_o_ok 1'1
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:367"
- wire width 1 $3
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:367"
- cell $eq $4
- parameter \A_SIGNED 0
- parameter \A_WIDTH 7
- parameter \B_SIGNED 0
- parameter \B_WIDTH 7
- parameter \Y_WIDTH 1
- connect \A \internal_op
- connect \B 7'0000111
- connect \Y $3
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:368"
- wire width 1 $5
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:368"
- cell $eq $6
- parameter \A_SIGNED 0
- parameter \A_WIDTH 7
- parameter \B_SIGNED 0
- parameter \B_WIDTH 7
- parameter \Y_WIDTH 1
- connect \A \internal_op
- connect \B 7'0001000
- connect \Y $5
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:368"
- wire width 1 $7
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:368"
- cell $or $8
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A $3
- connect \B $5
- connect \Y $7
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:374"
- wire width 1 $9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:374"
- cell $eq $10
- parameter \A_SIGNED 0
- parameter \A_WIDTH 7
- parameter \B_SIGNED 0
- parameter \B_WIDTH 7
- parameter \Y_WIDTH 1
- connect \A \internal_op
- connect \B 7'1000110
- connect \Y $9
- end
process $group_2
assign \fast_o 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:368"
- switch { $7 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:368"
- case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:369"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:364"
+ switch \internal_op
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:367"
+ attribute \nmigen.decoding "OP_BC/7|OP_B/6|OP_BCREG/8"
+ case 7'0000111, 7'0000110, 7'0001000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:368"
switch { \lk }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:369"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:368"
case 1'1
assign \fast_o 3'011
end
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:374"
- switch { $9 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:374"
- case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373"
+ attribute \nmigen.decoding "OP_RFID/70"
+ case 7'1000110
assign \fast_o 3'110
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:367"
- wire width 1 $11
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:367"
- cell $eq $12
- parameter \A_SIGNED 0
- parameter \A_WIDTH 7
- parameter \B_SIGNED 0
- parameter \B_WIDTH 7
- parameter \Y_WIDTH 1
- connect \A \internal_op
- connect \B 7'0000111
- connect \Y $11
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:368"
- wire width 1 $13
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:368"
- cell $eq $14
- parameter \A_SIGNED 0
- parameter \A_WIDTH 7
- parameter \B_SIGNED 0
- parameter \B_WIDTH 7
- parameter \Y_WIDTH 1
- connect \A \internal_op
- connect \B 7'0001000
- connect \Y $13
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:368"
- wire width 1 $15
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:368"
- cell $or $16
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A $11
- connect \B $13
- connect \Y $15
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:374"
- wire width 1 $17
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:374"
- cell $eq $18
- parameter \A_SIGNED 0
- parameter \A_WIDTH 7
- parameter \B_SIGNED 0
- parameter \B_WIDTH 7
- parameter \Y_WIDTH 1
- connect \A \internal_op
- connect \B 7'1000110
- connect \Y $17
- end
process $group_3
assign \fast_o_ok 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:368"
- switch { $15 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:368"
- case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:369"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:364"
+ switch \internal_op
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:367"
+ attribute \nmigen.decoding "OP_BC/7|OP_B/6|OP_BCREG/8"
+ case 7'0000111, 7'0000110, 7'0001000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:368"
switch { \lk }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:369"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:368"
case 1'1
assign \fast_o_ok 1'1
end
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:374"
- switch { $17 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:374"
- case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373"
+ attribute \nmigen.decoding "OP_RFID/70"
+ case 7'1000110
assign \fast_o_ok 1'1
end
sync init
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "RC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:388"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:387"
wire width 2 input 0 \sel_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 1 \rc
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 2 \rc_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
wire width 1 input 3 \Rc
process $group_0
assign \rc 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:397"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:396"
switch \sel_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:398"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:397"
attribute \nmigen.decoding "RC/2"
case 2'10
assign \rc \Rc
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:401"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:400"
attribute \nmigen.decoding "ONE/1"
case 2'01
assign \rc 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:403"
attribute \nmigen.decoding "NONE/0"
case 2'00
assign \rc 1'0
end
process $group_1
assign \rc_ok 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:397"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:396"
switch \sel_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:398"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:397"
attribute \nmigen.decoding "RC/2"
case 2'10
assign \rc_ok 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:401"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:400"
attribute \nmigen.decoding "ONE/1"
case 2'01
assign \rc_ok 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:403"
attribute \nmigen.decoding "NONE/0"
case 2'00
assign \rc_ok 1'1
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "RC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:424"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:423"
wire width 2 input 0 \sel_in
+ attribute \enum_base_type "MicrOp"
+ attribute \enum_value_0000000 "OP_ILLEGAL"
+ attribute \enum_value_0000001 "OP_NOP"
+ attribute \enum_value_0000010 "OP_ADD"
+ attribute \enum_value_0000011 "OP_ADDPCIS"
+ attribute \enum_value_0000100 "OP_AND"
+ attribute \enum_value_0000101 "OP_ATTN"
+ attribute \enum_value_0000110 "OP_B"
+ attribute \enum_value_0000111 "OP_BC"
+ attribute \enum_value_0001000 "OP_BCREG"
+ attribute \enum_value_0001001 "OP_BPERM"
+ attribute \enum_value_0001010 "OP_CMP"
+ attribute \enum_value_0001011 "OP_CMPB"
+ attribute \enum_value_0001100 "OP_CMPEQB"
+ attribute \enum_value_0001101 "OP_CMPRB"
+ attribute \enum_value_0001110 "OP_CNTZ"
+ attribute \enum_value_0001111 "OP_CRAND"
+ attribute \enum_value_0010000 "OP_CRANDC"
+ attribute \enum_value_0010001 "OP_CREQV"
+ attribute \enum_value_0010010 "OP_CRNAND"
+ attribute \enum_value_0010011 "OP_CRNOR"
+ attribute \enum_value_0010100 "OP_CROR"
+ attribute \enum_value_0010101 "OP_CRORC"
+ attribute \enum_value_0010110 "OP_CRXOR"
+ attribute \enum_value_0010111 "OP_DARN"
+ attribute \enum_value_0011000 "OP_DCBF"
+ attribute \enum_value_0011001 "OP_DCBST"
+ attribute \enum_value_0011010 "OP_DCBT"
+ attribute \enum_value_0011011 "OP_DCBTST"
+ attribute \enum_value_0011100 "OP_DCBZ"
+ attribute \enum_value_0011101 "OP_DIV"
+ attribute \enum_value_0011110 "OP_DIVE"
+ attribute \enum_value_0011111 "OP_EXTS"
+ attribute \enum_value_0100000 "OP_EXTSWSLI"
+ attribute \enum_value_0100001 "OP_ICBI"
+ attribute \enum_value_0100010 "OP_ICBT"
+ attribute \enum_value_0100011 "OP_ISEL"
+ attribute \enum_value_0100100 "OP_ISYNC"
+ attribute \enum_value_0100101 "OP_LOAD"
+ attribute \enum_value_0100110 "OP_STORE"
+ attribute \enum_value_0100111 "OP_MADDHD"
+ attribute \enum_value_0101000 "OP_MADDHDU"
+ attribute \enum_value_0101001 "OP_MADDLD"
+ attribute \enum_value_0101010 "OP_MCRF"
+ attribute \enum_value_0101011 "OP_MCRXR"
+ attribute \enum_value_0101100 "OP_MCRXRX"
+ attribute \enum_value_0101101 "OP_MFCR"
+ attribute \enum_value_0101110 "OP_MFSPR"
+ attribute \enum_value_0101111 "OP_MOD"
+ attribute \enum_value_0110000 "OP_MTCRF"
+ attribute \enum_value_0110001 "OP_MTSPR"
+ attribute \enum_value_0110010 "OP_MUL_L64"
+ attribute \enum_value_0110011 "OP_MUL_H64"
+ attribute \enum_value_0110100 "OP_MUL_H32"
+ attribute \enum_value_0110101 "OP_OR"
+ attribute \enum_value_0110110 "OP_POPCNT"
+ attribute \enum_value_0110111 "OP_PRTY"
+ attribute \enum_value_0111000 "OP_RLC"
+ attribute \enum_value_0111001 "OP_RLCL"
+ attribute \enum_value_0111010 "OP_RLCR"
+ attribute \enum_value_0111011 "OP_SETB"
+ attribute \enum_value_0111100 "OP_SHL"
+ attribute \enum_value_0111101 "OP_SHR"
+ attribute \enum_value_0111110 "OP_SYNC"
+ attribute \enum_value_0111111 "OP_TRAP"
+ attribute \enum_value_1000011 "OP_XOR"
+ attribute \enum_value_1000100 "OP_SIM_CONFIG"
+ attribute \enum_value_1000101 "OP_CROP"
+ attribute \enum_value_1000110 "OP_RFID"
+ attribute \enum_value_1000111 "OP_MFMSR"
+ attribute \enum_value_1001000 "OP_MTMSRD"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
+ wire width 7 input 1 \internal_op
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 1 \oe
+ wire width 1 output 2 \oe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 2 \oe_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
- wire width 1 input 3 \OE
+ wire width 1 output 3 \oe_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
+ wire width 1 input 4 \OE
process $group_0
assign \oe 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:433"
- switch \sel_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:434"
- attribute \nmigen.decoding "RC/2"
- case 2'10
- assign \oe \OE
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:432"
+ switch \internal_op
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:435"
+ attribute \nmigen.decoding "OP_MUL_H64/51|OP_MUL_H32/52"
+ case 7'0110011, 7'0110100
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:439"
+ attribute \nmigen.decoding ""
+ case
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441"
+ switch \sel_in
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442"
+ attribute \nmigen.decoding "RC/2"
+ case 2'10
+ assign \oe \OE
+ end
end
sync init
end
process $group_1
assign \oe_ok 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:433"
- switch \sel_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:434"
- attribute \nmigen.decoding "RC/2"
- case 2'10
- assign \oe_ok 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:432"
+ switch \internal_op
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:435"
+ attribute \nmigen.decoding "OP_MUL_H64/51|OP_MUL_H32/52"
+ case 7'0110011, 7'0110100
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:439"
+ attribute \nmigen.decoding ""
+ case
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441"
+ switch \sel_in
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442"
+ attribute \nmigen.decoding "RC/2"
+ case 2'10
+ assign \oe_ok 1'1
+ end
end
sync init
end
attribute \enum_value_100 "BA_BB"
attribute \enum_value_101 "BC"
attribute \enum_value_110 "WHOLE_REG"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:449"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:457"
wire width 3 input 0 \sel_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 3 output 1 \cr_bitfield
wire width 3 output 5 \cr_bitfield_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 6 \cr_bitfield_o_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:454"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462"
wire width 1 output 7 \whole_reg
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
wire width 5 input 8 \BB
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
wire width 5 input 9 \BA
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
wire width 5 input 10 \BT
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
wire width 5 input 11 \BI
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
wire width 5 input 12 \BC
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 3 input 13 \X_BFA
process $group_0
assign \cr_bitfield_ok 1'0
assign \cr_bitfield_ok 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:463"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471"
switch \sel_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:464"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:472"
attribute \nmigen.decoding "NONE/0"
case 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:466"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:474"
attribute \nmigen.decoding "CR0/1"
case 3'001
assign \cr_bitfield_ok 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:469"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:477"
attribute \nmigen.decoding "BI/2"
case 3'010
assign \cr_bitfield_ok 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:472"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:480"
attribute \nmigen.decoding "BFA/3"
case 3'011
assign \cr_bitfield_ok 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:475"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:483"
attribute \nmigen.decoding "BA_BB/4"
case 3'100
assign \cr_bitfield_ok 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:482"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:490"
attribute \nmigen.decoding "BC/5"
case 3'101
assign \cr_bitfield_ok 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:485"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:493"
attribute \nmigen.decoding "WHOLE_REG/6"
case 3'110
end
process $group_1
assign \cr_bitfield_b_ok 1'0
assign \cr_bitfield_b_ok 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:463"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471"
switch \sel_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:464"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:472"
attribute \nmigen.decoding "NONE/0"
case 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:466"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:474"
attribute \nmigen.decoding "CR0/1"
case 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:469"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:477"
attribute \nmigen.decoding "BI/2"
case 3'010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:472"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:480"
attribute \nmigen.decoding "BFA/3"
case 3'011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:475"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:483"
attribute \nmigen.decoding "BA_BB/4"
case 3'100
assign \cr_bitfield_b_ok 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:482"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:490"
attribute \nmigen.decoding "BC/5"
case 3'101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:485"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:493"
attribute \nmigen.decoding "WHOLE_REG/6"
case 3'110
end
process $group_2
assign \whole_reg 1'0
assign \whole_reg 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:463"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471"
switch \sel_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:464"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:472"
attribute \nmigen.decoding "NONE/0"
case 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:466"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:474"
attribute \nmigen.decoding "CR0/1"
case 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:469"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:477"
attribute \nmigen.decoding "BI/2"
case 3'010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:472"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:480"
attribute \nmigen.decoding "BFA/3"
case 3'011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:475"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:483"
attribute \nmigen.decoding "BA_BB/4"
case 3'100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:482"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:490"
attribute \nmigen.decoding "BC/5"
case 3'101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:485"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:493"
attribute \nmigen.decoding "WHOLE_REG/6"
case 3'110
assign \whole_reg 1'1
end
process $group_3
assign \cr_bitfield 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:463"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471"
switch \sel_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:464"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:472"
attribute \nmigen.decoding "NONE/0"
case 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:466"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:474"
attribute \nmigen.decoding "CR0/1"
case 3'001
assign \cr_bitfield 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:469"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:477"
attribute \nmigen.decoding "BI/2"
case 3'010
assign \cr_bitfield \BI [4:2]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:472"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:480"
attribute \nmigen.decoding "BFA/3"
case 3'011
assign \cr_bitfield \X_BFA
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:475"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:483"
attribute \nmigen.decoding "BA_BB/4"
case 3'100
assign \cr_bitfield \BA [4:2]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:482"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:490"
attribute \nmigen.decoding "BC/5"
case 3'101
assign \cr_bitfield \BC [4:2]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:485"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:493"
attribute \nmigen.decoding "WHOLE_REG/6"
case 3'110
end
end
process $group_4
assign \cr_bitfield_b 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:463"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471"
switch \sel_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:464"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:472"
attribute \nmigen.decoding "NONE/0"
case 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:466"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:474"
attribute \nmigen.decoding "CR0/1"
case 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:469"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:477"
attribute \nmigen.decoding "BI/2"
case 3'010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:472"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:480"
attribute \nmigen.decoding "BFA/3"
case 3'011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:475"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:483"
attribute \nmigen.decoding "BA_BB/4"
case 3'100
assign \cr_bitfield_b \BB [4:2]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:482"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:490"
attribute \nmigen.decoding "BC/5"
case 3'101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:485"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:493"
attribute \nmigen.decoding "WHOLE_REG/6"
case 3'110
end
end
process $group_5
assign \cr_bitfield_o 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:463"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471"
switch \sel_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:464"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:472"
attribute \nmigen.decoding "NONE/0"
case 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:466"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:474"
attribute \nmigen.decoding "CR0/1"
case 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:469"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:477"
attribute \nmigen.decoding "BI/2"
case 3'010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:472"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:480"
attribute \nmigen.decoding "BFA/3"
case 3'011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:475"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:483"
attribute \nmigen.decoding "BA_BB/4"
case 3'100
assign \cr_bitfield_o \BT [4:2]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:482"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:490"
attribute \nmigen.decoding "BC/5"
case 3'101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:485"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:493"
attribute \nmigen.decoding "WHOLE_REG/6"
case 3'110
end
end
process $group_6
assign \cr_bitfield_o_ok 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:463"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471"
switch \sel_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:464"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:472"
attribute \nmigen.decoding "NONE/0"
case 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:466"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:474"
attribute \nmigen.decoding "CR0/1"
case 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:469"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:477"
attribute \nmigen.decoding "BI/2"
case 3'010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:472"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:480"
attribute \nmigen.decoding "BFA/3"
case 3'011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:475"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:483"
attribute \nmigen.decoding "BA_BB/4"
case 3'100
assign \cr_bitfield_o_ok 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:482"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:490"
attribute \nmigen.decoding "BC/5"
case 3'101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:485"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:493"
attribute \nmigen.decoding "WHOLE_REG/6"
case 3'110
end
attribute \enum_value_010 "BF"
attribute \enum_value_011 "BT"
attribute \enum_value_100 "WHOLE_REG"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:501"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:509"
wire width 3 input 0 \sel_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:500"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508"
wire width 1 input 1 \rc_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 3 output 2 \cr_bitfield
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 3 \cr_bitfield_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:504"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:512"
wire width 1 output 4 \whole_reg
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 3 input 5 \X_BF
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 input 6 \XL_BT
process $group_0
assign \cr_bitfield_ok 1'0
assign \cr_bitfield_ok 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:512"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:520"
switch \sel_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:513"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521"
attribute \nmigen.decoding "NONE/0"
case 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:515"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:523"
attribute \nmigen.decoding "CR0/1"
case 3'001
assign \cr_bitfield_ok \rc_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:518"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:526"
attribute \nmigen.decoding "BF/2"
case 3'010
assign \cr_bitfield_ok 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529"
attribute \nmigen.decoding "BT/3"
case 3'011
assign \cr_bitfield_ok 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532"
attribute \nmigen.decoding "WHOLE_REG/4"
case 3'100
end
process $group_1
assign \whole_reg 1'0
assign \whole_reg 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:512"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:520"
switch \sel_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:513"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521"
attribute \nmigen.decoding "NONE/0"
case 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:515"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:523"
attribute \nmigen.decoding "CR0/1"
case 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:518"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:526"
attribute \nmigen.decoding "BF/2"
case 3'010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529"
attribute \nmigen.decoding "BT/3"
case 3'011
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532"
attribute \nmigen.decoding "WHOLE_REG/4"
case 3'100
assign \whole_reg 1'1
end
process $group_2
assign \cr_bitfield 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:512"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:520"
switch \sel_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:513"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521"
attribute \nmigen.decoding "NONE/0"
case 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:515"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:523"
attribute \nmigen.decoding "CR0/1"
case 3'001
assign \cr_bitfield 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:518"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:526"
attribute \nmigen.decoding "BF/2"
case 3'010
assign \cr_bitfield \X_BF
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529"
attribute \nmigen.decoding "BT/3"
case 3'011
assign \cr_bitfield \XL_BT [4:2]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532"
attribute \nmigen.decoding "WHOLE_REG/4"
case 3'100
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "test_issuer.core.pdecode2"
module \pdecode2
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:319"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:329"
wire width 1 input 0 \bigendian
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:328"
wire width 32 input 1 \raw_opcode_in
- attribute \enum_base_type "Function"
- attribute \enum_value_00000000000 "NONE"
- attribute \enum_value_00000000010 "ALU"
- attribute \enum_value_00000000100 "LDST"
- attribute \enum_value_00000001000 "SHIFT_ROT"
- attribute \enum_value_00000010000 "LOGICAL"
- attribute \enum_value_00000100000 "BRANCH"
- attribute \enum_value_00001000000 "CR"
- attribute \enum_value_00010000000 "TRAP"
- attribute \enum_value_00100000000 "MUL"
- attribute \enum_value_01000000000 "DIV"
- attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:33"
- wire width 11 output 2 \fn_unit
- attribute \enum_base_type "InternalOp"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:565"
+ wire width 64 input 2 \msr
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566"
+ wire width 64 input 3 \cia
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:32"
- wire width 7 output 3 \insn_type
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:38"
+ wire width 7 output 4 \insn_type
+ attribute \enum_base_type "Function"
+ attribute \enum_value_00000000000 "NONE"
+ attribute \enum_value_00000000010 "ALU"
+ attribute \enum_value_00000000100 "LDST"
+ attribute \enum_value_00000001000 "SHIFT_ROT"
+ attribute \enum_value_00000010000 "LOGICAL"
+ attribute \enum_value_00000100000 "BRANCH"
+ attribute \enum_value_00001000000 "CR"
+ attribute \enum_value_00010000000 "TRAP"
+ attribute \enum_value_00100000000 "MUL"
+ attribute \enum_value_01000000000 "DIV"
+ attribute \enum_value_10000000000 "SPR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:39"
+ wire width 11 output 5 \fn_unit
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 output 4 \imm
+ wire width 64 output 6 \imm
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 5 \imm_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:58"
- wire width 1 output 6 \lk
+ wire width 1 output 7 \imm_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 7 \rc
+ wire width 1 output 8 \rc
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 8 \rc_ok
+ wire width 1 output 9 \rc_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 9 \oe
+ wire width 1 output 10 \oe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 10 \oe_ok
+ wire width 1 output 11 \oe_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:44"
+ wire width 1 output 12 \invert_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:45"
+ wire width 1 output 13 \zero_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:50"
+ wire width 1 output 14 \invert_out
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:61"
- wire width 1 output 11 \invert_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:62"
- wire width 1 output 12 \zero_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:63"
- wire width 1 output 13 \invert_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 3 output 14 \cr_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 15 \cr_out_ok
+ wire width 1 output 15 \write_cr0
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:64"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:46"
wire width 2 output 16 \input_carry
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:65"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47"
wire width 1 output 17 \output_carry
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:66"
- wire width 1 output 18 \input_cr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:67"
- wire width 1 output 19 \output_cr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:68"
- wire width 1 output 20 \is_32bit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:69"
- wire width 1 output 21 \is_signed
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:71"
- wire width 4 output 22 \data_len
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:70"
- wire width 32 output 23 \insn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:72"
- wire width 1 output 24 \byte_reverse
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:73"
- wire width 1 output 25 \sign_extend
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 26 \reg1_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 27 \reg2_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:55"
- wire width 1 output 28 \read_cr_whole
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:51"
+ wire width 1 output 18 \is_32bit
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:52"
+ wire width 1 output 19 \is_signed
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53"
+ wire width 4 output 20 \data_len
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:37"
+ wire width 32 output 21 \insn
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 22 \reg1_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 23 \reg2_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:81"
+ wire width 1 output 24 \xer_in
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:59"
+ wire width 1 output 25 \read_cr_whole
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:60"
+ wire width 1 output 26 \write_cr_whole
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 27 \cr_in1_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 28 \cr_in2_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 29 \cr_in2_ok$1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:34"
+ wire width 64 output 30 \cia$2
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:41"
+ wire width 1 output 31 \lk
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 32 \fast1_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 33 \fast2_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:33"
+ wire width 64 output 34 \msr$3
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:57"
- wire width 1 output 29 \write_cr_whole
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 30 \cr_in1_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 31 \cr_in2_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 32 \cr_in2_ok$1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 33 \fast1_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 34 \fast2_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:75"
wire width 5 output 35 \traptype
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:58"
wire width 13 output 36 \trapaddr
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 37 \spr1_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48"
+ wire width 1 output 38 \input_cr
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:49"
+ wire width 1 output 39 \output_cr
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 40 \reg3_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:54"
+ wire width 1 output 41 \byte_reverse
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:55"
+ wire width 1 output 42 \sign_extend
+ attribute \enum_base_type "LDSTMode"
+ attribute \enum_value_00 "NONE"
+ attribute \enum_value_01 "update"
+ attribute \enum_value_10 "cix"
+ attribute \enum_value_11 "cx"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:56"
+ wire width 2 output 43 \ldst_mode
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 38 \reg3_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:74"
- wire width 1 output 39 \update
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 5 output 40 \reg1
+ wire width 5 output 44 \reg1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 5 output 41 \reg2
+ wire width 5 output 45 \reg2
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 5 output 42 \reg3
+ wire width 5 output 46 \reg3
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 3 output 43 \cr_in1
+ wire width 3 output 47 \cr_in1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 3 output 44 \cr_in2
+ wire width 3 output 48 \cr_in2
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 3 output 45 \cr_in2$2
+ wire width 3 output 49 \cr_in2$4
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 3 output 46 \fast1
+ wire width 3 output 50 \fast1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 3 output 47 \fast2
+ wire width 3 output 51 \fast2
attribute \enum_base_type "SPR"
attribute \enum_value_0000000001 "XER"
attribute \enum_value_0000000011 "DSCR"
attribute \enum_value_1110000010 "PPR32"
attribute \enum_value_1111111111 "PIR"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 10 output 48 \spr1
+ wire width 10 output 52 \spr1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 5 output 53 \rego
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 5 output 49 \rego
+ wire width 5 output 54 \ea
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 5 output 50 \ea
+ wire width 3 output 55 \cr_out
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 3 output 51 \fasto1
+ wire width 3 output 56 \fasto1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 3 output 52 \fasto2
+ wire width 3 output 57 \fasto2
attribute \enum_base_type "SPR"
attribute \enum_value_0000000001 "XER"
attribute \enum_value_0000000011 "DSCR"
attribute \enum_value_1110000010 "PPR32"
attribute \enum_value_1111111111 "PIR"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 10 output 53 \spro
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219"
- wire width 32 output 54 \opcode_in
+ wire width 10 output 58 \spro
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:229"
+ wire width 32 output 59 \opcode_in
attribute \enum_base_type "In1Sel"
attribute \enum_value_000 "NONE"
attribute \enum_value_001 "RA"
attribute \enum_value_011 "SPR"
attribute \enum_value_100 "RS"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
- wire width 3 output 55 \in1_sel
+ wire width 3 output 60 \in1_sel
attribute \enum_base_type "In2Sel"
attribute \enum_value_0000 "NONE"
attribute \enum_value_0001 "RB"
attribute \enum_value_1100 "SPR"
attribute \enum_value_1101 "RS"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
- wire width 4 output 56 \in2_sel
+ wire width 4 output 61 \in2_sel
attribute \enum_base_type "In3Sel"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "RS"
attribute \enum_value_10 "RB"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
- wire width 2 output 57 \in3_sel
+ wire width 2 output 62 \in3_sel
attribute \enum_base_type "OutSel"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "RT"
attribute \enum_value_10 "RA"
attribute \enum_value_11 "SPR"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
- wire width 2 output 58 \out_sel
+ wire width 2 output 63 \out_sel
attribute \enum_base_type "RC"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "RC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
- wire width 2 output 59 \rc_sel
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
+ wire width 2 output 64 \rc_sel
attribute \enum_base_type "CRInSel"
attribute \enum_value_000 "NONE"
attribute \enum_value_001 "CR0"
attribute \enum_value_101 "BC"
attribute \enum_value_110 "WHOLE_REG"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
- wire width 3 output 60 \cr_in
+ wire width 3 output 65 \cr_in
attribute \enum_base_type "CROutSel"
attribute \enum_value_000 "NONE"
attribute \enum_value_001 "CR0"
attribute \enum_value_011 "BT"
attribute \enum_value_100 "WHOLE_REG"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
- wire width 3 output 61 \cr_out$3
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:36"
- wire width 64 output 62 \nia
- attribute \enum_base_type "Function"
- attribute \enum_value_00000000000 "NONE"
- attribute \enum_value_00000000010 "ALU"
- attribute \enum_value_00000000100 "LDST"
- attribute \enum_value_00000001000 "SHIFT_ROT"
- attribute \enum_value_00000010000 "LOGICAL"
- attribute \enum_value_00000100000 "BRANCH"
- attribute \enum_value_00001000000 "CR"
- attribute \enum_value_00010000000 "TRAP"
- attribute \enum_value_00100000000 "MUL"
- attribute \enum_value_01000000000 "DIV"
- attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119"
- wire width 11 output 63 \function_unit
- attribute \enum_base_type "InternalOp"
+ wire width 3 output 66 \cr_out$5
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
+ attribute \enum_value_1001010 "OP_MTMSR"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
- wire width 7 output 64 \internal_op
+ wire width 7 output 67 \internal_op
+ attribute \enum_base_type "Function"
+ attribute \enum_value_00000000000 "NONE"
+ attribute \enum_value_00000000010 "ALU"
+ attribute \enum_value_00000000100 "LDST"
+ attribute \enum_value_00000001000 "SHIFT_ROT"
+ attribute \enum_value_00000010000 "LOGICAL"
+ attribute \enum_value_00000100000 "BRANCH"
+ attribute \enum_value_00001000000 "CR"
+ attribute \enum_value_00010000000 "TRAP"
+ attribute \enum_value_00100000000 "MUL"
+ attribute \enum_value_01000000000 "DIV"
+ attribute \enum_value_10000000000 "SPR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119"
+ wire width 11 output 68 \function_unit
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 65 \rego_ok
+ wire width 1 output 69 \rego_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 66 \ea_ok
+ wire width 1 output 70 \ea_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 67 \spro_ok
+ wire width 1 output 71 \spro_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 68 \fasto1_ok
+ wire width 1 output 72 \fasto1_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 69 \fasto2_ok
+ wire width 1 output 73 \fasto2_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 74 \cr_out_ok
attribute \enum_base_type "LdstLen"
attribute \enum_value_0000 "NONE"
attribute \enum_value_0001 "is1B"
attribute \enum_value_0100 "is4B"
attribute \enum_value_1000 "is8B"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
- wire width 4 output 70 \ldst_len
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 71 \inv_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 72 \inv_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 73 \cry_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 74 \is_32b
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 75 \sgn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 76 \lk$4
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 77 \br
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 78 \sgn_ext
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 79 \upd
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:35"
- wire width 8 output 80 \asmcode
+ wire width 4 output 75 \ldst_len
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 76 \inv_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 77 \inv_out
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 78 \cry_out
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 79 \is_32b
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 80 \sgn
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 81 \lk$6
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 82 \br
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 83 \sgn_ext
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:82"
+ wire width 1 output 84 \xer_out
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:71"
+ wire width 8 output 85 \asmcode
attribute \enum_base_type "Form"
attribute \enum_value_00000 "NONE"
attribute \enum_value_00001 "I"
attribute \enum_value_11011 "Z22"
attribute \enum_value_11100 "Z23"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
- wire width 5 output 81 \form
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 82 \rsrv
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 83 \sgl_pipe
+ wire width 5 output 86 \form
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 87 \rsrv
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 88 \sgl_pipe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
- wire width 8 output 84 \asmcode$5
+ wire width 8 output 89 \asmcode$7
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:133"
wire width 2 \dec_cry_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
wire width 1 \dec_LK
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \enum_base_type "LDSTMode"
+ attribute \enum_value_00 "NONE"
+ attribute \enum_value_01 "update"
+ attribute \enum_value_10 "cix"
+ attribute \enum_value_11 "cx"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
+ wire width 2 \dec_upd
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
wire width 5 \dec_RS
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
wire width 5 \dec_RT
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
wire width 5 \dec_RA
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
wire width 5 \dec_RB
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
wire width 16 \dec_SI
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
wire width 16 \dec_UI
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
wire width 5 \dec_SH32
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
wire width 6 \dec_sh
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
wire width 24 \dec_LI
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
wire width 1 \dec_Rc
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
wire width 1 \dec_OE
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
wire width 14 \dec_BD
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
wire width 5 \dec_BB
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
wire width 5 \dec_BA
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
wire width 5 \dec_BT
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
wire width 5 \dec_BO
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
wire width 5 \dec_BI
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
wire width 14 \dec_DS
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
wire width 5 \dec_BC
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:322"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
wire width 10 \dec_SPR
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 3 \dec_X_BF
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 3 \dec_X_BFA
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 5 \dec_XL_BT
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:345"
wire width 10 \dec_XL_XO
cell \dec \dec
connect \bigendian \bigendian
connect \out_sel \out_sel
connect \rc_sel \rc_sel
connect \cr_in \cr_in
- connect \cr_out \cr_out$3
- connect \function_unit \function_unit
+ connect \cr_out \cr_out$5
connect \internal_op \internal_op
+ connect \function_unit \function_unit
connect \ldst_len \ldst_len
connect \inv_a \inv_a
connect \inv_out \inv_out
connect \cry_out \cry_out
connect \is_32b \is_32b
connect \sgn \sgn
- connect \lk \lk$4
+ connect \lk \lk$6
connect \LK \dec_LK
connect \br \br
connect \sgn_ext \sgn_ext
- connect \upd \upd
+ connect \upd \dec_upd
connect \form \form
connect \rsrv \rsrv
connect \sgl_pipe \sgl_pipe
- connect \asmcode \asmcode$5
+ connect \asmcode \asmcode$7
connect \RS \dec_RS
connect \RT \dec_RT
connect \RA \dec_RA
attribute \enum_value_010 "RA_OR_ZERO"
attribute \enum_value_011 "SPR"
attribute \enum_value_100 "RS"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:80"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:75"
wire width 3 \dec_a_sel_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 5 \dec_a_reg_a
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 \dec_a_reg_a_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:83"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:78"
wire width 1 \dec_a_immz_out
attribute \enum_base_type "SPR"
attribute \enum_value_0000000001 "XER"
attribute \enum_value_1011 "CONST_SH32"
attribute \enum_value_1100 "SPR"
attribute \enum_value_1101 "RS"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:170"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:166"
wire width 4 \dec_b_sel_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 5 \dec_b_reg_b
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "RS"
attribute \enum_value_10 "RB"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:247"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243"
wire width 2 \dec_c_sel_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 5 \dec_c_reg_c
attribute \enum_value_01 "RT"
attribute \enum_value_10 "RA"
attribute \enum_value_11 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:275"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271"
wire width 2 \dec_o_sel_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 5 \dec_o_reg_o
connect \BO \dec_BO
connect \SPR \dec_SPR
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:351"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:347"
wire width 1 \dec_o2_lk
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 5 \dec_o2_reg_o
connect \reg_o_ok \dec_o2_reg_o_ok
connect \fast_o \dec_o2_fast_o
connect \fast_o_ok \dec_o2_fast_o_ok
- connect \upd \upd
+ connect \upd \dec_upd
connect \RA \dec_RA
end
attribute \enum_base_type "RC"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "RC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:388"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:387"
wire width 2 \dec_rc_sel_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 \dec_rc_rc
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "RC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:424"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:423"
wire width 2 \dec_oe_sel_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 \dec_oe_oe
wire width 1 \dec_oe_oe_ok
cell \dec_oe \dec_oe
connect \sel_in \dec_oe_sel_in
+ connect \internal_op \internal_op
connect \oe \dec_oe_oe
connect \oe_ok \dec_oe_oe_ok
connect \OE \dec_OE
attribute \enum_value_100 "BA_BB"
attribute \enum_value_101 "BC"
attribute \enum_value_110 "WHOLE_REG"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:449"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:457"
wire width 3 \dec_cr_in_sel_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 3 \dec_cr_in_cr_bitfield
wire width 3 \dec_cr_in_cr_bitfield_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 \dec_cr_in_cr_bitfield_o_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:454"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:462"
wire width 1 \dec_cr_in_whole_reg
cell \dec_cr_in \dec_cr_in
connect \sel_in \dec_cr_in_sel_in
attribute \enum_value_010 "BF"
attribute \enum_value_011 "BT"
attribute \enum_value_100 "WHOLE_REG"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:501"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:509"
wire width 3 \dec_cr_out_sel_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:500"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508"
wire width 1 \dec_cr_out_rc_in
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 3 \dec_cr_out_cr_bitfield
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 \dec_cr_out_cr_bitfield_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:504"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:512"
wire width 1 \dec_cr_out_whole_reg
cell \dec_cr_out \dec_cr_out
connect \sel_in \dec_cr_out_sel_in
connect \X_BF \dec_X_BF
connect \XL_BT \dec_XL_BT
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:590"
- wire width 7 $6
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:590"
- wire width 1 $7
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:590"
- cell $eq $8
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:670"
+ wire width 1 $8
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:670"
+ cell $eq $9
parameter \A_SIGNED 0
- parameter \A_WIDTH 11
+ parameter \A_WIDTH 7
parameter \B_SIGNED 0
- parameter \B_WIDTH 11
+ parameter \B_WIDTH 7
parameter \Y_WIDTH 1
- connect \A \function_unit
- connect \B 11'00000000000
- connect \Y $7
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:590"
- cell $mux $9
- parameter \WIDTH 7
connect \A \internal_op
- connect \B 7'0000000
- connect \S $7
- connect \Y $6
+ connect \B 7'0101110
+ connect \Y $8
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:646"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:672"
wire width 1 $10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:646"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:672"
cell $eq $11
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_WIDTH 7
parameter \Y_WIDTH 1
connect \A \internal_op
- connect \B 7'0111111
+ connect \B 7'0110001
connect \Y $10
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:653"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:676"
wire width 1 $12
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:653"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:676"
cell $eq $13
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_WIDTH 7
parameter \Y_WIDTH 1
connect \A \internal_op
- connect \B 7'0000000
+ connect \B 7'0111111
connect \Y $12
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:664"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:37"
+ wire width 1 \is_priv_insn
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:682"
wire width 1 $14
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:664"
- cell $eq $15
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:682"
+ cell $and $15
parameter \A_SIGNED 0
- parameter \A_WIDTH 7
+ parameter \A_WIDTH 1
parameter \B_SIGNED 0
- parameter \B_WIDTH 7
+ parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \insn_type
- connect \B 7'0111111
+ connect \A \is_priv_insn
+ connect \B \msr [14]
connect \Y $14
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:665"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:690"
wire width 1 $16
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:665"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:690"
cell $eq $17
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \B_WIDTH 7
parameter \Y_WIDTH 1
- connect \A \insn_type
- connect \B 7'1001001
+ connect \A \internal_op
+ connect \B 7'0000000
connect \Y $16
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:665"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:696"
wire width 1 $18
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:665"
- cell $or $19
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:696"
+ cell $eq $19
parameter \A_SIGNED 0
- parameter \A_WIDTH 1
+ parameter \A_WIDTH 7
parameter \B_SIGNED 0
- parameter \B_WIDTH 1
+ parameter \B_WIDTH 7
parameter \Y_WIDTH 1
- connect \A $14
- connect \B $16
+ connect \A \insn_type
+ connect \B 7'0111111
connect \Y $18
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:674"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697"
wire width 1 $20
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:674"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697"
cell $eq $21
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_WIDTH 7
parameter \Y_WIDTH 1
connect \A \insn_type
- connect \B 7'1000110
+ connect \B 7'1001001
connect \Y $20
end
- process $group_22
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697"
+ wire width 1 $22
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697"
+ cell $or $23
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A $18
+ connect \B $20
+ connect \Y $22
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:706"
+ wire width 1 $24
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:706"
+ cell $eq $25
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 7
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 7
+ parameter \Y_WIDTH 1
+ connect \A \insn_type
+ connect \B 7'1000110
+ connect \Y $24
+ end
+ process $group_82
assign \insn 32'00000000000000000000000000000000
- assign \nia 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \msr$3 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \cia$2 64'0000000000000000000000000000000000000000000000000000000000000000
assign \insn_type 7'0000000
assign \fn_unit 11'00000000000
assign \reg1 5'00000
assign \cr_in1_ok 1'0
assign \cr_in2 3'000
assign \cr_in2_ok 1'0
- assign \cr_in2$2 3'000
+ assign \cr_in2$4 3'000
assign \cr_in2_ok$1 1'0
- assign \read_cr_whole 1'0
assign \cr_out 3'000
assign \cr_out_ok 1'0
+ assign \read_cr_whole 1'0
assign \write_cr_whole 1'0
+ assign \write_cr0 1'0
assign \data_len 4'0000
assign \invert_a 1'0
assign \invert_out 1'0
assign \lk 1'0
assign \byte_reverse 1'0
assign \sign_extend 1'0
- assign \update 1'0
+ assign \ldst_mode 2'00
assign \input_cr 1'0
assign \output_cr 1'0
+ assign \xer_in 1'0
+ assign \xer_out 1'0
assign \trapaddr 13'0000000000000
assign \asmcode 8'00000000
assign \traptype 5'00000
assign \insn \opcode_in
- assign \nia 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \insn_type $6
+ assign \msr$3 \msr
+ assign \cia$2 \cia
+ assign \insn_type \internal_op
assign \fn_unit \function_unit
assign { \reg1_ok \reg1 } { \dec_a_reg_a_ok \dec_a_reg_a }
assign { \reg2_ok \reg2 } { \dec_b_reg_b_ok \dec_b_reg_b }
assign { \fasto2_ok \fasto2 } { \dec_o2_fast_o_ok \dec_o2_fast_o }
assign { \cr_in1_ok \cr_in1 } { \dec_cr_in_cr_bitfield_ok \dec_cr_in_cr_bitfield }
assign { \cr_in2_ok \cr_in2 } { \dec_cr_in_cr_bitfield_b_ok \dec_cr_in_cr_bitfield_b }
- assign { \cr_in2_ok$1 \cr_in2$2 } { \dec_cr_in_cr_bitfield_o_ok \dec_cr_in_cr_bitfield_o }
- assign \read_cr_whole \dec_cr_in_whole_reg
+ assign { \cr_in2_ok$1 \cr_in2$4 } { \dec_cr_in_cr_bitfield_o_ok \dec_cr_in_cr_bitfield_o }
assign { \cr_out_ok \cr_out } { \dec_cr_out_cr_bitfield_ok \dec_cr_out_cr_bitfield }
+ assign \read_cr_whole \dec_cr_in_whole_reg
assign \write_cr_whole \dec_cr_out_whole_reg
+ assign \write_cr0 \dec_cr_out_cr_bitfield_ok
assign \data_len \ldst_len
assign \invert_a \inv_a
assign \invert_out \inv_out
assign \output_carry \cry_out
assign \is_32bit \is_32b
assign \is_signed \sgn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:634"
- switch { \lk$4 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:634"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:656"
+ switch { \lk$6 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:656"
case 1'1
assign \lk \dec_LK
end
end
switch { }
case
- assign \update \upd
+ assign \ldst_mode \dec_upd
end
switch { }
case
end
switch { }
case
- assign \output_cr \cr_out$3 [0]
+ assign \output_cr \cr_out$5 [0]
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:646"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:670"
+ switch { $8 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:670"
+ case 1'1
+ assign \xer_in 1'1
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:672"
switch { $10 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:646"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:672"
case 1'1
- assign \trapaddr 13'0000001110000
+ assign \xer_out 1'1
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:653"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:676"
switch { $12 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:653"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:676"
case 1'1
- assign { \trapaddr \traptype \update \sign_extend \byte_reverse \data_len \insn \is_signed \is_32bit \output_cr \input_cr \output_carry \input_carry \invert_out \zero_a \invert_a { \oe_ok \oe } { \rc_ok \rc } \lk \write_cr_whole { \cr_out_ok \cr_out } \read_cr_whole { \cr_in2_ok$1 \cr_in2$2 } { \cr_in2_ok \cr_in2 } { \cr_in1_ok \cr_in1 } { \fasto2_ok \fasto2 } { \fasto1_ok \fasto1 } { \fast2_ok \fast2 } { \fast1_ok \fast1 } { \spr1_ok \spr1 } { \spro_ok \spro } { \imm_ok \imm } { \reg3_ok \reg3 } { \reg2_ok \reg2 } { \reg1_ok \reg1 } { \ea_ok \ea } { \rego_ok \rego } \nia \asmcode \fn_unit \insn_type } 313'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
+ assign \trapaddr 13'0000001110000
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:682"
+ switch { $16 $14 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:682"
+ case 2'-1
+ assign { \write_cr0 \write_cr_whole \read_cr_whole \trapaddr \traptype \ldst_mode \sign_extend \byte_reverse \data_len \is_signed \is_32bit \invert_out \output_cr \input_cr \output_carry \input_carry \zero_a \invert_a \oe_ok \oe \rc_ok \rc \lk \imm_ok \imm \fn_unit \insn_type \insn \cia$2 \msr$3 { \cr_out_ok \cr_out } { \cr_in2_ok$1 \cr_in2$4 } { \cr_in2_ok \cr_in2 } { \cr_in1_ok \cr_in1 } { \fasto2_ok \fasto2 } { \fasto1_ok \fasto1 } { \fast2_ok \fast2 } { \fast1_ok \fast1 } \xer_out \xer_in { \spr1_ok \spr1 } { \spro_ok \spro } { \reg3_ok \reg3 } { \reg2_ok \reg2 } { \reg1_ok \reg1 } { \ea_ok \ea } { \rego_ok \rego } \asmcode } 381'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
+ assign \insn \opcode_in
+ assign \insn_type 7'0111111
+ assign \fn_unit 11'00010000000
+ assign \trapaddr 13'0000001110000
+ assign \traptype 5'00010
+ assign \msr$3 \msr
+ assign \cia$2 \cia
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:690"
+ case 2'1-
+ assign { \write_cr0 \write_cr_whole \read_cr_whole \trapaddr \traptype \ldst_mode \sign_extend \byte_reverse \data_len \is_signed \is_32bit \invert_out \output_cr \input_cr \output_carry \input_carry \zero_a \invert_a \oe_ok \oe \rc_ok \rc \lk \imm_ok \imm \fn_unit \insn_type \insn \cia$2 \msr$3 { \cr_out_ok \cr_out } { \cr_in2_ok$1 \cr_in2$4 } { \cr_in2_ok \cr_in2 } { \cr_in1_ok \cr_in1 } { \fasto2_ok \fasto2 } { \fasto1_ok \fasto1 } { \fast2_ok \fast2 } { \fast1_ok \fast1 } \xer_out \xer_in { \spr1_ok \spr1 } { \spro_ok \spro } { \reg3_ok \reg3 } { \reg2_ok \reg2 } { \reg1_ok \reg1 } { \ea_ok \ea } { \rego_ok \rego } \asmcode } 381'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
assign \insn \opcode_in
assign \insn_type 7'0111111
assign \fn_unit 11'00010000000
assign \trapaddr 13'0000001110000
assign \traptype 5'10000
+ assign \msr$3 \msr
+ assign \cia$2 \cia
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:665"
- switch { $18 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:665"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697"
+ switch { $22 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:697"
case 1'1
assign \fasto1 3'101
assign \fasto1_ok 1'1
assign \fasto2 3'110
assign \fasto2_ok 1'1
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:674"
- switch { $20 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:674"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:706"
+ switch { $24 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:706"
case 1'1
assign \fast1 3'101
assign \fast1_ok 1'1
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:81"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:76"
wire width 32 \insn_in
process $group_1
assign \insn_in 32'00000000000000000000000000000000
assign \insn_in \opcode_in
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:171"
- wire width 32 \insn_in$22
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:167"
+ wire width 32 \insn_in$26
process $group_2
- assign \insn_in$22 32'00000000000000000000000000000000
- assign \insn_in$22 \opcode_in
+ assign \insn_in$26 32'00000000000000000000000000000000
+ assign \insn_in$26 \opcode_in
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248"
- wire width 32 \insn_in$23
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244"
+ wire width 32 \insn_in$27
process $group_3
- assign \insn_in$23 32'00000000000000000000000000000000
- assign \insn_in$23 \opcode_in
+ assign \insn_in$27 32'00000000000000000000000000000000
+ assign \insn_in$27 \opcode_in
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:276"
- wire width 32 \insn_in$24
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:272"
+ wire width 32 \insn_in$28
process $group_4
- assign \insn_in$24 32'00000000000000000000000000000000
- assign \insn_in$24 \opcode_in
+ assign \insn_in$28 32'00000000000000000000000000000000
+ assign \insn_in$28 \opcode_in
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:352"
- wire width 32 \insn_in$25
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:348"
+ wire width 32 \insn_in$29
process $group_5
- assign \insn_in$25 32'00000000000000000000000000000000
- assign \insn_in$25 \opcode_in
+ assign \insn_in$29 32'00000000000000000000000000000000
+ assign \insn_in$29 \opcode_in
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:389"
- wire width 32 \insn_in$26
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:388"
+ wire width 32 \insn_in$30
process $group_6
- assign \insn_in$26 32'00000000000000000000000000000000
- assign \insn_in$26 \opcode_in
+ assign \insn_in$30 32'00000000000000000000000000000000
+ assign \insn_in$30 \opcode_in
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:425"
- wire width 32 \insn_in$27
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:424"
+ wire width 32 \insn_in$31
process $group_7
- assign \insn_in$27 32'00000000000000000000000000000000
- assign \insn_in$27 \opcode_in
+ assign \insn_in$31 32'00000000000000000000000000000000
+ assign \insn_in$31 \opcode_in
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450"
- wire width 32 \insn_in$28
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:458"
+ wire width 32 \insn_in$32
process $group_8
- assign \insn_in$28 32'00000000000000000000000000000000
- assign \insn_in$28 \opcode_in
+ assign \insn_in$32 32'00000000000000000000000000000000
+ assign \insn_in$32 \opcode_in
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502"
- wire width 32 \insn_in$29
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:510"
+ wire width 32 \insn_in$33
process $group_9
- assign \insn_in$29 32'00000000000000000000000000000000
- assign \insn_in$29 \opcode_in
+ assign \insn_in$33 32'00000000000000000000000000000000
+ assign \insn_in$33 \opcode_in
sync init
end
process $group_10
attribute \enum_value_01 "RT"
attribute \enum_value_10 "RA"
attribute \enum_value_11 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:350"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:346"
wire width 2 \sel_in
process $group_14
assign \sel_in 2'00
end
process $group_19
assign \dec_cr_out_sel_in 3'000
- assign \dec_cr_out_sel_in \cr_out$3
+ assign \dec_cr_out_sel_in \cr_out$5
sync init
end
process $group_20
assign \dec_cr_out_rc_in \dec_rc_rc
sync init
end
+ process $group_81
+ assign \is_priv_insn 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:38"
+ switch \internal_op
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:40"
+ attribute \nmigen.decoding "OP_ATTN/5|OP_MFMSR/71|OP_MTMSRD/72|OP_MTMSR/74|OP_RFID/70"
+ case 7'0000101, 7'1000111, 7'1001000, 7'1001010, 7'1000110
+ assign \is_priv_insn 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:44"
+ attribute \nmigen.decoding "OP_MFSPR/46|OP_MTSPR/49"
+ case 7'0101110, 7'0110001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:45"
+ switch { \insn [20] }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:45"
+ case 1'1
+ assign \is_priv_insn 1'1
+ end
+ end
+ sync init
+ end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu_alu0.p"
module \p
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153"
wire width 1 input 0 \p_valid_i
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154"
wire width 1 input 1 \p_ready_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:156"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158"
wire width 1 \trigger
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:203"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205"
wire width 1 $1
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:203"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205"
cell $and $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
attribute \generator "nMigen"
attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu_alu0.n"
module \n
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
wire width 1 input 0 \n_valid_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
wire width 1 input 1 \n_ready_i
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:249"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251"
wire width 1 \trigger
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:295"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:297"
wire width 1 $1
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:295"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:297"
cell $and $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
attribute \generator "nMigen"
attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu_alu0.pipe.p"
module \p$2
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153"
wire width 1 input 0 \p_valid_i
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154"
wire width 1 input 1 \p_ready_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:156"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158"
wire width 1 \trigger
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:203"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205"
wire width 1 $1
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:203"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205"
cell $and $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
attribute \generator "nMigen"
attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu_alu0.pipe.n"
module \n$3
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
wire width 1 input 0 \n_valid_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
wire width 1 input 1 \n_ready_i
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:249"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251"
wire width 1 \trigger
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:295"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:297"
wire width 1 $1
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:295"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:297"
cell $and $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
attribute \generator "nMigen"
attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu_alu0.pipe.input"
module \input
- attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
wire width 2 input 0 \muxid
- attribute \enum_base_type "InternalOp"
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 7 input 1 \op__insn_type
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00100000000 "MUL"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 11 input 2 \op__fn_unit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 64 input 3 \op__imm_data__imm
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 input 4 \op__imm_data__imm_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 input 5 \op__lk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 input 6 \op__rc__rc
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 input 7 \op__rc__rc_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 input 8 \op__oe__oe
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 input 9 \op__oe__oe_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 input 10 \op__invert_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 input 11 \op__zero_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 input 12 \op__invert_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 3 input 13 \op__write_cr__data
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 input 14 \op__write_cr__ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 5 \op__rc__rc
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 6 \op__rc__rc_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 7 \op__oe__oe
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 8 \op__oe__oe_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 9 \op__invert_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 10 \op__zero_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 11 \op__invert_out
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 12 \op__write_cr0
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 2 input 15 \op__input_carry
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 input 16 \op__output_carry
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 input 17 \op__input_cr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 input 18 \op__output_cr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 input 19 \op__is_32bit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 input 20 \op__is_signed
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 4 input 21 \op__data_len
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 32 input 22 \op__insn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 input 23 \op__byte_reverse
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 input 24 \op__sign_extend
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
- wire width 64 input 25 \ra
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
- wire width 64 input 26 \rb
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
- wire width 1 input 27 \xer_so
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
- wire width 2 input 28 \xer_ca
- attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
- wire width 2 output 29 \muxid$1
- attribute \enum_base_type "InternalOp"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 2 input 13 \op__input_carry
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 14 \op__output_carry
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 15 \op__is_32bit
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 16 \op__is_signed
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 4 input 17 \op__data_len
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 input 18 \op__insn
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 64 input 19 \ra
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 64 input 20 \rb
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 1 input 21 \xer_so
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 2 input 22 \xer_ca
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+ wire width 2 output 23 \muxid$1
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 7 output 30 \op__insn_type$2
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 7 output 24 \op__insn_type$2
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00000000010 "ALU"
attribute \enum_value_00100000000 "MUL"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 11 output 31 \op__fn_unit$3
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 64 output 32 \op__imm_data__imm$4
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 output 33 \op__imm_data__imm_ok$5
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 output 34 \op__lk$6
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 output 35 \op__rc__rc$7
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 output 36 \op__rc__rc_ok$8
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 output 37 \op__oe__oe$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 output 38 \op__oe__oe_ok$10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 output 39 \op__invert_a$11
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 output 40 \op__zero_a$12
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 output 41 \op__invert_out$13
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 3 output 42 \op__write_cr__data$14
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 output 43 \op__write_cr__ok$15
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 11 output 25 \op__fn_unit$3
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 output 26 \op__imm_data__imm$4
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 27 \op__imm_data__imm_ok$5
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 28 \op__rc__rc$6
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 29 \op__rc__rc_ok$7
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 30 \op__oe__oe$8
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 31 \op__oe__oe_ok$9
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 32 \op__invert_a$10
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 33 \op__zero_a$11
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 34 \op__invert_out$12
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 35 \op__write_cr0$13
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 2 output 44 \op__input_carry$16
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 output 45 \op__output_carry$17
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 output 46 \op__input_cr$18
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 output 47 \op__output_cr$19
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 output 48 \op__is_32bit$20
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 output 49 \op__is_signed$21
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 4 output 50 \op__data_len$22
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 32 output 51 \op__insn$23
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 output 52 \op__byte_reverse$24
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 output 53 \op__sign_extend$25
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
- wire width 64 output 54 \ra$26
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
- wire width 64 output 55 \rb$27
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
- wire width 1 output 56 \xer_so$28
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
- wire width 2 output 57 \xer_ca$29
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 2 output 36 \op__input_carry$14
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 37 \op__output_carry$15
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 38 \op__is_32bit$16
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 39 \op__is_signed$17
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 4 output 40 \op__data_len$18
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 output 41 \op__insn$19
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 64 output 42 \ra$20
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 64 output 43 \rb$21
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 1 output 44 \xer_so$22
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 2 output 45 \xer_ca$23
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20"
wire width 64 \a
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:24"
- wire width 64 $30
+ wire width 64 $24
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:24"
- cell $not $31
+ cell $not $25
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
connect \A \ra
- connect \Y $30
+ connect \Y $24
end
process $group_0
assign \a 64'0000000000000000000000000000000000000000000000000000000000000000
switch { \op__invert_a }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:23"
case 1'1
- assign \a $30
+ assign \a $24
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:25"
case
assign \a \ra
sync init
end
process $group_1
- assign \ra$26 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \ra$26 \a
+ assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \ra$20 \a
sync init
end
process $group_2
- assign \xer_ca$29 2'00
+ assign \xer_ca$23 2'00
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:36"
switch \op__input_carry
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:37"
attribute \nmigen.decoding "ZERO/0"
case 2'00
- assign \xer_ca$29 2'00
+ assign \xer_ca$23 2'00
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:39"
attribute \nmigen.decoding "ONE/1"
case 2'01
- assign \xer_ca$29 2'11
+ assign \xer_ca$23 2'11
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:41"
attribute \nmigen.decoding "CA/2"
case 2'10
- assign \xer_ca$29 \xer_ca
+ assign \xer_ca$23 \xer_ca
end
sync init
end
process $group_3
- assign \xer_so$28 1'0
+ assign \xer_so$22 1'0
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:47"
switch { \op__oe__oe_ok }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:47"
case 1'1
- assign \xer_so$28 \xer_so
+ assign \xer_so$22 \xer_so
end
sync init
end
assign \op__fn_unit$3 11'00000000000
assign \op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000
assign \op__imm_data__imm_ok$5 1'0
- assign \op__lk$6 1'0
- assign \op__rc__rc$7 1'0
- assign \op__rc__rc_ok$8 1'0
- assign \op__oe__oe$9 1'0
- assign \op__oe__oe_ok$10 1'0
- assign \op__invert_a$11 1'0
- assign \op__zero_a$12 1'0
- assign \op__invert_out$13 1'0
- assign \op__write_cr__data$14 3'000
- assign \op__write_cr__ok$15 1'0
- assign \op__input_carry$16 2'00
- assign \op__output_carry$17 1'0
- assign \op__input_cr$18 1'0
- assign \op__output_cr$19 1'0
- assign \op__is_32bit$20 1'0
- assign \op__is_signed$21 1'0
- assign \op__data_len$22 4'0000
- assign \op__insn$23 32'00000000000000000000000000000000
- assign \op__byte_reverse$24 1'0
- assign \op__sign_extend$25 1'0
- assign { \op__sign_extend$25 \op__byte_reverse$24 \op__insn$23 \op__data_len$22 \op__is_signed$21 \op__is_32bit$20 \op__output_cr$19 \op__input_cr$18 \op__output_carry$17 \op__input_carry$16 { \op__write_cr__ok$15 \op__write_cr__data$14 } \op__invert_out$13 \op__zero_a$12 \op__invert_a$11 { \op__oe__oe_ok$10 \op__oe__oe$9 } { \op__rc__rc_ok$8 \op__rc__rc$7 } \op__lk$6 { \op__imm_data__imm_ok$5 \op__imm_data__imm$4 } \op__fn_unit$3 \op__insn_type$2 } { \op__sign_extend \op__byte_reverse \op__insn \op__data_len \op__is_signed \op__is_32bit \op__output_cr \op__input_cr \op__output_carry \op__input_carry { \op__write_cr__ok \op__write_cr__data } \op__invert_out \op__zero_a \op__invert_a { \op__oe__oe_ok \op__oe__oe } { \op__rc__rc_ok \op__rc__rc } \op__lk { \op__imm_data__imm_ok \op__imm_data__imm } \op__fn_unit \op__insn_type }
+ assign \op__rc__rc$6 1'0
+ assign \op__rc__rc_ok$7 1'0
+ assign \op__oe__oe$8 1'0
+ assign \op__oe__oe_ok$9 1'0
+ assign \op__invert_a$10 1'0
+ assign \op__zero_a$11 1'0
+ assign \op__invert_out$12 1'0
+ assign \op__write_cr0$13 1'0
+ assign \op__input_carry$14 2'00
+ assign \op__output_carry$15 1'0
+ assign \op__is_32bit$16 1'0
+ assign \op__is_signed$17 1'0
+ assign \op__data_len$18 4'0000
+ assign \op__insn$19 32'00000000000000000000000000000000
+ assign { \op__insn$19 \op__data_len$18 \op__is_signed$17 \op__is_32bit$16 \op__output_carry$15 \op__input_carry$14 \op__write_cr0$13 \op__invert_out$12 \op__zero_a$11 \op__invert_a$10 { \op__oe__oe_ok$9 \op__oe__oe$8 } { \op__rc__rc_ok$7 \op__rc__rc$6 } { \op__imm_data__imm_ok$5 \op__imm_data__imm$4 } \op__fn_unit$3 \op__insn_type$2 } { \op__insn \op__data_len \op__is_signed \op__is_32bit \op__output_carry \op__input_carry \op__write_cr0 \op__invert_out \op__zero_a \op__invert_a { \op__oe__oe_ok \op__oe__oe } { \op__rc__rc_ok \op__rc__rc } { \op__imm_data__imm_ok \op__imm_data__imm } \op__fn_unit \op__insn_type }
sync init
end
- process $group_29
- assign \rb$27 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \rb$27 \rb
+ process $group_23
+ assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \rb$21 \rb
sync init
end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu_alu0.pipe.main"
module \main
- attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
wire width 2 input 0 \muxid
- attribute \enum_base_type "InternalOp"
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 7 input 1 \op__insn_type
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00100000000 "MUL"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 11 input 2 \op__fn_unit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 64 input 3 \op__imm_data__imm
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 input 4 \op__imm_data__imm_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 input 5 \op__lk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 input 6 \op__rc__rc
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 input 7 \op__rc__rc_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 input 8 \op__oe__oe
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 input 9 \op__oe__oe_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 input 10 \op__invert_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 input 11 \op__zero_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 input 12 \op__invert_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 3 input 13 \op__write_cr__data
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 input 14 \op__write_cr__ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 5 \op__rc__rc
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 6 \op__rc__rc_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 7 \op__oe__oe
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 8 \op__oe__oe_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 9 \op__invert_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 10 \op__zero_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 11 \op__invert_out
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 12 \op__write_cr0
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 2 input 15 \op__input_carry
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 input 16 \op__output_carry
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 input 17 \op__input_cr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 input 18 \op__output_cr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 input 19 \op__is_32bit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 input 20 \op__is_signed
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 4 input 21 \op__data_len
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 32 input 22 \op__insn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 input 23 \op__byte_reverse
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 input 24 \op__sign_extend
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
- wire width 64 input 25 \ra
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
- wire width 64 input 26 \rb
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
- wire width 1 input 27 \xer_so
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
- wire width 2 input 28 \xer_ca
- attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
- wire width 2 output 29 \muxid$1
- attribute \enum_base_type "InternalOp"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 2 input 13 \op__input_carry
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 14 \op__output_carry
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 15 \op__is_32bit
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 16 \op__is_signed
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 4 input 17 \op__data_len
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 input 18 \op__insn
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 64 input 19 \ra
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 64 input 20 \rb
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 1 input 21 \xer_so
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 2 input 22 \xer_ca
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+ wire width 2 output 23 \muxid$1
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 7 output 30 \op__insn_type$2
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 7 output 24 \op__insn_type$2
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00000000010 "ALU"
attribute \enum_value_00100000000 "MUL"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 11 output 31 \op__fn_unit$3
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 64 output 32 \op__imm_data__imm$4
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 output 33 \op__imm_data__imm_ok$5
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 output 34 \op__lk$6
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 output 35 \op__rc__rc$7
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 output 36 \op__rc__rc_ok$8
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 output 37 \op__oe__oe$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 output 38 \op__oe__oe_ok$10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 output 39 \op__invert_a$11
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 output 40 \op__zero_a$12
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 output 41 \op__invert_out$13
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 3 output 42 \op__write_cr__data$14
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 output 43 \op__write_cr__ok$15
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 11 output 25 \op__fn_unit$3
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 output 26 \op__imm_data__imm$4
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 27 \op__imm_data__imm_ok$5
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 28 \op__rc__rc$6
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 29 \op__rc__rc_ok$7
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 30 \op__oe__oe$8
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 31 \op__oe__oe_ok$9
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 32 \op__invert_a$10
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 33 \op__zero_a$11
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 34 \op__invert_out$12
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 35 \op__write_cr0$13
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 2 output 44 \op__input_carry$16
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 output 45 \op__output_carry$17
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 output 46 \op__input_cr$18
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 output 47 \op__output_cr$19
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 output 48 \op__is_32bit$20
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 output 49 \op__is_signed$21
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 4 output 50 \op__data_len$22
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 32 output 51 \op__insn$23
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 output 52 \op__byte_reverse$24
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 output 53 \op__sign_extend$25
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 2 output 36 \op__input_carry$14
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 37 \op__output_carry$15
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 38 \op__is_32bit$16
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 39 \op__is_signed$17
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 4 output 40 \op__data_len$18
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 output 41 \op__insn$19
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 output 54 \o
+ wire width 64 output 42 \o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 55 \o_ok
+ wire width 1 output 43 \o_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 4 output 56 \cr_a
+ wire width 4 output 44 \cr_a
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 57 \cr_a_ok
+ wire width 1 output 45 \cr_a_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 2 output 58 \xer_ca$26
+ wire width 2 output 46 \xer_ca$20
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 59 \xer_ca_ok
+ wire width 1 output 47 \xer_ca_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 2 output 60 \xer_ov
+ wire width 2 output 48 \xer_ov
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 61 \xer_ov_ok
+ wire width 1 output 49 \xer_ov_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 62 \xer_so$27
+ wire width 1 output 50 \xer_so$21
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:39"
wire width 1 \is_32bit
process $group_0
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:40"
wire width 1 \sign_bit
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:42"
- wire width 1 $28
+ wire width 1 $22
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:42"
- cell $mux $29
+ cell $mux $23
parameter \WIDTH 1
connect \A \ra [63]
connect \B \ra [31]
connect \S \is_32bit
- connect \Y $28
+ connect \Y $22
end
process $group_1
assign \sign_bit 1'0
- assign \sign_bit $28
+ assign \sign_bit $22
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:46"
wire width 66 \add_a
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:49"
- wire width 1 $30
+ wire width 1 $24
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:49"
- cell $eq $31
+ cell $eq $25
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \op__insn_type
connect \B 7'0000010
- connect \Y $30
+ connect \Y $24
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:50"
- wire width 1 $32
+ wire width 1 $26
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:50"
- cell $eq $33
+ cell $eq $27
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \op__insn_type
connect \B 7'0001010
- connect \Y $32
+ connect \Y $26
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:50"
- wire width 1 $34
+ wire width 1 $28
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:50"
- cell $or $35
+ cell $or $29
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $30
- connect \B $32
- connect \Y $34
+ connect \A $24
+ connect \B $26
+ connect \Y $28
end
process $group_2
assign \add_a 66'000000000000000000000000000000000000000000000000000000000000000000
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:50"
- switch { $34 }
+ switch { $28 }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:50"
case 1'1
assign \add_a { 1'0 \ra \xer_ca [0] }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:47"
wire width 66 \add_b
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:49"
- wire width 1 $36
+ wire width 1 $30
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:49"
- cell $eq $37
+ cell $eq $31
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \op__insn_type
connect \B 7'0000010
- connect \Y $36
+ connect \Y $30
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:50"
- wire width 1 $38
+ wire width 1 $32
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:50"
- cell $eq $39
+ cell $eq $33
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \op__insn_type
connect \B 7'0001010
- connect \Y $38
+ connect \Y $32
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:50"
- wire width 1 $40
+ wire width 1 $34
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:50"
- cell $or $41
+ cell $or $35
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $36
- connect \B $38
- connect \Y $40
+ connect \A $30
+ connect \B $32
+ connect \Y $34
end
process $group_3
assign \add_b 66'000000000000000000000000000000000000000000000000000000000000000000
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:50"
- switch { $40 }
+ switch { $34 }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:50"
case 1'1
assign \add_b { 1'0 \rb 1'1 }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:48"
wire width 66 \add_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:49"
- wire width 1 $42
+ wire width 1 $36
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:49"
- cell $eq $43
+ cell $eq $37
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \op__insn_type
connect \B 7'0000010
- connect \Y $42
+ connect \Y $36
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:50"
- wire width 1 $44
+ wire width 1 $38
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:50"
- cell $eq $45
+ cell $eq $39
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \op__insn_type
connect \B 7'0001010
- connect \Y $44
+ connect \Y $38
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:50"
- wire width 1 $46
+ wire width 1 $40
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:50"
- cell $or $47
+ cell $or $41
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $42
- connect \B $44
- connect \Y $46
+ connect \A $36
+ connect \B $38
+ connect \Y $40
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:54"
- wire width 67 $48
+ wire width 67 $42
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:54"
- wire width 67 $49
+ wire width 67 $43
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:54"
- cell $add $50
+ cell $add $44
parameter \A_SIGNED 0
parameter \A_WIDTH 66
parameter \B_SIGNED 0
parameter \Y_WIDTH 67
connect \A \add_a
connect \B \add_b
- connect \Y $49
+ connect \Y $43
end
- connect $48 $49
+ connect $42 $43
process $group_4
assign \add_o 66'000000000000000000000000000000000000000000000000000000000000000000
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:50"
- switch { $46 }
+ switch { $40 }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:50"
case 1'1
- assign \add_o $48 [65:0]
+ assign \add_o $42 [65:0]
end
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91"
- wire width 1 $51
+ wire width 1 $45
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91"
- cell $eq $52
+ cell $eq $46
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \op__data_len
connect \B 1'1
- connect \Y $51
+ connect \Y $45
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:93"
- wire width 1 $53
+ wire width 1 $47
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:93"
- cell $eq $54
+ cell $eq $48
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \op__data_len
connect \B 2'10
- connect \Y $53
+ connect \Y $47
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:95"
- wire width 1 $55
+ wire width 1 $49
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:95"
- cell $eq $56
+ cell $eq $50
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \op__data_len
connect \B 3'100
- connect \Y $55
+ connect \Y $49
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:106"
- wire width 1 $57
+ wire width 1 $51
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:101"
wire width 8 \eqs
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:106"
- cell $reduce_or $58
+ cell $reduce_or $52
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \Y_WIDTH 1
connect \A \eqs
- connect \Y $57
+ connect \Y $51
end
process $group_5
assign \o 64'0000000000000000000000000000000000000000000000000000000000000000
attribute \nmigen.decoding "OP_EXTS/31"
case 7'0011111
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91"
- switch { $51 }
+ switch { $45 }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:91"
case 1'1
assign \o { { \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] } \ra [7:0] }
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:93"
- switch { $53 }
+ switch { $47 }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:93"
case 1'1
assign \o { { \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] } \ra [15:0] }
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:95"
- switch { $55 }
+ switch { $49 }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:95"
case 1'1
assign \o { { \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] } \ra [31:0] }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:100"
attribute \nmigen.decoding "OP_CMPEQB/12"
case 7'0001100
- assign \o [0] $57
+ assign \o [0] $51
end
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:77"
wire width 2 \ca
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:79"
- wire width 1 $59
+ wire width 1 $53
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:79"
- cell $xor $60
+ cell $xor $54
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [32]
connect \B \rb [32]
- connect \Y $59
+ connect \Y $53
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:79"
- wire width 1 $61
+ wire width 1 $55
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:79"
- cell $xor $62
+ cell $xor $56
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \add_o [33]
- connect \B $59
- connect \Y $61
+ connect \B $53
+ connect \Y $55
end
process $group_7
assign \ca 2'00
attribute \nmigen.decoding "OP_ADD/2"
case 7'0000010
assign \ca [0] \add_o [65]
- assign \ca [1] $61
+ assign \ca [1] $55
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:90"
attribute \nmigen.decoding "OP_EXTS/31"
case 7'0011111
sync init
end
process $group_8
- assign \xer_ca$26 2'00
+ assign \xer_ca$20 2'00
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:59"
switch \op__insn_type
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:61"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:70"
attribute \nmigen.decoding "OP_ADD/2"
case 7'0000010
- assign \xer_ca$26 \ca
+ assign \xer_ca$20 \ca
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:90"
attribute \nmigen.decoding "OP_EXTS/31"
case 7'0011111
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:83"
wire width 2 \ov
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:16"
- wire width 1 $63
+ wire width 1 $57
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:16"
- cell $xor $64
+ cell $xor $58
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ca [0]
connect \B \add_o [64]
- connect \Y $63
+ connect \Y $57
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:16"
- wire width 1 $65
+ wire width 1 $59
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:16"
- wire width 1 $66
+ wire width 1 $60
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:16"
- cell $xor $67
+ cell $xor $61
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [63]
connect \B \rb [63]
- connect \Y $66
+ connect \Y $60
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:16"
- cell $not $68
+ cell $not $62
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $66
- connect \Y $65
+ connect \A $60
+ connect \Y $59
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:16"
- wire width 1 $69
+ wire width 1 $63
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:16"
- cell $and $70
+ cell $and $64
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $63
- connect \B $65
- connect \Y $69
+ connect \A $57
+ connect \B $59
+ connect \Y $63
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:16"
- wire width 1 $71
+ wire width 1 $65
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:16"
- cell $xor $72
+ cell $xor $66
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ca [1]
connect \B \add_o [32]
- connect \Y $71
+ connect \Y $65
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:16"
- wire width 1 $73
+ wire width 1 $67
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:16"
- wire width 1 $74
+ wire width 1 $68
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:16"
- cell $xor $75
+ cell $xor $69
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ra [31]
connect \B \rb [31]
- connect \Y $74
+ connect \Y $68
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:16"
- cell $not $76
+ cell $not $70
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $74
- connect \Y $73
+ connect \A $68
+ connect \Y $67
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:16"
- wire width 1 $77
+ wire width 1 $71
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:16"
- cell $and $78
+ cell $and $72
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $71
- connect \B $73
- connect \Y $77
+ connect \A $65
+ connect \B $67
+ connect \Y $71
end
process $group_10
assign \ov 2'00
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:70"
attribute \nmigen.decoding "OP_ADD/2"
case 7'0000010
- assign \ov [0] $69
- assign \ov [1] $77
+ assign \ov [0] $63
+ assign \ov [1] $71
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:90"
attribute \nmigen.decoding "OP_EXTS/31"
case 7'0011111
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:105"
- wire width 1 $79
+ wire width 1 $73
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:105"
- cell $eq $80
+ cell $eq $74
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \src1
connect \B \rb [7:0]
- connect \Y $79
+ connect \Y $73
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:105"
- wire width 1 $81
+ wire width 1 $75
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:105"
- cell $eq $82
+ cell $eq $76
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \src1
connect \B \rb [15:8]
- connect \Y $81
+ connect \Y $75
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:105"
- wire width 1 $83
+ wire width 1 $77
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:105"
- cell $eq $84
+ cell $eq $78
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \src1
connect \B \rb [23:16]
- connect \Y $83
+ connect \Y $77
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:105"
- wire width 1 $85
+ wire width 1 $79
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:105"
- cell $eq $86
+ cell $eq $80
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \src1
connect \B \rb [31:24]
- connect \Y $85
+ connect \Y $79
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:105"
- wire width 1 $87
+ wire width 1 $81
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:105"
- cell $eq $88
+ cell $eq $82
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \src1
connect \B \rb [39:32]
- connect \Y $87
+ connect \Y $81
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:105"
- wire width 1 $89
+ wire width 1 $83
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:105"
- cell $eq $90
+ cell $eq $84
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \src1
connect \B \rb [47:40]
- connect \Y $89
+ connect \Y $83
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:105"
- wire width 1 $91
+ wire width 1 $85
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:105"
- cell $eq $92
+ cell $eq $86
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \src1
connect \B \rb [55:48]
- connect \Y $91
+ connect \Y $85
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:105"
- wire width 1 $93
+ wire width 1 $87
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:105"
- cell $eq $94
+ cell $eq $88
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \src1
connect \B \rb [63:56]
- connect \Y $93
+ connect \Y $87
end
process $group_14
assign \eqs 8'00000000
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:100"
attribute \nmigen.decoding "OP_CMPEQB/12"
case 7'0001100
- assign \eqs [0] $79
- assign \eqs [1] $81
- assign \eqs [2] $83
- assign \eqs [3] $85
- assign \eqs [4] $87
- assign \eqs [5] $89
- assign \eqs [6] $91
- assign \eqs [7] $93
+ assign \eqs [0] $73
+ assign \eqs [1] $75
+ assign \eqs [2] $77
+ assign \eqs [3] $79
+ assign \eqs [4] $81
+ assign \eqs [5] $83
+ assign \eqs [6] $85
+ assign \eqs [7] $87
end
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:108"
- wire width 1 $95
+ wire width 1 $89
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:108"
- cell $reduce_or $96
+ cell $reduce_or $90
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \Y_WIDTH 1
connect \A \eqs
- connect \Y $95
+ connect \Y $89
end
process $group_15
assign \cr_a 4'0000
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:100"
attribute \nmigen.decoding "OP_CMPEQB/12"
case 7'0001100
- assign \cr_a { 1'0 $95 2'00 }
+ assign \cr_a { 1'0 $89 2'00 }
end
sync init
end
sync init
end
process $group_17
- assign \xer_so$27 1'0
- assign \xer_so$27 \xer_so
+ assign \xer_so$21 1'0
+ assign \xer_so$21 \xer_so
sync init
end
process $group_18
assign \op__fn_unit$3 11'00000000000
assign \op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000
assign \op__imm_data__imm_ok$5 1'0
- assign \op__lk$6 1'0
- assign \op__rc__rc$7 1'0
- assign \op__rc__rc_ok$8 1'0
- assign \op__oe__oe$9 1'0
- assign \op__oe__oe_ok$10 1'0
- assign \op__invert_a$11 1'0
- assign \op__zero_a$12 1'0
- assign \op__invert_out$13 1'0
- assign \op__write_cr__data$14 3'000
- assign \op__write_cr__ok$15 1'0
- assign \op__input_carry$16 2'00
- assign \op__output_carry$17 1'0
- assign \op__input_cr$18 1'0
- assign \op__output_cr$19 1'0
- assign \op__is_32bit$20 1'0
- assign \op__is_signed$21 1'0
- assign \op__data_len$22 4'0000
- assign \op__insn$23 32'00000000000000000000000000000000
- assign \op__byte_reverse$24 1'0
- assign \op__sign_extend$25 1'0
- assign { \op__sign_extend$25 \op__byte_reverse$24 \op__insn$23 \op__data_len$22 \op__is_signed$21 \op__is_32bit$20 \op__output_cr$19 \op__input_cr$18 \op__output_carry$17 \op__input_carry$16 { \op__write_cr__ok$15 \op__write_cr__data$14 } \op__invert_out$13 \op__zero_a$12 \op__invert_a$11 { \op__oe__oe_ok$10 \op__oe__oe$9 } { \op__rc__rc_ok$8 \op__rc__rc$7 } \op__lk$6 { \op__imm_data__imm_ok$5 \op__imm_data__imm$4 } \op__fn_unit$3 \op__insn_type$2 } { \op__sign_extend \op__byte_reverse \op__insn \op__data_len \op__is_signed \op__is_32bit \op__output_cr \op__input_cr \op__output_carry \op__input_carry { \op__write_cr__ok \op__write_cr__data } \op__invert_out \op__zero_a \op__invert_a { \op__oe__oe_ok \op__oe__oe } { \op__rc__rc_ok \op__rc__rc } \op__lk { \op__imm_data__imm_ok \op__imm_data__imm } \op__fn_unit \op__insn_type }
+ assign \op__rc__rc$6 1'0
+ assign \op__rc__rc_ok$7 1'0
+ assign \op__oe__oe$8 1'0
+ assign \op__oe__oe_ok$9 1'0
+ assign \op__invert_a$10 1'0
+ assign \op__zero_a$11 1'0
+ assign \op__invert_out$12 1'0
+ assign \op__write_cr0$13 1'0
+ assign \op__input_carry$14 2'00
+ assign \op__output_carry$15 1'0
+ assign \op__is_32bit$16 1'0
+ assign \op__is_signed$17 1'0
+ assign \op__data_len$18 4'0000
+ assign \op__insn$19 32'00000000000000000000000000000000
+ assign { \op__insn$19 \op__data_len$18 \op__is_signed$17 \op__is_32bit$16 \op__output_carry$15 \op__input_carry$14 \op__write_cr0$13 \op__invert_out$12 \op__zero_a$11 \op__invert_a$10 { \op__oe__oe_ok$9 \op__oe__oe$8 } { \op__rc__rc_ok$7 \op__rc__rc$6 } { \op__imm_data__imm_ok$5 \op__imm_data__imm$4 } \op__fn_unit$3 \op__insn_type$2 } { \op__insn \op__data_len \op__is_signed \op__is_32bit \op__output_carry \op__input_carry \op__write_cr0 \op__invert_out \op__zero_a \op__invert_a { \op__oe__oe_ok \op__oe__oe } { \op__rc__rc_ok \op__rc__rc } { \op__imm_data__imm_ok \op__imm_data__imm } \op__fn_unit \op__insn_type }
sync init
end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu_alu0.pipe.output"
module \output
- attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
wire width 2 input 0 \muxid
- attribute \enum_base_type "InternalOp"
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 7 input 1 \op__insn_type
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00100000000 "MUL"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 11 input 2 \op__fn_unit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 64 input 3 \op__imm_data__imm
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 input 4 \op__imm_data__imm_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 input 5 \op__lk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 input 6 \op__rc__rc
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 input 7 \op__rc__rc_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 input 8 \op__oe__oe
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 input 9 \op__oe__oe_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 input 10 \op__invert_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 input 11 \op__zero_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 input 12 \op__invert_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 3 input 13 \op__write_cr__data
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 input 14 \op__write_cr__ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 5 \op__rc__rc
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 6 \op__rc__rc_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 7 \op__oe__oe
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 8 \op__oe__oe_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 9 \op__invert_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 10 \op__zero_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 11 \op__invert_out
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 12 \op__write_cr0
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 2 input 15 \op__input_carry
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 input 16 \op__output_carry
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 input 17 \op__input_cr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 input 18 \op__output_cr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 input 19 \op__is_32bit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 input 20 \op__is_signed
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 4 input 21 \op__data_len
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 32 input 22 \op__insn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 input 23 \op__byte_reverse
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 input 24 \op__sign_extend
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 2 input 13 \op__input_carry
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 14 \op__output_carry
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 15 \op__is_32bit
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 16 \op__is_signed
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 4 input 17 \op__data_len
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 input 18 \op__insn
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 input 25 \o
+ wire width 64 input 19 \o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 input 26 \o_ok
+ wire width 1 input 20 \o_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 4 input 27 \cr_a
+ wire width 4 input 21 \cr_a
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 2 input 28 \xer_ca
+ wire width 2 input 22 \xer_ca
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 2 input 29 \xer_ov
+ wire width 2 input 23 \xer_ov
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 input 30 \xer_so
- attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
- wire width 2 output 31 \muxid$1
- attribute \enum_base_type "InternalOp"
+ wire width 1 input 24 \xer_so
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+ wire width 2 output 25 \muxid$1
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 7 output 32 \op__insn_type$2
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 7 output 26 \op__insn_type$2
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00000000010 "ALU"
attribute \enum_value_00100000000 "MUL"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 11 output 33 \op__fn_unit$3
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 64 output 34 \op__imm_data__imm$4
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 output 35 \op__imm_data__imm_ok$5
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 output 36 \op__lk$6
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 output 37 \op__rc__rc$7
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 output 38 \op__rc__rc_ok$8
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 output 39 \op__oe__oe$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 output 40 \op__oe__oe_ok$10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 output 41 \op__invert_a$11
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 output 42 \op__zero_a$12
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 output 43 \op__invert_out$13
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 3 output 44 \op__write_cr__data$14
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 output 45 \op__write_cr__ok$15
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 11 output 27 \op__fn_unit$3
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 output 28 \op__imm_data__imm$4
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 29 \op__imm_data__imm_ok$5
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 30 \op__rc__rc$6
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 31 \op__rc__rc_ok$7
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 32 \op__oe__oe$8
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 33 \op__oe__oe_ok$9
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 34 \op__invert_a$10
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 35 \op__zero_a$11
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 36 \op__invert_out$12
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 37 \op__write_cr0$13
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 2 output 46 \op__input_carry$16
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 output 47 \op__output_carry$17
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 output 48 \op__input_cr$18
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 output 49 \op__output_cr$19
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 output 50 \op__is_32bit$20
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 output 51 \op__is_signed$21
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 4 output 52 \op__data_len$22
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 32 output 53 \op__insn$23
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 output 54 \op__byte_reverse$24
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 output 55 \op__sign_extend$25
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 output 56 \o$26
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 57 \o_ok$27
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 4 output 58 \cr_a$28
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 59 \cr_a_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 2 output 60 \xer_ca$29
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 61 \xer_ca_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 2 output 62 \xer_ov$30
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 63 \xer_ov_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 64 \xer_so$31
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 65 \xer_so_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:19"
- wire width 65 \o$32
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:22"
- wire width 65 $33
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:22"
- wire width 64 $34
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:22"
- cell $not $35
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 2 output 38 \op__input_carry$14
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 39 \op__output_carry$15
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 40 \op__is_32bit$16
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 41 \op__is_signed$17
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 4 output 42 \op__data_len$18
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 output 43 \op__insn$19
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 64 output 44 \o$20
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 45 \o_ok$21
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 4 output 46 \cr_a$22
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 47 \cr_a_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 2 output 48 \xer_ca$23
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 49 \xer_ca_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 2 output 50 \xer_ov$24
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 51 \xer_ov_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 52 \xer_so$25
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 53 \xer_so_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:23"
+ wire width 65 \o$26
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:26"
+ wire width 65 $27
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:26"
+ wire width 64 $28
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:26"
+ cell $not $29
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
connect \A \o
- connect \Y $34
+ connect \Y $28
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:22"
- cell $pos $36
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:26"
+ cell $pos $30
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 65
- connect \A $34
- connect \Y $33
+ connect \A $28
+ connect \Y $27
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 65 $37
+ wire width 65 $31
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- cell $pos $38
+ cell $pos $32
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 65
connect \A \o
- connect \Y $37
+ connect \Y $31
end
process $group_0
- assign \o$32 65'00000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:21"
+ assign \o$26 65'00000000000000000000000000000000000000000000000000000000000000000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:25"
switch { \op__invert_out }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:25"
case 1'1
- assign \o$32 $33
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:23"
+ assign \o$26 $27
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:27"
case
- assign \o$32 $37
+ assign \o$26 $31
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:35"
wire width 64 \target
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:251"
- wire width 64 $39
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:251"
- cell $pos $40
- parameter \A_SIGNED 0
- parameter \A_WIDTH 32
- parameter \Y_WIDTH 64
- connect \A \o$32 [31:0]
- connect \Y $39
- end
process $group_1
assign \target 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:30"
- switch { \op__is_32bit }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:30"
- case 1'1
- assign \target $39
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:32"
- case
- assign \target \o$32 [63:0]
- end
+ assign \target \o$26 [63:0]
sync init
end
process $group_2
- assign \xer_ca$29 2'00
- assign \xer_ca$29 \xer_ca
+ assign \xer_ca$23 2'00
+ assign \xer_ca$23 \xer_ca
sync init
end
process $group_3
assign \xer_ca_ok \op__output_carry
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:44"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:54"
wire width 1 \is_cmp
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:53"
- wire width 1 $41
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:53"
- cell $eq $42
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:63"
+ wire width 1 $33
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:63"
+ cell $eq $34
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \op__insn_type
connect \B 7'0001010
- connect \Y $41
+ connect \Y $33
end
process $group_4
assign \is_cmp 1'0
- assign \is_cmp $41
+ assign \is_cmp $33
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:45"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:55"
wire width 1 \is_cmpeqb
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:54"
- wire width 1 $43
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:54"
- cell $eq $44
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:64"
+ wire width 1 $35
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:64"
+ cell $eq $36
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \op__insn_type
connect \B 7'0001100
- connect \Y $43
+ connect \Y $35
end
process $group_5
assign \is_cmpeqb 1'0
- assign \is_cmpeqb $43
+ assign \is_cmpeqb $35
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:43"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:53"
wire width 1 \msb_test
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:55"
- wire width 1 $45
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:55"
- cell $xor $46
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \target [63]
- connect \B \is_cmp
- connect \Y $45
- end
process $group_6
assign \msb_test 1'0
- assign \msb_test $45
+ assign \msb_test \target [63]
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:40"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:50"
wire width 1 \is_nzero
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:56"
- wire width 1 $47
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:56"
- cell $reduce_bool $48
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71"
+ wire width 1 $37
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71"
+ cell $reduce_bool $38
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 1
connect \A \target
- connect \Y $47
+ connect \Y $37
end
process $group_7
assign \is_nzero 1'0
- assign \is_nzero $47
+ assign \is_nzero $37
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:51"
wire width 1 \is_positive
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:57"
- wire width 1 $49
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:57"
- cell $not $50
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77"
+ wire width 1 $39
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77"
+ cell $not $40
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \msb_test
- connect \Y $49
+ connect \Y $39
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:57"
- wire width 1 $51
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:57"
- cell $and $52
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77"
+ wire width 1 $41
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77"
+ cell $and $42
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \is_nzero
- connect \B $49
- connect \Y $51
+ connect \B $39
+ connect \Y $41
end
process $group_8
assign \is_positive 1'0
- assign \is_positive $51
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:72"
+ switch { \is_cmp }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:72"
+ case 1'1
+ assign \is_positive \msb_test
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:75"
+ case
+ assign \is_positive $41
+ end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:42"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:52"
wire width 1 \is_negative
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:58"
- wire width 1 $53
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:58"
- cell $and $54
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:74"
+ wire width 1 $43
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:74"
+ cell $not $44
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \msb_test
+ connect \Y $43
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:74"
+ wire width 1 $45
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:74"
+ cell $and $46
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \is_nzero
- connect \B \msb_test
- connect \Y $53
+ connect \B $43
+ connect \Y $45
end
process $group_9
assign \is_negative 1'0
- assign \is_negative $53
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:72"
+ switch { \is_cmp }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:72"
+ case 1'1
+ assign \is_negative $45
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:75"
+ case
+ assign \is_negative \msb_test
+ end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:47"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:57"
wire width 4 \cr0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:46"
- wire width 1 \so
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:63"
- wire width 1 $55
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:63"
- cell $not $56
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:82"
+ wire width 1 $47
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:82"
+ cell $not $48
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \is_nzero
- connect \Y $55
+ connect \Y $47
end
process $group_10
assign \cr0 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:60"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:79"
switch { \is_cmpeqb }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:60"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:79"
case 1'1
assign \cr0 \cr_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:62"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81"
case
- assign \cr0 { \is_negative \is_positive $55 \so }
+ assign \cr0 { \is_negative \is_positive $47 \xer_so$25 }
end
sync init
end
process $group_11
- assign \o$26 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \o$26 \o$32 [63:0]
+ assign \o$20 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \o$20 \o$26 [63:0]
sync init
end
process $group_12
- assign \o_ok$27 1'0
- assign \o_ok$27 \o_ok
+ assign \o_ok$21 1'0
+ assign \o_ok$21 \o_ok
sync init
end
process $group_13
- assign \cr_a$28 4'0000
- assign \cr_a$28 \cr0
+ assign \cr_a$22 4'0000
+ assign \cr_a$22 \cr0
sync init
end
process $group_14
assign \cr_a_ok 1'0
- assign \cr_a_ok \op__write_cr__ok
+ assign \cr_a_ok \op__write_cr0
sync init
end
process $group_15
assign \op__fn_unit$3 11'00000000000
assign \op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000
assign \op__imm_data__imm_ok$5 1'0
- assign \op__lk$6 1'0
- assign \op__rc__rc$7 1'0
- assign \op__rc__rc_ok$8 1'0
- assign \op__oe__oe$9 1'0
- assign \op__oe__oe_ok$10 1'0
- assign \op__invert_a$11 1'0
- assign \op__zero_a$12 1'0
- assign \op__invert_out$13 1'0
- assign \op__write_cr__data$14 3'000
- assign \op__write_cr__ok$15 1'0
- assign \op__input_carry$16 2'00
- assign \op__output_carry$17 1'0
- assign \op__input_cr$18 1'0
- assign \op__output_cr$19 1'0
- assign \op__is_32bit$20 1'0
- assign \op__is_signed$21 1'0
- assign \op__data_len$22 4'0000
- assign \op__insn$23 32'00000000000000000000000000000000
- assign \op__byte_reverse$24 1'0
- assign \op__sign_extend$25 1'0
- assign { \op__sign_extend$25 \op__byte_reverse$24 \op__insn$23 \op__data_len$22 \op__is_signed$21 \op__is_32bit$20 \op__output_cr$19 \op__input_cr$18 \op__output_carry$17 \op__input_carry$16 { \op__write_cr__ok$15 \op__write_cr__data$14 } \op__invert_out$13 \op__zero_a$12 \op__invert_a$11 { \op__oe__oe_ok$10 \op__oe__oe$9 } { \op__rc__rc_ok$8 \op__rc__rc$7 } \op__lk$6 { \op__imm_data__imm_ok$5 \op__imm_data__imm$4 } \op__fn_unit$3 \op__insn_type$2 } { \op__sign_extend \op__byte_reverse \op__insn \op__data_len \op__is_signed \op__is_32bit \op__output_cr \op__input_cr \op__output_carry \op__input_carry { \op__write_cr__ok \op__write_cr__data } \op__invert_out \op__zero_a \op__invert_a { \op__oe__oe_ok \op__oe__oe } { \op__rc__rc_ok \op__rc__rc } \op__lk { \op__imm_data__imm_ok \op__imm_data__imm } \op__fn_unit \op__insn_type }
+ assign \op__rc__rc$6 1'0
+ assign \op__rc__rc_ok$7 1'0
+ assign \op__oe__oe$8 1'0
+ assign \op__oe__oe_ok$9 1'0
+ assign \op__invert_a$10 1'0
+ assign \op__zero_a$11 1'0
+ assign \op__invert_out$12 1'0
+ assign \op__write_cr0$13 1'0
+ assign \op__input_carry$14 2'00
+ assign \op__output_carry$15 1'0
+ assign \op__is_32bit$16 1'0
+ assign \op__is_signed$17 1'0
+ assign \op__data_len$18 4'0000
+ assign \op__insn$19 32'00000000000000000000000000000000
+ assign { \op__insn$19 \op__data_len$18 \op__is_signed$17 \op__is_32bit$16 \op__output_carry$15 \op__input_carry$14 \op__write_cr0$13 \op__invert_out$12 \op__zero_a$11 \op__invert_a$10 { \op__oe__oe_ok$9 \op__oe__oe$8 } { \op__rc__rc_ok$7 \op__rc__rc$6 } { \op__imm_data__imm_ok$5 \op__imm_data__imm$4 } \op__fn_unit$3 \op__insn_type$2 } { \op__insn \op__data_len \op__is_signed \op__is_32bit \op__output_carry \op__input_carry \op__write_cr0 \op__invert_out \op__zero_a \op__invert_a { \op__oe__oe_ok \op__oe__oe } { \op__rc__rc_ok \op__rc__rc } { \op__imm_data__imm_ok \op__imm_data__imm } \op__fn_unit \op__insn_type }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:26"
- wire width 1 $57
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:26"
- cell $or $58
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:28"
+ wire width 1 \oe
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:29"
+ wire width 1 $49
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:29"
+ cell $and $50
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \xer_so
- connect \B \xer_ov [0]
- connect \Y $57
- end
- process $group_40
- assign \so 1'0
- assign \so $57
- sync init
+ connect \A \op__oe__oe
+ connect \B \op__oe__oe_ok
+ connect \Y $49
end
- process $group_41
- assign \xer_so$31 1'0
- assign \xer_so$31 \so
+ process $group_34
+ assign \oe 1'0
+ assign \oe $49
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30"
- wire width 1 $59
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30"
- cell $and $60
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:56"
+ wire width 1 \so
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:32"
+ wire width 1 $51
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:32"
+ cell $or $52
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \op__oe__oe
- connect \B \op__oe__oe_ok
- connect \Y $59
+ connect \A \xer_so
+ connect \B \xer_ov [0]
+ connect \Y $51
end
- process $group_42
- assign \xer_so_ok 1'0
- assign \xer_so_ok $59
+ process $group_35
+ assign \so 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30"
+ switch { \oe }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30"
+ case 1'1
+ assign \so $51
+ end
sync init
end
- process $group_43
- assign \xer_ov$30 2'00
- assign \xer_ov$30 \xer_ov
+ process $group_36
+ assign \xer_so$25 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30"
+ switch { \oe }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30"
+ case 1'1
+ assign \xer_so$25 \so
+ end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:32"
- wire width 1 $61
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:32"
- cell $and $62
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \op__oe__oe
- connect \B \op__oe__oe_ok
- connect \Y $61
+ process $group_37
+ assign \xer_so_ok 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30"
+ switch { \oe }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30"
+ case 1'1
+ assign \xer_so_ok 1'1
+ end
+ sync init
end
- process $group_44
+ process $group_38
+ assign \xer_ov$24 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30"
+ switch { \oe }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30"
+ case 1'1
+ assign \xer_ov$24 \xer_ov
+ end
+ sync init
+ end
+ process $group_39
assign \xer_ov_ok 1'0
- assign \xer_ov_ok $61
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30"
+ switch { \oe }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30"
+ case 1'1
+ assign \xer_ov_ok 1'1
+ end
sync init
end
end
wire width 1 input 0 \rst
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153"
wire width 1 input 2 \p_valid_i
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154"
wire width 1 output 3 \p_ready_o
- attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
wire width 2 input 4 \muxid
- attribute \enum_base_type "InternalOp"
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 7 input 5 \op__insn_type
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00100000000 "MUL"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 11 input 6 \op__fn_unit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 64 input 7 \op__imm_data__imm
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 input 8 \op__imm_data__imm_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 input 9 \op__lk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 input 10 \op__rc__rc
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 input 11 \op__rc__rc_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 input 12 \op__oe__oe
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 input 13 \op__oe__oe_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 input 14 \op__invert_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 input 15 \op__zero_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 input 16 \op__invert_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 3 input 17 \op__write_cr__data
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 input 18 \op__write_cr__ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 9 \op__rc__rc
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 10 \op__rc__rc_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 11 \op__oe__oe
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 12 \op__oe__oe_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 13 \op__invert_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 14 \op__zero_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 15 \op__invert_out
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 16 \op__write_cr0
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 2 input 19 \op__input_carry
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 input 20 \op__output_carry
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 input 21 \op__input_cr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 input 22 \op__output_cr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 input 23 \op__is_32bit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 input 24 \op__is_signed
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 4 input 25 \op__data_len
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 32 input 26 \op__insn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 input 27 \op__byte_reverse
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 input 28 \op__sign_extend
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
- wire width 64 input 29 \ra
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
- wire width 64 input 30 \rb
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
- wire width 1 input 31 \xer_so
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
- wire width 2 input 32 \xer_ca
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244"
- wire width 1 output 33 \n_valid_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245"
- wire width 1 input 34 \n_ready_i
- attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
- wire width 2 output 35 \muxid$1
- attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 2 input 17 \op__input_carry
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 18 \op__output_carry
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 19 \op__is_32bit
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 20 \op__is_signed
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 4 input 21 \op__data_len
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 input 22 \op__insn
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 64 input 23 \ra
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 64 input 24 \rb
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 1 input 25 \xer_so
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 2 input 26 \xer_ca
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
+ wire width 1 output 27 \n_valid_o
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
+ wire width 1 input 28 \n_ready_i
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+ wire width 2 output 29 \muxid$1
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
wire width 2 \muxid$1$next
- attribute \enum_base_type "InternalOp"
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 7 output 36 \op__insn_type$2
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 7 output 30 \op__insn_type$2
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 7 \op__insn_type$2$next
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00100000000 "MUL"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 11 output 37 \op__fn_unit$3
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 11 output 31 \op__fn_unit$3
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 11 \op__fn_unit$3$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 64 output 38 \op__imm_data__imm$4
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 output 32 \op__imm_data__imm$4
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 64 \op__imm_data__imm$4$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 output 39 \op__imm_data__imm_ok$5
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 33 \op__imm_data__imm_ok$5
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \op__imm_data__imm_ok$5$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 output 40 \op__lk$6
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 \op__lk$6$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 output 41 \op__rc__rc$7
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 \op__rc__rc$7$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 output 42 \op__rc__rc_ok$8
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 \op__rc__rc_ok$8$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 output 43 \op__oe__oe$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 \op__oe__oe$9$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 output 44 \op__oe__oe_ok$10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 \op__oe__oe_ok$10$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 output 45 \op__invert_a$11
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 \op__invert_a$11$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 output 46 \op__zero_a$12
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 \op__zero_a$12$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 output 47 \op__invert_out$13
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 \op__invert_out$13$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 3 output 48 \op__write_cr__data$14
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 3 \op__write_cr__data$14$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 output 49 \op__write_cr__ok$15
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 \op__write_cr__ok$15$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 34 \op__rc__rc$6
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__rc__rc$6$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 35 \op__rc__rc_ok$7
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__rc__rc_ok$7$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 36 \op__oe__oe$8
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__oe__oe$8$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 37 \op__oe__oe_ok$9
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__oe__oe_ok$9$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 38 \op__invert_a$10
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__invert_a$10$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 39 \op__zero_a$11
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__zero_a$11$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 40 \op__invert_out$12
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__invert_out$12$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 41 \op__write_cr0$13
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__write_cr0$13$next
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 2 output 50 \op__input_carry$16
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 2 \op__input_carry$16$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 output 51 \op__output_carry$17
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 \op__output_carry$17$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 output 52 \op__input_cr$18
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 \op__input_cr$18$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 output 53 \op__output_cr$19
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 \op__output_cr$19$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 output 54 \op__is_32bit$20
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 \op__is_32bit$20$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 output 55 \op__is_signed$21
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 \op__is_signed$21$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 4 output 56 \op__data_len$22
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 4 \op__data_len$22$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 32 output 57 \op__insn$23
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 32 \op__insn$23$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 output 58 \op__byte_reverse$24
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 \op__byte_reverse$24$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 output 59 \op__sign_extend$25
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 \op__sign_extend$25$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 output 60 \o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 2 output 42 \op__input_carry$14
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 2 \op__input_carry$14$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 43 \op__output_carry$15
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__output_carry$15$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 44 \op__is_32bit$16
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__is_32bit$16$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 45 \op__is_signed$17
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__is_signed$17$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 4 output 46 \op__data_len$18
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 4 \op__data_len$18$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 output 47 \op__insn$19
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 \op__insn$19$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 64 output 48 \o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 64 \o$next
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 61 \o_ok
+ wire width 1 output 49 \o_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 \o_ok$next
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 4 output 62 \cr_a
+ wire width 4 output 50 \cr_a
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 4 \cr_a$next
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 63 \cr_a_ok
+ wire width 1 output 51 \cr_a_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 \cr_a_ok$next
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 2 output 64 \xer_ca$26
+ wire width 2 output 52 \xer_ca$20
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 2 \xer_ca$26$next
+ wire width 2 \xer_ca$20$next
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 65 \xer_ca_ok
+ wire width 1 output 53 \xer_ca_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 \xer_ca_ok$next
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 2 output 66 \xer_ov
+ wire width 2 output 54 \xer_ov
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 2 \xer_ov$next
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 67 \xer_ov_ok
+ wire width 1 output 55 \xer_ov_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 \xer_ov_ok$next
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 68 \xer_so$27
+ wire width 1 output 56 \xer_so$21
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 \xer_so$27$next
+ wire width 1 \xer_so$21$next
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 69 \xer_so_ok
+ wire width 1 output 57 \xer_so_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 \xer_so_ok$next
cell \p$2 \p
connect \n_valid_o \n_valid_o
connect \n_ready_i \n_ready_i
end
- attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
wire width 2 \input_muxid
- attribute \enum_base_type "InternalOp"
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 7 \input_op__insn_type
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00100000000 "MUL"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 11 \input_op__fn_unit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 64 \input_op__imm_data__imm
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \input_op__imm_data__imm_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 \input_op__lk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \input_op__rc__rc
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \input_op__rc__rc_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \input_op__oe__oe
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \input_op__oe__oe_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \input_op__invert_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
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wire width 1 \input_op__zero_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
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wire width 1 \input_op__invert_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 3 \input_op__write_cr__data
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 \input_op__write_cr__ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \input_op__write_cr0
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 2 \input_op__input_carry
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \input_op__output_carry
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 \input_op__input_cr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 \input_op__output_cr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \input_op__is_32bit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \input_op__is_signed
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 4 \input_op__data_len
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 32 \input_op__insn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 \input_op__byte_reverse
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 \input_op__sign_extend
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
wire width 64 \input_ra
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
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wire width 64 \input_rb
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
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wire width 1 \input_xer_so
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
wire width 2 \input_xer_ca
- attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
- wire width 2 \input_muxid$28
- attribute \enum_base_type "InternalOp"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+ wire width 2 \input_muxid$22
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 7 \input_op__insn_type$29
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 7 \input_op__insn_type$23
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00000000010 "ALU"
attribute \enum_value_00100000000 "MUL"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 11 \input_op__fn_unit$30
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 64 \input_op__imm_data__imm$31
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 \input_op__imm_data__imm_ok$32
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 \input_op__lk$33
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 \input_op__rc__rc$34
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 \input_op__rc__rc_ok$35
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 \input_op__oe__oe$36
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 \input_op__oe__oe_ok$37
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
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- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 \input_op__zero_a$39
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
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- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 3 \input_op__write_cr__data$41
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 \input_op__write_cr__ok$42
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+ wire width 11 \input_op__fn_unit$24
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 \input_op__imm_data__imm$25
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+ wire width 1 \input_op__imm_data__imm_ok$26
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+ wire width 1 \input_op__rc__rc$27
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+ wire width 1 \input_op__rc__rc_ok$28
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+ wire width 1 \input_op__oe__oe$29
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+ wire width 1 \input_op__oe__oe_ok$30
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+ wire width 1 \input_op__invert_a$31
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+ wire width 1 \input_op__zero_a$32
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+ wire width 1 \input_op__invert_out$33
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \input_op__write_cr0$34
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 2 \input_op__input_carry$43
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 \input_op__output_carry$44
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 \input_op__input_cr$45
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 \input_op__output_cr$46
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 \input_op__is_32bit$47
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 \input_op__is_signed$48
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 4 \input_op__data_len$49
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 32 \input_op__insn$50
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 \input_op__byte_reverse$51
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 \input_op__sign_extend$52
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
- wire width 64 \input_ra$53
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
- wire width 64 \input_rb$54
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
- wire width 1 \input_xer_so$55
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
- wire width 2 \input_xer_ca$56
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+ wire width 1 \input_op__output_carry$36
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+ wire width 1 \input_op__is_32bit$37
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+ wire width 1 \input_op__is_signed$38
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+ wire width 4 \input_op__data_len$39
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 \input_op__insn$40
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+ wire width 64 \input_ra$41
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+ wire width 64 \input_rb$42
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+ wire width 1 \input_xer_so$43
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 2 \input_xer_ca$44
cell \input \input
connect \muxid \input_muxid
connect \op__insn_type \input_op__insn_type
connect \op__fn_unit \input_op__fn_unit
connect \op__imm_data__imm \input_op__imm_data__imm
connect \op__imm_data__imm_ok \input_op__imm_data__imm_ok
- connect \op__lk \input_op__lk
connect \op__rc__rc \input_op__rc__rc
connect \op__rc__rc_ok \input_op__rc__rc_ok
connect \op__oe__oe \input_op__oe__oe
connect \op__invert_a \input_op__invert_a
connect \op__zero_a \input_op__zero_a
connect \op__invert_out \input_op__invert_out
- connect \op__write_cr__data \input_op__write_cr__data
- connect \op__write_cr__ok \input_op__write_cr__ok
+ connect \op__write_cr0 \input_op__write_cr0
connect \op__input_carry \input_op__input_carry
connect \op__output_carry \input_op__output_carry
- connect \op__input_cr \input_op__input_cr
- connect \op__output_cr \input_op__output_cr
connect \op__is_32bit \input_op__is_32bit
connect \op__is_signed \input_op__is_signed
connect \op__data_len \input_op__data_len
connect \op__insn \input_op__insn
- connect \op__byte_reverse \input_op__byte_reverse
- connect \op__sign_extend \input_op__sign_extend
connect \ra \input_ra
connect \rb \input_rb
connect \xer_so \input_xer_so
connect \xer_ca \input_xer_ca
- connect \muxid$1 \input_muxid$28
- connect \op__insn_type$2 \input_op__insn_type$29
- connect \op__fn_unit$3 \input_op__fn_unit$30
- connect \op__imm_data__imm$4 \input_op__imm_data__imm$31
- connect \op__imm_data__imm_ok$5 \input_op__imm_data__imm_ok$32
- connect \op__lk$6 \input_op__lk$33
- connect \op__rc__rc$7 \input_op__rc__rc$34
- connect \op__rc__rc_ok$8 \input_op__rc__rc_ok$35
- connect \op__oe__oe$9 \input_op__oe__oe$36
- connect \op__oe__oe_ok$10 \input_op__oe__oe_ok$37
- connect \op__invert_a$11 \input_op__invert_a$38
- connect \op__zero_a$12 \input_op__zero_a$39
- connect \op__invert_out$13 \input_op__invert_out$40
- connect \op__write_cr__data$14 \input_op__write_cr__data$41
- connect \op__write_cr__ok$15 \input_op__write_cr__ok$42
- connect \op__input_carry$16 \input_op__input_carry$43
- connect \op__output_carry$17 \input_op__output_carry$44
- connect \op__input_cr$18 \input_op__input_cr$45
- connect \op__output_cr$19 \input_op__output_cr$46
- connect \op__is_32bit$20 \input_op__is_32bit$47
- connect \op__is_signed$21 \input_op__is_signed$48
- connect \op__data_len$22 \input_op__data_len$49
- connect \op__insn$23 \input_op__insn$50
- connect \op__byte_reverse$24 \input_op__byte_reverse$51
- connect \op__sign_extend$25 \input_op__sign_extend$52
- connect \ra$26 \input_ra$53
- connect \rb$27 \input_rb$54
- connect \xer_so$28 \input_xer_so$55
- connect \xer_ca$29 \input_xer_ca$56
- end
- attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+ connect \muxid$1 \input_muxid$22
+ connect \op__insn_type$2 \input_op__insn_type$23
+ connect \op__fn_unit$3 \input_op__fn_unit$24
+ connect \op__imm_data__imm$4 \input_op__imm_data__imm$25
+ connect \op__imm_data__imm_ok$5 \input_op__imm_data__imm_ok$26
+ connect \op__rc__rc$6 \input_op__rc__rc$27
+ connect \op__rc__rc_ok$7 \input_op__rc__rc_ok$28
+ connect \op__oe__oe$8 \input_op__oe__oe$29
+ connect \op__oe__oe_ok$9 \input_op__oe__oe_ok$30
+ connect \op__invert_a$10 \input_op__invert_a$31
+ connect \op__zero_a$11 \input_op__zero_a$32
+ connect \op__invert_out$12 \input_op__invert_out$33
+ connect \op__write_cr0$13 \input_op__write_cr0$34
+ connect \op__input_carry$14 \input_op__input_carry$35
+ connect \op__output_carry$15 \input_op__output_carry$36
+ connect \op__is_32bit$16 \input_op__is_32bit$37
+ connect \op__is_signed$17 \input_op__is_signed$38
+ connect \op__data_len$18 \input_op__data_len$39
+ connect \op__insn$19 \input_op__insn$40
+ connect \ra$20 \input_ra$41
+ connect \rb$21 \input_rb$42
+ connect \xer_so$22 \input_xer_so$43
+ connect \xer_ca$23 \input_xer_ca$44
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
wire width 2 \main_muxid
- attribute \enum_base_type "InternalOp"
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 7 \main_op__insn_type
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00100000000 "MUL"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 11 \main_op__fn_unit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 64 \main_op__imm_data__imm
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \main_op__imm_data__imm_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 \main_op__lk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \main_op__rc__rc
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \main_op__rc__rc_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \main_op__oe__oe
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \main_op__oe__oe_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \main_op__invert_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \main_op__zero_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \main_op__invert_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 3 \main_op__write_cr__data
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 \main_op__write_cr__ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \main_op__write_cr0
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 2 \main_op__input_carry
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \main_op__output_carry
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 \main_op__input_cr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 \main_op__output_cr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
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wire width 1 \main_op__is_32bit
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wire width 1 \main_op__is_signed
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wire width 4 \main_op__data_len
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wire width 32 \main_op__insn
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- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
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wire width 1 \main_xer_so
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wire width 2 \main_xer_ca
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- attribute \enum_base_type "InternalOp"
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attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
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attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00000000010 "ALU"
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attribute \enum_value_10000000000 "SPR"
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 64 \main_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 \main_cr_a_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 \main_xer_ca_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 \main_xer_ov_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
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cell \main \main
connect \muxid \main_muxid
connect \op__insn_type \main_op__insn_type
connect \op__fn_unit \main_op__fn_unit
connect \op__imm_data__imm \main_op__imm_data__imm
connect \op__imm_data__imm_ok \main_op__imm_data__imm_ok
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connect \op__rc__rc \main_op__rc__rc
connect \op__rc__rc_ok \main_op__rc__rc_ok
connect \op__oe__oe \main_op__oe__oe
connect \op__invert_a \main_op__invert_a
connect \op__zero_a \main_op__zero_a
connect \op__invert_out \main_op__invert_out
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connect \op__input_carry \main_op__input_carry
connect \op__output_carry \main_op__output_carry
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connect \op__is_32bit \main_op__is_32bit
connect \op__is_signed \main_op__is_signed
connect \op__data_len \main_op__data_len
connect \op__insn \main_op__insn
- connect \op__byte_reverse \main_op__byte_reverse
- connect \op__sign_extend \main_op__sign_extend
connect \ra \main_ra
connect \rb \main_rb
connect \xer_so \main_xer_so
connect \xer_ca \main_xer_ca
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- connect \op__byte_reverse$24 \main_op__byte_reverse$80
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+ connect \op__input_carry$14 \main_op__input_carry$58
+ connect \op__output_carry$15 \main_op__output_carry$59
+ connect \op__is_32bit$16 \main_op__is_32bit$60
+ connect \op__is_signed$17 \main_op__is_signed$61
+ connect \op__data_len$18 \main_op__data_len$62
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connect \o \main_o
connect \o_ok \main_o_ok
connect \cr_a \main_cr_a
connect \cr_a_ok \main_cr_a_ok
- connect \xer_ca$26 \main_xer_ca$82
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connect \xer_ca_ok \main_xer_ca_ok
connect \xer_ov \main_xer_ov
connect \xer_ov_ok \main_xer_ov_ok
- connect \xer_so$27 \main_xer_so$83
+ connect \xer_so$21 \main_xer_so$65
end
- attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
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wire width 2 \output_muxid
- attribute \enum_base_type "InternalOp"
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attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
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wire width 7 \output_op__insn_type
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00100000000 "MUL"
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attribute \enum_value_10000000000 "SPR"
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wire width 11 \output_op__fn_unit
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wire width 64 \output_op__imm_data__imm
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wire width 1 \output_op__rc__rc
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wire width 1 \output_op__rc__rc_ok
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wire width 1 \output_op__oe__oe
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wire width 1 \output_op__invert_out
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attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
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wire width 2 \output_op__input_carry
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wire width 1 \output_op__is_32bit
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attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
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attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 7 \output_op__insn_type$85
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 7 \output_op__insn_type$67
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00000000010 "ALU"
attribute \enum_value_00100000000 "MUL"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 11 \output_op__fn_unit$86
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 64 \output_op__imm_data__imm$87
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 \output_op__imm_data__imm_ok$88
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 \output_op__lk$89
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 \output_op__rc__rc$90
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 \output_op__rc__rc_ok$91
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 \output_op__oe__oe$92
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 \output_op__oe__oe_ok$93
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 \output_op__invert_a$94
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 \output_op__zero_a$95
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 \output_op__invert_out$96
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 3 \output_op__write_cr__data$97
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 \output_op__write_cr__ok$98
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 11 \output_op__fn_unit$68
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 \output_op__imm_data__imm$69
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \output_op__imm_data__imm_ok$70
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \output_op__rc__rc$71
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \output_op__rc__rc_ok$72
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \output_op__oe__oe$73
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \output_op__oe__oe_ok$74
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \output_op__invert_a$75
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \output_op__zero_a$76
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \output_op__invert_out$77
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \output_op__write_cr0$78
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 2 \output_op__input_carry$99
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 \output_op__output_carry$100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 \output_op__input_cr$101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 \output_op__output_cr$102
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 \output_op__is_32bit$103
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 \output_op__is_signed$104
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 4 \output_op__data_len$105
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 32 \output_op__insn$106
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 \output_op__byte_reverse$107
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 \output_op__sign_extend$108
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 \output_o$109
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 \output_o_ok$110
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 4 \output_cr_a$111
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 2 \output_op__input_carry$79
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \output_op__output_carry$80
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \output_op__is_32bit$81
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \output_op__is_signed$82
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 4 \output_op__data_len$83
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 \output_op__insn$84
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 64 \output_o$85
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 \output_o_ok$86
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 4 \output_cr_a$87
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 \output_cr_a_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 2 \output_xer_ca$112
+ wire width 2 \output_xer_ca$88
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 \output_xer_ca_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 2 \output_xer_ov$113
+ wire width 2 \output_xer_ov$89
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 \output_xer_ov_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 \output_xer_so$114
+ wire width 1 \output_xer_so$90
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 \output_xer_so_ok
cell \output \output
connect \op__fn_unit \output_op__fn_unit
connect \op__imm_data__imm \output_op__imm_data__imm
connect \op__imm_data__imm_ok \output_op__imm_data__imm_ok
- connect \op__lk \output_op__lk
connect \op__rc__rc \output_op__rc__rc
connect \op__rc__rc_ok \output_op__rc__rc_ok
connect \op__oe__oe \output_op__oe__oe
connect \op__invert_a \output_op__invert_a
connect \op__zero_a \output_op__zero_a
connect \op__invert_out \output_op__invert_out
- connect \op__write_cr__data \output_op__write_cr__data
- connect \op__write_cr__ok \output_op__write_cr__ok
+ connect \op__write_cr0 \output_op__write_cr0
connect \op__input_carry \output_op__input_carry
connect \op__output_carry \output_op__output_carry
- connect \op__input_cr \output_op__input_cr
- connect \op__output_cr \output_op__output_cr
connect \op__is_32bit \output_op__is_32bit
connect \op__is_signed \output_op__is_signed
connect \op__data_len \output_op__data_len
connect \op__insn \output_op__insn
- connect \op__byte_reverse \output_op__byte_reverse
- connect \op__sign_extend \output_op__sign_extend
connect \o \output_o
connect \o_ok \output_o_ok
connect \cr_a \output_cr_a
connect \xer_ca \output_xer_ca
connect \xer_ov \output_xer_ov
connect \xer_so \output_xer_so
- connect \muxid$1 \output_muxid$84
- connect \op__insn_type$2 \output_op__insn_type$85
- connect \op__fn_unit$3 \output_op__fn_unit$86
- connect \op__imm_data__imm$4 \output_op__imm_data__imm$87
- connect \op__imm_data__imm_ok$5 \output_op__imm_data__imm_ok$88
- connect \op__lk$6 \output_op__lk$89
- connect \op__rc__rc$7 \output_op__rc__rc$90
- connect \op__rc__rc_ok$8 \output_op__rc__rc_ok$91
- connect \op__oe__oe$9 \output_op__oe__oe$92
- connect \op__oe__oe_ok$10 \output_op__oe__oe_ok$93
- connect \op__invert_a$11 \output_op__invert_a$94
- connect \op__zero_a$12 \output_op__zero_a$95
- connect \op__invert_out$13 \output_op__invert_out$96
- connect \op__write_cr__data$14 \output_op__write_cr__data$97
- connect \op__write_cr__ok$15 \output_op__write_cr__ok$98
- connect \op__input_carry$16 \output_op__input_carry$99
- connect \op__output_carry$17 \output_op__output_carry$100
- connect \op__input_cr$18 \output_op__input_cr$101
- connect \op__output_cr$19 \output_op__output_cr$102
- connect \op__is_32bit$20 \output_op__is_32bit$103
- connect \op__is_signed$21 \output_op__is_signed$104
- connect \op__data_len$22 \output_op__data_len$105
- connect \op__insn$23 \output_op__insn$106
- connect \op__byte_reverse$24 \output_op__byte_reverse$107
- connect \op__sign_extend$25 \output_op__sign_extend$108
- connect \o$26 \output_o$109
- connect \o_ok$27 \output_o_ok$110
- connect \cr_a$28 \output_cr_a$111
+ connect \muxid$1 \output_muxid$66
+ connect \op__insn_type$2 \output_op__insn_type$67
+ connect \op__fn_unit$3 \output_op__fn_unit$68
+ connect \op__imm_data__imm$4 \output_op__imm_data__imm$69
+ connect \op__imm_data__imm_ok$5 \output_op__imm_data__imm_ok$70
+ connect \op__rc__rc$6 \output_op__rc__rc$71
+ connect \op__rc__rc_ok$7 \output_op__rc__rc_ok$72
+ connect \op__oe__oe$8 \output_op__oe__oe$73
+ connect \op__oe__oe_ok$9 \output_op__oe__oe_ok$74
+ connect \op__invert_a$10 \output_op__invert_a$75
+ connect \op__zero_a$11 \output_op__zero_a$76
+ connect \op__invert_out$12 \output_op__invert_out$77
+ connect \op__write_cr0$13 \output_op__write_cr0$78
+ connect \op__input_carry$14 \output_op__input_carry$79
+ connect \op__output_carry$15 \output_op__output_carry$80
+ connect \op__is_32bit$16 \output_op__is_32bit$81
+ connect \op__is_signed$17 \output_op__is_signed$82
+ connect \op__data_len$18 \output_op__data_len$83
+ connect \op__insn$19 \output_op__insn$84
+ connect \o$20 \output_o$85
+ connect \o_ok$21 \output_o_ok$86
+ connect \cr_a$22 \output_cr_a$87
connect \cr_a_ok \output_cr_a_ok
- connect \xer_ca$29 \output_xer_ca$112
+ connect \xer_ca$23 \output_xer_ca$88
connect \xer_ca_ok \output_xer_ca_ok
- connect \xer_ov$30 \output_xer_ov$113
+ connect \xer_ov$24 \output_xer_ov$89
connect \xer_ov_ok \output_xer_ov_ok
- connect \xer_so$31 \output_xer_so$114
+ connect \xer_so$25 \output_xer_so$90
connect \xer_so_ok \output_xer_so_ok
end
process $group_0
assign \input_op__fn_unit 11'00000000000
assign \input_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
assign \input_op__imm_data__imm_ok 1'0
- assign \input_op__lk 1'0
assign \input_op__rc__rc 1'0
assign \input_op__rc__rc_ok 1'0
assign \input_op__oe__oe 1'0
assign \input_op__invert_a 1'0
assign \input_op__zero_a 1'0
assign \input_op__invert_out 1'0
- assign \input_op__write_cr__data 3'000
- assign \input_op__write_cr__ok 1'0
+ assign \input_op__write_cr0 1'0
assign \input_op__input_carry 2'00
assign \input_op__output_carry 1'0
- assign \input_op__input_cr 1'0
- assign \input_op__output_cr 1'0
assign \input_op__is_32bit 1'0
assign \input_op__is_signed 1'0
assign \input_op__data_len 4'0000
assign \input_op__insn 32'00000000000000000000000000000000
- assign \input_op__byte_reverse 1'0
- assign \input_op__sign_extend 1'0
- assign { \input_op__sign_extend \input_op__byte_reverse \input_op__insn \input_op__data_len \input_op__is_signed \input_op__is_32bit \input_op__output_cr \input_op__input_cr \input_op__output_carry \input_op__input_carry { \input_op__write_cr__ok \input_op__write_cr__data } \input_op__invert_out \input_op__zero_a \input_op__invert_a { \input_op__oe__oe_ok \input_op__oe__oe } { \input_op__rc__rc_ok \input_op__rc__rc } \input_op__lk { \input_op__imm_data__imm_ok \input_op__imm_data__imm } \input_op__fn_unit \input_op__insn_type } { \op__sign_extend \op__byte_reverse \op__insn \op__data_len \op__is_signed \op__is_32bit \op__output_cr \op__input_cr \op__output_carry \op__input_carry { \op__write_cr__ok \op__write_cr__data } \op__invert_out \op__zero_a \op__invert_a { \op__oe__oe_ok \op__oe__oe } { \op__rc__rc_ok \op__rc__rc } \op__lk { \op__imm_data__imm_ok \op__imm_data__imm } \op__fn_unit \op__insn_type }
+ assign { \input_op__insn \input_op__data_len \input_op__is_signed \input_op__is_32bit \input_op__output_carry \input_op__input_carry \input_op__write_cr0 \input_op__invert_out \input_op__zero_a \input_op__invert_a { \input_op__oe__oe_ok \input_op__oe__oe } { \input_op__rc__rc_ok \input_op__rc__rc } { \input_op__imm_data__imm_ok \input_op__imm_data__imm } \input_op__fn_unit \input_op__insn_type } { \op__insn \op__data_len \op__is_signed \op__is_32bit \op__output_carry \op__input_carry \op__write_cr0 \op__invert_out \op__zero_a \op__invert_a { \op__oe__oe_ok \op__oe__oe } { \op__rc__rc_ok \op__rc__rc } { \op__imm_data__imm_ok \op__imm_data__imm } \op__fn_unit \op__insn_type }
sync init
end
- process $group_25
+ process $group_19
assign \input_ra 64'0000000000000000000000000000000000000000000000000000000000000000
assign \input_ra \ra
sync init
end
- process $group_26
+ process $group_20
assign \input_rb 64'0000000000000000000000000000000000000000000000000000000000000000
assign \input_rb \rb
sync init
end
- process $group_27
+ process $group_21
assign \input_xer_so 1'0
assign \input_xer_so \xer_so
sync init
end
- process $group_28
+ process $group_22
assign \input_xer_ca 2'00
assign \input_xer_ca \xer_ca
sync init
end
- process $group_29
+ process $group_23
assign \main_muxid 2'00
- assign \main_muxid \input_muxid$28
+ assign \main_muxid \input_muxid$22
sync init
end
- process $group_30
+ process $group_24
assign \main_op__insn_type 7'0000000
assign \main_op__fn_unit 11'00000000000
assign \main_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
assign \main_op__imm_data__imm_ok 1'0
- assign \main_op__lk 1'0
assign \main_op__rc__rc 1'0
assign \main_op__rc__rc_ok 1'0
assign \main_op__oe__oe 1'0
assign \main_op__invert_a 1'0
assign \main_op__zero_a 1'0
assign \main_op__invert_out 1'0
- assign \main_op__write_cr__data 3'000
- assign \main_op__write_cr__ok 1'0
+ assign \main_op__write_cr0 1'0
assign \main_op__input_carry 2'00
assign \main_op__output_carry 1'0
- assign \main_op__input_cr 1'0
- assign \main_op__output_cr 1'0
assign \main_op__is_32bit 1'0
assign \main_op__is_signed 1'0
assign \main_op__data_len 4'0000
assign \main_op__insn 32'00000000000000000000000000000000
- assign \main_op__byte_reverse 1'0
- assign \main_op__sign_extend 1'0
- assign { \main_op__sign_extend \main_op__byte_reverse \main_op__insn \main_op__data_len \main_op__is_signed \main_op__is_32bit \main_op__output_cr \main_op__input_cr \main_op__output_carry \main_op__input_carry { \main_op__write_cr__ok \main_op__write_cr__data } \main_op__invert_out \main_op__zero_a \main_op__invert_a { \main_op__oe__oe_ok \main_op__oe__oe } { \main_op__rc__rc_ok \main_op__rc__rc } \main_op__lk { \main_op__imm_data__imm_ok \main_op__imm_data__imm } \main_op__fn_unit \main_op__insn_type } { \input_op__sign_extend$52 \input_op__byte_reverse$51 \input_op__insn$50 \input_op__data_len$49 \input_op__is_signed$48 \input_op__is_32bit$47 \input_op__output_cr$46 \input_op__input_cr$45 \input_op__output_carry$44 \input_op__input_carry$43 { \input_op__write_cr__ok$42 \input_op__write_cr__data$41 } \input_op__invert_out$40 \input_op__zero_a$39 \input_op__invert_a$38 { \input_op__oe__oe_ok$37 \input_op__oe__oe$36 } { \input_op__rc__rc_ok$35 \input_op__rc__rc$34 } \input_op__lk$33 { \input_op__imm_data__imm_ok$32 \input_op__imm_data__imm$31 } \input_op__fn_unit$30 \input_op__insn_type$29 }
+ assign { \main_op__insn \main_op__data_len \main_op__is_signed \main_op__is_32bit \main_op__output_carry \main_op__input_carry \main_op__write_cr0 \main_op__invert_out \main_op__zero_a \main_op__invert_a { \main_op__oe__oe_ok \main_op__oe__oe } { \main_op__rc__rc_ok \main_op__rc__rc } { \main_op__imm_data__imm_ok \main_op__imm_data__imm } \main_op__fn_unit \main_op__insn_type } { \input_op__insn$40 \input_op__data_len$39 \input_op__is_signed$38 \input_op__is_32bit$37 \input_op__output_carry$36 \input_op__input_carry$35 \input_op__write_cr0$34 \input_op__invert_out$33 \input_op__zero_a$32 \input_op__invert_a$31 { \input_op__oe__oe_ok$30 \input_op__oe__oe$29 } { \input_op__rc__rc_ok$28 \input_op__rc__rc$27 } { \input_op__imm_data__imm_ok$26 \input_op__imm_data__imm$25 } \input_op__fn_unit$24 \input_op__insn_type$23 }
sync init
end
- process $group_54
+ process $group_42
assign \main_ra 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \main_ra \input_ra$53
+ assign \main_ra \input_ra$41
sync init
end
- process $group_55
+ process $group_43
assign \main_rb 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \main_rb \input_rb$54
+ assign \main_rb \input_rb$42
sync init
end
- process $group_56
+ process $group_44
assign \main_xer_so 1'0
- assign \main_xer_so \input_xer_so$55
+ assign \main_xer_so \input_xer_so$43
sync init
end
- process $group_57
+ process $group_45
assign \main_xer_ca 2'00
- assign \main_xer_ca \input_xer_ca$56
+ assign \main_xer_ca \input_xer_ca$44
sync init
end
- process $group_58
+ process $group_46
assign \output_muxid 2'00
- assign \output_muxid \main_muxid$57
+ assign \output_muxid \main_muxid$45
sync init
end
- process $group_59
+ process $group_47
assign \output_op__insn_type 7'0000000
assign \output_op__fn_unit 11'00000000000
assign \output_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
assign \output_op__imm_data__imm_ok 1'0
- assign \output_op__lk 1'0
assign \output_op__rc__rc 1'0
assign \output_op__rc__rc_ok 1'0
assign \output_op__oe__oe 1'0
assign \output_op__invert_a 1'0
assign \output_op__zero_a 1'0
assign \output_op__invert_out 1'0
- assign \output_op__write_cr__data 3'000
- assign \output_op__write_cr__ok 1'0
+ assign \output_op__write_cr0 1'0
assign \output_op__input_carry 2'00
assign \output_op__output_carry 1'0
- assign \output_op__input_cr 1'0
- assign \output_op__output_cr 1'0
assign \output_op__is_32bit 1'0
assign \output_op__is_signed 1'0
assign \output_op__data_len 4'0000
assign \output_op__insn 32'00000000000000000000000000000000
- assign \output_op__byte_reverse 1'0
- assign \output_op__sign_extend 1'0
- assign { \output_op__sign_extend \output_op__byte_reverse \output_op__insn \output_op__data_len \output_op__is_signed \output_op__is_32bit \output_op__output_cr \output_op__input_cr \output_op__output_carry \output_op__input_carry { \output_op__write_cr__ok \output_op__write_cr__data } \output_op__invert_out \output_op__zero_a \output_op__invert_a { \output_op__oe__oe_ok \output_op__oe__oe } { \output_op__rc__rc_ok \output_op__rc__rc } \output_op__lk { \output_op__imm_data__imm_ok \output_op__imm_data__imm } \output_op__fn_unit \output_op__insn_type } { \main_op__sign_extend$81 \main_op__byte_reverse$80 \main_op__insn$79 \main_op__data_len$78 \main_op__is_signed$77 \main_op__is_32bit$76 \main_op__output_cr$75 \main_op__input_cr$74 \main_op__output_carry$73 \main_op__input_carry$72 { \main_op__write_cr__ok$71 \main_op__write_cr__data$70 } \main_op__invert_out$69 \main_op__zero_a$68 \main_op__invert_a$67 { \main_op__oe__oe_ok$66 \main_op__oe__oe$65 } { \main_op__rc__rc_ok$64 \main_op__rc__rc$63 } \main_op__lk$62 { \main_op__imm_data__imm_ok$61 \main_op__imm_data__imm$60 } \main_op__fn_unit$59 \main_op__insn_type$58 }
+ assign { \output_op__insn \output_op__data_len \output_op__is_signed \output_op__is_32bit \output_op__output_carry \output_op__input_carry \output_op__write_cr0 \output_op__invert_out \output_op__zero_a \output_op__invert_a { \output_op__oe__oe_ok \output_op__oe__oe } { \output_op__rc__rc_ok \output_op__rc__rc } { \output_op__imm_data__imm_ok \output_op__imm_data__imm } \output_op__fn_unit \output_op__insn_type } { \main_op__insn$63 \main_op__data_len$62 \main_op__is_signed$61 \main_op__is_32bit$60 \main_op__output_carry$59 \main_op__input_carry$58 \main_op__write_cr0$57 \main_op__invert_out$56 \main_op__zero_a$55 \main_op__invert_a$54 { \main_op__oe__oe_ok$53 \main_op__oe__oe$52 } { \main_op__rc__rc_ok$51 \main_op__rc__rc$50 } { \main_op__imm_data__imm_ok$49 \main_op__imm_data__imm$48 } \main_op__fn_unit$47 \main_op__insn_type$46 }
sync init
end
- process $group_83
+ process $group_65
assign \output_o 64'0000000000000000000000000000000000000000000000000000000000000000
assign \output_o_ok 1'0
assign { \output_o_ok \output_o } { \main_o_ok \main_o }
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 \cr_a_ok$115
- process $group_85
+ wire width 1 \cr_a_ok$91
+ process $group_67
assign \output_cr_a 4'0000
- assign \cr_a_ok$115 1'0
- assign { \cr_a_ok$115 \output_cr_a } { \main_cr_a_ok \main_cr_a }
+ assign \cr_a_ok$91 1'0
+ assign { \cr_a_ok$91 \output_cr_a } { \main_cr_a_ok \main_cr_a }
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 \xer_ca_ok$116
- process $group_87
+ wire width 1 \xer_ca_ok$92
+ process $group_69
assign \output_xer_ca 2'00
- assign \xer_ca_ok$116 1'0
- assign { \xer_ca_ok$116 \output_xer_ca } { \main_xer_ca_ok \main_xer_ca$82 }
+ assign \xer_ca_ok$92 1'0
+ assign { \xer_ca_ok$92 \output_xer_ca } { \main_xer_ca_ok \main_xer_ca$64 }
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 \xer_ov_ok$117
- process $group_89
+ wire width 1 \xer_ov_ok$93
+ process $group_71
assign \output_xer_ov 2'00
- assign \xer_ov_ok$117 1'0
- assign { \xer_ov_ok$117 \output_xer_ov } { \main_xer_ov_ok \main_xer_ov }
+ assign \xer_ov_ok$93 1'0
+ assign { \xer_ov_ok$93 \output_xer_ov } { \main_xer_ov_ok \main_xer_ov }
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 \xer_so_ok$118
+ wire width 1 \xer_so_ok$94
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 \xer_so_ok$119
- process $group_91
+ wire width 1 \xer_so_ok$95
+ process $group_73
assign \output_xer_so 1'0
- assign \xer_so_ok$118 1'0
- assign { \xer_so_ok$118 \output_xer_so } { \xer_so_ok$119 \main_xer_so$83 }
+ assign \xer_so_ok$94 1'0
+ assign { \xer_so_ok$94 \output_xer_so } { \xer_so_ok$95 \main_xer_so$65 }
sync init
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621"
- wire width 1 \p_valid_i$120
- process $group_93
- assign \p_valid_i$120 1'0
- assign \p_valid_i$120 \p_valid_i
+ wire width 1 \p_valid_i$96
+ process $group_75
+ assign \p_valid_i$96 1'0
+ assign \p_valid_i$96 \p_valid_i
sync init
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619"
wire width 1 \n_i_rdy_data
- process $group_94
+ process $group_76
assign \n_i_rdy_data 1'0
assign \n_i_rdy_data \n_ready_i
sync init
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620"
wire width 1 \p_valid_i_p_ready_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624"
- wire width 1 $121
+ wire width 1 $97
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624"
- cell $and $122
+ cell $and $98
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \p_valid_i$120
+ connect \A \p_valid_i$96
connect \B \p_ready_o
- connect \Y $121
+ connect \Y $97
end
- process $group_95
+ process $group_77
assign \p_valid_i_p_ready_o 1'0
- assign \p_valid_i_p_ready_o $121
+ assign \p_valid_i_p_ready_o $97
sync init
end
- attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
- wire width 2 \muxid$123
- process $group_96
- assign \muxid$123 2'00
- assign \muxid$123 \output_muxid$84
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+ wire width 2 \muxid$99
+ process $group_78
+ assign \muxid$99 2'00
+ assign \muxid$99 \output_muxid$66
sync init
end
- attribute \enum_base_type "InternalOp"
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 7 \op__insn_type$124
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 7 \op__insn_type$100
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00000000010 "ALU"
attribute \enum_value_00100000000 "MUL"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 11 \op__fn_unit$125
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 64 \op__imm_data__imm$126
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 \op__imm_data__imm_ok$127
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 \op__lk$128
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 \op__rc__rc$129
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 \op__rc__rc_ok$130
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 \op__oe__oe$131
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 \op__oe__oe_ok$132
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 \op__invert_a$133
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 \op__zero_a$134
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 \op__invert_out$135
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 3 \op__write_cr__data$136
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 \op__write_cr__ok$137
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 11 \op__fn_unit$101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 \op__imm_data__imm$102
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__imm_data__imm_ok$103
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__rc__rc$104
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__rc__rc_ok$105
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__oe__oe$106
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__oe__oe_ok$107
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__invert_a$108
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__zero_a$109
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__invert_out$110
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__write_cr0$111
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 2 \op__input_carry$138
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 \op__output_carry$139
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 \op__input_cr$140
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 \op__output_cr$141
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 \op__is_32bit$142
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 \op__is_signed$143
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 4 \op__data_len$144
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 32 \op__insn$145
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 \op__byte_reverse$146
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 \op__sign_extend$147
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 2 \op__input_carry$112
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__output_carry$113
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__is_32bit$114
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__is_signed$115
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 4 \op__data_len$116
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 \op__insn$117
+ process $group_79
+ assign \op__insn_type$100 7'0000000
+ assign \op__fn_unit$101 11'00000000000
+ assign \op__imm_data__imm$102 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \op__imm_data__imm_ok$103 1'0
+ assign \op__rc__rc$104 1'0
+ assign \op__rc__rc_ok$105 1'0
+ assign \op__oe__oe$106 1'0
+ assign \op__oe__oe_ok$107 1'0
+ assign \op__invert_a$108 1'0
+ assign \op__zero_a$109 1'0
+ assign \op__invert_out$110 1'0
+ assign \op__write_cr0$111 1'0
+ assign \op__input_carry$112 2'00
+ assign \op__output_carry$113 1'0
+ assign \op__is_32bit$114 1'0
+ assign \op__is_signed$115 1'0
+ assign \op__data_len$116 4'0000
+ assign \op__insn$117 32'00000000000000000000000000000000
+ assign { \op__insn$117 \op__data_len$116 \op__is_signed$115 \op__is_32bit$114 \op__output_carry$113 \op__input_carry$112 \op__write_cr0$111 \op__invert_out$110 \op__zero_a$109 \op__invert_a$108 { \op__oe__oe_ok$107 \op__oe__oe$106 } { \op__rc__rc_ok$105 \op__rc__rc$104 } { \op__imm_data__imm_ok$103 \op__imm_data__imm$102 } \op__fn_unit$101 \op__insn_type$100 } { \output_op__insn$84 \output_op__data_len$83 \output_op__is_signed$82 \output_op__is_32bit$81 \output_op__output_carry$80 \output_op__input_carry$79 \output_op__write_cr0$78 \output_op__invert_out$77 \output_op__zero_a$76 \output_op__invert_a$75 { \output_op__oe__oe_ok$74 \output_op__oe__oe$73 } { \output_op__rc__rc_ok$72 \output_op__rc__rc$71 } { \output_op__imm_data__imm_ok$70 \output_op__imm_data__imm$69 } \output_op__fn_unit$68 \output_op__insn_type$67 }
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 64 \o$118
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 \o_ok$119
process $group_97
- assign \op__insn_type$124 7'0000000
- assign \op__fn_unit$125 11'00000000000
- assign \op__imm_data__imm$126 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \op__imm_data__imm_ok$127 1'0
- assign \op__lk$128 1'0
- assign \op__rc__rc$129 1'0
- assign \op__rc__rc_ok$130 1'0
- assign \op__oe__oe$131 1'0
- assign \op__oe__oe_ok$132 1'0
- assign \op__invert_a$133 1'0
- assign \op__zero_a$134 1'0
- assign \op__invert_out$135 1'0
- assign \op__write_cr__data$136 3'000
- assign \op__write_cr__ok$137 1'0
- assign \op__input_carry$138 2'00
- assign \op__output_carry$139 1'0
- assign \op__input_cr$140 1'0
- assign \op__output_cr$141 1'0
- assign \op__is_32bit$142 1'0
- assign \op__is_signed$143 1'0
- assign \op__data_len$144 4'0000
- assign \op__insn$145 32'00000000000000000000000000000000
- assign \op__byte_reverse$146 1'0
- assign \op__sign_extend$147 1'0
- assign { \op__sign_extend$147 \op__byte_reverse$146 \op__insn$145 \op__data_len$144 \op__is_signed$143 \op__is_32bit$142 \op__output_cr$141 \op__input_cr$140 \op__output_carry$139 \op__input_carry$138 { \op__write_cr__ok$137 \op__write_cr__data$136 } \op__invert_out$135 \op__zero_a$134 \op__invert_a$133 { \op__oe__oe_ok$132 \op__oe__oe$131 } { \op__rc__rc_ok$130 \op__rc__rc$129 } \op__lk$128 { \op__imm_data__imm_ok$127 \op__imm_data__imm$126 } \op__fn_unit$125 \op__insn_type$124 } { \output_op__sign_extend$108 \output_op__byte_reverse$107 \output_op__insn$106 \output_op__data_len$105 \output_op__is_signed$104 \output_op__is_32bit$103 \output_op__output_cr$102 \output_op__input_cr$101 \output_op__output_carry$100 \output_op__input_carry$99 { \output_op__write_cr__ok$98 \output_op__write_cr__data$97 } \output_op__invert_out$96 \output_op__zero_a$95 \output_op__invert_a$94 { \output_op__oe__oe_ok$93 \output_op__oe__oe$92 } { \output_op__rc__rc_ok$91 \output_op__rc__rc$90 } \output_op__lk$89 { \output_op__imm_data__imm_ok$88 \output_op__imm_data__imm$87 } \output_op__fn_unit$86 \output_op__insn_type$85 }
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 \o$148
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 \o_ok$149
- process $group_121
- assign \o$148 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \o_ok$149 1'0
- assign { \o_ok$149 \o$148 } { \output_o_ok$110 \output_o$109 }
+ assign \o$118 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \o_ok$119 1'0
+ assign { \o_ok$119 \o$118 } { \output_o_ok$86 \output_o$85 }
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 4 \cr_a$150
+ wire width 4 \cr_a$120
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 \cr_a_ok$151
- process $group_123
- assign \cr_a$150 4'0000
- assign \cr_a_ok$151 1'0
- assign { \cr_a_ok$151 \cr_a$150 } { \output_cr_a_ok \output_cr_a$111 }
+ wire width 1 \cr_a_ok$121
+ process $group_99
+ assign \cr_a$120 4'0000
+ assign \cr_a_ok$121 1'0
+ assign { \cr_a_ok$121 \cr_a$120 } { \output_cr_a_ok \output_cr_a$87 }
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 2 \xer_ca$152
+ wire width 2 \xer_ca$122
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 \xer_ca_ok$153
- process $group_125
- assign \xer_ca$152 2'00
- assign \xer_ca_ok$153 1'0
- assign { \xer_ca_ok$153 \xer_ca$152 } { \output_xer_ca_ok \output_xer_ca$112 }
+ wire width 1 \xer_ca_ok$123
+ process $group_101
+ assign \xer_ca$122 2'00
+ assign \xer_ca_ok$123 1'0
+ assign { \xer_ca_ok$123 \xer_ca$122 } { \output_xer_ca_ok \output_xer_ca$88 }
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 2 \xer_ov$154
+ wire width 2 \xer_ov$124
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 \xer_ov_ok$155
- process $group_127
- assign \xer_ov$154 2'00
- assign \xer_ov_ok$155 1'0
- assign { \xer_ov_ok$155 \xer_ov$154 } { \output_xer_ov_ok \output_xer_ov$113 }
+ wire width 1 \xer_ov_ok$125
+ process $group_103
+ assign \xer_ov$124 2'00
+ assign \xer_ov_ok$125 1'0
+ assign { \xer_ov_ok$125 \xer_ov$124 } { \output_xer_ov_ok \output_xer_ov$89 }
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 \xer_so$156
+ wire width 1 \xer_so$126
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 \xer_so_ok$157
- process $group_129
- assign \xer_so$156 1'0
- assign \xer_so_ok$157 1'0
- assign { \xer_so_ok$157 \xer_so$156 } { \output_xer_so_ok \output_xer_so$114 }
+ wire width 1 \xer_so_ok$127
+ process $group_105
+ assign \xer_so$126 1'0
+ assign \xer_so_ok$127 1'0
+ assign { \xer_so_ok$127 \xer_so$126 } { \output_xer_so_ok \output_xer_so$90 }
sync init
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615"
wire width 1 \r_busy
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615"
wire width 1 \r_busy$next
- process $group_131
+ process $group_107
assign \r_busy$next \r_busy
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
switch { \n_i_rdy_data \p_valid_i_p_ready_o }
sync posedge \clk
update \r_busy \r_busy$next
end
- process $group_132
+ process $group_108
assign \muxid$1$next \muxid$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
switch { \n_i_rdy_data \p_valid_i_p_ready_o }
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
case 2'-1
- assign \muxid$1$next \muxid$123
+ assign \muxid$1$next \muxid$99
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
case 2'1-
- assign \muxid$1$next \muxid$123
+ assign \muxid$1$next \muxid$99
end
sync init
update \muxid$1 2'00
sync posedge \clk
update \muxid$1 \muxid$1$next
end
- process $group_133
+ process $group_109
assign \op__insn_type$2$next \op__insn_type$2
assign \op__fn_unit$3$next \op__fn_unit$3
assign \op__imm_data__imm$4$next \op__imm_data__imm$4
assign \op__imm_data__imm_ok$5$next \op__imm_data__imm_ok$5
- assign \op__lk$6$next \op__lk$6
- assign \op__rc__rc$7$next \op__rc__rc$7
- assign \op__rc__rc_ok$8$next \op__rc__rc_ok$8
- assign \op__oe__oe$9$next \op__oe__oe$9
- assign \op__oe__oe_ok$10$next \op__oe__oe_ok$10
- assign \op__invert_a$11$next \op__invert_a$11
- assign \op__zero_a$12$next \op__zero_a$12
- assign \op__invert_out$13$next \op__invert_out$13
- assign \op__write_cr__data$14$next \op__write_cr__data$14
- assign \op__write_cr__ok$15$next \op__write_cr__ok$15
- assign \op__input_carry$16$next \op__input_carry$16
- assign \op__output_carry$17$next \op__output_carry$17
- assign \op__input_cr$18$next \op__input_cr$18
- assign \op__output_cr$19$next \op__output_cr$19
- assign \op__is_32bit$20$next \op__is_32bit$20
- assign \op__is_signed$21$next \op__is_signed$21
- assign \op__data_len$22$next \op__data_len$22
- assign \op__insn$23$next \op__insn$23
- assign \op__byte_reverse$24$next \op__byte_reverse$24
- assign \op__sign_extend$25$next \op__sign_extend$25
+ assign \op__rc__rc$6$next \op__rc__rc$6
+ assign \op__rc__rc_ok$7$next \op__rc__rc_ok$7
+ assign \op__oe__oe$8$next \op__oe__oe$8
+ assign \op__oe__oe_ok$9$next \op__oe__oe_ok$9
+ assign \op__invert_a$10$next \op__invert_a$10
+ assign \op__zero_a$11$next \op__zero_a$11
+ assign \op__invert_out$12$next \op__invert_out$12
+ assign \op__write_cr0$13$next \op__write_cr0$13
+ assign \op__input_carry$14$next \op__input_carry$14
+ assign \op__output_carry$15$next \op__output_carry$15
+ assign \op__is_32bit$16$next \op__is_32bit$16
+ assign \op__is_signed$17$next \op__is_signed$17
+ assign \op__data_len$18$next \op__data_len$18
+ assign \op__insn$19$next \op__insn$19
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
switch { \n_i_rdy_data \p_valid_i_p_ready_o }
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
case 2'-1
- assign { \op__sign_extend$25$next \op__byte_reverse$24$next \op__insn$23$next \op__data_len$22$next \op__is_signed$21$next \op__is_32bit$20$next \op__output_cr$19$next \op__input_cr$18$next \op__output_carry$17$next \op__input_carry$16$next { \op__write_cr__ok$15$next \op__write_cr__data$14$next } \op__invert_out$13$next \op__zero_a$12$next \op__invert_a$11$next { \op__oe__oe_ok$10$next \op__oe__oe$9$next } { \op__rc__rc_ok$8$next \op__rc__rc$7$next } \op__lk$6$next { \op__imm_data__imm_ok$5$next \op__imm_data__imm$4$next } \op__fn_unit$3$next \op__insn_type$2$next } { \op__sign_extend$147 \op__byte_reverse$146 \op__insn$145 \op__data_len$144 \op__is_signed$143 \op__is_32bit$142 \op__output_cr$141 \op__input_cr$140 \op__output_carry$139 \op__input_carry$138 { \op__write_cr__ok$137 \op__write_cr__data$136 } \op__invert_out$135 \op__zero_a$134 \op__invert_a$133 { \op__oe__oe_ok$132 \op__oe__oe$131 } { \op__rc__rc_ok$130 \op__rc__rc$129 } \op__lk$128 { \op__imm_data__imm_ok$127 \op__imm_data__imm$126 } \op__fn_unit$125 \op__insn_type$124 }
+ assign { \op__insn$19$next \op__data_len$18$next \op__is_signed$17$next \op__is_32bit$16$next \op__output_carry$15$next \op__input_carry$14$next \op__write_cr0$13$next \op__invert_out$12$next \op__zero_a$11$next \op__invert_a$10$next { \op__oe__oe_ok$9$next \op__oe__oe$8$next } { \op__rc__rc_ok$7$next \op__rc__rc$6$next } { \op__imm_data__imm_ok$5$next \op__imm_data__imm$4$next } \op__fn_unit$3$next \op__insn_type$2$next } { \op__insn$117 \op__data_len$116 \op__is_signed$115 \op__is_32bit$114 \op__output_carry$113 \op__input_carry$112 \op__write_cr0$111 \op__invert_out$110 \op__zero_a$109 \op__invert_a$108 { \op__oe__oe_ok$107 \op__oe__oe$106 } { \op__rc__rc_ok$105 \op__rc__rc$104 } { \op__imm_data__imm_ok$103 \op__imm_data__imm$102 } \op__fn_unit$101 \op__insn_type$100 }
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
case 2'1-
- assign { \op__sign_extend$25$next \op__byte_reverse$24$next \op__insn$23$next \op__data_len$22$next \op__is_signed$21$next \op__is_32bit$20$next \op__output_cr$19$next \op__input_cr$18$next \op__output_carry$17$next \op__input_carry$16$next { \op__write_cr__ok$15$next \op__write_cr__data$14$next } \op__invert_out$13$next \op__zero_a$12$next \op__invert_a$11$next { \op__oe__oe_ok$10$next \op__oe__oe$9$next } { \op__rc__rc_ok$8$next \op__rc__rc$7$next } \op__lk$6$next { \op__imm_data__imm_ok$5$next \op__imm_data__imm$4$next } \op__fn_unit$3$next \op__insn_type$2$next } { \op__sign_extend$147 \op__byte_reverse$146 \op__insn$145 \op__data_len$144 \op__is_signed$143 \op__is_32bit$142 \op__output_cr$141 \op__input_cr$140 \op__output_carry$139 \op__input_carry$138 { \op__write_cr__ok$137 \op__write_cr__data$136 } \op__invert_out$135 \op__zero_a$134 \op__invert_a$133 { \op__oe__oe_ok$132 \op__oe__oe$131 } { \op__rc__rc_ok$130 \op__rc__rc$129 } \op__lk$128 { \op__imm_data__imm_ok$127 \op__imm_data__imm$126 } \op__fn_unit$125 \op__insn_type$124 }
+ assign { \op__insn$19$next \op__data_len$18$next \op__is_signed$17$next \op__is_32bit$16$next \op__output_carry$15$next \op__input_carry$14$next \op__write_cr0$13$next \op__invert_out$12$next \op__zero_a$11$next \op__invert_a$10$next { \op__oe__oe_ok$9$next \op__oe__oe$8$next } { \op__rc__rc_ok$7$next \op__rc__rc$6$next } { \op__imm_data__imm_ok$5$next \op__imm_data__imm$4$next } \op__fn_unit$3$next \op__insn_type$2$next } { \op__insn$117 \op__data_len$116 \op__is_signed$115 \op__is_32bit$114 \op__output_carry$113 \op__input_carry$112 \op__write_cr0$111 \op__invert_out$110 \op__zero_a$109 \op__invert_a$108 { \op__oe__oe_ok$107 \op__oe__oe$106 } { \op__rc__rc_ok$105 \op__rc__rc$104 } { \op__imm_data__imm_ok$103 \op__imm_data__imm$102 } \op__fn_unit$101 \op__insn_type$100 }
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \op__imm_data__imm$4$next 64'0000000000000000000000000000000000000000000000000000000000000000
assign \op__imm_data__imm_ok$5$next 1'0
- assign \op__rc__rc$7$next 1'0
- assign \op__rc__rc_ok$8$next 1'0
- assign \op__oe__oe$9$next 1'0
- assign \op__oe__oe_ok$10$next 1'0
- assign \op__write_cr__data$14$next 3'000
- assign \op__write_cr__ok$15$next 1'0
- assign \op__insn$23$next 32'00000000000000000000000000000000
+ assign \op__rc__rc$6$next 1'0
+ assign \op__rc__rc_ok$7$next 1'0
+ assign \op__oe__oe$8$next 1'0
+ assign \op__oe__oe_ok$9$next 1'0
end
sync init
update \op__insn_type$2 7'0000000
update \op__fn_unit$3 11'00000000000
update \op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000
update \op__imm_data__imm_ok$5 1'0
- update \op__lk$6 1'0
- update \op__rc__rc$7 1'0
- update \op__rc__rc_ok$8 1'0
- update \op__oe__oe$9 1'0
- update \op__oe__oe_ok$10 1'0
- update \op__invert_a$11 1'0
- update \op__zero_a$12 1'0
- update \op__invert_out$13 1'0
- update \op__write_cr__data$14 3'000
- update \op__write_cr__ok$15 1'0
- update \op__input_carry$16 2'00
- update \op__output_carry$17 1'0
- update \op__input_cr$18 1'0
- update \op__output_cr$19 1'0
- update \op__is_32bit$20 1'0
- update \op__is_signed$21 1'0
- update \op__data_len$22 4'0000
- update \op__insn$23 32'00000000000000000000000000000000
- update \op__byte_reverse$24 1'0
- update \op__sign_extend$25 1'0
+ update \op__rc__rc$6 1'0
+ update \op__rc__rc_ok$7 1'0
+ update \op__oe__oe$8 1'0
+ update \op__oe__oe_ok$9 1'0
+ update \op__invert_a$10 1'0
+ update \op__zero_a$11 1'0
+ update \op__invert_out$12 1'0
+ update \op__write_cr0$13 1'0
+ update \op__input_carry$14 2'00
+ update \op__output_carry$15 1'0
+ update \op__is_32bit$16 1'0
+ update \op__is_signed$17 1'0
+ update \op__data_len$18 4'0000
+ update \op__insn$19 32'00000000000000000000000000000000
sync posedge \clk
update \op__insn_type$2 \op__insn_type$2$next
update \op__fn_unit$3 \op__fn_unit$3$next
update \op__imm_data__imm$4 \op__imm_data__imm$4$next
update \op__imm_data__imm_ok$5 \op__imm_data__imm_ok$5$next
- update \op__lk$6 \op__lk$6$next
- update \op__rc__rc$7 \op__rc__rc$7$next
- update \op__rc__rc_ok$8 \op__rc__rc_ok$8$next
- update \op__oe__oe$9 \op__oe__oe$9$next
- update \op__oe__oe_ok$10 \op__oe__oe_ok$10$next
- update \op__invert_a$11 \op__invert_a$11$next
- update \op__zero_a$12 \op__zero_a$12$next
- update \op__invert_out$13 \op__invert_out$13$next
- update \op__write_cr__data$14 \op__write_cr__data$14$next
- update \op__write_cr__ok$15 \op__write_cr__ok$15$next
- update \op__input_carry$16 \op__input_carry$16$next
- update \op__output_carry$17 \op__output_carry$17$next
- update \op__input_cr$18 \op__input_cr$18$next
- update \op__output_cr$19 \op__output_cr$19$next
- update \op__is_32bit$20 \op__is_32bit$20$next
- update \op__is_signed$21 \op__is_signed$21$next
- update \op__data_len$22 \op__data_len$22$next
- update \op__insn$23 \op__insn$23$next
- update \op__byte_reverse$24 \op__byte_reverse$24$next
- update \op__sign_extend$25 \op__sign_extend$25$next
+ update \op__rc__rc$6 \op__rc__rc$6$next
+ update \op__rc__rc_ok$7 \op__rc__rc_ok$7$next
+ update \op__oe__oe$8 \op__oe__oe$8$next
+ update \op__oe__oe_ok$9 \op__oe__oe_ok$9$next
+ update \op__invert_a$10 \op__invert_a$10$next
+ update \op__zero_a$11 \op__zero_a$11$next
+ update \op__invert_out$12 \op__invert_out$12$next
+ update \op__write_cr0$13 \op__write_cr0$13$next
+ update \op__input_carry$14 \op__input_carry$14$next
+ update \op__output_carry$15 \op__output_carry$15$next
+ update \op__is_32bit$16 \op__is_32bit$16$next
+ update \op__is_signed$17 \op__is_signed$17$next
+ update \op__data_len$18 \op__data_len$18$next
+ update \op__insn$19 \op__insn$19$next
end
- process $group_157
+ process $group_127
assign \o$next \o
assign \o_ok$next \o_ok
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
switch { \n_i_rdy_data \p_valid_i_p_ready_o }
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
case 2'-1
- assign { \o_ok$next \o$next } { \o_ok$149 \o$148 }
+ assign { \o_ok$next \o$next } { \o_ok$119 \o$118 }
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
case 2'1-
- assign { \o_ok$next \o$next } { \o_ok$149 \o$148 }
+ assign { \o_ok$next \o$next } { \o_ok$119 \o$118 }
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
update \o \o$next
update \o_ok \o_ok$next
end
- process $group_159
+ process $group_129
assign \cr_a$next \cr_a
assign \cr_a_ok$next \cr_a_ok
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
switch { \n_i_rdy_data \p_valid_i_p_ready_o }
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
case 2'-1
- assign { \cr_a_ok$next \cr_a$next } { \cr_a_ok$151 \cr_a$150 }
+ assign { \cr_a_ok$next \cr_a$next } { \cr_a_ok$121 \cr_a$120 }
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
case 2'1-
- assign { \cr_a_ok$next \cr_a$next } { \cr_a_ok$151 \cr_a$150 }
+ assign { \cr_a_ok$next \cr_a$next } { \cr_a_ok$121 \cr_a$120 }
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
update \cr_a \cr_a$next
update \cr_a_ok \cr_a_ok$next
end
- process $group_161
- assign \xer_ca$26$next \xer_ca$26
+ process $group_131
+ assign \xer_ca$20$next \xer_ca$20
assign \xer_ca_ok$next \xer_ca_ok
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
switch { \n_i_rdy_data \p_valid_i_p_ready_o }
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
case 2'-1
- assign { \xer_ca_ok$next \xer_ca$26$next } { \xer_ca_ok$153 \xer_ca$152 }
+ assign { \xer_ca_ok$next \xer_ca$20$next } { \xer_ca_ok$123 \xer_ca$122 }
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
case 2'1-
- assign { \xer_ca_ok$next \xer_ca$26$next } { \xer_ca_ok$153 \xer_ca$152 }
+ assign { \xer_ca_ok$next \xer_ca$20$next } { \xer_ca_ok$123 \xer_ca$122 }
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
assign \xer_ca_ok$next 1'0
end
sync init
- update \xer_ca$26 2'00
+ update \xer_ca$20 2'00
update \xer_ca_ok 1'0
sync posedge \clk
- update \xer_ca$26 \xer_ca$26$next
+ update \xer_ca$20 \xer_ca$20$next
update \xer_ca_ok \xer_ca_ok$next
end
- process $group_163
+ process $group_133
assign \xer_ov$next \xer_ov
assign \xer_ov_ok$next \xer_ov_ok
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
switch { \n_i_rdy_data \p_valid_i_p_ready_o }
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
case 2'-1
- assign { \xer_ov_ok$next \xer_ov$next } { \xer_ov_ok$155 \xer_ov$154 }
+ assign { \xer_ov_ok$next \xer_ov$next } { \xer_ov_ok$125 \xer_ov$124 }
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
case 2'1-
- assign { \xer_ov_ok$next \xer_ov$next } { \xer_ov_ok$155 \xer_ov$154 }
+ assign { \xer_ov_ok$next \xer_ov$next } { \xer_ov_ok$125 \xer_ov$124 }
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
update \xer_ov \xer_ov$next
update \xer_ov_ok \xer_ov_ok$next
end
- process $group_165
- assign \xer_so$27$next \xer_so$27
+ process $group_135
+ assign \xer_so$21$next \xer_so$21
assign \xer_so_ok$next \xer_so_ok
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
switch { \n_i_rdy_data \p_valid_i_p_ready_o }
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
case 2'-1
- assign { \xer_so_ok$next \xer_so$27$next } { \xer_so_ok$157 \xer_so$156 }
+ assign { \xer_so_ok$next \xer_so$21$next } { \xer_so_ok$127 \xer_so$126 }
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
case 2'1-
- assign { \xer_so_ok$next \xer_so$27$next } { \xer_so_ok$157 \xer_so$156 }
+ assign { \xer_so_ok$next \xer_so$21$next } { \xer_so_ok$127 \xer_so$126 }
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
assign \xer_so_ok$next 1'0
end
sync init
- update \xer_so$27 1'0
+ update \xer_so$21 1'0
update \xer_so_ok 1'0
sync posedge \clk
- update \xer_so$27 \xer_so$27$next
+ update \xer_so$21 \xer_so$21$next
update \xer_so_ok \xer_so_ok$next
end
- process $group_167
+ process $group_137
assign \n_valid_o 1'0
assign \n_valid_o \r_busy
sync init
end
- process $group_168
+ process $group_138
assign \p_ready_o 1'0
assign \p_ready_o \n_i_rdy_data
sync init
end
- connect \xer_so_ok$119 1'0
+ connect \xer_so_ok$95 1'0
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu_alu0"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 2 \o_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 output 3 \o
+ wire width 1 output 3 \cr_a_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 4 \cr_a_ok
+ wire width 1 output 4 \xer_ca_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 4 output 5 \cr_a
+ wire width 1 output 5 \xer_ov_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 6 \xer_ca_ok
+ wire width 1 output 6 \xer_so_ok
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
+ wire width 1 output 7 \n_valid_o
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
+ wire width 1 input 8 \n_ready_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 2 output 7 \xer_ca
+ wire width 64 output 9 \o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 8 \xer_ov_ok
+ wire width 4 output 10 \cr_a
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 2 output 9 \xer_ov
+ wire width 2 output 11 \xer_ca
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 10 \xer_so_ok
+ wire width 2 output 12 \xer_ov
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 11 \xer_so
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244"
- wire width 1 output 12 \n_valid_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245"
- wire width 1 input 13 \n_ready_i
- attribute \enum_base_type "InternalOp"
+ wire width 1 output 13 \xer_so
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 7 input 14 \op__insn_type
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00100000000 "MUL"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 11 input 15 \op__fn_unit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 64 input 16 \op__imm_data__imm
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 input 17 \op__imm_data__imm_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 input 18 \op__lk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 input 19 \op__rc__rc
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 input 20 \op__rc__rc_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 input 21 \op__oe__oe
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 input 22 \op__oe__oe_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 input 23 \op__invert_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 input 24 \op__zero_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 input 25 \op__invert_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 3 input 26 \op__write_cr__data
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 input 27 \op__write_cr__ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 18 \op__rc__rc
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 19 \op__rc__rc_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 20 \op__oe__oe
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 21 \op__oe__oe_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 22 \op__invert_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 23 \op__zero_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 24 \op__invert_out
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 25 \op__write_cr0
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 2 input 28 \op__input_carry
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 input 29 \op__output_carry
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 input 30 \op__input_cr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 input 31 \op__output_cr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 input 32 \op__is_32bit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 input 33 \op__is_signed
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 4 input 34 \op__data_len
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 32 input 35 \op__insn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 input 36 \op__byte_reverse
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 input 37 \op__sign_extend
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
- wire width 64 input 38 \ra
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
- wire width 64 input 39 \rb
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
- wire width 1 input 40 \xer_so$1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
- wire width 2 input 41 \xer_ca$2
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151"
- wire width 1 input 42 \p_valid_i
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152"
- wire width 1 output 43 \p_ready_o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 2 input 26 \op__input_carry
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 27 \op__output_carry
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 28 \op__is_32bit
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 29 \op__is_signed
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 4 input 30 \op__data_len
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 input 31 \op__insn
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 64 input 32 \ra
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 64 input 33 \rb
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 1 input 34 \xer_so$1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 2 input 35 \xer_ca$2
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153"
+ wire width 1 input 36 \p_valid_i
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154"
+ wire width 1 output 37 \p_ready_o
cell \p \p
connect \p_valid_i \p_valid_i
connect \p_ready_o \p_ready_o
connect \n_valid_o \n_valid_o
connect \n_ready_i \n_ready_i
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153"
wire width 1 \pipe_p_valid_i
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154"
wire width 1 \pipe_p_ready_o
- attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
wire width 2 \pipe_muxid
- attribute \enum_base_type "InternalOp"
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 7 \pipe_op__insn_type
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00100000000 "MUL"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 11 \pipe_op__fn_unit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 64 \pipe_op__imm_data__imm
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \pipe_op__imm_data__imm_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 \pipe_op__lk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \pipe_op__rc__rc
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \pipe_op__rc__rc_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \pipe_op__oe__oe
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \pipe_op__oe__oe_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \pipe_op__invert_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \pipe_op__zero_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \pipe_op__invert_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 3 \pipe_op__write_cr__data
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 \pipe_op__write_cr__ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \pipe_op__write_cr0
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 2 \pipe_op__input_carry
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \pipe_op__output_carry
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 \pipe_op__input_cr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 \pipe_op__output_cr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \pipe_op__is_32bit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \pipe_op__is_signed
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 4 \pipe_op__data_len
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 32 \pipe_op__insn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 \pipe_op__byte_reverse
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 \pipe_op__sign_extend
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
wire width 64 \pipe_ra
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
wire width 64 \pipe_rb
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
wire width 1 \pipe_xer_so
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
wire width 2 \pipe_xer_ca
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
wire width 1 \pipe_n_valid_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
wire width 1 \pipe_n_ready_i
- attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
wire width 2 \pipe_muxid$3
- attribute \enum_base_type "InternalOp"
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 7 \pipe_op__insn_type$4
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00100000000 "MUL"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 11 \pipe_op__fn_unit$5
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 64 \pipe_op__imm_data__imm$6
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \pipe_op__imm_data__imm_ok$7
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 \pipe_op__lk$8
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 \pipe_op__rc__rc$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 \pipe_op__rc__rc_ok$10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 \pipe_op__oe__oe$11
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 \pipe_op__oe__oe_ok$12
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 \pipe_op__invert_a$13
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 \pipe_op__zero_a$14
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 \pipe_op__invert_out$15
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 3 \pipe_op__write_cr__data$16
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 \pipe_op__write_cr__ok$17
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \pipe_op__rc__rc$8
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \pipe_op__rc__rc_ok$9
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \pipe_op__oe__oe$10
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \pipe_op__oe__oe_ok$11
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \pipe_op__invert_a$12
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \pipe_op__zero_a$13
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \pipe_op__invert_out$14
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \pipe_op__write_cr0$15
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 2 \pipe_op__input_carry$18
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 \pipe_op__output_carry$19
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 \pipe_op__input_cr$20
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 \pipe_op__output_cr$21
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 \pipe_op__is_32bit$22
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 \pipe_op__is_signed$23
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 4 \pipe_op__data_len$24
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 32 \pipe_op__insn$25
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 \pipe_op__byte_reverse$26
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 \pipe_op__sign_extend$27
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 2 \pipe_op__input_carry$16
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \pipe_op__output_carry$17
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \pipe_op__is_32bit$18
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \pipe_op__is_signed$19
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 4 \pipe_op__data_len$20
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 \pipe_op__insn$21
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 64 \pipe_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 \pipe_cr_a_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 2 \pipe_xer_ca$28
+ wire width 2 \pipe_xer_ca$22
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 \pipe_xer_ca_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 \pipe_xer_ov_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 \pipe_xer_so$29
+ wire width 1 \pipe_xer_so$23
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 \pipe_xer_so_ok
cell \pipe \pipe
connect \op__fn_unit \pipe_op__fn_unit
connect \op__imm_data__imm \pipe_op__imm_data__imm
connect \op__imm_data__imm_ok \pipe_op__imm_data__imm_ok
- connect \op__lk \pipe_op__lk
connect \op__rc__rc \pipe_op__rc__rc
connect \op__rc__rc_ok \pipe_op__rc__rc_ok
connect \op__oe__oe \pipe_op__oe__oe
connect \op__invert_a \pipe_op__invert_a
connect \op__zero_a \pipe_op__zero_a
connect \op__invert_out \pipe_op__invert_out
- connect \op__write_cr__data \pipe_op__write_cr__data
- connect \op__write_cr__ok \pipe_op__write_cr__ok
+ connect \op__write_cr0 \pipe_op__write_cr0
connect \op__input_carry \pipe_op__input_carry
connect \op__output_carry \pipe_op__output_carry
- connect \op__input_cr \pipe_op__input_cr
- connect \op__output_cr \pipe_op__output_cr
connect \op__is_32bit \pipe_op__is_32bit
connect \op__is_signed \pipe_op__is_signed
connect \op__data_len \pipe_op__data_len
connect \op__insn \pipe_op__insn
- connect \op__byte_reverse \pipe_op__byte_reverse
- connect \op__sign_extend \pipe_op__sign_extend
connect \ra \pipe_ra
connect \rb \pipe_rb
connect \xer_so \pipe_xer_so
connect \op__fn_unit$3 \pipe_op__fn_unit$5
connect \op__imm_data__imm$4 \pipe_op__imm_data__imm$6
connect \op__imm_data__imm_ok$5 \pipe_op__imm_data__imm_ok$7
- connect \op__lk$6 \pipe_op__lk$8
- connect \op__rc__rc$7 \pipe_op__rc__rc$9
- connect \op__rc__rc_ok$8 \pipe_op__rc__rc_ok$10
- connect \op__oe__oe$9 \pipe_op__oe__oe$11
- connect \op__oe__oe_ok$10 \pipe_op__oe__oe_ok$12
- connect \op__invert_a$11 \pipe_op__invert_a$13
- connect \op__zero_a$12 \pipe_op__zero_a$14
- connect \op__invert_out$13 \pipe_op__invert_out$15
- connect \op__write_cr__data$14 \pipe_op__write_cr__data$16
- connect \op__write_cr__ok$15 \pipe_op__write_cr__ok$17
- connect \op__input_carry$16 \pipe_op__input_carry$18
- connect \op__output_carry$17 \pipe_op__output_carry$19
- connect \op__input_cr$18 \pipe_op__input_cr$20
- connect \op__output_cr$19 \pipe_op__output_cr$21
- connect \op__is_32bit$20 \pipe_op__is_32bit$22
- connect \op__is_signed$21 \pipe_op__is_signed$23
- connect \op__data_len$22 \pipe_op__data_len$24
- connect \op__insn$23 \pipe_op__insn$25
- connect \op__byte_reverse$24 \pipe_op__byte_reverse$26
- connect \op__sign_extend$25 \pipe_op__sign_extend$27
+ connect \op__rc__rc$6 \pipe_op__rc__rc$8
+ connect \op__rc__rc_ok$7 \pipe_op__rc__rc_ok$9
+ connect \op__oe__oe$8 \pipe_op__oe__oe$10
+ connect \op__oe__oe_ok$9 \pipe_op__oe__oe_ok$11
+ connect \op__invert_a$10 \pipe_op__invert_a$12
+ connect \op__zero_a$11 \pipe_op__zero_a$13
+ connect \op__invert_out$12 \pipe_op__invert_out$14
+ connect \op__write_cr0$13 \pipe_op__write_cr0$15
+ connect \op__input_carry$14 \pipe_op__input_carry$16
+ connect \op__output_carry$15 \pipe_op__output_carry$17
+ connect \op__is_32bit$16 \pipe_op__is_32bit$18
+ connect \op__is_signed$17 \pipe_op__is_signed$19
+ connect \op__data_len$18 \pipe_op__data_len$20
+ connect \op__insn$19 \pipe_op__insn$21
connect \o \pipe_o
connect \o_ok \pipe_o_ok
connect \cr_a \pipe_cr_a
connect \cr_a_ok \pipe_cr_a_ok
- connect \xer_ca$26 \pipe_xer_ca$28
+ connect \xer_ca$20 \pipe_xer_ca$22
connect \xer_ca_ok \pipe_xer_ca_ok
connect \xer_ov \pipe_xer_ov
connect \xer_ov_ok \pipe_xer_ov_ok
- connect \xer_so$27 \pipe_xer_so$29
+ connect \xer_so$21 \pipe_xer_so$23
connect \xer_so_ok \pipe_xer_so_ok
end
process $group_0
assign \p_ready_o \pipe_p_ready_o
sync init
end
- attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
wire width 2 \muxid
process $group_2
assign \pipe_muxid 2'00
assign \pipe_op__fn_unit 11'00000000000
assign \pipe_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
assign \pipe_op__imm_data__imm_ok 1'0
- assign \pipe_op__lk 1'0
assign \pipe_op__rc__rc 1'0
assign \pipe_op__rc__rc_ok 1'0
assign \pipe_op__oe__oe 1'0
assign \pipe_op__invert_a 1'0
assign \pipe_op__zero_a 1'0
assign \pipe_op__invert_out 1'0
- assign \pipe_op__write_cr__data 3'000
- assign \pipe_op__write_cr__ok 1'0
+ assign \pipe_op__write_cr0 1'0
assign \pipe_op__input_carry 2'00
assign \pipe_op__output_carry 1'0
- assign \pipe_op__input_cr 1'0
- assign \pipe_op__output_cr 1'0
assign \pipe_op__is_32bit 1'0
assign \pipe_op__is_signed 1'0
assign \pipe_op__data_len 4'0000
assign \pipe_op__insn 32'00000000000000000000000000000000
- assign \pipe_op__byte_reverse 1'0
- assign \pipe_op__sign_extend 1'0
- assign { \pipe_op__sign_extend \pipe_op__byte_reverse \pipe_op__insn \pipe_op__data_len \pipe_op__is_signed \pipe_op__is_32bit \pipe_op__output_cr \pipe_op__input_cr \pipe_op__output_carry \pipe_op__input_carry { \pipe_op__write_cr__ok \pipe_op__write_cr__data } \pipe_op__invert_out \pipe_op__zero_a \pipe_op__invert_a { \pipe_op__oe__oe_ok \pipe_op__oe__oe } { \pipe_op__rc__rc_ok \pipe_op__rc__rc } \pipe_op__lk { \pipe_op__imm_data__imm_ok \pipe_op__imm_data__imm } \pipe_op__fn_unit \pipe_op__insn_type } { \op__sign_extend \op__byte_reverse \op__insn \op__data_len \op__is_signed \op__is_32bit \op__output_cr \op__input_cr \op__output_carry \op__input_carry { \op__write_cr__ok \op__write_cr__data } \op__invert_out \op__zero_a \op__invert_a { \op__oe__oe_ok \op__oe__oe } { \op__rc__rc_ok \op__rc__rc } \op__lk { \op__imm_data__imm_ok \op__imm_data__imm } \op__fn_unit \op__insn_type }
+ assign { \pipe_op__insn \pipe_op__data_len \pipe_op__is_signed \pipe_op__is_32bit \pipe_op__output_carry \pipe_op__input_carry \pipe_op__write_cr0 \pipe_op__invert_out \pipe_op__zero_a \pipe_op__invert_a { \pipe_op__oe__oe_ok \pipe_op__oe__oe } { \pipe_op__rc__rc_ok \pipe_op__rc__rc } { \pipe_op__imm_data__imm_ok \pipe_op__imm_data__imm } \pipe_op__fn_unit \pipe_op__insn_type } { \op__insn \op__data_len \op__is_signed \op__is_32bit \op__output_carry \op__input_carry \op__write_cr0 \op__invert_out \op__zero_a \op__invert_a { \op__oe__oe_ok \op__oe__oe } { \op__rc__rc_ok \op__rc__rc } { \op__imm_data__imm_ok \op__imm_data__imm } \op__fn_unit \op__insn_type }
sync init
end
- process $group_27
+ process $group_21
assign \pipe_ra 64'0000000000000000000000000000000000000000000000000000000000000000
assign \pipe_ra \ra
sync init
end
- process $group_28
+ process $group_22
assign \pipe_rb 64'0000000000000000000000000000000000000000000000000000000000000000
assign \pipe_rb \rb
sync init
end
- process $group_29
+ process $group_23
assign \pipe_xer_so 1'0
assign \pipe_xer_so \xer_so$1
sync init
end
- process $group_30
+ process $group_24
assign \pipe_xer_ca 2'00
assign \pipe_xer_ca \xer_ca$2
sync init
end
- process $group_31
+ process $group_25
assign \n_valid_o 1'0
assign \n_valid_o \pipe_n_valid_o
sync init
end
- process $group_32
+ process $group_26
assign \pipe_n_ready_i 1'0
assign \pipe_n_ready_i \n_ready_i
sync init
end
- attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
- wire width 2 \muxid$30
- process $group_33
- assign \muxid$30 2'00
- assign \muxid$30 \pipe_muxid$3
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+ wire width 2 \muxid$24
+ process $group_27
+ assign \muxid$24 2'00
+ assign \muxid$24 \pipe_muxid$3
sync init
end
- attribute \enum_base_type "InternalOp"
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 7 \op__insn_type$31
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 7 \op__insn_type$25
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00000000010 "ALU"
attribute \enum_value_00100000000 "MUL"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 11 \op__fn_unit$32
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 64 \op__imm_data__imm$33
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 \op__imm_data__imm_ok$34
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 \op__lk$35
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 \op__rc__rc$36
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 \op__rc__rc_ok$37
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 \op__oe__oe$38
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 \op__oe__oe_ok$39
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 \op__invert_a$40
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 \op__zero_a$41
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 \op__invert_out$42
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 3 \op__write_cr__data$43
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 \op__write_cr__ok$44
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 11 \op__fn_unit$26
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 \op__imm_data__imm$27
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__imm_data__imm_ok$28
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__rc__rc$29
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__rc__rc_ok$30
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__oe__oe$31
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__oe__oe_ok$32
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__invert_a$33
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__zero_a$34
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__invert_out$35
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__write_cr0$36
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 2 \op__input_carry$45
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 \op__output_carry$46
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 \op__input_cr$47
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 \op__output_cr$48
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 \op__is_32bit$49
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 \op__is_signed$50
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 4 \op__data_len$51
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 32 \op__insn$52
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 \op__byte_reverse$53
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 \op__sign_extend$54
- process $group_34
- assign \op__insn_type$31 7'0000000
- assign \op__fn_unit$32 11'00000000000
- assign \op__imm_data__imm$33 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \op__imm_data__imm_ok$34 1'0
- assign \op__lk$35 1'0
- assign \op__rc__rc$36 1'0
- assign \op__rc__rc_ok$37 1'0
- assign \op__oe__oe$38 1'0
- assign \op__oe__oe_ok$39 1'0
- assign \op__invert_a$40 1'0
- assign \op__zero_a$41 1'0
- assign \op__invert_out$42 1'0
- assign \op__write_cr__data$43 3'000
- assign \op__write_cr__ok$44 1'0
- assign \op__input_carry$45 2'00
- assign \op__output_carry$46 1'0
- assign \op__input_cr$47 1'0
- assign \op__output_cr$48 1'0
- assign \op__is_32bit$49 1'0
- assign \op__is_signed$50 1'0
- assign \op__data_len$51 4'0000
- assign \op__insn$52 32'00000000000000000000000000000000
- assign \op__byte_reverse$53 1'0
- assign \op__sign_extend$54 1'0
- assign { \op__sign_extend$54 \op__byte_reverse$53 \op__insn$52 \op__data_len$51 \op__is_signed$50 \op__is_32bit$49 \op__output_cr$48 \op__input_cr$47 \op__output_carry$46 \op__input_carry$45 { \op__write_cr__ok$44 \op__write_cr__data$43 } \op__invert_out$42 \op__zero_a$41 \op__invert_a$40 { \op__oe__oe_ok$39 \op__oe__oe$38 } { \op__rc__rc_ok$37 \op__rc__rc$36 } \op__lk$35 { \op__imm_data__imm_ok$34 \op__imm_data__imm$33 } \op__fn_unit$32 \op__insn_type$31 } { \pipe_op__sign_extend$27 \pipe_op__byte_reverse$26 \pipe_op__insn$25 \pipe_op__data_len$24 \pipe_op__is_signed$23 \pipe_op__is_32bit$22 \pipe_op__output_cr$21 \pipe_op__input_cr$20 \pipe_op__output_carry$19 \pipe_op__input_carry$18 { \pipe_op__write_cr__ok$17 \pipe_op__write_cr__data$16 } \pipe_op__invert_out$15 \pipe_op__zero_a$14 \pipe_op__invert_a$13 { \pipe_op__oe__oe_ok$12 \pipe_op__oe__oe$11 } { \pipe_op__rc__rc_ok$10 \pipe_op__rc__rc$9 } \pipe_op__lk$8 { \pipe_op__imm_data__imm_ok$7 \pipe_op__imm_data__imm$6 } \pipe_op__fn_unit$5 \pipe_op__insn_type$4 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 2 \op__input_carry$37
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__output_carry$38
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__is_32bit$39
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__is_signed$40
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 4 \op__data_len$41
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 \op__insn$42
+ process $group_28
+ assign \op__insn_type$25 7'0000000
+ assign \op__fn_unit$26 11'00000000000
+ assign \op__imm_data__imm$27 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \op__imm_data__imm_ok$28 1'0
+ assign \op__rc__rc$29 1'0
+ assign \op__rc__rc_ok$30 1'0
+ assign \op__oe__oe$31 1'0
+ assign \op__oe__oe_ok$32 1'0
+ assign \op__invert_a$33 1'0
+ assign \op__zero_a$34 1'0
+ assign \op__invert_out$35 1'0
+ assign \op__write_cr0$36 1'0
+ assign \op__input_carry$37 2'00
+ assign \op__output_carry$38 1'0
+ assign \op__is_32bit$39 1'0
+ assign \op__is_signed$40 1'0
+ assign \op__data_len$41 4'0000
+ assign \op__insn$42 32'00000000000000000000000000000000
+ assign { \op__insn$42 \op__data_len$41 \op__is_signed$40 \op__is_32bit$39 \op__output_carry$38 \op__input_carry$37 \op__write_cr0$36 \op__invert_out$35 \op__zero_a$34 \op__invert_a$33 { \op__oe__oe_ok$32 \op__oe__oe$31 } { \op__rc__rc_ok$30 \op__rc__rc$29 } { \op__imm_data__imm_ok$28 \op__imm_data__imm$27 } \op__fn_unit$26 \op__insn_type$25 } { \pipe_op__insn$21 \pipe_op__data_len$20 \pipe_op__is_signed$19 \pipe_op__is_32bit$18 \pipe_op__output_carry$17 \pipe_op__input_carry$16 \pipe_op__write_cr0$15 \pipe_op__invert_out$14 \pipe_op__zero_a$13 \pipe_op__invert_a$12 { \pipe_op__oe__oe_ok$11 \pipe_op__oe__oe$10 } { \pipe_op__rc__rc_ok$9 \pipe_op__rc__rc$8 } { \pipe_op__imm_data__imm_ok$7 \pipe_op__imm_data__imm$6 } \pipe_op__fn_unit$5 \pipe_op__insn_type$4 }
sync init
end
- process $group_58
+ process $group_46
assign \o 64'0000000000000000000000000000000000000000000000000000000000000000
assign \o_ok 1'0
assign { \o_ok \o } { \pipe_o_ok \pipe_o }
sync init
end
- process $group_60
+ process $group_48
assign \cr_a 4'0000
assign \cr_a_ok 1'0
assign { \cr_a_ok \cr_a } { \pipe_cr_a_ok \pipe_cr_a }
sync init
end
- process $group_62
+ process $group_50
assign \xer_ca 2'00
assign \xer_ca_ok 1'0
- assign { \xer_ca_ok \xer_ca } { \pipe_xer_ca_ok \pipe_xer_ca$28 }
+ assign { \xer_ca_ok \xer_ca } { \pipe_xer_ca_ok \pipe_xer_ca$22 }
sync init
end
- process $group_64
+ process $group_52
assign \xer_ov 2'00
assign \xer_ov_ok 1'0
assign { \xer_ov_ok \xer_ov } { \pipe_xer_ov_ok \pipe_xer_ov }
sync init
end
- process $group_66
+ process $group_54
assign \xer_so 1'0
assign \xer_so_ok 1'0
- assign { \xer_so_ok \xer_so } { \pipe_xer_so_ok \pipe_xer_so$29 }
+ assign { \xer_so_ok \xer_so } { \pipe_xer_so_ok \pipe_xer_so$23 }
sync init
end
connect \muxid 2'00
wire width 1 input 0 \rst
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
- attribute \enum_base_type "InternalOp"
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 7 input 2 \oper_i__insn_type
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00100000000 "MUL"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 11 input 3 \oper_i__fn_unit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 64 input 4 \oper_i__imm_data__imm
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 input 5 \oper_i__imm_data__imm_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 input 6 \oper_i__lk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 input 7 \oper_i__rc__rc
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 input 8 \oper_i__rc__rc_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 input 9 \oper_i__oe__oe
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 input 10 \oper_i__oe__oe_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 input 11 \oper_i__invert_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 input 12 \oper_i__zero_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 input 13 \oper_i__invert_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 3 input 14 \oper_i__write_cr__data
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 input 15 \oper_i__write_cr__ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 6 \oper_i__rc__rc
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 7 \oper_i__rc__rc_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 8 \oper_i__oe__oe
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 9 \oper_i__oe__oe_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 10 \oper_i__invert_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 11 \oper_i__zero_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 12 \oper_i__invert_out
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 13 \oper_i__write_cr0
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 2 input 16 \oper_i__input_carry
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 input 17 \oper_i__output_carry
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 input 18 \oper_i__input_cr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 input 19 \oper_i__output_cr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 input 20 \oper_i__is_32bit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 input 21 \oper_i__is_signed
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 4 input 22 \oper_i__data_len
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 32 input 23 \oper_i__insn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 input 24 \oper_i__byte_reverse
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 input 25 \oper_i__sign_extend
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 2 input 14 \oper_i__input_carry
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 15 \oper_i__output_carry
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 16 \oper_i__is_32bit
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 17 \oper_i__is_signed
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 4 input 18 \oper_i__data_len
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 input 19 \oper_i__insn
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94"
- wire width 1 input 26 \issue_i
+ wire width 1 input 20 \issue_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
- wire width 1 output 27 \busy_o
+ wire width 1 output 21 \busy_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:92"
- wire width 4 input 28 \rdmaskn
+ wire width 4 input 22 \rdmaskn
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 4 output 29 \rd__rel
+ wire width 4 output 23 \rd__rel
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 4 input 30 \rd__go
+ wire width 4 input 24 \rd__go
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
- wire width 64 input 31 \src1_i
+ wire width 64 input 25 \src1_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
- wire width 64 input 32 \src2_i
+ wire width 64 input 26 \src2_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
- wire width 1 input 33 \src3_i
+ wire width 1 input 27 \src3_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
- wire width 2 input 34 \src4_i
+ wire width 2 input 28 \src4_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 35 \o_ok
+ wire width 1 output 29 \o_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 5 output 36 \wr__rel
+ wire width 5 output 30 \wr__rel
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 5 input 37 \wr__go
+ wire width 5 input 31 \wr__go
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
+ wire width 64 output 32 \dest1_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 output 38 \o
+ wire width 1 output 33 \cr_a_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
+ wire width 4 output 34 \dest2_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 39 \cr_a_ok
+ wire width 1 output 35 \xer_ca_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
+ wire width 2 output 36 \dest3_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 4 output 40 \cr_a
+ wire width 1 output 37 \xer_ov_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
+ wire width 2 output 38 \dest4_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 41 \xer_ca_ok
+ wire width 1 output 39 \xer_so_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
+ wire width 1 output 40 \dest5_o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96"
+ wire width 1 input 41 \go_die_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
+ wire width 1 input 42 \shadown_i
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
+ wire width 1 \alu_alu0_n_valid_o
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
+ wire width 1 \alu_alu0_n_ready_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 2 output 42 \xer_ca
+ wire width 64 \alu_alu0_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 43 \xer_ov_ok
+ wire width 4 \alu_alu0_cr_a
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 2 output 44 \xer_ov
+ wire width 2 \alu_alu0_xer_ca
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 45 \xer_so_ok
+ wire width 2 \alu_alu0_xer_ov
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 46 \xer_so
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96"
- wire width 1 input 47 \go_die_i
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
- wire width 1 input 48 \shadown_i
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
- wire width 64 output 49 \dest1_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244"
- wire width 1 \alu_alu0_n_valid_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245"
- wire width 1 \alu_alu0_n_ready_i
- attribute \enum_base_type "InternalOp"
+ wire width 1 \alu_alu0_xer_so
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 7 \alu_alu0_op__insn_type
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00100000000 "MUL"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 11 \alu_alu0_op__fn_unit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 64 \alu_alu0_op__imm_data__imm
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \alu_alu0_op__imm_data__imm_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 \alu_alu0_op__lk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \alu_alu0_op__rc__rc
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \alu_alu0_op__rc__rc_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \alu_alu0_op__oe__oe
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \alu_alu0_op__oe__oe_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \alu_alu0_op__invert_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \alu_alu0_op__zero_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \alu_alu0_op__invert_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 3 \alu_alu0_op__write_cr__data
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 \alu_alu0_op__write_cr__ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \alu_alu0_op__write_cr0
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 2 \alu_alu0_op__input_carry
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \alu_alu0_op__output_carry
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 \alu_alu0_op__input_cr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 \alu_alu0_op__output_cr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \alu_alu0_op__is_32bit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \alu_alu0_op__is_signed
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 4 \alu_alu0_op__data_len
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 32 \alu_alu0_op__insn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 \alu_alu0_op__byte_reverse
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 \alu_alu0_op__sign_extend
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
wire width 64 \alu_alu0_ra
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
wire width 64 \alu_alu0_rb
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
- wire width 1 \alu_alu0_xer_so
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
- wire width 2 \alu_alu0_xer_ca
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 1 \alu_alu0_xer_so$1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 2 \alu_alu0_xer_ca$2
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153"
wire width 1 \alu_alu0_p_valid_i
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154"
wire width 1 \alu_alu0_p_ready_o
cell \alu_alu0 \alu_alu0
connect \rst \rst
connect \clk \clk
connect \o_ok \o_ok
- connect \o \o
connect \cr_a_ok \cr_a_ok
- connect \cr_a \cr_a
connect \xer_ca_ok \xer_ca_ok
- connect \xer_ca \xer_ca
connect \xer_ov_ok \xer_ov_ok
- connect \xer_ov \xer_ov
connect \xer_so_ok \xer_so_ok
- connect \xer_so \xer_so
connect \n_valid_o \alu_alu0_n_valid_o
connect \n_ready_i \alu_alu0_n_ready_i
+ connect \o \alu_alu0_o
+ connect \cr_a \alu_alu0_cr_a
+ connect \xer_ca \alu_alu0_xer_ca
+ connect \xer_ov \alu_alu0_xer_ov
+ connect \xer_so \alu_alu0_xer_so
connect \op__insn_type \alu_alu0_op__insn_type
connect \op__fn_unit \alu_alu0_op__fn_unit
connect \op__imm_data__imm \alu_alu0_op__imm_data__imm
connect \op__imm_data__imm_ok \alu_alu0_op__imm_data__imm_ok
- connect \op__lk \alu_alu0_op__lk
connect \op__rc__rc \alu_alu0_op__rc__rc
connect \op__rc__rc_ok \alu_alu0_op__rc__rc_ok
connect \op__oe__oe \alu_alu0_op__oe__oe
connect \op__invert_a \alu_alu0_op__invert_a
connect \op__zero_a \alu_alu0_op__zero_a
connect \op__invert_out \alu_alu0_op__invert_out
- connect \op__write_cr__data \alu_alu0_op__write_cr__data
- connect \op__write_cr__ok \alu_alu0_op__write_cr__ok
+ connect \op__write_cr0 \alu_alu0_op__write_cr0
connect \op__input_carry \alu_alu0_op__input_carry
connect \op__output_carry \alu_alu0_op__output_carry
- connect \op__input_cr \alu_alu0_op__input_cr
- connect \op__output_cr \alu_alu0_op__output_cr
connect \op__is_32bit \alu_alu0_op__is_32bit
connect \op__is_signed \alu_alu0_op__is_signed
connect \op__data_len \alu_alu0_op__data_len
connect \op__insn \alu_alu0_op__insn
- connect \op__byte_reverse \alu_alu0_op__byte_reverse
- connect \op__sign_extend \alu_alu0_op__sign_extend
connect \ra \alu_alu0_ra
connect \rb \alu_alu0_rb
- connect \xer_so$1 \alu_alu0_xer_so
- connect \xer_ca$2 \alu_alu0_xer_ca
+ connect \xer_so$1 \alu_alu0_xer_so$1
+ connect \xer_ca$2 \alu_alu0_xer_ca$2
connect \p_valid_i \alu_alu0_p_valid_i
connect \p_ready_o \alu_alu0_p_ready_o
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:178"
wire width 1 \all_rd
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179"
- wire width 1 $1
+ wire width 1 $3
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179"
- cell $and $2
+ cell $and $4
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \busy_o
connect \B \rok_l_q_rdok
- connect \Y $1
+ connect \Y $3
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180"
- wire width 1 $3
+ wire width 1 $5
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180"
- wire width 4 $4
+ wire width 4 $6
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180"
- cell $not $5
+ cell $not $7
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 4
connect \A \rd__rel
- connect \Y $4
+ connect \Y $6
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180"
- wire width 4 $6
+ wire width 4 $8
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180"
- cell $or $7
+ cell $or $9
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 4
- connect \A $4
+ connect \A $6
connect \B \rd__go
- connect \Y $6
+ connect \Y $8
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180"
- cell $reduce_and $8
+ cell $reduce_and $10
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 1
- connect \A $6
- connect \Y $3
+ connect \A $8
+ connect \Y $5
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180"
- wire width 1 $9
+ wire width 1 $11
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180"
- cell $and $10
+ cell $and $12
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $1
- connect \B $3
- connect \Y $9
+ connect \A $3
+ connect \B $5
+ connect \Y $11
end
process $group_0
assign \all_rd 1'0
- assign \all_rd $9
+ assign \all_rd $11
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:183"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:184"
wire width 1 \all_rd_pulse
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:186"
- wire width 1 $11
+ wire width 1 $13
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:186"
- cell $not $12
+ cell $not $14
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \all_rd_dly
- connect \Y $11
+ connect \Y $13
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:186"
- wire width 1 $13
+ wire width 1 $15
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:186"
- cell $and $14
+ cell $and $16
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \all_rd
- connect \B $11
- connect \Y $13
+ connect \B $13
+ connect \Y $15
end
process $group_2
assign \all_rd_pulse 1'0
- assign \all_rd_pulse $13
+ assign \all_rd_pulse $15
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:191"
wire width 1 \alu_pulse
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:195"
- wire width 1 $15
+ wire width 1 $17
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:195"
- cell $not $16
+ cell $not $18
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \alu_done_dly
- connect \Y $15
+ connect \Y $17
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:195"
- wire width 1 $17
+ wire width 1 $19
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:195"
- cell $and $18
+ cell $and $20
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \alu_done
- connect \B $15
- connect \Y $17
+ connect \B $17
+ connect \Y $19
end
process $group_5
assign \alu_pulse 1'0
- assign \alu_pulse $17
+ assign \alu_pulse $19
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:192"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:199"
wire width 5 \prev_wr_go$next
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:201"
- wire width 5 $19
+ wire width 5 $21
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:201"
- cell $and $20
+ cell $and $22
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A \wr__go
connect \B { \busy_o \busy_o \busy_o \busy_o \busy_o }
- connect \Y $19
+ connect \Y $21
end
process $group_7
assign \prev_wr_go$next \prev_wr_go
- assign \prev_wr_go$next $19
+ assign \prev_wr_go$next $21
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100"
wire width 1 \done_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
- wire width 1 $21
+ wire width 1 $23
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
- wire width 1 $22
+ wire width 1 $24
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
- wire width 5 $23
+ wire width 5 $25
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:93"
wire width 5 \wrmask
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
- cell $not $24
+ cell $not $26
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \Y_WIDTH 5
connect \A \wrmask
- connect \Y $23
+ connect \Y $25
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
- wire width 5 $25
+ wire width 5 $27
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
- cell $and $26
+ cell $and $28
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \B_WIDTH 5
parameter \Y_WIDTH 5
connect \A \wr__rel
- connect \B $23
- connect \Y $25
+ connect \B $25
+ connect \Y $27
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
- cell $reduce_bool $27
+ cell $reduce_bool $29
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \Y_WIDTH 1
- connect \A $25
- connect \Y $22
+ connect \A $27
+ connect \Y $24
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
- cell $not $28
+ cell $not $30
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $22
- connect \Y $21
+ connect \A $24
+ connect \Y $23
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
- wire width 1 $29
+ wire width 1 $31
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
- cell $and $30
+ cell $and $32
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \busy_o
- connect \B $21
- connect \Y $29
+ connect \B $23
+ connect \Y $31
end
process $group_8
assign \done_o 1'0
- assign \done_o $29
+ assign \done_o $31
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206"
wire width 1 \wr_any
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210"
- wire width 1 $31
+ wire width 1 $33
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210"
- cell $reduce_bool $32
+ cell $reduce_bool $34
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \Y_WIDTH 1
connect \A \wr__go
- connect \Y $31
+ connect \Y $33
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210"
- wire width 1 $33
+ wire width 1 $35
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210"
- cell $reduce_bool $34
+ cell $reduce_bool $36
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \Y_WIDTH 1
connect \A \prev_wr_go
- connect \Y $33
+ connect \Y $35
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210"
- wire width 1 $35
+ wire width 1 $37
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210"
- cell $or $36
+ cell $or $38
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $31
- connect \B $33
- connect \Y $35
+ connect \A $33
+ connect \B $35
+ connect \Y $37
end
process $group_9
assign \wr_any 1'0
- assign \wr_any $35
+ assign \wr_any $37
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:207"
wire width 1 \req_done
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211"
- wire width 1 $37
+ wire width 1 $39
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211"
- cell $not $38
+ cell $not $40
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \alu_alu0_n_ready_i
- connect \Y $37
+ connect \Y $39
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211"
- wire width 1 $39
+ wire width 1 $41
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211"
- cell $and $40
+ cell $and $42
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \wr_any
- connect \B $37
- connect \Y $39
+ connect \B $39
+ connect \Y $41
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212"
- wire width 5 $41
+ wire width 5 $43
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212"
- cell $and $42
+ cell $and $44
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A \req_l_q_req
connect \B \wrmask
- connect \Y $41
+ connect \Y $43
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212"
- wire width 1 $43
+ wire width 1 $45
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212"
- cell $eq $44
+ cell $eq $46
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $41
+ connect \A $43
connect \B 1'0
- connect \Y $43
+ connect \Y $45
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212"
- wire width 1 $45
+ wire width 1 $47
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212"
- cell $and $46
+ cell $and $48
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $39
- connect \B $43
- connect \Y $45
+ connect \A $41
+ connect \B $45
+ connect \Y $47
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
- wire width 1 $47
+ wire width 1 $49
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
- cell $eq $48
+ cell $eq $50
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wrmask
connect \B 1'0
- connect \Y $47
+ connect \Y $49
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
- wire width 1 $49
+ wire width 1 $51
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
- cell $and $50
+ cell $and $52
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $47
+ connect \A $49
connect \B \alu_alu0_n_ready_i
- connect \Y $49
+ connect \Y $51
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
- wire width 1 $51
+ wire width 1 $53
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
- cell $and $52
+ cell $and $54
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $49
+ connect \A $51
connect \B \alu_alu0_n_valid_o
- connect \Y $51
+ connect \Y $53
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
- wire width 1 $53
+ wire width 1 $55
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
- cell $and $54
+ cell $and $56
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $51
+ connect \A $53
connect \B \busy_o
- connect \Y $53
+ connect \Y $55
end
process $group_10
assign \req_done 1'0
- assign \req_done $45
+ assign \req_done $47
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
- switch { $53 }
+ switch { $55 }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
case 1'1
assign \req_done 1'1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:221"
wire width 1 \reset
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
- wire width 1 $55
+ wire width 1 $57
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
- cell $or $56
+ cell $or $58
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \req_done
connect \B \go_die_i
- connect \Y $55
+ connect \Y $57
end
process $group_11
assign \reset 1'0
- assign \reset $55
+ assign \reset $57
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222"
wire width 1 \rst_r
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226"
- wire width 1 $57
+ wire width 1 $59
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226"
- cell $or $58
+ cell $or $60
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \issue_i
connect \B \go_die_i
- connect \Y $57
+ connect \Y $59
end
process $group_12
assign \rst_r 1'0
- assign \rst_r $57
+ assign \rst_r $59
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:223"
wire width 5 \reset_w
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227"
- wire width 5 $59
+ wire width 5 $61
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227"
- cell $or $60
+ cell $or $62
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A \wr__go
connect \B { \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i }
- connect \Y $59
+ connect \Y $61
end
process $group_13
assign \reset_w 5'00000
- assign \reset_w $59
+ assign \reset_w $61
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:224"
wire width 4 \reset_r
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:228"
- wire width 4 $61
+ wire width 4 $63
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:228"
- cell $or $62
+ cell $or $64
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \rd__go
connect \B { \go_die_i \go_die_i \go_die_i \go_die_i }
- connect \Y $61
+ connect \Y $63
end
process $group_14
assign \reset_r 4'0000
- assign \reset_r $61
+ assign \reset_r $63
sync init
end
process $group_15
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232"
- wire width 1 $63
+ wire width 1 $65
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232"
- cell $and $64
+ cell $and $66
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \alu_alu0_n_valid_o
connect \B \busy_o
- connect \Y $63
+ connect \Y $65
end
process $group_16
assign \rok_l_r_rdok$next \rok_l_r_rdok
- assign \rok_l_r_rdok$next $63
+ assign \rok_l_r_rdok$next $65
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
update \src_l_r_src \src_l_r_src$next
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:247"
- wire width 5 $65
+ wire width 5 $67
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:247"
- cell $and $66
+ cell $and $68
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A \alu_pulsem
connect \B \wrmask
- connect \Y $65
+ connect \Y $67
end
process $group_23
assign \req_l_s_req 5'00000
- assign \req_l_s_req $65
+ assign \req_l_s_req $67
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:248"
- wire width 5 $67
+ wire width 5 $69
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:248"
- cell $or $68
+ cell $or $70
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A \reset_w
connect \B \prev_wr_go
- connect \Y $67
+ connect \Y $69
end
process $group_24
assign \req_l_r_req 5'11111
- assign \req_l_r_req $67
+ assign \req_l_r_req $69
sync init
end
- attribute \enum_base_type "InternalOp"
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 7 \oper_r__insn_type
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00100000000 "MUL"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 11 \oper_r__fn_unit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 64 \oper_r__imm_data__imm
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \oper_r__imm_data__imm_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 \oper_r__lk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \oper_r__rc__rc
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \oper_r__rc__rc_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \oper_r__oe__oe
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \oper_r__oe__oe_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \oper_r__invert_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \oper_r__zero_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \oper_r__invert_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 3 \oper_r__write_cr__data
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 \oper_r__write_cr__ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \oper_r__write_cr0
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 2 \oper_r__input_carry
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \oper_r__output_carry
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 \oper_r__input_cr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 \oper_r__output_cr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \oper_r__is_32bit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \oper_r__is_signed
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 4 \oper_r__data_len
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 32 \oper_r__insn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 \oper_r__byte_reverse
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 \oper_r__sign_extend
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
wire width 7 \oper_l__insn_type
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
wire width 1 \oper_l__imm_data__imm_ok$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
- wire width 1 \oper_l__lk
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
- wire width 1 \oper_l__lk$next
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
wire width 1 \oper_l__rc__rc
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
wire width 1 \oper_l__rc__rc$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
wire width 1 \oper_l__invert_out$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
- wire width 3 \oper_l__write_cr__data
+ wire width 1 \oper_l__write_cr0
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
- wire width 3 \oper_l__write_cr__data$next
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
- wire width 1 \oper_l__write_cr__ok
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
- wire width 1 \oper_l__write_cr__ok$next
+ wire width 1 \oper_l__write_cr0$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
wire width 2 \oper_l__input_carry
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
wire width 1 \oper_l__output_carry$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
- wire width 1 \oper_l__input_cr
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
- wire width 1 \oper_l__input_cr$next
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
- wire width 1 \oper_l__output_cr
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
- wire width 1 \oper_l__output_cr$next
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
wire width 1 \oper_l__is_32bit
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
wire width 1 \oper_l__is_32bit$next
wire width 32 \oper_l__insn
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
wire width 32 \oper_l__insn$next
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
- wire width 1 \oper_l__byte_reverse
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
- wire width 1 \oper_l__byte_reverse$next
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
- wire width 1 \oper_l__sign_extend
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
- wire width 1 \oper_l__sign_extend$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
- wire width 140 $69
+ wire width 132 $71
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
- cell $mux $70
- parameter \WIDTH 140
- connect \A { \oper_l__sign_extend \oper_l__byte_reverse \oper_l__insn \oper_l__data_len \oper_l__is_signed \oper_l__is_32bit \oper_l__output_cr \oper_l__input_cr \oper_l__output_carry \oper_l__input_carry { \oper_l__write_cr__ok \oper_l__write_cr__data } \oper_l__invert_out \oper_l__zero_a \oper_l__invert_a { \oper_l__oe__oe_ok \oper_l__oe__oe } { \oper_l__rc__rc_ok \oper_l__rc__rc } \oper_l__lk { \oper_l__imm_data__imm_ok \oper_l__imm_data__imm } \oper_l__fn_unit \oper_l__insn_type }
- connect \B { \oper_i__sign_extend \oper_i__byte_reverse \oper_i__insn \oper_i__data_len \oper_i__is_signed \oper_i__is_32bit \oper_i__output_cr \oper_i__input_cr \oper_i__output_carry \oper_i__input_carry { \oper_i__write_cr__ok \oper_i__write_cr__data } \oper_i__invert_out \oper_i__zero_a \oper_i__invert_a { \oper_i__oe__oe_ok \oper_i__oe__oe } { \oper_i__rc__rc_ok \oper_i__rc__rc } \oper_i__lk { \oper_i__imm_data__imm_ok \oper_i__imm_data__imm } \oper_i__fn_unit \oper_i__insn_type }
+ cell $mux $72
+ parameter \WIDTH 132
+ connect \A { \oper_l__insn \oper_l__data_len \oper_l__is_signed \oper_l__is_32bit \oper_l__output_carry \oper_l__input_carry \oper_l__write_cr0 \oper_l__invert_out \oper_l__zero_a \oper_l__invert_a { \oper_l__oe__oe_ok \oper_l__oe__oe } { \oper_l__rc__rc_ok \oper_l__rc__rc } { \oper_l__imm_data__imm_ok \oper_l__imm_data__imm } \oper_l__fn_unit \oper_l__insn_type }
+ connect \B { \oper_i__insn \oper_i__data_len \oper_i__is_signed \oper_i__is_32bit \oper_i__output_carry \oper_i__input_carry \oper_i__write_cr0 \oper_i__invert_out \oper_i__zero_a \oper_i__invert_a { \oper_i__oe__oe_ok \oper_i__oe__oe } { \oper_i__rc__rc_ok \oper_i__rc__rc } { \oper_i__imm_data__imm_ok \oper_i__imm_data__imm } \oper_i__fn_unit \oper_i__insn_type }
connect \S \issue_i
- connect \Y $69
+ connect \Y $71
end
process $group_25
assign \oper_r__insn_type 7'0000000
assign \oper_r__fn_unit 11'00000000000
assign \oper_r__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
assign \oper_r__imm_data__imm_ok 1'0
- assign \oper_r__lk 1'0
assign \oper_r__rc__rc 1'0
assign \oper_r__rc__rc_ok 1'0
assign \oper_r__oe__oe 1'0
assign \oper_r__invert_a 1'0
assign \oper_r__zero_a 1'0
assign \oper_r__invert_out 1'0
- assign \oper_r__write_cr__data 3'000
- assign \oper_r__write_cr__ok 1'0
+ assign \oper_r__write_cr0 1'0
assign \oper_r__input_carry 2'00
assign \oper_r__output_carry 1'0
- assign \oper_r__input_cr 1'0
- assign \oper_r__output_cr 1'0
assign \oper_r__is_32bit 1'0
assign \oper_r__is_signed 1'0
assign \oper_r__data_len 4'0000
assign \oper_r__insn 32'00000000000000000000000000000000
- assign \oper_r__byte_reverse 1'0
- assign \oper_r__sign_extend 1'0
- assign { \oper_r__sign_extend \oper_r__byte_reverse \oper_r__insn \oper_r__data_len \oper_r__is_signed \oper_r__is_32bit \oper_r__output_cr \oper_r__input_cr \oper_r__output_carry \oper_r__input_carry { \oper_r__write_cr__ok \oper_r__write_cr__data } \oper_r__invert_out \oper_r__zero_a \oper_r__invert_a { \oper_r__oe__oe_ok \oper_r__oe__oe } { \oper_r__rc__rc_ok \oper_r__rc__rc } \oper_r__lk { \oper_r__imm_data__imm_ok \oper_r__imm_data__imm } \oper_r__fn_unit \oper_r__insn_type } $69
+ assign { \oper_r__insn \oper_r__data_len \oper_r__is_signed \oper_r__is_32bit \oper_r__output_carry \oper_r__input_carry \oper_r__write_cr0 \oper_r__invert_out \oper_r__zero_a \oper_r__invert_a { \oper_r__oe__oe_ok \oper_r__oe__oe } { \oper_r__rc__rc_ok \oper_r__rc__rc } { \oper_r__imm_data__imm_ok \oper_r__imm_data__imm } \oper_r__fn_unit \oper_r__insn_type } $71
sync init
end
- process $group_49
+ process $group_43
assign \oper_l__insn_type$next \oper_l__insn_type
assign \oper_l__fn_unit$next \oper_l__fn_unit
assign \oper_l__imm_data__imm$next \oper_l__imm_data__imm
assign \oper_l__imm_data__imm_ok$next \oper_l__imm_data__imm_ok
- assign \oper_l__lk$next \oper_l__lk
assign \oper_l__rc__rc$next \oper_l__rc__rc
assign \oper_l__rc__rc_ok$next \oper_l__rc__rc_ok
assign \oper_l__oe__oe$next \oper_l__oe__oe
assign \oper_l__invert_a$next \oper_l__invert_a
assign \oper_l__zero_a$next \oper_l__zero_a
assign \oper_l__invert_out$next \oper_l__invert_out
- assign \oper_l__write_cr__data$next \oper_l__write_cr__data
- assign \oper_l__write_cr__ok$next \oper_l__write_cr__ok
+ assign \oper_l__write_cr0$next \oper_l__write_cr0
assign \oper_l__input_carry$next \oper_l__input_carry
assign \oper_l__output_carry$next \oper_l__output_carry
- assign \oper_l__input_cr$next \oper_l__input_cr
- assign \oper_l__output_cr$next \oper_l__output_cr
assign \oper_l__is_32bit$next \oper_l__is_32bit
assign \oper_l__is_signed$next \oper_l__is_signed
assign \oper_l__data_len$next \oper_l__data_len
assign \oper_l__insn$next \oper_l__insn
- assign \oper_l__byte_reverse$next \oper_l__byte_reverse
- assign \oper_l__sign_extend$next \oper_l__sign_extend
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
switch { \issue_i }
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
case 1'1
- assign { \oper_l__sign_extend$next \oper_l__byte_reverse$next \oper_l__insn$next \oper_l__data_len$next \oper_l__is_signed$next \oper_l__is_32bit$next \oper_l__output_cr$next \oper_l__input_cr$next \oper_l__output_carry$next \oper_l__input_carry$next { \oper_l__write_cr__ok$next \oper_l__write_cr__data$next } \oper_l__invert_out$next \oper_l__zero_a$next \oper_l__invert_a$next { \oper_l__oe__oe_ok$next \oper_l__oe__oe$next } { \oper_l__rc__rc_ok$next \oper_l__rc__rc$next } \oper_l__lk$next { \oper_l__imm_data__imm_ok$next \oper_l__imm_data__imm$next } \oper_l__fn_unit$next \oper_l__insn_type$next } { \oper_i__sign_extend \oper_i__byte_reverse \oper_i__insn \oper_i__data_len \oper_i__is_signed \oper_i__is_32bit \oper_i__output_cr \oper_i__input_cr \oper_i__output_carry \oper_i__input_carry { \oper_i__write_cr__ok \oper_i__write_cr__data } \oper_i__invert_out \oper_i__zero_a \oper_i__invert_a { \oper_i__oe__oe_ok \oper_i__oe__oe } { \oper_i__rc__rc_ok \oper_i__rc__rc } \oper_i__lk { \oper_i__imm_data__imm_ok \oper_i__imm_data__imm } \oper_i__fn_unit \oper_i__insn_type }
+ assign { \oper_l__insn$next \oper_l__data_len$next \oper_l__is_signed$next \oper_l__is_32bit$next \oper_l__output_carry$next \oper_l__input_carry$next \oper_l__write_cr0$next \oper_l__invert_out$next \oper_l__zero_a$next \oper_l__invert_a$next { \oper_l__oe__oe_ok$next \oper_l__oe__oe$next } { \oper_l__rc__rc_ok$next \oper_l__rc__rc$next } { \oper_l__imm_data__imm_ok$next \oper_l__imm_data__imm$next } \oper_l__fn_unit$next \oper_l__insn_type$next } { \oper_i__insn \oper_i__data_len \oper_i__is_signed \oper_i__is_32bit \oper_i__output_carry \oper_i__input_carry \oper_i__write_cr0 \oper_i__invert_out \oper_i__zero_a \oper_i__invert_a { \oper_i__oe__oe_ok \oper_i__oe__oe } { \oper_i__rc__rc_ok \oper_i__rc__rc } { \oper_i__imm_data__imm_ok \oper_i__imm_data__imm } \oper_i__fn_unit \oper_i__insn_type }
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
assign \oper_l__rc__rc_ok$next 1'0
assign \oper_l__oe__oe$next 1'0
assign \oper_l__oe__oe_ok$next 1'0
- assign \oper_l__write_cr__data$next 3'000
- assign \oper_l__write_cr__ok$next 1'0
- assign \oper_l__insn$next 32'00000000000000000000000000000000
end
sync init
update \oper_l__insn_type 7'0000000
update \oper_l__fn_unit 11'00000000000
update \oper_l__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
update \oper_l__imm_data__imm_ok 1'0
- update \oper_l__lk 1'0
update \oper_l__rc__rc 1'0
update \oper_l__rc__rc_ok 1'0
update \oper_l__oe__oe 1'0
update \oper_l__invert_a 1'0
update \oper_l__zero_a 1'0
update \oper_l__invert_out 1'0
- update \oper_l__write_cr__data 3'000
- update \oper_l__write_cr__ok 1'0
+ update \oper_l__write_cr0 1'0
update \oper_l__input_carry 2'00
update \oper_l__output_carry 1'0
- update \oper_l__input_cr 1'0
- update \oper_l__output_cr 1'0
update \oper_l__is_32bit 1'0
update \oper_l__is_signed 1'0
update \oper_l__data_len 4'0000
update \oper_l__insn 32'00000000000000000000000000000000
- update \oper_l__byte_reverse 1'0
- update \oper_l__sign_extend 1'0
sync posedge \clk
update \oper_l__insn_type \oper_l__insn_type$next
update \oper_l__fn_unit \oper_l__fn_unit$next
update \oper_l__imm_data__imm \oper_l__imm_data__imm$next
update \oper_l__imm_data__imm_ok \oper_l__imm_data__imm_ok$next
- update \oper_l__lk \oper_l__lk$next
update \oper_l__rc__rc \oper_l__rc__rc$next
update \oper_l__rc__rc_ok \oper_l__rc__rc_ok$next
update \oper_l__oe__oe \oper_l__oe__oe$next
update \oper_l__invert_a \oper_l__invert_a$next
update \oper_l__zero_a \oper_l__zero_a$next
update \oper_l__invert_out \oper_l__invert_out$next
- update \oper_l__write_cr__data \oper_l__write_cr__data$next
- update \oper_l__write_cr__ok \oper_l__write_cr__ok$next
+ update \oper_l__write_cr0 \oper_l__write_cr0$next
update \oper_l__input_carry \oper_l__input_carry$next
update \oper_l__output_carry \oper_l__output_carry$next
- update \oper_l__input_cr \oper_l__input_cr$next
- update \oper_l__output_cr \oper_l__output_cr$next
update \oper_l__is_32bit \oper_l__is_32bit$next
update \oper_l__is_signed \oper_l__is_signed$next
update \oper_l__data_len \oper_l__data_len$next
update \oper_l__insn \oper_l__insn$next
- update \oper_l__byte_reverse \oper_l__byte_reverse$next
- update \oper_l__sign_extend \oper_l__sign_extend$next
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262"
wire width 64 \data_r0__o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
wire width 1 \data_r0_l__o_ok$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
- wire width 65 $71
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:730"
- wire width 1 $72
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:730"
- cell $reduce_bool $73
+ wire width 65 $73
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744"
+ wire width 1 $74
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744"
+ cell $reduce_bool $75
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \Y_WIDTH 1
connect \A \alu_pulsem
- connect \Y $72
+ connect \Y $74
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
- cell $mux $74
+ cell $mux $76
parameter \WIDTH 65
connect \A { \data_r0_l__o_ok \data_r0_l__o }
- connect \B { \o_ok \o }
- connect \S $72
- connect \Y $71
+ connect \B { \o_ok \alu_alu0_o }
+ connect \S $74
+ connect \Y $73
end
- process $group_73
+ process $group_61
assign \data_r0__o 64'0000000000000000000000000000000000000000000000000000000000000000
assign \data_r0__o_ok 1'0
- assign { \data_r0__o_ok \data_r0__o } $71
+ assign { \data_r0__o_ok \data_r0__o } $73
sync init
end
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
- wire width 1 $75
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
- cell $reduce_bool $76
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
+ wire width 1 $77
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
+ cell $reduce_bool $78
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \Y_WIDTH 1
connect \A \alu_pulsem
- connect \Y $75
+ connect \Y $77
end
- process $group_75
+ process $group_63
assign \data_r0_l__o$next \data_r0_l__o
assign \data_r0_l__o_ok$next \data_r0_l__o_ok
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
- switch { $75 }
+ switch { $77 }
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
case 1'1
- assign { \data_r0_l__o_ok$next \data_r0_l__o$next } { \o_ok \o }
+ assign { \data_r0_l__o_ok$next \data_r0_l__o$next } { \o_ok \alu_alu0_o }
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
wire width 1 \data_r1_l__cr_a_ok$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
- wire width 5 $77
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:730"
- wire width 1 $78
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:730"
- cell $reduce_bool $79
+ wire width 5 $79
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744"
+ wire width 1 $80
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744"
+ cell $reduce_bool $81
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \Y_WIDTH 1
connect \A \alu_pulsem
- connect \Y $78
+ connect \Y $80
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
- cell $mux $80
+ cell $mux $82
parameter \WIDTH 5
connect \A { \data_r1_l__cr_a_ok \data_r1_l__cr_a }
- connect \B { \cr_a_ok \cr_a }
- connect \S $78
- connect \Y $77
+ connect \B { \cr_a_ok \alu_alu0_cr_a }
+ connect \S $80
+ connect \Y $79
end
- process $group_77
+ process $group_65
assign \data_r1__cr_a 4'0000
assign \data_r1__cr_a_ok 1'0
- assign { \data_r1__cr_a_ok \data_r1__cr_a } $77
+ assign { \data_r1__cr_a_ok \data_r1__cr_a } $79
sync init
end
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
- wire width 1 $81
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
- cell $reduce_bool $82
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
+ wire width 1 $83
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
+ cell $reduce_bool $84
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \Y_WIDTH 1
connect \A \alu_pulsem
- connect \Y $81
+ connect \Y $83
end
- process $group_79
+ process $group_67
assign \data_r1_l__cr_a$next \data_r1_l__cr_a
assign \data_r1_l__cr_a_ok$next \data_r1_l__cr_a_ok
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
- switch { $81 }
+ switch { $83 }
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
case 1'1
- assign { \data_r1_l__cr_a_ok$next \data_r1_l__cr_a$next } { \cr_a_ok \cr_a }
+ assign { \data_r1_l__cr_a_ok$next \data_r1_l__cr_a$next } { \cr_a_ok \alu_alu0_cr_a }
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
wire width 1 \data_r2_l__xer_ca_ok$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
- wire width 3 $83
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:730"
- wire width 1 $84
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:730"
- cell $reduce_bool $85
+ wire width 3 $85
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744"
+ wire width 1 $86
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744"
+ cell $reduce_bool $87
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \Y_WIDTH 1
connect \A \alu_pulsem
- connect \Y $84
+ connect \Y $86
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
- cell $mux $86
+ cell $mux $88
parameter \WIDTH 3
connect \A { \data_r2_l__xer_ca_ok \data_r2_l__xer_ca }
- connect \B { \xer_ca_ok \xer_ca }
- connect \S $84
- connect \Y $83
+ connect \B { \xer_ca_ok \alu_alu0_xer_ca }
+ connect \S $86
+ connect \Y $85
end
- process $group_81
+ process $group_69
assign \data_r2__xer_ca 2'00
assign \data_r2__xer_ca_ok 1'0
- assign { \data_r2__xer_ca_ok \data_r2__xer_ca } $83
+ assign { \data_r2__xer_ca_ok \data_r2__xer_ca } $85
sync init
end
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
- wire width 1 $87
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
- cell $reduce_bool $88
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
+ wire width 1 $89
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
+ cell $reduce_bool $90
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \Y_WIDTH 1
connect \A \alu_pulsem
- connect \Y $87
+ connect \Y $89
end
- process $group_83
+ process $group_71
assign \data_r2_l__xer_ca$next \data_r2_l__xer_ca
assign \data_r2_l__xer_ca_ok$next \data_r2_l__xer_ca_ok
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
- switch { $87 }
+ switch { $89 }
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
case 1'1
- assign { \data_r2_l__xer_ca_ok$next \data_r2_l__xer_ca$next } { \xer_ca_ok \xer_ca }
+ assign { \data_r2_l__xer_ca_ok$next \data_r2_l__xer_ca$next } { \xer_ca_ok \alu_alu0_xer_ca }
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
wire width 1 \data_r3_l__xer_ov_ok$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
- wire width 3 $89
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:730"
- wire width 1 $90
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:730"
- cell $reduce_bool $91
+ wire width 3 $91
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744"
+ wire width 1 $92
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744"
+ cell $reduce_bool $93
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \Y_WIDTH 1
connect \A \alu_pulsem
- connect \Y $90
+ connect \Y $92
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
- cell $mux $92
+ cell $mux $94
parameter \WIDTH 3
connect \A { \data_r3_l__xer_ov_ok \data_r3_l__xer_ov }
- connect \B { \xer_ov_ok \xer_ov }
- connect \S $90
- connect \Y $89
+ connect \B { \xer_ov_ok \alu_alu0_xer_ov }
+ connect \S $92
+ connect \Y $91
end
- process $group_85
+ process $group_73
assign \data_r3__xer_ov 2'00
assign \data_r3__xer_ov_ok 1'0
- assign { \data_r3__xer_ov_ok \data_r3__xer_ov } $89
+ assign { \data_r3__xer_ov_ok \data_r3__xer_ov } $91
sync init
end
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
- wire width 1 $93
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
- cell $reduce_bool $94
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
+ wire width 1 $95
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
+ cell $reduce_bool $96
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \Y_WIDTH 1
connect \A \alu_pulsem
- connect \Y $93
+ connect \Y $95
end
- process $group_87
+ process $group_75
assign \data_r3_l__xer_ov$next \data_r3_l__xer_ov
assign \data_r3_l__xer_ov_ok$next \data_r3_l__xer_ov_ok
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
- switch { $93 }
+ switch { $95 }
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
case 1'1
- assign { \data_r3_l__xer_ov_ok$next \data_r3_l__xer_ov$next } { \xer_ov_ok \xer_ov }
+ assign { \data_r3_l__xer_ov_ok$next \data_r3_l__xer_ov$next } { \xer_ov_ok \alu_alu0_xer_ov }
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
wire width 1 \data_r4_l__xer_so_ok$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
- wire width 2 $95
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:730"
- wire width 1 $96
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:730"
- cell $reduce_bool $97
+ wire width 2 $97
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744"
+ wire width 1 $98
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744"
+ cell $reduce_bool $99
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \Y_WIDTH 1
connect \A \alu_pulsem
- connect \Y $96
+ connect \Y $98
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
- cell $mux $98
+ cell $mux $100
parameter \WIDTH 2
connect \A { \data_r4_l__xer_so_ok \data_r4_l__xer_so }
- connect \B { \xer_so_ok \xer_so }
- connect \S $96
- connect \Y $95
+ connect \B { \xer_so_ok \alu_alu0_xer_so }
+ connect \S $98
+ connect \Y $97
end
- process $group_89
+ process $group_77
assign \data_r4__xer_so 1'0
assign \data_r4__xer_so_ok 1'0
- assign { \data_r4__xer_so_ok \data_r4__xer_so } $95
+ assign { \data_r4__xer_so_ok \data_r4__xer_so } $97
sync init
end
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
- wire width 1 $99
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
- cell $reduce_bool $100
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
+ wire width 1 $101
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
+ cell $reduce_bool $102
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \Y_WIDTH 1
connect \A \alu_pulsem
- connect \Y $99
+ connect \Y $101
end
- process $group_91
+ process $group_79
assign \data_r4_l__xer_so$next \data_r4_l__xer_so
assign \data_r4_l__xer_so_ok$next \data_r4_l__xer_so_ok
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
- switch { $99 }
+ switch { $101 }
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
case 1'1
- assign { \data_r4_l__xer_so_ok$next \data_r4_l__xer_so$next } { \xer_so_ok \xer_so }
+ assign { \data_r4_l__xer_so_ok$next \data_r4_l__xer_so$next } { \xer_so_ok \alu_alu0_xer_so }
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
update \data_r4_l__xer_so \data_r4_l__xer_so$next
update \data_r4_l__xer_so_ok \data_r4_l__xer_so_ok$next
end
- process $group_93
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+ wire width 1 $103
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+ cell $and $104
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \data_r0__o_ok
+ connect \B \busy_o
+ connect \Y $103
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+ wire width 1 $105
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+ cell $and $106
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \data_r1__cr_a_ok
+ connect \B \busy_o
+ connect \Y $105
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+ wire width 1 $107
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+ cell $and $108
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \data_r2__xer_ca_ok
+ connect \B \busy_o
+ connect \Y $107
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+ wire width 1 $109
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+ cell $and $110
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \data_r3__xer_ov_ok
+ connect \B \busy_o
+ connect \Y $109
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+ wire width 1 $111
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+ cell $and $112
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \data_r4__xer_so_ok
+ connect \B \busy_o
+ connect \Y $111
+ end
+ process $group_81
assign \wrmask 5'00000
- assign \wrmask { \data_r4__xer_so_ok \data_r3__xer_ov_ok \data_r2__xer_ca_ok \data_r1__cr_a_ok \data_r0__o_ok }
+ assign \wrmask { $111 $109 $107 $105 $103 }
sync init
end
- process $group_94
+ process $group_82
assign \alu_alu0_op__insn_type 7'0000000
assign \alu_alu0_op__fn_unit 11'00000000000
assign \alu_alu0_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
assign \alu_alu0_op__imm_data__imm_ok 1'0
- assign \alu_alu0_op__lk 1'0
assign \alu_alu0_op__rc__rc 1'0
assign \alu_alu0_op__rc__rc_ok 1'0
assign \alu_alu0_op__oe__oe 1'0
assign \alu_alu0_op__invert_a 1'0
assign \alu_alu0_op__zero_a 1'0
assign \alu_alu0_op__invert_out 1'0
- assign \alu_alu0_op__write_cr__data 3'000
- assign \alu_alu0_op__write_cr__ok 1'0
+ assign \alu_alu0_op__write_cr0 1'0
assign \alu_alu0_op__input_carry 2'00
assign \alu_alu0_op__output_carry 1'0
- assign \alu_alu0_op__input_cr 1'0
- assign \alu_alu0_op__output_cr 1'0
assign \alu_alu0_op__is_32bit 1'0
assign \alu_alu0_op__is_signed 1'0
assign \alu_alu0_op__data_len 4'0000
assign \alu_alu0_op__insn 32'00000000000000000000000000000000
- assign \alu_alu0_op__byte_reverse 1'0
- assign \alu_alu0_op__sign_extend 1'0
- assign { \alu_alu0_op__sign_extend \alu_alu0_op__byte_reverse \alu_alu0_op__insn \alu_alu0_op__data_len \alu_alu0_op__is_signed \alu_alu0_op__is_32bit \alu_alu0_op__output_cr \alu_alu0_op__input_cr \alu_alu0_op__output_carry \alu_alu0_op__input_carry { \alu_alu0_op__write_cr__ok \alu_alu0_op__write_cr__data } \alu_alu0_op__invert_out \alu_alu0_op__zero_a \alu_alu0_op__invert_a { \alu_alu0_op__oe__oe_ok \alu_alu0_op__oe__oe } { \alu_alu0_op__rc__rc_ok \alu_alu0_op__rc__rc } \alu_alu0_op__lk { \alu_alu0_op__imm_data__imm_ok \alu_alu0_op__imm_data__imm } \alu_alu0_op__fn_unit \alu_alu0_op__insn_type } { \oper_r__sign_extend \oper_r__byte_reverse \oper_r__insn \oper_r__data_len \oper_r__is_signed \oper_r__is_32bit \oper_r__output_cr \oper_r__input_cr \oper_r__output_carry \oper_r__input_carry { \oper_r__write_cr__ok \oper_r__write_cr__data } \oper_r__invert_out \oper_r__zero_a \oper_r__invert_a { \oper_r__oe__oe_ok \oper_r__oe__oe } { \oper_r__rc__rc_ok \oper_r__rc__rc } \oper_r__lk { \oper_r__imm_data__imm_ok \oper_r__imm_data__imm } \oper_r__fn_unit \oper_r__insn_type }
+ assign { \alu_alu0_op__insn \alu_alu0_op__data_len \alu_alu0_op__is_signed \alu_alu0_op__is_32bit \alu_alu0_op__output_carry \alu_alu0_op__input_carry \alu_alu0_op__write_cr0 \alu_alu0_op__invert_out \alu_alu0_op__zero_a \alu_alu0_op__invert_a { \alu_alu0_op__oe__oe_ok \alu_alu0_op__oe__oe } { \alu_alu0_op__rc__rc_ok \alu_alu0_op__rc__rc } { \alu_alu0_op__imm_data__imm_ok \alu_alu0_op__imm_data__imm } \alu_alu0_op__fn_unit \alu_alu0_op__insn_type } { \oper_r__insn \oper_r__data_len \oper_r__is_signed \oper_r__is_32bit \oper_r__output_carry \oper_r__input_carry \oper_r__write_cr0 \oper_r__invert_out \oper_r__zero_a \oper_r__invert_a { \oper_r__oe__oe_ok \oper_r__oe__oe } { \oper_r__rc__rc_ok \oper_r__rc__rc } { \oper_r__imm_data__imm_ok \oper_r__imm_data__imm } \oper_r__fn_unit \oper_r__insn_type }
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:158"
wire width 1 \src_sel
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:159"
- wire width 1 $101
+ wire width 1 $113
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:159"
- cell $mux $102
+ cell $mux $114
parameter \WIDTH 1
connect \A \src_l_q_src [0]
connect \B \opc_l_q_opc
connect \S \oper_r__zero_a
- connect \Y $101
+ connect \Y $113
end
- process $group_118
+ process $group_100
assign \src_sel 1'0
- assign \src_sel $101
+ assign \src_sel $113
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:157"
wire width 64 \src_or_imm
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:160"
- wire width 64 $103
+ wire width 64 $115
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:160"
- cell $mux $104
+ cell $mux $116
parameter \WIDTH 64
connect \A \src1_i
connect \B 64'0000000000000000000000000000000000000000000000000000000000000000
connect \S \oper_r__zero_a
- connect \Y $103
+ connect \Y $115
end
- process $group_119
+ process $group_101
assign \src_or_imm 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \src_or_imm $103
+ assign \src_or_imm $115
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:158"
- wire width 1 \src_sel$105
+ wire width 1 \src_sel$117
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:159"
- wire width 1 $106
+ wire width 1 $118
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:159"
- cell $mux $107
+ cell $mux $119
parameter \WIDTH 1
connect \A \src_l_q_src [1]
connect \B \opc_l_q_opc
connect \S \oper_r__imm_data__imm_ok
- connect \Y $106
+ connect \Y $118
end
- process $group_120
- assign \src_sel$105 1'0
- assign \src_sel$105 $106
+ process $group_102
+ assign \src_sel$117 1'0
+ assign \src_sel$117 $118
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:157"
- wire width 64 \src_or_imm$108
+ wire width 64 \src_or_imm$120
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:160"
- wire width 64 $109
+ wire width 64 $121
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:160"
- cell $mux $110
+ cell $mux $122
parameter \WIDTH 64
connect \A \src2_i
connect \B \oper_r__imm_data__imm
connect \S \oper_r__imm_data__imm_ok
- connect \Y $109
+ connect \Y $121
end
- process $group_121
- assign \src_or_imm$108 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \src_or_imm$108 $109
+ process $group_103
+ assign \src_or_imm$120 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \src_or_imm$120 $121
sync init
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
wire width 64 \src_r0$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
- wire width 64 $111
+ wire width 64 $123
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
- cell $mux $112
+ cell $mux $124
parameter \WIDTH 64
connect \A \src_r0
connect \B \src_or_imm
connect \S \src_sel
- connect \Y $111
+ connect \Y $123
end
- process $group_122
+ process $group_104
assign \alu_alu0_ra 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \alu_alu0_ra $111
+ assign \alu_alu0_ra $123
sync init
end
- process $group_123
+ process $group_105
assign \src_r0$next \src_r0
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
switch { \src_sel }
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
wire width 64 \src_r1$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
- wire width 64 $113
+ wire width 64 $125
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
- cell $mux $114
+ cell $mux $126
parameter \WIDTH 64
connect \A \src_r1
- connect \B \src_or_imm$108
- connect \S \src_sel$105
- connect \Y $113
+ connect \B \src_or_imm$120
+ connect \S \src_sel$117
+ connect \Y $125
end
- process $group_124
+ process $group_106
assign \alu_alu0_rb 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \alu_alu0_rb $113
+ assign \alu_alu0_rb $125
sync init
end
- process $group_125
+ process $group_107
assign \src_r1$next \src_r1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
- switch { \src_sel$105 }
+ switch { \src_sel$117 }
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
case 1'1
- assign \src_r1$next \src_or_imm$108
+ assign \src_r1$next \src_or_imm$120
end
sync init
update \src_r1 64'0000000000000000000000000000000000000000000000000000000000000000
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
wire width 1 \src_r2$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
- wire width 1 $115
+ wire width 1 $127
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
- cell $mux $116
+ cell $mux $128
parameter \WIDTH 1
connect \A \src_r2
connect \B \src3_i
connect \S \src_l_q_src [2]
- connect \Y $115
+ connect \Y $127
end
- process $group_126
- assign \alu_alu0_xer_so 1'0
- assign \alu_alu0_xer_so $115
+ process $group_108
+ assign \alu_alu0_xer_so$1 1'0
+ assign \alu_alu0_xer_so$1 $127
sync init
end
- process $group_127
+ process $group_109
assign \src_r2$next \src_r2
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
switch { \src_l_q_src [2] }
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
wire width 2 \src_r3$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
- wire width 2 $117
+ wire width 2 $129
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
- cell $mux $118
+ cell $mux $130
parameter \WIDTH 2
connect \A \src_r3
connect \B \src4_i
connect \S \src_l_q_src [3]
- connect \Y $117
+ connect \Y $129
end
- process $group_128
- assign \alu_alu0_xer_ca 2'00
- assign \alu_alu0_xer_ca $117
+ process $group_110
+ assign \alu_alu0_xer_ca$2 2'00
+ assign \alu_alu0_xer_ca$2 $129
sync init
end
- process $group_129
+ process $group_111
assign \src_r3$next \src_r3
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
switch { \src_l_q_src [3] }
sync posedge \clk
update \src_r3 \src_r3$next
end
- process $group_130
+ process $group_112
assign \alu_alu0_p_valid_i 1'0
assign \alu_alu0_p_valid_i \alui_l_q_alui
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:321"
- wire width 1 $119
+ wire width 1 $131
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:321"
- cell $and $120
+ cell $and $132
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \alu_alu0_p_ready_o
connect \B \alui_l_q_alui
- connect \Y $119
+ connect \Y $131
end
- process $group_131
+ process $group_113
assign \alui_l_r_alui$next \alui_l_r_alui
- assign \alui_l_r_alui$next $119
+ assign \alui_l_r_alui$next $131
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
sync posedge \clk
update \alui_l_r_alui \alui_l_r_alui$next
end
- process $group_132
+ process $group_114
assign \alui_l_s_alui 1'0
assign \alui_l_s_alui \all_rd_pulse
sync init
end
- process $group_133
+ process $group_115
assign \alu_alu0_n_ready_i 1'0
assign \alu_alu0_n_ready_i \alu_l_q_alu
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:328"
- wire width 1 $121
+ wire width 1 $133
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:328"
- cell $and $122
+ cell $and $134
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \alu_alu0_n_valid_o
connect \B \alu_l_q_alu
- connect \Y $121
+ connect \Y $133
end
- process $group_134
+ process $group_116
assign \alu_l_r_alu$next \alu_l_r_alu
- assign \alu_l_r_alu$next $121
+ assign \alu_l_r_alu$next $133
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
sync posedge \clk
update \alu_l_r_alu \alu_l_r_alu$next
end
- process $group_135
+ process $group_117
assign \alu_l_s_alu 1'0
assign \alu_l_s_alu \all_rd_pulse
sync init
end
- process $group_136
+ process $group_118
assign \busy_o 1'0
assign \busy_o \opc_l_q_opc
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341"
- wire width 4 $123
+ wire width 4 $135
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341"
- cell $and $124
+ cell $and $136
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \src_l_q_src
connect \B { \busy_o \busy_o \busy_o \busy_o }
- connect \Y $123
+ connect \Y $135
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:164"
- wire width 1 $125
+ wire width 1 $137
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:164"
- cell $not $126
+ cell $not $138
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \oper_r__zero_a
- connect \Y $125
+ connect \Y $137
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:164"
- wire width 1 $127
+ wire width 1 $139
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:164"
- cell $not $128
+ cell $not $140
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \oper_r__imm_data__imm_ok
- connect \Y $127
+ connect \Y $139
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341"
- wire width 4 $129
+ wire width 4 $141
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341"
- cell $and $130
+ cell $and $142
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 4
- connect \A $123
- connect \B { 1'1 1'1 $127 $125 }
- connect \Y $129
+ connect \A $135
+ connect \B { 1'1 1'1 $139 $137 }
+ connect \Y $141
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341"
- wire width 4 $131
+ wire width 4 $143
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341"
- cell $not $132
+ cell $not $144
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 4
connect \A \rdmaskn
- connect \Y $131
+ connect \Y $143
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341"
- wire width 4 $133
+ wire width 4 $145
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341"
- cell $and $134
+ cell $and $146
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 4
- connect \A $129
- connect \B $131
- connect \Y $133
+ connect \A $141
+ connect \B $143
+ connect \Y $145
end
- process $group_137
+ process $group_119
assign \rd__rel 4'0000
- assign \rd__rel $133
+ assign \rd__rel $145
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
- wire width 1 $135
+ wire width 1 $147
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
- cell $and $136
+ cell $and $148
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \busy_o
connect \B \shadown_i
- connect \Y $135
+ connect \Y $147
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
- wire width 1 $137
+ wire width 1 $149
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
- cell $and $138
+ cell $and $150
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \busy_o
connect \B \shadown_i
- connect \Y $137
+ connect \Y $149
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
- wire width 1 $139
+ wire width 1 $151
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
- cell $and $140
+ cell $and $152
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \busy_o
connect \B \shadown_i
- connect \Y $139
+ connect \Y $151
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
- wire width 1 $141
+ wire width 1 $153
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
- cell $and $142
+ cell $and $154
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \busy_o
connect \B \shadown_i
- connect \Y $141
+ connect \Y $153
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
- wire width 1 $143
+ wire width 1 $155
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
- cell $and $144
+ cell $and $156
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \busy_o
connect \B \shadown_i
- connect \Y $143
+ connect \Y $155
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:345"
- wire width 5 $145
+ wire width 5 $157
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:345"
- cell $and $146
+ cell $and $158
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \B_WIDTH 5
parameter \Y_WIDTH 5
connect \A \req_l_q_req
- connect \B { $135 $137 $139 $141 $143 }
- connect \Y $145
+ connect \B { $147 $149 $151 $153 $155 }
+ connect \Y $157
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:345"
- wire width 5 $147
+ wire width 5 $159
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:345"
- cell $and $148
+ cell $and $160
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \B_WIDTH 5
parameter \Y_WIDTH 5
- connect \A $145
+ connect \A $157
connect \B \wrmask
- connect \Y $147
+ connect \Y $159
end
- process $group_138
+ process $group_120
assign \wr__rel 5'00000
- assign \wr__rel $147
+ assign \wr__rel $159
sync init
end
- process $group_139
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+ wire width 1 $161
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+ cell $and $162
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \wr__go [0]
+ connect \B \busy_o
+ connect \Y $161
+ end
+ process $group_121
assign \dest1_o 64'0000000000000000000000000000000000000000000000000000000000000000
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
- switch { \wr__go [0] }
+ switch { $161 }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
case 1'1
assign \dest1_o { \data_r0__o_ok \data_r0__o } [63:0]
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
- wire width 4 \dest2_o
- process $group_140
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+ wire width 1 $163
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+ cell $and $164
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \wr__go [1]
+ connect \B \busy_o
+ connect \Y $163
+ end
+ process $group_122
assign \dest2_o 4'0000
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
- switch { \wr__go [1] }
+ switch { $163 }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
case 1'1
assign \dest2_o { \data_r1__cr_a_ok \data_r1__cr_a } [3:0]
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
- wire width 2 \dest3_o
- process $group_141
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+ wire width 1 $165
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+ cell $and $166
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \wr__go [2]
+ connect \B \busy_o
+ connect \Y $165
+ end
+ process $group_123
assign \dest3_o 2'00
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
- switch { \wr__go [2] }
+ switch { $165 }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
case 1'1
assign \dest3_o { \data_r2__xer_ca_ok \data_r2__xer_ca } [1:0]
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
- wire width 2 \dest4_o
- process $group_142
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+ wire width 1 $167
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+ cell $and $168
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \wr__go [3]
+ connect \B \busy_o
+ connect \Y $167
+ end
+ process $group_124
assign \dest4_o 2'00
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
- switch { \wr__go [3] }
+ switch { $167 }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
case 1'1
assign \dest4_o { \data_r3__xer_ov_ok \data_r3__xer_ov } [1:0]
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
- wire width 1 \dest5_o
- process $group_143
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+ wire width 1 $169
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+ cell $and $170
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \wr__go [4]
+ connect \B \busy_o
+ connect \Y $169
+ end
+ process $group_125
assign \dest5_o 1'0
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
- switch { \wr__go [4] }
+ switch { $169 }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
case 1'1
assign \dest5_o { \data_r4__xer_so_ok \data_r4__xer_so } [0]
attribute \generator "nMigen"
attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.alu_cr0.p"
module \p$4
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153"
wire width 1 input 0 \p_valid_i
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154"
wire width 1 input 1 \p_ready_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:156"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158"
wire width 1 \trigger
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:203"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205"
wire width 1 $1
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:203"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205"
cell $and $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
attribute \generator "nMigen"
attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.alu_cr0.n"
module \n$5
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
wire width 1 input 0 \n_valid_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
wire width 1 input 1 \n_ready_i
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:249"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251"
wire width 1 \trigger
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:295"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:297"
wire width 1 $1
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:295"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:297"
cell $and $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
attribute \generator "nMigen"
attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.alu_cr0.pipe.p"
module \p$7
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153"
wire width 1 input 0 \p_valid_i
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154"
wire width 1 input 1 \p_ready_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:156"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158"
wire width 1 \trigger
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:203"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205"
wire width 1 $1
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:203"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205"
cell $and $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
attribute \generator "nMigen"
attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.alu_cr0.pipe.n"
module \n$8
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
wire width 1 input 0 \n_valid_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
wire width 1 input 1 \n_ready_i
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:249"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251"
wire width 1 \trigger
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:295"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:297"
wire width 1 $1
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:295"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:297"
cell $and $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
attribute \generator "nMigen"
attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.alu_cr0.pipe.main"
module \main$9
- attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
wire width 2 input 0 \muxid
- attribute \enum_base_type "InternalOp"
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 7 input 1 \op__insn_type
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00100000000 "MUL"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 11 input 2 \op__fn_unit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 32 input 3 \op__insn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 input 4 \op__read_cr_whole
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 input 5 \op__write_cr_whole
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
wire width 64 input 6 \ra
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
wire width 64 input 7 \rb
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
wire width 32 input 8 \full_cr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
wire width 4 input 9 \cr_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
wire width 4 input 10 \cr_b
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
wire width 4 input 11 \cr_c
- attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
wire width 2 output 12 \muxid$1
- attribute \enum_base_type "InternalOp"
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 7 output 13 \op__insn_type$2
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00100000000 "MUL"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 11 output 14 \op__fn_unit$3
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 32 output 15 \op__insn$4
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 output 16 \op__read_cr_whole$5
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 output 17 \op__write_cr_whole$6
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 64 output 18 \o
assign \mask { { { \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] } [7] { \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] } [7] { \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] } [7] { \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] } [7] } { { \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] } [6] { \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] } [6] { \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] } [6] { \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] } [6] } { { \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] } [5] { \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] } [5] { \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] } [5] { \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] } [5] } { { \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] } [4] { \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] } [4] { \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] } [4] { \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] } [4] } { { \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] } [3] { \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] } [3] { \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] } [3] { \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] } [3] } { { \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] } [2] { \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] } [2] { \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] } [2] { \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] } [2] } { { \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] } [1] { \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] } [1] { \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] } [1] { \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] } [1] } { { \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] } [0] { \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] } [0] { \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] } [0] { \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] } [0] } }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
wire width 5 $9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
cell $pos $10
parameter \A_SIGNED 0
parameter \A_WIDTH 4
connect \A $35
connect \Y $34
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
wire width 64 $38
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
cell $pos $39
parameter \A_SIGNED 0
parameter \A_WIDTH 32
wire width 1 input 0 \rst
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153"
wire width 1 input 2 \p_valid_i
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154"
wire width 1 output 3 \p_ready_o
- attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
wire width 2 input 4 \muxid
- attribute \enum_base_type "InternalOp"
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 7 input 5 \op__insn_type
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00100000000 "MUL"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 11 input 6 \op__fn_unit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 32 input 7 \op__insn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 input 8 \op__read_cr_whole
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 input 9 \op__write_cr_whole
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
wire width 64 input 10 \ra
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
wire width 64 input 11 \rb
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
wire width 32 input 12 \full_cr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
wire width 4 input 13 \cr_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
wire width 4 input 14 \cr_b
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
wire width 4 input 15 \cr_c
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
wire width 1 output 16 \n_valid_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
wire width 1 input 17 \n_ready_i
- attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
wire width 2 output 18 \muxid$1
- attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
wire width 2 \muxid$1$next
- attribute \enum_base_type "InternalOp"
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 7 output 19 \op__insn_type$2
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 7 \op__insn_type$2$next
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00100000000 "MUL"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 11 output 20 \op__fn_unit$3
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 11 \op__fn_unit$3$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 32 output 21 \op__insn$4
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 32 \op__insn$4$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 output 22 \op__read_cr_whole$5
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \op__read_cr_whole$5$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 output 23 \op__write_cr_whole$6
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \op__write_cr_whole$6$next
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 64 output 24 \o
connect \n_valid_o \n_valid_o
connect \n_ready_i \n_ready_i
end
- attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
wire width 2 \main_muxid
- attribute \enum_base_type "InternalOp"
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 7 \main_op__insn_type
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00100000000 "MUL"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 11 \main_op__fn_unit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 32 \main_op__insn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \main_op__read_cr_whole
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \main_op__write_cr_whole
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
wire width 64 \main_ra
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
wire width 64 \main_rb
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
wire width 32 \main_full_cr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
wire width 4 \main_cr_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
wire width 4 \main_cr_b
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
wire width 4 \main_cr_c
- attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
wire width 2 \main_muxid$9
- attribute \enum_base_type "InternalOp"
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 7 \main_op__insn_type$10
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00100000000 "MUL"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 11 \main_op__fn_unit$11
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 32 \main_op__insn$12
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \main_op__read_cr_whole$13
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \main_op__write_cr_whole$14
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 64 \main_o
assign \p_valid_i_p_ready_o $18
sync init
end
- attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
wire width 2 \muxid$20
process $group_15
assign \muxid$20 2'00
assign \muxid$20 \main_muxid$9
sync init
end
- attribute \enum_base_type "InternalOp"
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 7 \op__insn_type$21
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00100000000 "MUL"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 11 \op__fn_unit$22
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 32 \op__insn$23
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \op__read_cr_whole$24
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \op__write_cr_whole$25
process $group_16
assign \op__insn_type$21 7'0000000
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 2 \o_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 output 3 \o
+ wire width 1 output 3 \full_cr_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 4 \full_cr_ok
+ wire width 1 output 4 \cr_a_ok
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
+ wire width 1 output 5 \n_valid_o
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
+ wire width 1 input 6 \n_ready_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 32 output 5 \full_cr
+ wire width 64 output 7 \o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 6 \cr_a_ok
+ wire width 32 output 8 \full_cr
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 4 output 7 \cr_a
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244"
- wire width 1 output 8 \n_valid_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245"
- wire width 1 input 9 \n_ready_i
- attribute \enum_base_type "InternalOp"
+ wire width 4 output 9 \cr_a
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 7 input 10 \op__insn_type
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00100000000 "MUL"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 11 input 11 \op__fn_unit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 32 input 12 \op__insn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 input 13 \op__read_cr_whole
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 input 14 \op__write_cr_whole
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
wire width 64 input 15 \ra
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
wire width 64 input 16 \rb
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
wire width 32 input 17 \full_cr$1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
wire width 4 input 18 \cr_a$2
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
wire width 4 input 19 \cr_b
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
wire width 4 input 20 \cr_c
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153"
wire width 1 input 21 \p_valid_i
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154"
wire width 1 output 22 \p_ready_o
cell \p$4 \p
connect \p_valid_i \p_valid_i
connect \n_valid_o \n_valid_o
connect \n_ready_i \n_ready_i
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153"
wire width 1 \pipe_p_valid_i
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154"
wire width 1 \pipe_p_ready_o
- attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
wire width 2 \pipe_muxid
- attribute \enum_base_type "InternalOp"
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 7 \pipe_op__insn_type
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00100000000 "MUL"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 11 \pipe_op__fn_unit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 32 \pipe_op__insn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \pipe_op__read_cr_whole
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \pipe_op__write_cr_whole
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
wire width 64 \pipe_ra
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
wire width 64 \pipe_rb
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
wire width 32 \pipe_full_cr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
wire width 4 \pipe_cr_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
wire width 4 \pipe_cr_b
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
wire width 4 \pipe_cr_c
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
wire width 1 \pipe_n_valid_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
wire width 1 \pipe_n_ready_i
- attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
wire width 2 \pipe_muxid$3
- attribute \enum_base_type "InternalOp"
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 7 \pipe_op__insn_type$4
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00100000000 "MUL"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 11 \pipe_op__fn_unit$5
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 32 \pipe_op__insn$6
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \pipe_op__read_cr_whole$7
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \pipe_op__write_cr_whole$8
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 64 \pipe_o
assign \p_ready_o \pipe_p_ready_o
sync init
end
- attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
wire width 2 \muxid
process $group_2
assign \pipe_muxid 2'00
assign \pipe_n_ready_i \n_ready_i
sync init
end
- attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
wire width 2 \muxid$11
process $group_16
assign \muxid$11 2'00
assign \muxid$11 \pipe_muxid$3
sync init
end
- attribute \enum_base_type "InternalOp"
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 7 \op__insn_type$12
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00100000000 "MUL"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 11 \op__fn_unit$13
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 32 \op__insn$14
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \op__read_cr_whole$15
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \op__write_cr_whole$16
process $group_17
assign \op__insn_type$12 7'0000000
wire width 1 input 0 \rst
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
- attribute \enum_base_type "InternalOp"
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 7 input 2 \oper_i__insn_type
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00100000000 "MUL"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 11 input 3 \oper_i__fn_unit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 32 input 4 \oper_i__insn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 input 5 \oper_i__read_cr_whole
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 input 6 \oper_i__write_cr_whole
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94"
wire width 1 input 7 \issue_i
wire width 3 output 19 \wr__rel
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
wire width 3 input 20 \wr__go
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 output 21 \o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
+ wire width 64 output 21 \dest1_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 22 \full_cr_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 32 output 23 \full_cr
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
+ wire width 32 output 23 \dest2_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 24 \cr_a_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 4 output 25 \cr_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
+ wire width 4 output 25 \dest3_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96"
wire width 1 input 26 \go_die_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
wire width 1 input 27 \shadown_i
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
- wire width 64 output 28 \dest1_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
wire width 1 \alu_cr0_n_valid_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
wire width 1 \alu_cr0_n_ready_i
- attribute \enum_base_type "InternalOp"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 64 \alu_cr0_o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 32 \alu_cr0_full_cr
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 4 \alu_cr0_cr_a
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 7 \alu_cr0_op__insn_type
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00100000000 "MUL"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 11 \alu_cr0_op__fn_unit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 32 \alu_cr0_op__insn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \alu_cr0_op__read_cr_whole
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \alu_cr0_op__write_cr_whole
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
wire width 64 \alu_cr0_ra
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
wire width 64 \alu_cr0_rb
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
- wire width 32 \alu_cr0_full_cr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
- wire width 4 \alu_cr0_cr_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 32 \alu_cr0_full_cr$1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 4 \alu_cr0_cr_a$2
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
wire width 4 \alu_cr0_cr_b
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
wire width 4 \alu_cr0_cr_c
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153"
wire width 1 \alu_cr0_p_valid_i
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154"
wire width 1 \alu_cr0_p_ready_o
cell \alu_cr0 \alu_cr0
connect \rst \rst
connect \clk \clk
connect \o_ok \o_ok
- connect \o \o
connect \full_cr_ok \full_cr_ok
- connect \full_cr \full_cr
connect \cr_a_ok \cr_a_ok
- connect \cr_a \cr_a
connect \n_valid_o \alu_cr0_n_valid_o
connect \n_ready_i \alu_cr0_n_ready_i
+ connect \o \alu_cr0_o
+ connect \full_cr \alu_cr0_full_cr
+ connect \cr_a \alu_cr0_cr_a
connect \op__insn_type \alu_cr0_op__insn_type
connect \op__fn_unit \alu_cr0_op__fn_unit
connect \op__insn \alu_cr0_op__insn
connect \op__write_cr_whole \alu_cr0_op__write_cr_whole
connect \ra \alu_cr0_ra
connect \rb \alu_cr0_rb
- connect \full_cr$1 \alu_cr0_full_cr
- connect \cr_a$2 \alu_cr0_cr_a
+ connect \full_cr$1 \alu_cr0_full_cr$1
+ connect \cr_a$2 \alu_cr0_cr_a$2
connect \cr_b \alu_cr0_cr_b
connect \cr_c \alu_cr0_cr_c
connect \p_valid_i \alu_cr0_p_valid_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:178"
wire width 1 \all_rd
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179"
- wire width 1 $1
+ wire width 1 $3
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179"
- cell $and $2
+ cell $and $4
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \busy_o
connect \B \rok_l_q_rdok
- connect \Y $1
+ connect \Y $3
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180"
- wire width 1 $3
+ wire width 1 $5
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180"
- wire width 6 $4
+ wire width 6 $6
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180"
- cell $not $5
+ cell $not $7
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \Y_WIDTH 6
connect \A \rd__rel
- connect \Y $4
+ connect \Y $6
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180"
- wire width 6 $6
+ wire width 6 $8
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180"
- cell $or $7
+ cell $or $9
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \B_WIDTH 6
parameter \Y_WIDTH 6
- connect \A $4
+ connect \A $6
connect \B \rd__go
- connect \Y $6
+ connect \Y $8
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180"
- cell $reduce_and $8
+ cell $reduce_and $10
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \Y_WIDTH 1
- connect \A $6
- connect \Y $3
+ connect \A $8
+ connect \Y $5
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180"
- wire width 1 $9
+ wire width 1 $11
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180"
- cell $and $10
+ cell $and $12
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $1
- connect \B $3
- connect \Y $9
+ connect \A $3
+ connect \B $5
+ connect \Y $11
end
process $group_0
assign \all_rd 1'0
- assign \all_rd $9
+ assign \all_rd $11
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:183"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:184"
wire width 1 \all_rd_pulse
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:186"
- wire width 1 $11
+ wire width 1 $13
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:186"
- cell $not $12
+ cell $not $14
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \all_rd_dly
- connect \Y $11
+ connect \Y $13
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:186"
- wire width 1 $13
+ wire width 1 $15
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:186"
- cell $and $14
+ cell $and $16
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \all_rd
- connect \B $11
- connect \Y $13
+ connect \B $13
+ connect \Y $15
end
process $group_2
assign \all_rd_pulse 1'0
- assign \all_rd_pulse $13
+ assign \all_rd_pulse $15
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:191"
wire width 1 \alu_pulse
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:195"
- wire width 1 $15
+ wire width 1 $17
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:195"
- cell $not $16
+ cell $not $18
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \alu_done_dly
- connect \Y $15
+ connect \Y $17
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:195"
- wire width 1 $17
+ wire width 1 $19
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:195"
- cell $and $18
+ cell $and $20
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \alu_done
- connect \B $15
- connect \Y $17
+ connect \B $17
+ connect \Y $19
end
process $group_5
assign \alu_pulse 1'0
- assign \alu_pulse $17
+ assign \alu_pulse $19
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:192"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:199"
wire width 3 \prev_wr_go$next
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:201"
- wire width 3 $19
+ wire width 3 $21
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:201"
- cell $and $20
+ cell $and $22
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \wr__go
connect \B { \busy_o \busy_o \busy_o }
- connect \Y $19
+ connect \Y $21
end
process $group_7
assign \prev_wr_go$next \prev_wr_go
- assign \prev_wr_go$next $19
+ assign \prev_wr_go$next $21
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100"
wire width 1 \done_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
- wire width 1 $21
+ wire width 1 $23
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
- wire width 1 $22
+ wire width 1 $24
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
- wire width 3 $23
+ wire width 3 $25
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:93"
wire width 3 \wrmask
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
- cell $not $24
+ cell $not $26
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 3
connect \A \wrmask
- connect \Y $23
+ connect \Y $25
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
- wire width 3 $25
+ wire width 3 $27
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
- cell $and $26
+ cell $and $28
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \B_WIDTH 3
parameter \Y_WIDTH 3
connect \A \wr__rel
- connect \B $23
- connect \Y $25
+ connect \B $25
+ connect \Y $27
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
- cell $reduce_bool $27
+ cell $reduce_bool $29
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 1
- connect \A $25
- connect \Y $22
+ connect \A $27
+ connect \Y $24
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
- cell $not $28
+ cell $not $30
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $22
- connect \Y $21
+ connect \A $24
+ connect \Y $23
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
- wire width 1 $29
+ wire width 1 $31
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
- cell $and $30
+ cell $and $32
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \busy_o
- connect \B $21
- connect \Y $29
+ connect \B $23
+ connect \Y $31
end
process $group_8
assign \done_o 1'0
- assign \done_o $29
+ assign \done_o $31
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206"
wire width 1 \wr_any
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210"
- wire width 1 $31
+ wire width 1 $33
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210"
- cell $reduce_bool $32
+ cell $reduce_bool $34
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 1
connect \A \wr__go
- connect \Y $31
+ connect \Y $33
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210"
- wire width 1 $33
+ wire width 1 $35
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210"
- cell $reduce_bool $34
+ cell $reduce_bool $36
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 1
connect \A \prev_wr_go
- connect \Y $33
+ connect \Y $35
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210"
- wire width 1 $35
+ wire width 1 $37
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210"
- cell $or $36
+ cell $or $38
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $31
- connect \B $33
- connect \Y $35
+ connect \A $33
+ connect \B $35
+ connect \Y $37
end
process $group_9
assign \wr_any 1'0
- assign \wr_any $35
+ assign \wr_any $37
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:207"
wire width 1 \req_done
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211"
- wire width 1 $37
+ wire width 1 $39
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211"
- cell $not $38
+ cell $not $40
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \alu_cr0_n_ready_i
- connect \Y $37
+ connect \Y $39
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211"
- wire width 1 $39
+ wire width 1 $41
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211"
- cell $and $40
+ cell $and $42
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \wr_any
- connect \B $37
- connect \Y $39
+ connect \B $39
+ connect \Y $41
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212"
- wire width 3 $41
+ wire width 3 $43
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212"
- cell $and $42
+ cell $and $44
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \req_l_q_req
connect \B \wrmask
- connect \Y $41
+ connect \Y $43
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212"
- wire width 1 $43
+ wire width 1 $45
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212"
- cell $eq $44
+ cell $eq $46
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $41
+ connect \A $43
connect \B 1'0
- connect \Y $43
+ connect \Y $45
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212"
- wire width 1 $45
+ wire width 1 $47
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212"
- cell $and $46
+ cell $and $48
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $39
- connect \B $43
- connect \Y $45
+ connect \A $41
+ connect \B $45
+ connect \Y $47
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
- wire width 1 $47
+ wire width 1 $49
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
- cell $eq $48
+ cell $eq $50
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wrmask
connect \B 1'0
- connect \Y $47
+ connect \Y $49
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
- wire width 1 $49
+ wire width 1 $51
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
- cell $and $50
+ cell $and $52
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $47
+ connect \A $49
connect \B \alu_cr0_n_ready_i
- connect \Y $49
+ connect \Y $51
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
- wire width 1 $51
+ wire width 1 $53
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
- cell $and $52
+ cell $and $54
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $49
+ connect \A $51
connect \B \alu_cr0_n_valid_o
- connect \Y $51
+ connect \Y $53
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
- wire width 1 $53
+ wire width 1 $55
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
- cell $and $54
+ cell $and $56
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $51
+ connect \A $53
connect \B \busy_o
- connect \Y $53
+ connect \Y $55
end
process $group_10
assign \req_done 1'0
- assign \req_done $45
+ assign \req_done $47
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
- switch { $53 }
+ switch { $55 }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
case 1'1
assign \req_done 1'1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:221"
wire width 1 \reset
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
- wire width 1 $55
+ wire width 1 $57
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
- cell $or $56
+ cell $or $58
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \req_done
connect \B \go_die_i
- connect \Y $55
+ connect \Y $57
end
process $group_11
assign \reset 1'0
- assign \reset $55
+ assign \reset $57
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222"
wire width 1 \rst_r
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226"
- wire width 1 $57
+ wire width 1 $59
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226"
- cell $or $58
+ cell $or $60
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \issue_i
connect \B \go_die_i
- connect \Y $57
+ connect \Y $59
end
process $group_12
assign \rst_r 1'0
- assign \rst_r $57
+ assign \rst_r $59
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:223"
wire width 3 \reset_w
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227"
- wire width 3 $59
+ wire width 3 $61
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227"
- cell $or $60
+ cell $or $62
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \wr__go
connect \B { \go_die_i \go_die_i \go_die_i }
- connect \Y $59
+ connect \Y $61
end
process $group_13
assign \reset_w 3'000
- assign \reset_w $59
+ assign \reset_w $61
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:224"
wire width 6 \reset_r
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:228"
- wire width 6 $61
+ wire width 6 $63
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:228"
- cell $or $62
+ cell $or $64
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 6
connect \A \rd__go
connect \B { \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i }
- connect \Y $61
+ connect \Y $63
end
process $group_14
assign \reset_r 6'000000
- assign \reset_r $61
+ assign \reset_r $63
sync init
end
process $group_15
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232"
- wire width 1 $63
+ wire width 1 $65
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232"
- cell $and $64
+ cell $and $66
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \alu_cr0_n_valid_o
connect \B \busy_o
- connect \Y $63
+ connect \Y $65
end
process $group_16
assign \rok_l_r_rdok$next \rok_l_r_rdok
- assign \rok_l_r_rdok$next $63
+ assign \rok_l_r_rdok$next $65
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
update \src_l_r_src \src_l_r_src$next
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:247"
- wire width 3 $65
+ wire width 3 $67
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:247"
- cell $and $66
+ cell $and $68
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \alu_pulsem
connect \B \wrmask
- connect \Y $65
+ connect \Y $67
end
process $group_23
assign \req_l_s_req 3'000
- assign \req_l_s_req $65
+ assign \req_l_s_req $67
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:248"
- wire width 3 $67
+ wire width 3 $69
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:248"
- cell $or $68
+ cell $or $70
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \reset_w
connect \B \prev_wr_go
- connect \Y $67
+ connect \Y $69
end
process $group_24
assign \req_l_r_req 3'111
- assign \req_l_r_req $67
+ assign \req_l_r_req $69
sync init
end
- attribute \enum_base_type "InternalOp"
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 7 \oper_r__insn_type
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00100000000 "MUL"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 11 \oper_r__fn_unit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 32 \oper_r__insn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \oper_r__read_cr_whole
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \oper_r__write_cr_whole
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
wire width 7 \oper_l__insn_type
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
wire width 1 \oper_l__write_cr_whole$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
- wire width 52 $69
+ wire width 52 $71
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
- cell $mux $70
+ cell $mux $72
parameter \WIDTH 52
connect \A { \oper_l__write_cr_whole \oper_l__read_cr_whole \oper_l__insn \oper_l__fn_unit \oper_l__insn_type }
connect \B { \oper_i__write_cr_whole \oper_i__read_cr_whole \oper_i__insn \oper_i__fn_unit \oper_i__insn_type }
connect \S \issue_i
- connect \Y $69
+ connect \Y $71
end
process $group_25
assign \oper_r__insn_type 7'0000000
assign \oper_r__insn 32'00000000000000000000000000000000
assign \oper_r__read_cr_whole 1'0
assign \oper_r__write_cr_whole 1'0
- assign { \oper_r__write_cr_whole \oper_r__read_cr_whole \oper_r__insn \oper_r__fn_unit \oper_r__insn_type } $69
+ assign { \oper_r__write_cr_whole \oper_r__read_cr_whole \oper_r__insn \oper_r__fn_unit \oper_r__insn_type } $71
sync init
end
process $group_30
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
wire width 1 \data_r0_l__o_ok$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
- wire width 65 $71
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:730"
- wire width 1 $72
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:730"
- cell $reduce_bool $73
+ wire width 65 $73
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744"
+ wire width 1 $74
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744"
+ cell $reduce_bool $75
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 1
connect \A \alu_pulsem
- connect \Y $72
+ connect \Y $74
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
- cell $mux $74
+ cell $mux $76
parameter \WIDTH 65
connect \A { \data_r0_l__o_ok \data_r0_l__o }
- connect \B { \o_ok \o }
- connect \S $72
- connect \Y $71
+ connect \B { \o_ok \alu_cr0_o }
+ connect \S $74
+ connect \Y $73
end
process $group_35
assign \data_r0__o 64'0000000000000000000000000000000000000000000000000000000000000000
assign \data_r0__o_ok 1'0
- assign { \data_r0__o_ok \data_r0__o } $71
+ assign { \data_r0__o_ok \data_r0__o } $73
sync init
end
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
- wire width 1 $75
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
- cell $reduce_bool $76
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
+ wire width 1 $77
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
+ cell $reduce_bool $78
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 1
connect \A \alu_pulsem
- connect \Y $75
+ connect \Y $77
end
process $group_37
assign \data_r0_l__o$next \data_r0_l__o
assign \data_r0_l__o_ok$next \data_r0_l__o_ok
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
- switch { $75 }
+ switch { $77 }
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
case 1'1
- assign { \data_r0_l__o_ok$next \data_r0_l__o$next } { \o_ok \o }
+ assign { \data_r0_l__o_ok$next \data_r0_l__o$next } { \o_ok \alu_cr0_o }
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
wire width 1 \data_r1_l__full_cr_ok$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
- wire width 33 $77
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:730"
- wire width 1 $78
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:730"
- cell $reduce_bool $79
+ wire width 33 $79
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744"
+ wire width 1 $80
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744"
+ cell $reduce_bool $81
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 1
connect \A \alu_pulsem
- connect \Y $78
+ connect \Y $80
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
- cell $mux $80
+ cell $mux $82
parameter \WIDTH 33
connect \A { \data_r1_l__full_cr_ok \data_r1_l__full_cr }
- connect \B { \full_cr_ok \full_cr }
- connect \S $78
- connect \Y $77
+ connect \B { \full_cr_ok \alu_cr0_full_cr }
+ connect \S $80
+ connect \Y $79
end
process $group_39
assign \data_r1__full_cr 32'00000000000000000000000000000000
assign \data_r1__full_cr_ok 1'0
- assign { \data_r1__full_cr_ok \data_r1__full_cr } $77
+ assign { \data_r1__full_cr_ok \data_r1__full_cr } $79
sync init
end
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
- wire width 1 $81
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
- cell $reduce_bool $82
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
+ wire width 1 $83
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
+ cell $reduce_bool $84
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 1
connect \A \alu_pulsem
- connect \Y $81
+ connect \Y $83
end
process $group_41
assign \data_r1_l__full_cr$next \data_r1_l__full_cr
assign \data_r1_l__full_cr_ok$next \data_r1_l__full_cr_ok
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
- switch { $81 }
+ switch { $83 }
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
case 1'1
- assign { \data_r1_l__full_cr_ok$next \data_r1_l__full_cr$next } { \full_cr_ok \full_cr }
+ assign { \data_r1_l__full_cr_ok$next \data_r1_l__full_cr$next } { \full_cr_ok \alu_cr0_full_cr }
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
wire width 1 \data_r2_l__cr_a_ok$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
- wire width 5 $83
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:730"
- wire width 1 $84
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:730"
- cell $reduce_bool $85
+ wire width 5 $85
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744"
+ wire width 1 $86
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744"
+ cell $reduce_bool $87
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 1
connect \A \alu_pulsem
- connect \Y $84
+ connect \Y $86
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
- cell $mux $86
+ cell $mux $88
parameter \WIDTH 5
connect \A { \data_r2_l__cr_a_ok \data_r2_l__cr_a }
- connect \B { \cr_a_ok \cr_a }
- connect \S $84
- connect \Y $83
+ connect \B { \cr_a_ok \alu_cr0_cr_a }
+ connect \S $86
+ connect \Y $85
end
process $group_43
assign \data_r2__cr_a 4'0000
assign \data_r2__cr_a_ok 1'0
- assign { \data_r2__cr_a_ok \data_r2__cr_a } $83
+ assign { \data_r2__cr_a_ok \data_r2__cr_a } $85
sync init
end
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
- wire width 1 $87
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
- cell $reduce_bool $88
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
+ wire width 1 $89
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
+ cell $reduce_bool $90
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 1
connect \A \alu_pulsem
- connect \Y $87
+ connect \Y $89
end
process $group_45
assign \data_r2_l__cr_a$next \data_r2_l__cr_a
assign \data_r2_l__cr_a_ok$next \data_r2_l__cr_a_ok
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
- switch { $87 }
+ switch { $89 }
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
case 1'1
- assign { \data_r2_l__cr_a_ok$next \data_r2_l__cr_a$next } { \cr_a_ok \cr_a }
+ assign { \data_r2_l__cr_a_ok$next \data_r2_l__cr_a$next } { \cr_a_ok \alu_cr0_cr_a }
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
update \data_r2_l__cr_a \data_r2_l__cr_a$next
update \data_r2_l__cr_a_ok \data_r2_l__cr_a_ok$next
end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+ wire width 1 $91
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+ cell $and $92
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \data_r0__o_ok
+ connect \B \busy_o
+ connect \Y $91
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+ wire width 1 $93
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+ cell $and $94
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \data_r1__full_cr_ok
+ connect \B \busy_o
+ connect \Y $93
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+ wire width 1 $95
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+ cell $and $96
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \data_r2__cr_a_ok
+ connect \B \busy_o
+ connect \Y $95
+ end
process $group_47
assign \wrmask 3'000
- assign \wrmask { \data_r2__cr_a_ok \data_r1__full_cr_ok \data_r0__o_ok }
+ assign \wrmask { $95 $93 $91 }
sync init
end
process $group_48
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
wire width 64 \src_r0$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
- wire width 64 $89
+ wire width 64 $97
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
- cell $mux $90
+ cell $mux $98
parameter \WIDTH 64
connect \A \src_r0
connect \B \src1_i
connect \S \src_l_q_src [0]
- connect \Y $89
+ connect \Y $97
end
process $group_53
assign \alu_cr0_ra 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \alu_cr0_ra $89
+ assign \alu_cr0_ra $97
sync init
end
process $group_54
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
wire width 64 \src_r1$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
- wire width 64 $91
+ wire width 64 $99
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
- cell $mux $92
+ cell $mux $100
parameter \WIDTH 64
connect \A \src_r1
connect \B \src2_i
connect \S \src_l_q_src [1]
- connect \Y $91
+ connect \Y $99
end
process $group_55
assign \alu_cr0_rb 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \alu_cr0_rb $91
+ assign \alu_cr0_rb $99
sync init
end
process $group_56
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
wire width 32 \src_r2$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
- wire width 32 $93
+ wire width 32 $101
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
- cell $mux $94
+ cell $mux $102
parameter \WIDTH 32
connect \A \src_r2
connect \B \src3_i
connect \S \src_l_q_src [2]
- connect \Y $93
+ connect \Y $101
end
process $group_57
- assign \alu_cr0_full_cr 32'00000000000000000000000000000000
- assign \alu_cr0_full_cr $93
+ assign \alu_cr0_full_cr$1 32'00000000000000000000000000000000
+ assign \alu_cr0_full_cr$1 $101
sync init
end
process $group_58
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
wire width 4 \src_r3$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
- wire width 4 $95
+ wire width 4 $103
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
- cell $mux $96
+ cell $mux $104
parameter \WIDTH 4
connect \A \src_r3
connect \B \src4_i
connect \S \src_l_q_src [3]
- connect \Y $95
+ connect \Y $103
end
process $group_59
- assign \alu_cr0_cr_a 4'0000
- assign \alu_cr0_cr_a $95
+ assign \alu_cr0_cr_a$2 4'0000
+ assign \alu_cr0_cr_a$2 $103
sync init
end
process $group_60
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
wire width 4 \src_r4$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
- wire width 4 $97
+ wire width 4 $105
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
- cell $mux $98
+ cell $mux $106
parameter \WIDTH 4
connect \A \src_r4
connect \B \src5_i
connect \S \src_l_q_src [4]
- connect \Y $97
+ connect \Y $105
end
process $group_61
assign \alu_cr0_cr_b 4'0000
- assign \alu_cr0_cr_b $97
+ assign \alu_cr0_cr_b $105
sync init
end
process $group_62
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
wire width 4 \src_r5$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
- wire width 4 $99
+ wire width 4 $107
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
- cell $mux $100
+ cell $mux $108
parameter \WIDTH 4
connect \A \src_r5
connect \B \src6_i
connect \S \src_l_q_src [5]
- connect \Y $99
+ connect \Y $107
end
process $group_63
assign \alu_cr0_cr_c 4'0000
- assign \alu_cr0_cr_c $99
+ assign \alu_cr0_cr_c $107
sync init
end
process $group_64
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:321"
- wire width 1 $101
+ wire width 1 $109
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:321"
- cell $and $102
+ cell $and $110
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \alu_cr0_p_ready_o
connect \B \alui_l_q_alui
- connect \Y $101
+ connect \Y $109
end
process $group_66
assign \alui_l_r_alui$next \alui_l_r_alui
- assign \alui_l_r_alui$next $101
+ assign \alui_l_r_alui$next $109
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:328"
- wire width 1 $103
+ wire width 1 $111
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:328"
- cell $and $104
+ cell $and $112
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \alu_cr0_n_valid_o
connect \B \alu_l_q_alu
- connect \Y $103
+ connect \Y $111
end
process $group_69
assign \alu_l_r_alu$next \alu_l_r_alu
- assign \alu_l_r_alu$next $103
+ assign \alu_l_r_alu$next $111
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341"
- wire width 6 $105
+ wire width 6 $113
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341"
- cell $and $106
+ cell $and $114
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 6
connect \A \src_l_q_src
connect \B { \busy_o \busy_o \busy_o \busy_o \busy_o \busy_o }
- connect \Y $105
+ connect \Y $113
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341"
- wire width 6 $107
+ wire width 6 $115
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341"
- cell $and $108
+ cell $and $116
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \B_WIDTH 6
parameter \Y_WIDTH 6
- connect \A $105
+ connect \A $113
connect \B { 1'1 1'1 1'1 1'1 1'1 1'1 }
- connect \Y $107
+ connect \Y $115
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341"
- wire width 6 $109
+ wire width 6 $117
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341"
- cell $not $110
+ cell $not $118
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \Y_WIDTH 6
connect \A \rdmaskn
- connect \Y $109
+ connect \Y $117
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341"
- wire width 6 $111
+ wire width 6 $119
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341"
- cell $and $112
+ cell $and $120
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \B_WIDTH 6
parameter \Y_WIDTH 6
- connect \A $107
- connect \B $109
- connect \Y $111
+ connect \A $115
+ connect \B $117
+ connect \Y $119
end
process $group_72
assign \rd__rel 6'000000
- assign \rd__rel $111
+ assign \rd__rel $119
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
- wire width 1 $113
+ wire width 1 $121
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
- cell $and $114
+ cell $and $122
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \busy_o
connect \B \shadown_i
- connect \Y $113
+ connect \Y $121
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
- wire width 1 $115
+ wire width 1 $123
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
- cell $and $116
+ cell $and $124
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \busy_o
connect \B \shadown_i
- connect \Y $115
+ connect \Y $123
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
- wire width 1 $117
+ wire width 1 $125
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
- cell $and $118
+ cell $and $126
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \busy_o
connect \B \shadown_i
- connect \Y $117
+ connect \Y $125
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:345"
- wire width 3 $119
+ wire width 3 $127
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:345"
- cell $and $120
+ cell $and $128
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \B_WIDTH 3
parameter \Y_WIDTH 3
connect \A \req_l_q_req
- connect \B { $113 $115 $117 }
- connect \Y $119
+ connect \B { $121 $123 $125 }
+ connect \Y $127
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:345"
- wire width 3 $121
+ wire width 3 $129
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:345"
- cell $and $122
+ cell $and $130
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \B_WIDTH 3
parameter \Y_WIDTH 3
- connect \A $119
+ connect \A $127
connect \B \wrmask
- connect \Y $121
+ connect \Y $129
end
process $group_73
assign \wr__rel 3'000
- assign \wr__rel $121
+ assign \wr__rel $129
sync init
end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+ wire width 1 $131
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+ cell $and $132
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \wr__go [0]
+ connect \B \busy_o
+ connect \Y $131
+ end
process $group_74
assign \dest1_o 64'0000000000000000000000000000000000000000000000000000000000000000
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
- switch { \wr__go [0] }
+ switch { $131 }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
case 1'1
assign \dest1_o { \data_r0__o_ok \data_r0__o } [63:0]
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
- wire width 32 \dest2_o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+ wire width 1 $133
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+ cell $and $134
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \wr__go [1]
+ connect \B \busy_o
+ connect \Y $133
+ end
process $group_75
assign \dest2_o 32'00000000000000000000000000000000
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
- switch { \wr__go [1] }
+ switch { $133 }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
case 1'1
assign \dest2_o { \data_r1__full_cr_ok \data_r1__full_cr } [31:0]
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
- wire width 4 \dest3_o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+ wire width 1 $135
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+ cell $and $136
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \wr__go [2]
+ connect \B \busy_o
+ connect \Y $135
+ end
process $group_76
assign \dest3_o 4'0000
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
- switch { \wr__go [2] }
+ switch { $135 }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
case 1'1
assign \dest3_o { \data_r2__cr_a_ok \data_r2__cr_a } [3:0]
attribute \generator "nMigen"
attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.alu_branch0.p"
module \p$17
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153"
wire width 1 input 0 \p_valid_i
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154"
wire width 1 input 1 \p_ready_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:156"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158"
wire width 1 \trigger
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:203"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205"
wire width 1 $1
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:203"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205"
cell $and $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
attribute \generator "nMigen"
attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.alu_branch0.n"
module \n$18
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
wire width 1 input 0 \n_valid_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
wire width 1 input 1 \n_ready_i
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:249"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251"
wire width 1 \trigger
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:295"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:297"
wire width 1 $1
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:295"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:297"
cell $and $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
attribute \generator "nMigen"
attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.alu_branch0.pipe.p"
module \p$20
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153"
wire width 1 input 0 \p_valid_i
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154"
wire width 1 input 1 \p_ready_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:156"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158"
wire width 1 \trigger
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:203"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205"
wire width 1 $1
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:203"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205"
cell $and $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
attribute \generator "nMigen"
attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.alu_branch0.pipe.n"
module \n$21
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
wire width 1 input 0 \n_valid_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
wire width 1 input 1 \n_ready_i
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:249"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251"
wire width 1 \trigger
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:295"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:297"
wire width 1 $1
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:295"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:297"
cell $and $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
attribute \generator "nMigen"
attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.alu_branch0.pipe.main"
module \main$22
- attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
wire width 2 input 0 \muxid
- attribute \enum_base_type "InternalOp"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 input 1 \op__cia
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
- wire width 7 input 1 \op__insn_type
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 7 input 2 \op__insn_type
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00000000010 "ALU"
attribute \enum_value_00100000000 "MUL"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
- wire width 11 input 2 \op__fn_unit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
- wire width 64 input 3 \op__imm_data__imm
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
- wire width 1 input 4 \op__imm_data__imm_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
- wire width 1 input 5 \op__lk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
- wire width 1 input 6 \op__is_32bit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
- wire width 32 input 7 \op__insn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
- wire width 64 input 8 \fast1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
- wire width 64 input 9 \fast2
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
- wire width 4 input 10 \cr_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
- wire width 64 input 11 \cia
- attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 11 input 3 \op__fn_unit
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 input 4 \op__insn
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 input 5 \op__imm_data__imm
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 6 \op__imm_data__imm_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 7 \op__lk
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 8 \op__is_32bit
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 64 input 9 \fast1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 64 input 10 \fast2
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 4 input 11 \cr_a
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
wire width 2 output 12 \muxid$1
- attribute \enum_base_type "InternalOp"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 output 13 \op__cia$2
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
- wire width 7 output 13 \op__insn_type$2
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 7 output 14 \op__insn_type$3
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00000000010 "ALU"
attribute \enum_value_00100000000 "MUL"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
- wire width 11 output 14 \op__fn_unit$3
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
- wire width 64 output 15 \op__imm_data__imm$4
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
- wire width 1 output 16 \op__imm_data__imm_ok$5
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
- wire width 1 output 17 \op__lk$6
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
- wire width 1 output 18 \op__is_32bit$7
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
- wire width 32 output 19 \op__insn$8
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 11 output 15 \op__fn_unit$4
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 output 16 \op__insn$5
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 output 17 \op__imm_data__imm$6
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 18 \op__imm_data__imm_ok$7
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 19 \op__lk$8
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 20 \op__is_32bit$9
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 output 20 \fast1$9
+ wire width 64 output 21 \fast1$10
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 21 \fast1_ok
+ wire width 1 output 22 \fast1_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 output 22 \fast2$10
+ wire width 64 output 23 \fast2$11
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 23 \fast2_ok
+ wire width 1 output 24 \fast2_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 output 24 \nia
+ wire width 64 output 25 \nia
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 25 \nia_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:69"
+ wire width 1 output 26 \nia_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:84"
wire width 64 \br_addr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:73"
- wire width 1 $11
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:73"
- cell $eq $12
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:88"
+ wire width 1 $12
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:88"
+ cell $eq $13
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \op__insn_type
connect \B 7'0001000
- connect \Y $11
+ connect \Y $12
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:73"
- wire width 1 $13
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:73"
- cell $or $14
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:88"
+ wire width 1 $14
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:88"
+ cell $or $15
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A { \op__insn [1] }
- connect \B $11
- connect \Y $13
+ connect \B $12
+ connect \Y $14
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:68"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:83"
wire width 64 \br_imm_addr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:76"
- wire width 65 $15
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:76"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:91"
wire width 65 $16
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:76"
- cell $add $17
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:91"
+ wire width 65 $17
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:91"
+ cell $add $18
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \B_WIDTH 64
parameter \Y_WIDTH 65
connect \A \br_imm_addr
- connect \B \cia
- connect \Y $16
+ connect \B \op__cia
+ connect \Y $17
end
- connect $15 $16
+ connect $16 $17
process $group_0
assign \br_addr 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:73"
- switch { $13 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:73"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:88"
+ switch { $14 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:88"
case 1'1
assign \br_addr \br_imm_addr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:75"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:90"
case
- assign \br_addr $15 [63:0]
+ assign \br_addr $16 [63:0]
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:86"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:101"
wire width 2 \bi
process $group_1
assign \bi 2'00
assign \bi { \op__insn [20] \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] } [1:0]
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:87"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:102"
wire width 1 \cr_bit
process $group_2
assign \cr_bit 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:89"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:104"
switch \bi
case 2'00
assign \cr_bit \cr_a [3]
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:92"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:107"
wire width 1 \ctr_write
process $group_3
assign \ctr_write 1'0
assign \ctr_write 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:97"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:112"
switch { { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] } [2] }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:97"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:112"
case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:99"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:114"
case
assign \ctr_write 1'1
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:96"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:111"
wire width 1 \bc_taken
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:98"
- wire width 1 $18
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:98"
- cell $eq $19
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:113"
+ wire width 1 $19
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:113"
+ cell $eq $20
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \cr_bit
connect \B { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] } [3]
- connect \Y $18
+ connect \Y $19
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:98"
- wire width 1 $20
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:98"
- cell $or $21
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:113"
+ wire width 1 $21
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:113"
+ cell $or $22
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $18
+ connect \A $19
connect \B { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] } [4]
- connect \Y $20
+ connect \Y $21
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:114"
- wire width 1 $22
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:114"
- cell $eq $23
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:129"
+ wire width 1 $23
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:129"
+ cell $eq $24
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] } [4:3]
connect \B 1'0
- connect \Y $22
+ connect \Y $23
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:116"
- wire width 1 $24
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:116"
- cell $eq $25
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:131"
+ wire width 1 $25
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:131"
+ cell $eq $26
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] } [4:3]
connect \B 1'1
- connect \Y $24
+ connect \Y $25
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:118"
- wire width 1 $26
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:118"
- cell $eq $27
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:133"
+ wire width 1 $27
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:133"
+ cell $eq $28
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] } [4]
connect \B 1'1
- connect \Y $26
+ connect \Y $27
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:127"
wire width 1 \ctr_zero_bo1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:115"
- wire width 1 $28
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:115"
- cell $not $29
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:130"
+ wire width 1 $29
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:130"
+ cell $not $30
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \cr_bit
- connect \Y $28
+ connect \Y $29
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:115"
- wire width 1 $30
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:115"
- cell $and $31
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:130"
+ wire width 1 $31
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:130"
+ cell $and $32
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \ctr_zero_bo1
- connect \B $28
- connect \Y $30
+ connect \B $29
+ connect \Y $31
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:117"
- wire width 1 $32
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:117"
- cell $and $33
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:132"
+ wire width 1 $33
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:132"
+ cell $and $34
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \ctr_zero_bo1
connect \B \cr_bit
- connect \Y $32
+ connect \Y $33
end
process $group_4
assign \bc_taken 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:97"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:112"
switch { { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] } [2] }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:97"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:112"
case 1'1
- assign \bc_taken $20
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:99"
+ assign \bc_taken $21
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:114"
case
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:114"
- switch { $26 $24 $22 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:114"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:129"
+ switch { $27 $25 $23 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:129"
case 3'--1
- assign \bc_taken $30
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:116"
+ assign \bc_taken $31
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:131"
case 3'-1-
- assign \bc_taken $32
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:118"
+ assign \bc_taken $33
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:133"
case 3'1--
assign \bc_taken \ctr_zero_bo1
end
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:101"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:116"
wire width 64 \ctr_n
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:102"
- wire width 65 $34
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:102"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:117"
wire width 65 $35
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:102"
- cell $sub $36
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:117"
+ wire width 65 $36
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:117"
+ cell $sub $37
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 65
connect \A \fast1
connect \B 1'1
- connect \Y $35
+ connect \Y $36
end
- connect $34 $35
+ connect $35 $36
process $group_5
assign \ctr_n 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:97"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:112"
switch { { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] } [2] }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:97"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:112"
case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:99"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:114"
case
- assign \ctr_n $34 [63:0]
+ assign \ctr_n $35 [63:0]
end
sync init
end
process $group_6
- assign \fast1$9 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:97"
+ assign \fast1$10 64'0000000000000000000000000000000000000000000000000000000000000000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:112"
switch { { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] } [2] }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:97"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:112"
case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:99"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:114"
case
- assign \fast1$9 \ctr_n
+ assign \fast1$10 \ctr_n
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:106"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:121"
wire width 64 \ctr_m
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:251"
- wire width 64 $37
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:251"
- cell $pos $38
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265"
+ wire width 64 $38
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265"
+ cell $pos $39
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \Y_WIDTH 64
connect \A \fast1 [31:0]
- connect \Y $37
+ connect \Y $38
end
process $group_7
assign \ctr_m 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:97"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:112"
switch { { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] } [2] }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:97"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:112"
case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:99"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:114"
case
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:107"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:122"
switch { \op__is_32bit }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:107"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:122"
case 1'1
- assign \ctr_m $37
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:109"
+ assign \ctr_m $38
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:124"
case
assign \ctr_m \fast1
end
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:113"
- wire width 1 $39
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:113"
- cell $reduce_or $40
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:128"
+ wire width 1 $40
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:128"
+ cell $reduce_or $41
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 1
connect \A \ctr_m
- connect \Y $39
+ connect \Y $40
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:113"
- wire width 1 $41
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:113"
- cell $xor $42
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:128"
+ wire width 1 $42
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:128"
+ cell $xor $43
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] } [1]
- connect \B $39
- connect \Y $41
+ connect \B $40
+ connect \Y $42
end
process $group_8
assign \ctr_zero_bo1 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:97"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:112"
switch { { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] } [2] }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:97"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:112"
case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:99"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:114"
case
- assign \ctr_zero_bo1 $41
+ assign \ctr_zero_bo1 $42
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:137"
- wire width 1 $43
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:137"
- cell $not $44
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:152"
+ wire width 1 $44
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:152"
+ cell $not $45
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A { \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] \op__insn [1] } [5]
- connect \Y $43
+ connect \Y $44
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:137"
- wire width 1 $45
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:137"
- cell $and $46
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:152"
+ wire width 1 $46
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:152"
+ cell $and $47
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A { \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] \op__insn [1] } [9]
- connect \B $43
- connect \Y $45
+ connect \B $44
+ connect \Y $46
end
process $group_9
assign \br_imm_addr 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:122"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:137"
switch \op__insn_type
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:124"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:139"
attribute \nmigen.decoding "OP_B/6"
case 7'0000110
assign \br_imm_addr { { { { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] \op__insn [20] \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [23] { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] \op__insn [20] \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [23] { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] \op__insn [20] \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [23] { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] \op__insn [20] \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [23] { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] \op__insn [20] \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [23] { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] \op__insn [20] \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [23] { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] \op__insn [20] \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [23] { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] \op__insn [20] \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [23] { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] \op__insn [20] \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [23] { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] \op__insn [20] \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [23] { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] \op__insn [20] \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [23] { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] \op__insn [20] \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [23] { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] \op__insn [20] \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [23] { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] \op__insn [20] \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [23] { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] \op__insn [20] \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [23] { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] \op__insn [20] \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [23] { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] \op__insn [20] \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [23] { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] \op__insn [20] \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [23] { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] \op__insn [20] \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [23] { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] \op__insn [20] \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [23] { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] \op__insn [20] \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [23] { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] \op__insn [20] \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [23] { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] \op__insn [20] \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [23] { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] \op__insn [20] \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [23] { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] \op__insn [20] \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [23] { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] \op__insn [20] \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [23] { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] \op__insn [20] \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [23] { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] \op__insn [20] \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [23] { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] \op__insn [20] \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [23] { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] \op__insn [20] \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [23] { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] \op__insn [20] \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [23] { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] \op__insn [20] \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [23] { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] \op__insn [20] \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [23] { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] \op__insn [20] \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [23] { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] \op__insn [20] \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [23] { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] \op__insn [20] \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [23] { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] \op__insn [20] \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [23] { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] \op__insn [20] \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [23] } { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] \op__insn [20] \op__insn [19] \op__insn [18] \op__insn [17] \op__insn [16] \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } } 2'00 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:129"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:144"
attribute \nmigen.decoding "OP_BC/7"
case 7'0000111
assign \br_imm_addr { { { { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } [13] } { \op__insn [15] \op__insn [14] \op__insn [13] \op__insn [12] \op__insn [11] \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] } } 2'00 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:150"
attribute \nmigen.decoding "OP_BCREG/8"
case 7'0001000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:137"
- switch { $45 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:137"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:152"
+ switch { $46 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:152"
case 1'1
assign \br_imm_addr { \fast1 [63:2] 2'00 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:139"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:154"
case
assign \br_imm_addr { \fast2 [63:2] 2'00 }
end
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:70"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:85"
wire width 1 \br_taken
process $group_10
assign \br_taken 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:122"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:137"
switch \op__insn_type
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:124"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:139"
attribute \nmigen.decoding "OP_B/6"
case 7'0000110
assign \br_taken 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:129"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:144"
attribute \nmigen.decoding "OP_BC/7"
case 7'0000111
assign \br_taken \bc_taken
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:150"
attribute \nmigen.decoding "OP_BCREG/8"
case 7'0001000
assign \br_taken \bc_taken
end
process $group_11
assign \fast1_ok 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:122"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:137"
switch \op__insn_type
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:124"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:139"
attribute \nmigen.decoding "OP_B/6"
case 7'0000110
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:129"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:144"
attribute \nmigen.decoding "OP_BC/7"
case 7'0000111
assign \fast1_ok \ctr_write
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:135"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:150"
attribute \nmigen.decoding "OP_BCREG/8"
case 7'0001000
assign \fast1_ok \ctr_write
assign \nia_ok \br_taken
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:152"
- wire width 65 $47
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:152"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:167"
wire width 65 $48
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:152"
- cell $add $49
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:167"
+ wire width 65 $49
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:167"
+ cell $add $50
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \B_WIDTH 3
parameter \Y_WIDTH 65
- connect \A \cia
+ connect \A \op__cia
connect \B 3'100
- connect \Y $48
+ connect \Y $49
end
- connect $47 $48
+ connect $48 $49
process $group_14
- assign \fast2$10 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:149"
+ assign \fast2$11 64'0000000000000000000000000000000000000000000000000000000000000000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:164"
switch { \op__lk }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:149"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:164"
case 1'1
- assign \fast2$10 $47 [63:0]
+ assign \fast2$11 $48 [63:0]
end
sync init
end
process $group_15
assign \fast2_ok 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:149"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:164"
switch { \op__lk }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:149"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:164"
case 1'1
assign \fast2_ok 1'1
end
sync init
end
process $group_17
- assign \op__insn_type$2 7'0000000
- assign \op__fn_unit$3 11'00000000000
- assign \op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \op__imm_data__imm_ok$5 1'0
- assign \op__lk$6 1'0
- assign \op__is_32bit$7 1'0
- assign \op__insn$8 32'00000000000000000000000000000000
- assign { \op__insn$8 \op__is_32bit$7 \op__lk$6 { \op__imm_data__imm_ok$5 \op__imm_data__imm$4 } \op__fn_unit$3 \op__insn_type$2 } { \op__insn \op__is_32bit \op__lk { \op__imm_data__imm_ok \op__imm_data__imm } \op__fn_unit \op__insn_type }
+ assign \op__cia$2 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \op__insn_type$3 7'0000000
+ assign \op__fn_unit$4 11'00000000000
+ assign \op__insn$5 32'00000000000000000000000000000000
+ assign \op__imm_data__imm$6 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \op__imm_data__imm_ok$7 1'0
+ assign \op__lk$8 1'0
+ assign \op__is_32bit$9 1'0
+ assign { \op__is_32bit$9 \op__lk$8 { \op__imm_data__imm_ok$7 \op__imm_data__imm$6 } \op__insn$5 \op__fn_unit$4 \op__insn_type$3 \op__cia$2 } { \op__is_32bit \op__lk { \op__imm_data__imm_ok \op__imm_data__imm } \op__insn \op__fn_unit \op__insn_type \op__cia }
sync init
end
end
wire width 1 input 0 \rst
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153"
wire width 1 input 2 \p_valid_i
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154"
wire width 1 output 3 \p_ready_o
- attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
wire width 2 input 4 \muxid
- attribute \enum_base_type "InternalOp"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 input 5 \op__cia
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
- wire width 7 input 5 \op__insn_type
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 7 input 6 \op__insn_type
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00000000010 "ALU"
attribute \enum_value_00100000000 "MUL"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
- wire width 11 input 6 \op__fn_unit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
- wire width 64 input 7 \op__imm_data__imm
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
- wire width 1 input 8 \op__imm_data__imm_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
- wire width 1 input 9 \op__lk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
- wire width 1 input 10 \op__is_32bit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
- wire width 32 input 11 \op__insn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
- wire width 64 input 12 \fast1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
- wire width 64 input 13 \fast2
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
- wire width 4 input 14 \cr_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
- wire width 64 input 15 \cia
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 11 input 7 \op__fn_unit
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 input 8 \op__insn
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 input 9 \op__imm_data__imm
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 10 \op__imm_data__imm_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 11 \op__lk
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 12 \op__is_32bit
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 64 input 13 \fast1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 64 input 14 \fast2
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 4 input 15 \cr_a
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
wire width 1 output 16 \n_valid_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
wire width 1 input 17 \n_ready_i
- attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
wire width 2 output 18 \muxid$1
- attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
wire width 2 \muxid$1$next
- attribute \enum_base_type "InternalOp"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 output 19 \op__cia$2
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 \op__cia$2$next
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
- wire width 7 output 19 \op__insn_type$2
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
- wire width 7 \op__insn_type$2$next
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 7 output 20 \op__insn_type$3
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 7 \op__insn_type$3$next
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00000000010 "ALU"
attribute \enum_value_00100000000 "MUL"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
- wire width 11 output 20 \op__fn_unit$3
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
- wire width 11 \op__fn_unit$3$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
- wire width 64 output 21 \op__imm_data__imm$4
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
- wire width 64 \op__imm_data__imm$4$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
- wire width 1 output 22 \op__imm_data__imm_ok$5
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
- wire width 1 \op__imm_data__imm_ok$5$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
- wire width 1 output 23 \op__lk$6
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
- wire width 1 \op__lk$6$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
- wire width 1 output 24 \op__is_32bit$7
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
- wire width 1 \op__is_32bit$7$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
- wire width 32 output 25 \op__insn$8
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
- wire width 32 \op__insn$8$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 output 26 \fast1$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 \fast1$9$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 27 \fast1_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 11 output 21 \op__fn_unit$4
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 11 \op__fn_unit$4$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 output 22 \op__insn$5
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 \op__insn$5$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 output 23 \op__imm_data__imm$6
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 \op__imm_data__imm$6$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 24 \op__imm_data__imm_ok$7
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__imm_data__imm_ok$7$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 25 \op__lk$8
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__lk$8$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 26 \op__is_32bit$9
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__is_32bit$9$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 64 output 27 \fast1$10
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 64 \fast1$10$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 28 \fast1_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 \fast1_ok$next
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 output 28 \fast2$10
+ wire width 64 output 29 \fast2$11
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 \fast2$10$next
+ wire width 64 \fast2$11$next
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 29 \fast2_ok
+ wire width 1 output 30 \fast2_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 \fast2_ok$next
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 output 30 \nia
+ wire width 64 output 31 \nia
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 64 \nia$next
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 31 \nia_ok
+ wire width 1 output 32 \nia_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 \nia_ok$next
cell \p$20 \p
connect \n_valid_o \n_valid_o
connect \n_ready_i \n_ready_i
end
- attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
wire width 2 \main_muxid
- attribute \enum_base_type "InternalOp"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 \main_op__cia
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 7 \main_op__insn_type
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00100000000 "MUL"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 11 \main_op__fn_unit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 \main_op__insn
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 64 \main_op__imm_data__imm
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \main_op__imm_data__imm_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \main_op__lk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \main_op__is_32bit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
- wire width 32 \main_op__insn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
wire width 64 \main_fast1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
wire width 64 \main_fast2
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
wire width 4 \main_cr_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
- wire width 64 \main_cia
- attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
- wire width 2 \main_muxid$11
- attribute \enum_base_type "InternalOp"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+ wire width 2 \main_muxid$12
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 \main_op__cia$13
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
- wire width 7 \main_op__insn_type$12
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 7 \main_op__insn_type$14
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00000000010 "ALU"
attribute \enum_value_00100000000 "MUL"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
- wire width 11 \main_op__fn_unit$13
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
- wire width 64 \main_op__imm_data__imm$14
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
- wire width 1 \main_op__imm_data__imm_ok$15
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
- wire width 1 \main_op__lk$16
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
- wire width 1 \main_op__is_32bit$17
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
- wire width 32 \main_op__insn$18
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 \main_fast1$19
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 11 \main_op__fn_unit$15
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 \main_op__insn$16
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 \main_op__imm_data__imm$17
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \main_op__imm_data__imm_ok$18
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \main_op__lk$19
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \main_op__is_32bit$20
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 64 \main_fast1$21
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 \main_fast1_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 \main_fast2$20
+ wire width 64 \main_fast2$22
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 \main_fast2_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 \main_nia_ok
cell \main$22 \main
connect \muxid \main_muxid
+ connect \op__cia \main_op__cia
connect \op__insn_type \main_op__insn_type
connect \op__fn_unit \main_op__fn_unit
+ connect \op__insn \main_op__insn
connect \op__imm_data__imm \main_op__imm_data__imm
connect \op__imm_data__imm_ok \main_op__imm_data__imm_ok
connect \op__lk \main_op__lk
connect \op__is_32bit \main_op__is_32bit
- connect \op__insn \main_op__insn
connect \fast1 \main_fast1
connect \fast2 \main_fast2
connect \cr_a \main_cr_a
- connect \cia \main_cia
- connect \muxid$1 \main_muxid$11
- connect \op__insn_type$2 \main_op__insn_type$12
- connect \op__fn_unit$3 \main_op__fn_unit$13
- connect \op__imm_data__imm$4 \main_op__imm_data__imm$14
- connect \op__imm_data__imm_ok$5 \main_op__imm_data__imm_ok$15
- connect \op__lk$6 \main_op__lk$16
- connect \op__is_32bit$7 \main_op__is_32bit$17
- connect \op__insn$8 \main_op__insn$18
- connect \fast1$9 \main_fast1$19
+ connect \muxid$1 \main_muxid$12
+ connect \op__cia$2 \main_op__cia$13
+ connect \op__insn_type$3 \main_op__insn_type$14
+ connect \op__fn_unit$4 \main_op__fn_unit$15
+ connect \op__insn$5 \main_op__insn$16
+ connect \op__imm_data__imm$6 \main_op__imm_data__imm$17
+ connect \op__imm_data__imm_ok$7 \main_op__imm_data__imm_ok$18
+ connect \op__lk$8 \main_op__lk$19
+ connect \op__is_32bit$9 \main_op__is_32bit$20
+ connect \fast1$10 \main_fast1$21
connect \fast1_ok \main_fast1_ok
- connect \fast2$10 \main_fast2$20
+ connect \fast2$11 \main_fast2$22
connect \fast2_ok \main_fast2_ok
connect \nia \main_nia
connect \nia_ok \main_nia_ok
sync init
end
process $group_1
+ assign \main_op__cia 64'0000000000000000000000000000000000000000000000000000000000000000
assign \main_op__insn_type 7'0000000
assign \main_op__fn_unit 11'00000000000
+ assign \main_op__insn 32'00000000000000000000000000000000
assign \main_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
assign \main_op__imm_data__imm_ok 1'0
assign \main_op__lk 1'0
assign \main_op__is_32bit 1'0
- assign \main_op__insn 32'00000000000000000000000000000000
- assign { \main_op__insn \main_op__is_32bit \main_op__lk { \main_op__imm_data__imm_ok \main_op__imm_data__imm } \main_op__fn_unit \main_op__insn_type } { \op__insn \op__is_32bit \op__lk { \op__imm_data__imm_ok \op__imm_data__imm } \op__fn_unit \op__insn_type }
+ assign { \main_op__is_32bit \main_op__lk { \main_op__imm_data__imm_ok \main_op__imm_data__imm } \main_op__insn \main_op__fn_unit \main_op__insn_type \main_op__cia } { \op__is_32bit \op__lk { \op__imm_data__imm_ok \op__imm_data__imm } \op__insn \op__fn_unit \op__insn_type \op__cia }
sync init
end
- process $group_8
+ process $group_9
assign \main_fast1 64'0000000000000000000000000000000000000000000000000000000000000000
assign \main_fast1 \fast1
sync init
end
- process $group_9
+ process $group_10
assign \main_fast2 64'0000000000000000000000000000000000000000000000000000000000000000
assign \main_fast2 \fast2
sync init
end
- process $group_10
+ process $group_11
assign \main_cr_a 4'0000
assign \main_cr_a \cr_a
sync init
end
- process $group_11
- assign \main_cia 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \main_cia \cia
- sync init
- end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621"
- wire width 1 \p_valid_i$21
+ wire width 1 \p_valid_i$23
process $group_12
- assign \p_valid_i$21 1'0
- assign \p_valid_i$21 \p_valid_i
+ assign \p_valid_i$23 1'0
+ assign \p_valid_i$23 \p_valid_i
sync init
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620"
wire width 1 \p_valid_i_p_ready_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624"
- wire width 1 $22
+ wire width 1 $24
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624"
- cell $and $23
+ cell $and $25
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \p_valid_i$21
+ connect \A \p_valid_i$23
connect \B \p_ready_o
- connect \Y $22
+ connect \Y $24
end
process $group_14
assign \p_valid_i_p_ready_o 1'0
- assign \p_valid_i_p_ready_o $22
+ assign \p_valid_i_p_ready_o $24
sync init
end
- attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
- wire width 2 \muxid$24
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+ wire width 2 \muxid$26
process $group_15
- assign \muxid$24 2'00
- assign \muxid$24 \main_muxid$11
+ assign \muxid$26 2'00
+ assign \muxid$26 \main_muxid$12
sync init
end
- attribute \enum_base_type "InternalOp"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 \op__cia$27
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
- wire width 7 \op__insn_type$25
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 7 \op__insn_type$28
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00000000010 "ALU"
attribute \enum_value_00100000000 "MUL"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
- wire width 11 \op__fn_unit$26
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
- wire width 64 \op__imm_data__imm$27
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
- wire width 1 \op__imm_data__imm_ok$28
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
- wire width 1 \op__lk$29
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
- wire width 1 \op__is_32bit$30
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
- wire width 32 \op__insn$31
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 11 \op__fn_unit$29
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 \op__insn$30
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 \op__imm_data__imm$31
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__imm_data__imm_ok$32
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__lk$33
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__is_32bit$34
process $group_16
- assign \op__insn_type$25 7'0000000
- assign \op__fn_unit$26 11'00000000000
- assign \op__imm_data__imm$27 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \op__imm_data__imm_ok$28 1'0
- assign \op__lk$29 1'0
- assign \op__is_32bit$30 1'0
- assign \op__insn$31 32'00000000000000000000000000000000
- assign { \op__insn$31 \op__is_32bit$30 \op__lk$29 { \op__imm_data__imm_ok$28 \op__imm_data__imm$27 } \op__fn_unit$26 \op__insn_type$25 } { \main_op__insn$18 \main_op__is_32bit$17 \main_op__lk$16 { \main_op__imm_data__imm_ok$15 \main_op__imm_data__imm$14 } \main_op__fn_unit$13 \main_op__insn_type$12 }
+ assign \op__cia$27 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \op__insn_type$28 7'0000000
+ assign \op__fn_unit$29 11'00000000000
+ assign \op__insn$30 32'00000000000000000000000000000000
+ assign \op__imm_data__imm$31 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \op__imm_data__imm_ok$32 1'0
+ assign \op__lk$33 1'0
+ assign \op__is_32bit$34 1'0
+ assign { \op__is_32bit$34 \op__lk$33 { \op__imm_data__imm_ok$32 \op__imm_data__imm$31 } \op__insn$30 \op__fn_unit$29 \op__insn_type$28 \op__cia$27 } { \main_op__is_32bit$20 \main_op__lk$19 { \main_op__imm_data__imm_ok$18 \main_op__imm_data__imm$17 } \main_op__insn$16 \main_op__fn_unit$15 \main_op__insn_type$14 \main_op__cia$13 }
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 \fast1$32
+ wire width 64 \fast1$35
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 \fast1_ok$33
- process $group_23
- assign \fast1$32 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \fast1_ok$33 1'0
- assign { \fast1_ok$33 \fast1$32 } { \main_fast1_ok \main_fast1$19 }
+ wire width 1 \fast1_ok$36
+ process $group_24
+ assign \fast1$35 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \fast1_ok$36 1'0
+ assign { \fast1_ok$36 \fast1$35 } { \main_fast1_ok \main_fast1$21 }
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 \fast2$34
+ wire width 64 \fast2$37
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 \fast2_ok$35
- process $group_25
- assign \fast2$34 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \fast2_ok$35 1'0
- assign { \fast2_ok$35 \fast2$34 } { \main_fast2_ok \main_fast2$20 }
+ wire width 1 \fast2_ok$38
+ process $group_26
+ assign \fast2$37 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \fast2_ok$38 1'0
+ assign { \fast2_ok$38 \fast2$37 } { \main_fast2_ok \main_fast2$22 }
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 \nia$36
+ wire width 64 \nia$39
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 \nia_ok$37
- process $group_27
- assign \nia$36 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \nia_ok$37 1'0
- assign { \nia_ok$37 \nia$36 } { \main_nia_ok \main_nia }
+ wire width 1 \nia_ok$40
+ process $group_28
+ assign \nia$39 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \nia_ok$40 1'0
+ assign { \nia_ok$40 \nia$39 } { \main_nia_ok \main_nia }
sync init
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615"
wire width 1 \r_busy
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615"
wire width 1 \r_busy$next
- process $group_29
+ process $group_30
assign \r_busy$next \r_busy
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
switch { \n_i_rdy_data \p_valid_i_p_ready_o }
sync posedge \clk
update \r_busy \r_busy$next
end
- process $group_30
+ process $group_31
assign \muxid$1$next \muxid$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
switch { \n_i_rdy_data \p_valid_i_p_ready_o }
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
case 2'-1
- assign \muxid$1$next \muxid$24
+ assign \muxid$1$next \muxid$26
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
case 2'1-
- assign \muxid$1$next \muxid$24
+ assign \muxid$1$next \muxid$26
end
sync init
update \muxid$1 2'00
sync posedge \clk
update \muxid$1 \muxid$1$next
end
- process $group_31
- assign \op__insn_type$2$next \op__insn_type$2
- assign \op__fn_unit$3$next \op__fn_unit$3
- assign \op__imm_data__imm$4$next \op__imm_data__imm$4
- assign \op__imm_data__imm_ok$5$next \op__imm_data__imm_ok$5
- assign \op__lk$6$next \op__lk$6
- assign \op__is_32bit$7$next \op__is_32bit$7
- assign \op__insn$8$next \op__insn$8
+ process $group_32
+ assign \op__cia$2$next \op__cia$2
+ assign \op__insn_type$3$next \op__insn_type$3
+ assign \op__fn_unit$4$next \op__fn_unit$4
+ assign \op__insn$5$next \op__insn$5
+ assign \op__imm_data__imm$6$next \op__imm_data__imm$6
+ assign \op__imm_data__imm_ok$7$next \op__imm_data__imm_ok$7
+ assign \op__lk$8$next \op__lk$8
+ assign \op__is_32bit$9$next \op__is_32bit$9
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
switch { \n_i_rdy_data \p_valid_i_p_ready_o }
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
case 2'-1
- assign { \op__insn$8$next \op__is_32bit$7$next \op__lk$6$next { \op__imm_data__imm_ok$5$next \op__imm_data__imm$4$next } \op__fn_unit$3$next \op__insn_type$2$next } { \op__insn$31 \op__is_32bit$30 \op__lk$29 { \op__imm_data__imm_ok$28 \op__imm_data__imm$27 } \op__fn_unit$26 \op__insn_type$25 }
+ assign { \op__is_32bit$9$next \op__lk$8$next { \op__imm_data__imm_ok$7$next \op__imm_data__imm$6$next } \op__insn$5$next \op__fn_unit$4$next \op__insn_type$3$next \op__cia$2$next } { \op__is_32bit$34 \op__lk$33 { \op__imm_data__imm_ok$32 \op__imm_data__imm$31 } \op__insn$30 \op__fn_unit$29 \op__insn_type$28 \op__cia$27 }
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
case 2'1-
- assign { \op__insn$8$next \op__is_32bit$7$next \op__lk$6$next { \op__imm_data__imm_ok$5$next \op__imm_data__imm$4$next } \op__fn_unit$3$next \op__insn_type$2$next } { \op__insn$31 \op__is_32bit$30 \op__lk$29 { \op__imm_data__imm_ok$28 \op__imm_data__imm$27 } \op__fn_unit$26 \op__insn_type$25 }
+ assign { \op__is_32bit$9$next \op__lk$8$next { \op__imm_data__imm_ok$7$next \op__imm_data__imm$6$next } \op__insn$5$next \op__fn_unit$4$next \op__insn_type$3$next \op__cia$2$next } { \op__is_32bit$34 \op__lk$33 { \op__imm_data__imm_ok$32 \op__imm_data__imm$31 } \op__insn$30 \op__fn_unit$29 \op__insn_type$28 \op__cia$27 }
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
- assign \op__imm_data__imm$4$next 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \op__imm_data__imm_ok$5$next 1'0
+ assign \op__imm_data__imm$6$next 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \op__imm_data__imm_ok$7$next 1'0
end
sync init
- update \op__insn_type$2 7'0000000
- update \op__fn_unit$3 11'00000000000
- update \op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000
- update \op__imm_data__imm_ok$5 1'0
- update \op__lk$6 1'0
- update \op__is_32bit$7 1'0
- update \op__insn$8 32'00000000000000000000000000000000
+ update \op__cia$2 64'0000000000000000000000000000000000000000000000000000000000000000
+ update \op__insn_type$3 7'0000000
+ update \op__fn_unit$4 11'00000000000
+ update \op__insn$5 32'00000000000000000000000000000000
+ update \op__imm_data__imm$6 64'0000000000000000000000000000000000000000000000000000000000000000
+ update \op__imm_data__imm_ok$7 1'0
+ update \op__lk$8 1'0
+ update \op__is_32bit$9 1'0
sync posedge \clk
- update \op__insn_type$2 \op__insn_type$2$next
- update \op__fn_unit$3 \op__fn_unit$3$next
- update \op__imm_data__imm$4 \op__imm_data__imm$4$next
- update \op__imm_data__imm_ok$5 \op__imm_data__imm_ok$5$next
- update \op__lk$6 \op__lk$6$next
- update \op__is_32bit$7 \op__is_32bit$7$next
- update \op__insn$8 \op__insn$8$next
+ update \op__cia$2 \op__cia$2$next
+ update \op__insn_type$3 \op__insn_type$3$next
+ update \op__fn_unit$4 \op__fn_unit$4$next
+ update \op__insn$5 \op__insn$5$next
+ update \op__imm_data__imm$6 \op__imm_data__imm$6$next
+ update \op__imm_data__imm_ok$7 \op__imm_data__imm_ok$7$next
+ update \op__lk$8 \op__lk$8$next
+ update \op__is_32bit$9 \op__is_32bit$9$next
end
- process $group_38
- assign \fast1$9$next \fast1$9
+ process $group_40
+ assign \fast1$10$next \fast1$10
assign \fast1_ok$next \fast1_ok
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
switch { \n_i_rdy_data \p_valid_i_p_ready_o }
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
case 2'-1
- assign { \fast1_ok$next \fast1$9$next } { \fast1_ok$33 \fast1$32 }
+ assign { \fast1_ok$next \fast1$10$next } { \fast1_ok$36 \fast1$35 }
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
case 2'1-
- assign { \fast1_ok$next \fast1$9$next } { \fast1_ok$33 \fast1$32 }
+ assign { \fast1_ok$next \fast1$10$next } { \fast1_ok$36 \fast1$35 }
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
assign \fast1_ok$next 1'0
end
sync init
- update \fast1$9 64'0000000000000000000000000000000000000000000000000000000000000000
+ update \fast1$10 64'0000000000000000000000000000000000000000000000000000000000000000
update \fast1_ok 1'0
sync posedge \clk
- update \fast1$9 \fast1$9$next
+ update \fast1$10 \fast1$10$next
update \fast1_ok \fast1_ok$next
end
- process $group_40
- assign \fast2$10$next \fast2$10
+ process $group_42
+ assign \fast2$11$next \fast2$11
assign \fast2_ok$next \fast2_ok
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
switch { \n_i_rdy_data \p_valid_i_p_ready_o }
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
case 2'-1
- assign { \fast2_ok$next \fast2$10$next } { \fast2_ok$35 \fast2$34 }
+ assign { \fast2_ok$next \fast2$11$next } { \fast2_ok$38 \fast2$37 }
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
case 2'1-
- assign { \fast2_ok$next \fast2$10$next } { \fast2_ok$35 \fast2$34 }
+ assign { \fast2_ok$next \fast2$11$next } { \fast2_ok$38 \fast2$37 }
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
assign \fast2_ok$next 1'0
end
sync init
- update \fast2$10 64'0000000000000000000000000000000000000000000000000000000000000000
+ update \fast2$11 64'0000000000000000000000000000000000000000000000000000000000000000
update \fast2_ok 1'0
sync posedge \clk
- update \fast2$10 \fast2$10$next
+ update \fast2$11 \fast2$11$next
update \fast2_ok \fast2_ok$next
end
- process $group_42
+ process $group_44
assign \nia$next \nia
assign \nia_ok$next \nia_ok
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
switch { \n_i_rdy_data \p_valid_i_p_ready_o }
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
case 2'-1
- assign { \nia_ok$next \nia$next } { \nia_ok$37 \nia$36 }
+ assign { \nia_ok$next \nia$next } { \nia_ok$40 \nia$39 }
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
case 2'1-
- assign { \nia_ok$next \nia$next } { \nia_ok$37 \nia$36 }
+ assign { \nia_ok$next \nia$next } { \nia_ok$40 \nia$39 }
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
update \nia \nia$next
update \nia_ok \nia_ok$next
end
- process $group_44
+ process $group_46
assign \n_valid_o 1'0
assign \n_valid_o \r_busy
sync init
end
- process $group_45
+ process $group_47
assign \p_ready_o 1'0
assign \p_ready_o \n_i_rdy_data
sync init
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 2 \fast1_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 output 3 \fast1
+ wire width 1 output 3 \fast2_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 4 \fast2_ok
+ wire width 1 output 4 \nia_ok
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
+ wire width 1 output 5 \n_valid_o
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
+ wire width 1 input 6 \n_ready_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 output 5 \fast2
+ wire width 64 output 7 \fast1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 6 \nia_ok
+ wire width 64 output 8 \fast2
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 output 7 \nia
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244"
- wire width 1 output 8 \n_valid_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245"
- wire width 1 input 9 \n_ready_i
- attribute \enum_base_type "InternalOp"
+ wire width 64 output 9 \nia
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 input 10 \op__cia
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
- wire width 7 input 10 \op__insn_type
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 7 input 11 \op__insn_type
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00000000010 "ALU"
attribute \enum_value_00100000000 "MUL"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
- wire width 11 input 11 \op__fn_unit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
- wire width 64 input 12 \op__imm_data__imm
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
- wire width 1 input 13 \op__imm_data__imm_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
- wire width 1 input 14 \op__lk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
- wire width 1 input 15 \op__is_32bit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
- wire width 32 input 16 \op__insn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
- wire width 64 input 17 \fast1$1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
- wire width 64 input 18 \fast2$2
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
- wire width 4 input 19 \cr_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
- wire width 64 input 20 \cia
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 11 input 12 \op__fn_unit
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 input 13 \op__insn
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 input 14 \op__imm_data__imm
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 15 \op__imm_data__imm_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 16 \op__lk
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 17 \op__is_32bit
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 64 input 18 \fast1$1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 64 input 19 \fast2$2
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 4 input 20 \cr_a
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153"
wire width 1 input 21 \p_valid_i
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154"
wire width 1 output 22 \p_ready_o
cell \p$17 \p
connect \p_valid_i \p_valid_i
connect \n_valid_o \n_valid_o
connect \n_ready_i \n_ready_i
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153"
wire width 1 \pipe_p_valid_i
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154"
wire width 1 \pipe_p_ready_o
- attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
wire width 2 \pipe_muxid
- attribute \enum_base_type "InternalOp"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 \pipe_op__cia
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 7 \pipe_op__insn_type
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00100000000 "MUL"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 11 \pipe_op__fn_unit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 \pipe_op__insn
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 64 \pipe_op__imm_data__imm
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \pipe_op__imm_data__imm_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \pipe_op__lk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \pipe_op__is_32bit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
- wire width 32 \pipe_op__insn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
wire width 64 \pipe_fast1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
wire width 64 \pipe_fast2
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
wire width 4 \pipe_cr_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
- wire width 64 \pipe_cia
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
wire width 1 \pipe_n_valid_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
wire width 1 \pipe_n_ready_i
- attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
wire width 2 \pipe_muxid$3
- attribute \enum_base_type "InternalOp"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 \pipe_op__cia$4
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
- wire width 7 \pipe_op__insn_type$4
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 7 \pipe_op__insn_type$5
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00000000010 "ALU"
attribute \enum_value_00100000000 "MUL"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
- wire width 11 \pipe_op__fn_unit$5
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
- wire width 64 \pipe_op__imm_data__imm$6
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
- wire width 1 \pipe_op__imm_data__imm_ok$7
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
- wire width 1 \pipe_op__lk$8
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
- wire width 1 \pipe_op__is_32bit$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
- wire width 32 \pipe_op__insn$10
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 11 \pipe_op__fn_unit$6
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 \pipe_op__insn$7
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 \pipe_op__imm_data__imm$8
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \pipe_op__imm_data__imm_ok$9
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \pipe_op__lk$10
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \pipe_op__is_32bit$11
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 \pipe_fast1$11
+ wire width 64 \pipe_fast1$12
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 \pipe_fast1_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 \pipe_fast2$12
+ wire width 64 \pipe_fast2$13
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 \pipe_fast2_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
connect \p_valid_i \pipe_p_valid_i
connect \p_ready_o \pipe_p_ready_o
connect \muxid \pipe_muxid
+ connect \op__cia \pipe_op__cia
connect \op__insn_type \pipe_op__insn_type
connect \op__fn_unit \pipe_op__fn_unit
+ connect \op__insn \pipe_op__insn
connect \op__imm_data__imm \pipe_op__imm_data__imm
connect \op__imm_data__imm_ok \pipe_op__imm_data__imm_ok
connect \op__lk \pipe_op__lk
connect \op__is_32bit \pipe_op__is_32bit
- connect \op__insn \pipe_op__insn
connect \fast1 \pipe_fast1
connect \fast2 \pipe_fast2
connect \cr_a \pipe_cr_a
- connect \cia \pipe_cia
connect \n_valid_o \pipe_n_valid_o
connect \n_ready_i \pipe_n_ready_i
connect \muxid$1 \pipe_muxid$3
- connect \op__insn_type$2 \pipe_op__insn_type$4
- connect \op__fn_unit$3 \pipe_op__fn_unit$5
- connect \op__imm_data__imm$4 \pipe_op__imm_data__imm$6
- connect \op__imm_data__imm_ok$5 \pipe_op__imm_data__imm_ok$7
- connect \op__lk$6 \pipe_op__lk$8
- connect \op__is_32bit$7 \pipe_op__is_32bit$9
- connect \op__insn$8 \pipe_op__insn$10
- connect \fast1$9 \pipe_fast1$11
+ connect \op__cia$2 \pipe_op__cia$4
+ connect \op__insn_type$3 \pipe_op__insn_type$5
+ connect \op__fn_unit$4 \pipe_op__fn_unit$6
+ connect \op__insn$5 \pipe_op__insn$7
+ connect \op__imm_data__imm$6 \pipe_op__imm_data__imm$8
+ connect \op__imm_data__imm_ok$7 \pipe_op__imm_data__imm_ok$9
+ connect \op__lk$8 \pipe_op__lk$10
+ connect \op__is_32bit$9 \pipe_op__is_32bit$11
+ connect \fast1$10 \pipe_fast1$12
connect \fast1_ok \pipe_fast1_ok
- connect \fast2$10 \pipe_fast2$12
+ connect \fast2$11 \pipe_fast2$13
connect \fast2_ok \pipe_fast2_ok
connect \nia \pipe_nia
connect \nia_ok \pipe_nia_ok
assign \p_ready_o \pipe_p_ready_o
sync init
end
- attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
wire width 2 \muxid
process $group_2
assign \pipe_muxid 2'00
sync init
end
process $group_3
+ assign \pipe_op__cia 64'0000000000000000000000000000000000000000000000000000000000000000
assign \pipe_op__insn_type 7'0000000
assign \pipe_op__fn_unit 11'00000000000
+ assign \pipe_op__insn 32'00000000000000000000000000000000
assign \pipe_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
assign \pipe_op__imm_data__imm_ok 1'0
assign \pipe_op__lk 1'0
assign \pipe_op__is_32bit 1'0
- assign \pipe_op__insn 32'00000000000000000000000000000000
- assign { \pipe_op__insn \pipe_op__is_32bit \pipe_op__lk { \pipe_op__imm_data__imm_ok \pipe_op__imm_data__imm } \pipe_op__fn_unit \pipe_op__insn_type } { \op__insn \op__is_32bit \op__lk { \op__imm_data__imm_ok \op__imm_data__imm } \op__fn_unit \op__insn_type }
+ assign { \pipe_op__is_32bit \pipe_op__lk { \pipe_op__imm_data__imm_ok \pipe_op__imm_data__imm } \pipe_op__insn \pipe_op__fn_unit \pipe_op__insn_type \pipe_op__cia } { \op__is_32bit \op__lk { \op__imm_data__imm_ok \op__imm_data__imm } \op__insn \op__fn_unit \op__insn_type \op__cia }
sync init
end
- process $group_10
+ process $group_11
assign \pipe_fast1 64'0000000000000000000000000000000000000000000000000000000000000000
assign \pipe_fast1 \fast1$1
sync init
end
- process $group_11
+ process $group_12
assign \pipe_fast2 64'0000000000000000000000000000000000000000000000000000000000000000
assign \pipe_fast2 \fast2$2
sync init
end
- process $group_12
+ process $group_13
assign \pipe_cr_a 4'0000
assign \pipe_cr_a \cr_a
sync init
end
- process $group_13
- assign \pipe_cia 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \pipe_cia \cia
- sync init
- end
process $group_14
assign \n_valid_o 1'0
assign \n_valid_o \pipe_n_valid_o
assign \pipe_n_ready_i \n_ready_i
sync init
end
- attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
- wire width 2 \muxid$13
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+ wire width 2 \muxid$14
process $group_16
- assign \muxid$13 2'00
- assign \muxid$13 \pipe_muxid$3
+ assign \muxid$14 2'00
+ assign \muxid$14 \pipe_muxid$3
sync init
end
- attribute \enum_base_type "InternalOp"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 \op__cia$15
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
- wire width 7 \op__insn_type$14
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 7 \op__insn_type$16
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00000000010 "ALU"
attribute \enum_value_00100000000 "MUL"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
- wire width 11 \op__fn_unit$15
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
- wire width 64 \op__imm_data__imm$16
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
- wire width 1 \op__imm_data__imm_ok$17
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
- wire width 1 \op__lk$18
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
- wire width 1 \op__is_32bit$19
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
- wire width 32 \op__insn$20
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 11 \op__fn_unit$17
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 \op__insn$18
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 \op__imm_data__imm$19
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__imm_data__imm_ok$20
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__lk$21
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__is_32bit$22
process $group_17
- assign \op__insn_type$14 7'0000000
- assign \op__fn_unit$15 11'00000000000
- assign \op__imm_data__imm$16 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \op__imm_data__imm_ok$17 1'0
- assign \op__lk$18 1'0
- assign \op__is_32bit$19 1'0
- assign \op__insn$20 32'00000000000000000000000000000000
- assign { \op__insn$20 \op__is_32bit$19 \op__lk$18 { \op__imm_data__imm_ok$17 \op__imm_data__imm$16 } \op__fn_unit$15 \op__insn_type$14 } { \pipe_op__insn$10 \pipe_op__is_32bit$9 \pipe_op__lk$8 { \pipe_op__imm_data__imm_ok$7 \pipe_op__imm_data__imm$6 } \pipe_op__fn_unit$5 \pipe_op__insn_type$4 }
+ assign \op__cia$15 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \op__insn_type$16 7'0000000
+ assign \op__fn_unit$17 11'00000000000
+ assign \op__insn$18 32'00000000000000000000000000000000
+ assign \op__imm_data__imm$19 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \op__imm_data__imm_ok$20 1'0
+ assign \op__lk$21 1'0
+ assign \op__is_32bit$22 1'0
+ assign { \op__is_32bit$22 \op__lk$21 { \op__imm_data__imm_ok$20 \op__imm_data__imm$19 } \op__insn$18 \op__fn_unit$17 \op__insn_type$16 \op__cia$15 } { \pipe_op__is_32bit$11 \pipe_op__lk$10 { \pipe_op__imm_data__imm_ok$9 \pipe_op__imm_data__imm$8 } \pipe_op__insn$7 \pipe_op__fn_unit$6 \pipe_op__insn_type$5 \pipe_op__cia$4 }
sync init
end
- process $group_24
+ process $group_25
assign \fast1 64'0000000000000000000000000000000000000000000000000000000000000000
assign \fast1_ok 1'0
- assign { \fast1_ok \fast1 } { \pipe_fast1_ok \pipe_fast1$11 }
+ assign { \fast1_ok \fast1 } { \pipe_fast1_ok \pipe_fast1$12 }
sync init
end
- process $group_26
+ process $group_27
assign \fast2 64'0000000000000000000000000000000000000000000000000000000000000000
assign \fast2_ok 1'0
- assign { \fast2_ok \fast2 } { \pipe_fast2_ok \pipe_fast2$12 }
+ assign { \fast2_ok \fast2 } { \pipe_fast2_ok \pipe_fast2$13 }
sync init
end
- process $group_28
+ process $group_29
assign \nia 64'0000000000000000000000000000000000000000000000000000000000000000
assign \nia_ok 1'0
assign { \nia_ok \nia } { \pipe_nia_ok \pipe_nia }
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
- wire width 4 input 2 \s_src
+ wire width 3 input 2 \s_src
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
- wire width 4 input 3 \r_src
+ wire width 3 input 3 \r_src
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
- wire width 4 output 4 \q_src
+ wire width 3 output 4 \q_src
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
- wire width 4 \q_int
+ wire width 3 \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
- wire width 4 \q_int$next
+ wire width 3 \q_int$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
- wire width 4 $1
+ wire width 3 $1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
cell $not $2
parameter \A_SIGNED 0
- parameter \A_WIDTH 4
- parameter \Y_WIDTH 4
+ parameter \A_WIDTH 3
+ parameter \Y_WIDTH 3
connect \A \r_src
connect \Y $1
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
- wire width 4 $3
+ wire width 3 $3
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
cell $and $4
parameter \A_SIGNED 0
- parameter \A_WIDTH 4
+ parameter \A_WIDTH 3
parameter \B_SIGNED 0
- parameter \B_WIDTH 4
- parameter \Y_WIDTH 4
+ parameter \B_WIDTH 3
+ parameter \Y_WIDTH 3
connect \A \q_int
connect \B $1
connect \Y $3
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
- wire width 4 $5
+ wire width 3 $5
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
cell $or $6
parameter \A_SIGNED 0
- parameter \A_WIDTH 4
+ parameter \A_WIDTH 3
parameter \B_SIGNED 0
- parameter \B_WIDTH 4
- parameter \Y_WIDTH 4
+ parameter \B_WIDTH 3
+ parameter \Y_WIDTH 3
connect \A $3
connect \B \s_src
connect \Y $5
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
- assign \q_int$next 4'0000
+ assign \q_int$next 3'000
end
sync init
- update \q_int 4'0000
+ update \q_int 3'000
sync posedge \clk
update \q_int \q_int$next
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
- wire width 4 $7
+ wire width 3 $7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
cell $not $8
parameter \A_SIGNED 0
- parameter \A_WIDTH 4
- parameter \Y_WIDTH 4
+ parameter \A_WIDTH 3
+ parameter \Y_WIDTH 3
connect \A \r_src
connect \Y $7
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
- wire width 4 $9
+ wire width 3 $9
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
cell $and $10
parameter \A_SIGNED 0
- parameter \A_WIDTH 4
+ parameter \A_WIDTH 3
parameter \B_SIGNED 0
- parameter \B_WIDTH 4
- parameter \Y_WIDTH 4
+ parameter \B_WIDTH 3
+ parameter \Y_WIDTH 3
connect \A \q_int
connect \B $7
connect \Y $9
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
- wire width 4 $11
+ wire width 3 $11
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
cell $or $12
parameter \A_SIGNED 0
- parameter \A_WIDTH 4
+ parameter \A_WIDTH 3
parameter \B_SIGNED 0
- parameter \B_WIDTH 4
- parameter \Y_WIDTH 4
+ parameter \B_WIDTH 3
+ parameter \Y_WIDTH 3
connect \A $9
connect \B \s_src
connect \Y $11
end
process $group_1
- assign \q_src 4'0000
+ assign \q_src 3'000
assign \q_src $11
sync init
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
- wire width 4 \qn_src
+ wire width 3 \qn_src
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
- wire width 4 $13
+ wire width 3 $13
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
cell $not $14
parameter \A_SIGNED 0
- parameter \A_WIDTH 4
- parameter \Y_WIDTH 4
+ parameter \A_WIDTH 3
+ parameter \Y_WIDTH 3
connect \A \q_src
connect \Y $13
end
process $group_2
- assign \qn_src 4'0000
+ assign \qn_src 3'000
assign \qn_src $13
sync init
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62"
- wire width 4 \qlq_src
+ wire width 3 \qlq_src
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
- wire width 4 $15
+ wire width 3 $15
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
cell $or $16
parameter \A_SIGNED 0
- parameter \A_WIDTH 4
+ parameter \A_WIDTH 3
parameter \B_SIGNED 0
- parameter \B_WIDTH 4
- parameter \Y_WIDTH 4
+ parameter \B_WIDTH 3
+ parameter \Y_WIDTH 3
connect \A \q_src
connect \B \q_int
connect \Y $15
end
process $group_3
- assign \qlq_src 4'0000
+ assign \qlq_src 3'000
assign \qlq_src $15
sync init
end
wire width 1 input 0 \rst
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
- attribute \enum_base_type "InternalOp"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 input 2 \oper_i__cia
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
- wire width 7 input 2 \oper_i__insn_type
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 7 input 3 \oper_i__insn_type
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00000000010 "ALU"
attribute \enum_value_00100000000 "MUL"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
- wire width 11 input 3 \oper_i__fn_unit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
- wire width 64 input 4 \oper_i__imm_data__imm
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
- wire width 1 input 5 \oper_i__imm_data__imm_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
- wire width 1 input 6 \oper_i__lk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
- wire width 1 input 7 \oper_i__is_32bit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
- wire width 32 input 8 \oper_i__insn
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 11 input 4 \oper_i__fn_unit
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 input 5 \oper_i__insn
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 input 6 \oper_i__imm_data__imm
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 7 \oper_i__imm_data__imm_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 8 \oper_i__lk
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 9 \oper_i__is_32bit
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94"
- wire width 1 input 9 \issue_i
+ wire width 1 input 10 \issue_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
- wire width 1 output 10 \busy_o
+ wire width 1 output 11 \busy_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:92"
- wire width 4 input 11 \rdmaskn
+ wire width 3 input 12 \rdmaskn
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 4 output 12 \rd__rel
+ wire width 3 output 13 \rd__rel
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 4 input 13 \rd__go
+ wire width 3 input 14 \rd__go
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
- wire width 4 input 14 \src3_i
+ wire width 4 input 15 \src3_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
- wire width 64 input 15 \src1_i
+ wire width 64 input 16 \src1_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
- wire width 64 input 16 \src2_i
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
- wire width 64 input 17 \src4_i
+ wire width 64 input 17 \src2_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 18 \fast1_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
wire width 3 output 19 \wr__rel
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
wire width 3 input 20 \wr__go
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 output 21 \fast1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
+ wire width 64 output 21 \dest1_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 22 \fast2_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 output 23 \fast2
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
+ wire width 64 output 23 \dest2_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 24 \nia_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 output 25 \nia
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
+ wire width 64 output 25 \dest3_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96"
wire width 1 input 26 \go_die_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
wire width 1 input 27 \shadown_i
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
- wire width 64 output 28 \dest1_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
wire width 1 \alu_branch0_n_valid_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
wire width 1 \alu_branch0_n_ready_i
- attribute \enum_base_type "InternalOp"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 64 \alu_branch0_fast1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 64 \alu_branch0_fast2
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 64 \alu_branch0_nia
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 \alu_branch0_op__cia
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 7 \alu_branch0_op__insn_type
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00100000000 "MUL"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 11 \alu_branch0_op__fn_unit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 \alu_branch0_op__insn
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 64 \alu_branch0_op__imm_data__imm
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \alu_branch0_op__imm_data__imm_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \alu_branch0_op__lk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \alu_branch0_op__is_32bit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
- wire width 32 \alu_branch0_op__insn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
- wire width 64 \alu_branch0_fast1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
- wire width 64 \alu_branch0_fast2
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 64 \alu_branch0_fast1$1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 64 \alu_branch0_fast2$2
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
wire width 4 \alu_branch0_cr_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
- wire width 64 \alu_branch0_cia
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153"
wire width 1 \alu_branch0_p_valid_i
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154"
wire width 1 \alu_branch0_p_ready_o
cell \alu_branch0 \alu_branch0
connect \rst \rst
connect \clk \clk
connect \fast1_ok \fast1_ok
- connect \fast1 \fast1
connect \fast2_ok \fast2_ok
- connect \fast2 \fast2
connect \nia_ok \nia_ok
- connect \nia \nia
connect \n_valid_o \alu_branch0_n_valid_o
connect \n_ready_i \alu_branch0_n_ready_i
+ connect \fast1 \alu_branch0_fast1
+ connect \fast2 \alu_branch0_fast2
+ connect \nia \alu_branch0_nia
+ connect \op__cia \alu_branch0_op__cia
connect \op__insn_type \alu_branch0_op__insn_type
connect \op__fn_unit \alu_branch0_op__fn_unit
+ connect \op__insn \alu_branch0_op__insn
connect \op__imm_data__imm \alu_branch0_op__imm_data__imm
connect \op__imm_data__imm_ok \alu_branch0_op__imm_data__imm_ok
connect \op__lk \alu_branch0_op__lk
connect \op__is_32bit \alu_branch0_op__is_32bit
- connect \op__insn \alu_branch0_op__insn
- connect \fast1$1 \alu_branch0_fast1
- connect \fast2$2 \alu_branch0_fast2
+ connect \fast1$1 \alu_branch0_fast1$1
+ connect \fast2$2 \alu_branch0_fast2$2
connect \cr_a \alu_branch0_cr_a
- connect \cia \alu_branch0_cia
connect \p_valid_i \alu_branch0_p_valid_i
connect \p_ready_o \alu_branch0_p_ready_o
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
- wire width 4 \src_l_s_src
+ wire width 3 \src_l_s_src
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
- wire width 4 \src_l_s_src$next
+ wire width 3 \src_l_s_src$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
- wire width 4 \src_l_r_src
+ wire width 3 \src_l_r_src
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
- wire width 4 \src_l_r_src$next
+ wire width 3 \src_l_r_src$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
- wire width 4 \src_l_q_src
+ wire width 3 \src_l_q_src
cell \src_l$23 \src_l
connect \rst \rst
connect \clk \clk
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:178"
wire width 1 \all_rd
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179"
- wire width 1 $1
+ wire width 1 $3
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179"
- cell $and $2
+ cell $and $4
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \busy_o
connect \B \rok_l_q_rdok
- connect \Y $1
+ connect \Y $3
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180"
- wire width 1 $3
+ wire width 1 $5
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180"
- wire width 4 $4
+ wire width 3 $6
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180"
- cell $not $5
+ cell $not $7
parameter \A_SIGNED 0
- parameter \A_WIDTH 4
- parameter \Y_WIDTH 4
+ parameter \A_WIDTH 3
+ parameter \Y_WIDTH 3
connect \A \rd__rel
- connect \Y $4
+ connect \Y $6
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180"
- wire width 4 $6
+ wire width 3 $8
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180"
- cell $or $7
+ cell $or $9
parameter \A_SIGNED 0
- parameter \A_WIDTH 4
+ parameter \A_WIDTH 3
parameter \B_SIGNED 0
- parameter \B_WIDTH 4
- parameter \Y_WIDTH 4
- connect \A $4
+ parameter \B_WIDTH 3
+ parameter \Y_WIDTH 3
+ connect \A $6
connect \B \rd__go
- connect \Y $6
+ connect \Y $8
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180"
- cell $reduce_and $8
+ cell $reduce_and $10
parameter \A_SIGNED 0
- parameter \A_WIDTH 4
+ parameter \A_WIDTH 3
parameter \Y_WIDTH 1
- connect \A $6
- connect \Y $3
+ connect \A $8
+ connect \Y $5
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180"
- wire width 1 $9
+ wire width 1 $11
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180"
- cell $and $10
+ cell $and $12
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $1
- connect \B $3
- connect \Y $9
+ connect \A $3
+ connect \B $5
+ connect \Y $11
end
process $group_0
assign \all_rd 1'0
- assign \all_rd $9
+ assign \all_rd $11
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:183"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:184"
wire width 1 \all_rd_pulse
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:186"
- wire width 1 $11
+ wire width 1 $13
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:186"
- cell $not $12
+ cell $not $14
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \all_rd_dly
- connect \Y $11
+ connect \Y $13
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:186"
- wire width 1 $13
+ wire width 1 $15
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:186"
- cell $and $14
+ cell $and $16
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \all_rd
- connect \B $11
- connect \Y $13
+ connect \B $13
+ connect \Y $15
end
process $group_2
assign \all_rd_pulse 1'0
- assign \all_rd_pulse $13
+ assign \all_rd_pulse $15
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:191"
wire width 1 \alu_pulse
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:195"
- wire width 1 $15
+ wire width 1 $17
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:195"
- cell $not $16
+ cell $not $18
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \alu_done_dly
- connect \Y $15
+ connect \Y $17
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:195"
- wire width 1 $17
+ wire width 1 $19
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:195"
- cell $and $18
+ cell $and $20
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \alu_done
- connect \B $15
- connect \Y $17
+ connect \B $17
+ connect \Y $19
end
process $group_5
assign \alu_pulse 1'0
- assign \alu_pulse $17
+ assign \alu_pulse $19
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:192"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:199"
wire width 3 \prev_wr_go$next
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:201"
- wire width 3 $19
+ wire width 3 $21
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:201"
- cell $and $20
+ cell $and $22
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \wr__go
connect \B { \busy_o \busy_o \busy_o }
- connect \Y $19
+ connect \Y $21
end
process $group_7
assign \prev_wr_go$next \prev_wr_go
- assign \prev_wr_go$next $19
+ assign \prev_wr_go$next $21
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100"
wire width 1 \done_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
- wire width 1 $21
+ wire width 1 $23
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
- wire width 1 $22
+ wire width 1 $24
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
- wire width 3 $23
+ wire width 3 $25
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:93"
wire width 3 \wrmask
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
- cell $not $24
+ cell $not $26
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 3
connect \A \wrmask
- connect \Y $23
+ connect \Y $25
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
- wire width 3 $25
+ wire width 3 $27
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
- cell $and $26
+ cell $and $28
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \B_WIDTH 3
parameter \Y_WIDTH 3
connect \A \wr__rel
- connect \B $23
- connect \Y $25
+ connect \B $25
+ connect \Y $27
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
- cell $reduce_bool $27
+ cell $reduce_bool $29
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 1
- connect \A $25
- connect \Y $22
+ connect \A $27
+ connect \Y $24
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
- cell $not $28
+ cell $not $30
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $22
- connect \Y $21
+ connect \A $24
+ connect \Y $23
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
- wire width 1 $29
+ wire width 1 $31
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
- cell $and $30
+ cell $and $32
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \busy_o
- connect \B $21
- connect \Y $29
+ connect \B $23
+ connect \Y $31
end
process $group_8
assign \done_o 1'0
- assign \done_o $29
+ assign \done_o $31
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206"
wire width 1 \wr_any
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210"
- wire width 1 $31
+ wire width 1 $33
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210"
- cell $reduce_bool $32
+ cell $reduce_bool $34
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 1
connect \A \wr__go
- connect \Y $31
+ connect \Y $33
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210"
- wire width 1 $33
+ wire width 1 $35
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210"
- cell $reduce_bool $34
+ cell $reduce_bool $36
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 1
connect \A \prev_wr_go
- connect \Y $33
+ connect \Y $35
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210"
- wire width 1 $35
+ wire width 1 $37
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210"
- cell $or $36
+ cell $or $38
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $31
- connect \B $33
- connect \Y $35
+ connect \A $33
+ connect \B $35
+ connect \Y $37
end
process $group_9
assign \wr_any 1'0
- assign \wr_any $35
+ assign \wr_any $37
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:207"
wire width 1 \req_done
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211"
- wire width 1 $37
+ wire width 1 $39
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211"
- cell $not $38
+ cell $not $40
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \alu_branch0_n_ready_i
- connect \Y $37
+ connect \Y $39
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211"
- wire width 1 $39
+ wire width 1 $41
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211"
- cell $and $40
+ cell $and $42
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \wr_any
- connect \B $37
- connect \Y $39
+ connect \B $39
+ connect \Y $41
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212"
- wire width 3 $41
+ wire width 3 $43
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212"
- cell $and $42
+ cell $and $44
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \req_l_q_req
connect \B \wrmask
- connect \Y $41
+ connect \Y $43
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212"
- wire width 1 $43
+ wire width 1 $45
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212"
- cell $eq $44
+ cell $eq $46
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $41
+ connect \A $43
connect \B 1'0
- connect \Y $43
+ connect \Y $45
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212"
- wire width 1 $45
+ wire width 1 $47
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212"
- cell $and $46
+ cell $and $48
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $39
- connect \B $43
- connect \Y $45
+ connect \A $41
+ connect \B $45
+ connect \Y $47
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
- wire width 1 $47
+ wire width 1 $49
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
- cell $eq $48
+ cell $eq $50
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wrmask
connect \B 1'0
- connect \Y $47
+ connect \Y $49
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
- wire width 1 $49
+ wire width 1 $51
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
- cell $and $50
+ cell $and $52
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $47
+ connect \A $49
connect \B \alu_branch0_n_ready_i
- connect \Y $49
+ connect \Y $51
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
- wire width 1 $51
+ wire width 1 $53
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
- cell $and $52
+ cell $and $54
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $49
+ connect \A $51
connect \B \alu_branch0_n_valid_o
- connect \Y $51
+ connect \Y $53
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
- wire width 1 $53
+ wire width 1 $55
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
- cell $and $54
+ cell $and $56
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $51
+ connect \A $53
connect \B \busy_o
- connect \Y $53
+ connect \Y $55
end
process $group_10
assign \req_done 1'0
- assign \req_done $45
+ assign \req_done $47
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
- switch { $53 }
+ switch { $55 }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
case 1'1
assign \req_done 1'1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:221"
wire width 1 \reset
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
- wire width 1 $55
+ wire width 1 $57
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
- cell $or $56
+ cell $or $58
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \req_done
connect \B \go_die_i
- connect \Y $55
+ connect \Y $57
end
process $group_11
assign \reset 1'0
- assign \reset $55
+ assign \reset $57
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222"
wire width 1 \rst_r
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226"
- wire width 1 $57
+ wire width 1 $59
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226"
- cell $or $58
+ cell $or $60
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \issue_i
connect \B \go_die_i
- connect \Y $57
+ connect \Y $59
end
process $group_12
assign \rst_r 1'0
- assign \rst_r $57
+ assign \rst_r $59
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:223"
wire width 3 \reset_w
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227"
- wire width 3 $59
+ wire width 3 $61
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227"
- cell $or $60
+ cell $or $62
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \wr__go
connect \B { \go_die_i \go_die_i \go_die_i }
- connect \Y $59
+ connect \Y $61
end
process $group_13
assign \reset_w 3'000
- assign \reset_w $59
+ assign \reset_w $61
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:224"
- wire width 4 \reset_r
+ wire width 3 \reset_r
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:228"
- wire width 4 $61
+ wire width 3 $63
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:228"
- cell $or $62
+ cell $or $64
parameter \A_SIGNED 0
- parameter \A_WIDTH 4
+ parameter \A_WIDTH 3
parameter \B_SIGNED 0
- parameter \B_WIDTH 4
- parameter \Y_WIDTH 4
+ parameter \B_WIDTH 3
+ parameter \Y_WIDTH 3
connect \A \rd__go
- connect \B { \go_die_i \go_die_i \go_die_i \go_die_i }
- connect \Y $61
+ connect \B { \go_die_i \go_die_i \go_die_i }
+ connect \Y $63
end
process $group_14
- assign \reset_r 4'0000
- assign \reset_r $61
+ assign \reset_r 3'000
+ assign \reset_r $63
sync init
end
process $group_15
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232"
- wire width 1 $63
+ wire width 1 $65
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232"
- cell $and $64
+ cell $and $66
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \alu_branch0_n_valid_o
connect \B \busy_o
- connect \Y $63
+ connect \Y $65
end
process $group_16
assign \rok_l_r_rdok$next \rok_l_r_rdok
- assign \rok_l_r_rdok$next $63
+ assign \rok_l_r_rdok$next $65
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
end
process $group_21
assign \src_l_s_src$next \src_l_s_src
- assign \src_l_s_src$next { \issue_i \issue_i \issue_i \issue_i }
+ assign \src_l_s_src$next { \issue_i \issue_i \issue_i }
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
- assign \src_l_s_src$next 4'0000
+ assign \src_l_s_src$next 3'000
end
sync init
- update \src_l_s_src 4'0000
+ update \src_l_s_src 3'000
sync posedge \clk
update \src_l_s_src \src_l_s_src$next
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
- assign \src_l_r_src$next 4'1111
+ assign \src_l_r_src$next 3'111
end
sync init
- update \src_l_r_src 4'1111
+ update \src_l_r_src 3'111
sync posedge \clk
update \src_l_r_src \src_l_r_src$next
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:247"
- wire width 3 $65
+ wire width 3 $67
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:247"
- cell $and $66
+ cell $and $68
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \alu_pulsem
connect \B \wrmask
- connect \Y $65
+ connect \Y $67
end
process $group_23
assign \req_l_s_req 3'000
- assign \req_l_s_req $65
+ assign \req_l_s_req $67
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:248"
- wire width 3 $67
+ wire width 3 $69
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:248"
- cell $or $68
+ cell $or $70
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \reset_w
connect \B \prev_wr_go
- connect \Y $67
+ connect \Y $69
end
process $group_24
assign \req_l_r_req 3'111
- assign \req_l_r_req $67
+ assign \req_l_r_req $69
sync init
end
- attribute \enum_base_type "InternalOp"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 \oper_r__cia
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 7 \oper_r__insn_type
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00100000000 "MUL"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 11 \oper_r__fn_unit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 \oper_r__insn
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 64 \oper_r__imm_data__imm
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \oper_r__imm_data__imm_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \oper_r__lk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \oper_r__is_32bit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
- wire width 32 \oper_r__insn
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+ wire width 64 \oper_l__cia
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+ wire width 64 \oper_l__cia$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
wire width 7 \oper_l__insn_type
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
wire width 11 \oper_l__fn_unit$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+ wire width 32 \oper_l__insn
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+ wire width 32 \oper_l__insn$next
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
wire width 64 \oper_l__imm_data__imm
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
wire width 64 \oper_l__imm_data__imm$next
wire width 1 \oper_l__is_32bit
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
wire width 1 \oper_l__is_32bit$next
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
- wire width 32 \oper_l__insn
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
- wire width 32 \oper_l__insn$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
- wire width 117 $69
+ wire width 181 $71
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
- cell $mux $70
- parameter \WIDTH 117
- connect \A { \oper_l__insn \oper_l__is_32bit \oper_l__lk { \oper_l__imm_data__imm_ok \oper_l__imm_data__imm } \oper_l__fn_unit \oper_l__insn_type }
- connect \B { \oper_i__insn \oper_i__is_32bit \oper_i__lk { \oper_i__imm_data__imm_ok \oper_i__imm_data__imm } \oper_i__fn_unit \oper_i__insn_type }
+ cell $mux $72
+ parameter \WIDTH 181
+ connect \A { \oper_l__is_32bit \oper_l__lk { \oper_l__imm_data__imm_ok \oper_l__imm_data__imm } \oper_l__insn \oper_l__fn_unit \oper_l__insn_type \oper_l__cia }
+ connect \B { \oper_i__is_32bit \oper_i__lk { \oper_i__imm_data__imm_ok \oper_i__imm_data__imm } \oper_i__insn \oper_i__fn_unit \oper_i__insn_type \oper_i__cia }
connect \S \issue_i
- connect \Y $69
+ connect \Y $71
end
process $group_25
+ assign \oper_r__cia 64'0000000000000000000000000000000000000000000000000000000000000000
assign \oper_r__insn_type 7'0000000
assign \oper_r__fn_unit 11'00000000000
+ assign \oper_r__insn 32'00000000000000000000000000000000
assign \oper_r__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
assign \oper_r__imm_data__imm_ok 1'0
assign \oper_r__lk 1'0
assign \oper_r__is_32bit 1'0
- assign \oper_r__insn 32'00000000000000000000000000000000
- assign { \oper_r__insn \oper_r__is_32bit \oper_r__lk { \oper_r__imm_data__imm_ok \oper_r__imm_data__imm } \oper_r__fn_unit \oper_r__insn_type } $69
+ assign { \oper_r__is_32bit \oper_r__lk { \oper_r__imm_data__imm_ok \oper_r__imm_data__imm } \oper_r__insn \oper_r__fn_unit \oper_r__insn_type \oper_r__cia } $71
sync init
end
- process $group_32
+ process $group_33
+ assign \oper_l__cia$next \oper_l__cia
assign \oper_l__insn_type$next \oper_l__insn_type
assign \oper_l__fn_unit$next \oper_l__fn_unit
+ assign \oper_l__insn$next \oper_l__insn
assign \oper_l__imm_data__imm$next \oper_l__imm_data__imm
assign \oper_l__imm_data__imm_ok$next \oper_l__imm_data__imm_ok
assign \oper_l__lk$next \oper_l__lk
assign \oper_l__is_32bit$next \oper_l__is_32bit
- assign \oper_l__insn$next \oper_l__insn
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
switch { \issue_i }
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
case 1'1
- assign { \oper_l__insn$next \oper_l__is_32bit$next \oper_l__lk$next { \oper_l__imm_data__imm_ok$next \oper_l__imm_data__imm$next } \oper_l__fn_unit$next \oper_l__insn_type$next } { \oper_i__insn \oper_i__is_32bit \oper_i__lk { \oper_i__imm_data__imm_ok \oper_i__imm_data__imm } \oper_i__fn_unit \oper_i__insn_type }
+ assign { \oper_l__is_32bit$next \oper_l__lk$next { \oper_l__imm_data__imm_ok$next \oper_l__imm_data__imm$next } \oper_l__insn$next \oper_l__fn_unit$next \oper_l__insn_type$next \oper_l__cia$next } { \oper_i__is_32bit \oper_i__lk { \oper_i__imm_data__imm_ok \oper_i__imm_data__imm } \oper_i__insn \oper_i__fn_unit \oper_i__insn_type \oper_i__cia }
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
assign \oper_l__imm_data__imm_ok$next 1'0
end
sync init
+ update \oper_l__cia 64'0000000000000000000000000000000000000000000000000000000000000000
update \oper_l__insn_type 7'0000000
update \oper_l__fn_unit 11'00000000000
+ update \oper_l__insn 32'00000000000000000000000000000000
update \oper_l__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
update \oper_l__imm_data__imm_ok 1'0
update \oper_l__lk 1'0
update \oper_l__is_32bit 1'0
- update \oper_l__insn 32'00000000000000000000000000000000
sync posedge \clk
+ update \oper_l__cia \oper_l__cia$next
update \oper_l__insn_type \oper_l__insn_type$next
update \oper_l__fn_unit \oper_l__fn_unit$next
+ update \oper_l__insn \oper_l__insn$next
update \oper_l__imm_data__imm \oper_l__imm_data__imm$next
update \oper_l__imm_data__imm_ok \oper_l__imm_data__imm_ok$next
update \oper_l__lk \oper_l__lk$next
update \oper_l__is_32bit \oper_l__is_32bit$next
- update \oper_l__insn \oper_l__insn$next
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262"
wire width 64 \data_r0__fast1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
wire width 1 \data_r0_l__fast1_ok$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
- wire width 65 $71
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:730"
- wire width 1 $72
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:730"
- cell $reduce_bool $73
+ wire width 65 $73
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744"
+ wire width 1 $74
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744"
+ cell $reduce_bool $75
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 1
connect \A \alu_pulsem
- connect \Y $72
+ connect \Y $74
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
- cell $mux $74
+ cell $mux $76
parameter \WIDTH 65
connect \A { \data_r0_l__fast1_ok \data_r0_l__fast1 }
- connect \B { \fast1_ok \fast1 }
- connect \S $72
- connect \Y $71
+ connect \B { \fast1_ok \alu_branch0_fast1 }
+ connect \S $74
+ connect \Y $73
end
- process $group_39
+ process $group_41
assign \data_r0__fast1 64'0000000000000000000000000000000000000000000000000000000000000000
assign \data_r0__fast1_ok 1'0
- assign { \data_r0__fast1_ok \data_r0__fast1 } $71
+ assign { \data_r0__fast1_ok \data_r0__fast1 } $73
sync init
end
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
- wire width 1 $75
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
- cell $reduce_bool $76
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
+ wire width 1 $77
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
+ cell $reduce_bool $78
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 1
connect \A \alu_pulsem
- connect \Y $75
+ connect \Y $77
end
- process $group_41
+ process $group_43
assign \data_r0_l__fast1$next \data_r0_l__fast1
assign \data_r0_l__fast1_ok$next \data_r0_l__fast1_ok
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
- switch { $75 }
+ switch { $77 }
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
case 1'1
- assign { \data_r0_l__fast1_ok$next \data_r0_l__fast1$next } { \fast1_ok \fast1 }
+ assign { \data_r0_l__fast1_ok$next \data_r0_l__fast1$next } { \fast1_ok \alu_branch0_fast1 }
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
wire width 1 \data_r1_l__fast2_ok$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
- wire width 65 $77
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:730"
- wire width 1 $78
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:730"
- cell $reduce_bool $79
+ wire width 65 $79
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744"
+ wire width 1 $80
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744"
+ cell $reduce_bool $81
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 1
connect \A \alu_pulsem
- connect \Y $78
+ connect \Y $80
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
- cell $mux $80
+ cell $mux $82
parameter \WIDTH 65
connect \A { \data_r1_l__fast2_ok \data_r1_l__fast2 }
- connect \B { \fast2_ok \fast2 }
- connect \S $78
- connect \Y $77
+ connect \B { \fast2_ok \alu_branch0_fast2 }
+ connect \S $80
+ connect \Y $79
end
- process $group_43
+ process $group_45
assign \data_r1__fast2 64'0000000000000000000000000000000000000000000000000000000000000000
assign \data_r1__fast2_ok 1'0
- assign { \data_r1__fast2_ok \data_r1__fast2 } $77
+ assign { \data_r1__fast2_ok \data_r1__fast2 } $79
sync init
end
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
- wire width 1 $81
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
- cell $reduce_bool $82
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
+ wire width 1 $83
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
+ cell $reduce_bool $84
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 1
connect \A \alu_pulsem
- connect \Y $81
+ connect \Y $83
end
- process $group_45
+ process $group_47
assign \data_r1_l__fast2$next \data_r1_l__fast2
assign \data_r1_l__fast2_ok$next \data_r1_l__fast2_ok
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
- switch { $81 }
+ switch { $83 }
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
case 1'1
- assign { \data_r1_l__fast2_ok$next \data_r1_l__fast2$next } { \fast2_ok \fast2 }
+ assign { \data_r1_l__fast2_ok$next \data_r1_l__fast2$next } { \fast2_ok \alu_branch0_fast2 }
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
wire width 1 \data_r2_l__nia_ok$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
- wire width 65 $83
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:730"
- wire width 1 $84
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:730"
- cell $reduce_bool $85
+ wire width 65 $85
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744"
+ wire width 1 $86
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744"
+ cell $reduce_bool $87
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 1
connect \A \alu_pulsem
- connect \Y $84
+ connect \Y $86
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
- cell $mux $86
+ cell $mux $88
parameter \WIDTH 65
connect \A { \data_r2_l__nia_ok \data_r2_l__nia }
- connect \B { \nia_ok \nia }
- connect \S $84
- connect \Y $83
+ connect \B { \nia_ok \alu_branch0_nia }
+ connect \S $86
+ connect \Y $85
end
- process $group_47
+ process $group_49
assign \data_r2__nia 64'0000000000000000000000000000000000000000000000000000000000000000
assign \data_r2__nia_ok 1'0
- assign { \data_r2__nia_ok \data_r2__nia } $83
+ assign { \data_r2__nia_ok \data_r2__nia } $85
sync init
end
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
- wire width 1 $87
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
- cell $reduce_bool $88
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
+ wire width 1 $89
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
+ cell $reduce_bool $90
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 1
connect \A \alu_pulsem
- connect \Y $87
+ connect \Y $89
end
- process $group_49
+ process $group_51
assign \data_r2_l__nia$next \data_r2_l__nia
assign \data_r2_l__nia_ok$next \data_r2_l__nia_ok
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
- switch { $87 }
+ switch { $89 }
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
case 1'1
- assign { \data_r2_l__nia_ok$next \data_r2_l__nia$next } { \nia_ok \nia }
+ assign { \data_r2_l__nia_ok$next \data_r2_l__nia$next } { \nia_ok \alu_branch0_nia }
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
update \data_r2_l__nia \data_r2_l__nia$next
update \data_r2_l__nia_ok \data_r2_l__nia_ok$next
end
- process $group_51
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+ wire width 1 $91
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+ cell $and $92
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \data_r0__fast1_ok
+ connect \B \busy_o
+ connect \Y $91
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+ wire width 1 $93
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+ cell $and $94
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \data_r1__fast2_ok
+ connect \B \busy_o
+ connect \Y $93
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+ wire width 1 $95
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+ cell $and $96
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \data_r2__nia_ok
+ connect \B \busy_o
+ connect \Y $95
+ end
+ process $group_53
assign \wrmask 3'000
- assign \wrmask { \data_r2__nia_ok \data_r1__fast2_ok \data_r0__fast1_ok }
+ assign \wrmask { $95 $93 $91 }
sync init
end
- process $group_52
+ process $group_54
+ assign \alu_branch0_op__cia 64'0000000000000000000000000000000000000000000000000000000000000000
assign \alu_branch0_op__insn_type 7'0000000
assign \alu_branch0_op__fn_unit 11'00000000000
+ assign \alu_branch0_op__insn 32'00000000000000000000000000000000
assign \alu_branch0_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
assign \alu_branch0_op__imm_data__imm_ok 1'0
assign \alu_branch0_op__lk 1'0
assign \alu_branch0_op__is_32bit 1'0
- assign \alu_branch0_op__insn 32'00000000000000000000000000000000
- assign { \alu_branch0_op__insn \alu_branch0_op__is_32bit \alu_branch0_op__lk { \alu_branch0_op__imm_data__imm_ok \alu_branch0_op__imm_data__imm } \alu_branch0_op__fn_unit \alu_branch0_op__insn_type } { \oper_r__insn \oper_r__is_32bit \oper_r__lk { \oper_r__imm_data__imm_ok \oper_r__imm_data__imm } \oper_r__fn_unit \oper_r__insn_type }
+ assign { \alu_branch0_op__is_32bit \alu_branch0_op__lk { \alu_branch0_op__imm_data__imm_ok \alu_branch0_op__imm_data__imm } \alu_branch0_op__insn \alu_branch0_op__fn_unit \alu_branch0_op__insn_type \alu_branch0_op__cia } { \oper_r__is_32bit \oper_r__lk { \oper_r__imm_data__imm_ok \oper_r__imm_data__imm } \oper_r__insn \oper_r__fn_unit \oper_r__insn_type \oper_r__cia }
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:158"
wire width 1 \src_sel
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:159"
- wire width 1 $89
+ wire width 1 $97
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:159"
- cell $mux $90
+ cell $mux $98
parameter \WIDTH 1
connect \A \src_l_q_src [1]
connect \B \opc_l_q_opc
connect \S \oper_r__imm_data__imm_ok
- connect \Y $89
+ connect \Y $97
end
- process $group_59
+ process $group_62
assign \src_sel 1'0
- assign \src_sel $89
+ assign \src_sel $97
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:157"
wire width 64 \src_or_imm
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:160"
- wire width 64 $91
+ wire width 64 $99
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:160"
- cell $mux $92
+ cell $mux $100
parameter \WIDTH 64
connect \A \src2_i
connect \B \oper_r__imm_data__imm
connect \S \oper_r__imm_data__imm_ok
- connect \Y $91
+ connect \Y $99
end
- process $group_60
+ process $group_63
assign \src_or_imm 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \src_or_imm $91
+ assign \src_or_imm $99
sync init
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
wire width 64 \src_r0$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
- wire width 64 $93
+ wire width 64 $101
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
- cell $mux $94
+ cell $mux $102
parameter \WIDTH 64
connect \A \src_r0
connect \B \src1_i
connect \S \src_l_q_src [0]
- connect \Y $93
+ connect \Y $101
end
- process $group_61
- assign \alu_branch0_fast1 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \alu_branch0_fast1 $93
+ process $group_64
+ assign \alu_branch0_fast1$1 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \alu_branch0_fast1$1 $101
sync init
end
- process $group_62
+ process $group_65
assign \src_r0$next \src_r0
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
switch { \src_l_q_src [0] }
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
wire width 64 \src_r1$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
- wire width 64 $95
+ wire width 64 $103
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
- cell $mux $96
+ cell $mux $104
parameter \WIDTH 64
connect \A \src_r1
connect \B \src_or_imm
connect \S \src_sel
- connect \Y $95
+ connect \Y $103
end
- process $group_63
- assign \alu_branch0_fast2 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \alu_branch0_fast2 $95
+ process $group_66
+ assign \alu_branch0_fast2$2 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \alu_branch0_fast2$2 $103
sync init
end
- process $group_64
+ process $group_67
assign \src_r1$next \src_r1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
switch { \src_sel }
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
wire width 4 \src_r2$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
- wire width 4 $97
+ wire width 4 $105
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
- cell $mux $98
+ cell $mux $106
parameter \WIDTH 4
connect \A \src_r2
connect \B \src3_i
connect \S \src_l_q_src [2]
- connect \Y $97
+ connect \Y $105
end
- process $group_65
+ process $group_68
assign \alu_branch0_cr_a 4'0000
- assign \alu_branch0_cr_a $97
+ assign \alu_branch0_cr_a $105
sync init
end
- process $group_66
+ process $group_69
assign \src_r2$next \src_r2
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
switch { \src_l_q_src [2] }
sync posedge \clk
update \src_r2 \src_r2$next
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
- wire width 64 \src_r3
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
- wire width 64 \src_r3$next
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
- wire width 64 $99
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
- cell $mux $100
- parameter \WIDTH 64
- connect \A \src_r3
- connect \B \src4_i
- connect \S \src_l_q_src [3]
- connect \Y $99
- end
- process $group_67
- assign \alu_branch0_cia 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \alu_branch0_cia $99
- sync init
- end
- process $group_68
- assign \src_r3$next \src_r3
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
- switch { \src_l_q_src [3] }
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
- case 1'1
- assign \src_r3$next \src4_i
- end
- sync init
- update \src_r3 64'0000000000000000000000000000000000000000000000000000000000000000
- sync posedge \clk
- update \src_r3 \src_r3$next
- end
- process $group_69
+ process $group_70
assign \alu_branch0_p_valid_i 1'0
assign \alu_branch0_p_valid_i \alui_l_q_alui
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:321"
- wire width 1 $101
+ wire width 1 $107
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:321"
- cell $and $102
+ cell $and $108
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \alu_branch0_p_ready_o
connect \B \alui_l_q_alui
- connect \Y $101
+ connect \Y $107
end
- process $group_70
+ process $group_71
assign \alui_l_r_alui$next \alui_l_r_alui
- assign \alui_l_r_alui$next $101
+ assign \alui_l_r_alui$next $107
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
sync posedge \clk
update \alui_l_r_alui \alui_l_r_alui$next
end
- process $group_71
+ process $group_72
assign \alui_l_s_alui 1'0
assign \alui_l_s_alui \all_rd_pulse
sync init
end
- process $group_72
+ process $group_73
assign \alu_branch0_n_ready_i 1'0
assign \alu_branch0_n_ready_i \alu_l_q_alu
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:328"
- wire width 1 $103
+ wire width 1 $109
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:328"
- cell $and $104
+ cell $and $110
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \alu_branch0_n_valid_o
connect \B \alu_l_q_alu
- connect \Y $103
+ connect \Y $109
end
- process $group_73
+ process $group_74
assign \alu_l_r_alu$next \alu_l_r_alu
- assign \alu_l_r_alu$next $103
+ assign \alu_l_r_alu$next $109
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
sync posedge \clk
update \alu_l_r_alu \alu_l_r_alu$next
end
- process $group_74
+ process $group_75
assign \alu_l_s_alu 1'0
assign \alu_l_s_alu \all_rd_pulse
sync init
end
- process $group_75
+ process $group_76
assign \busy_o 1'0
assign \busy_o \opc_l_q_opc
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341"
- wire width 4 $105
+ wire width 3 $111
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341"
- cell $and $106
+ cell $and $112
parameter \A_SIGNED 0
- parameter \A_WIDTH 4
+ parameter \A_WIDTH 3
parameter \B_SIGNED 0
- parameter \B_WIDTH 4
- parameter \Y_WIDTH 4
+ parameter \B_WIDTH 3
+ parameter \Y_WIDTH 3
connect \A \src_l_q_src
- connect \B { \busy_o \busy_o \busy_o \busy_o }
- connect \Y $105
+ connect \B { \busy_o \busy_o \busy_o }
+ connect \Y $111
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:164"
- wire width 1 $107
+ wire width 1 $113
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:164"
- cell $not $108
+ cell $not $114
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \oper_r__imm_data__imm_ok
- connect \Y $107
+ connect \Y $113
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341"
- wire width 4 $109
+ wire width 3 $115
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341"
- cell $and $110
+ cell $and $116
parameter \A_SIGNED 0
- parameter \A_WIDTH 4
+ parameter \A_WIDTH 3
parameter \B_SIGNED 0
- parameter \B_WIDTH 4
- parameter \Y_WIDTH 4
- connect \A $105
- connect \B { 1'1 1'1 $107 1'1 }
- connect \Y $109
+ parameter \B_WIDTH 3
+ parameter \Y_WIDTH 3
+ connect \A $111
+ connect \B { 1'1 $113 1'1 }
+ connect \Y $115
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341"
- wire width 4 $111
+ wire width 3 $117
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341"
- cell $not $112
+ cell $not $118
parameter \A_SIGNED 0
- parameter \A_WIDTH 4
- parameter \Y_WIDTH 4
+ parameter \A_WIDTH 3
+ parameter \Y_WIDTH 3
connect \A \rdmaskn
- connect \Y $111
+ connect \Y $117
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341"
- wire width 4 $113
+ wire width 3 $119
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341"
- cell $and $114
+ cell $and $120
parameter \A_SIGNED 0
- parameter \A_WIDTH 4
+ parameter \A_WIDTH 3
parameter \B_SIGNED 0
- parameter \B_WIDTH 4
- parameter \Y_WIDTH 4
- connect \A $109
- connect \B $111
- connect \Y $113
+ parameter \B_WIDTH 3
+ parameter \Y_WIDTH 3
+ connect \A $115
+ connect \B $117
+ connect \Y $119
end
- process $group_76
- assign \rd__rel 4'0000
- assign \rd__rel $113
+ process $group_77
+ assign \rd__rel 3'000
+ assign \rd__rel $119
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
- wire width 1 $115
+ wire width 1 $121
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
- cell $and $116
+ cell $and $122
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \busy_o
connect \B \shadown_i
- connect \Y $115
+ connect \Y $121
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
- wire width 1 $117
+ wire width 1 $123
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
- cell $and $118
+ cell $and $124
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \busy_o
connect \B \shadown_i
- connect \Y $117
+ connect \Y $123
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
- wire width 1 $119
+ wire width 1 $125
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
- cell $and $120
+ cell $and $126
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \busy_o
connect \B \shadown_i
- connect \Y $119
+ connect \Y $125
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:345"
- wire width 3 $121
+ wire width 3 $127
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:345"
- cell $and $122
+ cell $and $128
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \B_WIDTH 3
parameter \Y_WIDTH 3
connect \A \req_l_q_req
- connect \B { $115 $117 $119 }
- connect \Y $121
+ connect \B { $121 $123 $125 }
+ connect \Y $127
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:345"
- wire width 3 $123
+ wire width 3 $129
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:345"
- cell $and $124
+ cell $and $130
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \B_WIDTH 3
parameter \Y_WIDTH 3
- connect \A $121
+ connect \A $127
connect \B \wrmask
- connect \Y $123
+ connect \Y $129
end
- process $group_77
+ process $group_78
assign \wr__rel 3'000
- assign \wr__rel $123
+ assign \wr__rel $129
sync init
end
- process $group_78
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+ wire width 1 $131
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+ cell $and $132
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \wr__go [0]
+ connect \B \busy_o
+ connect \Y $131
+ end
+ process $group_79
assign \dest1_o 64'0000000000000000000000000000000000000000000000000000000000000000
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
- switch { \wr__go [0] }
+ switch { $131 }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
case 1'1
assign \dest1_o { \data_r0__fast1_ok \data_r0__fast1 } [63:0]
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
- wire width 64 \dest2_o
- process $group_79
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+ wire width 1 $133
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+ cell $and $134
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \wr__go [1]
+ connect \B \busy_o
+ connect \Y $133
+ end
+ process $group_80
assign \dest2_o 64'0000000000000000000000000000000000000000000000000000000000000000
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
- switch { \wr__go [1] }
+ switch { $133 }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
case 1'1
assign \dest2_o { \data_r1__fast2_ok \data_r1__fast2 } [63:0]
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
- wire width 64 \dest3_o
- process $group_80
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+ wire width 1 $135
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+ cell $and $136
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \wr__go [2]
+ connect \B \busy_o
+ connect \Y $135
+ end
+ process $group_81
assign \dest3_o 64'0000000000000000000000000000000000000000000000000000000000000000
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
- switch { \wr__go [2] }
+ switch { $135 }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
case 1'1
assign \dest3_o { \data_r2__nia_ok \data_r2__nia } [63:0]
attribute \generator "nMigen"
attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.alu_trap0.p"
module \p$30
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153"
wire width 1 input 0 \p_valid_i
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154"
wire width 1 input 1 \p_ready_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:156"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158"
wire width 1 \trigger
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:203"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205"
wire width 1 $1
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:203"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205"
cell $and $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
attribute \generator "nMigen"
attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.alu_trap0.n"
module \n$31
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
wire width 1 input 0 \n_valid_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
wire width 1 input 1 \n_ready_i
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:249"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251"
wire width 1 \trigger
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:295"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:297"
wire width 1 $1
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:295"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:297"
cell $and $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
attribute \generator "nMigen"
attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.alu_trap0.pipe.p"
module \p$33
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153"
wire width 1 input 0 \p_valid_i
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154"
wire width 1 input 1 \p_ready_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:156"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158"
wire width 1 \trigger
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:203"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205"
wire width 1 $1
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:203"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205"
cell $and $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
attribute \generator "nMigen"
attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.alu_trap0.pipe.n"
module \n$34
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
wire width 1 input 0 \n_valid_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
wire width 1 input 1 \n_ready_i
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:249"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251"
wire width 1 \trigger
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:295"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:297"
wire width 1 $1
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:295"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:297"
cell $and $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
attribute \generator "nMigen"
attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.alu_trap0.pipe.main"
module \main$35
- attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
wire width 2 input 0 \muxid
- attribute \enum_base_type "InternalOp"
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 7 input 1 \op__insn_type
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00100000000 "MUL"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 11 input 2 \op__fn_unit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 32 input 3 \op__insn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
- wire width 1 input 4 \op__is_32bit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
- wire width 5 input 5 \op__traptype
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
- wire width 13 input 6 \op__trapaddr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
- wire width 64 input 7 \ra
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
- wire width 64 input 8 \rb
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
- wire width 64 input 9 \fast1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
- wire width 64 input 10 \fast2
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
- wire width 64 input 11 \cia
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
- wire width 64 input 12 \msr
- attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 input 4 \op__msr
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 input 5 \op__cia
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 6 \op__is_32bit
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 5 input 7 \op__traptype
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 13 input 8 \op__trapaddr
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 64 input 9 \ra
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 64 input 10 \rb
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 64 input 11 \fast1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 64 input 12 \fast2
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
wire width 2 output 13 \muxid$1
- attribute \enum_base_type "InternalOp"
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 7 output 14 \op__insn_type$2
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00100000000 "MUL"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 11 output 15 \op__fn_unit$3
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 32 output 16 \op__insn$4
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
- wire width 1 output 17 \op__is_32bit$5
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
- wire width 5 output 18 \op__traptype$6
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
- wire width 13 output 19 \op__trapaddr$7
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 output 17 \op__msr$5
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 output 18 \op__cia$6
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 19 \op__is_32bit$7
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 5 output 20 \op__traptype$8
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 13 output 21 \op__trapaddr$9
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 output 20 \o
+ wire width 64 output 22 \o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 21 \o_ok
+ wire width 1 output 23 \o_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 output 22 \fast1$8
+ wire width 64 output 24 \fast1$10
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 23 \fast1_ok
+ wire width 1 output 25 \fast1_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 output 24 \fast2$9
+ wire width 64 output 26 \fast2$11
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 25 \fast2_ok
+ wire width 1 output 27 \fast2_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 output 26 \nia
+ wire width 64 output 28 \nia
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 27 \nia_ok
+ wire width 1 output 29 \nia_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 output 28 \msr$10
+ wire width 64 output 30 \msr
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 29 \msr_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:101"
+ wire width 1 output 31 \msr_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:121"
wire width 5 \to
process $group_0
assign \to 5'00000
assign \to { \op__insn [25] \op__insn [24] \op__insn [23] \op__insn [22] \op__insn [21] }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:105"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:125"
wire width 64 \a_s
process $group_1
assign \a_s 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:132"
switch { \op__is_32bit }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:132"
case 1'1
assign \a_s { { \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] } \ra [31:0] }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:117"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:137"
case
assign \a_s \ra
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:106"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:126"
wire width 64 \b_s
process $group_2
assign \b_s 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:132"
switch { \op__is_32bit }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:132"
case 1'1
assign \b_s { { \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] } \rb [31:0] }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:117"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:137"
case
assign \b_s \rb
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:108"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:128"
wire width 64 \a
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:251"
- wire width 64 $11
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:251"
- cell $pos $12
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265"
+ wire width 64 $12
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265"
+ cell $pos $13
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \Y_WIDTH 64
connect \A \ra [31:0]
- connect \Y $11
+ connect \Y $12
end
process $group_3
assign \a 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:132"
switch { \op__is_32bit }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:132"
case 1'1
- assign \a $11
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:117"
+ assign \a $12
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:137"
case
assign \a \ra
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:109"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:129"
wire width 64 \b
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:251"
- wire width 64 $13
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:251"
- cell $pos $14
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265"
+ wire width 64 $14
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265"
+ cell $pos $15
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \Y_WIDTH 64
connect \A \rb [31:0]
- connect \Y $13
+ connect \Y $14
end
process $group_4
assign \b 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:132"
switch { \op__is_32bit }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:112"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:132"
case 1'1
- assign \b $13
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:117"
+ assign \b $14
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:137"
case
assign \b \rb
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:124"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:144"
wire width 1 \lt_s
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:130"
- wire width 1 $15
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:130"
- cell $lt $16
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:150"
+ wire width 1 $16
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:150"
+ cell $lt $17
parameter \A_SIGNED 1
parameter \A_WIDTH 64
parameter \B_SIGNED 1
parameter \Y_WIDTH 1
connect \A \a_s
connect \B \b_s
- connect \Y $15
+ connect \Y $16
end
process $group_5
assign \lt_s 1'0
- assign \lt_s $15
+ assign \lt_s $16
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:125"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:145"
wire width 1 \gt_s
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:131"
- wire width 1 $17
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:131"
- cell $gt $18
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:151"
+ wire width 1 $18
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:151"
+ cell $gt $19
parameter \A_SIGNED 1
parameter \A_WIDTH 64
parameter \B_SIGNED 1
parameter \Y_WIDTH 1
connect \A \a_s
connect \B \b_s
- connect \Y $17
+ connect \Y $18
end
process $group_6
assign \gt_s 1'0
- assign \gt_s $17
+ assign \gt_s $18
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:126"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:146"
wire width 1 \lt_u
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:132"
- wire width 1 $19
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:132"
- cell $lt $20
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:152"
+ wire width 1 $20
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:152"
+ cell $lt $21
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \a
connect \B \b
- connect \Y $19
+ connect \Y $20
end
process $group_7
assign \lt_u 1'0
- assign \lt_u $19
+ assign \lt_u $20
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:127"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:147"
wire width 1 \gt_u
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:133"
- wire width 1 $21
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:133"
- cell $gt $22
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:153"
+ wire width 1 $22
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:153"
+ cell $gt $23
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \a
connect \B \b
- connect \Y $21
+ connect \Y $22
end
process $group_8
assign \gt_u 1'0
- assign \gt_u $21
+ assign \gt_u $22
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:128"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:148"
wire width 1 \equal
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:134"
- wire width 1 $23
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:134"
- cell $eq $24
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:154"
+ wire width 1 $24
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:154"
+ cell $eq $25
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \a
connect \B \b
- connect \Y $23
+ connect \Y $24
end
process $group_9
assign \equal 1'0
- assign \equal $23
+ assign \equal $24
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:138"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:158"
wire width 5 \trap_bits
process $group_10
assign \trap_bits 5'00000
assign \trap_bits { \lt_s \gt_s \equal \lt_u \gt_u }
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:143"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:163"
wire width 1 \should_trap
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:144"
- wire width 1 $25
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:144"
- wire width 5 $26
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:144"
- cell $and $27
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:164"
+ wire width 1 $26
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:164"
+ wire width 5 $27
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:164"
+ cell $and $28
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A \trap_bits
connect \B \to
- connect \Y $26
+ connect \Y $27
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:144"
- cell $reduce_or $28
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:164"
+ cell $reduce_or $29
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \Y_WIDTH 1
- connect \A $26
- connect \Y $25
+ connect \A $27
+ connect \Y $26
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:144"
- wire width 1 $29
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:144"
- cell $reduce_or $30
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:164"
+ wire width 1 $30
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:164"
+ cell $reduce_or $31
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \Y_WIDTH 1
connect \A \op__traptype
- connect \Y $29
+ connect \Y $30
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:144"
- wire width 1 $31
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:144"
- cell $or $32
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:164"
+ wire width 1 $32
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:164"
+ cell $or $33
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $25
- connect \B $29
- connect \Y $31
+ connect \A $26
+ connect \B $30
+ connect \Y $32
end
process $group_11
assign \should_trap 1'0
- assign \should_trap $31
+ assign \should_trap $32
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:153"
- wire width 64 $33
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:153"
- wire width 20 $34
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:153"
- cell $sshl $35
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:173"
+ wire width 64 $34
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:173"
+ wire width 20 $35
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:173"
+ cell $sshl $36
parameter \A_SIGNED 0
parameter \A_WIDTH 13
parameter \B_SIGNED 0
parameter \Y_WIDTH 20
connect \A \op__trapaddr
connect \B 3'100
- connect \Y $34
+ connect \Y $35
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:153"
- cell $pos $36
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:173"
+ cell $pos $37
parameter \A_SIGNED 0
parameter \A_WIDTH 20
parameter \Y_WIDTH 64
- connect \A $34
- connect \Y $33
+ connect \A $35
+ connect \Y $34
end
process $group_12
assign \nia 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:147"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:167"
switch \op__insn_type
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:149"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:169"
attribute \nmigen.decoding "OP_TRAP/63"
case 7'0111111
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:151"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:171"
switch { \should_trap }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:151"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:171"
case 1'1
- assign \nia $33
+ assign \nia $34
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:167"
- attribute \nmigen.decoding "OP_MTMSRD/72"
- case 7'1001000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:182"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:191"
+ attribute \nmigen.decoding "OP_MTMSRD/72|OP_MTMSR/74"
+ case 7'1001000, 7'1001010
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:213"
attribute \nmigen.decoding "OP_MFMSR/71"
case 7'1000111
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:218"
attribute \nmigen.decoding "OP_RFID/70"
case 7'1000110
assign \nia { { { } \fast1 [63:2] } 2'00 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:200"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:249"
attribute \nmigen.decoding "OP_SC/73"
case 7'1001001
assign \nia 64'0000000000000000000000000000000000000000000000000000110000000000
end
process $group_13
assign \nia_ok 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:147"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:167"
switch \op__insn_type
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:149"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:169"
attribute \nmigen.decoding "OP_TRAP/63"
case 7'0111111
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:151"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:171"
switch { \should_trap }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:151"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:171"
case 1'1
assign \nia_ok 1'1
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:167"
- attribute \nmigen.decoding "OP_MTMSRD/72"
- case 7'1001000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:182"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:191"
+ attribute \nmigen.decoding "OP_MTMSRD/72|OP_MTMSR/74"
+ case 7'1001000, 7'1001010
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:213"
attribute \nmigen.decoding "OP_MFMSR/71"
case 7'1000111
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:218"
attribute \nmigen.decoding "OP_RFID/70"
case 7'1000110
assign \nia_ok 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:200"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:249"
attribute \nmigen.decoding "OP_SC/73"
case 7'1001001
assign \nia_ok 1'1
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:205"
- wire width 65 $37
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:205"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:254"
wire width 65 $38
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:205"
- cell $add $39
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:254"
+ wire width 65 $39
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:254"
+ cell $add $40
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \B_WIDTH 3
parameter \Y_WIDTH 65
- connect \A \cia
+ connect \A \op__cia
connect \B 3'100
- connect \Y $38
+ connect \Y $39
end
- connect $37 $38
+ connect $38 $39
process $group_14
- assign \fast1$8 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:147"
+ assign \fast1$10 64'0000000000000000000000000000000000000000000000000000000000000000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:167"
switch \op__insn_type
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:149"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:169"
attribute \nmigen.decoding "OP_TRAP/63"
case 7'0111111
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:151"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:171"
switch { \should_trap }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:151"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:171"
case 1'1
- assign \fast1$8 \cia
+ assign \fast1$10 \op__cia
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:167"
- attribute \nmigen.decoding "OP_MTMSRD/72"
- case 7'1001000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:182"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:191"
+ attribute \nmigen.decoding "OP_MTMSRD/72|OP_MTMSR/74"
+ case 7'1001000, 7'1001010
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:213"
attribute \nmigen.decoding "OP_MFMSR/71"
case 7'1000111
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:218"
attribute \nmigen.decoding "OP_RFID/70"
case 7'1000110
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:200"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:249"
attribute \nmigen.decoding "OP_SC/73"
case 7'1001001
- assign \fast1$8 $37 [63:0]
+ assign \fast1$10 $38 [63:0]
end
sync init
end
process $group_15
assign \fast1_ok 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:147"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:167"
switch \op__insn_type
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:149"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:169"
attribute \nmigen.decoding "OP_TRAP/63"
case 7'0111111
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:151"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:171"
switch { \should_trap }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:151"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:171"
case 1'1
assign \fast1_ok 1'1
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:167"
- attribute \nmigen.decoding "OP_MTMSRD/72"
- case 7'1001000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:182"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:191"
+ attribute \nmigen.decoding "OP_MTMSRD/72|OP_MTMSR/74"
+ case 7'1001000, 7'1001010
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:213"
attribute \nmigen.decoding "OP_MFMSR/71"
case 7'1000111
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:218"
attribute \nmigen.decoding "OP_RFID/70"
case 7'1000110
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:200"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:249"
attribute \nmigen.decoding "OP_SC/73"
case 7'1001001
assign \fast1_ok 1'1
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:154"
- wire width 1 $40
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:154"
- cell $eq $41
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:174"
+ wire width 1 $41
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:174"
+ cell $eq $42
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \op__traptype
connect \B 1'0
- connect \Y $40
+ connect \Y $41
end
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
- wire width 1 $42
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:157"
- wire width 5 $43
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:157"
- cell $and $44
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
+ wire width 1 $43
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:177"
+ wire width 5 $44
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:177"
+ cell $and $45
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A \op__traptype
connect \B 2'10
- connect \Y $43
+ connect \Y $44
end
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
- cell $reduce_bool $45
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
+ cell $reduce_bool $46
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \Y_WIDTH 1
- connect \A $43
- connect \Y $42
+ connect \A $44
+ connect \Y $43
end
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
- wire width 1 $46
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:159"
- wire width 5 $47
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:159"
- cell $and $48
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
+ wire width 1 $47
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:179"
+ wire width 5 $48
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:179"
+ cell $and $49
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A \op__traptype
connect \B 1'1
- connect \Y $47
+ connect \Y $48
end
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
- cell $reduce_bool $49
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
+ cell $reduce_bool $50
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \Y_WIDTH 1
- connect \A $47
- connect \Y $46
+ connect \A $48
+ connect \Y $47
end
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
- wire width 1 $50
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:161"
- wire width 5 $51
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:161"
- cell $and $52
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
+ wire width 1 $51
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:181"
+ wire width 5 $52
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:181"
+ cell $and $53
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A \op__traptype
connect \B 4'1000
- connect \Y $51
+ connect \Y $52
end
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
- cell $reduce_bool $53
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
+ cell $reduce_bool $54
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \Y_WIDTH 1
- connect \A $51
- connect \Y $50
+ connect \A $52
+ connect \Y $51
end
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
- wire width 1 $54
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:163"
- wire width 5 $55
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:163"
- cell $and $56
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
+ wire width 1 $55
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:183"
+ wire width 5 $56
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:183"
+ cell $and $57
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A \op__traptype
connect \B 5'10000
- connect \Y $55
+ connect \Y $56
end
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
- cell $reduce_bool $57
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
+ cell $reduce_bool $58
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \Y_WIDTH 1
- connect \A $55
- connect \Y $54
+ connect \A $56
+ connect \Y $55
end
process $group_16
- assign \fast2$9 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:147"
+ assign \fast2$11 64'0000000000000000000000000000000000000000000000000000000000000000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:167"
switch \op__insn_type
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:149"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:169"
attribute \nmigen.decoding "OP_TRAP/63"
case 7'0111111
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:151"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:171"
switch { \should_trap }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:151"
- case 1'1
- assign \fast2$9 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \fast2$9 [15:0] \msr [15:0]
- assign \fast2$9 [26:22] \msr [26:22]
- assign \fast2$9 [63:31] \msr [63:31]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:154"
- switch { $40 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:154"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:171"
+ case 1'1
+ assign \fast2$11 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \fast2$11 [15:0] \op__msr [15:0]
+ assign \fast2$11 [26:22] \op__msr [26:22]
+ assign \fast2$11 [63:31] \op__msr [63:31]
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:174"
+ switch { $41 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:174"
case 1'1
- assign \fast2$9 [17] 1'1
+ assign \fast2$11 [17] 1'1
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:157"
- switch { $42 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:157"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:177"
+ switch { $43 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:177"
case 1'1
- assign \fast2$9 [18] 1'1
+ assign \fast2$11 [18] 1'1
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:159"
- switch { $46 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:159"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:179"
+ switch { $47 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:179"
case 1'1
- assign \fast2$9 [20] 1'1
+ assign \fast2$11 [20] 1'1
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:161"
- switch { $50 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:161"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:181"
+ switch { $51 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:181"
case 1'1
- assign \fast2$9 [16] 1'1
+ assign \fast2$11 [16] 1'1
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:163"
- switch { $54 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:163"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:183"
+ switch { $55 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:183"
case 1'1
- assign \fast2$9 [19] 1'1
+ assign \fast2$11 [19] 1'1
end
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:167"
- attribute \nmigen.decoding "OP_MTMSRD/72"
- case 7'1001000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:182"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:191"
+ attribute \nmigen.decoding "OP_MTMSRD/72|OP_MTMSR/74"
+ case 7'1001000, 7'1001010
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:213"
attribute \nmigen.decoding "OP_MFMSR/71"
case 7'1000111
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:218"
attribute \nmigen.decoding "OP_RFID/70"
case 7'1000110
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:200"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:249"
attribute \nmigen.decoding "OP_SC/73"
case 7'1001001
- assign \fast2$9 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \fast2$9 [15:0] \msr [15:0]
- assign \fast2$9 [26:22] \msr [26:22]
- assign \fast2$9 [63:31] \msr [63:31]
+ assign \fast2$11 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \fast2$11 [15:0] \op__msr [15:0]
+ assign \fast2$11 [26:22] \op__msr [26:22]
+ assign \fast2$11 [63:31] \op__msr [63:31]
end
sync init
end
process $group_17
assign \fast2_ok 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:147"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:167"
switch \op__insn_type
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:149"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:169"
attribute \nmigen.decoding "OP_TRAP/63"
case 7'0111111
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:151"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:171"
switch { \should_trap }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:151"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:171"
case 1'1
assign \fast2_ok 1'1
+ assign \fast2_ok 1'1
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:167"
- attribute \nmigen.decoding "OP_MTMSRD/72"
- case 7'1001000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:182"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:191"
+ attribute \nmigen.decoding "OP_MTMSRD/72|OP_MTMSR/74"
+ case 7'1001000, 7'1001010
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:213"
attribute \nmigen.decoding "OP_MFMSR/71"
case 7'1000111
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:218"
attribute \nmigen.decoding "OP_RFID/70"
case 7'1000110
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:200"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:249"
attribute \nmigen.decoding "OP_SC/73"
case 7'1001001
assign \fast2_ok 1'1
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
- wire width 1 $58
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
- cell $reduce_bool $59
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 65 $59
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ cell $pos $60
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 64
+ parameter \Y_WIDTH 65
+ connect \A \op__msr
+ connect \Y $59
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
+ wire width 1 $61
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
+ cell $reduce_bool $62
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \Y_WIDTH 1
connect \A { \op__insn [22] \op__insn [21] }
- connect \Y $58
+ connect \Y $61
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:202"
+ wire width 1 $63
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:202"
+ cell $eq $64
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 7
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 7
+ parameter \Y_WIDTH 1
+ connect \A \op__insn_type
+ connect \B 7'1001000
+ connect \Y $63
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:235"
+ wire width 1 $65
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:235"
+ cell $not $66
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \op__msr [60]
+ connect \Y $65
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:242"
+ wire width 1 $67
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:242"
+ cell $eq $68
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 3
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 3
+ parameter \Y_WIDTH 1
+ connect \A \op__msr [34:32]
+ connect \B 3'010
+ connect \Y $67
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:243"
+ wire width 1 $69
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:243"
+ cell $eq $70
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 3
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 3
+ parameter \Y_WIDTH 1
+ connect \A \fast2 [34:32]
+ connect \B 3'000
+ connect \Y $69
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:243"
+ wire width 1 $71
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:243"
+ cell $and $72
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A $67
+ connect \B $69
+ connect \Y $71
end
process $group_18
- assign \msr$10 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:147"
+ assign \msr 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \msr_ok 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:167"
switch \op__insn_type
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:149"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:169"
attribute \nmigen.decoding "OP_TRAP/63"
case 7'0111111
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:167"
- attribute \nmigen.decoding "OP_MTMSRD/72"
- case 7'1001000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:169"
- switch { $58 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:169"
- case 1'1
- assign \msr$10 [15] \ra [15]
- assign \msr$10 [1] \ra [1]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:173"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:171"
+ switch { \should_trap }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:171"
+ case 1'1
+ assign \msr \op__msr
+ assign \msr [63] 1'1
+ assign \msr [15] 1'0
+ assign \msr [14] 1'0
+ assign \msr [5] 1'0
+ assign \msr [4] 1'0
+ assign \msr [1] 1'0
+ assign \msr [0] 1'1
+ assign \msr_ok 1'1
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:191"
+ attribute \nmigen.decoding "OP_MTMSRD/72|OP_MTMSR/74"
+ case 7'1001000, 7'1001010
+ assign { \msr_ok \msr } $59
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:195"
+ switch { $61 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:195"
+ case 1'1
+ assign \msr [1] \ra [1]
+ assign \msr [15] \ra [15]
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:199"
case
- assign \msr$10 [11:1] \ra [11:1]
- assign \msr$10 [59:13] \ra [59:13]
- assign \msr$10 [63:61] \ra [63:61]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:50"
- switch { \msr$10 [14] }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:50"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:202"
+ switch { $63 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:202"
case 1'1
- assign \msr$10 [15] 1'1
- assign \msr$10 [5] 1'1
- assign \msr$10 [4] 1'1
+ assign \msr [11:1] \ra [11:1]
+ assign \msr [59:13] \ra [59:13]
+ assign \msr [63:61] \ra [63:61]
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:205"
+ case
+ assign \msr [11:1] \ra [11:1]
+ assign \msr [31:13] \ra [31:13]
end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:48"
+ switch { \msr [14] }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:48"
+ case 1'1
+ assign \msr [15] 1'1
+ assign \msr [5] 1'1
+ assign \msr [4] 1'1
+ end
+ end
+ switch { }
+ case
+ assign \msr_ok 1'1
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:182"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:213"
attribute \nmigen.decoding "OP_MFMSR/71"
case 7'1000111
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:218"
attribute \nmigen.decoding "OP_RFID/70"
case 7'1000110
- assign \msr$10 [15:0] \fast2 [15:0]
- assign \msr$10 [26:22] \fast2 [26:22]
- assign \msr$10 [63:31] \fast2 [63:31]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:50"
- switch { \msr$10 [14] }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:50"
- case 1'1
- assign \msr$10 [15] 1'1
- assign \msr$10 [5] 1'1
- assign \msr$10 [4] 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:200"
+ assign \msr [15:0] \fast2 [15:0]
+ assign \msr [26:22] \fast2 [26:22]
+ assign \msr [63:31] \fast2 [63:31]
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:48"
+ switch { \msr [14] }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:48"
+ case 1'1
+ assign \msr [15] 1'1
+ assign \msr [5] 1'1
+ assign \msr [4] 1'1
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:235"
+ switch { $65 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:235"
+ case 1'1
+ assign \msr [60] \op__msr [60]
+ assign \msr [12] \op__msr [12]
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:243"
+ switch { $71 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:243"
+ case 1'1
+ assign \msr [34:32] \op__msr [34:32]
+ end
+ switch { }
+ case
+ assign \msr_ok 1'1
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:249"
attribute \nmigen.decoding "OP_SC/73"
case 7'1001001
- end
- sync init
- end
- process $group_19
- assign \msr_ok 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:147"
- switch \op__insn_type
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:149"
- attribute \nmigen.decoding "OP_TRAP/63"
- case 7'0111111
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:167"
- attribute \nmigen.decoding "OP_MTMSRD/72"
- case 7'1001000
- assign \msr_ok 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:182"
- attribute \nmigen.decoding "OP_MFMSR/71"
- case 7'1000111
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187"
- attribute \nmigen.decoding "OP_RFID/70"
- case 7'1000110
+ assign \msr \op__msr
+ assign \msr [63] 1'1
+ assign \msr [15] 1'0
+ assign \msr [14] 1'0
+ assign \msr [5] 1'0
+ assign \msr [4] 1'0
+ assign \msr [1] 1'0
+ assign \msr [0] 1'1
assign \msr_ok 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:200"
- attribute \nmigen.decoding "OP_SC/73"
- case 7'1001001
end
sync init
end
process $group_20
assign \o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:147"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:167"
switch \op__insn_type
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:149"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:169"
attribute \nmigen.decoding "OP_TRAP/63"
case 7'0111111
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:167"
- attribute \nmigen.decoding "OP_MTMSRD/72"
- case 7'1001000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:182"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:191"
+ attribute \nmigen.decoding "OP_MTMSRD/72|OP_MTMSR/74"
+ case 7'1001000, 7'1001010
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:213"
attribute \nmigen.decoding "OP_MFMSR/71"
case 7'1000111
- assign \o \msr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187"
+ assign \o \op__msr
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:218"
attribute \nmigen.decoding "OP_RFID/70"
case 7'1000110
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:200"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:249"
attribute \nmigen.decoding "OP_SC/73"
case 7'1001001
end
end
process $group_21
assign \o_ok 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:147"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:167"
switch \op__insn_type
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:149"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:169"
attribute \nmigen.decoding "OP_TRAP/63"
case 7'0111111
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:167"
- attribute \nmigen.decoding "OP_MTMSRD/72"
- case 7'1001000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:182"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:191"
+ attribute \nmigen.decoding "OP_MTMSRD/72|OP_MTMSR/74"
+ case 7'1001000, 7'1001010
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:213"
attribute \nmigen.decoding "OP_MFMSR/71"
case 7'1000111
assign \o_ok 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:187"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:218"
attribute \nmigen.decoding "OP_RFID/70"
case 7'1000110
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:200"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:249"
attribute \nmigen.decoding "OP_SC/73"
case 7'1001001
end
assign \op__insn_type$2 7'0000000
assign \op__fn_unit$3 11'00000000000
assign \op__insn$4 32'00000000000000000000000000000000
- assign \op__is_32bit$5 1'0
- assign \op__traptype$6 5'00000
- assign \op__trapaddr$7 13'0000000000000
- assign { \op__trapaddr$7 \op__traptype$6 \op__is_32bit$5 \op__insn$4 \op__fn_unit$3 \op__insn_type$2 } { \op__trapaddr \op__traptype \op__is_32bit \op__insn \op__fn_unit \op__insn_type }
+ assign \op__msr$5 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \op__cia$6 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \op__is_32bit$7 1'0
+ assign \op__traptype$8 5'00000
+ assign \op__trapaddr$9 13'0000000000000
+ assign { \op__trapaddr$9 \op__traptype$8 \op__is_32bit$7 \op__cia$6 \op__msr$5 \op__insn$4 \op__fn_unit$3 \op__insn_type$2 } { \op__trapaddr \op__traptype \op__is_32bit \op__cia \op__msr \op__insn \op__fn_unit \op__insn_type }
sync init
end
end
wire width 1 input 0 \rst
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153"
wire width 1 input 2 \p_valid_i
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154"
wire width 1 output 3 \p_ready_o
- attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
wire width 2 input 4 \muxid
- attribute \enum_base_type "InternalOp"
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 7 input 5 \op__insn_type
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00100000000 "MUL"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 11 input 6 \op__fn_unit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 32 input 7 \op__insn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
- wire width 1 input 8 \op__is_32bit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
- wire width 5 input 9 \op__traptype
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
- wire width 13 input 10 \op__trapaddr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
- wire width 64 input 11 \ra
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
- wire width 64 input 12 \rb
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
- wire width 64 input 13 \fast1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
- wire width 64 input 14 \fast2
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
- wire width 64 input 15 \cia
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
- wire width 64 input 16 \msr
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 input 8 \op__msr
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 input 9 \op__cia
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 10 \op__is_32bit
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 5 input 11 \op__traptype
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 13 input 12 \op__trapaddr
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 64 input 13 \ra
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 64 input 14 \rb
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 64 input 15 \fast1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 64 input 16 \fast2
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
wire width 1 output 17 \n_valid_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
wire width 1 input 18 \n_ready_i
- attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
wire width 2 output 19 \muxid$1
- attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
wire width 2 \muxid$1$next
- attribute \enum_base_type "InternalOp"
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 7 output 20 \op__insn_type$2
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 7 \op__insn_type$2$next
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00100000000 "MUL"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 11 output 21 \op__fn_unit$3
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 11 \op__fn_unit$3$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 32 output 22 \op__insn$4
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 32 \op__insn$4$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
- wire width 1 output 23 \op__is_32bit$5
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
- wire width 1 \op__is_32bit$5$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
- wire width 5 output 24 \op__traptype$6
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
- wire width 5 \op__traptype$6$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
- wire width 13 output 25 \op__trapaddr$7
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
- wire width 13 \op__trapaddr$7$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 output 23 \op__msr$5
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 \op__msr$5$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 output 24 \op__cia$6
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 \op__cia$6$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 25 \op__is_32bit$7
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__is_32bit$7$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 5 output 26 \op__traptype$8
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 5 \op__traptype$8$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 13 output 27 \op__trapaddr$9
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 13 \op__trapaddr$9$next
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 output 26 \o
+ wire width 64 output 28 \o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 64 \o$next
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 27 \o_ok
+ wire width 1 output 29 \o_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 \o_ok$next
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 output 28 \fast1$8
+ wire width 64 output 30 \fast1$10
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 \fast1$8$next
+ wire width 64 \fast1$10$next
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 29 \fast1_ok
+ wire width 1 output 31 \fast1_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 \fast1_ok$next
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 output 30 \fast2$9
+ wire width 64 output 32 \fast2$11
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 \fast2$9$next
+ wire width 64 \fast2$11$next
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 31 \fast2_ok
+ wire width 1 output 33 \fast2_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 \fast2_ok$next
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 output 32 \nia
+ wire width 64 output 34 \nia
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 64 \nia$next
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 33 \nia_ok
+ wire width 1 output 35 \nia_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 \nia_ok$next
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 output 34 \msr$10
+ wire width 64 output 36 \msr
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 \msr$10$next
+ wire width 64 \msr$next
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 35 \msr_ok
+ wire width 1 output 37 \msr_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 \msr_ok$next
cell \p$33 \p
connect \n_valid_o \n_valid_o
connect \n_ready_i \n_ready_i
end
- attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
wire width 2 \main_muxid
- attribute \enum_base_type "InternalOp"
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 7 \main_op__insn_type
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00100000000 "MUL"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 11 \main_op__fn_unit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 32 \main_op__insn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 \main_op__msr
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 \main_op__cia
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \main_op__is_32bit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 5 \main_op__traptype
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 13 \main_op__trapaddr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
wire width 64 \main_ra
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
wire width 64 \main_rb
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
wire width 64 \main_fast1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
wire width 64 \main_fast2
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
- wire width 64 \main_cia
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
- wire width 64 \main_msr
- attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
- wire width 2 \main_muxid$11
- attribute \enum_base_type "InternalOp"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+ wire width 2 \main_muxid$12
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
- wire width 7 \main_op__insn_type$12
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 7 \main_op__insn_type$13
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00000000010 "ALU"
attribute \enum_value_00100000000 "MUL"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
- wire width 11 \main_op__fn_unit$13
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
- wire width 32 \main_op__insn$14
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
- wire width 1 \main_op__is_32bit$15
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
- wire width 5 \main_op__traptype$16
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
- wire width 13 \main_op__trapaddr$17
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 11 \main_op__fn_unit$14
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 \main_op__insn$15
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 \main_op__msr$16
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 \main_op__cia$17
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \main_op__is_32bit$18
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 5 \main_op__traptype$19
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 13 \main_op__trapaddr$20
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 64 \main_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 \main_o_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 \main_fast1$18
+ wire width 64 \main_fast1$21
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 \main_fast1_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 \main_fast2$19
+ wire width 64 \main_fast2$22
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 \main_fast2_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 \main_nia_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 \main_msr$20
+ wire width 64 \main_msr
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 \main_msr_ok
cell \main$35 \main
connect \op__insn_type \main_op__insn_type
connect \op__fn_unit \main_op__fn_unit
connect \op__insn \main_op__insn
+ connect \op__msr \main_op__msr
+ connect \op__cia \main_op__cia
connect \op__is_32bit \main_op__is_32bit
connect \op__traptype \main_op__traptype
connect \op__trapaddr \main_op__trapaddr
connect \rb \main_rb
connect \fast1 \main_fast1
connect \fast2 \main_fast2
- connect \cia \main_cia
- connect \msr \main_msr
- connect \muxid$1 \main_muxid$11
- connect \op__insn_type$2 \main_op__insn_type$12
- connect \op__fn_unit$3 \main_op__fn_unit$13
- connect \op__insn$4 \main_op__insn$14
- connect \op__is_32bit$5 \main_op__is_32bit$15
- connect \op__traptype$6 \main_op__traptype$16
- connect \op__trapaddr$7 \main_op__trapaddr$17
+ connect \muxid$1 \main_muxid$12
+ connect \op__insn_type$2 \main_op__insn_type$13
+ connect \op__fn_unit$3 \main_op__fn_unit$14
+ connect \op__insn$4 \main_op__insn$15
+ connect \op__msr$5 \main_op__msr$16
+ connect \op__cia$6 \main_op__cia$17
+ connect \op__is_32bit$7 \main_op__is_32bit$18
+ connect \op__traptype$8 \main_op__traptype$19
+ connect \op__trapaddr$9 \main_op__trapaddr$20
connect \o \main_o
connect \o_ok \main_o_ok
- connect \fast1$8 \main_fast1$18
+ connect \fast1$10 \main_fast1$21
connect \fast1_ok \main_fast1_ok
- connect \fast2$9 \main_fast2$19
+ connect \fast2$11 \main_fast2$22
connect \fast2_ok \main_fast2_ok
connect \nia \main_nia
connect \nia_ok \main_nia_ok
- connect \msr$10 \main_msr$20
+ connect \msr \main_msr
connect \msr_ok \main_msr_ok
end
process $group_0
assign \main_op__insn_type 7'0000000
assign \main_op__fn_unit 11'00000000000
assign \main_op__insn 32'00000000000000000000000000000000
+ assign \main_op__msr 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \main_op__cia 64'0000000000000000000000000000000000000000000000000000000000000000
assign \main_op__is_32bit 1'0
assign \main_op__traptype 5'00000
assign \main_op__trapaddr 13'0000000000000
- assign { \main_op__trapaddr \main_op__traptype \main_op__is_32bit \main_op__insn \main_op__fn_unit \main_op__insn_type } { \op__trapaddr \op__traptype \op__is_32bit \op__insn \op__fn_unit \op__insn_type }
+ assign { \main_op__trapaddr \main_op__traptype \main_op__is_32bit \main_op__cia \main_op__msr \main_op__insn \main_op__fn_unit \main_op__insn_type } { \op__trapaddr \op__traptype \op__is_32bit \op__cia \op__msr \op__insn \op__fn_unit \op__insn_type }
sync init
end
- process $group_7
+ process $group_9
assign \main_ra 64'0000000000000000000000000000000000000000000000000000000000000000
assign \main_ra \ra
sync init
end
- process $group_8
+ process $group_10
assign \main_rb 64'0000000000000000000000000000000000000000000000000000000000000000
assign \main_rb \rb
sync init
end
- process $group_9
+ process $group_11
assign \main_fast1 64'0000000000000000000000000000000000000000000000000000000000000000
assign \main_fast1 \fast1
sync init
end
- process $group_10
+ process $group_12
assign \main_fast2 64'0000000000000000000000000000000000000000000000000000000000000000
assign \main_fast2 \fast2
sync init
end
- process $group_11
- assign \main_cia 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \main_cia \cia
- sync init
- end
- process $group_12
- assign \main_msr 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \main_msr \msr
- sync init
- end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621"
- wire width 1 \p_valid_i$21
+ wire width 1 \p_valid_i$23
process $group_13
- assign \p_valid_i$21 1'0
- assign \p_valid_i$21 \p_valid_i
+ assign \p_valid_i$23 1'0
+ assign \p_valid_i$23 \p_valid_i
sync init
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620"
wire width 1 \p_valid_i_p_ready_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624"
- wire width 1 $22
+ wire width 1 $24
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624"
- cell $and $23
+ cell $and $25
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \p_valid_i$21
+ connect \A \p_valid_i$23
connect \B \p_ready_o
- connect \Y $22
+ connect \Y $24
end
process $group_15
assign \p_valid_i_p_ready_o 1'0
- assign \p_valid_i_p_ready_o $22
+ assign \p_valid_i_p_ready_o $24
sync init
end
- attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
- wire width 2 \muxid$24
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+ wire width 2 \muxid$26
process $group_16
- assign \muxid$24 2'00
- assign \muxid$24 \main_muxid$11
+ assign \muxid$26 2'00
+ assign \muxid$26 \main_muxid$12
sync init
end
- attribute \enum_base_type "InternalOp"
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
- wire width 7 \op__insn_type$25
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 7 \op__insn_type$27
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00000000010 "ALU"
attribute \enum_value_00100000000 "MUL"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
- wire width 11 \op__fn_unit$26
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
- wire width 32 \op__insn$27
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
- wire width 1 \op__is_32bit$28
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
- wire width 5 \op__traptype$29
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
- wire width 13 \op__trapaddr$30
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 11 \op__fn_unit$28
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 \op__insn$29
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 \op__msr$30
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 \op__cia$31
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__is_32bit$32
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 5 \op__traptype$33
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 13 \op__trapaddr$34
process $group_17
- assign \op__insn_type$25 7'0000000
- assign \op__fn_unit$26 11'00000000000
- assign \op__insn$27 32'00000000000000000000000000000000
- assign \op__is_32bit$28 1'0
- assign \op__traptype$29 5'00000
- assign \op__trapaddr$30 13'0000000000000
- assign { \op__trapaddr$30 \op__traptype$29 \op__is_32bit$28 \op__insn$27 \op__fn_unit$26 \op__insn_type$25 } { \main_op__trapaddr$17 \main_op__traptype$16 \main_op__is_32bit$15 \main_op__insn$14 \main_op__fn_unit$13 \main_op__insn_type$12 }
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 \o$31
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 \o_ok$32
- process $group_23
- assign \o$31 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \o_ok$32 1'0
- assign { \o_ok$32 \o$31 } { \main_o_ok \main_o }
+ assign \op__insn_type$27 7'0000000
+ assign \op__fn_unit$28 11'00000000000
+ assign \op__insn$29 32'00000000000000000000000000000000
+ assign \op__msr$30 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \op__cia$31 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \op__is_32bit$32 1'0
+ assign \op__traptype$33 5'00000
+ assign \op__trapaddr$34 13'0000000000000
+ assign { \op__trapaddr$34 \op__traptype$33 \op__is_32bit$32 \op__cia$31 \op__msr$30 \op__insn$29 \op__fn_unit$28 \op__insn_type$27 } { \main_op__trapaddr$20 \main_op__traptype$19 \main_op__is_32bit$18 \main_op__cia$17 \main_op__msr$16 \main_op__insn$15 \main_op__fn_unit$14 \main_op__insn_type$13 }
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 \fast1$33
+ wire width 64 \o$35
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 \fast1_ok$34
+ wire width 1 \o_ok$36
process $group_25
- assign \fast1$33 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \fast1_ok$34 1'0
- assign { \fast1_ok$34 \fast1$33 } { \main_fast1_ok \main_fast1$18 }
+ assign \o$35 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \o_ok$36 1'0
+ assign { \o_ok$36 \o$35 } { \main_o_ok \main_o }
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 \fast2$35
+ wire width 64 \fast1$37
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 \fast2_ok$36
+ wire width 1 \fast1_ok$38
process $group_27
- assign \fast2$35 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \fast2_ok$36 1'0
- assign { \fast2_ok$36 \fast2$35 } { \main_fast2_ok \main_fast2$19 }
+ assign \fast1$37 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \fast1_ok$38 1'0
+ assign { \fast1_ok$38 \fast1$37 } { \main_fast1_ok \main_fast1$21 }
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 \nia$37
+ wire width 64 \fast2$39
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 \nia_ok$38
+ wire width 1 \fast2_ok$40
process $group_29
- assign \nia$37 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \nia_ok$38 1'0
- assign { \nia_ok$38 \nia$37 } { \main_nia_ok \main_nia }
+ assign \fast2$39 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \fast2_ok$40 1'0
+ assign { \fast2_ok$40 \fast2$39 } { \main_fast2_ok \main_fast2$22 }
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 \msr$39
+ wire width 64 \nia$41
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 \msr_ok$40
+ wire width 1 \nia_ok$42
process $group_31
- assign \msr$39 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \msr_ok$40 1'0
- assign { \msr_ok$40 \msr$39 } { \main_msr_ok \main_msr$20 }
+ assign \nia$41 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \nia_ok$42 1'0
+ assign { \nia_ok$42 \nia$41 } { \main_nia_ok \main_nia }
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 64 \msr$43
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 \msr_ok$44
+ process $group_33
+ assign \msr$43 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \msr_ok$44 1'0
+ assign { \msr_ok$44 \msr$43 } { \main_msr_ok \main_msr }
sync init
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615"
wire width 1 \r_busy
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615"
wire width 1 \r_busy$next
- process $group_33
+ process $group_35
assign \r_busy$next \r_busy
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
switch { \n_i_rdy_data \p_valid_i_p_ready_o }
sync posedge \clk
update \r_busy \r_busy$next
end
- process $group_34
+ process $group_36
assign \muxid$1$next \muxid$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
switch { \n_i_rdy_data \p_valid_i_p_ready_o }
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
case 2'-1
- assign \muxid$1$next \muxid$24
+ assign \muxid$1$next \muxid$26
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
case 2'1-
- assign \muxid$1$next \muxid$24
+ assign \muxid$1$next \muxid$26
end
sync init
update \muxid$1 2'00
sync posedge \clk
update \muxid$1 \muxid$1$next
end
- process $group_35
+ process $group_37
assign \op__insn_type$2$next \op__insn_type$2
assign \op__fn_unit$3$next \op__fn_unit$3
assign \op__insn$4$next \op__insn$4
- assign \op__is_32bit$5$next \op__is_32bit$5
- assign \op__traptype$6$next \op__traptype$6
- assign \op__trapaddr$7$next \op__trapaddr$7
+ assign \op__msr$5$next \op__msr$5
+ assign \op__cia$6$next \op__cia$6
+ assign \op__is_32bit$7$next \op__is_32bit$7
+ assign \op__traptype$8$next \op__traptype$8
+ assign \op__trapaddr$9$next \op__trapaddr$9
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
switch { \n_i_rdy_data \p_valid_i_p_ready_o }
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
case 2'-1
- assign { \op__trapaddr$7$next \op__traptype$6$next \op__is_32bit$5$next \op__insn$4$next \op__fn_unit$3$next \op__insn_type$2$next } { \op__trapaddr$30 \op__traptype$29 \op__is_32bit$28 \op__insn$27 \op__fn_unit$26 \op__insn_type$25 }
+ assign { \op__trapaddr$9$next \op__traptype$8$next \op__is_32bit$7$next \op__cia$6$next \op__msr$5$next \op__insn$4$next \op__fn_unit$3$next \op__insn_type$2$next } { \op__trapaddr$34 \op__traptype$33 \op__is_32bit$32 \op__cia$31 \op__msr$30 \op__insn$29 \op__fn_unit$28 \op__insn_type$27 }
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
case 2'1-
- assign { \op__trapaddr$7$next \op__traptype$6$next \op__is_32bit$5$next \op__insn$4$next \op__fn_unit$3$next \op__insn_type$2$next } { \op__trapaddr$30 \op__traptype$29 \op__is_32bit$28 \op__insn$27 \op__fn_unit$26 \op__insn_type$25 }
+ assign { \op__trapaddr$9$next \op__traptype$8$next \op__is_32bit$7$next \op__cia$6$next \op__msr$5$next \op__insn$4$next \op__fn_unit$3$next \op__insn_type$2$next } { \op__trapaddr$34 \op__traptype$33 \op__is_32bit$32 \op__cia$31 \op__msr$30 \op__insn$29 \op__fn_unit$28 \op__insn_type$27 }
end
sync init
update \op__insn_type$2 7'0000000
update \op__fn_unit$3 11'00000000000
update \op__insn$4 32'00000000000000000000000000000000
- update \op__is_32bit$5 1'0
- update \op__traptype$6 5'00000
- update \op__trapaddr$7 13'0000000000000
+ update \op__msr$5 64'0000000000000000000000000000000000000000000000000000000000000000
+ update \op__cia$6 64'0000000000000000000000000000000000000000000000000000000000000000
+ update \op__is_32bit$7 1'0
+ update \op__traptype$8 5'00000
+ update \op__trapaddr$9 13'0000000000000
sync posedge \clk
update \op__insn_type$2 \op__insn_type$2$next
update \op__fn_unit$3 \op__fn_unit$3$next
update \op__insn$4 \op__insn$4$next
- update \op__is_32bit$5 \op__is_32bit$5$next
- update \op__traptype$6 \op__traptype$6$next
- update \op__trapaddr$7 \op__trapaddr$7$next
+ update \op__msr$5 \op__msr$5$next
+ update \op__cia$6 \op__cia$6$next
+ update \op__is_32bit$7 \op__is_32bit$7$next
+ update \op__traptype$8 \op__traptype$8$next
+ update \op__trapaddr$9 \op__trapaddr$9$next
end
- process $group_41
+ process $group_45
assign \o$next \o
assign \o_ok$next \o_ok
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
switch { \n_i_rdy_data \p_valid_i_p_ready_o }
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
case 2'-1
- assign { \o_ok$next \o$next } { \o_ok$32 \o$31 }
+ assign { \o_ok$next \o$next } { \o_ok$36 \o$35 }
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
case 2'1-
- assign { \o_ok$next \o$next } { \o_ok$32 \o$31 }
+ assign { \o_ok$next \o$next } { \o_ok$36 \o$35 }
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
update \o \o$next
update \o_ok \o_ok$next
end
- process $group_43
- assign \fast1$8$next \fast1$8
+ process $group_47
+ assign \fast1$10$next \fast1$10
assign \fast1_ok$next \fast1_ok
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
switch { \n_i_rdy_data \p_valid_i_p_ready_o }
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
case 2'-1
- assign { \fast1_ok$next \fast1$8$next } { \fast1_ok$34 \fast1$33 }
+ assign { \fast1_ok$next \fast1$10$next } { \fast1_ok$38 \fast1$37 }
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
case 2'1-
- assign { \fast1_ok$next \fast1$8$next } { \fast1_ok$34 \fast1$33 }
+ assign { \fast1_ok$next \fast1$10$next } { \fast1_ok$38 \fast1$37 }
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
assign \fast1_ok$next 1'0
end
sync init
- update \fast1$8 64'0000000000000000000000000000000000000000000000000000000000000000
+ update \fast1$10 64'0000000000000000000000000000000000000000000000000000000000000000
update \fast1_ok 1'0
sync posedge \clk
- update \fast1$8 \fast1$8$next
+ update \fast1$10 \fast1$10$next
update \fast1_ok \fast1_ok$next
end
- process $group_45
- assign \fast2$9$next \fast2$9
+ process $group_49
+ assign \fast2$11$next \fast2$11
assign \fast2_ok$next \fast2_ok
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
switch { \n_i_rdy_data \p_valid_i_p_ready_o }
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
case 2'-1
- assign { \fast2_ok$next \fast2$9$next } { \fast2_ok$36 \fast2$35 }
+ assign { \fast2_ok$next \fast2$11$next } { \fast2_ok$40 \fast2$39 }
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
case 2'1-
- assign { \fast2_ok$next \fast2$9$next } { \fast2_ok$36 \fast2$35 }
+ assign { \fast2_ok$next \fast2$11$next } { \fast2_ok$40 \fast2$39 }
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
assign \fast2_ok$next 1'0
end
sync init
- update \fast2$9 64'0000000000000000000000000000000000000000000000000000000000000000
+ update \fast2$11 64'0000000000000000000000000000000000000000000000000000000000000000
update \fast2_ok 1'0
sync posedge \clk
- update \fast2$9 \fast2$9$next
+ update \fast2$11 \fast2$11$next
update \fast2_ok \fast2_ok$next
end
- process $group_47
+ process $group_51
assign \nia$next \nia
assign \nia_ok$next \nia_ok
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
switch { \n_i_rdy_data \p_valid_i_p_ready_o }
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
case 2'-1
- assign { \nia_ok$next \nia$next } { \nia_ok$38 \nia$37 }
+ assign { \nia_ok$next \nia$next } { \nia_ok$42 \nia$41 }
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
case 2'1-
- assign { \nia_ok$next \nia$next } { \nia_ok$38 \nia$37 }
+ assign { \nia_ok$next \nia$next } { \nia_ok$42 \nia$41 }
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
update \nia \nia$next
update \nia_ok \nia_ok$next
end
- process $group_49
- assign \msr$10$next \msr$10
+ process $group_53
+ assign \msr$next \msr
assign \msr_ok$next \msr_ok
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
switch { \n_i_rdy_data \p_valid_i_p_ready_o }
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
case 2'-1
- assign { \msr_ok$next \msr$10$next } { \msr_ok$40 \msr$39 }
+ assign { \msr_ok$next \msr$next } { \msr_ok$44 \msr$43 }
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
case 2'1-
- assign { \msr_ok$next \msr$10$next } { \msr_ok$40 \msr$39 }
+ assign { \msr_ok$next \msr$next } { \msr_ok$44 \msr$43 }
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
assign \msr_ok$next 1'0
end
sync init
- update \msr$10 64'0000000000000000000000000000000000000000000000000000000000000000
+ update \msr 64'0000000000000000000000000000000000000000000000000000000000000000
update \msr_ok 1'0
sync posedge \clk
- update \msr$10 \msr$10$next
+ update \msr \msr$next
update \msr_ok \msr_ok$next
end
- process $group_51
+ process $group_55
assign \n_valid_o 1'0
assign \n_valid_o \r_busy
sync init
end
- process $group_52
+ process $group_56
assign \p_ready_o 1'0
assign \p_ready_o \n_i_rdy_data
sync init
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 2 \o_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 output 3 \o
+ wire width 1 output 3 \fast1_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 4 \fast1_ok
+ wire width 1 output 4 \fast2_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 output 5 \fast1
+ wire width 1 output 5 \nia_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 6 \fast2_ok
+ wire width 1 output 6 \msr_ok
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
+ wire width 1 output 7 \n_valid_o
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
+ wire width 1 input 8 \n_ready_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 output 7 \fast2
+ wire width 64 output 9 \o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 8 \nia_ok
+ wire width 64 output 10 \fast1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 output 9 \nia
+ wire width 64 output 11 \fast2
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 10 \msr_ok
+ wire width 64 output 12 \nia
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 output 11 \msr
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244"
- wire width 1 output 12 \n_valid_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245"
- wire width 1 input 13 \n_ready_i
- attribute \enum_base_type "InternalOp"
+ wire width 64 output 13 \msr
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 7 input 14 \op__insn_type
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00100000000 "MUL"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 11 input 15 \op__fn_unit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 32 input 16 \op__insn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
- wire width 1 input 17 \op__is_32bit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
- wire width 5 input 18 \op__traptype
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
- wire width 13 input 19 \op__trapaddr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
- wire width 64 input 20 \ra
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
- wire width 64 input 21 \rb
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
- wire width 64 input 22 \fast1$1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
- wire width 64 input 23 \fast2$2
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
- wire width 64 input 24 \cia
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
- wire width 64 input 25 \msr$3
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 input 17 \op__msr
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 input 18 \op__cia
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 19 \op__is_32bit
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 5 input 20 \op__traptype
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 13 input 21 \op__trapaddr
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 64 input 22 \ra
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 64 input 23 \rb
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 64 input 24 \fast1$1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 64 input 25 \fast2$2
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153"
wire width 1 input 26 \p_valid_i
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154"
wire width 1 output 27 \p_ready_o
cell \p$30 \p
connect \p_valid_i \p_valid_i
connect \n_valid_o \n_valid_o
connect \n_ready_i \n_ready_i
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153"
wire width 1 \pipe_p_valid_i
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154"
wire width 1 \pipe_p_ready_o
- attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
wire width 2 \pipe_muxid
- attribute \enum_base_type "InternalOp"
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 7 \pipe_op__insn_type
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00100000000 "MUL"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 11 \pipe_op__fn_unit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 32 \pipe_op__insn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 \pipe_op__msr
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 \pipe_op__cia
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \pipe_op__is_32bit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 5 \pipe_op__traptype
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 13 \pipe_op__trapaddr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
wire width 64 \pipe_ra
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
wire width 64 \pipe_rb
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
wire width 64 \pipe_fast1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
wire width 64 \pipe_fast2
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
- wire width 64 \pipe_cia
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
- wire width 64 \pipe_msr
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
wire width 1 \pipe_n_valid_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
wire width 1 \pipe_n_ready_i
- attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
- wire width 2 \pipe_muxid$4
- attribute \enum_base_type "InternalOp"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+ wire width 2 \pipe_muxid$3
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
- wire width 7 \pipe_op__insn_type$5
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 7 \pipe_op__insn_type$4
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00000000010 "ALU"
attribute \enum_value_00100000000 "MUL"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
- wire width 11 \pipe_op__fn_unit$6
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
- wire width 32 \pipe_op__insn$7
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
- wire width 1 \pipe_op__is_32bit$8
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
- wire width 5 \pipe_op__traptype$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
- wire width 13 \pipe_op__trapaddr$10
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 11 \pipe_op__fn_unit$5
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 \pipe_op__insn$6
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 \pipe_op__msr$7
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 \pipe_op__cia$8
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \pipe_op__is_32bit$9
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 5 \pipe_op__traptype$10
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 13 \pipe_op__trapaddr$11
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 64 \pipe_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 \pipe_o_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 \pipe_fast1$11
+ wire width 64 \pipe_fast1$12
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 \pipe_fast1_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 \pipe_fast2$12
+ wire width 64 \pipe_fast2$13
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 \pipe_fast2_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 \pipe_nia_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 \pipe_msr$13
+ wire width 64 \pipe_msr
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 \pipe_msr_ok
cell \pipe$32 \pipe
connect \op__insn_type \pipe_op__insn_type
connect \op__fn_unit \pipe_op__fn_unit
connect \op__insn \pipe_op__insn
+ connect \op__msr \pipe_op__msr
+ connect \op__cia \pipe_op__cia
connect \op__is_32bit \pipe_op__is_32bit
connect \op__traptype \pipe_op__traptype
connect \op__trapaddr \pipe_op__trapaddr
connect \rb \pipe_rb
connect \fast1 \pipe_fast1
connect \fast2 \pipe_fast2
- connect \cia \pipe_cia
- connect \msr \pipe_msr
connect \n_valid_o \pipe_n_valid_o
connect \n_ready_i \pipe_n_ready_i
- connect \muxid$1 \pipe_muxid$4
- connect \op__insn_type$2 \pipe_op__insn_type$5
- connect \op__fn_unit$3 \pipe_op__fn_unit$6
- connect \op__insn$4 \pipe_op__insn$7
- connect \op__is_32bit$5 \pipe_op__is_32bit$8
- connect \op__traptype$6 \pipe_op__traptype$9
- connect \op__trapaddr$7 \pipe_op__trapaddr$10
+ connect \muxid$1 \pipe_muxid$3
+ connect \op__insn_type$2 \pipe_op__insn_type$4
+ connect \op__fn_unit$3 \pipe_op__fn_unit$5
+ connect \op__insn$4 \pipe_op__insn$6
+ connect \op__msr$5 \pipe_op__msr$7
+ connect \op__cia$6 \pipe_op__cia$8
+ connect \op__is_32bit$7 \pipe_op__is_32bit$9
+ connect \op__traptype$8 \pipe_op__traptype$10
+ connect \op__trapaddr$9 \pipe_op__trapaddr$11
connect \o \pipe_o
connect \o_ok \pipe_o_ok
- connect \fast1$8 \pipe_fast1$11
+ connect \fast1$10 \pipe_fast1$12
connect \fast1_ok \pipe_fast1_ok
- connect \fast2$9 \pipe_fast2$12
+ connect \fast2$11 \pipe_fast2$13
connect \fast2_ok \pipe_fast2_ok
connect \nia \pipe_nia
connect \nia_ok \pipe_nia_ok
- connect \msr$10 \pipe_msr$13
+ connect \msr \pipe_msr
connect \msr_ok \pipe_msr_ok
end
process $group_0
assign \p_ready_o \pipe_p_ready_o
sync init
end
- attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
wire width 2 \muxid
process $group_2
assign \pipe_muxid 2'00
assign \pipe_op__insn_type 7'0000000
assign \pipe_op__fn_unit 11'00000000000
assign \pipe_op__insn 32'00000000000000000000000000000000
+ assign \pipe_op__msr 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \pipe_op__cia 64'0000000000000000000000000000000000000000000000000000000000000000
assign \pipe_op__is_32bit 1'0
assign \pipe_op__traptype 5'00000
assign \pipe_op__trapaddr 13'0000000000000
- assign { \pipe_op__trapaddr \pipe_op__traptype \pipe_op__is_32bit \pipe_op__insn \pipe_op__fn_unit \pipe_op__insn_type } { \op__trapaddr \op__traptype \op__is_32bit \op__insn \op__fn_unit \op__insn_type }
+ assign { \pipe_op__trapaddr \pipe_op__traptype \pipe_op__is_32bit \pipe_op__cia \pipe_op__msr \pipe_op__insn \pipe_op__fn_unit \pipe_op__insn_type } { \op__trapaddr \op__traptype \op__is_32bit \op__cia \op__msr \op__insn \op__fn_unit \op__insn_type }
sync init
end
- process $group_9
+ process $group_11
assign \pipe_ra 64'0000000000000000000000000000000000000000000000000000000000000000
assign \pipe_ra \ra
sync init
end
- process $group_10
+ process $group_12
assign \pipe_rb 64'0000000000000000000000000000000000000000000000000000000000000000
assign \pipe_rb \rb
sync init
end
- process $group_11
+ process $group_13
assign \pipe_fast1 64'0000000000000000000000000000000000000000000000000000000000000000
assign \pipe_fast1 \fast1$1
sync init
end
- process $group_12
+ process $group_14
assign \pipe_fast2 64'0000000000000000000000000000000000000000000000000000000000000000
assign \pipe_fast2 \fast2$2
sync init
end
- process $group_13
- assign \pipe_cia 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \pipe_cia \cia
- sync init
- end
- process $group_14
- assign \pipe_msr 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \pipe_msr \msr$3
- sync init
- end
process $group_15
assign \n_valid_o 1'0
assign \n_valid_o \pipe_n_valid_o
assign \pipe_n_ready_i \n_ready_i
sync init
end
- attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
wire width 2 \muxid$14
process $group_17
assign \muxid$14 2'00
- assign \muxid$14 \pipe_muxid$4
+ assign \muxid$14 \pipe_muxid$3
sync init
end
- attribute \enum_base_type "InternalOp"
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 7 \op__insn_type$15
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00100000000 "MUL"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 11 \op__fn_unit$16
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 32 \op__insn$17
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
- wire width 1 \op__is_32bit$18
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
- wire width 5 \op__traptype$19
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
- wire width 13 \op__trapaddr$20
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 \op__msr$18
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 \op__cia$19
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__is_32bit$20
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 5 \op__traptype$21
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 13 \op__trapaddr$22
process $group_18
assign \op__insn_type$15 7'0000000
assign \op__fn_unit$16 11'00000000000
assign \op__insn$17 32'00000000000000000000000000000000
- assign \op__is_32bit$18 1'0
- assign \op__traptype$19 5'00000
- assign \op__trapaddr$20 13'0000000000000
- assign { \op__trapaddr$20 \op__traptype$19 \op__is_32bit$18 \op__insn$17 \op__fn_unit$16 \op__insn_type$15 } { \pipe_op__trapaddr$10 \pipe_op__traptype$9 \pipe_op__is_32bit$8 \pipe_op__insn$7 \pipe_op__fn_unit$6 \pipe_op__insn_type$5 }
+ assign \op__msr$18 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \op__cia$19 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \op__is_32bit$20 1'0
+ assign \op__traptype$21 5'00000
+ assign \op__trapaddr$22 13'0000000000000
+ assign { \op__trapaddr$22 \op__traptype$21 \op__is_32bit$20 \op__cia$19 \op__msr$18 \op__insn$17 \op__fn_unit$16 \op__insn_type$15 } { \pipe_op__trapaddr$11 \pipe_op__traptype$10 \pipe_op__is_32bit$9 \pipe_op__cia$8 \pipe_op__msr$7 \pipe_op__insn$6 \pipe_op__fn_unit$5 \pipe_op__insn_type$4 }
sync init
end
- process $group_24
+ process $group_26
assign \o 64'0000000000000000000000000000000000000000000000000000000000000000
assign \o_ok 1'0
assign { \o_ok \o } { \pipe_o_ok \pipe_o }
sync init
end
- process $group_26
+ process $group_28
assign \fast1 64'0000000000000000000000000000000000000000000000000000000000000000
assign \fast1_ok 1'0
- assign { \fast1_ok \fast1 } { \pipe_fast1_ok \pipe_fast1$11 }
+ assign { \fast1_ok \fast1 } { \pipe_fast1_ok \pipe_fast1$12 }
sync init
end
- process $group_28
+ process $group_30
assign \fast2 64'0000000000000000000000000000000000000000000000000000000000000000
assign \fast2_ok 1'0
- assign { \fast2_ok \fast2 } { \pipe_fast2_ok \pipe_fast2$12 }
+ assign { \fast2_ok \fast2 } { \pipe_fast2_ok \pipe_fast2$13 }
sync init
end
- process $group_30
+ process $group_32
assign \nia 64'0000000000000000000000000000000000000000000000000000000000000000
assign \nia_ok 1'0
assign { \nia_ok \nia } { \pipe_nia_ok \pipe_nia }
sync init
end
- process $group_32
+ process $group_34
assign \msr 64'0000000000000000000000000000000000000000000000000000000000000000
assign \msr_ok 1'0
- assign { \msr_ok \msr } { \pipe_msr_ok \pipe_msr$13 }
+ assign { \msr_ok \msr } { \pipe_msr_ok \pipe_msr }
sync init
end
connect \muxid 2'00
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
- wire width 6 input 2 \s_src
+ wire width 4 input 2 \s_src
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
- wire width 6 input 3 \r_src
+ wire width 4 input 3 \r_src
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
- wire width 6 output 4 \q_src
+ wire width 4 output 4 \q_src
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
- wire width 6 \q_int
+ wire width 4 \q_int
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
- wire width 6 \q_int$next
+ wire width 4 \q_int$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
- wire width 6 $1
+ wire width 4 $1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
cell $not $2
parameter \A_SIGNED 0
- parameter \A_WIDTH 6
- parameter \Y_WIDTH 6
+ parameter \A_WIDTH 4
+ parameter \Y_WIDTH 4
connect \A \r_src
connect \Y $1
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
- wire width 6 $3
+ wire width 4 $3
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
cell $and $4
parameter \A_SIGNED 0
- parameter \A_WIDTH 6
+ parameter \A_WIDTH 4
parameter \B_SIGNED 0
- parameter \B_WIDTH 6
- parameter \Y_WIDTH 6
+ parameter \B_WIDTH 4
+ parameter \Y_WIDTH 4
connect \A \q_int
connect \B $1
connect \Y $3
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
- wire width 6 $5
+ wire width 4 $5
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
cell $or $6
parameter \A_SIGNED 0
- parameter \A_WIDTH 6
+ parameter \A_WIDTH 4
parameter \B_SIGNED 0
- parameter \B_WIDTH 6
- parameter \Y_WIDTH 6
+ parameter \B_WIDTH 4
+ parameter \Y_WIDTH 4
connect \A $3
connect \B \s_src
connect \Y $5
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
- assign \q_int$next 6'000000
+ assign \q_int$next 4'0000
end
sync init
- update \q_int 6'000000
+ update \q_int 4'0000
sync posedge \clk
update \q_int \q_int$next
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
- wire width 6 $7
+ wire width 4 $7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
cell $not $8
parameter \A_SIGNED 0
- parameter \A_WIDTH 6
- parameter \Y_WIDTH 6
+ parameter \A_WIDTH 4
+ parameter \Y_WIDTH 4
connect \A \r_src
connect \Y $7
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
- wire width 6 $9
+ wire width 4 $9
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
cell $and $10
parameter \A_SIGNED 0
- parameter \A_WIDTH 6
+ parameter \A_WIDTH 4
parameter \B_SIGNED 0
- parameter \B_WIDTH 6
- parameter \Y_WIDTH 6
+ parameter \B_WIDTH 4
+ parameter \Y_WIDTH 4
connect \A \q_int
connect \B $7
connect \Y $9
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
- wire width 6 $11
+ wire width 4 $11
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
cell $or $12
parameter \A_SIGNED 0
- parameter \A_WIDTH 6
+ parameter \A_WIDTH 4
parameter \B_SIGNED 0
- parameter \B_WIDTH 6
- parameter \Y_WIDTH 6
+ parameter \B_WIDTH 4
+ parameter \Y_WIDTH 4
connect \A $9
connect \B \s_src
connect \Y $11
end
process $group_1
- assign \q_src 6'000000
+ assign \q_src 4'0000
assign \q_src $11
sync init
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
- wire width 6 \qn_src
+ wire width 4 \qn_src
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
- wire width 6 $13
+ wire width 4 $13
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
cell $not $14
parameter \A_SIGNED 0
- parameter \A_WIDTH 6
- parameter \Y_WIDTH 6
+ parameter \A_WIDTH 4
+ parameter \Y_WIDTH 4
connect \A \q_src
connect \Y $13
end
process $group_2
- assign \qn_src 6'000000
+ assign \qn_src 4'0000
assign \qn_src $13
sync init
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62"
- wire width 6 \qlq_src
+ wire width 4 \qlq_src
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
- wire width 6 $15
+ wire width 4 $15
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
cell $or $16
parameter \A_SIGNED 0
- parameter \A_WIDTH 6
+ parameter \A_WIDTH 4
parameter \B_SIGNED 0
- parameter \B_WIDTH 6
- parameter \Y_WIDTH 6
+ parameter \B_WIDTH 4
+ parameter \Y_WIDTH 4
connect \A \q_src
connect \B \q_int
connect \Y $15
end
process $group_3
- assign \qlq_src 6'000000
+ assign \qlq_src 4'0000
assign \qlq_src $15
sync init
end
wire width 1 input 0 \rst
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
- attribute \enum_base_type "InternalOp"
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 7 input 2 \oper_i__insn_type
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00100000000 "MUL"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 11 input 3 \oper_i__fn_unit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 32 input 4 \oper_i__insn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
- wire width 1 input 5 \oper_i__is_32bit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
- wire width 5 input 6 \oper_i__traptype
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
- wire width 13 input 7 \oper_i__trapaddr
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 input 5 \oper_i__msr
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 input 6 \oper_i__cia
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 7 \oper_i__is_32bit
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 5 input 8 \oper_i__traptype
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 13 input 9 \oper_i__trapaddr
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94"
- wire width 1 input 8 \issue_i
+ wire width 1 input 10 \issue_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
- wire width 1 output 9 \busy_o
+ wire width 1 output 11 \busy_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:92"
- wire width 6 input 10 \rdmaskn
+ wire width 4 input 12 \rdmaskn
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 6 output 11 \rd__rel
+ wire width 4 output 13 \rd__rel
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 6 input 12 \rd__go
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
- wire width 64 input 13 \src1_i
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
- wire width 64 input 14 \src2_i
+ wire width 4 input 14 \rd__go
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
- wire width 64 input 15 \src3_i
+ wire width 64 input 15 \src1_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
- wire width 64 input 16 \src4_i
+ wire width 64 input 16 \src2_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
- wire width 64 input 17 \src5_i
+ wire width 64 input 17 \src3_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
- wire width 64 input 18 \src6_i
+ wire width 64 input 18 \src4_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 19 \o_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
wire width 5 output 20 \wr__rel
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
wire width 5 input 21 \wr__go
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 output 22 \o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
+ wire width 64 output 22 \dest1_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 23 \fast1_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 output 24 \fast1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
+ wire width 64 output 24 \dest2_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 25 \fast2_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 output 26 \fast2
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
+ wire width 64 output 26 \dest3_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 27 \nia_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 output 28 \nia
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
+ wire width 64 output 28 \dest4_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 29 \msr_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 output 30 \msr
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
+ wire width 64 output 30 \dest5_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96"
wire width 1 input 31 \go_die_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
wire width 1 input 32 \shadown_i
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
- wire width 64 output 33 \dest1_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
wire width 1 \alu_trap0_n_valid_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
wire width 1 \alu_trap0_n_ready_i
- attribute \enum_base_type "InternalOp"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 64 \alu_trap0_o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 64 \alu_trap0_fast1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 64 \alu_trap0_fast2
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 64 \alu_trap0_nia
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 64 \alu_trap0_msr
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 7 \alu_trap0_op__insn_type
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00100000000 "MUL"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 11 \alu_trap0_op__fn_unit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 32 \alu_trap0_op__insn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 \alu_trap0_op__msr
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 \alu_trap0_op__cia
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \alu_trap0_op__is_32bit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 5 \alu_trap0_op__traptype
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 13 \alu_trap0_op__trapaddr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
wire width 64 \alu_trap0_ra
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
wire width 64 \alu_trap0_rb
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
- wire width 64 \alu_trap0_fast1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
- wire width 64 \alu_trap0_fast2
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
- wire width 64 \alu_trap0_cia
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
- wire width 64 \alu_trap0_msr
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 64 \alu_trap0_fast1$1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 64 \alu_trap0_fast2$2
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153"
wire width 1 \alu_trap0_p_valid_i
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154"
wire width 1 \alu_trap0_p_ready_o
cell \alu_trap0 \alu_trap0
connect \rst \rst
connect \clk \clk
connect \o_ok \o_ok
- connect \o \o
connect \fast1_ok \fast1_ok
- connect \fast1 \fast1
connect \fast2_ok \fast2_ok
- connect \fast2 \fast2
connect \nia_ok \nia_ok
- connect \nia \nia
connect \msr_ok \msr_ok
- connect \msr \msr
connect \n_valid_o \alu_trap0_n_valid_o
connect \n_ready_i \alu_trap0_n_ready_i
+ connect \o \alu_trap0_o
+ connect \fast1 \alu_trap0_fast1
+ connect \fast2 \alu_trap0_fast2
+ connect \nia \alu_trap0_nia
+ connect \msr \alu_trap0_msr
connect \op__insn_type \alu_trap0_op__insn_type
connect \op__fn_unit \alu_trap0_op__fn_unit
connect \op__insn \alu_trap0_op__insn
+ connect \op__msr \alu_trap0_op__msr
+ connect \op__cia \alu_trap0_op__cia
connect \op__is_32bit \alu_trap0_op__is_32bit
connect \op__traptype \alu_trap0_op__traptype
connect \op__trapaddr \alu_trap0_op__trapaddr
connect \ra \alu_trap0_ra
connect \rb \alu_trap0_rb
- connect \fast1$1 \alu_trap0_fast1
- connect \fast2$2 \alu_trap0_fast2
- connect \cia \alu_trap0_cia
- connect \msr$3 \alu_trap0_msr
+ connect \fast1$1 \alu_trap0_fast1$1
+ connect \fast2$2 \alu_trap0_fast2$2
connect \p_valid_i \alu_trap0_p_valid_i
connect \p_ready_o \alu_trap0_p_ready_o
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
- wire width 6 \src_l_s_src
+ wire width 4 \src_l_s_src
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
- wire width 6 \src_l_s_src$next
+ wire width 4 \src_l_s_src$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
- wire width 6 \src_l_r_src
+ wire width 4 \src_l_r_src
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
- wire width 6 \src_l_r_src$next
+ wire width 4 \src_l_r_src$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
- wire width 6 \src_l_q_src
+ wire width 4 \src_l_q_src
cell \src_l$36 \src_l
connect \rst \rst
connect \clk \clk
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:178"
wire width 1 \all_rd
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179"
- wire width 1 $1
+ wire width 1 $3
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179"
- cell $and $2
+ cell $and $4
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \busy_o
connect \B \rok_l_q_rdok
- connect \Y $1
+ connect \Y $3
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180"
- wire width 1 $3
+ wire width 1 $5
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180"
- wire width 6 $4
+ wire width 4 $6
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180"
- cell $not $5
+ cell $not $7
parameter \A_SIGNED 0
- parameter \A_WIDTH 6
- parameter \Y_WIDTH 6
+ parameter \A_WIDTH 4
+ parameter \Y_WIDTH 4
connect \A \rd__rel
- connect \Y $4
+ connect \Y $6
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180"
- wire width 6 $6
+ wire width 4 $8
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180"
- cell $or $7
+ cell $or $9
parameter \A_SIGNED 0
- parameter \A_WIDTH 6
+ parameter \A_WIDTH 4
parameter \B_SIGNED 0
- parameter \B_WIDTH 6
- parameter \Y_WIDTH 6
- connect \A $4
+ parameter \B_WIDTH 4
+ parameter \Y_WIDTH 4
+ connect \A $6
connect \B \rd__go
- connect \Y $6
+ connect \Y $8
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180"
- cell $reduce_and $8
+ cell $reduce_and $10
parameter \A_SIGNED 0
- parameter \A_WIDTH 6
+ parameter \A_WIDTH 4
parameter \Y_WIDTH 1
- connect \A $6
- connect \Y $3
+ connect \A $8
+ connect \Y $5
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180"
- wire width 1 $9
+ wire width 1 $11
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180"
- cell $and $10
+ cell $and $12
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $1
- connect \B $3
- connect \Y $9
+ connect \A $3
+ connect \B $5
+ connect \Y $11
end
process $group_0
assign \all_rd 1'0
- assign \all_rd $9
+ assign \all_rd $11
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:183"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:184"
wire width 1 \all_rd_pulse
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:186"
- wire width 1 $11
+ wire width 1 $13
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:186"
- cell $not $12
+ cell $not $14
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \all_rd_dly
- connect \Y $11
+ connect \Y $13
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:186"
- wire width 1 $13
+ wire width 1 $15
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:186"
- cell $and $14
+ cell $and $16
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \all_rd
- connect \B $11
- connect \Y $13
+ connect \B $13
+ connect \Y $15
end
process $group_2
assign \all_rd_pulse 1'0
- assign \all_rd_pulse $13
+ assign \all_rd_pulse $15
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:191"
wire width 1 \alu_pulse
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:195"
- wire width 1 $15
+ wire width 1 $17
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:195"
- cell $not $16
+ cell $not $18
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \alu_done_dly
- connect \Y $15
+ connect \Y $17
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:195"
- wire width 1 $17
+ wire width 1 $19
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:195"
- cell $and $18
+ cell $and $20
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \alu_done
- connect \B $15
- connect \Y $17
+ connect \B $17
+ connect \Y $19
end
process $group_5
assign \alu_pulse 1'0
- assign \alu_pulse $17
+ assign \alu_pulse $19
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:192"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:199"
wire width 5 \prev_wr_go$next
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:201"
- wire width 5 $19
+ wire width 5 $21
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:201"
- cell $and $20
+ cell $and $22
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A \wr__go
connect \B { \busy_o \busy_o \busy_o \busy_o \busy_o }
- connect \Y $19
+ connect \Y $21
end
process $group_7
assign \prev_wr_go$next \prev_wr_go
- assign \prev_wr_go$next $19
+ assign \prev_wr_go$next $21
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100"
wire width 1 \done_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
- wire width 1 $21
+ wire width 1 $23
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
- wire width 1 $22
+ wire width 1 $24
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
- wire width 5 $23
+ wire width 5 $25
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:93"
wire width 5 \wrmask
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
- cell $not $24
+ cell $not $26
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \Y_WIDTH 5
connect \A \wrmask
- connect \Y $23
+ connect \Y $25
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
- wire width 5 $25
+ wire width 5 $27
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
- cell $and $26
+ cell $and $28
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \B_WIDTH 5
parameter \Y_WIDTH 5
connect \A \wr__rel
- connect \B $23
- connect \Y $25
+ connect \B $25
+ connect \Y $27
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
- cell $reduce_bool $27
+ cell $reduce_bool $29
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \Y_WIDTH 1
- connect \A $25
- connect \Y $22
+ connect \A $27
+ connect \Y $24
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
- cell $not $28
+ cell $not $30
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $22
- connect \Y $21
+ connect \A $24
+ connect \Y $23
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
- wire width 1 $29
+ wire width 1 $31
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
- cell $and $30
+ cell $and $32
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \busy_o
- connect \B $21
- connect \Y $29
+ connect \B $23
+ connect \Y $31
end
process $group_8
assign \done_o 1'0
- assign \done_o $29
+ assign \done_o $31
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206"
wire width 1 \wr_any
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210"
- wire width 1 $31
+ wire width 1 $33
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210"
- cell $reduce_bool $32
+ cell $reduce_bool $34
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \Y_WIDTH 1
connect \A \wr__go
- connect \Y $31
+ connect \Y $33
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210"
- wire width 1 $33
+ wire width 1 $35
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210"
- cell $reduce_bool $34
+ cell $reduce_bool $36
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \Y_WIDTH 1
connect \A \prev_wr_go
- connect \Y $33
+ connect \Y $35
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210"
- wire width 1 $35
+ wire width 1 $37
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210"
- cell $or $36
+ cell $or $38
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $31
- connect \B $33
- connect \Y $35
+ connect \A $33
+ connect \B $35
+ connect \Y $37
end
process $group_9
assign \wr_any 1'0
- assign \wr_any $35
+ assign \wr_any $37
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:207"
wire width 1 \req_done
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211"
- wire width 1 $37
+ wire width 1 $39
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211"
- cell $not $38
+ cell $not $40
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \alu_trap0_n_ready_i
- connect \Y $37
+ connect \Y $39
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211"
- wire width 1 $39
+ wire width 1 $41
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211"
- cell $and $40
+ cell $and $42
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \wr_any
- connect \B $37
- connect \Y $39
+ connect \B $39
+ connect \Y $41
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212"
- wire width 5 $41
+ wire width 5 $43
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212"
- cell $and $42
+ cell $and $44
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A \req_l_q_req
connect \B \wrmask
- connect \Y $41
+ connect \Y $43
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212"
- wire width 1 $43
+ wire width 1 $45
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212"
- cell $eq $44
+ cell $eq $46
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $41
+ connect \A $43
connect \B 1'0
- connect \Y $43
+ connect \Y $45
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212"
- wire width 1 $45
+ wire width 1 $47
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212"
- cell $and $46
+ cell $and $48
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $39
- connect \B $43
- connect \Y $45
+ connect \A $41
+ connect \B $45
+ connect \Y $47
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
- wire width 1 $47
+ wire width 1 $49
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
- cell $eq $48
+ cell $eq $50
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wrmask
connect \B 1'0
- connect \Y $47
+ connect \Y $49
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
- wire width 1 $49
+ wire width 1 $51
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
- cell $and $50
+ cell $and $52
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $47
+ connect \A $49
connect \B \alu_trap0_n_ready_i
- connect \Y $49
+ connect \Y $51
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
- wire width 1 $51
+ wire width 1 $53
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
- cell $and $52
+ cell $and $54
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $49
+ connect \A $51
connect \B \alu_trap0_n_valid_o
- connect \Y $51
+ connect \Y $53
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
- wire width 1 $53
+ wire width 1 $55
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
- cell $and $54
+ cell $and $56
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $51
+ connect \A $53
connect \B \busy_o
- connect \Y $53
+ connect \Y $55
end
process $group_10
assign \req_done 1'0
- assign \req_done $45
+ assign \req_done $47
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
- switch { $53 }
+ switch { $55 }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
case 1'1
assign \req_done 1'1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:221"
wire width 1 \reset
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
- wire width 1 $55
+ wire width 1 $57
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
- cell $or $56
+ cell $or $58
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \req_done
connect \B \go_die_i
- connect \Y $55
+ connect \Y $57
end
process $group_11
assign \reset 1'0
- assign \reset $55
+ assign \reset $57
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222"
wire width 1 \rst_r
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226"
- wire width 1 $57
+ wire width 1 $59
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226"
- cell $or $58
+ cell $or $60
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \issue_i
connect \B \go_die_i
- connect \Y $57
+ connect \Y $59
end
process $group_12
assign \rst_r 1'0
- assign \rst_r $57
+ assign \rst_r $59
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:223"
wire width 5 \reset_w
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227"
- wire width 5 $59
+ wire width 5 $61
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227"
- cell $or $60
+ cell $or $62
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A \wr__go
connect \B { \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i }
- connect \Y $59
+ connect \Y $61
end
process $group_13
assign \reset_w 5'00000
- assign \reset_w $59
+ assign \reset_w $61
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:224"
- wire width 6 \reset_r
+ wire width 4 \reset_r
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:228"
- wire width 6 $61
+ wire width 4 $63
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:228"
- cell $or $62
+ cell $or $64
parameter \A_SIGNED 0
- parameter \A_WIDTH 6
+ parameter \A_WIDTH 4
parameter \B_SIGNED 0
- parameter \B_WIDTH 6
- parameter \Y_WIDTH 6
+ parameter \B_WIDTH 4
+ parameter \Y_WIDTH 4
connect \A \rd__go
- connect \B { \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i }
- connect \Y $61
+ connect \B { \go_die_i \go_die_i \go_die_i \go_die_i }
+ connect \Y $63
end
process $group_14
- assign \reset_r 6'000000
- assign \reset_r $61
+ assign \reset_r 4'0000
+ assign \reset_r $63
sync init
end
process $group_15
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232"
- wire width 1 $63
+ wire width 1 $65
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232"
- cell $and $64
+ cell $and $66
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \alu_trap0_n_valid_o
connect \B \busy_o
- connect \Y $63
+ connect \Y $65
end
process $group_16
assign \rok_l_r_rdok$next \rok_l_r_rdok
- assign \rok_l_r_rdok$next $63
+ assign \rok_l_r_rdok$next $65
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
end
process $group_21
assign \src_l_s_src$next \src_l_s_src
- assign \src_l_s_src$next { \issue_i \issue_i \issue_i \issue_i \issue_i \issue_i }
+ assign \src_l_s_src$next { \issue_i \issue_i \issue_i \issue_i }
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
- assign \src_l_s_src$next 6'000000
+ assign \src_l_s_src$next 4'0000
end
sync init
- update \src_l_s_src 6'000000
+ update \src_l_s_src 4'0000
sync posedge \clk
update \src_l_s_src \src_l_s_src$next
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
- assign \src_l_r_src$next 6'111111
+ assign \src_l_r_src$next 4'1111
end
sync init
- update \src_l_r_src 6'111111
+ update \src_l_r_src 4'1111
sync posedge \clk
update \src_l_r_src \src_l_r_src$next
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:247"
- wire width 5 $65
+ wire width 5 $67
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:247"
- cell $and $66
+ cell $and $68
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A \alu_pulsem
connect \B \wrmask
- connect \Y $65
+ connect \Y $67
end
process $group_23
assign \req_l_s_req 5'00000
- assign \req_l_s_req $65
+ assign \req_l_s_req $67
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:248"
- wire width 5 $67
+ wire width 5 $69
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:248"
- cell $or $68
+ cell $or $70
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \Y_WIDTH 5
connect \A \reset_w
connect \B \prev_wr_go
- connect \Y $67
+ connect \Y $69
end
process $group_24
assign \req_l_r_req 5'11111
- assign \req_l_r_req $67
+ assign \req_l_r_req $69
sync init
end
- attribute \enum_base_type "InternalOp"
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 7 \oper_r__insn_type
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00100000000 "MUL"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 11 \oper_r__fn_unit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 32 \oper_r__insn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 \oper_r__msr
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 \oper_r__cia
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \oper_r__is_32bit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 5 \oper_r__traptype
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 13 \oper_r__trapaddr
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
wire width 7 \oper_l__insn_type
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
wire width 32 \oper_l__insn$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+ wire width 64 \oper_l__msr
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+ wire width 64 \oper_l__msr$next
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+ wire width 64 \oper_l__cia
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+ wire width 64 \oper_l__cia$next
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
wire width 1 \oper_l__is_32bit
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
wire width 1 \oper_l__is_32bit$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
wire width 13 \oper_l__trapaddr$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
- wire width 69 $69
+ wire width 197 $71
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
- cell $mux $70
- parameter \WIDTH 69
- connect \A { \oper_l__trapaddr \oper_l__traptype \oper_l__is_32bit \oper_l__insn \oper_l__fn_unit \oper_l__insn_type }
- connect \B { \oper_i__trapaddr \oper_i__traptype \oper_i__is_32bit \oper_i__insn \oper_i__fn_unit \oper_i__insn_type }
+ cell $mux $72
+ parameter \WIDTH 197
+ connect \A { \oper_l__trapaddr \oper_l__traptype \oper_l__is_32bit \oper_l__cia \oper_l__msr \oper_l__insn \oper_l__fn_unit \oper_l__insn_type }
+ connect \B { \oper_i__trapaddr \oper_i__traptype \oper_i__is_32bit \oper_i__cia \oper_i__msr \oper_i__insn \oper_i__fn_unit \oper_i__insn_type }
connect \S \issue_i
- connect \Y $69
+ connect \Y $71
end
process $group_25
assign \oper_r__insn_type 7'0000000
assign \oper_r__fn_unit 11'00000000000
assign \oper_r__insn 32'00000000000000000000000000000000
+ assign \oper_r__msr 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \oper_r__cia 64'0000000000000000000000000000000000000000000000000000000000000000
assign \oper_r__is_32bit 1'0
assign \oper_r__traptype 5'00000
assign \oper_r__trapaddr 13'0000000000000
- assign { \oper_r__trapaddr \oper_r__traptype \oper_r__is_32bit \oper_r__insn \oper_r__fn_unit \oper_r__insn_type } $69
+ assign { \oper_r__trapaddr \oper_r__traptype \oper_r__is_32bit \oper_r__cia \oper_r__msr \oper_r__insn \oper_r__fn_unit \oper_r__insn_type } $71
sync init
end
- process $group_31
+ process $group_33
assign \oper_l__insn_type$next \oper_l__insn_type
assign \oper_l__fn_unit$next \oper_l__fn_unit
assign \oper_l__insn$next \oper_l__insn
+ assign \oper_l__msr$next \oper_l__msr
+ assign \oper_l__cia$next \oper_l__cia
assign \oper_l__is_32bit$next \oper_l__is_32bit
assign \oper_l__traptype$next \oper_l__traptype
assign \oper_l__trapaddr$next \oper_l__trapaddr
switch { \issue_i }
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
case 1'1
- assign { \oper_l__trapaddr$next \oper_l__traptype$next \oper_l__is_32bit$next \oper_l__insn$next \oper_l__fn_unit$next \oper_l__insn_type$next } { \oper_i__trapaddr \oper_i__traptype \oper_i__is_32bit \oper_i__insn \oper_i__fn_unit \oper_i__insn_type }
+ assign { \oper_l__trapaddr$next \oper_l__traptype$next \oper_l__is_32bit$next \oper_l__cia$next \oper_l__msr$next \oper_l__insn$next \oper_l__fn_unit$next \oper_l__insn_type$next } { \oper_i__trapaddr \oper_i__traptype \oper_i__is_32bit \oper_i__cia \oper_i__msr \oper_i__insn \oper_i__fn_unit \oper_i__insn_type }
end
sync init
update \oper_l__insn_type 7'0000000
update \oper_l__fn_unit 11'00000000000
update \oper_l__insn 32'00000000000000000000000000000000
+ update \oper_l__msr 64'0000000000000000000000000000000000000000000000000000000000000000
+ update \oper_l__cia 64'0000000000000000000000000000000000000000000000000000000000000000
update \oper_l__is_32bit 1'0
update \oper_l__traptype 5'00000
update \oper_l__trapaddr 13'0000000000000
update \oper_l__insn_type \oper_l__insn_type$next
update \oper_l__fn_unit \oper_l__fn_unit$next
update \oper_l__insn \oper_l__insn$next
+ update \oper_l__msr \oper_l__msr$next
+ update \oper_l__cia \oper_l__cia$next
update \oper_l__is_32bit \oper_l__is_32bit$next
update \oper_l__traptype \oper_l__traptype$next
update \oper_l__trapaddr \oper_l__trapaddr$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
wire width 1 \data_r0_l__o_ok$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
- wire width 65 $71
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:730"
- wire width 1 $72
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:730"
- cell $reduce_bool $73
+ wire width 65 $73
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744"
+ wire width 1 $74
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744"
+ cell $reduce_bool $75
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \Y_WIDTH 1
connect \A \alu_pulsem
- connect \Y $72
+ connect \Y $74
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
- cell $mux $74
+ cell $mux $76
parameter \WIDTH 65
connect \A { \data_r0_l__o_ok \data_r0_l__o }
- connect \B { \o_ok \o }
- connect \S $72
- connect \Y $71
+ connect \B { \o_ok \alu_trap0_o }
+ connect \S $74
+ connect \Y $73
end
- process $group_37
+ process $group_41
assign \data_r0__o 64'0000000000000000000000000000000000000000000000000000000000000000
assign \data_r0__o_ok 1'0
- assign { \data_r0__o_ok \data_r0__o } $71
+ assign { \data_r0__o_ok \data_r0__o } $73
sync init
end
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
- wire width 1 $75
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
- cell $reduce_bool $76
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
+ wire width 1 $77
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
+ cell $reduce_bool $78
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \Y_WIDTH 1
connect \A \alu_pulsem
- connect \Y $75
+ connect \Y $77
end
- process $group_39
+ process $group_43
assign \data_r0_l__o$next \data_r0_l__o
assign \data_r0_l__o_ok$next \data_r0_l__o_ok
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
- switch { $75 }
+ switch { $77 }
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
case 1'1
- assign { \data_r0_l__o_ok$next \data_r0_l__o$next } { \o_ok \o }
+ assign { \data_r0_l__o_ok$next \data_r0_l__o$next } { \o_ok \alu_trap0_o }
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
wire width 1 \data_r1_l__fast1_ok$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
- wire width 65 $77
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:730"
- wire width 1 $78
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:730"
- cell $reduce_bool $79
+ wire width 65 $79
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744"
+ wire width 1 $80
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744"
+ cell $reduce_bool $81
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \Y_WIDTH 1
connect \A \alu_pulsem
- connect \Y $78
+ connect \Y $80
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
- cell $mux $80
+ cell $mux $82
parameter \WIDTH 65
connect \A { \data_r1_l__fast1_ok \data_r1_l__fast1 }
- connect \B { \fast1_ok \fast1 }
- connect \S $78
- connect \Y $77
+ connect \B { \fast1_ok \alu_trap0_fast1 }
+ connect \S $80
+ connect \Y $79
end
- process $group_41
+ process $group_45
assign \data_r1__fast1 64'0000000000000000000000000000000000000000000000000000000000000000
assign \data_r1__fast1_ok 1'0
- assign { \data_r1__fast1_ok \data_r1__fast1 } $77
+ assign { \data_r1__fast1_ok \data_r1__fast1 } $79
sync init
end
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
- wire width 1 $81
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
- cell $reduce_bool $82
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
+ wire width 1 $83
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
+ cell $reduce_bool $84
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \Y_WIDTH 1
connect \A \alu_pulsem
- connect \Y $81
+ connect \Y $83
end
- process $group_43
+ process $group_47
assign \data_r1_l__fast1$next \data_r1_l__fast1
assign \data_r1_l__fast1_ok$next \data_r1_l__fast1_ok
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
- switch { $81 }
+ switch { $83 }
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
case 1'1
- assign { \data_r1_l__fast1_ok$next \data_r1_l__fast1$next } { \fast1_ok \fast1 }
+ assign { \data_r1_l__fast1_ok$next \data_r1_l__fast1$next } { \fast1_ok \alu_trap0_fast1 }
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
wire width 1 \data_r2_l__fast2_ok$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
- wire width 65 $83
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:730"
- wire width 1 $84
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:730"
- cell $reduce_bool $85
+ wire width 65 $85
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744"
+ wire width 1 $86
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744"
+ cell $reduce_bool $87
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \Y_WIDTH 1
connect \A \alu_pulsem
- connect \Y $84
+ connect \Y $86
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
- cell $mux $86
+ cell $mux $88
parameter \WIDTH 65
connect \A { \data_r2_l__fast2_ok \data_r2_l__fast2 }
- connect \B { \fast2_ok \fast2 }
- connect \S $84
- connect \Y $83
+ connect \B { \fast2_ok \alu_trap0_fast2 }
+ connect \S $86
+ connect \Y $85
end
- process $group_45
+ process $group_49
assign \data_r2__fast2 64'0000000000000000000000000000000000000000000000000000000000000000
assign \data_r2__fast2_ok 1'0
- assign { \data_r2__fast2_ok \data_r2__fast2 } $83
+ assign { \data_r2__fast2_ok \data_r2__fast2 } $85
sync init
end
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
- wire width 1 $87
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
- cell $reduce_bool $88
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
+ wire width 1 $89
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
+ cell $reduce_bool $90
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \Y_WIDTH 1
connect \A \alu_pulsem
- connect \Y $87
+ connect \Y $89
end
- process $group_47
+ process $group_51
assign \data_r2_l__fast2$next \data_r2_l__fast2
assign \data_r2_l__fast2_ok$next \data_r2_l__fast2_ok
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
- switch { $87 }
+ switch { $89 }
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
case 1'1
- assign { \data_r2_l__fast2_ok$next \data_r2_l__fast2$next } { \fast2_ok \fast2 }
+ assign { \data_r2_l__fast2_ok$next \data_r2_l__fast2$next } { \fast2_ok \alu_trap0_fast2 }
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
wire width 1 \data_r3_l__nia_ok$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
- wire width 65 $89
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:730"
- wire width 1 $90
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:730"
- cell $reduce_bool $91
+ wire width 65 $91
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744"
+ wire width 1 $92
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744"
+ cell $reduce_bool $93
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \Y_WIDTH 1
connect \A \alu_pulsem
- connect \Y $90
+ connect \Y $92
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
- cell $mux $92
+ cell $mux $94
parameter \WIDTH 65
connect \A { \data_r3_l__nia_ok \data_r3_l__nia }
- connect \B { \nia_ok \nia }
- connect \S $90
- connect \Y $89
+ connect \B { \nia_ok \alu_trap0_nia }
+ connect \S $92
+ connect \Y $91
end
- process $group_49
+ process $group_53
assign \data_r3__nia 64'0000000000000000000000000000000000000000000000000000000000000000
assign \data_r3__nia_ok 1'0
- assign { \data_r3__nia_ok \data_r3__nia } $89
+ assign { \data_r3__nia_ok \data_r3__nia } $91
sync init
end
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
- wire width 1 $93
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
- cell $reduce_bool $94
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
+ wire width 1 $95
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
+ cell $reduce_bool $96
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \Y_WIDTH 1
connect \A \alu_pulsem
- connect \Y $93
+ connect \Y $95
end
- process $group_51
+ process $group_55
assign \data_r3_l__nia$next \data_r3_l__nia
assign \data_r3_l__nia_ok$next \data_r3_l__nia_ok
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
- switch { $93 }
+ switch { $95 }
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
case 1'1
- assign { \data_r3_l__nia_ok$next \data_r3_l__nia$next } { \nia_ok \nia }
+ assign { \data_r3_l__nia_ok$next \data_r3_l__nia$next } { \nia_ok \alu_trap0_nia }
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
wire width 1 \data_r4_l__msr_ok$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
- wire width 65 $95
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:730"
- wire width 1 $96
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:730"
- cell $reduce_bool $97
+ wire width 65 $97
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744"
+ wire width 1 $98
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744"
+ cell $reduce_bool $99
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \Y_WIDTH 1
connect \A \alu_pulsem
- connect \Y $96
+ connect \Y $98
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
- cell $mux $98
+ cell $mux $100
parameter \WIDTH 65
connect \A { \data_r4_l__msr_ok \data_r4_l__msr }
- connect \B { \msr_ok \msr }
- connect \S $96
- connect \Y $95
+ connect \B { \msr_ok \alu_trap0_msr }
+ connect \S $98
+ connect \Y $97
end
- process $group_53
+ process $group_57
assign \data_r4__msr 64'0000000000000000000000000000000000000000000000000000000000000000
assign \data_r4__msr_ok 1'0
- assign { \data_r4__msr_ok \data_r4__msr } $95
+ assign { \data_r4__msr_ok \data_r4__msr } $97
sync init
end
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
- wire width 1 $99
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
- cell $reduce_bool $100
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
+ wire width 1 $101
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
+ cell $reduce_bool $102
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \Y_WIDTH 1
connect \A \alu_pulsem
- connect \Y $99
+ connect \Y $101
end
- process $group_55
+ process $group_59
assign \data_r4_l__msr$next \data_r4_l__msr
assign \data_r4_l__msr_ok$next \data_r4_l__msr_ok
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
- switch { $99 }
+ switch { $101 }
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
case 1'1
- assign { \data_r4_l__msr_ok$next \data_r4_l__msr$next } { \msr_ok \msr }
+ assign { \data_r4_l__msr_ok$next \data_r4_l__msr$next } { \msr_ok \alu_trap0_msr }
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
update \data_r4_l__msr \data_r4_l__msr$next
update \data_r4_l__msr_ok \data_r4_l__msr_ok$next
end
- process $group_57
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+ wire width 1 $103
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+ cell $and $104
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \data_r0__o_ok
+ connect \B \busy_o
+ connect \Y $103
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+ wire width 1 $105
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+ cell $and $106
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \data_r1__fast1_ok
+ connect \B \busy_o
+ connect \Y $105
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+ wire width 1 $107
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+ cell $and $108
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \data_r2__fast2_ok
+ connect \B \busy_o
+ connect \Y $107
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+ wire width 1 $109
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+ cell $and $110
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \data_r3__nia_ok
+ connect \B \busy_o
+ connect \Y $109
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+ wire width 1 $111
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+ cell $and $112
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \data_r4__msr_ok
+ connect \B \busy_o
+ connect \Y $111
+ end
+ process $group_61
assign \wrmask 5'00000
- assign \wrmask { \data_r4__msr_ok \data_r3__nia_ok \data_r2__fast2_ok \data_r1__fast1_ok \data_r0__o_ok }
+ assign \wrmask { $111 $109 $107 $105 $103 }
sync init
end
- process $group_58
+ process $group_62
assign \alu_trap0_op__insn_type 7'0000000
assign \alu_trap0_op__fn_unit 11'00000000000
assign \alu_trap0_op__insn 32'00000000000000000000000000000000
+ assign \alu_trap0_op__msr 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \alu_trap0_op__cia 64'0000000000000000000000000000000000000000000000000000000000000000
assign \alu_trap0_op__is_32bit 1'0
assign \alu_trap0_op__traptype 5'00000
assign \alu_trap0_op__trapaddr 13'0000000000000
- assign { \alu_trap0_op__trapaddr \alu_trap0_op__traptype \alu_trap0_op__is_32bit \alu_trap0_op__insn \alu_trap0_op__fn_unit \alu_trap0_op__insn_type } { \oper_r__trapaddr \oper_r__traptype \oper_r__is_32bit \oper_r__insn \oper_r__fn_unit \oper_r__insn_type }
+ assign { \alu_trap0_op__trapaddr \alu_trap0_op__traptype \alu_trap0_op__is_32bit \alu_trap0_op__cia \alu_trap0_op__msr \alu_trap0_op__insn \alu_trap0_op__fn_unit \alu_trap0_op__insn_type } { \oper_r__trapaddr \oper_r__traptype \oper_r__is_32bit \oper_r__cia \oper_r__msr \oper_r__insn \oper_r__fn_unit \oper_r__insn_type }
sync init
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
wire width 64 \src_r0$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
- wire width 64 $101
+ wire width 64 $113
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
- cell $mux $102
+ cell $mux $114
parameter \WIDTH 64
connect \A \src_r0
connect \B \src1_i
connect \S \src_l_q_src [0]
- connect \Y $101
+ connect \Y $113
end
- process $group_64
+ process $group_70
assign \alu_trap0_ra 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \alu_trap0_ra $101
+ assign \alu_trap0_ra $113
sync init
end
- process $group_65
+ process $group_71
assign \src_r0$next \src_r0
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
switch { \src_l_q_src [0] }
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
wire width 64 \src_r1$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
- wire width 64 $103
+ wire width 64 $115
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
- cell $mux $104
+ cell $mux $116
parameter \WIDTH 64
connect \A \src_r1
connect \B \src2_i
connect \S \src_l_q_src [1]
- connect \Y $103
+ connect \Y $115
end
- process $group_66
+ process $group_72
assign \alu_trap0_rb 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \alu_trap0_rb $103
+ assign \alu_trap0_rb $115
sync init
end
- process $group_67
+ process $group_73
assign \src_r1$next \src_r1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
switch { \src_l_q_src [1] }
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
wire width 64 \src_r2$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
- wire width 64 $105
+ wire width 64 $117
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
- cell $mux $106
+ cell $mux $118
parameter \WIDTH 64
connect \A \src_r2
connect \B \src3_i
connect \S \src_l_q_src [2]
- connect \Y $105
+ connect \Y $117
end
- process $group_68
- assign \alu_trap0_fast1 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \alu_trap0_fast1 $105
+ process $group_74
+ assign \alu_trap0_fast1$1 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \alu_trap0_fast1$1 $117
sync init
end
- process $group_69
+ process $group_75
assign \src_r2$next \src_r2
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
switch { \src_l_q_src [2] }
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
wire width 64 \src_r3$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
- wire width 64 $107
+ wire width 64 $119
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
- cell $mux $108
+ cell $mux $120
parameter \WIDTH 64
connect \A \src_r3
connect \B \src4_i
connect \S \src_l_q_src [3]
- connect \Y $107
+ connect \Y $119
end
- process $group_70
- assign \alu_trap0_fast2 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \alu_trap0_fast2 $107
+ process $group_76
+ assign \alu_trap0_fast2$2 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \alu_trap0_fast2$2 $119
sync init
end
- process $group_71
+ process $group_77
assign \src_r3$next \src_r3
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
switch { \src_l_q_src [3] }
sync posedge \clk
update \src_r3 \src_r3$next
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
- wire width 64 \src_r4
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
- wire width 64 \src_r4$next
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
- wire width 64 $109
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
- cell $mux $110
- parameter \WIDTH 64
- connect \A \src_r4
- connect \B \src5_i
- connect \S \src_l_q_src [4]
- connect \Y $109
- end
- process $group_72
- assign \alu_trap0_cia 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \alu_trap0_cia $109
- sync init
- end
- process $group_73
- assign \src_r4$next \src_r4
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
- switch { \src_l_q_src [4] }
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
- case 1'1
- assign \src_r4$next \src5_i
- end
- sync init
- update \src_r4 64'0000000000000000000000000000000000000000000000000000000000000000
- sync posedge \clk
- update \src_r4 \src_r4$next
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
- wire width 64 \src_r5
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
- wire width 64 \src_r5$next
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
- wire width 64 $111
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
- cell $mux $112
- parameter \WIDTH 64
- connect \A \src_r5
- connect \B \src6_i
- connect \S \src_l_q_src [5]
- connect \Y $111
- end
- process $group_74
- assign \alu_trap0_msr 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \alu_trap0_msr $111
- sync init
- end
- process $group_75
- assign \src_r5$next \src_r5
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
- switch { \src_l_q_src [5] }
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
- case 1'1
- assign \src_r5$next \src6_i
- end
- sync init
- update \src_r5 64'0000000000000000000000000000000000000000000000000000000000000000
- sync posedge \clk
- update \src_r5 \src_r5$next
- end
- process $group_76
+ process $group_78
assign \alu_trap0_p_valid_i 1'0
assign \alu_trap0_p_valid_i \alui_l_q_alui
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:321"
- wire width 1 $113
+ wire width 1 $121
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:321"
- cell $and $114
+ cell $and $122
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \alu_trap0_p_ready_o
connect \B \alui_l_q_alui
- connect \Y $113
+ connect \Y $121
end
- process $group_77
+ process $group_79
assign \alui_l_r_alui$next \alui_l_r_alui
- assign \alui_l_r_alui$next $113
+ assign \alui_l_r_alui$next $121
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
sync posedge \clk
update \alui_l_r_alui \alui_l_r_alui$next
end
- process $group_78
+ process $group_80
assign \alui_l_s_alui 1'0
assign \alui_l_s_alui \all_rd_pulse
sync init
end
- process $group_79
+ process $group_81
assign \alu_trap0_n_ready_i 1'0
assign \alu_trap0_n_ready_i \alu_l_q_alu
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:328"
- wire width 1 $115
+ wire width 1 $123
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:328"
- cell $and $116
+ cell $and $124
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \alu_trap0_n_valid_o
connect \B \alu_l_q_alu
- connect \Y $115
+ connect \Y $123
end
- process $group_80
+ process $group_82
assign \alu_l_r_alu$next \alu_l_r_alu
- assign \alu_l_r_alu$next $115
+ assign \alu_l_r_alu$next $123
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
sync posedge \clk
update \alu_l_r_alu \alu_l_r_alu$next
end
- process $group_81
+ process $group_83
assign \alu_l_s_alu 1'0
assign \alu_l_s_alu \all_rd_pulse
sync init
end
- process $group_82
+ process $group_84
assign \busy_o 1'0
assign \busy_o \opc_l_q_opc
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341"
- wire width 6 $117
+ wire width 4 $125
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341"
- cell $and $118
+ cell $and $126
parameter \A_SIGNED 0
- parameter \A_WIDTH 6
+ parameter \A_WIDTH 4
parameter \B_SIGNED 0
- parameter \B_WIDTH 6
- parameter \Y_WIDTH 6
+ parameter \B_WIDTH 4
+ parameter \Y_WIDTH 4
connect \A \src_l_q_src
- connect \B { \busy_o \busy_o \busy_o \busy_o \busy_o \busy_o }
- connect \Y $117
+ connect \B { \busy_o \busy_o \busy_o \busy_o }
+ connect \Y $125
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341"
- wire width 6 $119
+ wire width 4 $127
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341"
- cell $and $120
+ cell $and $128
parameter \A_SIGNED 0
- parameter \A_WIDTH 6
+ parameter \A_WIDTH 4
parameter \B_SIGNED 0
- parameter \B_WIDTH 6
- parameter \Y_WIDTH 6
- connect \A $117
- connect \B { 1'1 1'1 1'1 1'1 1'1 1'1 }
- connect \Y $119
+ parameter \B_WIDTH 4
+ parameter \Y_WIDTH 4
+ connect \A $125
+ connect \B { 1'1 1'1 1'1 1'1 }
+ connect \Y $127
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341"
- wire width 6 $121
+ wire width 4 $129
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341"
- cell $not $122
+ cell $not $130
parameter \A_SIGNED 0
- parameter \A_WIDTH 6
- parameter \Y_WIDTH 6
+ parameter \A_WIDTH 4
+ parameter \Y_WIDTH 4
connect \A \rdmaskn
- connect \Y $121
+ connect \Y $129
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341"
- wire width 6 $123
+ wire width 4 $131
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341"
- cell $and $124
+ cell $and $132
parameter \A_SIGNED 0
- parameter \A_WIDTH 6
+ parameter \A_WIDTH 4
parameter \B_SIGNED 0
- parameter \B_WIDTH 6
- parameter \Y_WIDTH 6
- connect \A $119
- connect \B $121
- connect \Y $123
+ parameter \B_WIDTH 4
+ parameter \Y_WIDTH 4
+ connect \A $127
+ connect \B $129
+ connect \Y $131
end
- process $group_83
- assign \rd__rel 6'000000
- assign \rd__rel $123
+ process $group_85
+ assign \rd__rel 4'0000
+ assign \rd__rel $131
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
- wire width 1 $125
+ wire width 1 $133
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
- cell $and $126
+ cell $and $134
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \busy_o
connect \B \shadown_i
- connect \Y $125
+ connect \Y $133
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
- wire width 1 $127
+ wire width 1 $135
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
- cell $and $128
+ cell $and $136
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \busy_o
connect \B \shadown_i
- connect \Y $127
+ connect \Y $135
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
- wire width 1 $129
+ wire width 1 $137
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
- cell $and $130
+ cell $and $138
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \busy_o
connect \B \shadown_i
- connect \Y $129
+ connect \Y $137
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
- wire width 1 $131
+ wire width 1 $139
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
- cell $and $132
+ cell $and $140
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \busy_o
connect \B \shadown_i
- connect \Y $131
+ connect \Y $139
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
- wire width 1 $133
+ wire width 1 $141
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
- cell $and $134
+ cell $and $142
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \busy_o
connect \B \shadown_i
- connect \Y $133
+ connect \Y $141
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:345"
- wire width 5 $135
+ wire width 5 $143
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:345"
- cell $and $136
+ cell $and $144
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \B_WIDTH 5
parameter \Y_WIDTH 5
connect \A \req_l_q_req
- connect \B { $125 $127 $129 $131 $133 }
- connect \Y $135
+ connect \B { $133 $135 $137 $139 $141 }
+ connect \Y $143
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:345"
- wire width 5 $137
+ wire width 5 $145
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:345"
- cell $and $138
+ cell $and $146
parameter \A_SIGNED 0
parameter \A_WIDTH 5
parameter \B_SIGNED 0
parameter \B_WIDTH 5
parameter \Y_WIDTH 5
- connect \A $135
+ connect \A $143
connect \B \wrmask
- connect \Y $137
+ connect \Y $145
end
- process $group_84
+ process $group_86
assign \wr__rel 5'00000
- assign \wr__rel $137
+ assign \wr__rel $145
sync init
end
- process $group_85
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+ wire width 1 $147
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+ cell $and $148
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \wr__go [0]
+ connect \B \busy_o
+ connect \Y $147
+ end
+ process $group_87
assign \dest1_o 64'0000000000000000000000000000000000000000000000000000000000000000
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
- switch { \wr__go [0] }
+ switch { $147 }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
case 1'1
assign \dest1_o { \data_r0__o_ok \data_r0__o } [63:0]
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
- wire width 64 \dest2_o
- process $group_86
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+ wire width 1 $149
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+ cell $and $150
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \wr__go [1]
+ connect \B \busy_o
+ connect \Y $149
+ end
+ process $group_88
assign \dest2_o 64'0000000000000000000000000000000000000000000000000000000000000000
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
- switch { \wr__go [1] }
+ switch { $149 }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
case 1'1
assign \dest2_o { \data_r1__fast1_ok \data_r1__fast1 } [63:0]
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
- wire width 64 \dest3_o
- process $group_87
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+ wire width 1 $151
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+ cell $and $152
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \wr__go [2]
+ connect \B \busy_o
+ connect \Y $151
+ end
+ process $group_89
assign \dest3_o 64'0000000000000000000000000000000000000000000000000000000000000000
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
- switch { \wr__go [2] }
+ switch { $151 }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
case 1'1
assign \dest3_o { \data_r2__fast2_ok \data_r2__fast2 } [63:0]
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
- wire width 64 \dest4_o
- process $group_88
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+ wire width 1 $153
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+ cell $and $154
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \wr__go [3]
+ connect \B \busy_o
+ connect \Y $153
+ end
+ process $group_90
assign \dest4_o 64'0000000000000000000000000000000000000000000000000000000000000000
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
- switch { \wr__go [3] }
+ switch { $153 }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
case 1'1
assign \dest4_o { \data_r3__nia_ok \data_r3__nia } [63:0]
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
- wire width 64 \dest5_o
- process $group_89
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+ wire width 1 $155
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+ cell $and $156
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \wr__go [4]
+ connect \B \busy_o
+ connect \Y $155
+ end
+ process $group_91
assign \dest5_o 64'0000000000000000000000000000000000000000000000000000000000000000
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
- switch { \wr__go [4] }
+ switch { $155 }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
case 1'1
assign \dest5_o { \data_r4__msr_ok \data_r4__msr } [63:0]
attribute \generator "nMigen"
attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_logical0.p"
module \p$43
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153"
wire width 1 input 0 \p_valid_i
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154"
wire width 1 input 1 \p_ready_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:156"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158"
wire width 1 \trigger
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:203"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205"
wire width 1 $1
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:203"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205"
cell $and $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
attribute \generator "nMigen"
attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_logical0.n"
module \n$44
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
wire width 1 input 0 \n_valid_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
wire width 1 input 1 \n_ready_i
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:249"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251"
wire width 1 \trigger
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:295"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:297"
wire width 1 $1
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:295"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:297"
cell $and $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
attribute \generator "nMigen"
attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_logical0.pipe.p"
module \p$46
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153"
wire width 1 input 0 \p_valid_i
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154"
wire width 1 input 1 \p_ready_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:156"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158"
wire width 1 \trigger
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:203"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205"
wire width 1 $1
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:203"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205"
cell $and $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
attribute \generator "nMigen"
attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_logical0.pipe.n"
module \n$47
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
wire width 1 input 0 \n_valid_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
wire width 1 input 1 \n_ready_i
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:249"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251"
wire width 1 \trigger
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:295"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:297"
wire width 1 $1
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:295"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:297"
cell $and $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
attribute \generator "nMigen"
attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_logical0.pipe.input"
module \input$48
- attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
wire width 2 input 0 \muxid
- attribute \enum_base_type "InternalOp"
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 7 input 1 \op__insn_type
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00100000000 "MUL"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 11 input 2 \op__fn_unit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 64 input 3 \op__imm_data__imm
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 input 4 \op__imm_data__imm_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 input 5 \op__lk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 input 6 \op__rc__rc
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 input 7 \op__rc__rc_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 input 8 \op__oe__oe
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 input 9 \op__oe__oe_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 input 10 \op__invert_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 input 11 \op__zero_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 5 \op__rc__rc
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 6 \op__rc__rc_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 7 \op__oe__oe
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 8 \op__oe__oe_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 9 \op__invert_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 10 \op__zero_a
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 2 input 12 \op__input_carry
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 input 13 \op__invert_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 3 input 14 \op__write_cr__data
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 input 15 \op__write_cr__ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 input 16 \op__output_carry
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 input 17 \op__is_32bit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 input 18 \op__is_signed
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 4 input 19 \op__data_len
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 32 input 20 \op__insn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
- wire width 64 input 21 \ra
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
- wire width 64 input 22 \rb
- attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
- wire width 2 output 23 \muxid$1
- attribute \enum_base_type "InternalOp"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 2 input 11 \op__input_carry
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 12 \op__invert_out
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 13 \op__write_cr0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 14 \op__output_carry
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 15 \op__is_32bit
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 16 \op__is_signed
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 4 input 17 \op__data_len
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 input 18 \op__insn
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 64 input 19 \ra
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 64 input 20 \rb
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+ wire width 2 output 21 \muxid$1
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 7 output 24 \op__insn_type$2
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 7 output 22 \op__insn_type$2
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00000000010 "ALU"
attribute \enum_value_00100000000 "MUL"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 11 output 25 \op__fn_unit$3
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 64 output 26 \op__imm_data__imm$4
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 output 27 \op__imm_data__imm_ok$5
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 output 28 \op__lk$6
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 output 29 \op__rc__rc$7
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 output 30 \op__rc__rc_ok$8
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 output 31 \op__oe__oe$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 output 32 \op__oe__oe_ok$10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 output 33 \op__invert_a$11
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 output 34 \op__zero_a$12
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 11 output 23 \op__fn_unit$3
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 output 24 \op__imm_data__imm$4
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 25 \op__imm_data__imm_ok$5
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 26 \op__rc__rc$6
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 27 \op__rc__rc_ok$7
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 28 \op__oe__oe$8
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 29 \op__oe__oe_ok$9
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 30 \op__invert_a$10
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 31 \op__zero_a$11
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 2 output 35 \op__input_carry$13
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 output 36 \op__invert_out$14
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 3 output 37 \op__write_cr__data$15
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 output 38 \op__write_cr__ok$16
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 output 39 \op__output_carry$17
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 output 40 \op__is_32bit$18
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 output 41 \op__is_signed$19
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 4 output 42 \op__data_len$20
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 32 output 43 \op__insn$21
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
- wire width 64 output 44 \ra$22
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
- wire width 64 output 45 \rb$23
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 2 output 32 \op__input_carry$12
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 33 \op__invert_out$13
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 34 \op__write_cr0$14
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 35 \op__output_carry$15
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 36 \op__is_32bit$16
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 37 \op__is_signed$17
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 4 output 38 \op__data_len$18
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 output 39 \op__insn$19
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 64 output 40 \ra$20
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 64 output 41 \rb$21
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20"
wire width 64 \a
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:24"
- wire width 64 $24
+ wire width 64 $22
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:24"
- cell $not $25
+ cell $not $23
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
connect \A \ra
- connect \Y $24
+ connect \Y $22
end
process $group_0
assign \a 64'0000000000000000000000000000000000000000000000000000000000000000
switch { \op__invert_a }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:23"
case 1'1
- assign \a $24
+ assign \a $22
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:25"
case
assign \a \ra
sync init
end
process $group_1
- assign \ra$22 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \ra$22 \a
+ assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \ra$20 \a
sync init
end
process $group_2
assign \op__fn_unit$3 11'00000000000
assign \op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000
assign \op__imm_data__imm_ok$5 1'0
- assign \op__lk$6 1'0
- assign \op__rc__rc$7 1'0
- assign \op__rc__rc_ok$8 1'0
- assign \op__oe__oe$9 1'0
- assign \op__oe__oe_ok$10 1'0
- assign \op__invert_a$11 1'0
- assign \op__zero_a$12 1'0
- assign \op__input_carry$13 2'00
- assign \op__invert_out$14 1'0
- assign \op__write_cr__data$15 3'000
- assign \op__write_cr__ok$16 1'0
- assign \op__output_carry$17 1'0
- assign \op__is_32bit$18 1'0
- assign \op__is_signed$19 1'0
- assign \op__data_len$20 4'0000
- assign \op__insn$21 32'00000000000000000000000000000000
- assign { \op__insn$21 \op__data_len$20 \op__is_signed$19 \op__is_32bit$18 \op__output_carry$17 { \op__write_cr__ok$16 \op__write_cr__data$15 } \op__invert_out$14 \op__input_carry$13 \op__zero_a$12 \op__invert_a$11 { \op__oe__oe_ok$10 \op__oe__oe$9 } { \op__rc__rc_ok$8 \op__rc__rc$7 } \op__lk$6 { \op__imm_data__imm_ok$5 \op__imm_data__imm$4 } \op__fn_unit$3 \op__insn_type$2 } { \op__insn \op__data_len \op__is_signed \op__is_32bit \op__output_carry { \op__write_cr__ok \op__write_cr__data } \op__invert_out \op__input_carry \op__zero_a \op__invert_a { \op__oe__oe_ok \op__oe__oe } { \op__rc__rc_ok \op__rc__rc } \op__lk { \op__imm_data__imm_ok \op__imm_data__imm } \op__fn_unit \op__insn_type }
+ assign \op__rc__rc$6 1'0
+ assign \op__rc__rc_ok$7 1'0
+ assign \op__oe__oe$8 1'0
+ assign \op__oe__oe_ok$9 1'0
+ assign \op__invert_a$10 1'0
+ assign \op__zero_a$11 1'0
+ assign \op__input_carry$12 2'00
+ assign \op__invert_out$13 1'0
+ assign \op__write_cr0$14 1'0
+ assign \op__output_carry$15 1'0
+ assign \op__is_32bit$16 1'0
+ assign \op__is_signed$17 1'0
+ assign \op__data_len$18 4'0000
+ assign \op__insn$19 32'00000000000000000000000000000000
+ assign { \op__insn$19 \op__data_len$18 \op__is_signed$17 \op__is_32bit$16 \op__output_carry$15 \op__write_cr0$14 \op__invert_out$13 \op__input_carry$12 \op__zero_a$11 \op__invert_a$10 { \op__oe__oe_ok$9 \op__oe__oe$8 } { \op__rc__rc_ok$7 \op__rc__rc$6 } { \op__imm_data__imm_ok$5 \op__imm_data__imm$4 } \op__fn_unit$3 \op__insn_type$2 } { \op__insn \op__data_len \op__is_signed \op__is_32bit \op__output_carry \op__write_cr0 \op__invert_out \op__input_carry \op__zero_a \op__invert_a { \op__oe__oe_ok \op__oe__oe } { \op__rc__rc_ok \op__rc__rc } { \op__imm_data__imm_ok \op__imm_data__imm } \op__fn_unit \op__insn_type }
sync init
end
- process $group_23
- assign \rb$23 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \rb$23 \rb
+ process $group_21
+ assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \rb$21 \rb
sync init
end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_logical0.pipe.main"
module \main$49
- attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
wire width 2 input 0 \muxid
- attribute \enum_base_type "InternalOp"
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 7 input 1 \op__insn_type
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00100000000 "MUL"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 11 input 2 \op__fn_unit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 64 input 3 \op__imm_data__imm
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 input 4 \op__imm_data__imm_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 input 5 \op__lk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 input 6 \op__rc__rc
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 input 7 \op__rc__rc_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 input 8 \op__oe__oe
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 input 9 \op__oe__oe_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 input 10 \op__invert_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 input 11 \op__zero_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 5 \op__rc__rc
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 6 \op__rc__rc_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 7 \op__oe__oe
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 8 \op__oe__oe_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 9 \op__invert_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 10 \op__zero_a
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 2 input 12 \op__input_carry
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 input 13 \op__invert_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 3 input 14 \op__write_cr__data
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 input 15 \op__write_cr__ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 input 16 \op__output_carry
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 input 17 \op__is_32bit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 input 18 \op__is_signed
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 4 input 19 \op__data_len
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 32 input 20 \op__insn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
- wire width 64 input 21 \ra
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
- wire width 64 input 22 \rb
- attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
- wire width 2 output 23 \muxid$1
- attribute \enum_base_type "InternalOp"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 2 input 11 \op__input_carry
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 12 \op__invert_out
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 13 \op__write_cr0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 14 \op__output_carry
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 15 \op__is_32bit
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 16 \op__is_signed
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 4 input 17 \op__data_len
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 input 18 \op__insn
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 64 input 19 \ra
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 64 input 20 \rb
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+ wire width 2 output 21 \muxid$1
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 7 output 24 \op__insn_type$2
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 7 output 22 \op__insn_type$2
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00000000010 "ALU"
attribute \enum_value_00100000000 "MUL"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 11 output 25 \op__fn_unit$3
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 64 output 26 \op__imm_data__imm$4
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 output 27 \op__imm_data__imm_ok$5
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 output 28 \op__lk$6
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 output 29 \op__rc__rc$7
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 output 30 \op__rc__rc_ok$8
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 output 31 \op__oe__oe$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 output 32 \op__oe__oe_ok$10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 output 33 \op__invert_a$11
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 output 34 \op__zero_a$12
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 11 output 23 \op__fn_unit$3
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 output 24 \op__imm_data__imm$4
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 25 \op__imm_data__imm_ok$5
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 26 \op__rc__rc$6
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 27 \op__rc__rc_ok$7
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 28 \op__oe__oe$8
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 29 \op__oe__oe_ok$9
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 30 \op__invert_a$10
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 31 \op__zero_a$11
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 2 output 35 \op__input_carry$13
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 output 36 \op__invert_out$14
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 3 output 37 \op__write_cr__data$15
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 output 38 \op__write_cr__ok$16
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 output 39 \op__output_carry$17
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 output 40 \op__is_32bit$18
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 output 41 \op__is_signed$19
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 4 output 42 \op__data_len$20
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 32 output 43 \op__insn$21
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 2 output 32 \op__input_carry$12
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 33 \op__invert_out$13
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 34 \op__write_cr0$14
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 35 \op__output_carry$15
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 36 \op__is_32bit$16
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 37 \op__is_signed$17
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 4 output 38 \op__data_len$18
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 output 39 \op__insn$19
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 output 44 \o
+ wire width 64 output 40 \o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 45 \o_ok
+ wire width 1 output 41 \o_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:54"
wire width 64 \bpermd_rs
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:56"
connect \lz \clz_lz
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:51"
- wire width 64 $22
+ wire width 64 $20
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:51"
- cell $and $23
+ cell $and $21
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 64
connect \A \ra
connect \B \rb
- connect \Y $22
+ connect \Y $20
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:53"
- wire width 64 $24
+ wire width 64 $22
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:53"
- cell $or $25
+ cell $or $23
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 64
connect \A \ra
connect \B \rb
- connect \Y $24
+ connect \Y $22
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:55"
- wire width 64 $26
+ wire width 64 $24
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:55"
- cell $xor $27
+ cell $xor $25
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \Y_WIDTH 64
connect \A \ra
connect \B \rb
+ connect \Y $24
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
+ wire width 1 $26
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
+ cell $eq $27
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 8
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 8
+ parameter \Y_WIDTH 1
+ connect \A \ra [7:0]
+ connect \B \rb [7:0]
connect \Y $26
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
parameter \B_SIGNED 0
parameter \B_WIDTH 8
parameter \Y_WIDTH 1
- connect \A \ra [7:0]
- connect \B \rb [7:0]
+ connect \A \ra [15:8]
+ connect \B \rb [15:8]
connect \Y $42
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
parameter \B_SIGNED 0
parameter \B_WIDTH 8
parameter \Y_WIDTH 1
- connect \A \ra [15:8]
- connect \B \rb [15:8]
+ connect \A \ra [23:16]
+ connect \B \rb [23:16]
connect \Y $58
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
parameter \B_SIGNED 0
parameter \B_WIDTH 8
parameter \Y_WIDTH 1
- connect \A \ra [23:16]
- connect \B \rb [23:16]
+ connect \A \ra [31:24]
+ connect \B \rb [31:24]
connect \Y $74
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
parameter \B_SIGNED 0
parameter \B_WIDTH 8
parameter \Y_WIDTH 1
- connect \A \ra [31:24]
- connect \B \rb [31:24]
+ connect \A \ra [39:32]
+ connect \B \rb [39:32]
connect \Y $90
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
parameter \B_SIGNED 0
parameter \B_WIDTH 8
parameter \Y_WIDTH 1
- connect \A \ra [39:32]
- connect \B \rb [39:32]
+ connect \A \ra [47:40]
+ connect \B \rb [47:40]
connect \Y $106
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
parameter \B_SIGNED 0
parameter \B_WIDTH 8
parameter \Y_WIDTH 1
- connect \A \ra [47:40]
- connect \B \rb [47:40]
+ connect \A \ra [55:48]
+ connect \B \rb [55:48]
connect \Y $122
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
parameter \B_SIGNED 0
parameter \B_WIDTH 8
parameter \Y_WIDTH 1
- connect \A \ra [55:48]
- connect \B \rb [55:48]
+ connect \A \ra [63:56]
+ connect \B \rb [63:56]
connect \Y $138
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
connect \B \rb [63:56]
connect \Y $152
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
- wire width 1 $154
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:62"
- cell $eq $155
- parameter \A_SIGNED 0
- parameter \A_WIDTH 8
- parameter \B_SIGNED 0
- parameter \B_WIDTH 8
- parameter \Y_WIDTH 1
- connect \A \ra [63:56]
- connect \B \rb [63:56]
- connect \Y $154
- end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:79"
- wire width 1 $156
+ wire width 1 $154
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:79"
- cell $eq $157
+ cell $eq $155
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \op__data_len [3]
connect \B 1'1
- connect \Y $156
+ connect \Y $154
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:80"
- wire width 64 $158
+ wire width 64 $156
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:75"
wire width 1 \par0
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:76"
wire width 1 \par1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:80"
- wire width 1 $159
+ wire width 1 $157
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:80"
- cell $xor $160
+ cell $xor $158
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \par0
connect \B \par1
- connect \Y $159
+ connect \Y $157
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:80"
- cell $pos $161
+ cell $pos $159
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 64
- connect \A $159
- connect \Y $158
+ connect \A $157
+ connect \Y $156
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:102"
- wire width 64 $162
+ wire width 64 $160
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:102"
- wire width 8 $163
+ wire width 8 $161
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:102"
- cell $sub $164
+ cell $sub $162
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 8
connect \A \clz_lz
connect \B 6'100000
- connect \Y $163
+ connect \Y $161
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:13"
- wire width 8 $165
+ wire width 8 $163
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:13"
- cell $pos $166
+ cell $pos $164
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \Y_WIDTH 8
connect \A \clz_lz
- connect \Y $165
+ connect \Y $163
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:102"
- wire width 8 $167
+ wire width 8 $165
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:102"
- cell $mux $168
+ cell $mux $166
parameter \WIDTH 8
- connect \A $165
- connect \B $163
+ connect \A $163
+ connect \B $161
connect \S \op__is_32bit
- connect \Y $167
+ connect \Y $165
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:102"
- cell $pos $169
+ cell $pos $167
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \Y_WIDTH 64
- connect \A $167
- connect \Y $162
+ connect \A $165
+ connect \Y $160
end
process $group_1
assign \o_ok 1'0
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:50"
attribute \nmigen.decoding "OP_AND/4"
case 7'0000100
- assign \o $22
+ assign \o $20
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:52"
attribute \nmigen.decoding "OP_OR/53"
case 7'0110101
- assign \o $24
+ assign \o $22
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:54"
attribute \nmigen.decoding "OP_XOR/67"
case 7'1000011
- assign \o $26
+ assign \o $24
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:58"
attribute \nmigen.decoding "OP_CMPB/11"
case 7'0001011
- assign \o { { $140 $142 $144 $146 $148 $150 $152 $154 } { $124 $126 $128 $130 $132 $134 $136 $138 } { $108 $110 $112 $114 $116 $118 $120 $122 } { $92 $94 $96 $98 $100 $102 $104 $106 } { $76 $78 $80 $82 $84 $86 $88 $90 } { $60 $62 $64 $66 $68 $70 $72 $74 } { $44 $46 $48 $50 $52 $54 $56 $58 } { $28 $30 $32 $34 $36 $38 $40 $42 } }
+ assign \o { { $138 $140 $142 $144 $146 $148 $150 $152 } { $122 $124 $126 $128 $130 $132 $134 $136 } { $106 $108 $110 $112 $114 $116 $118 $120 } { $90 $92 $94 $96 $98 $100 $102 $104 } { $74 $76 $78 $80 $82 $84 $86 $88 } { $58 $60 $62 $64 $66 $68 $70 $72 } { $42 $44 $46 $48 $50 $52 $54 $56 } { $26 $28 $30 $32 $34 $36 $38 $40 } }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
attribute \nmigen.decoding "OP_POPCNT/54"
case 7'0110110
attribute \nmigen.decoding "OP_PRTY/55"
case 7'0110111
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:79"
- switch { $156 }
+ switch { $154 }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:79"
case 1'1
- assign \o $158
+ assign \o $156
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:81"
case
assign { \o_ok \o } [0] \par0
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:86"
attribute \nmigen.decoding "OP_CNTZ/14"
case 7'0001110
- assign \o $162
+ assign \o $160
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:105"
attribute \nmigen.decoding "OP_BPERM/9"
case 7'0001001
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 64 $170
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- cell $pos $171
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 $168
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ cell $pos $169
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 64
connect \A \op__data_len
- connect \Y $170
+ connect \Y $168
end
process $group_4
assign \popcount_data_len 64'0000000000000000000000000000000000000000000000000000000000000000
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:66"
attribute \nmigen.decoding "OP_POPCNT/54"
case 7'0110110
- assign \popcount_data_len $170
+ assign \popcount_data_len $168
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:73"
attribute \nmigen.decoding "OP_PRTY/55"
case 7'0110111
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:77"
- wire width 1 $172
+ wire width 1 $170
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:77"
- cell $reduce_xor $173
+ cell $reduce_xor $171
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 1
connect \A { \ra [24] \ra [16] \ra [8] \ra [0] }
- connect \Y $172
+ connect \Y $170
end
process $group_5
assign \par0 1'0
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:73"
attribute \nmigen.decoding "OP_PRTY/55"
case 7'0110111
- assign \par0 $172
+ assign \par0 $170
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:86"
attribute \nmigen.decoding "OP_CNTZ/14"
case 7'0001110
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:78"
- wire width 1 $174
+ wire width 1 $172
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:78"
- cell $reduce_xor $175
+ cell $reduce_xor $173
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 1
connect \A { \ra [56] \ra [48] \ra [40] \ra [32] }
- connect \Y $174
+ connect \Y $172
end
process $group_6
assign \par1 1'0
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:73"
attribute \nmigen.decoding "OP_PRTY/55"
case 7'0110111
- assign \par1 $174
+ assign \par1 $172
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:86"
attribute \nmigen.decoding "OP_CNTZ/14"
case 7'0001110
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:91"
wire width 64 \cntz_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:96"
- wire width 64 $176
+ wire width 64 $174
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:96"
- wire width 32 $177
+ wire width 32 $175
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:96"
- cell $mux $178
+ cell $mux $176
parameter \WIDTH 32
connect \A \a32
connect \B { \a32 [0] \a32 [1] \a32 [2] \a32 [3] \a32 [4] \a32 [5] \a32 [6] \a32 [7] \a32 [8] \a32 [9] \a32 [10] \a32 [11] \a32 [12] \a32 [13] \a32 [14] \a32 [15] \a32 [16] \a32 [17] \a32 [18] \a32 [19] \a32 [20] \a32 [21] \a32 [22] \a32 [23] \a32 [24] \a32 [25] \a32 [26] \a32 [27] \a32 [28] \a32 [29] \a32 [30] \a32 [31] }
connect \S \count_right
- connect \Y $177
+ connect \Y $175
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:96"
- cell $pos $179
+ cell $pos $177
parameter \A_SIGNED 0
parameter \A_WIDTH 32
parameter \Y_WIDTH 64
- connect \A $177
- connect \Y $176
+ connect \A $175
+ connect \Y $174
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:98"
- wire width 64 $180
+ wire width 64 $178
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:98"
- cell $mux $181
+ cell $mux $179
parameter \WIDTH 64
connect \A \ra
connect \B { \ra [0] \ra [1] \ra [2] \ra [3] \ra [4] \ra [5] \ra [6] \ra [7] \ra [8] \ra [9] \ra [10] \ra [11] \ra [12] \ra [13] \ra [14] \ra [15] \ra [16] \ra [17] \ra [18] \ra [19] \ra [20] \ra [21] \ra [22] \ra [23] \ra [24] \ra [25] \ra [26] \ra [27] \ra [28] \ra [29] \ra [30] \ra [31] \ra [32] \ra [33] \ra [34] \ra [35] \ra [36] \ra [37] \ra [38] \ra [39] \ra [40] \ra [41] \ra [42] \ra [43] \ra [44] \ra [45] \ra [46] \ra [47] \ra [48] \ra [49] \ra [50] \ra [51] \ra [52] \ra [53] \ra [54] \ra [55] \ra [56] \ra [57] \ra [58] \ra [59] \ra [60] \ra [61] \ra [62] \ra [63] }
connect \S \count_right
- connect \Y $180
+ connect \Y $178
end
process $group_9
assign \cntz_i 64'0000000000000000000000000000000000000000000000000000000000000000
switch { \op__is_32bit }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:95"
case 1'1
- assign \cntz_i $176
+ assign \cntz_i $174
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:97"
case
- assign \cntz_i $180
+ assign \cntz_i $178
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:105"
attribute \nmigen.decoding "OP_BPERM/9"
assign \op__fn_unit$3 11'00000000000
assign \op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000
assign \op__imm_data__imm_ok$5 1'0
- assign \op__lk$6 1'0
- assign \op__rc__rc$7 1'0
- assign \op__rc__rc_ok$8 1'0
- assign \op__oe__oe$9 1'0
- assign \op__oe__oe_ok$10 1'0
- assign \op__invert_a$11 1'0
- assign \op__zero_a$12 1'0
- assign \op__input_carry$13 2'00
- assign \op__invert_out$14 1'0
- assign \op__write_cr__data$15 3'000
- assign \op__write_cr__ok$16 1'0
- assign \op__output_carry$17 1'0
- assign \op__is_32bit$18 1'0
- assign \op__is_signed$19 1'0
- assign \op__data_len$20 4'0000
- assign \op__insn$21 32'00000000000000000000000000000000
- assign { \op__insn$21 \op__data_len$20 \op__is_signed$19 \op__is_32bit$18 \op__output_carry$17 { \op__write_cr__ok$16 \op__write_cr__data$15 } \op__invert_out$14 \op__input_carry$13 \op__zero_a$12 \op__invert_a$11 { \op__oe__oe_ok$10 \op__oe__oe$9 } { \op__rc__rc_ok$8 \op__rc__rc$7 } \op__lk$6 { \op__imm_data__imm_ok$5 \op__imm_data__imm$4 } \op__fn_unit$3 \op__insn_type$2 } { \op__insn \op__data_len \op__is_signed \op__is_32bit \op__output_carry { \op__write_cr__ok \op__write_cr__data } \op__invert_out \op__input_carry \op__zero_a \op__invert_a { \op__oe__oe_ok \op__oe__oe } { \op__rc__rc_ok \op__rc__rc } \op__lk { \op__imm_data__imm_ok \op__imm_data__imm } \op__fn_unit \op__insn_type }
+ assign \op__rc__rc$6 1'0
+ assign \op__rc__rc_ok$7 1'0
+ assign \op__oe__oe$8 1'0
+ assign \op__oe__oe_ok$9 1'0
+ assign \op__invert_a$10 1'0
+ assign \op__zero_a$11 1'0
+ assign \op__input_carry$12 2'00
+ assign \op__invert_out$13 1'0
+ assign \op__write_cr0$14 1'0
+ assign \op__output_carry$15 1'0
+ assign \op__is_32bit$16 1'0
+ assign \op__is_signed$17 1'0
+ assign \op__data_len$18 4'0000
+ assign \op__insn$19 32'00000000000000000000000000000000
+ assign { \op__insn$19 \op__data_len$18 \op__is_signed$17 \op__is_32bit$16 \op__output_carry$15 \op__write_cr0$14 \op__invert_out$13 \op__input_carry$12 \op__zero_a$11 \op__invert_a$10 { \op__oe__oe_ok$9 \op__oe__oe$8 } { \op__rc__rc_ok$7 \op__rc__rc$6 } { \op__imm_data__imm_ok$5 \op__imm_data__imm$4 } \op__fn_unit$3 \op__insn_type$2 } { \op__insn \op__data_len \op__is_signed \op__is_32bit \op__output_carry \op__write_cr0 \op__invert_out \op__input_carry \op__zero_a \op__invert_a { \op__oe__oe_ok \op__oe__oe } { \op__rc__rc_ok \op__rc__rc } { \op__imm_data__imm_ok \op__imm_data__imm } \op__fn_unit \op__insn_type }
sync init
end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_logical0.pipe.output"
module \output$50
- attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
wire width 2 input 0 \muxid
- attribute \enum_base_type "InternalOp"
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 7 input 1 \op__insn_type
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00100000000 "MUL"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 11 input 2 \op__fn_unit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 64 input 3 \op__imm_data__imm
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 input 4 \op__imm_data__imm_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 input 5 \op__lk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 input 6 \op__rc__rc
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 input 7 \op__rc__rc_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 input 8 \op__oe__oe
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 input 9 \op__oe__oe_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 input 10 \op__invert_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 input 11 \op__zero_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 5 \op__rc__rc
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 6 \op__rc__rc_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 7 \op__oe__oe
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 8 \op__oe__oe_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 9 \op__invert_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 10 \op__zero_a
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 2 input 12 \op__input_carry
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 input 13 \op__invert_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 3 input 14 \op__write_cr__data
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 input 15 \op__write_cr__ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 input 16 \op__output_carry
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 input 17 \op__is_32bit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 input 18 \op__is_signed
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 4 input 19 \op__data_len
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 32 input 20 \op__insn
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 2 input 11 \op__input_carry
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 12 \op__invert_out
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 13 \op__write_cr0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 14 \op__output_carry
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 15 \op__is_32bit
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 16 \op__is_signed
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 4 input 17 \op__data_len
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 input 18 \op__insn
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 input 21 \o
+ wire width 64 input 19 \o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 input 22 \o_ok
+ wire width 1 input 20 \o_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 4 input 23 \cr_a
+ wire width 4 input 21 \cr_a
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 2 input 24 \xer_ca
- attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
- wire width 2 output 25 \muxid$1
- attribute \enum_base_type "InternalOp"
+ wire width 2 input 22 \xer_ca
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+ wire width 2 output 23 \muxid$1
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 7 output 26 \op__insn_type$2
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 7 output 24 \op__insn_type$2
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00000000010 "ALU"
attribute \enum_value_00100000000 "MUL"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 11 output 27 \op__fn_unit$3
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 64 output 28 \op__imm_data__imm$4
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 output 29 \op__imm_data__imm_ok$5
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 output 30 \op__lk$6
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 output 31 \op__rc__rc$7
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 output 32 \op__rc__rc_ok$8
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 output 33 \op__oe__oe$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 output 34 \op__oe__oe_ok$10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 output 35 \op__invert_a$11
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 output 36 \op__zero_a$12
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 11 output 25 \op__fn_unit$3
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 output 26 \op__imm_data__imm$4
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 27 \op__imm_data__imm_ok$5
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 28 \op__rc__rc$6
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 29 \op__rc__rc_ok$7
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 30 \op__oe__oe$8
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 31 \op__oe__oe_ok$9
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 32 \op__invert_a$10
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 33 \op__zero_a$11
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 2 output 37 \op__input_carry$13
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 output 38 \op__invert_out$14
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 3 output 39 \op__write_cr__data$15
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 output 40 \op__write_cr__ok$16
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 output 41 \op__output_carry$17
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 output 42 \op__is_32bit$18
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 output 43 \op__is_signed$19
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 4 output 44 \op__data_len$20
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 32 output 45 \op__insn$21
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 output 46 \o$22
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 47 \o_ok$23
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 4 output 48 \cr_a$24
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 49 \cr_a_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 2 output 50 \xer_ca$25
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 51 \xer_ca_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:19"
- wire width 65 \o$26
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:22"
- wire width 65 $27
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:22"
- wire width 64 $28
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:22"
- cell $not $29
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 2 output 34 \op__input_carry$12
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 35 \op__invert_out$13
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 36 \op__write_cr0$14
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 37 \op__output_carry$15
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 38 \op__is_32bit$16
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 39 \op__is_signed$17
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 4 output 40 \op__data_len$18
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 output 41 \op__insn$19
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 64 output 42 \o$20
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 43 \o_ok$21
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 4 output 44 \cr_a$22
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 45 \cr_a_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 2 output 46 \xer_ca$23
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 47 \xer_ca_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:23"
+ wire width 65 \o$24
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:26"
+ wire width 65 $25
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:26"
+ wire width 64 $26
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:26"
+ cell $not $27
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 64
connect \A \o
- connect \Y $28
+ connect \Y $26
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:22"
- cell $pos $30
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:26"
+ cell $pos $28
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 65
- connect \A $28
- connect \Y $27
+ connect \A $26
+ connect \Y $25
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 65 $31
+ wire width 65 $29
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- cell $pos $32
+ cell $pos $30
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 65
connect \A \o
- connect \Y $31
+ connect \Y $29
end
process $group_0
- assign \o$26 65'00000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:21"
+ assign \o$24 65'00000000000000000000000000000000000000000000000000000000000000000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:25"
switch { \op__invert_out }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:21"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:25"
case 1'1
- assign \o$26 $27
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:23"
+ assign \o$24 $25
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:27"
case
- assign \o$26 $31
+ assign \o$24 $29
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:35"
wire width 64 \target
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:251"
- wire width 64 $33
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:251"
- cell $pos $34
- parameter \A_SIGNED 0
- parameter \A_WIDTH 32
- parameter \Y_WIDTH 64
- connect \A \o$26 [31:0]
- connect \Y $33
- end
process $group_1
assign \target 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:30"
- switch { \op__is_32bit }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:30"
- case 1'1
- assign \target $33
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:32"
- case
- assign \target \o$26 [63:0]
- end
+ assign \target \o$24 [63:0]
sync init
end
process $group_2
- assign \xer_ca$25 2'00
- assign \xer_ca$25 \xer_ca
+ assign \xer_ca$23 2'00
+ assign \xer_ca$23 \xer_ca
sync init
end
process $group_3
assign \xer_ca_ok \op__output_carry
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:44"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:54"
wire width 1 \is_cmp
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:53"
- wire width 1 $35
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:53"
- cell $eq $36
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:63"
+ wire width 1 $31
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:63"
+ cell $eq $32
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \op__insn_type
connect \B 7'0001010
- connect \Y $35
+ connect \Y $31
end
process $group_4
assign \is_cmp 1'0
- assign \is_cmp $35
+ assign \is_cmp $31
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:45"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:55"
wire width 1 \is_cmpeqb
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:54"
- wire width 1 $37
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:54"
- cell $eq $38
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:64"
+ wire width 1 $33
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:64"
+ cell $eq $34
parameter \A_SIGNED 0
parameter \A_WIDTH 7
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \op__insn_type
connect \B 7'0001100
- connect \Y $37
+ connect \Y $33
end
process $group_5
assign \is_cmpeqb 1'0
- assign \is_cmpeqb $37
+ assign \is_cmpeqb $33
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:43"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:53"
wire width 1 \msb_test
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:55"
- wire width 1 $39
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:55"
- cell $xor $40
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \target [63]
- connect \B \is_cmp
- connect \Y $39
- end
process $group_6
assign \msb_test 1'0
- assign \msb_test $39
+ assign \msb_test \target [63]
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:40"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:50"
wire width 1 \is_nzero
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:56"
- wire width 1 $41
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:56"
- cell $reduce_bool $42
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71"
+ wire width 1 $35
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71"
+ cell $reduce_bool $36
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 1
connect \A \target
- connect \Y $41
+ connect \Y $35
end
process $group_7
assign \is_nzero 1'0
- assign \is_nzero $41
+ assign \is_nzero $35
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:51"
wire width 1 \is_positive
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:57"
- wire width 1 $43
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:57"
- cell $not $44
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77"
+ wire width 1 $37
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77"
+ cell $not $38
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \msb_test
- connect \Y $43
+ connect \Y $37
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:57"
- wire width 1 $45
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:57"
- cell $and $46
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77"
+ wire width 1 $39
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77"
+ cell $and $40
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \is_nzero
- connect \B $43
- connect \Y $45
+ connect \B $37
+ connect \Y $39
end
process $group_8
assign \is_positive 1'0
- assign \is_positive $45
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:72"
+ switch { \is_cmp }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:72"
+ case 1'1
+ assign \is_positive \msb_test
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:75"
+ case
+ assign \is_positive $39
+ end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:42"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:52"
wire width 1 \is_negative
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:58"
- wire width 1 $47
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:58"
- cell $and $48
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:74"
+ wire width 1 $41
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:74"
+ cell $not $42
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \msb_test
+ connect \Y $41
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:74"
+ wire width 1 $43
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:74"
+ cell $and $44
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \is_nzero
- connect \B \msb_test
- connect \Y $47
+ connect \B $41
+ connect \Y $43
end
process $group_9
assign \is_negative 1'0
- assign \is_negative $47
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:72"
+ switch { \is_cmp }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:72"
+ case 1'1
+ assign \is_negative $43
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:75"
+ case
+ assign \is_negative \msb_test
+ end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:47"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:57"
wire width 4 \cr0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:46"
- wire width 1 \so
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:63"
- wire width 1 $49
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:63"
- cell $not $50
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:82"
+ wire width 1 $45
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:82"
+ cell $not $46
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \is_nzero
- connect \Y $49
+ connect \Y $45
end
process $group_10
assign \cr0 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:60"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:79"
switch { \is_cmpeqb }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:60"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:79"
case 1'1
assign \cr0 \cr_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:62"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81"
case
- assign \cr0 { \is_negative \is_positive $49 \so }
+ assign \cr0 { \is_negative \is_positive $45 1'0 }
end
sync init
end
process $group_11
- assign \o$22 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \o$22 \o$26 [63:0]
+ assign \o$20 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \o$20 \o$24 [63:0]
sync init
end
process $group_12
- assign \o_ok$23 1'0
- assign \o_ok$23 \o_ok
+ assign \o_ok$21 1'0
+ assign \o_ok$21 \o_ok
sync init
end
process $group_13
- assign \cr_a$24 4'0000
- assign \cr_a$24 \cr0
+ assign \cr_a$22 4'0000
+ assign \cr_a$22 \cr0
sync init
end
process $group_14
assign \cr_a_ok 1'0
- assign \cr_a_ok \op__write_cr__ok
+ assign \cr_a_ok \op__write_cr0
sync init
end
process $group_15
assign \op__fn_unit$3 11'00000000000
assign \op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000
assign \op__imm_data__imm_ok$5 1'0
- assign \op__lk$6 1'0
- assign \op__rc__rc$7 1'0
- assign \op__rc__rc_ok$8 1'0
- assign \op__oe__oe$9 1'0
- assign \op__oe__oe_ok$10 1'0
- assign \op__invert_a$11 1'0
- assign \op__zero_a$12 1'0
- assign \op__input_carry$13 2'00
- assign \op__invert_out$14 1'0
- assign \op__write_cr__data$15 3'000
- assign \op__write_cr__ok$16 1'0
- assign \op__output_carry$17 1'0
- assign \op__is_32bit$18 1'0
- assign \op__is_signed$19 1'0
- assign \op__data_len$20 4'0000
- assign \op__insn$21 32'00000000000000000000000000000000
- assign { \op__insn$21 \op__data_len$20 \op__is_signed$19 \op__is_32bit$18 \op__output_carry$17 { \op__write_cr__ok$16 \op__write_cr__data$15 } \op__invert_out$14 \op__input_carry$13 \op__zero_a$12 \op__invert_a$11 { \op__oe__oe_ok$10 \op__oe__oe$9 } { \op__rc__rc_ok$8 \op__rc__rc$7 } \op__lk$6 { \op__imm_data__imm_ok$5 \op__imm_data__imm$4 } \op__fn_unit$3 \op__insn_type$2 } { \op__insn \op__data_len \op__is_signed \op__is_32bit \op__output_carry { \op__write_cr__ok \op__write_cr__data } \op__invert_out \op__input_carry \op__zero_a \op__invert_a { \op__oe__oe_ok \op__oe__oe } { \op__rc__rc_ok \op__rc__rc } \op__lk { \op__imm_data__imm_ok \op__imm_data__imm } \op__fn_unit \op__insn_type }
- sync init
- end
- connect \so 1'0
+ assign \op__rc__rc$6 1'0
+ assign \op__rc__rc_ok$7 1'0
+ assign \op__oe__oe$8 1'0
+ assign \op__oe__oe_ok$9 1'0
+ assign \op__invert_a$10 1'0
+ assign \op__zero_a$11 1'0
+ assign \op__input_carry$12 2'00
+ assign \op__invert_out$13 1'0
+ assign \op__write_cr0$14 1'0
+ assign \op__output_carry$15 1'0
+ assign \op__is_32bit$16 1'0
+ assign \op__is_signed$17 1'0
+ assign \op__data_len$18 4'0000
+ assign \op__insn$19 32'00000000000000000000000000000000
+ assign { \op__insn$19 \op__data_len$18 \op__is_signed$17 \op__is_32bit$16 \op__output_carry$15 \op__write_cr0$14 \op__invert_out$13 \op__input_carry$12 \op__zero_a$11 \op__invert_a$10 { \op__oe__oe_ok$9 \op__oe__oe$8 } { \op__rc__rc_ok$7 \op__rc__rc$6 } { \op__imm_data__imm_ok$5 \op__imm_data__imm$4 } \op__fn_unit$3 \op__insn_type$2 } { \op__insn \op__data_len \op__is_signed \op__is_32bit \op__output_carry \op__write_cr0 \op__invert_out \op__input_carry \op__zero_a \op__invert_a { \op__oe__oe_ok \op__oe__oe } { \op__rc__rc_ok \op__rc__rc } { \op__imm_data__imm_ok \op__imm_data__imm } \op__fn_unit \op__insn_type }
+ sync init
+ end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_logical0.pipe"
wire width 1 input 0 \rst
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153"
wire width 1 input 2 \p_valid_i
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154"
wire width 1 output 3 \p_ready_o
- attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
wire width 2 input 4 \muxid
- attribute \enum_base_type "InternalOp"
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 7 input 5 \op__insn_type
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00100000000 "MUL"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 11 input 6 \op__fn_unit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 64 input 7 \op__imm_data__imm
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 input 8 \op__imm_data__imm_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 input 9 \op__lk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 input 10 \op__rc__rc
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 input 11 \op__rc__rc_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 input 12 \op__oe__oe
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 input 13 \op__oe__oe_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 input 14 \op__invert_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 input 15 \op__zero_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 9 \op__rc__rc
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 10 \op__rc__rc_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 11 \op__oe__oe
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 12 \op__oe__oe_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 13 \op__invert_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 14 \op__zero_a
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 2 input 16 \op__input_carry
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 input 17 \op__invert_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 3 input 18 \op__write_cr__data
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 input 19 \op__write_cr__ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 input 20 \op__output_carry
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 input 21 \op__is_32bit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 input 22 \op__is_signed
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 4 input 23 \op__data_len
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 32 input 24 \op__insn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
- wire width 64 input 25 \ra
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
- wire width 64 input 26 \rb
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244"
- wire width 1 output 27 \n_valid_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245"
- wire width 1 input 28 \n_ready_i
- attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
- wire width 2 output 29 \muxid$1
- attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 2 input 15 \op__input_carry
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 16 \op__invert_out
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 17 \op__write_cr0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 18 \op__output_carry
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 19 \op__is_32bit
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 20 \op__is_signed
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 4 input 21 \op__data_len
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 input 22 \op__insn
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 64 input 23 \ra
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 64 input 24 \rb
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
+ wire width 1 output 25 \n_valid_o
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
+ wire width 1 input 26 \n_ready_i
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+ wire width 2 output 27 \muxid$1
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
wire width 2 \muxid$1$next
- attribute \enum_base_type "InternalOp"
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 7 output 30 \op__insn_type$2
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 7 output 28 \op__insn_type$2
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 7 \op__insn_type$2$next
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00100000000 "MUL"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 11 output 31 \op__fn_unit$3
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 11 output 29 \op__fn_unit$3
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 11 \op__fn_unit$3$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 64 output 32 \op__imm_data__imm$4
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 output 30 \op__imm_data__imm$4
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 64 \op__imm_data__imm$4$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 output 33 \op__imm_data__imm_ok$5
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 31 \op__imm_data__imm_ok$5
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \op__imm_data__imm_ok$5$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 output 34 \op__lk$6
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 \op__lk$6$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 output 35 \op__rc__rc$7
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 \op__rc__rc$7$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 output 36 \op__rc__rc_ok$8
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 \op__rc__rc_ok$8$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 output 37 \op__oe__oe$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 \op__oe__oe$9$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 output 38 \op__oe__oe_ok$10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 \op__oe__oe_ok$10$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 output 39 \op__invert_a$11
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 \op__invert_a$11$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 output 40 \op__zero_a$12
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 \op__zero_a$12$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 32 \op__rc__rc$6
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__rc__rc$6$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 33 \op__rc__rc_ok$7
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__rc__rc_ok$7$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 34 \op__oe__oe$8
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__oe__oe$8$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 35 \op__oe__oe_ok$9
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__oe__oe_ok$9$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 36 \op__invert_a$10
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__invert_a$10$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 37 \op__zero_a$11
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__zero_a$11$next
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 2 output 41 \op__input_carry$13
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 2 \op__input_carry$13$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 output 42 \op__invert_out$14
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 \op__invert_out$14$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 3 output 43 \op__write_cr__data$15
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 3 \op__write_cr__data$15$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 output 44 \op__write_cr__ok$16
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 \op__write_cr__ok$16$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 output 45 \op__output_carry$17
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 \op__output_carry$17$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 output 46 \op__is_32bit$18
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 \op__is_32bit$18$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 output 47 \op__is_signed$19
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 \op__is_signed$19$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 4 output 48 \op__data_len$20
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 4 \op__data_len$20$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 32 output 49 \op__insn$21
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 32 \op__insn$21$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 output 50 \o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 2 output 38 \op__input_carry$12
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 2 \op__input_carry$12$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 39 \op__invert_out$13
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__invert_out$13$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 40 \op__write_cr0$14
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__write_cr0$14$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 41 \op__output_carry$15
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__output_carry$15$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 42 \op__is_32bit$16
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__is_32bit$16$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 43 \op__is_signed$17
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__is_signed$17$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 4 output 44 \op__data_len$18
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 4 \op__data_len$18$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 output 45 \op__insn$19
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 \op__insn$19$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 64 output 46 \o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 64 \o$next
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 51 \o_ok
+ wire width 1 output 47 \o_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 \o_ok$next
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 4 output 52 \cr_a
+ wire width 4 output 48 \cr_a
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 4 \cr_a$next
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 \cr_a_ok$next
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 2 output 54 \xer_ca
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 2 \xer_ca$next
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 \xer_ca_ok$next
cell \p$46 \p
connect \n_valid_o \n_valid_o
connect \n_ready_i \n_ready_i
end
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wire width 2 \input_muxid
- attribute \enum_base_type "InternalOp"
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attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
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wire width 7 \input_op__insn_type
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
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attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
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wire width 11 \input_op__fn_unit
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wire width 64 \input_op__imm_data__imm
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wire width 1 \input_op__imm_data__imm_ok
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wire width 1 \input_op__rc__rc
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wire width 1 \input_op__rc__rc_ok
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wire width 1 \input_op__oe__oe
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wire width 1 \input_op__oe__oe_ok
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wire width 1 \input_op__invert_a
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wire width 1 \input_op__zero_a
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attribute \enum_value_10 "CA"
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wire width 2 \input_op__input_carry
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wire width 1 \input_op__invert_out
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wire width 1 \input_op__output_carry
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wire width 1 \input_op__is_32bit
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wire width 1 \input_op__is_signed
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wire width 4 \input_op__data_len
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wire width 32 \input_op__insn
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wire width 64 \input_ra
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wire width 64 \input_rb
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- wire width 2 \input_muxid$22
- attribute \enum_base_type "InternalOp"
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attribute \enum_value_0000000 "OP_ILLEGAL"
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attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
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- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 7 \input_op__insn_type$23
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attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00000000010 "ALU"
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- wire width 1 \input_op__zero_a$33
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attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
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cell \input$48 \input
connect \muxid \input_muxid
connect \op__insn_type \input_op__insn_type
connect \op__fn_unit \input_op__fn_unit
connect \op__imm_data__imm \input_op__imm_data__imm
connect \op__imm_data__imm_ok \input_op__imm_data__imm_ok
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connect \op__rc__rc \input_op__rc__rc
connect \op__rc__rc_ok \input_op__rc__rc_ok
connect \op__oe__oe \input_op__oe__oe
connect \op__zero_a \input_op__zero_a
connect \op__input_carry \input_op__input_carry
connect \op__invert_out \input_op__invert_out
- connect \op__write_cr__data \input_op__write_cr__data
- connect \op__write_cr__ok \input_op__write_cr__ok
+ connect \op__write_cr0 \input_op__write_cr0
connect \op__output_carry \input_op__output_carry
connect \op__is_32bit \input_op__is_32bit
connect \op__is_signed \input_op__is_signed
connect \op__insn \input_op__insn
connect \ra \input_ra
connect \rb \input_rb
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- connect \rb$23 \input_rb$44
- end
- attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+ connect \muxid$1 \input_muxid$20
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+ connect \op__fn_unit$3 \input_op__fn_unit$22
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+ connect \op__write_cr0$14 \input_op__write_cr0$33
+ connect \op__output_carry$15 \input_op__output_carry$34
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+ connect \op__is_signed$17 \input_op__is_signed$36
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+ connect \op__insn$19 \input_op__insn$38
+ connect \ra$20 \input_ra$39
+ connect \rb$21 \input_rb$40
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
wire width 2 \main_muxid
- attribute \enum_base_type "InternalOp"
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attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
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wire width 7 \main_op__insn_type
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00100000000 "MUL"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
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wire width 11 \main_op__fn_unit
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wire width 64 \main_op__imm_data__imm
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wire width 1 \main_op__imm_data__imm_ok
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- wire width 1 \main_op__lk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
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wire width 1 \main_op__rc__rc
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wire width 1 \main_op__rc__rc_ok
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wire width 1 \main_op__oe__oe
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wire width 1 \main_op__oe__oe_ok
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wire width 1 \main_op__invert_a
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wire width 1 \main_op__zero_a
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
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wire width 2 \main_op__input_carry
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
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wire width 1 \main_op__invert_out
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connect \o \main_o
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end
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \output_op__oe__oe_ok$68
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \output_op__invert_a$69
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \output_op__zero_a$70
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 2 \output_op__input_carry$78
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 \output_op__invert_out$79
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 3 \output_op__write_cr__data$80
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 \output_op__write_cr__ok$81
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 \output_op__output_carry$82
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 \output_op__is_32bit$83
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 \output_op__is_signed$84
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 4 \output_op__data_len$85
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 32 \output_op__insn$86
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 \output_o$87
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 \output_o_ok$88
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 4 \output_cr_a$89
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 2 \output_op__input_carry$71
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \output_op__invert_out$72
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \output_op__write_cr0$73
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \output_op__output_carry$74
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \output_op__is_32bit$75
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \output_op__is_signed$76
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 4 \output_op__data_len$77
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 \output_op__insn$78
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 64 \output_o$79
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 \output_o_ok$80
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 4 \output_cr_a$81
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 \output_cr_a_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 2 \output_xer_ca$90
+ wire width 2 \output_xer_ca$82
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 \output_xer_ca_ok
cell \output$50 \output
connect \op__fn_unit \output_op__fn_unit
connect \op__imm_data__imm \output_op__imm_data__imm
connect \op__imm_data__imm_ok \output_op__imm_data__imm_ok
- connect \op__lk \output_op__lk
connect \op__rc__rc \output_op__rc__rc
connect \op__rc__rc_ok \output_op__rc__rc_ok
connect \op__oe__oe \output_op__oe__oe
connect \op__zero_a \output_op__zero_a
connect \op__input_carry \output_op__input_carry
connect \op__invert_out \output_op__invert_out
- connect \op__write_cr__data \output_op__write_cr__data
- connect \op__write_cr__ok \output_op__write_cr__ok
+ connect \op__write_cr0 \output_op__write_cr0
connect \op__output_carry \output_op__output_carry
connect \op__is_32bit \output_op__is_32bit
connect \op__is_signed \output_op__is_signed
connect \o_ok \output_o_ok
connect \cr_a \output_cr_a
connect \xer_ca \output_xer_ca
- connect \muxid$1 \output_muxid$66
- connect \op__insn_type$2 \output_op__insn_type$67
- connect \op__fn_unit$3 \output_op__fn_unit$68
- connect \op__imm_data__imm$4 \output_op__imm_data__imm$69
- connect \op__imm_data__imm_ok$5 \output_op__imm_data__imm_ok$70
- connect \op__lk$6 \output_op__lk$71
- connect \op__rc__rc$7 \output_op__rc__rc$72
- connect \op__rc__rc_ok$8 \output_op__rc__rc_ok$73
- connect \op__oe__oe$9 \output_op__oe__oe$74
- connect \op__oe__oe_ok$10 \output_op__oe__oe_ok$75
- connect \op__invert_a$11 \output_op__invert_a$76
- connect \op__zero_a$12 \output_op__zero_a$77
- connect \op__input_carry$13 \output_op__input_carry$78
- connect \op__invert_out$14 \output_op__invert_out$79
- connect \op__write_cr__data$15 \output_op__write_cr__data$80
- connect \op__write_cr__ok$16 \output_op__write_cr__ok$81
- connect \op__output_carry$17 \output_op__output_carry$82
- connect \op__is_32bit$18 \output_op__is_32bit$83
- connect \op__is_signed$19 \output_op__is_signed$84
- connect \op__data_len$20 \output_op__data_len$85
- connect \op__insn$21 \output_op__insn$86
- connect \o$22 \output_o$87
- connect \o_ok$23 \output_o_ok$88
- connect \cr_a$24 \output_cr_a$89
+ connect \muxid$1 \output_muxid$60
+ connect \op__insn_type$2 \output_op__insn_type$61
+ connect \op__fn_unit$3 \output_op__fn_unit$62
+ connect \op__imm_data__imm$4 \output_op__imm_data__imm$63
+ connect \op__imm_data__imm_ok$5 \output_op__imm_data__imm_ok$64
+ connect \op__rc__rc$6 \output_op__rc__rc$65
+ connect \op__rc__rc_ok$7 \output_op__rc__rc_ok$66
+ connect \op__oe__oe$8 \output_op__oe__oe$67
+ connect \op__oe__oe_ok$9 \output_op__oe__oe_ok$68
+ connect \op__invert_a$10 \output_op__invert_a$69
+ connect \op__zero_a$11 \output_op__zero_a$70
+ connect \op__input_carry$12 \output_op__input_carry$71
+ connect \op__invert_out$13 \output_op__invert_out$72
+ connect \op__write_cr0$14 \output_op__write_cr0$73
+ connect \op__output_carry$15 \output_op__output_carry$74
+ connect \op__is_32bit$16 \output_op__is_32bit$75
+ connect \op__is_signed$17 \output_op__is_signed$76
+ connect \op__data_len$18 \output_op__data_len$77
+ connect \op__insn$19 \output_op__insn$78
+ connect \o$20 \output_o$79
+ connect \o_ok$21 \output_o_ok$80
+ connect \cr_a$22 \output_cr_a$81
connect \cr_a_ok \output_cr_a_ok
- connect \xer_ca$25 \output_xer_ca$90
+ connect \xer_ca$23 \output_xer_ca$82
connect \xer_ca_ok \output_xer_ca_ok
end
process $group_0
assign \input_op__fn_unit 11'00000000000
assign \input_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
assign \input_op__imm_data__imm_ok 1'0
- assign \input_op__lk 1'0
assign \input_op__rc__rc 1'0
assign \input_op__rc__rc_ok 1'0
assign \input_op__oe__oe 1'0
assign \input_op__zero_a 1'0
assign \input_op__input_carry 2'00
assign \input_op__invert_out 1'0
- assign \input_op__write_cr__data 3'000
- assign \input_op__write_cr__ok 1'0
+ assign \input_op__write_cr0 1'0
assign \input_op__output_carry 1'0
assign \input_op__is_32bit 1'0
assign \input_op__is_signed 1'0
assign \input_op__data_len 4'0000
assign \input_op__insn 32'00000000000000000000000000000000
- assign { \input_op__insn \input_op__data_len \input_op__is_signed \input_op__is_32bit \input_op__output_carry { \input_op__write_cr__ok \input_op__write_cr__data } \input_op__invert_out \input_op__input_carry \input_op__zero_a \input_op__invert_a { \input_op__oe__oe_ok \input_op__oe__oe } { \input_op__rc__rc_ok \input_op__rc__rc } \input_op__lk { \input_op__imm_data__imm_ok \input_op__imm_data__imm } \input_op__fn_unit \input_op__insn_type } { \op__insn \op__data_len \op__is_signed \op__is_32bit \op__output_carry { \op__write_cr__ok \op__write_cr__data } \op__invert_out \op__input_carry \op__zero_a \op__invert_a { \op__oe__oe_ok \op__oe__oe } { \op__rc__rc_ok \op__rc__rc } \op__lk { \op__imm_data__imm_ok \op__imm_data__imm } \op__fn_unit \op__insn_type }
+ assign { \input_op__insn \input_op__data_len \input_op__is_signed \input_op__is_32bit \input_op__output_carry \input_op__write_cr0 \input_op__invert_out \input_op__input_carry \input_op__zero_a \input_op__invert_a { \input_op__oe__oe_ok \input_op__oe__oe } { \input_op__rc__rc_ok \input_op__rc__rc } { \input_op__imm_data__imm_ok \input_op__imm_data__imm } \input_op__fn_unit \input_op__insn_type } { \op__insn \op__data_len \op__is_signed \op__is_32bit \op__output_carry \op__write_cr0 \op__invert_out \op__input_carry \op__zero_a \op__invert_a { \op__oe__oe_ok \op__oe__oe } { \op__rc__rc_ok \op__rc__rc } { \op__imm_data__imm_ok \op__imm_data__imm } \op__fn_unit \op__insn_type }
sync init
end
- process $group_21
+ process $group_19
assign \input_ra 64'0000000000000000000000000000000000000000000000000000000000000000
assign \input_ra \ra
sync init
end
- process $group_22
+ process $group_20
assign \input_rb 64'0000000000000000000000000000000000000000000000000000000000000000
assign \input_rb \rb
sync init
end
- process $group_23
+ process $group_21
assign \main_muxid 2'00
- assign \main_muxid \input_muxid$22
+ assign \main_muxid \input_muxid$20
sync init
end
- process $group_24
+ process $group_22
assign \main_op__insn_type 7'0000000
assign \main_op__fn_unit 11'00000000000
assign \main_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
assign \main_op__imm_data__imm_ok 1'0
- assign \main_op__lk 1'0
assign \main_op__rc__rc 1'0
assign \main_op__rc__rc_ok 1'0
assign \main_op__oe__oe 1'0
assign \main_op__zero_a 1'0
assign \main_op__input_carry 2'00
assign \main_op__invert_out 1'0
- assign \main_op__write_cr__data 3'000
- assign \main_op__write_cr__ok 1'0
+ assign \main_op__write_cr0 1'0
assign \main_op__output_carry 1'0
assign \main_op__is_32bit 1'0
assign \main_op__is_signed 1'0
assign \main_op__data_len 4'0000
assign \main_op__insn 32'00000000000000000000000000000000
- assign { \main_op__insn \main_op__data_len \main_op__is_signed \main_op__is_32bit \main_op__output_carry { \main_op__write_cr__ok \main_op__write_cr__data } \main_op__invert_out \main_op__input_carry \main_op__zero_a \main_op__invert_a { \main_op__oe__oe_ok \main_op__oe__oe } { \main_op__rc__rc_ok \main_op__rc__rc } \main_op__lk { \main_op__imm_data__imm_ok \main_op__imm_data__imm } \main_op__fn_unit \main_op__insn_type } { \input_op__insn$42 \input_op__data_len$41 \input_op__is_signed$40 \input_op__is_32bit$39 \input_op__output_carry$38 { \input_op__write_cr__ok$37 \input_op__write_cr__data$36 } \input_op__invert_out$35 \input_op__input_carry$34 \input_op__zero_a$33 \input_op__invert_a$32 { \input_op__oe__oe_ok$31 \input_op__oe__oe$30 } { \input_op__rc__rc_ok$29 \input_op__rc__rc$28 } \input_op__lk$27 { \input_op__imm_data__imm_ok$26 \input_op__imm_data__imm$25 } \input_op__fn_unit$24 \input_op__insn_type$23 }
+ assign { \main_op__insn \main_op__data_len \main_op__is_signed \main_op__is_32bit \main_op__output_carry \main_op__write_cr0 \main_op__invert_out \main_op__input_carry \main_op__zero_a \main_op__invert_a { \main_op__oe__oe_ok \main_op__oe__oe } { \main_op__rc__rc_ok \main_op__rc__rc } { \main_op__imm_data__imm_ok \main_op__imm_data__imm } \main_op__fn_unit \main_op__insn_type } { \input_op__insn$38 \input_op__data_len$37 \input_op__is_signed$36 \input_op__is_32bit$35 \input_op__output_carry$34 \input_op__write_cr0$33 \input_op__invert_out$32 \input_op__input_carry$31 \input_op__zero_a$30 \input_op__invert_a$29 { \input_op__oe__oe_ok$28 \input_op__oe__oe$27 } { \input_op__rc__rc_ok$26 \input_op__rc__rc$25 } { \input_op__imm_data__imm_ok$24 \input_op__imm_data__imm$23 } \input_op__fn_unit$22 \input_op__insn_type$21 }
sync init
end
- process $group_44
+ process $group_40
assign \main_ra 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \main_ra \input_ra$43
+ assign \main_ra \input_ra$39
sync init
end
- process $group_45
+ process $group_41
assign \main_rb 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \main_rb \input_rb$44
+ assign \main_rb \input_rb$40
sync init
end
- process $group_46
+ process $group_42
assign \output_muxid 2'00
- assign \output_muxid \main_muxid$45
+ assign \output_muxid \main_muxid$41
sync init
end
- process $group_47
+ process $group_43
assign \output_op__insn_type 7'0000000
assign \output_op__fn_unit 11'00000000000
assign \output_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
assign \output_op__imm_data__imm_ok 1'0
- assign \output_op__lk 1'0
assign \output_op__rc__rc 1'0
assign \output_op__rc__rc_ok 1'0
assign \output_op__oe__oe 1'0
assign \output_op__zero_a 1'0
assign \output_op__input_carry 2'00
assign \output_op__invert_out 1'0
- assign \output_op__write_cr__data 3'000
- assign \output_op__write_cr__ok 1'0
+ assign \output_op__write_cr0 1'0
assign \output_op__output_carry 1'0
assign \output_op__is_32bit 1'0
assign \output_op__is_signed 1'0
assign \output_op__data_len 4'0000
assign \output_op__insn 32'00000000000000000000000000000000
- assign { \output_op__insn \output_op__data_len \output_op__is_signed \output_op__is_32bit \output_op__output_carry { \output_op__write_cr__ok \output_op__write_cr__data } \output_op__invert_out \output_op__input_carry \output_op__zero_a \output_op__invert_a { \output_op__oe__oe_ok \output_op__oe__oe } { \output_op__rc__rc_ok \output_op__rc__rc } \output_op__lk { \output_op__imm_data__imm_ok \output_op__imm_data__imm } \output_op__fn_unit \output_op__insn_type } { \main_op__insn$65 \main_op__data_len$64 \main_op__is_signed$63 \main_op__is_32bit$62 \main_op__output_carry$61 { \main_op__write_cr__ok$60 \main_op__write_cr__data$59 } \main_op__invert_out$58 \main_op__input_carry$57 \main_op__zero_a$56 \main_op__invert_a$55 { \main_op__oe__oe_ok$54 \main_op__oe__oe$53 } { \main_op__rc__rc_ok$52 \main_op__rc__rc$51 } \main_op__lk$50 { \main_op__imm_data__imm_ok$49 \main_op__imm_data__imm$48 } \main_op__fn_unit$47 \main_op__insn_type$46 }
+ assign { \output_op__insn \output_op__data_len \output_op__is_signed \output_op__is_32bit \output_op__output_carry \output_op__write_cr0 \output_op__invert_out \output_op__input_carry \output_op__zero_a \output_op__invert_a { \output_op__oe__oe_ok \output_op__oe__oe } { \output_op__rc__rc_ok \output_op__rc__rc } { \output_op__imm_data__imm_ok \output_op__imm_data__imm } \output_op__fn_unit \output_op__insn_type } { \main_op__insn$59 \main_op__data_len$58 \main_op__is_signed$57 \main_op__is_32bit$56 \main_op__output_carry$55 \main_op__write_cr0$54 \main_op__invert_out$53 \main_op__input_carry$52 \main_op__zero_a$51 \main_op__invert_a$50 { \main_op__oe__oe_ok$49 \main_op__oe__oe$48 } { \main_op__rc__rc_ok$47 \main_op__rc__rc$46 } { \main_op__imm_data__imm_ok$45 \main_op__imm_data__imm$44 } \main_op__fn_unit$43 \main_op__insn_type$42 }
sync init
end
- process $group_67
+ process $group_61
assign \output_o 64'0000000000000000000000000000000000000000000000000000000000000000
assign \output_o_ok 1'0
assign { \output_o_ok \output_o } { \main_o_ok \main_o }
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 \cr_a_ok$91
+ wire width 1 \cr_a_ok$83
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 4 \cr_a$92
+ wire width 4 \cr_a$84
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 \cr_a_ok$93
- process $group_69
+ wire width 1 \cr_a_ok$85
+ process $group_63
assign \output_cr_a 4'0000
- assign \cr_a_ok$91 1'0
- assign { \cr_a_ok$91 \output_cr_a } { \cr_a_ok$93 \cr_a$92 }
+ assign \cr_a_ok$83 1'0
+ assign { \cr_a_ok$83 \output_cr_a } { \cr_a_ok$85 \cr_a$84 }
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 \xer_ca_ok$94
+ wire width 1 \xer_ca_ok$86
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 2 \xer_ca$95
+ wire width 2 \xer_ca$87
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 \xer_ca_ok$96
- process $group_71
+ wire width 1 \xer_ca_ok$88
+ process $group_65
assign \output_xer_ca 2'00
- assign \xer_ca_ok$94 1'0
- assign { \xer_ca_ok$94 \output_xer_ca } { \xer_ca_ok$96 \xer_ca$95 }
+ assign \xer_ca_ok$86 1'0
+ assign { \xer_ca_ok$86 \output_xer_ca } { \xer_ca_ok$88 \xer_ca$87 }
sync init
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621"
- wire width 1 \p_valid_i$97
- process $group_73
- assign \p_valid_i$97 1'0
- assign \p_valid_i$97 \p_valid_i
+ wire width 1 \p_valid_i$89
+ process $group_67
+ assign \p_valid_i$89 1'0
+ assign \p_valid_i$89 \p_valid_i
sync init
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619"
wire width 1 \n_i_rdy_data
- process $group_74
+ process $group_68
assign \n_i_rdy_data 1'0
assign \n_i_rdy_data \n_ready_i
sync init
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620"
wire width 1 \p_valid_i_p_ready_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624"
- wire width 1 $98
+ wire width 1 $90
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624"
- cell $and $99
+ cell $and $91
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \p_valid_i$97
+ connect \A \p_valid_i$89
connect \B \p_ready_o
- connect \Y $98
+ connect \Y $90
end
- process $group_75
+ process $group_69
assign \p_valid_i_p_ready_o 1'0
- assign \p_valid_i_p_ready_o $98
+ assign \p_valid_i_p_ready_o $90
sync init
end
- attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
- wire width 2 \muxid$100
- process $group_76
- assign \muxid$100 2'00
- assign \muxid$100 \output_muxid$66
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+ wire width 2 \muxid$92
+ process $group_70
+ assign \muxid$92 2'00
+ assign \muxid$92 \output_muxid$60
sync init
end
- attribute \enum_base_type "InternalOp"
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 7 \op__insn_type$101
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 7 \op__insn_type$93
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00000000010 "ALU"
attribute \enum_value_00100000000 "MUL"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 11 \op__fn_unit$102
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 64 \op__imm_data__imm$103
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 \op__imm_data__imm_ok$104
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 \op__lk$105
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 \op__rc__rc$106
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 \op__rc__rc_ok$107
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 \op__oe__oe$108
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 \op__oe__oe_ok$109
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 \op__invert_a$110
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 \op__zero_a$111
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 11 \op__fn_unit$94
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 \op__imm_data__imm$95
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__imm_data__imm_ok$96
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__rc__rc$97
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__rc__rc_ok$98
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__oe__oe$99
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__oe__oe_ok$100
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__invert_a$101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__zero_a$102
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 2 \op__input_carry$112
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 \op__invert_out$113
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 3 \op__write_cr__data$114
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 \op__write_cr__ok$115
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 \op__output_carry$116
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 \op__is_32bit$117
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 \op__is_signed$118
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 4 \op__data_len$119
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 32 \op__insn$120
- process $group_77
- assign \op__insn_type$101 7'0000000
- assign \op__fn_unit$102 11'00000000000
- assign \op__imm_data__imm$103 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \op__imm_data__imm_ok$104 1'0
- assign \op__lk$105 1'0
- assign \op__rc__rc$106 1'0
- assign \op__rc__rc_ok$107 1'0
- assign \op__oe__oe$108 1'0
- assign \op__oe__oe_ok$109 1'0
- assign \op__invert_a$110 1'0
- assign \op__zero_a$111 1'0
- assign \op__input_carry$112 2'00
- assign \op__invert_out$113 1'0
- assign \op__write_cr__data$114 3'000
- assign \op__write_cr__ok$115 1'0
- assign \op__output_carry$116 1'0
- assign \op__is_32bit$117 1'0
- assign \op__is_signed$118 1'0
- assign \op__data_len$119 4'0000
- assign \op__insn$120 32'00000000000000000000000000000000
- assign { \op__insn$120 \op__data_len$119 \op__is_signed$118 \op__is_32bit$117 \op__output_carry$116 { \op__write_cr__ok$115 \op__write_cr__data$114 } \op__invert_out$113 \op__input_carry$112 \op__zero_a$111 \op__invert_a$110 { \op__oe__oe_ok$109 \op__oe__oe$108 } { \op__rc__rc_ok$107 \op__rc__rc$106 } \op__lk$105 { \op__imm_data__imm_ok$104 \op__imm_data__imm$103 } \op__fn_unit$102 \op__insn_type$101 } { \output_op__insn$86 \output_op__data_len$85 \output_op__is_signed$84 \output_op__is_32bit$83 \output_op__output_carry$82 { \output_op__write_cr__ok$81 \output_op__write_cr__data$80 } \output_op__invert_out$79 \output_op__input_carry$78 \output_op__zero_a$77 \output_op__invert_a$76 { \output_op__oe__oe_ok$75 \output_op__oe__oe$74 } { \output_op__rc__rc_ok$73 \output_op__rc__rc$72 } \output_op__lk$71 { \output_op__imm_data__imm_ok$70 \output_op__imm_data__imm$69 } \output_op__fn_unit$68 \output_op__insn_type$67 }
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 \o$121
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 \o_ok$122
- process $group_97
- assign \o$121 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \o_ok$122 1'0
- assign { \o_ok$122 \o$121 } { \output_o_ok$88 \output_o$87 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 2 \op__input_carry$103
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__invert_out$104
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__write_cr0$105
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__output_carry$106
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__is_32bit$107
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__is_signed$108
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 4 \op__data_len$109
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 \op__insn$110
+ process $group_71
+ assign \op__insn_type$93 7'0000000
+ assign \op__fn_unit$94 11'00000000000
+ assign \op__imm_data__imm$95 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \op__imm_data__imm_ok$96 1'0
+ assign \op__rc__rc$97 1'0
+ assign \op__rc__rc_ok$98 1'0
+ assign \op__oe__oe$99 1'0
+ assign \op__oe__oe_ok$100 1'0
+ assign \op__invert_a$101 1'0
+ assign \op__zero_a$102 1'0
+ assign \op__input_carry$103 2'00
+ assign \op__invert_out$104 1'0
+ assign \op__write_cr0$105 1'0
+ assign \op__output_carry$106 1'0
+ assign \op__is_32bit$107 1'0
+ assign \op__is_signed$108 1'0
+ assign \op__data_len$109 4'0000
+ assign \op__insn$110 32'00000000000000000000000000000000
+ assign { \op__insn$110 \op__data_len$109 \op__is_signed$108 \op__is_32bit$107 \op__output_carry$106 \op__write_cr0$105 \op__invert_out$104 \op__input_carry$103 \op__zero_a$102 \op__invert_a$101 { \op__oe__oe_ok$100 \op__oe__oe$99 } { \op__rc__rc_ok$98 \op__rc__rc$97 } { \op__imm_data__imm_ok$96 \op__imm_data__imm$95 } \op__fn_unit$94 \op__insn_type$93 } { \output_op__insn$78 \output_op__data_len$77 \output_op__is_signed$76 \output_op__is_32bit$75 \output_op__output_carry$74 \output_op__write_cr0$73 \output_op__invert_out$72 \output_op__input_carry$71 \output_op__zero_a$70 \output_op__invert_a$69 { \output_op__oe__oe_ok$68 \output_op__oe__oe$67 } { \output_op__rc__rc_ok$66 \output_op__rc__rc$65 } { \output_op__imm_data__imm_ok$64 \output_op__imm_data__imm$63 } \output_op__fn_unit$62 \output_op__insn_type$61 }
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 64 \o$111
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 \o_ok$112
+ process $group_89
+ assign \o$111 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \o_ok$112 1'0
+ assign { \o_ok$112 \o$111 } { \output_o_ok$80 \output_o$79 }
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 4 \cr_a$123
+ wire width 4 \cr_a$113
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 \cr_a_ok$124
- process $group_99
- assign \cr_a$123 4'0000
- assign \cr_a_ok$124 1'0
- assign { \cr_a_ok$124 \cr_a$123 } { \output_cr_a_ok \output_cr_a$89 }
+ wire width 1 \cr_a_ok$114
+ process $group_91
+ assign \cr_a$113 4'0000
+ assign \cr_a_ok$114 1'0
+ assign { \cr_a_ok$114 \cr_a$113 } { \output_cr_a_ok \output_cr_a$81 }
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 2 \xer_ca$125
+ wire width 2 \xer_ca$115
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 \xer_ca_ok$126
- process $group_101
- assign \xer_ca$125 2'00
- assign \xer_ca_ok$126 1'0
- assign { \xer_ca_ok$126 \xer_ca$125 } { \output_xer_ca_ok \output_xer_ca$90 }
+ wire width 1 \xer_ca_ok$116
+ process $group_93
+ assign \xer_ca$115 2'00
+ assign \xer_ca_ok$116 1'0
+ assign { \xer_ca_ok$116 \xer_ca$115 } { \output_xer_ca_ok \output_xer_ca$82 }
sync init
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615"
wire width 1 \r_busy
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615"
wire width 1 \r_busy$next
- process $group_103
+ process $group_95
assign \r_busy$next \r_busy
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
switch { \n_i_rdy_data \p_valid_i_p_ready_o }
sync posedge \clk
update \r_busy \r_busy$next
end
- process $group_104
+ process $group_96
assign \muxid$1$next \muxid$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
switch { \n_i_rdy_data \p_valid_i_p_ready_o }
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
case 2'-1
- assign \muxid$1$next \muxid$100
+ assign \muxid$1$next \muxid$92
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
case 2'1-
- assign \muxid$1$next \muxid$100
+ assign \muxid$1$next \muxid$92
end
sync init
update \muxid$1 2'00
sync posedge \clk
update \muxid$1 \muxid$1$next
end
- process $group_105
+ process $group_97
assign \op__insn_type$2$next \op__insn_type$2
assign \op__fn_unit$3$next \op__fn_unit$3
assign \op__imm_data__imm$4$next \op__imm_data__imm$4
assign \op__imm_data__imm_ok$5$next \op__imm_data__imm_ok$5
- assign \op__lk$6$next \op__lk$6
- assign \op__rc__rc$7$next \op__rc__rc$7
- assign \op__rc__rc_ok$8$next \op__rc__rc_ok$8
- assign \op__oe__oe$9$next \op__oe__oe$9
- assign \op__oe__oe_ok$10$next \op__oe__oe_ok$10
- assign \op__invert_a$11$next \op__invert_a$11
- assign \op__zero_a$12$next \op__zero_a$12
- assign \op__input_carry$13$next \op__input_carry$13
- assign \op__invert_out$14$next \op__invert_out$14
- assign \op__write_cr__data$15$next \op__write_cr__data$15
- assign \op__write_cr__ok$16$next \op__write_cr__ok$16
- assign \op__output_carry$17$next \op__output_carry$17
- assign \op__is_32bit$18$next \op__is_32bit$18
- assign \op__is_signed$19$next \op__is_signed$19
- assign \op__data_len$20$next \op__data_len$20
- assign \op__insn$21$next \op__insn$21
+ assign \op__rc__rc$6$next \op__rc__rc$6
+ assign \op__rc__rc_ok$7$next \op__rc__rc_ok$7
+ assign \op__oe__oe$8$next \op__oe__oe$8
+ assign \op__oe__oe_ok$9$next \op__oe__oe_ok$9
+ assign \op__invert_a$10$next \op__invert_a$10
+ assign \op__zero_a$11$next \op__zero_a$11
+ assign \op__input_carry$12$next \op__input_carry$12
+ assign \op__invert_out$13$next \op__invert_out$13
+ assign \op__write_cr0$14$next \op__write_cr0$14
+ assign \op__output_carry$15$next \op__output_carry$15
+ assign \op__is_32bit$16$next \op__is_32bit$16
+ assign \op__is_signed$17$next \op__is_signed$17
+ assign \op__data_len$18$next \op__data_len$18
+ assign \op__insn$19$next \op__insn$19
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
switch { \n_i_rdy_data \p_valid_i_p_ready_o }
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
case 2'-1
- assign { \op__insn$21$next \op__data_len$20$next \op__is_signed$19$next \op__is_32bit$18$next \op__output_carry$17$next { \op__write_cr__ok$16$next \op__write_cr__data$15$next } \op__invert_out$14$next \op__input_carry$13$next \op__zero_a$12$next \op__invert_a$11$next { \op__oe__oe_ok$10$next \op__oe__oe$9$next } { \op__rc__rc_ok$8$next \op__rc__rc$7$next } \op__lk$6$next { \op__imm_data__imm_ok$5$next \op__imm_data__imm$4$next } \op__fn_unit$3$next \op__insn_type$2$next } { \op__insn$120 \op__data_len$119 \op__is_signed$118 \op__is_32bit$117 \op__output_carry$116 { \op__write_cr__ok$115 \op__write_cr__data$114 } \op__invert_out$113 \op__input_carry$112 \op__zero_a$111 \op__invert_a$110 { \op__oe__oe_ok$109 \op__oe__oe$108 } { \op__rc__rc_ok$107 \op__rc__rc$106 } \op__lk$105 { \op__imm_data__imm_ok$104 \op__imm_data__imm$103 } \op__fn_unit$102 \op__insn_type$101 }
+ assign { \op__insn$19$next \op__data_len$18$next \op__is_signed$17$next \op__is_32bit$16$next \op__output_carry$15$next \op__write_cr0$14$next \op__invert_out$13$next \op__input_carry$12$next \op__zero_a$11$next \op__invert_a$10$next { \op__oe__oe_ok$9$next \op__oe__oe$8$next } { \op__rc__rc_ok$7$next \op__rc__rc$6$next } { \op__imm_data__imm_ok$5$next \op__imm_data__imm$4$next } \op__fn_unit$3$next \op__insn_type$2$next } { \op__insn$110 \op__data_len$109 \op__is_signed$108 \op__is_32bit$107 \op__output_carry$106 \op__write_cr0$105 \op__invert_out$104 \op__input_carry$103 \op__zero_a$102 \op__invert_a$101 { \op__oe__oe_ok$100 \op__oe__oe$99 } { \op__rc__rc_ok$98 \op__rc__rc$97 } { \op__imm_data__imm_ok$96 \op__imm_data__imm$95 } \op__fn_unit$94 \op__insn_type$93 }
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
case 2'1-
- assign { \op__insn$21$next \op__data_len$20$next \op__is_signed$19$next \op__is_32bit$18$next \op__output_carry$17$next { \op__write_cr__ok$16$next \op__write_cr__data$15$next } \op__invert_out$14$next \op__input_carry$13$next \op__zero_a$12$next \op__invert_a$11$next { \op__oe__oe_ok$10$next \op__oe__oe$9$next } { \op__rc__rc_ok$8$next \op__rc__rc$7$next } \op__lk$6$next { \op__imm_data__imm_ok$5$next \op__imm_data__imm$4$next } \op__fn_unit$3$next \op__insn_type$2$next } { \op__insn$120 \op__data_len$119 \op__is_signed$118 \op__is_32bit$117 \op__output_carry$116 { \op__write_cr__ok$115 \op__write_cr__data$114 } \op__invert_out$113 \op__input_carry$112 \op__zero_a$111 \op__invert_a$110 { \op__oe__oe_ok$109 \op__oe__oe$108 } { \op__rc__rc_ok$107 \op__rc__rc$106 } \op__lk$105 { \op__imm_data__imm_ok$104 \op__imm_data__imm$103 } \op__fn_unit$102 \op__insn_type$101 }
+ assign { \op__insn$19$next \op__data_len$18$next \op__is_signed$17$next \op__is_32bit$16$next \op__output_carry$15$next \op__write_cr0$14$next \op__invert_out$13$next \op__input_carry$12$next \op__zero_a$11$next \op__invert_a$10$next { \op__oe__oe_ok$9$next \op__oe__oe$8$next } { \op__rc__rc_ok$7$next \op__rc__rc$6$next } { \op__imm_data__imm_ok$5$next \op__imm_data__imm$4$next } \op__fn_unit$3$next \op__insn_type$2$next } { \op__insn$110 \op__data_len$109 \op__is_signed$108 \op__is_32bit$107 \op__output_carry$106 \op__write_cr0$105 \op__invert_out$104 \op__input_carry$103 \op__zero_a$102 \op__invert_a$101 { \op__oe__oe_ok$100 \op__oe__oe$99 } { \op__rc__rc_ok$98 \op__rc__rc$97 } { \op__imm_data__imm_ok$96 \op__imm_data__imm$95 } \op__fn_unit$94 \op__insn_type$93 }
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \op__imm_data__imm$4$next 64'0000000000000000000000000000000000000000000000000000000000000000
assign \op__imm_data__imm_ok$5$next 1'0
- assign \op__rc__rc$7$next 1'0
- assign \op__rc__rc_ok$8$next 1'0
- assign \op__oe__oe$9$next 1'0
- assign \op__oe__oe_ok$10$next 1'0
- assign \op__write_cr__data$15$next 3'000
- assign \op__write_cr__ok$16$next 1'0
- assign \op__insn$21$next 32'00000000000000000000000000000000
+ assign \op__rc__rc$6$next 1'0
+ assign \op__rc__rc_ok$7$next 1'0
+ assign \op__oe__oe$8$next 1'0
+ assign \op__oe__oe_ok$9$next 1'0
end
sync init
update \op__insn_type$2 7'0000000
update \op__fn_unit$3 11'00000000000
update \op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000
update \op__imm_data__imm_ok$5 1'0
- update \op__lk$6 1'0
- update \op__rc__rc$7 1'0
- update \op__rc__rc_ok$8 1'0
- update \op__oe__oe$9 1'0
- update \op__oe__oe_ok$10 1'0
- update \op__invert_a$11 1'0
- update \op__zero_a$12 1'0
- update \op__input_carry$13 2'00
- update \op__invert_out$14 1'0
- update \op__write_cr__data$15 3'000
- update \op__write_cr__ok$16 1'0
- update \op__output_carry$17 1'0
- update \op__is_32bit$18 1'0
- update \op__is_signed$19 1'0
- update \op__data_len$20 4'0000
- update \op__insn$21 32'00000000000000000000000000000000
+ update \op__rc__rc$6 1'0
+ update \op__rc__rc_ok$7 1'0
+ update \op__oe__oe$8 1'0
+ update \op__oe__oe_ok$9 1'0
+ update \op__invert_a$10 1'0
+ update \op__zero_a$11 1'0
+ update \op__input_carry$12 2'00
+ update \op__invert_out$13 1'0
+ update \op__write_cr0$14 1'0
+ update \op__output_carry$15 1'0
+ update \op__is_32bit$16 1'0
+ update \op__is_signed$17 1'0
+ update \op__data_len$18 4'0000
+ update \op__insn$19 32'00000000000000000000000000000000
sync posedge \clk
update \op__insn_type$2 \op__insn_type$2$next
update \op__fn_unit$3 \op__fn_unit$3$next
update \op__imm_data__imm$4 \op__imm_data__imm$4$next
update \op__imm_data__imm_ok$5 \op__imm_data__imm_ok$5$next
- update \op__lk$6 \op__lk$6$next
- update \op__rc__rc$7 \op__rc__rc$7$next
- update \op__rc__rc_ok$8 \op__rc__rc_ok$8$next
- update \op__oe__oe$9 \op__oe__oe$9$next
- update \op__oe__oe_ok$10 \op__oe__oe_ok$10$next
- update \op__invert_a$11 \op__invert_a$11$next
- update \op__zero_a$12 \op__zero_a$12$next
- update \op__input_carry$13 \op__input_carry$13$next
- update \op__invert_out$14 \op__invert_out$14$next
- update \op__write_cr__data$15 \op__write_cr__data$15$next
- update \op__write_cr__ok$16 \op__write_cr__ok$16$next
- update \op__output_carry$17 \op__output_carry$17$next
- update \op__is_32bit$18 \op__is_32bit$18$next
- update \op__is_signed$19 \op__is_signed$19$next
- update \op__data_len$20 \op__data_len$20$next
- update \op__insn$21 \op__insn$21$next
+ update \op__rc__rc$6 \op__rc__rc$6$next
+ update \op__rc__rc_ok$7 \op__rc__rc_ok$7$next
+ update \op__oe__oe$8 \op__oe__oe$8$next
+ update \op__oe__oe_ok$9 \op__oe__oe_ok$9$next
+ update \op__invert_a$10 \op__invert_a$10$next
+ update \op__zero_a$11 \op__zero_a$11$next
+ update \op__input_carry$12 \op__input_carry$12$next
+ update \op__invert_out$13 \op__invert_out$13$next
+ update \op__write_cr0$14 \op__write_cr0$14$next
+ update \op__output_carry$15 \op__output_carry$15$next
+ update \op__is_32bit$16 \op__is_32bit$16$next
+ update \op__is_signed$17 \op__is_signed$17$next
+ update \op__data_len$18 \op__data_len$18$next
+ update \op__insn$19 \op__insn$19$next
end
- process $group_125
+ process $group_115
assign \o$next \o
assign \o_ok$next \o_ok
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
switch { \n_i_rdy_data \p_valid_i_p_ready_o }
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
case 2'-1
- assign { \o_ok$next \o$next } { \o_ok$122 \o$121 }
+ assign { \o_ok$next \o$next } { \o_ok$112 \o$111 }
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
case 2'1-
- assign { \o_ok$next \o$next } { \o_ok$122 \o$121 }
+ assign { \o_ok$next \o$next } { \o_ok$112 \o$111 }
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
update \o \o$next
update \o_ok \o_ok$next
end
- process $group_127
+ process $group_117
assign \cr_a$next \cr_a
assign \cr_a_ok$next \cr_a_ok
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
switch { \n_i_rdy_data \p_valid_i_p_ready_o }
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
case 2'-1
- assign { \cr_a_ok$next \cr_a$next } { \cr_a_ok$124 \cr_a$123 }
+ assign { \cr_a_ok$next \cr_a$next } { \cr_a_ok$114 \cr_a$113 }
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
case 2'1-
- assign { \cr_a_ok$next \cr_a$next } { \cr_a_ok$124 \cr_a$123 }
+ assign { \cr_a_ok$next \cr_a$next } { \cr_a_ok$114 \cr_a$113 }
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
update \cr_a \cr_a$next
update \cr_a_ok \cr_a_ok$next
end
- process $group_129
+ process $group_119
assign \xer_ca$next \xer_ca
assign \xer_ca_ok$next \xer_ca_ok
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
switch { \n_i_rdy_data \p_valid_i_p_ready_o }
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
case 2'-1
- assign { \xer_ca_ok$next \xer_ca$next } { \xer_ca_ok$126 \xer_ca$125 }
+ assign { \xer_ca_ok$next \xer_ca$next } { \xer_ca_ok$116 \xer_ca$115 }
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
case 2'1-
- assign { \xer_ca_ok$next \xer_ca$next } { \xer_ca_ok$126 \xer_ca$125 }
+ assign { \xer_ca_ok$next \xer_ca$next } { \xer_ca_ok$116 \xer_ca$115 }
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
update \xer_ca \xer_ca$next
update \xer_ca_ok \xer_ca_ok$next
end
- process $group_131
+ process $group_121
assign \n_valid_o 1'0
assign \n_valid_o \r_busy
sync init
end
- process $group_132
+ process $group_122
assign \p_ready_o 1'0
assign \p_ready_o \n_i_rdy_data
sync init
end
- connect \cr_a$92 4'0000
- connect \cr_a_ok$93 1'0
- connect \xer_ca$95 2'00
- connect \xer_ca_ok$96 1'0
+ connect \cr_a$84 4'0000
+ connect \cr_a_ok$85 1'0
+ connect \xer_ca$87 2'00
+ connect \xer_ca_ok$88 1'0
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_logical0"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 2 \o_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 output 3 \o
+ wire width 1 output 3 \cr_a_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 4 \cr_a_ok
+ wire width 1 output 4 \xer_ca_ok
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
+ wire width 1 output 5 \n_valid_o
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
+ wire width 1 input 6 \n_ready_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 4 output 5 \cr_a
+ wire width 64 output 7 \o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 6 \xer_ca_ok
+ wire width 4 output 8 \cr_a
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 2 output 7 \xer_ca
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244"
- wire width 1 output 8 \n_valid_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245"
- wire width 1 input 9 \n_ready_i
- attribute \enum_base_type "InternalOp"
+ wire width 2 output 9 \xer_ca
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 7 input 10 \op__insn_type
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00100000000 "MUL"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 11 input 11 \op__fn_unit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 64 input 12 \op__imm_data__imm
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 input 13 \op__imm_data__imm_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 input 14 \op__lk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 input 15 \op__rc__rc
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 input 16 \op__rc__rc_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 input 17 \op__oe__oe
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 input 18 \op__oe__oe_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 input 19 \op__invert_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 input 20 \op__zero_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 14 \op__rc__rc
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 15 \op__rc__rc_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 16 \op__oe__oe
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 17 \op__oe__oe_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 18 \op__invert_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 19 \op__zero_a
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 2 input 21 \op__input_carry
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 input 22 \op__invert_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 3 input 23 \op__write_cr__data
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 input 24 \op__write_cr__ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 input 25 \op__output_carry
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 input 26 \op__is_32bit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 input 27 \op__is_signed
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 4 input 28 \op__data_len
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 32 input 29 \op__insn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
- wire width 64 input 30 \ra
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
- wire width 64 input 31 \rb
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151"
- wire width 1 input 32 \p_valid_i
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152"
- wire width 1 output 33 \p_ready_o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 2 input 20 \op__input_carry
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 21 \op__invert_out
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 22 \op__write_cr0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 23 \op__output_carry
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 24 \op__is_32bit
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 25 \op__is_signed
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 4 input 26 \op__data_len
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 input 27 \op__insn
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 64 input 28 \ra
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 64 input 29 \rb
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153"
+ wire width 1 input 30 \p_valid_i
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154"
+ wire width 1 output 31 \p_ready_o
cell \p$43 \p
connect \p_valid_i \p_valid_i
connect \p_ready_o \p_ready_o
connect \n_valid_o \n_valid_o
connect \n_ready_i \n_ready_i
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153"
wire width 1 \pipe_p_valid_i
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154"
wire width 1 \pipe_p_ready_o
- attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
wire width 2 \pipe_muxid
- attribute \enum_base_type "InternalOp"
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 7 \pipe_op__insn_type
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00100000000 "MUL"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 11 \pipe_op__fn_unit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 64 \pipe_op__imm_data__imm
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \pipe_op__imm_data__imm_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 \pipe_op__lk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \pipe_op__rc__rc
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \pipe_op__rc__rc_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \pipe_op__oe__oe
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \pipe_op__oe__oe_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \pipe_op__invert_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \pipe_op__zero_a
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 2 \pipe_op__input_carry
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \pipe_op__invert_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 3 \pipe_op__write_cr__data
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 \pipe_op__write_cr__ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \pipe_op__write_cr0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \pipe_op__output_carry
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \pipe_op__is_32bit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \pipe_op__is_signed
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 4 \pipe_op__data_len
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 32 \pipe_op__insn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
wire width 64 \pipe_ra
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
wire width 64 \pipe_rb
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
wire width 1 \pipe_n_valid_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
wire width 1 \pipe_n_ready_i
- attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
wire width 2 \pipe_muxid$1
- attribute \enum_base_type "InternalOp"
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 7 \pipe_op__insn_type$2
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00100000000 "MUL"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 11 \pipe_op__fn_unit$3
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 64 \pipe_op__imm_data__imm$4
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \pipe_op__imm_data__imm_ok$5
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 \pipe_op__lk$6
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 \pipe_op__rc__rc$7
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 \pipe_op__rc__rc_ok$8
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 \pipe_op__oe__oe$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 \pipe_op__oe__oe_ok$10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 \pipe_op__invert_a$11
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 \pipe_op__zero_a$12
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \pipe_op__rc__rc$6
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \pipe_op__rc__rc_ok$7
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \pipe_op__oe__oe$8
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \pipe_op__oe__oe_ok$9
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \pipe_op__invert_a$10
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \pipe_op__zero_a$11
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 2 \pipe_op__input_carry$13
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 \pipe_op__invert_out$14
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 3 \pipe_op__write_cr__data$15
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 \pipe_op__write_cr__ok$16
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 \pipe_op__output_carry$17
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 \pipe_op__is_32bit$18
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 \pipe_op__is_signed$19
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 4 \pipe_op__data_len$20
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 32 \pipe_op__insn$21
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 2 \pipe_op__input_carry$12
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \pipe_op__invert_out$13
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \pipe_op__write_cr0$14
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \pipe_op__output_carry$15
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \pipe_op__is_32bit$16
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \pipe_op__is_signed$17
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 4 \pipe_op__data_len$18
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 \pipe_op__insn$19
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 64 \pipe_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
connect \op__fn_unit \pipe_op__fn_unit
connect \op__imm_data__imm \pipe_op__imm_data__imm
connect \op__imm_data__imm_ok \pipe_op__imm_data__imm_ok
- connect \op__lk \pipe_op__lk
connect \op__rc__rc \pipe_op__rc__rc
connect \op__rc__rc_ok \pipe_op__rc__rc_ok
connect \op__oe__oe \pipe_op__oe__oe
connect \op__zero_a \pipe_op__zero_a
connect \op__input_carry \pipe_op__input_carry
connect \op__invert_out \pipe_op__invert_out
- connect \op__write_cr__data \pipe_op__write_cr__data
- connect \op__write_cr__ok \pipe_op__write_cr__ok
+ connect \op__write_cr0 \pipe_op__write_cr0
connect \op__output_carry \pipe_op__output_carry
connect \op__is_32bit \pipe_op__is_32bit
connect \op__is_signed \pipe_op__is_signed
connect \op__fn_unit$3 \pipe_op__fn_unit$3
connect \op__imm_data__imm$4 \pipe_op__imm_data__imm$4
connect \op__imm_data__imm_ok$5 \pipe_op__imm_data__imm_ok$5
- connect \op__lk$6 \pipe_op__lk$6
- connect \op__rc__rc$7 \pipe_op__rc__rc$7
- connect \op__rc__rc_ok$8 \pipe_op__rc__rc_ok$8
- connect \op__oe__oe$9 \pipe_op__oe__oe$9
- connect \op__oe__oe_ok$10 \pipe_op__oe__oe_ok$10
- connect \op__invert_a$11 \pipe_op__invert_a$11
- connect \op__zero_a$12 \pipe_op__zero_a$12
- connect \op__input_carry$13 \pipe_op__input_carry$13
- connect \op__invert_out$14 \pipe_op__invert_out$14
- connect \op__write_cr__data$15 \pipe_op__write_cr__data$15
- connect \op__write_cr__ok$16 \pipe_op__write_cr__ok$16
- connect \op__output_carry$17 \pipe_op__output_carry$17
- connect \op__is_32bit$18 \pipe_op__is_32bit$18
- connect \op__is_signed$19 \pipe_op__is_signed$19
- connect \op__data_len$20 \pipe_op__data_len$20
- connect \op__insn$21 \pipe_op__insn$21
+ connect \op__rc__rc$6 \pipe_op__rc__rc$6
+ connect \op__rc__rc_ok$7 \pipe_op__rc__rc_ok$7
+ connect \op__oe__oe$8 \pipe_op__oe__oe$8
+ connect \op__oe__oe_ok$9 \pipe_op__oe__oe_ok$9
+ connect \op__invert_a$10 \pipe_op__invert_a$10
+ connect \op__zero_a$11 \pipe_op__zero_a$11
+ connect \op__input_carry$12 \pipe_op__input_carry$12
+ connect \op__invert_out$13 \pipe_op__invert_out$13
+ connect \op__write_cr0$14 \pipe_op__write_cr0$14
+ connect \op__output_carry$15 \pipe_op__output_carry$15
+ connect \op__is_32bit$16 \pipe_op__is_32bit$16
+ connect \op__is_signed$17 \pipe_op__is_signed$17
+ connect \op__data_len$18 \pipe_op__data_len$18
+ connect \op__insn$19 \pipe_op__insn$19
connect \o \pipe_o
connect \o_ok \pipe_o_ok
connect \cr_a \pipe_cr_a
assign \p_ready_o \pipe_p_ready_o
sync init
end
- attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
wire width 2 \muxid
process $group_2
assign \pipe_muxid 2'00
assign \pipe_op__fn_unit 11'00000000000
assign \pipe_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
assign \pipe_op__imm_data__imm_ok 1'0
- assign \pipe_op__lk 1'0
assign \pipe_op__rc__rc 1'0
assign \pipe_op__rc__rc_ok 1'0
assign \pipe_op__oe__oe 1'0
assign \pipe_op__zero_a 1'0
assign \pipe_op__input_carry 2'00
assign \pipe_op__invert_out 1'0
- assign \pipe_op__write_cr__data 3'000
- assign \pipe_op__write_cr__ok 1'0
+ assign \pipe_op__write_cr0 1'0
assign \pipe_op__output_carry 1'0
assign \pipe_op__is_32bit 1'0
assign \pipe_op__is_signed 1'0
assign \pipe_op__data_len 4'0000
assign \pipe_op__insn 32'00000000000000000000000000000000
- assign { \pipe_op__insn \pipe_op__data_len \pipe_op__is_signed \pipe_op__is_32bit \pipe_op__output_carry { \pipe_op__write_cr__ok \pipe_op__write_cr__data } \pipe_op__invert_out \pipe_op__input_carry \pipe_op__zero_a \pipe_op__invert_a { \pipe_op__oe__oe_ok \pipe_op__oe__oe } { \pipe_op__rc__rc_ok \pipe_op__rc__rc } \pipe_op__lk { \pipe_op__imm_data__imm_ok \pipe_op__imm_data__imm } \pipe_op__fn_unit \pipe_op__insn_type } { \op__insn \op__data_len \op__is_signed \op__is_32bit \op__output_carry { \op__write_cr__ok \op__write_cr__data } \op__invert_out \op__input_carry \op__zero_a \op__invert_a { \op__oe__oe_ok \op__oe__oe } { \op__rc__rc_ok \op__rc__rc } \op__lk { \op__imm_data__imm_ok \op__imm_data__imm } \op__fn_unit \op__insn_type }
+ assign { \pipe_op__insn \pipe_op__data_len \pipe_op__is_signed \pipe_op__is_32bit \pipe_op__output_carry \pipe_op__write_cr0 \pipe_op__invert_out \pipe_op__input_carry \pipe_op__zero_a \pipe_op__invert_a { \pipe_op__oe__oe_ok \pipe_op__oe__oe } { \pipe_op__rc__rc_ok \pipe_op__rc__rc } { \pipe_op__imm_data__imm_ok \pipe_op__imm_data__imm } \pipe_op__fn_unit \pipe_op__insn_type } { \op__insn \op__data_len \op__is_signed \op__is_32bit \op__output_carry \op__write_cr0 \op__invert_out \op__input_carry \op__zero_a \op__invert_a { \op__oe__oe_ok \op__oe__oe } { \op__rc__rc_ok \op__rc__rc } { \op__imm_data__imm_ok \op__imm_data__imm } \op__fn_unit \op__insn_type }
sync init
end
- process $group_23
+ process $group_21
assign \pipe_ra 64'0000000000000000000000000000000000000000000000000000000000000000
assign \pipe_ra \ra
sync init
end
- process $group_24
+ process $group_22
assign \pipe_rb 64'0000000000000000000000000000000000000000000000000000000000000000
assign \pipe_rb \rb
sync init
end
- process $group_25
+ process $group_23
assign \n_valid_o 1'0
assign \n_valid_o \pipe_n_valid_o
sync init
end
- process $group_26
+ process $group_24
assign \pipe_n_ready_i 1'0
assign \pipe_n_ready_i \n_ready_i
sync init
end
- attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
- wire width 2 \muxid$22
- process $group_27
- assign \muxid$22 2'00
- assign \muxid$22 \pipe_muxid$1
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+ wire width 2 \muxid$20
+ process $group_25
+ assign \muxid$20 2'00
+ assign \muxid$20 \pipe_muxid$1
sync init
end
- attribute \enum_base_type "InternalOp"
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 7 \op__insn_type$23
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 7 \op__insn_type$21
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00000000010 "ALU"
attribute \enum_value_00100000000 "MUL"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 11 \op__fn_unit$24
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 64 \op__imm_data__imm$25
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 \op__imm_data__imm_ok$26
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 \op__lk$27
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 \op__rc__rc$28
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 \op__rc__rc_ok$29
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 \op__oe__oe$30
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 \op__oe__oe_ok$31
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 \op__invert_a$32
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 \op__zero_a$33
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 11 \op__fn_unit$22
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 \op__imm_data__imm$23
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__imm_data__imm_ok$24
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__rc__rc$25
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__rc__rc_ok$26
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__oe__oe$27
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__oe__oe_ok$28
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__invert_a$29
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__zero_a$30
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 2 \op__input_carry$34
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 \op__invert_out$35
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 3 \op__write_cr__data$36
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 \op__write_cr__ok$37
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 \op__output_carry$38
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 \op__is_32bit$39
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 \op__is_signed$40
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 4 \op__data_len$41
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 32 \op__insn$42
- process $group_28
- assign \op__insn_type$23 7'0000000
- assign \op__fn_unit$24 11'00000000000
- assign \op__imm_data__imm$25 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \op__imm_data__imm_ok$26 1'0
- assign \op__lk$27 1'0
- assign \op__rc__rc$28 1'0
- assign \op__rc__rc_ok$29 1'0
- assign \op__oe__oe$30 1'0
- assign \op__oe__oe_ok$31 1'0
- assign \op__invert_a$32 1'0
- assign \op__zero_a$33 1'0
- assign \op__input_carry$34 2'00
- assign \op__invert_out$35 1'0
- assign \op__write_cr__data$36 3'000
- assign \op__write_cr__ok$37 1'0
- assign \op__output_carry$38 1'0
- assign \op__is_32bit$39 1'0
- assign \op__is_signed$40 1'0
- assign \op__data_len$41 4'0000
- assign \op__insn$42 32'00000000000000000000000000000000
- assign { \op__insn$42 \op__data_len$41 \op__is_signed$40 \op__is_32bit$39 \op__output_carry$38 { \op__write_cr__ok$37 \op__write_cr__data$36 } \op__invert_out$35 \op__input_carry$34 \op__zero_a$33 \op__invert_a$32 { \op__oe__oe_ok$31 \op__oe__oe$30 } { \op__rc__rc_ok$29 \op__rc__rc$28 } \op__lk$27 { \op__imm_data__imm_ok$26 \op__imm_data__imm$25 } \op__fn_unit$24 \op__insn_type$23 } { \pipe_op__insn$21 \pipe_op__data_len$20 \pipe_op__is_signed$19 \pipe_op__is_32bit$18 \pipe_op__output_carry$17 { \pipe_op__write_cr__ok$16 \pipe_op__write_cr__data$15 } \pipe_op__invert_out$14 \pipe_op__input_carry$13 \pipe_op__zero_a$12 \pipe_op__invert_a$11 { \pipe_op__oe__oe_ok$10 \pipe_op__oe__oe$9 } { \pipe_op__rc__rc_ok$8 \pipe_op__rc__rc$7 } \pipe_op__lk$6 { \pipe_op__imm_data__imm_ok$5 \pipe_op__imm_data__imm$4 } \pipe_op__fn_unit$3 \pipe_op__insn_type$2 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 2 \op__input_carry$31
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__invert_out$32
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__write_cr0$33
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__output_carry$34
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__is_32bit$35
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__is_signed$36
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 4 \op__data_len$37
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 \op__insn$38
+ process $group_26
+ assign \op__insn_type$21 7'0000000
+ assign \op__fn_unit$22 11'00000000000
+ assign \op__imm_data__imm$23 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \op__imm_data__imm_ok$24 1'0
+ assign \op__rc__rc$25 1'0
+ assign \op__rc__rc_ok$26 1'0
+ assign \op__oe__oe$27 1'0
+ assign \op__oe__oe_ok$28 1'0
+ assign \op__invert_a$29 1'0
+ assign \op__zero_a$30 1'0
+ assign \op__input_carry$31 2'00
+ assign \op__invert_out$32 1'0
+ assign \op__write_cr0$33 1'0
+ assign \op__output_carry$34 1'0
+ assign \op__is_32bit$35 1'0
+ assign \op__is_signed$36 1'0
+ assign \op__data_len$37 4'0000
+ assign \op__insn$38 32'00000000000000000000000000000000
+ assign { \op__insn$38 \op__data_len$37 \op__is_signed$36 \op__is_32bit$35 \op__output_carry$34 \op__write_cr0$33 \op__invert_out$32 \op__input_carry$31 \op__zero_a$30 \op__invert_a$29 { \op__oe__oe_ok$28 \op__oe__oe$27 } { \op__rc__rc_ok$26 \op__rc__rc$25 } { \op__imm_data__imm_ok$24 \op__imm_data__imm$23 } \op__fn_unit$22 \op__insn_type$21 } { \pipe_op__insn$19 \pipe_op__data_len$18 \pipe_op__is_signed$17 \pipe_op__is_32bit$16 \pipe_op__output_carry$15 \pipe_op__write_cr0$14 \pipe_op__invert_out$13 \pipe_op__input_carry$12 \pipe_op__zero_a$11 \pipe_op__invert_a$10 { \pipe_op__oe__oe_ok$9 \pipe_op__oe__oe$8 } { \pipe_op__rc__rc_ok$7 \pipe_op__rc__rc$6 } { \pipe_op__imm_data__imm_ok$5 \pipe_op__imm_data__imm$4 } \pipe_op__fn_unit$3 \pipe_op__insn_type$2 }
sync init
end
- process $group_48
+ process $group_44
assign \o 64'0000000000000000000000000000000000000000000000000000000000000000
assign \o_ok 1'0
assign { \o_ok \o } { \pipe_o_ok \pipe_o }
sync init
end
- process $group_50
+ process $group_46
assign \cr_a 4'0000
assign \cr_a_ok 1'0
assign { \cr_a_ok \cr_a } { \pipe_cr_a_ok \pipe_cr_a }
sync init
end
- process $group_52
+ process $group_48
assign \xer_ca 2'00
assign \xer_ca_ok 1'0
assign { \xer_ca_ok \xer_ca } { \pipe_xer_ca_ok \pipe_xer_ca }
wire width 1 input 0 \rst
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
- attribute \enum_base_type "InternalOp"
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 7 input 2 \oper_i__insn_type
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00100000000 "MUL"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 11 input 3 \oper_i__fn_unit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 64 input 4 \oper_i__imm_data__imm
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 input 5 \oper_i__imm_data__imm_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 input 6 \oper_i__lk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 input 7 \oper_i__rc__rc
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 input 8 \oper_i__rc__rc_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 input 9 \oper_i__oe__oe
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 input 10 \oper_i__oe__oe_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 input 11 \oper_i__invert_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 input 12 \oper_i__zero_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 6 \oper_i__rc__rc
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 7 \oper_i__rc__rc_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 8 \oper_i__oe__oe
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 9 \oper_i__oe__oe_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 10 \oper_i__invert_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 11 \oper_i__zero_a
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 2 input 13 \oper_i__input_carry
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 input 14 \oper_i__invert_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 3 input 15 \oper_i__write_cr__data
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 input 16 \oper_i__write_cr__ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 input 17 \oper_i__output_carry
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 input 18 \oper_i__is_32bit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 input 19 \oper_i__is_signed
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 4 input 20 \oper_i__data_len
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 32 input 21 \oper_i__insn
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 2 input 12 \oper_i__input_carry
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 13 \oper_i__invert_out
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 14 \oper_i__write_cr0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 15 \oper_i__output_carry
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 16 \oper_i__is_32bit
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 17 \oper_i__is_signed
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 4 input 18 \oper_i__data_len
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 input 19 \oper_i__insn
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94"
- wire width 1 input 22 \issue_i
+ wire width 1 input 20 \issue_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
- wire width 1 output 23 \busy_o
+ wire width 1 output 21 \busy_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:92"
- wire width 2 input 24 \rdmaskn
+ wire width 2 input 22 \rdmaskn
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 2 output 25 \rd__rel
+ wire width 2 output 23 \rd__rel
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 2 input 26 \rd__go
+ wire width 2 input 24 \rd__go
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
- wire width 64 input 27 \src1_i
+ wire width 64 input 25 \src1_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
- wire width 64 input 28 \src2_i
+ wire width 64 input 26 \src2_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 29 \o_ok
+ wire width 1 output 27 \o_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 3 output 30 \wr__rel
+ wire width 3 output 28 \wr__rel
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 3 input 31 \wr__go
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 output 32 \o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 33 \cr_a_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 4 output 34 \cr_a
+ wire width 3 input 29 \wr__go
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
+ wire width 64 output 30 \dest1_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 35 \xer_ca_ok
+ wire width 1 output 31 \cr_a_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
+ wire width 4 output 32 \dest2_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 2 output 36 \xer_ca
+ wire width 1 output 33 \xer_ca_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
+ wire width 2 output 34 \dest3_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96"
- wire width 1 input 37 \go_die_i
+ wire width 1 input 35 \go_die_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
- wire width 1 input 38 \shadown_i
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
- wire width 64 output 39 \dest1_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244"
+ wire width 1 input 36 \shadown_i
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
wire width 1 \alu_logical0_n_valid_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
wire width 1 \alu_logical0_n_ready_i
- attribute \enum_base_type "InternalOp"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 64 \alu_logical0_o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 4 \alu_logical0_cr_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 2 \alu_logical0_xer_ca
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 7 \alu_logical0_op__insn_type
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00100000000 "MUL"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 11 \alu_logical0_op__fn_unit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 64 \alu_logical0_op__imm_data__imm
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \alu_logical0_op__imm_data__imm_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 \alu_logical0_op__lk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \alu_logical0_op__rc__rc
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \alu_logical0_op__rc__rc_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \alu_logical0_op__oe__oe
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \alu_logical0_op__oe__oe_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \alu_logical0_op__invert_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \alu_logical0_op__zero_a
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 2 \alu_logical0_op__input_carry
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \alu_logical0_op__invert_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 3 \alu_logical0_op__write_cr__data
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 \alu_logical0_op__write_cr__ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \alu_logical0_op__write_cr0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \alu_logical0_op__output_carry
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \alu_logical0_op__is_32bit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \alu_logical0_op__is_signed
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 4 \alu_logical0_op__data_len
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 32 \alu_logical0_op__insn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
wire width 64 \alu_logical0_ra
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
wire width 64 \alu_logical0_rb
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153"
wire width 1 \alu_logical0_p_valid_i
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154"
wire width 1 \alu_logical0_p_ready_o
cell \alu_logical0 \alu_logical0
connect \rst \rst
connect \clk \clk
connect \o_ok \o_ok
- connect \o \o
connect \cr_a_ok \cr_a_ok
- connect \cr_a \cr_a
connect \xer_ca_ok \xer_ca_ok
- connect \xer_ca \xer_ca
connect \n_valid_o \alu_logical0_n_valid_o
connect \n_ready_i \alu_logical0_n_ready_i
+ connect \o \alu_logical0_o
+ connect \cr_a \alu_logical0_cr_a
+ connect \xer_ca \alu_logical0_xer_ca
connect \op__insn_type \alu_logical0_op__insn_type
connect \op__fn_unit \alu_logical0_op__fn_unit
connect \op__imm_data__imm \alu_logical0_op__imm_data__imm
connect \op__imm_data__imm_ok \alu_logical0_op__imm_data__imm_ok
- connect \op__lk \alu_logical0_op__lk
connect \op__rc__rc \alu_logical0_op__rc__rc
connect \op__rc__rc_ok \alu_logical0_op__rc__rc_ok
connect \op__oe__oe \alu_logical0_op__oe__oe
connect \op__zero_a \alu_logical0_op__zero_a
connect \op__input_carry \alu_logical0_op__input_carry
connect \op__invert_out \alu_logical0_op__invert_out
- connect \op__write_cr__data \alu_logical0_op__write_cr__data
- connect \op__write_cr__ok \alu_logical0_op__write_cr__ok
+ connect \op__write_cr0 \alu_logical0_op__write_cr0
connect \op__output_carry \alu_logical0_op__output_carry
connect \op__is_32bit \alu_logical0_op__is_32bit
connect \op__is_signed \alu_logical0_op__is_signed
assign \req_l_r_req $67
sync init
end
- attribute \enum_base_type "InternalOp"
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 7 \oper_r__insn_type
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00100000000 "MUL"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 11 \oper_r__fn_unit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 64 \oper_r__imm_data__imm
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \oper_r__imm_data__imm_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 \oper_r__lk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \oper_r__rc__rc
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \oper_r__rc__rc_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \oper_r__oe__oe
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \oper_r__oe__oe_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \oper_r__invert_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \oper_r__zero_a
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 2 \oper_r__input_carry
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \oper_r__invert_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 3 \oper_r__write_cr__data
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 \oper_r__write_cr__ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \oper_r__write_cr0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \oper_r__output_carry
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \oper_r__is_32bit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \oper_r__is_signed
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 4 \oper_r__data_len
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 32 \oper_r__insn
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
wire width 7 \oper_l__insn_type
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
wire width 1 \oper_l__imm_data__imm_ok$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
- wire width 1 \oper_l__lk
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
- wire width 1 \oper_l__lk$next
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
wire width 1 \oper_l__rc__rc
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
wire width 1 \oper_l__rc__rc$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
wire width 1 \oper_l__invert_out$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
- wire width 3 \oper_l__write_cr__data
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
- wire width 3 \oper_l__write_cr__data$next
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
- wire width 1 \oper_l__write_cr__ok
+ wire width 1 \oper_l__write_cr0
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
- wire width 1 \oper_l__write_cr__ok$next
+ wire width 1 \oper_l__write_cr0$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
wire width 1 \oper_l__output_carry
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
wire width 32 \oper_l__insn$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
- wire width 136 $69
+ wire width 132 $69
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
cell $mux $70
- parameter \WIDTH 136
- connect \A { \oper_l__insn \oper_l__data_len \oper_l__is_signed \oper_l__is_32bit \oper_l__output_carry { \oper_l__write_cr__ok \oper_l__write_cr__data } \oper_l__invert_out \oper_l__input_carry \oper_l__zero_a \oper_l__invert_a { \oper_l__oe__oe_ok \oper_l__oe__oe } { \oper_l__rc__rc_ok \oper_l__rc__rc } \oper_l__lk { \oper_l__imm_data__imm_ok \oper_l__imm_data__imm } \oper_l__fn_unit \oper_l__insn_type }
- connect \B { \oper_i__insn \oper_i__data_len \oper_i__is_signed \oper_i__is_32bit \oper_i__output_carry { \oper_i__write_cr__ok \oper_i__write_cr__data } \oper_i__invert_out \oper_i__input_carry \oper_i__zero_a \oper_i__invert_a { \oper_i__oe__oe_ok \oper_i__oe__oe } { \oper_i__rc__rc_ok \oper_i__rc__rc } \oper_i__lk { \oper_i__imm_data__imm_ok \oper_i__imm_data__imm } \oper_i__fn_unit \oper_i__insn_type }
+ parameter \WIDTH 132
+ connect \A { \oper_l__insn \oper_l__data_len \oper_l__is_signed \oper_l__is_32bit \oper_l__output_carry \oper_l__write_cr0 \oper_l__invert_out \oper_l__input_carry \oper_l__zero_a \oper_l__invert_a { \oper_l__oe__oe_ok \oper_l__oe__oe } { \oper_l__rc__rc_ok \oper_l__rc__rc } { \oper_l__imm_data__imm_ok \oper_l__imm_data__imm } \oper_l__fn_unit \oper_l__insn_type }
+ connect \B { \oper_i__insn \oper_i__data_len \oper_i__is_signed \oper_i__is_32bit \oper_i__output_carry \oper_i__write_cr0 \oper_i__invert_out \oper_i__input_carry \oper_i__zero_a \oper_i__invert_a { \oper_i__oe__oe_ok \oper_i__oe__oe } { \oper_i__rc__rc_ok \oper_i__rc__rc } { \oper_i__imm_data__imm_ok \oper_i__imm_data__imm } \oper_i__fn_unit \oper_i__insn_type }
connect \S \issue_i
connect \Y $69
end
assign \oper_r__fn_unit 11'00000000000
assign \oper_r__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
assign \oper_r__imm_data__imm_ok 1'0
- assign \oper_r__lk 1'0
assign \oper_r__rc__rc 1'0
assign \oper_r__rc__rc_ok 1'0
assign \oper_r__oe__oe 1'0
assign \oper_r__zero_a 1'0
assign \oper_r__input_carry 2'00
assign \oper_r__invert_out 1'0
- assign \oper_r__write_cr__data 3'000
- assign \oper_r__write_cr__ok 1'0
+ assign \oper_r__write_cr0 1'0
assign \oper_r__output_carry 1'0
assign \oper_r__is_32bit 1'0
assign \oper_r__is_signed 1'0
assign \oper_r__data_len 4'0000
assign \oper_r__insn 32'00000000000000000000000000000000
- assign { \oper_r__insn \oper_r__data_len \oper_r__is_signed \oper_r__is_32bit \oper_r__output_carry { \oper_r__write_cr__ok \oper_r__write_cr__data } \oper_r__invert_out \oper_r__input_carry \oper_r__zero_a \oper_r__invert_a { \oper_r__oe__oe_ok \oper_r__oe__oe } { \oper_r__rc__rc_ok \oper_r__rc__rc } \oper_r__lk { \oper_r__imm_data__imm_ok \oper_r__imm_data__imm } \oper_r__fn_unit \oper_r__insn_type } $69
+ assign { \oper_r__insn \oper_r__data_len \oper_r__is_signed \oper_r__is_32bit \oper_r__output_carry \oper_r__write_cr0 \oper_r__invert_out \oper_r__input_carry \oper_r__zero_a \oper_r__invert_a { \oper_r__oe__oe_ok \oper_r__oe__oe } { \oper_r__rc__rc_ok \oper_r__rc__rc } { \oper_r__imm_data__imm_ok \oper_r__imm_data__imm } \oper_r__fn_unit \oper_r__insn_type } $69
sync init
end
- process $group_45
+ process $group_43
assign \oper_l__insn_type$next \oper_l__insn_type
assign \oper_l__fn_unit$next \oper_l__fn_unit
assign \oper_l__imm_data__imm$next \oper_l__imm_data__imm
assign \oper_l__imm_data__imm_ok$next \oper_l__imm_data__imm_ok
- assign \oper_l__lk$next \oper_l__lk
assign \oper_l__rc__rc$next \oper_l__rc__rc
assign \oper_l__rc__rc_ok$next \oper_l__rc__rc_ok
assign \oper_l__oe__oe$next \oper_l__oe__oe
assign \oper_l__zero_a$next \oper_l__zero_a
assign \oper_l__input_carry$next \oper_l__input_carry
assign \oper_l__invert_out$next \oper_l__invert_out
- assign \oper_l__write_cr__data$next \oper_l__write_cr__data
- assign \oper_l__write_cr__ok$next \oper_l__write_cr__ok
+ assign \oper_l__write_cr0$next \oper_l__write_cr0
assign \oper_l__output_carry$next \oper_l__output_carry
assign \oper_l__is_32bit$next \oper_l__is_32bit
assign \oper_l__is_signed$next \oper_l__is_signed
switch { \issue_i }
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
case 1'1
- assign { \oper_l__insn$next \oper_l__data_len$next \oper_l__is_signed$next \oper_l__is_32bit$next \oper_l__output_carry$next { \oper_l__write_cr__ok$next \oper_l__write_cr__data$next } \oper_l__invert_out$next \oper_l__input_carry$next \oper_l__zero_a$next \oper_l__invert_a$next { \oper_l__oe__oe_ok$next \oper_l__oe__oe$next } { \oper_l__rc__rc_ok$next \oper_l__rc__rc$next } \oper_l__lk$next { \oper_l__imm_data__imm_ok$next \oper_l__imm_data__imm$next } \oper_l__fn_unit$next \oper_l__insn_type$next } { \oper_i__insn \oper_i__data_len \oper_i__is_signed \oper_i__is_32bit \oper_i__output_carry { \oper_i__write_cr__ok \oper_i__write_cr__data } \oper_i__invert_out \oper_i__input_carry \oper_i__zero_a \oper_i__invert_a { \oper_i__oe__oe_ok \oper_i__oe__oe } { \oper_i__rc__rc_ok \oper_i__rc__rc } \oper_i__lk { \oper_i__imm_data__imm_ok \oper_i__imm_data__imm } \oper_i__fn_unit \oper_i__insn_type }
+ assign { \oper_l__insn$next \oper_l__data_len$next \oper_l__is_signed$next \oper_l__is_32bit$next \oper_l__output_carry$next \oper_l__write_cr0$next \oper_l__invert_out$next \oper_l__input_carry$next \oper_l__zero_a$next \oper_l__invert_a$next { \oper_l__oe__oe_ok$next \oper_l__oe__oe$next } { \oper_l__rc__rc_ok$next \oper_l__rc__rc$next } { \oper_l__imm_data__imm_ok$next \oper_l__imm_data__imm$next } \oper_l__fn_unit$next \oper_l__insn_type$next } { \oper_i__insn \oper_i__data_len \oper_i__is_signed \oper_i__is_32bit \oper_i__output_carry \oper_i__write_cr0 \oper_i__invert_out \oper_i__input_carry \oper_i__zero_a \oper_i__invert_a { \oper_i__oe__oe_ok \oper_i__oe__oe } { \oper_i__rc__rc_ok \oper_i__rc__rc } { \oper_i__imm_data__imm_ok \oper_i__imm_data__imm } \oper_i__fn_unit \oper_i__insn_type }
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
assign \oper_l__rc__rc_ok$next 1'0
assign \oper_l__oe__oe$next 1'0
assign \oper_l__oe__oe_ok$next 1'0
- assign \oper_l__write_cr__data$next 3'000
- assign \oper_l__write_cr__ok$next 1'0
- assign \oper_l__insn$next 32'00000000000000000000000000000000
end
sync init
update \oper_l__insn_type 7'0000000
update \oper_l__fn_unit 11'00000000000
update \oper_l__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
update \oper_l__imm_data__imm_ok 1'0
- update \oper_l__lk 1'0
update \oper_l__rc__rc 1'0
update \oper_l__rc__rc_ok 1'0
update \oper_l__oe__oe 1'0
update \oper_l__zero_a 1'0
update \oper_l__input_carry 2'00
update \oper_l__invert_out 1'0
- update \oper_l__write_cr__data 3'000
- update \oper_l__write_cr__ok 1'0
+ update \oper_l__write_cr0 1'0
update \oper_l__output_carry 1'0
update \oper_l__is_32bit 1'0
update \oper_l__is_signed 1'0
update \oper_l__fn_unit \oper_l__fn_unit$next
update \oper_l__imm_data__imm \oper_l__imm_data__imm$next
update \oper_l__imm_data__imm_ok \oper_l__imm_data__imm_ok$next
- update \oper_l__lk \oper_l__lk$next
update \oper_l__rc__rc \oper_l__rc__rc$next
update \oper_l__rc__rc_ok \oper_l__rc__rc_ok$next
update \oper_l__oe__oe \oper_l__oe__oe$next
update \oper_l__zero_a \oper_l__zero_a$next
update \oper_l__input_carry \oper_l__input_carry$next
update \oper_l__invert_out \oper_l__invert_out$next
- update \oper_l__write_cr__data \oper_l__write_cr__data$next
- update \oper_l__write_cr__ok \oper_l__write_cr__ok$next
+ update \oper_l__write_cr0 \oper_l__write_cr0$next
update \oper_l__output_carry \oper_l__output_carry$next
update \oper_l__is_32bit \oper_l__is_32bit$next
update \oper_l__is_signed \oper_l__is_signed$next
wire width 1 \data_r0_l__o_ok$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
wire width 65 $71
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:730"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744"
wire width 1 $72
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:730"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744"
cell $reduce_bool $73
parameter \A_SIGNED 0
parameter \A_WIDTH 3
cell $mux $74
parameter \WIDTH 65
connect \A { \data_r0_l__o_ok \data_r0_l__o }
- connect \B { \o_ok \o }
+ connect \B { \o_ok \alu_logical0_o }
connect \S $72
connect \Y $71
end
- process $group_65
+ process $group_61
assign \data_r0__o 64'0000000000000000000000000000000000000000000000000000000000000000
assign \data_r0__o_ok 1'0
assign { \data_r0__o_ok \data_r0__o } $71
sync init
end
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
wire width 1 $75
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
cell $reduce_bool $76
parameter \A_SIGNED 0
parameter \A_WIDTH 3
connect \A \alu_pulsem
connect \Y $75
end
- process $group_67
+ process $group_63
assign \data_r0_l__o$next \data_r0_l__o
assign \data_r0_l__o_ok$next \data_r0_l__o_ok
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
switch { $75 }
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
case 1'1
- assign { \data_r0_l__o_ok$next \data_r0_l__o$next } { \o_ok \o }
+ assign { \data_r0_l__o_ok$next \data_r0_l__o$next } { \o_ok \alu_logical0_o }
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
wire width 1 \data_r1_l__cr_a_ok$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
wire width 5 $77
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:730"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744"
wire width 1 $78
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:730"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744"
cell $reduce_bool $79
parameter \A_SIGNED 0
parameter \A_WIDTH 3
cell $mux $80
parameter \WIDTH 5
connect \A { \data_r1_l__cr_a_ok \data_r1_l__cr_a }
- connect \B { \cr_a_ok \cr_a }
+ connect \B { \cr_a_ok \alu_logical0_cr_a }
connect \S $78
connect \Y $77
end
- process $group_69
+ process $group_65
assign \data_r1__cr_a 4'0000
assign \data_r1__cr_a_ok 1'0
assign { \data_r1__cr_a_ok \data_r1__cr_a } $77
sync init
end
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
wire width 1 $81
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
cell $reduce_bool $82
parameter \A_SIGNED 0
parameter \A_WIDTH 3
connect \A \alu_pulsem
connect \Y $81
end
- process $group_71
+ process $group_67
assign \data_r1_l__cr_a$next \data_r1_l__cr_a
assign \data_r1_l__cr_a_ok$next \data_r1_l__cr_a_ok
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
switch { $81 }
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
case 1'1
- assign { \data_r1_l__cr_a_ok$next \data_r1_l__cr_a$next } { \cr_a_ok \cr_a }
+ assign { \data_r1_l__cr_a_ok$next \data_r1_l__cr_a$next } { \cr_a_ok \alu_logical0_cr_a }
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
wire width 1 \data_r2_l__xer_ca_ok$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
wire width 3 $83
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:730"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744"
wire width 1 $84
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:730"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744"
cell $reduce_bool $85
parameter \A_SIGNED 0
parameter \A_WIDTH 3
cell $mux $86
parameter \WIDTH 3
connect \A { \data_r2_l__xer_ca_ok \data_r2_l__xer_ca }
- connect \B { \xer_ca_ok \xer_ca }
+ connect \B { \xer_ca_ok \alu_logical0_xer_ca }
connect \S $84
connect \Y $83
end
- process $group_73
+ process $group_69
assign \data_r2__xer_ca 2'00
assign \data_r2__xer_ca_ok 1'0
assign { \data_r2__xer_ca_ok \data_r2__xer_ca } $83
sync init
end
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
wire width 1 $87
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
cell $reduce_bool $88
parameter \A_SIGNED 0
parameter \A_WIDTH 3
connect \A \alu_pulsem
connect \Y $87
end
- process $group_75
+ process $group_71
assign \data_r2_l__xer_ca$next \data_r2_l__xer_ca
assign \data_r2_l__xer_ca_ok$next \data_r2_l__xer_ca_ok
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
switch { $87 }
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
case 1'1
- assign { \data_r2_l__xer_ca_ok$next \data_r2_l__xer_ca$next } { \xer_ca_ok \xer_ca }
+ assign { \data_r2_l__xer_ca_ok$next \data_r2_l__xer_ca$next } { \xer_ca_ok \alu_logical0_xer_ca }
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
update \data_r2_l__xer_ca \data_r2_l__xer_ca$next
update \data_r2_l__xer_ca_ok \data_r2_l__xer_ca_ok$next
end
- process $group_77
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+ wire width 1 $89
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+ cell $and $90
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \data_r0__o_ok
+ connect \B \busy_o
+ connect \Y $89
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+ wire width 1 $91
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+ cell $and $92
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \data_r1__cr_a_ok
+ connect \B \busy_o
+ connect \Y $91
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+ wire width 1 $93
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+ cell $and $94
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \data_r2__xer_ca_ok
+ connect \B \busy_o
+ connect \Y $93
+ end
+ process $group_73
assign \wrmask 3'000
- assign \wrmask { \data_r2__xer_ca_ok \data_r1__cr_a_ok \data_r0__o_ok }
+ assign \wrmask { $93 $91 $89 }
sync init
end
- process $group_78
+ process $group_74
assign \alu_logical0_op__insn_type 7'0000000
assign \alu_logical0_op__fn_unit 11'00000000000
assign \alu_logical0_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
assign \alu_logical0_op__imm_data__imm_ok 1'0
- assign \alu_logical0_op__lk 1'0
assign \alu_logical0_op__rc__rc 1'0
assign \alu_logical0_op__rc__rc_ok 1'0
assign \alu_logical0_op__oe__oe 1'0
assign \alu_logical0_op__zero_a 1'0
assign \alu_logical0_op__input_carry 2'00
assign \alu_logical0_op__invert_out 1'0
- assign \alu_logical0_op__write_cr__data 3'000
- assign \alu_logical0_op__write_cr__ok 1'0
+ assign \alu_logical0_op__write_cr0 1'0
assign \alu_logical0_op__output_carry 1'0
assign \alu_logical0_op__is_32bit 1'0
assign \alu_logical0_op__is_signed 1'0
assign \alu_logical0_op__data_len 4'0000
assign \alu_logical0_op__insn 32'00000000000000000000000000000000
- assign { \alu_logical0_op__insn \alu_logical0_op__data_len \alu_logical0_op__is_signed \alu_logical0_op__is_32bit \alu_logical0_op__output_carry { \alu_logical0_op__write_cr__ok \alu_logical0_op__write_cr__data } \alu_logical0_op__invert_out \alu_logical0_op__input_carry \alu_logical0_op__zero_a \alu_logical0_op__invert_a { \alu_logical0_op__oe__oe_ok \alu_logical0_op__oe__oe } { \alu_logical0_op__rc__rc_ok \alu_logical0_op__rc__rc } \alu_logical0_op__lk { \alu_logical0_op__imm_data__imm_ok \alu_logical0_op__imm_data__imm } \alu_logical0_op__fn_unit \alu_logical0_op__insn_type } { \oper_r__insn \oper_r__data_len \oper_r__is_signed \oper_r__is_32bit \oper_r__output_carry { \oper_r__write_cr__ok \oper_r__write_cr__data } \oper_r__invert_out \oper_r__input_carry \oper_r__zero_a \oper_r__invert_a { \oper_r__oe__oe_ok \oper_r__oe__oe } { \oper_r__rc__rc_ok \oper_r__rc__rc } \oper_r__lk { \oper_r__imm_data__imm_ok \oper_r__imm_data__imm } \oper_r__fn_unit \oper_r__insn_type }
+ assign { \alu_logical0_op__insn \alu_logical0_op__data_len \alu_logical0_op__is_signed \alu_logical0_op__is_32bit \alu_logical0_op__output_carry \alu_logical0_op__write_cr0 \alu_logical0_op__invert_out \alu_logical0_op__input_carry \alu_logical0_op__zero_a \alu_logical0_op__invert_a { \alu_logical0_op__oe__oe_ok \alu_logical0_op__oe__oe } { \alu_logical0_op__rc__rc_ok \alu_logical0_op__rc__rc } { \alu_logical0_op__imm_data__imm_ok \alu_logical0_op__imm_data__imm } \alu_logical0_op__fn_unit \alu_logical0_op__insn_type } { \oper_r__insn \oper_r__data_len \oper_r__is_signed \oper_r__is_32bit \oper_r__output_carry \oper_r__write_cr0 \oper_r__invert_out \oper_r__input_carry \oper_r__zero_a \oper_r__invert_a { \oper_r__oe__oe_ok \oper_r__oe__oe } { \oper_r__rc__rc_ok \oper_r__rc__rc } { \oper_r__imm_data__imm_ok \oper_r__imm_data__imm } \oper_r__fn_unit \oper_r__insn_type }
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:158"
wire width 1 \src_sel
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:159"
- wire width 1 $89
+ wire width 1 $95
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:159"
- cell $mux $90
+ cell $mux $96
parameter \WIDTH 1
connect \A \src_l_q_src [0]
connect \B \opc_l_q_opc
connect \S \oper_r__zero_a
- connect \Y $89
+ connect \Y $95
end
- process $group_98
+ process $group_92
assign \src_sel 1'0
- assign \src_sel $89
+ assign \src_sel $95
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:157"
wire width 64 \src_or_imm
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:160"
- wire width 64 $91
+ wire width 64 $97
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:160"
- cell $mux $92
+ cell $mux $98
parameter \WIDTH 64
connect \A \src1_i
connect \B 64'0000000000000000000000000000000000000000000000000000000000000000
connect \S \oper_r__zero_a
- connect \Y $91
+ connect \Y $97
end
- process $group_99
+ process $group_93
assign \src_or_imm 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \src_or_imm $91
+ assign \src_or_imm $97
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:158"
- wire width 1 \src_sel$93
+ wire width 1 \src_sel$99
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:159"
- wire width 1 $94
+ wire width 1 $100
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:159"
- cell $mux $95
+ cell $mux $101
parameter \WIDTH 1
connect \A \src_l_q_src [1]
connect \B \opc_l_q_opc
connect \S \oper_r__imm_data__imm_ok
- connect \Y $94
+ connect \Y $100
end
- process $group_100
- assign \src_sel$93 1'0
- assign \src_sel$93 $94
+ process $group_94
+ assign \src_sel$99 1'0
+ assign \src_sel$99 $100
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:157"
- wire width 64 \src_or_imm$96
+ wire width 64 \src_or_imm$102
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:160"
- wire width 64 $97
+ wire width 64 $103
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:160"
- cell $mux $98
+ cell $mux $104
parameter \WIDTH 64
connect \A \src2_i
connect \B \oper_r__imm_data__imm
connect \S \oper_r__imm_data__imm_ok
- connect \Y $97
+ connect \Y $103
end
- process $group_101
- assign \src_or_imm$96 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \src_or_imm$96 $97
+ process $group_95
+ assign \src_or_imm$102 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \src_or_imm$102 $103
sync init
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
wire width 64 \src_r0$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
- wire width 64 $99
+ wire width 64 $105
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
- cell $mux $100
+ cell $mux $106
parameter \WIDTH 64
connect \A \src_r0
connect \B \src_or_imm
connect \S \src_sel
- connect \Y $99
+ connect \Y $105
end
- process $group_102
+ process $group_96
assign \alu_logical0_ra 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \alu_logical0_ra $99
+ assign \alu_logical0_ra $105
sync init
end
- process $group_103
+ process $group_97
assign \src_r0$next \src_r0
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
switch { \src_sel }
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
wire width 64 \src_r1$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
- wire width 64 $101
+ wire width 64 $107
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
- cell $mux $102
+ cell $mux $108
parameter \WIDTH 64
connect \A \src_r1
- connect \B \src_or_imm$96
- connect \S \src_sel$93
- connect \Y $101
+ connect \B \src_or_imm$102
+ connect \S \src_sel$99
+ connect \Y $107
end
- process $group_104
+ process $group_98
assign \alu_logical0_rb 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \alu_logical0_rb $101
+ assign \alu_logical0_rb $107
sync init
end
- process $group_105
+ process $group_99
assign \src_r1$next \src_r1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
- switch { \src_sel$93 }
+ switch { \src_sel$99 }
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
case 1'1
- assign \src_r1$next \src_or_imm$96
+ assign \src_r1$next \src_or_imm$102
end
sync init
update \src_r1 64'0000000000000000000000000000000000000000000000000000000000000000
sync posedge \clk
update \src_r1 \src_r1$next
end
- process $group_106
+ process $group_100
assign \alu_logical0_p_valid_i 1'0
assign \alu_logical0_p_valid_i \alui_l_q_alui
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:321"
- wire width 1 $103
+ wire width 1 $109
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:321"
- cell $and $104
+ cell $and $110
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \alu_logical0_p_ready_o
connect \B \alui_l_q_alui
- connect \Y $103
+ connect \Y $109
end
- process $group_107
+ process $group_101
assign \alui_l_r_alui$next \alui_l_r_alui
- assign \alui_l_r_alui$next $103
+ assign \alui_l_r_alui$next $109
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
sync posedge \clk
update \alui_l_r_alui \alui_l_r_alui$next
end
- process $group_108
+ process $group_102
assign \alui_l_s_alui 1'0
assign \alui_l_s_alui \all_rd_pulse
sync init
end
- process $group_109
+ process $group_103
assign \alu_logical0_n_ready_i 1'0
assign \alu_logical0_n_ready_i \alu_l_q_alu
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:328"
- wire width 1 $105
+ wire width 1 $111
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:328"
- cell $and $106
+ cell $and $112
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \alu_logical0_n_valid_o
connect \B \alu_l_q_alu
- connect \Y $105
+ connect \Y $111
end
- process $group_110
+ process $group_104
assign \alu_l_r_alu$next \alu_l_r_alu
- assign \alu_l_r_alu$next $105
+ assign \alu_l_r_alu$next $111
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
sync posedge \clk
update \alu_l_r_alu \alu_l_r_alu$next
end
- process $group_111
+ process $group_105
assign \alu_l_s_alu 1'0
assign \alu_l_s_alu \all_rd_pulse
sync init
end
- process $group_112
+ process $group_106
assign \busy_o 1'0
assign \busy_o \opc_l_q_opc
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341"
- wire width 2 $107
+ wire width 2 $113
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341"
- cell $and $108
+ cell $and $114
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 2
connect \A \src_l_q_src
connect \B { \busy_o \busy_o }
- connect \Y $107
+ connect \Y $113
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:164"
- wire width 1 $109
+ wire width 1 $115
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:164"
- cell $not $110
+ cell $not $116
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \oper_r__zero_a
- connect \Y $109
+ connect \Y $115
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:164"
- wire width 1 $111
+ wire width 1 $117
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:164"
- cell $not $112
+ cell $not $118
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \oper_r__imm_data__imm_ok
- connect \Y $111
+ connect \Y $117
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341"
- wire width 2 $113
+ wire width 2 $119
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341"
- cell $and $114
+ cell $and $120
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \B_WIDTH 2
parameter \Y_WIDTH 2
- connect \A $107
- connect \B { $111 $109 }
- connect \Y $113
+ connect \A $113
+ connect \B { $117 $115 }
+ connect \Y $119
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341"
- wire width 2 $115
+ wire width 2 $121
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341"
- cell $not $116
+ cell $not $122
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \Y_WIDTH 2
connect \A \rdmaskn
- connect \Y $115
+ connect \Y $121
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341"
- wire width 2 $117
+ wire width 2 $123
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341"
- cell $and $118
+ cell $and $124
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \B_WIDTH 2
parameter \Y_WIDTH 2
- connect \A $113
- connect \B $115
- connect \Y $117
+ connect \A $119
+ connect \B $121
+ connect \Y $123
end
- process $group_113
+ process $group_107
assign \rd__rel 2'00
- assign \rd__rel $117
+ assign \rd__rel $123
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
- wire width 1 $119
+ wire width 1 $125
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
- cell $and $120
+ cell $and $126
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \busy_o
connect \B \shadown_i
- connect \Y $119
+ connect \Y $125
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
- wire width 1 $121
+ wire width 1 $127
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
- cell $and $122
+ cell $and $128
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \busy_o
connect \B \shadown_i
- connect \Y $121
+ connect \Y $127
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
- wire width 1 $123
+ wire width 1 $129
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
- cell $and $124
+ cell $and $130
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \busy_o
connect \B \shadown_i
- connect \Y $123
+ connect \Y $129
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:345"
- wire width 3 $125
+ wire width 3 $131
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:345"
- cell $and $126
+ cell $and $132
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \B_WIDTH 3
parameter \Y_WIDTH 3
connect \A \req_l_q_req
- connect \B { $119 $121 $123 }
- connect \Y $125
+ connect \B { $125 $127 $129 }
+ connect \Y $131
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:345"
- wire width 3 $127
+ wire width 3 $133
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:345"
- cell $and $128
+ cell $and $134
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \B_WIDTH 3
parameter \Y_WIDTH 3
- connect \A $125
+ connect \A $131
connect \B \wrmask
- connect \Y $127
+ connect \Y $133
end
- process $group_114
+ process $group_108
assign \wr__rel 3'000
- assign \wr__rel $127
+ assign \wr__rel $133
sync init
end
- process $group_115
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+ wire width 1 $135
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+ cell $and $136
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \wr__go [0]
+ connect \B \busy_o
+ connect \Y $135
+ end
+ process $group_109
assign \dest1_o 64'0000000000000000000000000000000000000000000000000000000000000000
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
- switch { \wr__go [0] }
+ switch { $135 }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
case 1'1
assign \dest1_o { \data_r0__o_ok \data_r0__o } [63:0]
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
- wire width 4 \dest2_o
- process $group_116
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+ wire width 1 $137
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+ cell $and $138
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \wr__go [1]
+ connect \B \busy_o
+ connect \Y $137
+ end
+ process $group_110
assign \dest2_o 4'0000
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
- switch { \wr__go [1] }
+ switch { $137 }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
case 1'1
assign \dest2_o { \data_r1__cr_a_ok \data_r1__cr_a } [3:0]
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
- wire width 2 \dest3_o
- process $group_117
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+ wire width 1 $139
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+ cell $and $140
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \wr__go [2]
+ connect \B \busy_o
+ connect \Y $139
+ end
+ process $group_111
assign \dest3_o 2'00
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
- switch { \wr__go [2] }
+ switch { $139 }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
case 1'1
assign \dest3_o { \data_r2__xer_ca_ok \data_r2__xer_ca } [1:0]
attribute \generator "nMigen"
attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.alu_spr0.p"
module \p$58
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153"
wire width 1 input 0 \p_valid_i
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154"
wire width 1 input 1 \p_ready_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:156"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158"
wire width 1 \trigger
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:203"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205"
wire width 1 $1
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:203"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205"
cell $and $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
attribute \generator "nMigen"
attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.alu_spr0.n"
module \n$59
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
wire width 1 input 0 \n_valid_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
wire width 1 input 1 \n_ready_i
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:249"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251"
wire width 1 \trigger
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:295"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:297"
wire width 1 $1
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:295"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:297"
cell $and $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
attribute \generator "nMigen"
attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.alu_spr0.pipe.p"
module \p$61
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153"
wire width 1 input 0 \p_valid_i
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154"
wire width 1 input 1 \p_ready_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:156"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158"
wire width 1 \trigger
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:203"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205"
wire width 1 $1
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:203"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205"
cell $and $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
attribute \generator "nMigen"
attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.alu_spr0.pipe.n"
module \n$62
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
wire width 1 input 0 \n_valid_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
wire width 1 input 1 \n_ready_i
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:249"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251"
wire width 1 \trigger
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:295"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:297"
wire width 1 $1
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:295"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:297"
cell $and $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
attribute \generator "nMigen"
attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.alu_spr0.pipe.spr_main"
module \spr_main
- attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
wire width 2 input 0 \muxid
- attribute \enum_base_type "InternalOp"
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20"
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 7 input 1 \op__insn_type
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00100000000 "MUL"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 11 input 2 \op__fn_unit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 32 input 3 \op__insn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 input 4 \op__is_32bit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
wire width 64 input 5 \ra
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
wire width 64 input 6 \fast1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
wire width 1 input 7 \xer_so
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
wire width 2 input 8 \xer_ov
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
wire width 2 input 9 \xer_ca
- attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
wire width 2 output 10 \muxid$1
- attribute \enum_base_type "InternalOp"
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20"
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 7 output 11 \op__insn_type$2
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00100000000 "MUL"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 11 output 12 \op__fn_unit$3
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 32 output 13 \op__insn$4
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 output 14 \op__is_32bit$5
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 64 output 15 \o
wire width 1 input 0 \rst
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153"
wire width 1 input 2 \p_valid_i
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154"
wire width 1 output 3 \p_ready_o
- attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
wire width 2 input 4 \muxid
- attribute \enum_base_type "InternalOp"
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20"
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 7 input 5 \op__insn_type
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00100000000 "MUL"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 11 input 6 \op__fn_unit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 32 input 7 \op__insn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 input 8 \op__is_32bit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
wire width 64 input 9 \ra
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
wire width 64 input 10 \spr1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
wire width 64 input 11 \fast1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
wire width 1 input 12 \xer_so
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
wire width 2 input 13 \xer_ov
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
wire width 2 input 14 \xer_ca
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
wire width 1 output 15 \n_valid_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
wire width 1 input 16 \n_ready_i
- attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
wire width 2 output 17 \muxid$1
- attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
wire width 2 \muxid$1$next
- attribute \enum_base_type "InternalOp"
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20"
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 7 output 18 \op__insn_type$2
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 7 \op__insn_type$2$next
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00100000000 "MUL"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 11 output 19 \op__fn_unit$3
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 11 \op__fn_unit$3$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 32 output 20 \op__insn$4
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 32 \op__insn$4$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 output 21 \op__is_32bit$5
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \op__is_32bit$5$next
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 64 output 22 \o
connect \n_valid_o \n_valid_o
connect \n_ready_i \n_ready_i
end
- attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
wire width 2 \spr_main_muxid
- attribute \enum_base_type "InternalOp"
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20"
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 7 \spr_main_op__insn_type
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00100000000 "MUL"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 11 \spr_main_op__fn_unit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 32 \spr_main_op__insn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \spr_main_op__is_32bit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
wire width 64 \spr_main_ra
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
wire width 64 \spr_main_fast1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
wire width 1 \spr_main_xer_so
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
wire width 2 \spr_main_xer_ov
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
wire width 2 \spr_main_xer_ca
- attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
wire width 2 \spr_main_muxid$11
- attribute \enum_base_type "InternalOp"
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20"
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 7 \spr_main_op__insn_type$12
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00100000000 "MUL"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 11 \spr_main_op__fn_unit$13
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 32 \spr_main_op__insn$14
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \spr_main_op__is_32bit$15
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 64 \spr_main_o
assign \spr_main_ra \ra
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
wire width 64 \spr1$20
process $group_6
assign \spr1$20 64'0000000000000000000000000000000000000000000000000000000000000000
assign \p_valid_i_p_ready_o $22
sync init
end
- attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
wire width 2 \muxid$24
process $group_14
assign \muxid$24 2'00
assign \muxid$24 \spr_main_muxid$11
sync init
end
- attribute \enum_base_type "InternalOp"
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20"
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 7 \op__insn_type$25
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00100000000 "MUL"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 11 \op__fn_unit$26
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 32 \op__insn$27
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \op__is_32bit$28
process $group_15
assign \op__insn_type$25 7'0000000
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 2 \o_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 output 3 \o
+ wire width 1 output 3 \xer_ca_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 4 \xer_ca_ok
+ wire width 1 output 4 \xer_ov_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 2 output 5 \xer_ca
+ wire width 1 output 5 \xer_so_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 6 \xer_ov_ok
+ wire width 1 output 6 \fast1_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 2 output 7 \xer_ov
+ wire width 1 output 7 \spr1_ok
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
+ wire width 1 output 8 \n_valid_o
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
+ wire width 1 input 9 \n_ready_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 8 \xer_so_ok
+ wire width 64 output 10 \o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 9 \xer_so
+ wire width 64 output 11 \spr1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 10 \fast1_ok
+ wire width 64 output 12 \fast1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 output 11 \fast1
+ wire width 1 output 13 \xer_so
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 12 \spr1_ok
+ wire width 2 output 14 \xer_ov
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 output 13 \spr1
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244"
- wire width 1 output 14 \n_valid_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245"
- wire width 1 input 15 \n_ready_i
- attribute \enum_base_type "InternalOp"
+ wire width 2 output 15 \xer_ca
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20"
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 7 input 16 \op__insn_type
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00100000000 "MUL"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 11 input 17 \op__fn_unit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 32 input 18 \op__insn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 input 19 \op__is_32bit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
wire width 64 input 20 \ra
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
wire width 64 input 21 \spr1$1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
wire width 64 input 22 \fast1$2
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
wire width 1 input 23 \xer_so$3
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
wire width 2 input 24 \xer_ov$4
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
wire width 2 input 25 \xer_ca$5
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153"
wire width 1 input 26 \p_valid_i
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154"
wire width 1 output 27 \p_ready_o
cell \p$58 \p
connect \p_valid_i \p_valid_i
connect \n_valid_o \n_valid_o
connect \n_ready_i \n_ready_i
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153"
wire width 1 \pipe_p_valid_i
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154"
wire width 1 \pipe_p_ready_o
- attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
wire width 2 \pipe_muxid
- attribute \enum_base_type "InternalOp"
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20"
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 7 \pipe_op__insn_type
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00100000000 "MUL"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 11 \pipe_op__fn_unit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 32 \pipe_op__insn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \pipe_op__is_32bit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
wire width 64 \pipe_ra
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
wire width 64 \pipe_spr1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
wire width 64 \pipe_fast1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
wire width 1 \pipe_xer_so
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
wire width 2 \pipe_xer_ov
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
wire width 2 \pipe_xer_ca
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
wire width 1 \pipe_n_valid_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
wire width 1 \pipe_n_ready_i
- attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
wire width 2 \pipe_muxid$6
- attribute \enum_base_type "InternalOp"
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20"
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 7 \pipe_op__insn_type$7
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00100000000 "MUL"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 11 \pipe_op__fn_unit$8
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 32 \pipe_op__insn$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \pipe_op__is_32bit$10
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 64 \pipe_o
assign \p_ready_o \pipe_p_ready_o
sync init
end
- attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
wire width 2 \muxid
process $group_2
assign \pipe_muxid 2'00
assign \pipe_n_ready_i \n_ready_i
sync init
end
- attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
wire width 2 \muxid$16
process $group_15
assign \muxid$16 2'00
assign \muxid$16 \pipe_muxid$6
sync init
end
- attribute \enum_base_type "InternalOp"
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20"
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 7 \op__insn_type$17
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00100000000 "MUL"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 11 \op__fn_unit$18
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 32 \op__insn$19
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \op__is_32bit$20
process $group_16
assign \op__insn_type$17 7'0000000
wire width 1 input 0 \rst
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
- attribute \enum_base_type "InternalOp"
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20"
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 7 input 2 \oper_i__insn_type
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00100000000 "MUL"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 11 input 3 \oper_i__fn_unit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 32 input 4 \oper_i__insn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 input 5 \oper_i__is_32bit
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94"
wire width 1 input 6 \issue_i
wire width 6 output 18 \wr__rel
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
wire width 6 input 19 \wr__go
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 output 20 \o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
+ wire width 64 output 20 \dest1_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 21 \xer_ca_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 2 output 22 \xer_ca
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
+ wire width 2 output 22 \dest6_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 23 \xer_ov_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 2 output 24 \xer_ov
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
+ wire width 2 output 24 \dest5_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 25 \xer_so_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 26 \xer_so
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
+ wire width 1 output 26 \dest4_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 27 \fast1_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 output 28 \fast1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
+ wire width 64 output 28 \dest3_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 29 \spr1_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 output 30 \spr1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
+ wire width 64 output 30 \dest2_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96"
wire width 1 input 31 \go_die_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
wire width 1 input 32 \shadown_i
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
- wire width 64 output 33 \dest1_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
wire width 1 \alu_spr0_n_valid_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
wire width 1 \alu_spr0_n_ready_i
- attribute \enum_base_type "InternalOp"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 64 \alu_spr0_o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 64 \alu_spr0_spr1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 64 \alu_spr0_fast1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 \alu_spr0_xer_so
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 2 \alu_spr0_xer_ov
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 2 \alu_spr0_xer_ca
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20"
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 7 \alu_spr0_op__insn_type
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00100000000 "MUL"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 11 \alu_spr0_op__fn_unit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 32 \alu_spr0_op__insn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \alu_spr0_op__is_32bit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
wire width 64 \alu_spr0_ra
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
- wire width 64 \alu_spr0_spr1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
- wire width 64 \alu_spr0_fast1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
- wire width 1 \alu_spr0_xer_so
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
- wire width 2 \alu_spr0_xer_ov
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
- wire width 2 \alu_spr0_xer_ca
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 64 \alu_spr0_spr1$1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 64 \alu_spr0_fast1$2
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 1 \alu_spr0_xer_so$3
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 2 \alu_spr0_xer_ov$4
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 2 \alu_spr0_xer_ca$5
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153"
wire width 1 \alu_spr0_p_valid_i
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154"
wire width 1 \alu_spr0_p_ready_o
cell \alu_spr0 \alu_spr0
connect \rst \rst
connect \clk \clk
connect \o_ok \o_ok
- connect \o \o
connect \xer_ca_ok \xer_ca_ok
- connect \xer_ca \xer_ca
connect \xer_ov_ok \xer_ov_ok
- connect \xer_ov \xer_ov
connect \xer_so_ok \xer_so_ok
- connect \xer_so \xer_so
connect \fast1_ok \fast1_ok
- connect \fast1 \fast1
connect \spr1_ok \spr1_ok
- connect \spr1 \spr1
connect \n_valid_o \alu_spr0_n_valid_o
connect \n_ready_i \alu_spr0_n_ready_i
+ connect \o \alu_spr0_o
+ connect \spr1 \alu_spr0_spr1
+ connect \fast1 \alu_spr0_fast1
+ connect \xer_so \alu_spr0_xer_so
+ connect \xer_ov \alu_spr0_xer_ov
+ connect \xer_ca \alu_spr0_xer_ca
connect \op__insn_type \alu_spr0_op__insn_type
connect \op__fn_unit \alu_spr0_op__fn_unit
connect \op__insn \alu_spr0_op__insn
connect \op__is_32bit \alu_spr0_op__is_32bit
connect \ra \alu_spr0_ra
- connect \spr1$1 \alu_spr0_spr1
- connect \fast1$2 \alu_spr0_fast1
- connect \xer_so$3 \alu_spr0_xer_so
- connect \xer_ov$4 \alu_spr0_xer_ov
- connect \xer_ca$5 \alu_spr0_xer_ca
+ connect \spr1$1 \alu_spr0_spr1$1
+ connect \fast1$2 \alu_spr0_fast1$2
+ connect \xer_so$3 \alu_spr0_xer_so$3
+ connect \xer_ov$4 \alu_spr0_xer_ov$4
+ connect \xer_ca$5 \alu_spr0_xer_ca$5
connect \p_valid_i \alu_spr0_p_valid_i
connect \p_ready_o \alu_spr0_p_ready_o
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:178"
wire width 1 \all_rd
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179"
- wire width 1 $1
+ wire width 1 $6
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179"
- cell $and $2
+ cell $and $7
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \busy_o
connect \B \rok_l_q_rdok
- connect \Y $1
+ connect \Y $6
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180"
- wire width 1 $3
+ wire width 1 $8
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180"
- wire width 6 $4
+ wire width 6 $9
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180"
- cell $not $5
+ cell $not $10
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \Y_WIDTH 6
connect \A \rd__rel
- connect \Y $4
+ connect \Y $9
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180"
- wire width 6 $6
+ wire width 6 $11
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180"
- cell $or $7
+ cell $or $12
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \B_WIDTH 6
parameter \Y_WIDTH 6
- connect \A $4
+ connect \A $9
connect \B \rd__go
- connect \Y $6
+ connect \Y $11
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180"
- cell $reduce_and $8
+ cell $reduce_and $13
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \Y_WIDTH 1
- connect \A $6
- connect \Y $3
+ connect \A $11
+ connect \Y $8
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180"
- wire width 1 $9
+ wire width 1 $14
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180"
- cell $and $10
+ cell $and $15
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $1
- connect \B $3
- connect \Y $9
+ connect \A $6
+ connect \B $8
+ connect \Y $14
end
process $group_0
assign \all_rd 1'0
- assign \all_rd $9
+ assign \all_rd $14
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:183"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:184"
wire width 1 \all_rd_pulse
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:186"
- wire width 1 $11
+ wire width 1 $16
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:186"
- cell $not $12
+ cell $not $17
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \all_rd_dly
- connect \Y $11
+ connect \Y $16
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:186"
- wire width 1 $13
+ wire width 1 $18
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:186"
- cell $and $14
+ cell $and $19
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \all_rd
- connect \B $11
- connect \Y $13
+ connect \B $16
+ connect \Y $18
end
process $group_2
assign \all_rd_pulse 1'0
- assign \all_rd_pulse $13
+ assign \all_rd_pulse $18
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:191"
wire width 1 \alu_pulse
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:195"
- wire width 1 $15
+ wire width 1 $20
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:195"
- cell $not $16
+ cell $not $21
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \alu_done_dly
- connect \Y $15
+ connect \Y $20
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:195"
- wire width 1 $17
+ wire width 1 $22
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:195"
- cell $and $18
+ cell $and $23
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \alu_done
- connect \B $15
- connect \Y $17
+ connect \B $20
+ connect \Y $22
end
process $group_5
assign \alu_pulse 1'0
- assign \alu_pulse $17
+ assign \alu_pulse $22
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:192"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:199"
wire width 6 \prev_wr_go$next
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:201"
- wire width 6 $19
+ wire width 6 $24
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:201"
- cell $and $20
+ cell $and $25
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 6
connect \A \wr__go
connect \B { \busy_o \busy_o \busy_o \busy_o \busy_o \busy_o }
- connect \Y $19
+ connect \Y $24
end
process $group_7
assign \prev_wr_go$next \prev_wr_go
- assign \prev_wr_go$next $19
+ assign \prev_wr_go$next $24
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100"
wire width 1 \done_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
- wire width 1 $21
+ wire width 1 $26
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
- wire width 1 $22
+ wire width 1 $27
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
- wire width 6 $23
+ wire width 6 $28
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:93"
wire width 6 \wrmask
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
- cell $not $24
+ cell $not $29
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \Y_WIDTH 6
connect \A \wrmask
- connect \Y $23
+ connect \Y $28
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
- wire width 6 $25
+ wire width 6 $30
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
- cell $and $26
+ cell $and $31
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \B_WIDTH 6
parameter \Y_WIDTH 6
connect \A \wr__rel
- connect \B $23
- connect \Y $25
+ connect \B $28
+ connect \Y $30
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
- cell $reduce_bool $27
+ cell $reduce_bool $32
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \Y_WIDTH 1
- connect \A $25
- connect \Y $22
+ connect \A $30
+ connect \Y $27
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
- cell $not $28
+ cell $not $33
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $22
- connect \Y $21
+ connect \A $27
+ connect \Y $26
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
- wire width 1 $29
+ wire width 1 $34
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
- cell $and $30
+ cell $and $35
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \busy_o
- connect \B $21
- connect \Y $29
+ connect \B $26
+ connect \Y $34
end
process $group_8
assign \done_o 1'0
- assign \done_o $29
+ assign \done_o $34
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206"
wire width 1 \wr_any
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210"
- wire width 1 $31
+ wire width 1 $36
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210"
- cell $reduce_bool $32
+ cell $reduce_bool $37
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \Y_WIDTH 1
connect \A \wr__go
- connect \Y $31
+ connect \Y $36
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210"
- wire width 1 $33
+ wire width 1 $38
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210"
- cell $reduce_bool $34
+ cell $reduce_bool $39
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \Y_WIDTH 1
connect \A \prev_wr_go
- connect \Y $33
+ connect \Y $38
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210"
- wire width 1 $35
+ wire width 1 $40
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210"
- cell $or $36
+ cell $or $41
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $31
- connect \B $33
- connect \Y $35
+ connect \A $36
+ connect \B $38
+ connect \Y $40
end
process $group_9
assign \wr_any 1'0
- assign \wr_any $35
+ assign \wr_any $40
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:207"
wire width 1 \req_done
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211"
- wire width 1 $37
+ wire width 1 $42
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211"
- cell $not $38
+ cell $not $43
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \alu_spr0_n_ready_i
- connect \Y $37
+ connect \Y $42
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211"
- wire width 1 $39
+ wire width 1 $44
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211"
- cell $and $40
+ cell $and $45
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \wr_any
- connect \B $37
- connect \Y $39
+ connect \B $42
+ connect \Y $44
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212"
- wire width 6 $41
+ wire width 6 $46
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212"
- cell $and $42
+ cell $and $47
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 6
connect \A \req_l_q_req
connect \B \wrmask
- connect \Y $41
+ connect \Y $46
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212"
- wire width 1 $43
+ wire width 1 $48
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212"
- cell $eq $44
+ cell $eq $49
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $41
+ connect \A $46
connect \B 1'0
- connect \Y $43
+ connect \Y $48
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212"
- wire width 1 $45
+ wire width 1 $50
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212"
- cell $and $46
+ cell $and $51
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $39
- connect \B $43
- connect \Y $45
+ connect \A $44
+ connect \B $48
+ connect \Y $50
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
- wire width 1 $47
+ wire width 1 $52
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
- cell $eq $48
+ cell $eq $53
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wrmask
connect \B 1'0
- connect \Y $47
+ connect \Y $52
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
- wire width 1 $49
+ wire width 1 $54
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
- cell $and $50
+ cell $and $55
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $47
+ connect \A $52
connect \B \alu_spr0_n_ready_i
- connect \Y $49
+ connect \Y $54
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
- wire width 1 $51
+ wire width 1 $56
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
- cell $and $52
+ cell $and $57
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $49
+ connect \A $54
connect \B \alu_spr0_n_valid_o
- connect \Y $51
+ connect \Y $56
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
- wire width 1 $53
+ wire width 1 $58
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
- cell $and $54
+ cell $and $59
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $51
+ connect \A $56
connect \B \busy_o
- connect \Y $53
+ connect \Y $58
end
process $group_10
assign \req_done 1'0
- assign \req_done $45
+ assign \req_done $50
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
- switch { $53 }
+ switch { $58 }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
case 1'1
assign \req_done 1'1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:221"
wire width 1 \reset
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
- wire width 1 $55
+ wire width 1 $60
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
- cell $or $56
+ cell $or $61
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \req_done
connect \B \go_die_i
- connect \Y $55
+ connect \Y $60
end
process $group_11
assign \reset 1'0
- assign \reset $55
+ assign \reset $60
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222"
wire width 1 \rst_r
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226"
- wire width 1 $57
+ wire width 1 $62
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226"
- cell $or $58
+ cell $or $63
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \issue_i
connect \B \go_die_i
- connect \Y $57
+ connect \Y $62
end
process $group_12
assign \rst_r 1'0
- assign \rst_r $57
+ assign \rst_r $62
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:223"
wire width 6 \reset_w
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227"
- wire width 6 $59
+ wire width 6 $64
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227"
- cell $or $60
+ cell $or $65
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 6
connect \A \wr__go
connect \B { \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i }
- connect \Y $59
+ connect \Y $64
end
process $group_13
assign \reset_w 6'000000
- assign \reset_w $59
+ assign \reset_w $64
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:224"
wire width 6 \reset_r
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:228"
- wire width 6 $61
+ wire width 6 $66
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:228"
- cell $or $62
+ cell $or $67
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 6
connect \A \rd__go
connect \B { \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i \go_die_i }
- connect \Y $61
+ connect \Y $66
end
process $group_14
assign \reset_r 6'000000
- assign \reset_r $61
+ assign \reset_r $66
sync init
end
process $group_15
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232"
- wire width 1 $63
+ wire width 1 $68
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232"
- cell $and $64
+ cell $and $69
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \alu_spr0_n_valid_o
connect \B \busy_o
- connect \Y $63
+ connect \Y $68
end
process $group_16
assign \rok_l_r_rdok$next \rok_l_r_rdok
- assign \rok_l_r_rdok$next $63
+ assign \rok_l_r_rdok$next $68
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
update \src_l_r_src \src_l_r_src$next
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:247"
- wire width 6 $65
+ wire width 6 $70
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:247"
- cell $and $66
+ cell $and $71
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 6
connect \A \alu_pulsem
connect \B \wrmask
- connect \Y $65
+ connect \Y $70
end
process $group_23
assign \req_l_s_req 6'000000
- assign \req_l_s_req $65
+ assign \req_l_s_req $70
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:248"
- wire width 6 $67
+ wire width 6 $72
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:248"
- cell $or $68
+ cell $or $73
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 6
connect \A \reset_w
connect \B \prev_wr_go
- connect \Y $67
+ connect \Y $72
end
process $group_24
assign \req_l_r_req 6'111111
- assign \req_l_r_req $67
+ assign \req_l_r_req $72
sync init
end
- attribute \enum_base_type "InternalOp"
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20"
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 7 \oper_r__insn_type
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00100000000 "MUL"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 11 \oper_r__fn_unit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 32 \oper_r__insn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \oper_r__is_32bit
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
wire width 7 \oper_l__insn_type
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
wire width 1 \oper_l__is_32bit$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
- wire width 51 $69
+ wire width 51 $74
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
- cell $mux $70
+ cell $mux $75
parameter \WIDTH 51
connect \A { \oper_l__is_32bit \oper_l__insn \oper_l__fn_unit \oper_l__insn_type }
connect \B { \oper_i__is_32bit \oper_i__insn \oper_i__fn_unit \oper_i__insn_type }
connect \S \issue_i
- connect \Y $69
+ connect \Y $74
end
process $group_25
assign \oper_r__insn_type 7'0000000
assign \oper_r__fn_unit 11'00000000000
assign \oper_r__insn 32'00000000000000000000000000000000
assign \oper_r__is_32bit 1'0
- assign { \oper_r__is_32bit \oper_r__insn \oper_r__fn_unit \oper_r__insn_type } $69
+ assign { \oper_r__is_32bit \oper_r__insn \oper_r__fn_unit \oper_r__insn_type } $74
sync init
end
process $group_29
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
wire width 1 \data_r0_l__o_ok$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
- wire width 65 $71
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:730"
- wire width 1 $72
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:730"
- cell $reduce_bool $73
+ wire width 65 $76
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744"
+ wire width 1 $77
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744"
+ cell $reduce_bool $78
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \Y_WIDTH 1
connect \A \alu_pulsem
- connect \Y $72
+ connect \Y $77
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
- cell $mux $74
+ cell $mux $79
parameter \WIDTH 65
connect \A { \data_r0_l__o_ok \data_r0_l__o }
- connect \B { \o_ok \o }
- connect \S $72
- connect \Y $71
+ connect \B { \o_ok \alu_spr0_o }
+ connect \S $77
+ connect \Y $76
end
process $group_33
assign \data_r0__o 64'0000000000000000000000000000000000000000000000000000000000000000
assign \data_r0__o_ok 1'0
- assign { \data_r0__o_ok \data_r0__o } $71
+ assign { \data_r0__o_ok \data_r0__o } $76
sync init
end
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
- wire width 1 $75
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
- cell $reduce_bool $76
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
+ wire width 1 $80
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
+ cell $reduce_bool $81
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \Y_WIDTH 1
connect \A \alu_pulsem
- connect \Y $75
+ connect \Y $80
end
process $group_35
assign \data_r0_l__o$next \data_r0_l__o
assign \data_r0_l__o_ok$next \data_r0_l__o_ok
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
- switch { $75 }
+ switch { $80 }
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
case 1'1
- assign { \data_r0_l__o_ok$next \data_r0_l__o$next } { \o_ok \o }
+ assign { \data_r0_l__o_ok$next \data_r0_l__o$next } { \o_ok \alu_spr0_o }
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
wire width 1 \data_r1_l__spr1_ok$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
- wire width 65 $77
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:730"
- wire width 1 $78
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:730"
- cell $reduce_bool $79
+ wire width 65 $82
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744"
+ wire width 1 $83
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744"
+ cell $reduce_bool $84
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \Y_WIDTH 1
connect \A \alu_pulsem
- connect \Y $78
+ connect \Y $83
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
- cell $mux $80
+ cell $mux $85
parameter \WIDTH 65
connect \A { \data_r1_l__spr1_ok \data_r1_l__spr1 }
- connect \B { \spr1_ok \spr1 }
- connect \S $78
- connect \Y $77
+ connect \B { \spr1_ok \alu_spr0_spr1 }
+ connect \S $83
+ connect \Y $82
end
process $group_37
assign \data_r1__spr1 64'0000000000000000000000000000000000000000000000000000000000000000
assign \data_r1__spr1_ok 1'0
- assign { \data_r1__spr1_ok \data_r1__spr1 } $77
+ assign { \data_r1__spr1_ok \data_r1__spr1 } $82
sync init
end
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
- wire width 1 $81
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
- cell $reduce_bool $82
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
+ wire width 1 $86
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
+ cell $reduce_bool $87
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \Y_WIDTH 1
connect \A \alu_pulsem
- connect \Y $81
+ connect \Y $86
end
process $group_39
assign \data_r1_l__spr1$next \data_r1_l__spr1
assign \data_r1_l__spr1_ok$next \data_r1_l__spr1_ok
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
- switch { $81 }
+ switch { $86 }
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
case 1'1
- assign { \data_r1_l__spr1_ok$next \data_r1_l__spr1$next } { \spr1_ok \spr1 }
+ assign { \data_r1_l__spr1_ok$next \data_r1_l__spr1$next } { \spr1_ok \alu_spr0_spr1 }
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
wire width 1 \data_r2_l__fast1_ok$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
- wire width 65 $83
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:730"
- wire width 1 $84
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:730"
- cell $reduce_bool $85
+ wire width 65 $88
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744"
+ wire width 1 $89
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744"
+ cell $reduce_bool $90
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \Y_WIDTH 1
connect \A \alu_pulsem
- connect \Y $84
+ connect \Y $89
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
- cell $mux $86
+ cell $mux $91
parameter \WIDTH 65
connect \A { \data_r2_l__fast1_ok \data_r2_l__fast1 }
- connect \B { \fast1_ok \fast1 }
- connect \S $84
- connect \Y $83
+ connect \B { \fast1_ok \alu_spr0_fast1 }
+ connect \S $89
+ connect \Y $88
end
process $group_41
assign \data_r2__fast1 64'0000000000000000000000000000000000000000000000000000000000000000
assign \data_r2__fast1_ok 1'0
- assign { \data_r2__fast1_ok \data_r2__fast1 } $83
+ assign { \data_r2__fast1_ok \data_r2__fast1 } $88
sync init
end
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
- wire width 1 $87
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
- cell $reduce_bool $88
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
+ wire width 1 $92
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
+ cell $reduce_bool $93
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \Y_WIDTH 1
connect \A \alu_pulsem
- connect \Y $87
+ connect \Y $92
end
process $group_43
assign \data_r2_l__fast1$next \data_r2_l__fast1
assign \data_r2_l__fast1_ok$next \data_r2_l__fast1_ok
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
- switch { $87 }
+ switch { $92 }
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
case 1'1
- assign { \data_r2_l__fast1_ok$next \data_r2_l__fast1$next } { \fast1_ok \fast1 }
+ assign { \data_r2_l__fast1_ok$next \data_r2_l__fast1$next } { \fast1_ok \alu_spr0_fast1 }
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
wire width 1 \data_r3_l__xer_so_ok$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
- wire width 2 $89
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:730"
- wire width 1 $90
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:730"
- cell $reduce_bool $91
+ wire width 2 $94
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744"
+ wire width 1 $95
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744"
+ cell $reduce_bool $96
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \Y_WIDTH 1
connect \A \alu_pulsem
- connect \Y $90
+ connect \Y $95
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
- cell $mux $92
+ cell $mux $97
parameter \WIDTH 2
connect \A { \data_r3_l__xer_so_ok \data_r3_l__xer_so }
- connect \B { \xer_so_ok \xer_so }
- connect \S $90
- connect \Y $89
+ connect \B { \xer_so_ok \alu_spr0_xer_so }
+ connect \S $95
+ connect \Y $94
end
process $group_45
assign \data_r3__xer_so 1'0
assign \data_r3__xer_so_ok 1'0
- assign { \data_r3__xer_so_ok \data_r3__xer_so } $89
+ assign { \data_r3__xer_so_ok \data_r3__xer_so } $94
sync init
end
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
- wire width 1 $93
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
- cell $reduce_bool $94
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
+ wire width 1 $98
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
+ cell $reduce_bool $99
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \Y_WIDTH 1
connect \A \alu_pulsem
- connect \Y $93
+ connect \Y $98
end
process $group_47
assign \data_r3_l__xer_so$next \data_r3_l__xer_so
assign \data_r3_l__xer_so_ok$next \data_r3_l__xer_so_ok
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
- switch { $93 }
+ switch { $98 }
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
case 1'1
- assign { \data_r3_l__xer_so_ok$next \data_r3_l__xer_so$next } { \xer_so_ok \xer_so }
+ assign { \data_r3_l__xer_so_ok$next \data_r3_l__xer_so$next } { \xer_so_ok \alu_spr0_xer_so }
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
wire width 1 \data_r4_l__xer_ov_ok$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
- wire width 3 $95
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:730"
- wire width 1 $96
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:730"
- cell $reduce_bool $97
+ wire width 3 $100
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744"
+ wire width 1 $101
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744"
+ cell $reduce_bool $102
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \Y_WIDTH 1
connect \A \alu_pulsem
- connect \Y $96
+ connect \Y $101
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
- cell $mux $98
+ cell $mux $103
parameter \WIDTH 3
connect \A { \data_r4_l__xer_ov_ok \data_r4_l__xer_ov }
- connect \B { \xer_ov_ok \xer_ov }
- connect \S $96
- connect \Y $95
+ connect \B { \xer_ov_ok \alu_spr0_xer_ov }
+ connect \S $101
+ connect \Y $100
end
process $group_49
assign \data_r4__xer_ov 2'00
assign \data_r4__xer_ov_ok 1'0
- assign { \data_r4__xer_ov_ok \data_r4__xer_ov } $95
+ assign { \data_r4__xer_ov_ok \data_r4__xer_ov } $100
sync init
end
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
- wire width 1 $99
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
- cell $reduce_bool $100
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
+ wire width 1 $104
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
+ cell $reduce_bool $105
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \Y_WIDTH 1
connect \A \alu_pulsem
- connect \Y $99
+ connect \Y $104
end
process $group_51
assign \data_r4_l__xer_ov$next \data_r4_l__xer_ov
assign \data_r4_l__xer_ov_ok$next \data_r4_l__xer_ov_ok
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
- switch { $99 }
+ switch { $104 }
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
case 1'1
- assign { \data_r4_l__xer_ov_ok$next \data_r4_l__xer_ov$next } { \xer_ov_ok \xer_ov }
+ assign { \data_r4_l__xer_ov_ok$next \data_r4_l__xer_ov$next } { \xer_ov_ok \alu_spr0_xer_ov }
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
wire width 1 \data_r5_l__xer_ca_ok$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
- wire width 3 $101
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:730"
- wire width 1 $102
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:730"
- cell $reduce_bool $103
+ wire width 3 $106
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744"
+ wire width 1 $107
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744"
+ cell $reduce_bool $108
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \Y_WIDTH 1
connect \A \alu_pulsem
- connect \Y $102
+ connect \Y $107
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
- cell $mux $104
+ cell $mux $109
parameter \WIDTH 3
connect \A { \data_r5_l__xer_ca_ok \data_r5_l__xer_ca }
- connect \B { \xer_ca_ok \xer_ca }
- connect \S $102
- connect \Y $101
+ connect \B { \xer_ca_ok \alu_spr0_xer_ca }
+ connect \S $107
+ connect \Y $106
end
process $group_53
assign \data_r5__xer_ca 2'00
assign \data_r5__xer_ca_ok 1'0
- assign { \data_r5__xer_ca_ok \data_r5__xer_ca } $101
+ assign { \data_r5__xer_ca_ok \data_r5__xer_ca } $106
sync init
end
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
- wire width 1 $105
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
- cell $reduce_bool $106
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
+ wire width 1 $110
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
+ cell $reduce_bool $111
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \Y_WIDTH 1
connect \A \alu_pulsem
- connect \Y $105
+ connect \Y $110
end
process $group_55
assign \data_r5_l__xer_ca$next \data_r5_l__xer_ca
assign \data_r5_l__xer_ca_ok$next \data_r5_l__xer_ca_ok
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
- switch { $105 }
+ switch { $110 }
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
case 1'1
- assign { \data_r5_l__xer_ca_ok$next \data_r5_l__xer_ca$next } { \xer_ca_ok \xer_ca }
+ assign { \data_r5_l__xer_ca_ok$next \data_r5_l__xer_ca$next } { \xer_ca_ok \alu_spr0_xer_ca }
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
update \data_r5_l__xer_ca \data_r5_l__xer_ca$next
update \data_r5_l__xer_ca_ok \data_r5_l__xer_ca_ok$next
end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+ wire width 1 $112
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+ cell $and $113
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \data_r0__o_ok
+ connect \B \busy_o
+ connect \Y $112
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+ wire width 1 $114
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+ cell $and $115
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \data_r1__spr1_ok
+ connect \B \busy_o
+ connect \Y $114
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+ wire width 1 $116
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+ cell $and $117
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \data_r2__fast1_ok
+ connect \B \busy_o
+ connect \Y $116
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+ wire width 1 $118
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+ cell $and $119
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \data_r3__xer_so_ok
+ connect \B \busy_o
+ connect \Y $118
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+ wire width 1 $120
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+ cell $and $121
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \data_r4__xer_ov_ok
+ connect \B \busy_o
+ connect \Y $120
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+ wire width 1 $122
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+ cell $and $123
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \data_r5__xer_ca_ok
+ connect \B \busy_o
+ connect \Y $122
+ end
process $group_57
assign \wrmask 6'000000
- assign \wrmask { \data_r5__xer_ca_ok \data_r4__xer_ov_ok \data_r3__xer_so_ok \data_r2__fast1_ok \data_r1__spr1_ok \data_r0__o_ok }
+ assign \wrmask { $122 $120 $118 $116 $114 $112 }
sync init
end
process $group_58
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
wire width 64 \src_r0$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
- wire width 64 $107
+ wire width 64 $124
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
- cell $mux $108
+ cell $mux $125
parameter \WIDTH 64
connect \A \src_r0
connect \B \src1_i
connect \S \src_l_q_src [0]
- connect \Y $107
+ connect \Y $124
end
process $group_62
assign \alu_spr0_ra 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \alu_spr0_ra $107
+ assign \alu_spr0_ra $124
sync init
end
process $group_63
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
wire width 64 \src_r1$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
- wire width 64 $109
+ wire width 64 $126
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
- cell $mux $110
+ cell $mux $127
parameter \WIDTH 64
connect \A \src_r1
connect \B \src2_i
connect \S \src_l_q_src [1]
- connect \Y $109
+ connect \Y $126
end
process $group_64
- assign \alu_spr0_spr1 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \alu_spr0_spr1 $109
+ assign \alu_spr0_spr1$1 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \alu_spr0_spr1$1 $126
sync init
end
process $group_65
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
wire width 64 \src_r2$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
- wire width 64 $111
+ wire width 64 $128
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
- cell $mux $112
+ cell $mux $129
parameter \WIDTH 64
connect \A \src_r2
connect \B \src3_i
connect \S \src_l_q_src [2]
- connect \Y $111
+ connect \Y $128
end
process $group_66
- assign \alu_spr0_fast1 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \alu_spr0_fast1 $111
+ assign \alu_spr0_fast1$2 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \alu_spr0_fast1$2 $128
sync init
end
process $group_67
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
wire width 1 \src_r3$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
- wire width 1 $113
+ wire width 1 $130
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
- cell $mux $114
+ cell $mux $131
parameter \WIDTH 1
connect \A \src_r3
connect \B \src4_i
connect \S \src_l_q_src [3]
- connect \Y $113
+ connect \Y $130
end
process $group_68
- assign \alu_spr0_xer_so 1'0
- assign \alu_spr0_xer_so $113
+ assign \alu_spr0_xer_so$3 1'0
+ assign \alu_spr0_xer_so$3 $130
sync init
end
process $group_69
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
wire width 2 \src_r4$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
- wire width 2 $115
+ wire width 2 $132
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
- cell $mux $116
+ cell $mux $133
parameter \WIDTH 2
connect \A \src_r4
connect \B \src5_i
connect \S \src_l_q_src [4]
- connect \Y $115
+ connect \Y $132
end
process $group_70
- assign \alu_spr0_xer_ov 2'00
- assign \alu_spr0_xer_ov $115
+ assign \alu_spr0_xer_ov$4 2'00
+ assign \alu_spr0_xer_ov$4 $132
sync init
end
process $group_71
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
wire width 2 \src_r5$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
- wire width 2 $117
+ wire width 2 $134
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
- cell $mux $118
+ cell $mux $135
parameter \WIDTH 2
connect \A \src_r5
connect \B \src6_i
connect \S \src_l_q_src [5]
- connect \Y $117
+ connect \Y $134
end
process $group_72
- assign \alu_spr0_xer_ca 2'00
- assign \alu_spr0_xer_ca $117
+ assign \alu_spr0_xer_ca$5 2'00
+ assign \alu_spr0_xer_ca$5 $134
sync init
end
process $group_73
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:321"
- wire width 1 $119
+ wire width 1 $136
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:321"
- cell $and $120
+ cell $and $137
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \alu_spr0_p_ready_o
connect \B \alui_l_q_alui
- connect \Y $119
+ connect \Y $136
end
process $group_75
assign \alui_l_r_alui$next \alui_l_r_alui
- assign \alui_l_r_alui$next $119
+ assign \alui_l_r_alui$next $136
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:328"
- wire width 1 $121
+ wire width 1 $138
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:328"
- cell $and $122
+ cell $and $139
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \alu_spr0_n_valid_o
connect \B \alu_l_q_alu
- connect \Y $121
+ connect \Y $138
end
process $group_78
assign \alu_l_r_alu$next \alu_l_r_alu
- assign \alu_l_r_alu$next $121
+ assign \alu_l_r_alu$next $138
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341"
- wire width 6 $123
+ wire width 6 $140
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341"
- cell $and $124
+ cell $and $141
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \Y_WIDTH 6
connect \A \src_l_q_src
connect \B { \busy_o \busy_o \busy_o \busy_o \busy_o \busy_o }
- connect \Y $123
+ connect \Y $140
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341"
- wire width 6 $125
+ wire width 6 $142
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341"
- cell $and $126
+ cell $and $143
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \B_WIDTH 6
parameter \Y_WIDTH 6
- connect \A $123
+ connect \A $140
connect \B { 1'1 1'1 1'1 1'1 1'1 1'1 }
- connect \Y $125
+ connect \Y $142
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341"
- wire width 6 $127
+ wire width 6 $144
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341"
- cell $not $128
+ cell $not $145
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \Y_WIDTH 6
connect \A \rdmaskn
- connect \Y $127
+ connect \Y $144
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341"
- wire width 6 $129
+ wire width 6 $146
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341"
- cell $and $130
+ cell $and $147
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \B_WIDTH 6
parameter \Y_WIDTH 6
- connect \A $125
- connect \B $127
- connect \Y $129
+ connect \A $142
+ connect \B $144
+ connect \Y $146
end
process $group_81
assign \rd__rel 6'000000
- assign \rd__rel $129
+ assign \rd__rel $146
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
- wire width 1 $131
+ wire width 1 $148
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
- cell $and $132
+ cell $and $149
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \busy_o
connect \B \shadown_i
- connect \Y $131
+ connect \Y $148
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
- wire width 1 $133
+ wire width 1 $150
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
- cell $and $134
+ cell $and $151
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \busy_o
connect \B \shadown_i
- connect \Y $133
+ connect \Y $150
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
- wire width 1 $135
+ wire width 1 $152
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
- cell $and $136
+ cell $and $153
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \busy_o
connect \B \shadown_i
- connect \Y $135
+ connect \Y $152
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
- wire width 1 $137
+ wire width 1 $154
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
- cell $and $138
+ cell $and $155
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \busy_o
connect \B \shadown_i
- connect \Y $137
+ connect \Y $154
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
- wire width 1 $139
+ wire width 1 $156
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
- cell $and $140
+ cell $and $157
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \busy_o
connect \B \shadown_i
- connect \Y $139
+ connect \Y $156
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
- wire width 1 $141
+ wire width 1 $158
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
- cell $and $142
+ cell $and $159
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \busy_o
connect \B \shadown_i
- connect \Y $141
+ connect \Y $158
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:345"
- wire width 6 $143
+ wire width 6 $160
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:345"
- cell $and $144
+ cell $and $161
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \B_WIDTH 6
parameter \Y_WIDTH 6
connect \A \req_l_q_req
- connect \B { $131 $133 $135 $137 $139 $141 }
- connect \Y $143
+ connect \B { $148 $150 $152 $154 $156 $158 }
+ connect \Y $160
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:345"
- wire width 6 $145
+ wire width 6 $162
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:345"
- cell $and $146
+ cell $and $163
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \B_SIGNED 0
parameter \B_WIDTH 6
parameter \Y_WIDTH 6
- connect \A $143
+ connect \A $160
connect \B \wrmask
- connect \Y $145
+ connect \Y $162
end
process $group_82
assign \wr__rel 6'000000
- assign \wr__rel $145
+ assign \wr__rel $162
sync init
end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+ wire width 1 $164
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+ cell $and $165
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \wr__go [0]
+ connect \B \busy_o
+ connect \Y $164
+ end
process $group_83
assign \dest1_o 64'0000000000000000000000000000000000000000000000000000000000000000
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
- switch { \wr__go [0] }
+ switch { $164 }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
case 1'1
assign \dest1_o { \data_r0__o_ok \data_r0__o } [63:0]
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
- wire width 64 \dest2_o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+ wire width 1 $166
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+ cell $and $167
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \wr__go [1]
+ connect \B \busy_o
+ connect \Y $166
+ end
process $group_84
assign \dest2_o 64'0000000000000000000000000000000000000000000000000000000000000000
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
- switch { \wr__go [1] }
+ switch { $166 }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
case 1'1
assign \dest2_o { \data_r1__spr1_ok \data_r1__spr1 } [63:0]
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
- wire width 64 \dest3_o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+ wire width 1 $168
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+ cell $and $169
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \wr__go [2]
+ connect \B \busy_o
+ connect \Y $168
+ end
process $group_85
assign \dest3_o 64'0000000000000000000000000000000000000000000000000000000000000000
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
- switch { \wr__go [2] }
+ switch { $168 }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
case 1'1
assign \dest3_o { \data_r2__fast1_ok \data_r2__fast1 } [63:0]
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
- wire width 1 \dest4_o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+ wire width 1 $170
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+ cell $and $171
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \wr__go [3]
+ connect \B \busy_o
+ connect \Y $170
+ end
process $group_86
assign \dest4_o 1'0
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
- switch { \wr__go [3] }
+ switch { $170 }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
case 1'1
assign \dest4_o { \data_r3__xer_so_ok \data_r3__xer_so } [0]
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
- wire width 2 \dest5_o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+ wire width 1 $172
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+ cell $and $173
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \wr__go [4]
+ connect \B \busy_o
+ connect \Y $172
+ end
process $group_87
assign \dest5_o 2'00
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
- switch { \wr__go [4] }
+ switch { $172 }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
case 1'1
assign \dest5_o { \data_r4__xer_ov_ok \data_r4__xer_ov } [1:0]
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
- wire width 2 \dest6_o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+ wire width 1 $174
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+ cell $and $175
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \wr__go [5]
+ connect \B \busy_o
+ connect \Y $174
+ end
process $group_88
assign \dest6_o 2'00
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
- switch { \wr__go [5] }
+ switch { $174 }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
case 1'1
assign \dest6_o { \data_r5__xer_ca_ok \data_r5__xer_ca } [1:0]
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.p"
+attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.p"
module \p$70
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153"
wire width 1 input 0 \p_valid_i
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154"
wire width 1 input 1 \p_ready_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:156"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158"
wire width 1 \trigger
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:203"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205"
wire width 1 $1
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:203"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205"
cell $and $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.n"
+attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.n"
module \n$71
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
wire width 1 input 0 \n_valid_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
wire width 1 input 1 \n_ready_i
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:249"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251"
wire width 1 \trigger
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:295"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:297"
wire width 1 $1
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:295"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:297"
cell $and $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe.p"
-module \p$73
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151"
+attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe1.p"
+module \p$72
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153"
wire width 1 input 0 \p_valid_i
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154"
wire width 1 input 1 \p_ready_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:156"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158"
wire width 1 \trigger
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:203"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205"
wire width 1 $1
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:203"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205"
cell $and $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe.n"
-module \n$74
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244"
+attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe1.n"
+module \n$73
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
wire width 1 input 0 \n_valid_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
wire width 1 input 1 \n_ready_i
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:249"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251"
wire width 1 \trigger
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:295"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:297"
wire width 1 $1
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:295"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:297"
cell $and $2
parameter \A_SIGNED 0
parameter \A_WIDTH 1
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe.input"
-module \input$75
- attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
+attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe1.input"
+module \input$74
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
wire width 2 input 0 \muxid
- attribute \enum_base_type "InternalOp"
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 7 input 1 \op__insn_type
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00100000000 "MUL"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 11 input 2 \op__fn_unit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 64 input 3 \op__imm_data__imm
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 input 4 \op__imm_data__imm_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 input 5 \op__rc__rc
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 input 6 \op__rc__rc_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 input 7 \op__oe__oe
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 input 8 \op__oe__oe_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 3 input 9 \op__write_cr__data
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 input 10 \op__write_cr__ok
- attribute \enum_base_type "CryIn"
- attribute \enum_value_00 "ZERO"
- attribute \enum_value_01 "ONE"
- attribute \enum_value_10 "CA"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 2 input 11 \op__input_carry
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 input 12 \op__output_carry
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 input 13 \op__input_cr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 input 14 \op__output_cr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 input 15 \op__is_32bit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 input 16 \op__is_signed
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 32 input 17 \op__insn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
- wire width 64 input 18 \ra
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
- wire width 64 input 19 \rb
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
- wire width 64 input 20 \rc
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
- wire width 2 input 21 \xer_ca
- attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
- wire width 2 output 22 \muxid$1
- attribute \enum_base_type "InternalOp"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 9 \op__invert_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 10 \op__zero_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 11 \op__invert_out
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 12 \op__write_cr0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 13 \op__is_32bit
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 14 \op__is_signed
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 input 15 \op__insn
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 64 input 16 \ra
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 64 input 17 \rb
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 1 input 18 \xer_so
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+ wire width 2 output 19 \muxid$1
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 7 output 23 \op__insn_type$2
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 7 output 20 \op__insn_type$2
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00000000010 "ALU"
attribute \enum_value_00100000000 "MUL"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 11 output 24 \op__fn_unit$3
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 64 output 25 \op__imm_data__imm$4
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 output 26 \op__imm_data__imm_ok$5
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 output 27 \op__rc__rc$6
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 output 28 \op__rc__rc_ok$7
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 output 29 \op__oe__oe$8
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 output 30 \op__oe__oe_ok$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 3 output 31 \op__write_cr__data$10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 output 32 \op__write_cr__ok$11
- attribute \enum_base_type "CryIn"
- attribute \enum_value_00 "ZERO"
- attribute \enum_value_01 "ONE"
- attribute \enum_value_10 "CA"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 2 output 33 \op__input_carry$12
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 output 34 \op__output_carry$13
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 output 35 \op__input_cr$14
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 output 36 \op__output_cr$15
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 output 37 \op__is_32bit$16
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 output 38 \op__is_signed$17
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 32 output 39 \op__insn$18
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
- wire width 64 output 40 \ra$19
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
- wire width 64 output 41 \rb$20
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
- wire width 64 output 42 \rc$21
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
- wire width 2 output 43 \xer_ca$22
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 11 output 21 \op__fn_unit$3
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 output 22 \op__imm_data__imm$4
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 23 \op__imm_data__imm_ok$5
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 24 \op__rc__rc$6
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 25 \op__rc__rc_ok$7
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 26 \op__oe__oe$8
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 27 \op__oe__oe_ok$9
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 28 \op__invert_a$10
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 29 \op__zero_a$11
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 30 \op__invert_out$12
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 31 \op__write_cr0$13
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 32 \op__is_32bit$14
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 33 \op__is_signed$15
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 output 34 \op__insn$16
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 64 output 35 \ra$17
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 64 output 36 \rb$18
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 1 output 37 \xer_so$19
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20"
wire width 64 \a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:24"
+ wire width 64 $20
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:24"
+ cell $not $21
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 64
+ parameter \Y_WIDTH 64
+ connect \A \ra
+ connect \Y $20
+ end
process $group_0
assign \a 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \a \ra
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:23"
+ switch { \op__invert_a }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:23"
+ case 1'1
+ assign \a $20
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:25"
+ case
+ assign \a \ra
+ end
sync init
end
process $group_1
- assign \ra$19 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \ra$19 \a
+ assign \ra$17 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \ra$17 \a
sync init
end
process $group_2
- assign \xer_ca$22 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:36"
- switch \op__input_carry
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:37"
- attribute \nmigen.decoding "ZERO/0"
- case 2'00
- assign \xer_ca$22 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:39"
- attribute \nmigen.decoding "ONE/1"
- case 2'01
- assign \xer_ca$22 2'11
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:41"
- attribute \nmigen.decoding "CA/2"
- case 2'10
- assign \xer_ca$22 \xer_ca
+ assign \xer_so$19 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:47"
+ switch { \op__oe__oe_ok }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:47"
+ case 1'1
+ assign \xer_so$19 \xer_so
end
sync init
end
assign \op__rc__rc_ok$7 1'0
assign \op__oe__oe$8 1'0
assign \op__oe__oe_ok$9 1'0
- assign \op__write_cr__data$10 3'000
- assign \op__write_cr__ok$11 1'0
- assign \op__input_carry$12 2'00
- assign \op__output_carry$13 1'0
- assign \op__input_cr$14 1'0
- assign \op__output_cr$15 1'0
- assign \op__is_32bit$16 1'0
- assign \op__is_signed$17 1'0
- assign \op__insn$18 32'00000000000000000000000000000000
- assign { \op__insn$18 \op__is_signed$17 \op__is_32bit$16 \op__output_cr$15 \op__input_cr$14 \op__output_carry$13 \op__input_carry$12 { \op__write_cr__ok$11 \op__write_cr__data$10 } { \op__oe__oe_ok$9 \op__oe__oe$8 } { \op__rc__rc_ok$7 \op__rc__rc$6 } { \op__imm_data__imm_ok$5 \op__imm_data__imm$4 } \op__fn_unit$3 \op__insn_type$2 } { \op__insn \op__is_signed \op__is_32bit \op__output_cr \op__input_cr \op__output_carry \op__input_carry { \op__write_cr__ok \op__write_cr__data } { \op__oe__oe_ok \op__oe__oe } { \op__rc__rc_ok \op__rc__rc } { \op__imm_data__imm_ok \op__imm_data__imm } \op__fn_unit \op__insn_type }
+ assign \op__invert_a$10 1'0
+ assign \op__zero_a$11 1'0
+ assign \op__invert_out$12 1'0
+ assign \op__write_cr0$13 1'0
+ assign \op__is_32bit$14 1'0
+ assign \op__is_signed$15 1'0
+ assign \op__insn$16 32'00000000000000000000000000000000
+ assign { \op__insn$16 \op__is_signed$15 \op__is_32bit$14 \op__write_cr0$13 \op__invert_out$12 \op__zero_a$11 \op__invert_a$10 { \op__oe__oe_ok$9 \op__oe__oe$8 } { \op__rc__rc_ok$7 \op__rc__rc$6 } { \op__imm_data__imm_ok$5 \op__imm_data__imm$4 } \op__fn_unit$3 \op__insn_type$2 } { \op__insn \op__is_signed \op__is_32bit \op__write_cr0 \op__invert_out \op__zero_a \op__invert_a { \op__oe__oe_ok \op__oe__oe } { \op__rc__rc_ok \op__rc__rc } { \op__imm_data__imm_ok \op__imm_data__imm } \op__fn_unit \op__insn_type }
sync init
end
- process $group_21
- assign \rb$20 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \rb$20 \rb
- sync init
- end
- process $group_22
- assign \rc$21 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \rc$21 \rc
+ process $group_19
+ assign \rb$18 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \rb$18 \rb
sync init
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe.main.rotator.rotl"
-module \rotl
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:8"
- wire width 64 input 0 \a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:9"
- wire width 6 input 1 \b
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:11"
- wire width 64 output 2 \o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:17"
- wire width 64 \shl
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:20"
- wire width 127 $1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:20"
- wire width 127 $2
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:20"
- cell $sshl $3
- parameter \A_SIGNED 0
- parameter \A_WIDTH 64
- parameter \B_SIGNED 0
- parameter \B_WIDTH 6
- parameter \Y_WIDTH 127
- connect \A \a
- connect \B \b
- connect \Y $2
- end
- connect $1 $2
+attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe1.mul1"
+module \mul1
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+ wire width 2 input 0 \muxid
+ attribute \enum_base_type "MicrOp"
+ attribute \enum_value_0000000 "OP_ILLEGAL"
+ attribute \enum_value_0000001 "OP_NOP"
+ attribute \enum_value_0000010 "OP_ADD"
+ attribute \enum_value_0000011 "OP_ADDPCIS"
+ attribute \enum_value_0000100 "OP_AND"
+ attribute \enum_value_0000101 "OP_ATTN"
+ attribute \enum_value_0000110 "OP_B"
+ attribute \enum_value_0000111 "OP_BC"
+ attribute \enum_value_0001000 "OP_BCREG"
+ attribute \enum_value_0001001 "OP_BPERM"
+ attribute \enum_value_0001010 "OP_CMP"
+ attribute \enum_value_0001011 "OP_CMPB"
+ attribute \enum_value_0001100 "OP_CMPEQB"
+ attribute \enum_value_0001101 "OP_CMPRB"
+ attribute \enum_value_0001110 "OP_CNTZ"
+ attribute \enum_value_0001111 "OP_CRAND"
+ attribute \enum_value_0010000 "OP_CRANDC"
+ attribute \enum_value_0010001 "OP_CREQV"
+ attribute \enum_value_0010010 "OP_CRNAND"
+ attribute \enum_value_0010011 "OP_CRNOR"
+ attribute \enum_value_0010100 "OP_CROR"
+ attribute \enum_value_0010101 "OP_CRORC"
+ attribute \enum_value_0010110 "OP_CRXOR"
+ attribute \enum_value_0010111 "OP_DARN"
+ attribute \enum_value_0011000 "OP_DCBF"
+ attribute \enum_value_0011001 "OP_DCBST"
+ attribute \enum_value_0011010 "OP_DCBT"
+ attribute \enum_value_0011011 "OP_DCBTST"
+ attribute \enum_value_0011100 "OP_DCBZ"
+ attribute \enum_value_0011101 "OP_DIV"
+ attribute \enum_value_0011110 "OP_DIVE"
+ attribute \enum_value_0011111 "OP_EXTS"
+ attribute \enum_value_0100000 "OP_EXTSWSLI"
+ attribute \enum_value_0100001 "OP_ICBI"
+ attribute \enum_value_0100010 "OP_ICBT"
+ attribute \enum_value_0100011 "OP_ISEL"
+ attribute \enum_value_0100100 "OP_ISYNC"
+ attribute \enum_value_0100101 "OP_LOAD"
+ attribute \enum_value_0100110 "OP_STORE"
+ attribute \enum_value_0100111 "OP_MADDHD"
+ attribute \enum_value_0101000 "OP_MADDHDU"
+ attribute \enum_value_0101001 "OP_MADDLD"
+ attribute \enum_value_0101010 "OP_MCRF"
+ attribute \enum_value_0101011 "OP_MCRXR"
+ attribute \enum_value_0101100 "OP_MCRXRX"
+ attribute \enum_value_0101101 "OP_MFCR"
+ attribute \enum_value_0101110 "OP_MFSPR"
+ attribute \enum_value_0101111 "OP_MOD"
+ attribute \enum_value_0110000 "OP_MTCRF"
+ attribute \enum_value_0110001 "OP_MTSPR"
+ attribute \enum_value_0110010 "OP_MUL_L64"
+ attribute \enum_value_0110011 "OP_MUL_H64"
+ attribute \enum_value_0110100 "OP_MUL_H32"
+ attribute \enum_value_0110101 "OP_OR"
+ attribute \enum_value_0110110 "OP_POPCNT"
+ attribute \enum_value_0110111 "OP_PRTY"
+ attribute \enum_value_0111000 "OP_RLC"
+ attribute \enum_value_0111001 "OP_RLCL"
+ attribute \enum_value_0111010 "OP_RLCR"
+ attribute \enum_value_0111011 "OP_SETB"
+ attribute \enum_value_0111100 "OP_SHL"
+ attribute \enum_value_0111101 "OP_SHR"
+ attribute \enum_value_0111110 "OP_SYNC"
+ attribute \enum_value_0111111 "OP_TRAP"
+ attribute \enum_value_1000011 "OP_XOR"
+ attribute \enum_value_1000100 "OP_SIM_CONFIG"
+ attribute \enum_value_1000101 "OP_CROP"
+ attribute \enum_value_1000110 "OP_RFID"
+ attribute \enum_value_1000111 "OP_MFMSR"
+ attribute \enum_value_1001000 "OP_MTMSRD"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 7 input 1 \op__insn_type
+ attribute \enum_base_type "Function"
+ attribute \enum_value_00000000000 "NONE"
+ attribute \enum_value_00000000010 "ALU"
+ attribute \enum_value_00000000100 "LDST"
+ attribute \enum_value_00000001000 "SHIFT_ROT"
+ attribute \enum_value_00000010000 "LOGICAL"
+ attribute \enum_value_00000100000 "BRANCH"
+ attribute \enum_value_00001000000 "CR"
+ attribute \enum_value_00010000000 "TRAP"
+ attribute \enum_value_00100000000 "MUL"
+ attribute \enum_value_01000000000 "DIV"
+ attribute \enum_value_10000000000 "SPR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 11 input 2 \op__fn_unit
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 input 3 \op__imm_data__imm
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 4 \op__imm_data__imm_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 5 \op__rc__rc
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 6 \op__rc__rc_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 7 \op__oe__oe
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 8 \op__oe__oe_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 9 \op__invert_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 10 \op__zero_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 11 \op__invert_out
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 12 \op__write_cr0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 13 \op__is_32bit
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 14 \op__is_signed
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 input 15 \op__insn
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 64 input 16 \ra
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 64 input 17 \rb
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 1 input 18 \xer_so
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+ wire width 2 output 19 \muxid$1
+ attribute \enum_base_type "MicrOp"
+ attribute \enum_value_0000000 "OP_ILLEGAL"
+ attribute \enum_value_0000001 "OP_NOP"
+ attribute \enum_value_0000010 "OP_ADD"
+ attribute \enum_value_0000011 "OP_ADDPCIS"
+ attribute \enum_value_0000100 "OP_AND"
+ attribute \enum_value_0000101 "OP_ATTN"
+ attribute \enum_value_0000110 "OP_B"
+ attribute \enum_value_0000111 "OP_BC"
+ attribute \enum_value_0001000 "OP_BCREG"
+ attribute \enum_value_0001001 "OP_BPERM"
+ attribute \enum_value_0001010 "OP_CMP"
+ attribute \enum_value_0001011 "OP_CMPB"
+ attribute \enum_value_0001100 "OP_CMPEQB"
+ attribute \enum_value_0001101 "OP_CMPRB"
+ attribute \enum_value_0001110 "OP_CNTZ"
+ attribute \enum_value_0001111 "OP_CRAND"
+ attribute \enum_value_0010000 "OP_CRANDC"
+ attribute \enum_value_0010001 "OP_CREQV"
+ attribute \enum_value_0010010 "OP_CRNAND"
+ attribute \enum_value_0010011 "OP_CRNOR"
+ attribute \enum_value_0010100 "OP_CROR"
+ attribute \enum_value_0010101 "OP_CRORC"
+ attribute \enum_value_0010110 "OP_CRXOR"
+ attribute \enum_value_0010111 "OP_DARN"
+ attribute \enum_value_0011000 "OP_DCBF"
+ attribute \enum_value_0011001 "OP_DCBST"
+ attribute \enum_value_0011010 "OP_DCBT"
+ attribute \enum_value_0011011 "OP_DCBTST"
+ attribute \enum_value_0011100 "OP_DCBZ"
+ attribute \enum_value_0011101 "OP_DIV"
+ attribute \enum_value_0011110 "OP_DIVE"
+ attribute \enum_value_0011111 "OP_EXTS"
+ attribute \enum_value_0100000 "OP_EXTSWSLI"
+ attribute \enum_value_0100001 "OP_ICBI"
+ attribute \enum_value_0100010 "OP_ICBT"
+ attribute \enum_value_0100011 "OP_ISEL"
+ attribute \enum_value_0100100 "OP_ISYNC"
+ attribute \enum_value_0100101 "OP_LOAD"
+ attribute \enum_value_0100110 "OP_STORE"
+ attribute \enum_value_0100111 "OP_MADDHD"
+ attribute \enum_value_0101000 "OP_MADDHDU"
+ attribute \enum_value_0101001 "OP_MADDLD"
+ attribute \enum_value_0101010 "OP_MCRF"
+ attribute \enum_value_0101011 "OP_MCRXR"
+ attribute \enum_value_0101100 "OP_MCRXRX"
+ attribute \enum_value_0101101 "OP_MFCR"
+ attribute \enum_value_0101110 "OP_MFSPR"
+ attribute \enum_value_0101111 "OP_MOD"
+ attribute \enum_value_0110000 "OP_MTCRF"
+ attribute \enum_value_0110001 "OP_MTSPR"
+ attribute \enum_value_0110010 "OP_MUL_L64"
+ attribute \enum_value_0110011 "OP_MUL_H64"
+ attribute \enum_value_0110100 "OP_MUL_H32"
+ attribute \enum_value_0110101 "OP_OR"
+ attribute \enum_value_0110110 "OP_POPCNT"
+ attribute \enum_value_0110111 "OP_PRTY"
+ attribute \enum_value_0111000 "OP_RLC"
+ attribute \enum_value_0111001 "OP_RLCL"
+ attribute \enum_value_0111010 "OP_RLCR"
+ attribute \enum_value_0111011 "OP_SETB"
+ attribute \enum_value_0111100 "OP_SHL"
+ attribute \enum_value_0111101 "OP_SHR"
+ attribute \enum_value_0111110 "OP_SYNC"
+ attribute \enum_value_0111111 "OP_TRAP"
+ attribute \enum_value_1000011 "OP_XOR"
+ attribute \enum_value_1000100 "OP_SIM_CONFIG"
+ attribute \enum_value_1000101 "OP_CROP"
+ attribute \enum_value_1000110 "OP_RFID"
+ attribute \enum_value_1000111 "OP_MFMSR"
+ attribute \enum_value_1001000 "OP_MTMSRD"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 7 output 20 \op__insn_type$2
+ attribute \enum_base_type "Function"
+ attribute \enum_value_00000000000 "NONE"
+ attribute \enum_value_00000000010 "ALU"
+ attribute \enum_value_00000000100 "LDST"
+ attribute \enum_value_00000001000 "SHIFT_ROT"
+ attribute \enum_value_00000010000 "LOGICAL"
+ attribute \enum_value_00000100000 "BRANCH"
+ attribute \enum_value_00001000000 "CR"
+ attribute \enum_value_00010000000 "TRAP"
+ attribute \enum_value_00100000000 "MUL"
+ attribute \enum_value_01000000000 "DIV"
+ attribute \enum_value_10000000000 "SPR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 11 output 21 \op__fn_unit$3
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 output 22 \op__imm_data__imm$4
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 23 \op__imm_data__imm_ok$5
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 24 \op__rc__rc$6
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 25 \op__rc__rc_ok$7
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 26 \op__oe__oe$8
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 27 \op__oe__oe_ok$9
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 28 \op__invert_a$10
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 29 \op__zero_a$11
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 30 \op__invert_out$12
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 31 \op__write_cr0$13
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 32 \op__is_32bit$14
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 33 \op__is_signed$15
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 output 34 \op__insn$16
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 64 output 35 \ra$17
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 64 output 36 \rb$18
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 1 output 37 \xer_so$19
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11"
+ wire width 1 output 38 \neg_res
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12"
+ wire width 1 output 39 \neg_res32
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:30"
+ wire width 1 \is_32bit
process $group_0
- assign \shl 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \shl $1 [63:0]
+ assign \is_32bit 1'0
+ assign \is_32bit \op__is_32bit
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:18"
- wire width 64 \shr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:21"
- wire width 8 $4
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:21"
- cell $sub $5
- parameter \A_SIGNED 0
- parameter \A_WIDTH 7
- parameter \B_SIGNED 0
- parameter \B_WIDTH 6
- parameter \Y_WIDTH 8
- connect \A 7'1000000
- connect \B \b
- connect \Y $4
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:31"
+ wire width 1 \sign_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:38"
+ wire width 1 $20
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:38"
+ cell $mux $21
+ parameter \WIDTH 1
+ connect \A \ra [63]
+ connect \B \ra [31]
+ connect \S \op__is_32bit
+ connect \Y $20
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:21"
- wire width 64 $6
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:21"
- cell $sshr $7
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:38"
+ wire width 1 $22
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:38"
+ cell $and $23
parameter \A_SIGNED 0
- parameter \A_WIDTH 64
+ parameter \A_WIDTH 1
parameter \B_SIGNED 0
- parameter \B_WIDTH 8
- parameter \Y_WIDTH 64
- connect \A \a
- connect \B $4
- connect \Y $6
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A $20
+ connect \B \op__is_signed
+ connect \Y $22
end
process $group_1
- assign \shr 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \shr $6
+ assign \sign_a 1'0
+ assign \sign_a $22
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:23"
- wire width 64 $8
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:23"
- cell $or $9
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:32"
+ wire width 1 \sign_b
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:39"
+ wire width 1 $24
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:39"
+ cell $mux $25
+ parameter \WIDTH 1
+ connect \A \rb [63]
+ connect \B \rb [31]
+ connect \S \op__is_32bit
+ connect \Y $24
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:39"
+ wire width 1 $26
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:39"
+ cell $and $27
parameter \A_SIGNED 0
- parameter \A_WIDTH 64
+ parameter \A_WIDTH 1
parameter \B_SIGNED 0
- parameter \B_WIDTH 64
- parameter \Y_WIDTH 64
- connect \A \shl
- connect \B \shr
- connect \Y $8
- end
- process $group_2
- assign \o 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \o $8
- sync init
- end
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe.main.rotator"
-module \rotator
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:43"
- wire width 5 input 0 \me
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:44"
- wire width 5 input 1 \mb
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:45"
- wire width 1 input 2 \mb_extra
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:47"
- wire width 64 input 3 \rs
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:46"
- wire width 64 input 4 \ra
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:48"
- wire width 7 input 5 \shift
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:49"
- wire width 1 input 6 \is_32bit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:51"
- wire width 1 input 7 \arith
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:54"
- wire width 1 input 8 \sign_ext_rs
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:50"
- wire width 1 input 9 \right_shift
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:52"
- wire width 1 input 10 \clear_left
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:53"
- wire width 1 input 11 \clear_right
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:56"
- wire width 64 output 12 \result_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:57"
- wire width 1 output 13 \carry_out_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:8"
- wire width 64 \rotl_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:9"
- wire width 6 \rotl_b
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:11"
- wire width 64 \rotl_o
- cell \rotl \rotl
- connect \a \rotl_a
- connect \b \rotl_b
- connect \o \rotl_o
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:73"
- wire width 32 \hi32
- process $group_0
- assign \hi32 32'00000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:77"
- switch { \sign_ext_rs \is_32bit }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:77"
- case 2'-1
- assign \hi32 \rs [31:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:79"
- case 2'1-
- assign \hi32 { \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:82"
- case
- assign \hi32 \rs [63:32]
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:74"
- wire width 64 \repl32
- process $group_1
- assign \repl32 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \repl32 { \hi32 \rs [31:0] }
- sync init
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A $24
+ connect \B \op__is_signed
+ connect \Y $26
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:86"
- wire width 6 \shift_signed
process $group_2
- assign \shift_signed 6'000000
- assign \shift_signed \shift [5:0]
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:65"
- wire width 6 \rot_count
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:91"
- wire width 7 $1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:91"
- wire width 7 $2
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:91"
- cell $neg $3
- parameter \A_SIGNED 1
- parameter \A_WIDTH 6
- parameter \Y_WIDTH 7
- connect \A \shift_signed
- connect \Y $2
- end
- connect $1 $2
- process $group_3
- assign \rot_count 6'000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:90"
- switch { \right_shift }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:90"
- case 1'1
- assign \rot_count $1 [5:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:92"
- case
- assign \rot_count \shift [5:0]
- end
- sync init
- end
- process $group_4
- assign \rotl_a 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \rotl_a \repl32
- sync init
- end
- process $group_5
- assign \rotl_b 6'000000
- assign \rotl_b \rot_count
+ assign \sign_b 1'0
+ assign \sign_b $26
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:66"
- wire width 64 \rot
- process $group_6
- assign \rot 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \rot \rotl_o
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:67"
- wire width 7 \sh
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:102"
- wire width 1 $4
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:102"
- cell $not $5
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \is_32bit
- connect \Y $4
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:102"
- wire width 1 $6
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:102"
- cell $and $7
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:33"
+ wire width 1 \sign32_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:40"
+ wire width 1 $28
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:40"
+ cell $and $29
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \shift [6]
- connect \B $4
- connect \Y $6
+ connect \A \ra [31]
+ connect \B \op__is_signed
+ connect \Y $28
end
- process $group_7
- assign \sh 7'0000000
- assign \sh { $6 \shift [5:0] }
+ process $group_3
+ assign \sign32_a 1'0
+ assign \sign32_a $28
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:68"
- wire width 7 \mb$8
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:44"
- wire width 7 $9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:44"
- cell $pos $10
- parameter \A_SIGNED 0
- parameter \A_WIDTH 5
- parameter \Y_WIDTH 7
- connect \A \mb
- connect \Y $9
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:118"
- wire width 1 $11
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:118"
- cell $not $12
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:34"
+ wire width 1 \sign32_b
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:41"
+ wire width 1 $30
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:41"
+ cell $and $31
parameter \A_SIGNED 0
parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \sh [5]
- connect \Y $11
+ connect \A \rb [31]
+ connect \B \op__is_signed
+ connect \Y $30
end
- process $group_8
- assign \mb$8 7'0000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:108"
- switch { \right_shift \clear_left }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:108"
- case 2'-1
- assign \mb$8 $9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:110"
- switch { \is_32bit }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:110"
- case 1'1
- assign \mb$8 [6:5] 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:112"
- case
- assign \mb$8 [6:5] { 1'0 \mb_extra }
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:114"
- case 2'1-
- assign \mb$8 \sh
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:117"
- switch { \is_32bit }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:117"
- case 1'1
- assign \mb$8 [6:5] { \sh [5] $11 }
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:119"
- case
- assign \mb$8 { 1'0 \is_32bit 5'00000 }
- end
+ process $group_4
+ assign \sign32_b 1'0
+ assign \sign32_b $30
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:69"
- wire width 7 \me$13
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:123"
- wire width 1 $14
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:123"
- cell $and $15
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:44"
+ wire width 1 $32
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:44"
+ cell $xor $33
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \clear_right
- connect \B \is_32bit
- connect \Y $14
+ connect \A \sign_a
+ connect \B \sign_b
+ connect \Y $32
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:126"
- wire width 1 $16
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:126"
- cell $not $17
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \clear_left
- connect \Y $16
+ process $group_5
+ assign \neg_res 1'0
+ assign \neg_res $32
+ sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:126"
- wire width 1 $18
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:126"
- cell $and $19
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:45"
+ wire width 1 $34
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:45"
+ cell $xor $35
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \clear_right
- connect \B $16
- connect \Y $18
+ connect \A \sign32_a
+ connect \B \sign32_b
+ connect \Y $34
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:131"
- wire width 6 $20
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:131"
- cell $not $21
- parameter \A_SIGNED 0
- parameter \A_WIDTH 6
- parameter \Y_WIDTH 6
- connect \A \sh [5:0]
- connect \Y $20
+ process $group_6
+ assign \neg_res32 1'0
+ assign \neg_res32 $34
+ sync init
end
- process $group_9
- assign \me$13 7'0000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:123"
- switch { $18 $14 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:123"
- case 2'-1
- assign \me$13 { 2'01 \me }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:126"
- case 2'1-
- assign \me$13 { 1'0 \mb_extra \mb }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:129"
- case
- assign \me$13 { \sh [6] $20 }
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:12"
- wire width 64 \right_mask
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:13"
- wire width 1 $22
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:13"
- cell $le $23
- parameter \A_SIGNED 0
- parameter \A_WIDTH 7
- parameter \B_SIGNED 0
- parameter \B_WIDTH 7
- parameter \Y_WIDTH 1
- connect \A \mb$8
- connect \B 7'1000000
- connect \Y $22
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:14"
- wire width 257 $24
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:14"
- wire width 8 $25
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:14"
- cell $sub $26
- parameter \A_SIGNED 0
- parameter \A_WIDTH 7
- parameter \B_SIGNED 0
- parameter \B_WIDTH 7
- parameter \Y_WIDTH 8
- connect \A 7'1000000
- connect \B \mb$8
- connect \Y $25
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:14"
- wire width 256 $27
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:14"
- cell $sshl $28
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 8
- parameter \Y_WIDTH 256
- connect \A 1'1
- connect \B $25
- connect \Y $27
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:14"
- wire width 257 $29
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:14"
- cell $sub $30
- parameter \A_SIGNED 0
- parameter \A_WIDTH 256
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 257
- connect \A $27
- connect \B 1'1
- connect \Y $29
- end
- connect $24 $29
- process $group_10
- assign \right_mask 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:13"
- switch { $22 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:13"
- case 1'1
- assign \right_mask $24 [63:0]
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:70"
- wire width 64 \mr
- process $group_11
- assign \mr 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \mr \right_mask
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:18"
- wire width 64 \left_mask
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:19"
- wire width 257 $31
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:19"
- wire width 257 $32
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:19"
- wire width 8 $33
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:19"
- cell $sub $34
- parameter \A_SIGNED 0
- parameter \A_WIDTH 6
- parameter \B_SIGNED 0
- parameter \B_WIDTH 7
- parameter \Y_WIDTH 8
- connect \A 6'111111
- connect \B \me$13
- connect \Y $33
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:19"
- wire width 256 $35
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:19"
- cell $sshl $36
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 8
- parameter \Y_WIDTH 256
- connect \A 1'1
- connect \B $33
- connect \Y $35
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:19"
- wire width 257 $37
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:19"
- cell $sub $38
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:50"
+ wire width 64 \abs_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:52"
+ wire width 65 $36
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:52"
+ wire width 65 $37
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:52"
+ cell $neg $38
parameter \A_SIGNED 0
- parameter \A_WIDTH 256
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 257
- connect \A $35
- connect \B 1'1
+ parameter \A_WIDTH 64
+ parameter \Y_WIDTH 65
+ connect \A \ra
connect \Y $37
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:19"
- cell $not $39
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 65 $39
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ cell $pos $40
parameter \A_SIGNED 0
- parameter \A_WIDTH 257
- parameter \Y_WIDTH 257
- connect \A $37
- connect \Y $32
+ parameter \A_WIDTH 64
+ parameter \Y_WIDTH 65
+ connect \A \ra
+ connect \Y $39
end
- connect $31 $32
- process $group_12
- assign \left_mask 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \left_mask $31 [63:0]
- sync init
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:52"
+ wire width 65 $41
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:52"
+ cell $mux $42
+ parameter \WIDTH 65
+ connect \A $39
+ connect \B $37
+ connect \S \sign_a
+ connect \Y $41
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:71"
- wire width 64 \ml
- process $group_13
- assign \ml 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \ml \left_mask
+ connect $36 $41
+ process $group_7
+ assign \abs_a 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \abs_a $36 [63:0]
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:72"
- wire width 2 \output_mode
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:142"
- wire width 1 $40
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:142"
- cell $not $41
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \clear_right
- connect \Y $40
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:142"
- wire width 1 $42
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:142"
- cell $and $43
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \clear_left
- connect \B $40
- connect \Y $42
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:142"
- wire width 1 $44
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:142"
- cell $or $45
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:51"
+ wire width 64 \abs_b
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:53"
+ wire width 65 $43
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:53"
+ wire width 65 $44
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:53"
+ cell $neg $45
parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A $42
- connect \B \right_shift
+ parameter \A_WIDTH 64
+ parameter \Y_WIDTH 65
+ connect \A \rb
connect \Y $44
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:143"
- wire width 1 $46
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:143"
- cell $and $47
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 65 $46
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ cell $pos $47
parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \arith
- connect \B \repl32 [63]
+ parameter \A_WIDTH 64
+ parameter \Y_WIDTH 65
+ connect \A \rb
connect \Y $46
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:145"
- wire width 1 $48
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:145"
- cell $gt $49
- parameter \A_SIGNED 0
- parameter \A_WIDTH 6
- parameter \B_SIGNED 0
- parameter \B_WIDTH 6
- parameter \Y_WIDTH 1
- connect \A \mb$8 [5:0]
- connect \B \me$13 [5:0]
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:53"
+ wire width 65 $48
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:53"
+ cell $mux $49
+ parameter \WIDTH 65
+ connect \A $46
+ connect \B $44
+ connect \S \sign_b
connect \Y $48
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:145"
- wire width 1 $50
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:145"
- cell $and $51
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \clear_right
- connect \B $48
+ connect $43 $48
+ process $group_8
+ assign \abs_b 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \abs_b $43 [63:0]
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:34"
+ wire width 32 $50
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:34"
+ cell $mux $51
+ parameter \WIDTH 32
+ connect \A \abs_a [63:32]
+ connect \B 32'00000000000000000000000000000000
+ connect \S \is_32bit
connect \Y $50
end
- process $group_14
- assign \output_mode 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:142"
- switch { $44 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:142"
- case 1'1
- assign \output_mode { 1'1 $46 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:144"
- case
- assign \output_mode { 1'0 $50 }
- end
+ process $group_9
+ assign \ra$17 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \ra$17 [31:0] \abs_a [31:0]
+ assign \ra$17 [63:32] $50
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:151"
- wire width 64 $52
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:151"
- cell $and $53
- parameter \A_SIGNED 0
- parameter \A_WIDTH 64
- parameter \B_SIGNED 0
- parameter \B_WIDTH 64
- parameter \Y_WIDTH 64
- connect \A \mr
- connect \B \ml
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:34"
+ wire width 32 $52
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:34"
+ cell $mux $53
+ parameter \WIDTH 32
+ connect \A \abs_b [63:32]
+ connect \B 32'00000000000000000000000000000000
+ connect \S \is_32bit
connect \Y $52
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:151"
- wire width 64 $54
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:151"
- cell $and $55
- parameter \A_SIGNED 0
- parameter \A_WIDTH 64
- parameter \B_SIGNED 0
- parameter \B_WIDTH 64
- parameter \Y_WIDTH 64
- connect \A \rot
- connect \B $52
- connect \Y $54
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:151"
- wire width 64 $56
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:151"
- wire width 64 $57
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:151"
- cell $and $58
- parameter \A_SIGNED 0
- parameter \A_WIDTH 64
- parameter \B_SIGNED 0
- parameter \B_WIDTH 64
- parameter \Y_WIDTH 64
- connect \A \mr
- connect \B \ml
- connect \Y $57
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:151"
- cell $not $59
- parameter \A_SIGNED 0
- parameter \A_WIDTH 64
- parameter \Y_WIDTH 64
- connect \A $57
- connect \Y $56
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:151"
- wire width 64 $60
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:151"
- cell $and $61
- parameter \A_SIGNED 0
- parameter \A_WIDTH 64
- parameter \B_SIGNED 0
- parameter \B_WIDTH 64
- parameter \Y_WIDTH 64
- connect \A \ra
- connect \B $56
- connect \Y $60
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:151"
- wire width 64 $62
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:151"
- cell $or $63
- parameter \A_SIGNED 0
- parameter \A_WIDTH 64
- parameter \B_SIGNED 0
- parameter \B_WIDTH 64
- parameter \Y_WIDTH 64
- connect \A $54
- connect \B $60
- connect \Y $62
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:153"
- wire width 64 $64
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:153"
- cell $or $65
- parameter \A_SIGNED 0
- parameter \A_WIDTH 64
- parameter \B_SIGNED 0
- parameter \B_WIDTH 64
- parameter \Y_WIDTH 64
- connect \A \mr
- connect \B \ml
- connect \Y $64
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:153"
- wire width 64 $66
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:153"
- cell $and $67
- parameter \A_SIGNED 0
- parameter \A_WIDTH 64
- parameter \B_SIGNED 0
- parameter \B_WIDTH 64
- parameter \Y_WIDTH 64
- connect \A \rot
- connect \B $64
- connect \Y $66
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:153"
- wire width 64 $68
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:153"
- wire width 64 $69
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:153"
- cell $or $70
- parameter \A_SIGNED 0
- parameter \A_WIDTH 64
- parameter \B_SIGNED 0
- parameter \B_WIDTH 64
- parameter \Y_WIDTH 64
- connect \A \mr
- connect \B \ml
- connect \Y $69
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:153"
- cell $not $71
- parameter \A_SIGNED 0
- parameter \A_WIDTH 64
- parameter \Y_WIDTH 64
- connect \A $69
- connect \Y $68
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:153"
- wire width 64 $72
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:153"
- cell $and $73
- parameter \A_SIGNED 0
- parameter \A_WIDTH 64
- parameter \B_SIGNED 0
- parameter \B_WIDTH 64
- parameter \Y_WIDTH 64
- connect \A \ra
- connect \B $68
- connect \Y $72
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:153"
- wire width 64 $74
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:153"
- cell $or $75
- parameter \A_SIGNED 0
- parameter \A_WIDTH 64
- parameter \B_SIGNED 0
- parameter \B_WIDTH 64
- parameter \Y_WIDTH 64
- connect \A $66
- connect \B $72
- connect \Y $74
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:155"
- wire width 64 $76
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:155"
- cell $and $77
- parameter \A_SIGNED 0
- parameter \A_WIDTH 64
- parameter \B_SIGNED 0
- parameter \B_WIDTH 64
- parameter \Y_WIDTH 64
- connect \A \rot
- connect \B \mr
- connect \Y $76
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:157"
- wire width 64 $78
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:157"
- cell $not $79
- parameter \A_SIGNED 0
- parameter \A_WIDTH 64
- parameter \Y_WIDTH 64
- connect \A \mr
- connect \Y $78
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:157"
- wire width 64 $80
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:157"
- cell $or $81
- parameter \A_SIGNED 0
- parameter \A_WIDTH 64
- parameter \B_SIGNED 0
- parameter \B_WIDTH 64
- parameter \Y_WIDTH 64
- connect \A \rot
- connect \B $78
- connect \Y $80
- end
- process $group_15
- assign \result_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:149"
- switch \output_mode
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:150"
- case 2'00
- assign \result_o $62
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:152"
- case 2'01
- assign \result_o $74
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:154"
- case 2'10
- assign \result_o $76
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:156"
- case 2'11
- assign \result_o $80
- end
+ process $group_10
+ assign \rb$18 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \rb$18 [31:0] \abs_b [31:0]
+ assign \rb$18 [63:32] $52
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:159"
- wire width 1 $82
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:159"
- wire width 64 $83
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:159"
- cell $not $84
- parameter \A_SIGNED 0
- parameter \A_WIDTH 64
- parameter \Y_WIDTH 64
- connect \A \ml
- connect \Y $83
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:159"
- wire width 64 $85
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:159"
- cell $and $86
- parameter \A_SIGNED 0
- parameter \A_WIDTH 64
- parameter \B_SIGNED 0
- parameter \B_WIDTH 64
- parameter \Y_WIDTH 64
- connect \A \rs
- connect \B $83
- connect \Y $85
+ process $group_11
+ assign \xer_so$19 1'0
+ assign \xer_so$19 \xer_so
+ sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:159"
- cell $reduce_bool $87
- parameter \A_SIGNED 0
- parameter \A_WIDTH 64
- parameter \Y_WIDTH 1
- connect \A $85
- connect \Y $82
+ process $group_12
+ assign \muxid$1 2'00
+ assign \muxid$1 \muxid
+ sync init
end
- process $group_16
- assign \carry_out_o 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:149"
- switch \output_mode
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:150"
- case 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:152"
- case 2'01
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:154"
- case 2'10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:156"
- case 2'11
- assign \carry_out_o $82
- end
+ process $group_13
+ assign \op__insn_type$2 7'0000000
+ assign \op__fn_unit$3 11'00000000000
+ assign \op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \op__imm_data__imm_ok$5 1'0
+ assign \op__rc__rc$6 1'0
+ assign \op__rc__rc_ok$7 1'0
+ assign \op__oe__oe$8 1'0
+ assign \op__oe__oe_ok$9 1'0
+ assign \op__invert_a$10 1'0
+ assign \op__zero_a$11 1'0
+ assign \op__invert_out$12 1'0
+ assign \op__write_cr0$13 1'0
+ assign \op__is_32bit$14 1'0
+ assign \op__is_signed$15 1'0
+ assign \op__insn$16 32'00000000000000000000000000000000
+ assign { \op__insn$16 \op__is_signed$15 \op__is_32bit$14 \op__write_cr0$13 \op__invert_out$12 \op__zero_a$11 \op__invert_a$10 { \op__oe__oe_ok$9 \op__oe__oe$8 } { \op__rc__rc_ok$7 \op__rc__rc$6 } { \op__imm_data__imm_ok$5 \op__imm_data__imm$4 } \op__fn_unit$3 \op__insn_type$2 } { \op__insn \op__is_signed \op__is_32bit \op__write_cr0 \op__invert_out \op__zero_a \op__invert_a { \op__oe__oe_ok \op__oe__oe } { \op__rc__rc_ok \op__rc__rc } { \op__imm_data__imm_ok \op__imm_data__imm } \op__fn_unit \op__insn_type }
sync init
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe.main"
-module \main$76
- attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
- wire width 2 input 0 \muxid
- attribute \enum_base_type "InternalOp"
+attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe1"
+module \mul_pipe1
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
+ wire width 1 input 0 \rst
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
+ wire width 1 input 1 \clk
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
+ wire width 1 output 2 \n_valid_o
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
+ wire width 1 input 3 \n_ready_i
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+ wire width 2 output 4 \muxid
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+ wire width 2 \muxid$next
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 7 input 1 \op__insn_type
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 7 output 5 \op__insn_type
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 7 \op__insn_type$next
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00000000010 "ALU"
attribute \enum_value_00100000000 "MUL"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 11 input 2 \op__fn_unit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 64 input 3 \op__imm_data__imm
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 input 4 \op__imm_data__imm_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 input 5 \op__rc__rc
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 input 6 \op__rc__rc_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 input 7 \op__oe__oe
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 input 8 \op__oe__oe_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 3 input 9 \op__write_cr__data
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 input 10 \op__write_cr__ok
- attribute \enum_base_type "CryIn"
- attribute \enum_value_00 "ZERO"
- attribute \enum_value_01 "ONE"
- attribute \enum_value_10 "CA"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 2 input 11 \op__input_carry
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 input 12 \op__output_carry
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 input 13 \op__input_cr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 input 14 \op__output_cr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 input 15 \op__is_32bit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 input 16 \op__is_signed
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 32 input 17 \op__insn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
- wire width 64 input 18 \ra
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
- wire width 64 input 19 \rb
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
- wire width 64 input 20 \rc
- attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
- wire width 2 output 21 \muxid$1
- attribute \enum_base_type "InternalOp"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 11 output 6 \op__fn_unit
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 11 \op__fn_unit$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 output 7 \op__imm_data__imm
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 \op__imm_data__imm$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 8 \op__imm_data__imm_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__imm_data__imm_ok$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 9 \op__rc__rc
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__rc__rc$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 10 \op__rc__rc_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__rc__rc_ok$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 11 \op__oe__oe
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__oe__oe$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 12 \op__oe__oe_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__oe__oe_ok$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 13 \op__invert_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__invert_a$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 14 \op__zero_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__zero_a$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 15 \op__invert_out
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__invert_out$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 16 \op__write_cr0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__write_cr0$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 17 \op__is_32bit
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__is_32bit$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 18 \op__is_signed
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__is_signed$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 output 19 \op__insn
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 \op__insn$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 64 output 20 \ra
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 64 \ra$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 64 output 21 \rb
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 64 \rb$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 1 output 22 \xer_so
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 1 \xer_so$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11"
+ wire width 1 output 23 \neg_res
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11"
+ wire width 1 \neg_res$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12"
+ wire width 1 output 24 \neg_res32
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12"
+ wire width 1 \neg_res32$next
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153"
+ wire width 1 input 25 \p_valid_i
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154"
+ wire width 1 output 26 \p_ready_o
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+ wire width 2 input 27 \muxid$1
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 7 output 22 \op__insn_type$2
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 7 input 28 \op__insn_type$2
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00000000010 "ALU"
attribute \enum_value_00100000000 "MUL"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 11 output 23 \op__fn_unit$3
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 64 output 24 \op__imm_data__imm$4
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 output 25 \op__imm_data__imm_ok$5
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 output 26 \op__rc__rc$6
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 output 27 \op__rc__rc_ok$7
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 output 28 \op__oe__oe$8
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 output 29 \op__oe__oe_ok$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 3 output 30 \op__write_cr__data$10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 output 31 \op__write_cr__ok$11
- attribute \enum_base_type "CryIn"
- attribute \enum_value_00 "ZERO"
- attribute \enum_value_01 "ONE"
- attribute \enum_value_10 "CA"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 2 output 32 \op__input_carry$12
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 output 33 \op__output_carry$13
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 output 34 \op__input_cr$14
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 output 35 \op__output_cr$15
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 output 36 \op__is_32bit$16
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 output 37 \op__is_signed$17
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 32 output 38 \op__insn$18
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 output 39 \o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 40 \o_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 2 output 41 \xer_ca
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:43"
- wire width 5 \rotator_me
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:44"
- wire width 5 \rotator_mb
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:45"
- wire width 1 \rotator_mb_extra
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:47"
- wire width 64 \rotator_rs
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:46"
- wire width 64 \rotator_ra
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:48"
- wire width 7 \rotator_shift
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:49"
- wire width 1 \rotator_is_32bit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:51"
- wire width 1 \rotator_arith
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:54"
- wire width 1 \rotator_sign_ext_rs
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:50"
- wire width 1 \rotator_right_shift
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:52"
- wire width 1 \rotator_clear_left
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:53"
- wire width 1 \rotator_clear_right
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:56"
- wire width 64 \rotator_result_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:57"
- wire width 1 \rotator_carry_out_o
- cell \rotator \rotator
- connect \me \rotator_me
- connect \mb \rotator_mb
- connect \mb_extra \rotator_mb_extra
- connect \rs \rotator_rs
- connect \ra \rotator_ra
- connect \shift \rotator_shift
- connect \is_32bit \rotator_is_32bit
- connect \arith \rotator_arith
- connect \sign_ext_rs \rotator_sign_ext_rs
- connect \right_shift \rotator_right_shift
- connect \clear_left \rotator_clear_left
- connect \clear_right \rotator_clear_right
- connect \result_o \rotator_result_o
- connect \carry_out_o \rotator_carry_out_o
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:38"
- wire width 5 \mb
- process $group_0
- assign \mb 5'00000
- assign \mb { \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] }
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:39"
- wire width 5 \me
- process $group_1
- assign \me 5'00000
- assign \me { \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] \op__insn [1] }
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:40"
- wire width 1 \mb_extra
- process $group_2
- assign \mb_extra 1'0
- assign \mb_extra { \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] } [0]
- sync init
- end
- process $group_3
- assign \rotator_me 5'00000
- assign \rotator_me \me
- sync init
- end
- process $group_4
- assign \rotator_mb 5'00000
- assign \rotator_mb \mb
- sync init
- end
- process $group_5
- assign \rotator_mb_extra 1'0
- assign \rotator_mb_extra \mb_extra
- sync init
- end
- process $group_6
- assign \rotator_rs 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \rotator_rs \rc
- sync init
- end
- process $group_7
- assign \rotator_ra 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \rotator_ra \ra
- sync init
- end
- process $group_8
- assign \rotator_shift 7'0000000
- assign \rotator_shift \rb [6:0]
- sync init
- end
- process $group_9
- assign \rotator_is_32bit 1'0
- assign \rotator_is_32bit \op__is_32bit
- sync init
- end
- process $group_10
- assign \rotator_arith 1'0
- assign \rotator_arith \op__is_signed
- sync init
- end
- wire width 1 $verilog_initial_trigger
- process $group_11
- assign \rotator_sign_ext_rs 1'0
- assign \rotator_sign_ext_rs 1'0
- assign $verilog_initial_trigger $verilog_initial_trigger
- sync init
- update $verilog_initial_trigger 1'0
- end
- process $group_12
- assign \o_ok 1'0
- assign \o_ok 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:64"
- switch \op__insn_type
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:65"
- attribute \nmigen.decoding "OP_SHL/60"
- case 7'0111100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:66"
- attribute \nmigen.decoding "OP_SHR/61"
- case 7'0111101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:67"
- attribute \nmigen.decoding "OP_RLC/56"
- case 7'0111000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:68"
- attribute \nmigen.decoding "OP_RLCL/57"
- case 7'0111001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:69"
- attribute \nmigen.decoding "OP_RLCR/58"
- case 7'0111010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:70"
- attribute \nmigen.decoding ""
- case
- assign \o_ok 1'0
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:63"
- wire width 3 \mode
- process $group_13
- assign \mode 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:64"
- switch \op__insn_type
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:65"
- attribute \nmigen.decoding "OP_SHL/60"
- case 7'0111100
- assign \mode 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:66"
- attribute \nmigen.decoding "OP_SHR/61"
- case 7'0111101
- assign \mode 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:67"
- attribute \nmigen.decoding "OP_RLC/56"
- case 7'0111000
- assign \mode 3'110
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:68"
- attribute \nmigen.decoding "OP_RLCL/57"
- case 7'0111001
- assign \mode 3'010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:69"
- attribute \nmigen.decoding "OP_RLCR/58"
- case 7'0111010
- assign \mode 3'100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:70"
- attribute \nmigen.decoding ""
- case
- end
- sync init
- end
- process $group_14
- assign \rotator_right_shift 1'0
- assign \rotator_clear_left 1'0
- assign \rotator_clear_right 1'0
- assign { \rotator_clear_right \rotator_clear_left \rotator_right_shift } \mode
- sync init
- end
- process $group_17
- assign \o 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \o \rotator_result_o
- sync init
- end
- process $group_18
- assign \xer_ca 2'00
- assign \xer_ca { \rotator_carry_out_o \rotator_carry_out_o }
- sync init
- end
- process $group_19
- assign \muxid$1 2'00
- assign \muxid$1 \muxid
- sync init
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 11 input 29 \op__fn_unit$3
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 input 30 \op__imm_data__imm$4
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 31 \op__imm_data__imm_ok$5
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 32 \op__rc__rc$6
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 33 \op__rc__rc_ok$7
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 34 \op__oe__oe$8
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 35 \op__oe__oe_ok$9
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 36 \op__invert_a$10
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 37 \op__zero_a$11
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 38 \op__invert_out$12
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 39 \op__write_cr0$13
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 40 \op__is_32bit$14
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 41 \op__is_signed$15
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 input 42 \op__insn$16
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 64 input 43 \ra$17
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 64 input 44 \rb$18
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 1 input 45 \xer_so$19
+ cell \p$72 \p
+ connect \p_valid_i \p_valid_i
+ connect \p_ready_o \p_ready_o
end
- process $group_20
- assign \op__insn_type$2 7'0000000
- assign \op__fn_unit$3 11'00000000000
- assign \op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \op__imm_data__imm_ok$5 1'0
- assign \op__rc__rc$6 1'0
- assign \op__rc__rc_ok$7 1'0
- assign \op__oe__oe$8 1'0
- assign \op__oe__oe_ok$9 1'0
- assign \op__write_cr__data$10 3'000
- assign \op__write_cr__ok$11 1'0
- assign \op__input_carry$12 2'00
- assign \op__output_carry$13 1'0
- assign \op__input_cr$14 1'0
- assign \op__output_cr$15 1'0
- assign \op__is_32bit$16 1'0
- assign \op__is_signed$17 1'0
- assign \op__insn$18 32'00000000000000000000000000000000
- assign { \op__insn$18 \op__is_signed$17 \op__is_32bit$16 \op__output_cr$15 \op__input_cr$14 \op__output_carry$13 \op__input_carry$12 { \op__write_cr__ok$11 \op__write_cr__data$10 } { \op__oe__oe_ok$9 \op__oe__oe$8 } { \op__rc__rc_ok$7 \op__rc__rc$6 } { \op__imm_data__imm_ok$5 \op__imm_data__imm$4 } \op__fn_unit$3 \op__insn_type$2 } { \op__insn \op__is_signed \op__is_32bit \op__output_cr \op__input_cr \op__output_carry \op__input_carry { \op__write_cr__ok \op__write_cr__data } { \op__oe__oe_ok \op__oe__oe } { \op__rc__rc_ok \op__rc__rc } { \op__imm_data__imm_ok \op__imm_data__imm } \op__fn_unit \op__insn_type }
- sync init
+ cell \n$73 \n
+ connect \n_valid_o \n_valid_o
+ connect \n_ready_i \n_ready_i
end
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe.output"
-module \output$77
- attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
- wire width 2 input 0 \muxid
- attribute \enum_base_type "InternalOp"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+ wire width 2 \input_muxid
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 7 input 1 \op__insn_type
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 7 \input_op__insn_type
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00000000010 "ALU"
attribute \enum_value_00100000000 "MUL"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 11 input 2 \op__fn_unit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 64 input 3 \op__imm_data__imm
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 input 4 \op__imm_data__imm_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 input 5 \op__rc__rc
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 input 6 \op__rc__rc_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 input 7 \op__oe__oe
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 input 8 \op__oe__oe_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 3 input 9 \op__write_cr__data
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 input 10 \op__write_cr__ok
- attribute \enum_base_type "CryIn"
- attribute \enum_value_00 "ZERO"
- attribute \enum_value_01 "ONE"
- attribute \enum_value_10 "CA"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 2 input 11 \op__input_carry
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 input 12 \op__output_carry
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 input 13 \op__input_cr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 input 14 \op__output_cr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 input 15 \op__is_32bit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 input 16 \op__is_signed
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 32 input 17 \op__insn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 input 18 \o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 input 19 \o_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 4 input 20 \cr_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 2 input 21 \xer_ca
- attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
- wire width 2 output 22 \muxid$1
- attribute \enum_base_type "InternalOp"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 11 \input_op__fn_unit
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 \input_op__imm_data__imm
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \input_op__imm_data__imm_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \input_op__rc__rc
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \input_op__rc__rc_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \input_op__oe__oe
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \input_op__oe__oe_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \input_op__invert_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \input_op__zero_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \input_op__invert_out
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \input_op__write_cr0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \input_op__is_32bit
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \input_op__is_signed
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 \input_op__insn
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 64 \input_ra
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 64 \input_rb
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 1 \input_xer_so
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+ wire width 2 \input_muxid$20
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 7 output 23 \op__insn_type$2
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 7 \input_op__insn_type$21
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00000000010 "ALU"
attribute \enum_value_00100000000 "MUL"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 11 output 24 \op__fn_unit$3
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 64 output 25 \op__imm_data__imm$4
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 output 26 \op__imm_data__imm_ok$5
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 output 27 \op__rc__rc$6
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 output 28 \op__rc__rc_ok$7
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 output 29 \op__oe__oe$8
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 output 30 \op__oe__oe_ok$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 3 output 31 \op__write_cr__data$10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 output 32 \op__write_cr__ok$11
- attribute \enum_base_type "CryIn"
- attribute \enum_value_00 "ZERO"
- attribute \enum_value_01 "ONE"
- attribute \enum_value_10 "CA"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 2 output 33 \op__input_carry$12
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 output 34 \op__output_carry$13
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 output 35 \op__input_cr$14
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 output 36 \op__output_cr$15
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 output 37 \op__is_32bit$16
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 output 38 \op__is_signed$17
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 32 output 39 \op__insn$18
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 output 40 \o$19
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 41 \o_ok$20
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 4 output 42 \cr_a$21
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 43 \cr_a_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 2 output 44 \xer_ca$22
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 45 \xer_ca_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:19"
- wire width 65 \o$23
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 65 $24
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- cell $pos $25
- parameter \A_SIGNED 0
- parameter \A_WIDTH 64
- parameter \Y_WIDTH 65
- connect \A \o
- connect \Y $24
- end
- process $group_0
- assign \o$23 65'00000000000000000000000000000000000000000000000000000000000000000
- assign \o$23 $24
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29"
- wire width 64 \target
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:251"
- wire width 64 $26
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:251"
- cell $pos $27
- parameter \A_SIGNED 0
- parameter \A_WIDTH 32
- parameter \Y_WIDTH 64
- connect \A \o$23 [31:0]
- connect \Y $26
- end
- process $group_1
- assign \target 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:30"
- switch { \op__is_32bit }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:30"
- case 1'1
- assign \target $26
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:32"
- case
- assign \target \o$23 [63:0]
- end
- sync init
- end
- process $group_2
- assign \xer_ca$22 2'00
- assign \xer_ca$22 \xer_ca
- sync init
- end
- process $group_3
- assign \xer_ca_ok 1'0
- assign \xer_ca_ok \op__output_carry
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:44"
- wire width 1 \is_cmp
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:53"
- wire width 1 $28
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:53"
- cell $eq $29
- parameter \A_SIGNED 0
- parameter \A_WIDTH 7
- parameter \B_SIGNED 0
- parameter \B_WIDTH 7
- parameter \Y_WIDTH 1
- connect \A \op__insn_type
- connect \B 7'0001010
- connect \Y $28
- end
- process $group_4
- assign \is_cmp 1'0
- assign \is_cmp $28
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:45"
- wire width 1 \is_cmpeqb
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:54"
- wire width 1 $30
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:54"
- cell $eq $31
- parameter \A_SIGNED 0
- parameter \A_WIDTH 7
- parameter \B_SIGNED 0
- parameter \B_WIDTH 7
- parameter \Y_WIDTH 1
- connect \A \op__insn_type
- connect \B 7'0001100
- connect \Y $30
- end
- process $group_5
- assign \is_cmpeqb 1'0
- assign \is_cmpeqb $30
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:43"
- wire width 1 \msb_test
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:55"
- wire width 1 $32
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:55"
- cell $xor $33
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \target [63]
- connect \B \is_cmp
- connect \Y $32
- end
- process $group_6
- assign \msb_test 1'0
- assign \msb_test $32
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:40"
- wire width 1 \is_nzero
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:56"
- wire width 1 $34
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:56"
- cell $reduce_bool $35
- parameter \A_SIGNED 0
- parameter \A_WIDTH 64
- parameter \Y_WIDTH 1
- connect \A \target
- connect \Y $34
- end
- process $group_7
- assign \is_nzero 1'0
- assign \is_nzero $34
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41"
- wire width 1 \is_positive
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:57"
- wire width 1 $36
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:57"
- cell $not $37
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \msb_test
- connect \Y $36
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:57"
- wire width 1 $38
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:57"
- cell $and $39
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \is_nzero
- connect \B $36
- connect \Y $38
- end
- process $group_8
- assign \is_positive 1'0
- assign \is_positive $38
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:42"
- wire width 1 \is_negative
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:58"
- wire width 1 $40
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:58"
- cell $and $41
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \is_nzero
- connect \B \msb_test
- connect \Y $40
- end
- process $group_9
- assign \is_negative 1'0
- assign \is_negative $40
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:47"
- wire width 4 \cr0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:46"
- wire width 1 \so
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:63"
- wire width 1 $42
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:63"
- cell $not $43
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \is_nzero
- connect \Y $42
- end
- process $group_10
- assign \cr0 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:60"
- switch { \is_cmpeqb }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:60"
- case 1'1
- assign \cr0 \cr_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:62"
- case
- assign \cr0 { \is_negative \is_positive $42 \so }
- end
- sync init
- end
- process $group_11
- assign \o$19 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \o$19 \o$23 [63:0]
- sync init
- end
- process $group_12
- assign \o_ok$20 1'0
- assign \o_ok$20 \o_ok
- sync init
- end
- process $group_13
- assign \cr_a$21 4'0000
- assign \cr_a$21 \cr0
- sync init
- end
- process $group_14
- assign \cr_a_ok 1'0
- assign \cr_a_ok \op__write_cr__ok
- sync init
- end
- process $group_15
- assign \muxid$1 2'00
- assign \muxid$1 \muxid
- sync init
- end
- process $group_16
- assign \op__insn_type$2 7'0000000
- assign \op__fn_unit$3 11'00000000000
- assign \op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \op__imm_data__imm_ok$5 1'0
- assign \op__rc__rc$6 1'0
- assign \op__rc__rc_ok$7 1'0
- assign \op__oe__oe$8 1'0
- assign \op__oe__oe_ok$9 1'0
- assign \op__write_cr__data$10 3'000
- assign \op__write_cr__ok$11 1'0
- assign \op__input_carry$12 2'00
- assign \op__output_carry$13 1'0
- assign \op__input_cr$14 1'0
- assign \op__output_cr$15 1'0
- assign \op__is_32bit$16 1'0
- assign \op__is_signed$17 1'0
- assign \op__insn$18 32'00000000000000000000000000000000
- assign { \op__insn$18 \op__is_signed$17 \op__is_32bit$16 \op__output_cr$15 \op__input_cr$14 \op__output_carry$13 \op__input_carry$12 { \op__write_cr__ok$11 \op__write_cr__data$10 } { \op__oe__oe_ok$9 \op__oe__oe$8 } { \op__rc__rc_ok$7 \op__rc__rc$6 } { \op__imm_data__imm_ok$5 \op__imm_data__imm$4 } \op__fn_unit$3 \op__insn_type$2 } { \op__insn \op__is_signed \op__is_32bit \op__output_cr \op__input_cr \op__output_carry \op__input_carry { \op__write_cr__ok \op__write_cr__data } { \op__oe__oe_ok \op__oe__oe } { \op__rc__rc_ok \op__rc__rc } { \op__imm_data__imm_ok \op__imm_data__imm } \op__fn_unit \op__insn_type }
- sync init
- end
- connect \so 1'0
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe"
-module \pipe$72
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
- wire width 1 input 0 \rst
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
- wire width 1 input 1 \clk
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151"
- wire width 1 input 2 \p_valid_i
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152"
- wire width 1 output 3 \p_ready_o
- attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
- wire width 2 input 4 \muxid
- attribute \enum_base_type "InternalOp"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 11 \input_op__fn_unit$22
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 \input_op__imm_data__imm$23
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \input_op__imm_data__imm_ok$24
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \input_op__rc__rc$25
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \input_op__rc__rc_ok$26
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \input_op__oe__oe$27
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \input_op__oe__oe_ok$28
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \input_op__invert_a$29
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \input_op__zero_a$30
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \input_op__invert_out$31
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \input_op__write_cr0$32
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \input_op__is_32bit$33
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \input_op__is_signed$34
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 \input_op__insn$35
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 64 \input_ra$36
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 64 \input_rb$37
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 1 \input_xer_so$38
+ cell \input$74 \input
+ connect \muxid \input_muxid
+ connect \op__insn_type \input_op__insn_type
+ connect \op__fn_unit \input_op__fn_unit
+ connect \op__imm_data__imm \input_op__imm_data__imm
+ connect \op__imm_data__imm_ok \input_op__imm_data__imm_ok
+ connect \op__rc__rc \input_op__rc__rc
+ connect \op__rc__rc_ok \input_op__rc__rc_ok
+ connect \op__oe__oe \input_op__oe__oe
+ connect \op__oe__oe_ok \input_op__oe__oe_ok
+ connect \op__invert_a \input_op__invert_a
+ connect \op__zero_a \input_op__zero_a
+ connect \op__invert_out \input_op__invert_out
+ connect \op__write_cr0 \input_op__write_cr0
+ connect \op__is_32bit \input_op__is_32bit
+ connect \op__is_signed \input_op__is_signed
+ connect \op__insn \input_op__insn
+ connect \ra \input_ra
+ connect \rb \input_rb
+ connect \xer_so \input_xer_so
+ connect \muxid$1 \input_muxid$20
+ connect \op__insn_type$2 \input_op__insn_type$21
+ connect \op__fn_unit$3 \input_op__fn_unit$22
+ connect \op__imm_data__imm$4 \input_op__imm_data__imm$23
+ connect \op__imm_data__imm_ok$5 \input_op__imm_data__imm_ok$24
+ connect \op__rc__rc$6 \input_op__rc__rc$25
+ connect \op__rc__rc_ok$7 \input_op__rc__rc_ok$26
+ connect \op__oe__oe$8 \input_op__oe__oe$27
+ connect \op__oe__oe_ok$9 \input_op__oe__oe_ok$28
+ connect \op__invert_a$10 \input_op__invert_a$29
+ connect \op__zero_a$11 \input_op__zero_a$30
+ connect \op__invert_out$12 \input_op__invert_out$31
+ connect \op__write_cr0$13 \input_op__write_cr0$32
+ connect \op__is_32bit$14 \input_op__is_32bit$33
+ connect \op__is_signed$15 \input_op__is_signed$34
+ connect \op__insn$16 \input_op__insn$35
+ connect \ra$17 \input_ra$36
+ connect \rb$18 \input_rb$37
+ connect \xer_so$19 \input_xer_so$38
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+ wire width 2 \mul1_muxid
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 7 input 5 \op__insn_type
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 7 \mul1_op__insn_type
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00000000010 "ALU"
attribute \enum_value_00100000000 "MUL"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 11 input 6 \op__fn_unit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 64 input 7 \op__imm_data__imm
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 input 8 \op__imm_data__imm_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 input 9 \op__rc__rc
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 input 10 \op__rc__rc_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 input 11 \op__oe__oe
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 input 12 \op__oe__oe_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 3 input 13 \op__write_cr__data
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 input 14 \op__write_cr__ok
- attribute \enum_base_type "CryIn"
- attribute \enum_value_00 "ZERO"
- attribute \enum_value_01 "ONE"
- attribute \enum_value_10 "CA"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 2 input 15 \op__input_carry
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 input 16 \op__output_carry
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 input 17 \op__input_cr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 input 18 \op__output_cr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 input 19 \op__is_32bit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 input 20 \op__is_signed
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 32 input 21 \op__insn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
- wire width 64 input 22 \ra
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
- wire width 64 input 23 \rb
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
- wire width 64 input 24 \rc
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
- wire width 2 input 25 \xer_ca
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244"
- wire width 1 output 26 \n_valid_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245"
- wire width 1 input 27 \n_ready_i
- attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
- wire width 2 output 28 \muxid$1
- attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
- wire width 2 \muxid$1$next
- attribute \enum_base_type "InternalOp"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 11 \mul1_op__fn_unit
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 \mul1_op__imm_data__imm
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \mul1_op__imm_data__imm_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \mul1_op__rc__rc
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \mul1_op__rc__rc_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \mul1_op__oe__oe
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \mul1_op__oe__oe_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \mul1_op__invert_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \mul1_op__zero_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \mul1_op__invert_out
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \mul1_op__write_cr0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \mul1_op__is_32bit
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \mul1_op__is_signed
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 \mul1_op__insn
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 64 \mul1_ra
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 64 \mul1_rb
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 1 \mul1_xer_so
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+ wire width 2 \mul1_muxid$39
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 7 output 29 \op__insn_type$2
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 7 \op__insn_type$2$next
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 7 \mul1_op__insn_type$40
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00000000010 "ALU"
attribute \enum_value_00100000000 "MUL"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 11 output 30 \op__fn_unit$3
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 11 \op__fn_unit$3$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 64 output 31 \op__imm_data__imm$4
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 64 \op__imm_data__imm$4$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 output 32 \op__imm_data__imm_ok$5
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 \op__imm_data__imm_ok$5$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 output 33 \op__rc__rc$6
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 \op__rc__rc$6$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 output 34 \op__rc__rc_ok$7
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 \op__rc__rc_ok$7$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 output 35 \op__oe__oe$8
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 \op__oe__oe$8$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 output 36 \op__oe__oe_ok$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 \op__oe__oe_ok$9$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 3 output 37 \op__write_cr__data$10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 3 \op__write_cr__data$10$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 output 38 \op__write_cr__ok$11
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 \op__write_cr__ok$11$next
- attribute \enum_base_type "CryIn"
- attribute \enum_value_00 "ZERO"
- attribute \enum_value_01 "ONE"
- attribute \enum_value_10 "CA"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 2 output 39 \op__input_carry$12
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 2 \op__input_carry$12$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 output 40 \op__output_carry$13
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 \op__output_carry$13$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 output 41 \op__input_cr$14
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 \op__input_cr$14$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 output 42 \op__output_cr$15
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 \op__output_cr$15$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 output 43 \op__is_32bit$16
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 \op__is_32bit$16$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 output 44 \op__is_signed$17
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 \op__is_signed$17$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 32 output 45 \op__insn$18
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 32 \op__insn$18$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 output 46 \o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 \o$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 47 \o_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 \o_ok$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 4 output 48 \cr_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 4 \cr_a$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 49 \cr_a_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 \cr_a_ok$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 2 output 50 \xer_ca$19
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 2 \xer_ca$19$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 51 \xer_ca_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 \xer_ca_ok$next
- cell \p$73 \p
- connect \p_valid_i \p_valid_i
- connect \p_ready_o \p_ready_o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 11 \mul1_op__fn_unit$41
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 \mul1_op__imm_data__imm$42
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \mul1_op__imm_data__imm_ok$43
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \mul1_op__rc__rc$44
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \mul1_op__rc__rc_ok$45
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \mul1_op__oe__oe$46
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \mul1_op__oe__oe_ok$47
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \mul1_op__invert_a$48
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \mul1_op__zero_a$49
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \mul1_op__invert_out$50
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \mul1_op__write_cr0$51
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \mul1_op__is_32bit$52
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \mul1_op__is_signed$53
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 \mul1_op__insn$54
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 64 \mul1_ra$55
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 64 \mul1_rb$56
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 1 \mul1_xer_so$57
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11"
+ wire width 1 \mul1_neg_res
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12"
+ wire width 1 \mul1_neg_res32
+ cell \mul1 \mul1
+ connect \muxid \mul1_muxid
+ connect \op__insn_type \mul1_op__insn_type
+ connect \op__fn_unit \mul1_op__fn_unit
+ connect \op__imm_data__imm \mul1_op__imm_data__imm
+ connect \op__imm_data__imm_ok \mul1_op__imm_data__imm_ok
+ connect \op__rc__rc \mul1_op__rc__rc
+ connect \op__rc__rc_ok \mul1_op__rc__rc_ok
+ connect \op__oe__oe \mul1_op__oe__oe
+ connect \op__oe__oe_ok \mul1_op__oe__oe_ok
+ connect \op__invert_a \mul1_op__invert_a
+ connect \op__zero_a \mul1_op__zero_a
+ connect \op__invert_out \mul1_op__invert_out
+ connect \op__write_cr0 \mul1_op__write_cr0
+ connect \op__is_32bit \mul1_op__is_32bit
+ connect \op__is_signed \mul1_op__is_signed
+ connect \op__insn \mul1_op__insn
+ connect \ra \mul1_ra
+ connect \rb \mul1_rb
+ connect \xer_so \mul1_xer_so
+ connect \muxid$1 \mul1_muxid$39
+ connect \op__insn_type$2 \mul1_op__insn_type$40
+ connect \op__fn_unit$3 \mul1_op__fn_unit$41
+ connect \op__imm_data__imm$4 \mul1_op__imm_data__imm$42
+ connect \op__imm_data__imm_ok$5 \mul1_op__imm_data__imm_ok$43
+ connect \op__rc__rc$6 \mul1_op__rc__rc$44
+ connect \op__rc__rc_ok$7 \mul1_op__rc__rc_ok$45
+ connect \op__oe__oe$8 \mul1_op__oe__oe$46
+ connect \op__oe__oe_ok$9 \mul1_op__oe__oe_ok$47
+ connect \op__invert_a$10 \mul1_op__invert_a$48
+ connect \op__zero_a$11 \mul1_op__zero_a$49
+ connect \op__invert_out$12 \mul1_op__invert_out$50
+ connect \op__write_cr0$13 \mul1_op__write_cr0$51
+ connect \op__is_32bit$14 \mul1_op__is_32bit$52
+ connect \op__is_signed$15 \mul1_op__is_signed$53
+ connect \op__insn$16 \mul1_op__insn$54
+ connect \ra$17 \mul1_ra$55
+ connect \rb$18 \mul1_rb$56
+ connect \xer_so$19 \mul1_xer_so$57
+ connect \neg_res \mul1_neg_res
+ connect \neg_res32 \mul1_neg_res32
end
- cell \n$74 \n
- connect \n_valid_o \n_valid_o
- connect \n_ready_i \n_ready_i
+ process $group_0
+ assign \input_muxid 2'00
+ assign \input_muxid \muxid$1
+ sync init
end
- attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
- wire width 2 \input_muxid
- attribute \enum_base_type "InternalOp"
+ process $group_1
+ assign \input_op__insn_type 7'0000000
+ assign \input_op__fn_unit 11'00000000000
+ assign \input_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \input_op__imm_data__imm_ok 1'0
+ assign \input_op__rc__rc 1'0
+ assign \input_op__rc__rc_ok 1'0
+ assign \input_op__oe__oe 1'0
+ assign \input_op__oe__oe_ok 1'0
+ assign \input_op__invert_a 1'0
+ assign \input_op__zero_a 1'0
+ assign \input_op__invert_out 1'0
+ assign \input_op__write_cr0 1'0
+ assign \input_op__is_32bit 1'0
+ assign \input_op__is_signed 1'0
+ assign \input_op__insn 32'00000000000000000000000000000000
+ assign { \input_op__insn \input_op__is_signed \input_op__is_32bit \input_op__write_cr0 \input_op__invert_out \input_op__zero_a \input_op__invert_a { \input_op__oe__oe_ok \input_op__oe__oe } { \input_op__rc__rc_ok \input_op__rc__rc } { \input_op__imm_data__imm_ok \input_op__imm_data__imm } \input_op__fn_unit \input_op__insn_type } { \op__insn$16 \op__is_signed$15 \op__is_32bit$14 \op__write_cr0$13 \op__invert_out$12 \op__zero_a$11 \op__invert_a$10 { \op__oe__oe_ok$9 \op__oe__oe$8 } { \op__rc__rc_ok$7 \op__rc__rc$6 } { \op__imm_data__imm_ok$5 \op__imm_data__imm$4 } \op__fn_unit$3 \op__insn_type$2 }
+ sync init
+ end
+ process $group_16
+ assign \input_ra 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \input_ra \ra$17
+ sync init
+ end
+ process $group_17
+ assign \input_rb 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \input_rb \rb$18
+ sync init
+ end
+ process $group_18
+ assign \input_xer_so 1'0
+ assign \input_xer_so \xer_so$19
+ sync init
+ end
+ process $group_19
+ assign \mul1_muxid 2'00
+ assign \mul1_muxid \input_muxid$20
+ sync init
+ end
+ process $group_20
+ assign \mul1_op__insn_type 7'0000000
+ assign \mul1_op__fn_unit 11'00000000000
+ assign \mul1_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \mul1_op__imm_data__imm_ok 1'0
+ assign \mul1_op__rc__rc 1'0
+ assign \mul1_op__rc__rc_ok 1'0
+ assign \mul1_op__oe__oe 1'0
+ assign \mul1_op__oe__oe_ok 1'0
+ assign \mul1_op__invert_a 1'0
+ assign \mul1_op__zero_a 1'0
+ assign \mul1_op__invert_out 1'0
+ assign \mul1_op__write_cr0 1'0
+ assign \mul1_op__is_32bit 1'0
+ assign \mul1_op__is_signed 1'0
+ assign \mul1_op__insn 32'00000000000000000000000000000000
+ assign { \mul1_op__insn \mul1_op__is_signed \mul1_op__is_32bit \mul1_op__write_cr0 \mul1_op__invert_out \mul1_op__zero_a \mul1_op__invert_a { \mul1_op__oe__oe_ok \mul1_op__oe__oe } { \mul1_op__rc__rc_ok \mul1_op__rc__rc } { \mul1_op__imm_data__imm_ok \mul1_op__imm_data__imm } \mul1_op__fn_unit \mul1_op__insn_type } { \input_op__insn$35 \input_op__is_signed$34 \input_op__is_32bit$33 \input_op__write_cr0$32 \input_op__invert_out$31 \input_op__zero_a$30 \input_op__invert_a$29 { \input_op__oe__oe_ok$28 \input_op__oe__oe$27 } { \input_op__rc__rc_ok$26 \input_op__rc__rc$25 } { \input_op__imm_data__imm_ok$24 \input_op__imm_data__imm$23 } \input_op__fn_unit$22 \input_op__insn_type$21 }
+ sync init
+ end
+ process $group_35
+ assign \mul1_ra 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \mul1_ra \input_ra$36
+ sync init
+ end
+ process $group_36
+ assign \mul1_rb 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \mul1_rb \input_rb$37
+ sync init
+ end
+ process $group_37
+ assign \mul1_xer_so 1'0
+ assign \mul1_xer_so \input_xer_so$38
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621"
+ wire width 1 \p_valid_i$58
+ process $group_38
+ assign \p_valid_i$58 1'0
+ assign \p_valid_i$58 \p_valid_i
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619"
+ wire width 1 \n_i_rdy_data
+ process $group_39
+ assign \n_i_rdy_data 1'0
+ assign \n_i_rdy_data \n_ready_i
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620"
+ wire width 1 \p_valid_i_p_ready_o
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624"
+ wire width 1 $59
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624"
+ cell $and $60
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \p_valid_i$58
+ connect \B \p_ready_o
+ connect \Y $59
+ end
+ process $group_40
+ assign \p_valid_i_p_ready_o 1'0
+ assign \p_valid_i_p_ready_o $59
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+ wire width 2 \muxid$61
+ process $group_41
+ assign \muxid$61 2'00
+ assign \muxid$61 \mul1_muxid$39
+ sync init
+ end
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 7 \input_op__insn_type
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 7 \op__insn_type$62
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00000000010 "ALU"
attribute \enum_value_00100000000 "MUL"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 11 \input_op__fn_unit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 64 \input_op__imm_data__imm
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 \input_op__imm_data__imm_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 \input_op__rc__rc
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 \input_op__rc__rc_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 \input_op__oe__oe
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 \input_op__oe__oe_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 3 \input_op__write_cr__data
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 \input_op__write_cr__ok
- attribute \enum_base_type "CryIn"
- attribute \enum_value_00 "ZERO"
- attribute \enum_value_01 "ONE"
- attribute \enum_value_10 "CA"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 2 \input_op__input_carry
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 \input_op__output_carry
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 \input_op__input_cr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 \input_op__output_cr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 \input_op__is_32bit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 \input_op__is_signed
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 32 \input_op__insn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
- wire width 64 \input_ra
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
- wire width 64 \input_rb
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
- wire width 64 \input_rc
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
- wire width 2 \input_xer_ca
- attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
- wire width 2 \input_muxid$20
- attribute \enum_base_type "InternalOp"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 11 \op__fn_unit$63
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 \op__imm_data__imm$64
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__imm_data__imm_ok$65
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__rc__rc$66
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__rc__rc_ok$67
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__oe__oe$68
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__oe__oe_ok$69
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__invert_a$70
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__zero_a$71
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__invert_out$72
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__write_cr0$73
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__is_32bit$74
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__is_signed$75
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 \op__insn$76
+ process $group_42
+ assign \op__insn_type$62 7'0000000
+ assign \op__fn_unit$63 11'00000000000
+ assign \op__imm_data__imm$64 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \op__imm_data__imm_ok$65 1'0
+ assign \op__rc__rc$66 1'0
+ assign \op__rc__rc_ok$67 1'0
+ assign \op__oe__oe$68 1'0
+ assign \op__oe__oe_ok$69 1'0
+ assign \op__invert_a$70 1'0
+ assign \op__zero_a$71 1'0
+ assign \op__invert_out$72 1'0
+ assign \op__write_cr0$73 1'0
+ assign \op__is_32bit$74 1'0
+ assign \op__is_signed$75 1'0
+ assign \op__insn$76 32'00000000000000000000000000000000
+ assign { \op__insn$76 \op__is_signed$75 \op__is_32bit$74 \op__write_cr0$73 \op__invert_out$72 \op__zero_a$71 \op__invert_a$70 { \op__oe__oe_ok$69 \op__oe__oe$68 } { \op__rc__rc_ok$67 \op__rc__rc$66 } { \op__imm_data__imm_ok$65 \op__imm_data__imm$64 } \op__fn_unit$63 \op__insn_type$62 } { \mul1_op__insn$54 \mul1_op__is_signed$53 \mul1_op__is_32bit$52 \mul1_op__write_cr0$51 \mul1_op__invert_out$50 \mul1_op__zero_a$49 \mul1_op__invert_a$48 { \mul1_op__oe__oe_ok$47 \mul1_op__oe__oe$46 } { \mul1_op__rc__rc_ok$45 \mul1_op__rc__rc$44 } { \mul1_op__imm_data__imm_ok$43 \mul1_op__imm_data__imm$42 } \mul1_op__fn_unit$41 \mul1_op__insn_type$40 }
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 64 \ra$77
+ process $group_57
+ assign \ra$77 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \ra$77 \mul1_ra$55
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 64 \rb$78
+ process $group_58
+ assign \rb$78 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \rb$78 \mul1_rb$56
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 1 \xer_so$79
+ process $group_59
+ assign \xer_so$79 1'0
+ assign \xer_so$79 \mul1_xer_so$57
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11"
+ wire width 1 \neg_res$80
+ process $group_60
+ assign \neg_res$80 1'0
+ assign \neg_res$80 \mul1_neg_res
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12"
+ wire width 1 \neg_res32$81
+ process $group_61
+ assign \neg_res32$81 1'0
+ assign \neg_res32$81 \mul1_neg_res32
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615"
+ wire width 1 \r_busy
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615"
+ wire width 1 \r_busy$next
+ process $group_62
+ assign \r_busy$next \r_busy
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+ switch { \n_i_rdy_data \p_valid_i_p_ready_o }
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+ case 2'-1
+ assign \r_busy$next 1'1
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
+ case 2'1-
+ assign \r_busy$next 1'0
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+ switch \rst
+ case 1'1
+ assign \r_busy$next 1'0
+ end
+ sync init
+ update \r_busy 1'0
+ sync posedge \clk
+ update \r_busy \r_busy$next
+ end
+ process $group_63
+ assign \muxid$next \muxid
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+ switch { \n_i_rdy_data \p_valid_i_p_ready_o }
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+ case 2'-1
+ assign \muxid$next \muxid$61
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
+ case 2'1-
+ assign \muxid$next \muxid$61
+ end
+ sync init
+ update \muxid 2'00
+ sync posedge \clk
+ update \muxid \muxid$next
+ end
+ process $group_64
+ assign \op__insn_type$next \op__insn_type
+ assign \op__fn_unit$next \op__fn_unit
+ assign \op__imm_data__imm$next \op__imm_data__imm
+ assign \op__imm_data__imm_ok$next \op__imm_data__imm_ok
+ assign \op__rc__rc$next \op__rc__rc
+ assign \op__rc__rc_ok$next \op__rc__rc_ok
+ assign \op__oe__oe$next \op__oe__oe
+ assign \op__oe__oe_ok$next \op__oe__oe_ok
+ assign \op__invert_a$next \op__invert_a
+ assign \op__zero_a$next \op__zero_a
+ assign \op__invert_out$next \op__invert_out
+ assign \op__write_cr0$next \op__write_cr0
+ assign \op__is_32bit$next \op__is_32bit
+ assign \op__is_signed$next \op__is_signed
+ assign \op__insn$next \op__insn
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+ switch { \n_i_rdy_data \p_valid_i_p_ready_o }
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+ case 2'-1
+ assign { \op__insn$next \op__is_signed$next \op__is_32bit$next \op__write_cr0$next \op__invert_out$next \op__zero_a$next \op__invert_a$next { \op__oe__oe_ok$next \op__oe__oe$next } { \op__rc__rc_ok$next \op__rc__rc$next } { \op__imm_data__imm_ok$next \op__imm_data__imm$next } \op__fn_unit$next \op__insn_type$next } { \op__insn$76 \op__is_signed$75 \op__is_32bit$74 \op__write_cr0$73 \op__invert_out$72 \op__zero_a$71 \op__invert_a$70 { \op__oe__oe_ok$69 \op__oe__oe$68 } { \op__rc__rc_ok$67 \op__rc__rc$66 } { \op__imm_data__imm_ok$65 \op__imm_data__imm$64 } \op__fn_unit$63 \op__insn_type$62 }
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
+ case 2'1-
+ assign { \op__insn$next \op__is_signed$next \op__is_32bit$next \op__write_cr0$next \op__invert_out$next \op__zero_a$next \op__invert_a$next { \op__oe__oe_ok$next \op__oe__oe$next } { \op__rc__rc_ok$next \op__rc__rc$next } { \op__imm_data__imm_ok$next \op__imm_data__imm$next } \op__fn_unit$next \op__insn_type$next } { \op__insn$76 \op__is_signed$75 \op__is_32bit$74 \op__write_cr0$73 \op__invert_out$72 \op__zero_a$71 \op__invert_a$70 { \op__oe__oe_ok$69 \op__oe__oe$68 } { \op__rc__rc_ok$67 \op__rc__rc$66 } { \op__imm_data__imm_ok$65 \op__imm_data__imm$64 } \op__fn_unit$63 \op__insn_type$62 }
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+ switch \rst
+ case 1'1
+ assign \op__imm_data__imm$next 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \op__imm_data__imm_ok$next 1'0
+ assign \op__rc__rc$next 1'0
+ assign \op__rc__rc_ok$next 1'0
+ assign \op__oe__oe$next 1'0
+ assign \op__oe__oe_ok$next 1'0
+ end
+ sync init
+ update \op__insn_type 7'0000000
+ update \op__fn_unit 11'00000000000
+ update \op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
+ update \op__imm_data__imm_ok 1'0
+ update \op__rc__rc 1'0
+ update \op__rc__rc_ok 1'0
+ update \op__oe__oe 1'0
+ update \op__oe__oe_ok 1'0
+ update \op__invert_a 1'0
+ update \op__zero_a 1'0
+ update \op__invert_out 1'0
+ update \op__write_cr0 1'0
+ update \op__is_32bit 1'0
+ update \op__is_signed 1'0
+ update \op__insn 32'00000000000000000000000000000000
+ sync posedge \clk
+ update \op__insn_type \op__insn_type$next
+ update \op__fn_unit \op__fn_unit$next
+ update \op__imm_data__imm \op__imm_data__imm$next
+ update \op__imm_data__imm_ok \op__imm_data__imm_ok$next
+ update \op__rc__rc \op__rc__rc$next
+ update \op__rc__rc_ok \op__rc__rc_ok$next
+ update \op__oe__oe \op__oe__oe$next
+ update \op__oe__oe_ok \op__oe__oe_ok$next
+ update \op__invert_a \op__invert_a$next
+ update \op__zero_a \op__zero_a$next
+ update \op__invert_out \op__invert_out$next
+ update \op__write_cr0 \op__write_cr0$next
+ update \op__is_32bit \op__is_32bit$next
+ update \op__is_signed \op__is_signed$next
+ update \op__insn \op__insn$next
+ end
+ process $group_79
+ assign \ra$next \ra
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+ switch { \n_i_rdy_data \p_valid_i_p_ready_o }
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+ case 2'-1
+ assign \ra$next \ra$77
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
+ case 2'1-
+ assign \ra$next \ra$77
+ end
+ sync init
+ update \ra 64'0000000000000000000000000000000000000000000000000000000000000000
+ sync posedge \clk
+ update \ra \ra$next
+ end
+ process $group_80
+ assign \rb$next \rb
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+ switch { \n_i_rdy_data \p_valid_i_p_ready_o }
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+ case 2'-1
+ assign \rb$next \rb$78
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
+ case 2'1-
+ assign \rb$next \rb$78
+ end
+ sync init
+ update \rb 64'0000000000000000000000000000000000000000000000000000000000000000
+ sync posedge \clk
+ update \rb \rb$next
+ end
+ process $group_81
+ assign \xer_so$next \xer_so
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+ switch { \n_i_rdy_data \p_valid_i_p_ready_o }
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+ case 2'-1
+ assign \xer_so$next \xer_so$79
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
+ case 2'1-
+ assign \xer_so$next \xer_so$79
+ end
+ sync init
+ update \xer_so 1'0
+ sync posedge \clk
+ update \xer_so \xer_so$next
+ end
+ process $group_82
+ assign \neg_res$next \neg_res
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+ switch { \n_i_rdy_data \p_valid_i_p_ready_o }
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+ case 2'-1
+ assign \neg_res$next \neg_res$80
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
+ case 2'1-
+ assign \neg_res$next \neg_res$80
+ end
+ sync init
+ update \neg_res 1'0
+ sync posedge \clk
+ update \neg_res \neg_res$next
+ end
+ process $group_83
+ assign \neg_res32$next \neg_res32
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+ switch { \n_i_rdy_data \p_valid_i_p_ready_o }
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+ case 2'-1
+ assign \neg_res32$next \neg_res32$81
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
+ case 2'1-
+ assign \neg_res32$next \neg_res32$81
+ end
+ sync init
+ update \neg_res32 1'0
+ sync posedge \clk
+ update \neg_res32 \neg_res32$next
+ end
+ process $group_84
+ assign \n_valid_o 1'0
+ assign \n_valid_o \r_busy
+ sync init
+ end
+ process $group_85
+ assign \p_ready_o 1'0
+ assign \p_ready_o \n_i_rdy_data
+ sync init
+ end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe2.p"
+module \p$75
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153"
+ wire width 1 input 0 \p_valid_i
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154"
+ wire width 1 input 1 \p_ready_o
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158"
+ wire width 1 \trigger
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205"
+ wire width 1 $1
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205"
+ cell $and $2
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \p_valid_i
+ connect \B \p_ready_o
+ connect \Y $1
+ end
+ process $group_0
+ assign \trigger 1'0
+ assign \trigger $1
+ sync init
+ end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe2.n"
+module \n$76
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
+ wire width 1 input 0 \n_valid_o
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
+ wire width 1 input 1 \n_ready_i
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251"
+ wire width 1 \trigger
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:297"
+ wire width 1 $1
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:297"
+ cell $and $2
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \n_ready_i
+ connect \B \n_valid_o
+ connect \Y $1
+ end
+ process $group_0
+ assign \trigger 1'0
+ assign \trigger $1
+ sync init
+ end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe2.mul2"
+module \mul2
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+ wire width 2 input 0 \muxid
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 7 \input_op__insn_type$21
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 7 input 1 \op__insn_type
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00000000010 "ALU"
attribute \enum_value_00100000000 "MUL"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 11 \input_op__fn_unit$22
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 64 \input_op__imm_data__imm$23
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 \input_op__imm_data__imm_ok$24
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 \input_op__rc__rc$25
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 \input_op__rc__rc_ok$26
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 \input_op__oe__oe$27
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 \input_op__oe__oe_ok$28
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 3 \input_op__write_cr__data$29
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 \input_op__write_cr__ok$30
- attribute \enum_base_type "CryIn"
- attribute \enum_value_00 "ZERO"
- attribute \enum_value_01 "ONE"
- attribute \enum_value_10 "CA"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 2 \input_op__input_carry$31
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 \input_op__output_carry$32
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 \input_op__input_cr$33
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 \input_op__output_cr$34
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 \input_op__is_32bit$35
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 \input_op__is_signed$36
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 32 \input_op__insn$37
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
- wire width 64 \input_ra$38
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
- wire width 64 \input_rb$39
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
- wire width 64 \input_rc$40
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
- wire width 2 \input_xer_ca$41
- cell \input$75 \input
- connect \muxid \input_muxid
- connect \op__insn_type \input_op__insn_type
- connect \op__fn_unit \input_op__fn_unit
- connect \op__imm_data__imm \input_op__imm_data__imm
- connect \op__imm_data__imm_ok \input_op__imm_data__imm_ok
- connect \op__rc__rc \input_op__rc__rc
- connect \op__rc__rc_ok \input_op__rc__rc_ok
- connect \op__oe__oe \input_op__oe__oe
- connect \op__oe__oe_ok \input_op__oe__oe_ok
- connect \op__write_cr__data \input_op__write_cr__data
- connect \op__write_cr__ok \input_op__write_cr__ok
- connect \op__input_carry \input_op__input_carry
- connect \op__output_carry \input_op__output_carry
- connect \op__input_cr \input_op__input_cr
- connect \op__output_cr \input_op__output_cr
- connect \op__is_32bit \input_op__is_32bit
- connect \op__is_signed \input_op__is_signed
- connect \op__insn \input_op__insn
- connect \ra \input_ra
- connect \rb \input_rb
- connect \rc \input_rc
- connect \xer_ca \input_xer_ca
- connect \muxid$1 \input_muxid$20
- connect \op__insn_type$2 \input_op__insn_type$21
- connect \op__fn_unit$3 \input_op__fn_unit$22
- connect \op__imm_data__imm$4 \input_op__imm_data__imm$23
- connect \op__imm_data__imm_ok$5 \input_op__imm_data__imm_ok$24
- connect \op__rc__rc$6 \input_op__rc__rc$25
- connect \op__rc__rc_ok$7 \input_op__rc__rc_ok$26
- connect \op__oe__oe$8 \input_op__oe__oe$27
- connect \op__oe__oe_ok$9 \input_op__oe__oe_ok$28
- connect \op__write_cr__data$10 \input_op__write_cr__data$29
- connect \op__write_cr__ok$11 \input_op__write_cr__ok$30
- connect \op__input_carry$12 \input_op__input_carry$31
- connect \op__output_carry$13 \input_op__output_carry$32
- connect \op__input_cr$14 \input_op__input_cr$33
- connect \op__output_cr$15 \input_op__output_cr$34
- connect \op__is_32bit$16 \input_op__is_32bit$35
- connect \op__is_signed$17 \input_op__is_signed$36
- connect \op__insn$18 \input_op__insn$37
- connect \ra$19 \input_ra$38
- connect \rb$20 \input_rb$39
- connect \rc$21 \input_rc$40
- connect \xer_ca$22 \input_xer_ca$41
- end
- attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
- wire width 2 \main_muxid
- attribute \enum_base_type "InternalOp"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 11 input 2 \op__fn_unit
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 input 3 \op__imm_data__imm
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 4 \op__imm_data__imm_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 5 \op__rc__rc
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 6 \op__rc__rc_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 7 \op__oe__oe
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 8 \op__oe__oe_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 9 \op__invert_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 10 \op__zero_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 11 \op__invert_out
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 12 \op__write_cr0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 13 \op__is_32bit
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 14 \op__is_signed
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 input 15 \op__insn
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 64 input 16 \ra
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 64 input 17 \rb
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 1 input 18 \xer_so
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11"
+ wire width 1 input 19 \neg_res
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12"
+ wire width 1 input 20 \neg_res32
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+ wire width 2 output 21 \muxid$1
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 7 \main_op__insn_type
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 7 output 22 \op__insn_type$2
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00000000010 "ALU"
attribute \enum_value_00100000000 "MUL"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 11 \main_op__fn_unit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 64 \main_op__imm_data__imm
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 \main_op__imm_data__imm_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 \main_op__rc__rc
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 \main_op__rc__rc_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 \main_op__oe__oe
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 \main_op__oe__oe_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 3 \main_op__write_cr__data
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 \main_op__write_cr__ok
- attribute \enum_base_type "CryIn"
- attribute \enum_value_00 "ZERO"
- attribute \enum_value_01 "ONE"
- attribute \enum_value_10 "CA"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 2 \main_op__input_carry
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 \main_op__output_carry
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 \main_op__input_cr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 \main_op__output_cr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 \main_op__is_32bit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 \main_op__is_signed
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 32 \main_op__insn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
- wire width 64 \main_ra
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
- wire width 64 \main_rb
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
- wire width 64 \main_rc
- attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
- wire width 2 \main_muxid$42
- attribute \enum_base_type "InternalOp"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 11 output 23 \op__fn_unit$3
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 output 24 \op__imm_data__imm$4
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 25 \op__imm_data__imm_ok$5
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 26 \op__rc__rc$6
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 27 \op__rc__rc_ok$7
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 28 \op__oe__oe$8
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 29 \op__oe__oe_ok$9
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 30 \op__invert_a$10
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 31 \op__zero_a$11
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 32 \op__invert_out$12
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 33 \op__write_cr0$13
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 34 \op__is_32bit$14
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 35 \op__is_signed$15
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 output 36 \op__insn$16
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 129 output 37 \o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 1 output 38 \xer_so$17
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23"
+ wire width 1 output 39 \neg_res$18
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24"
+ wire width 1 output 40 \neg_res32$19
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28"
+ wire width 129 $20
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28"
+ wire width 128 $21
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28"
+ cell $mul $22
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 64
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 64
+ parameter \Y_WIDTH 128
+ connect \A \ra
+ connect \B \rb
+ connect \Y $21
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28"
+ cell $pos $23
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 128
+ parameter \Y_WIDTH 129
+ connect \A $21
+ connect \Y $20
+ end
+ process $group_0
+ assign \o 129'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
+ assign \o $20
+ sync init
+ end
+ process $group_1
+ assign \neg_res$18 1'0
+ assign \neg_res$18 \neg_res
+ sync init
+ end
+ process $group_2
+ assign \neg_res32$19 1'0
+ assign \neg_res32$19 \neg_res32
+ sync init
+ end
+ process $group_3
+ assign \xer_so$17 1'0
+ assign \xer_so$17 \xer_so
+ sync init
+ end
+ process $group_4
+ assign \muxid$1 2'00
+ assign \muxid$1 \muxid
+ sync init
+ end
+ process $group_5
+ assign \op__insn_type$2 7'0000000
+ assign \op__fn_unit$3 11'00000000000
+ assign \op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \op__imm_data__imm_ok$5 1'0
+ assign \op__rc__rc$6 1'0
+ assign \op__rc__rc_ok$7 1'0
+ assign \op__oe__oe$8 1'0
+ assign \op__oe__oe_ok$9 1'0
+ assign \op__invert_a$10 1'0
+ assign \op__zero_a$11 1'0
+ assign \op__invert_out$12 1'0
+ assign \op__write_cr0$13 1'0
+ assign \op__is_32bit$14 1'0
+ assign \op__is_signed$15 1'0
+ assign \op__insn$16 32'00000000000000000000000000000000
+ assign { \op__insn$16 \op__is_signed$15 \op__is_32bit$14 \op__write_cr0$13 \op__invert_out$12 \op__zero_a$11 \op__invert_a$10 { \op__oe__oe_ok$9 \op__oe__oe$8 } { \op__rc__rc_ok$7 \op__rc__rc$6 } { \op__imm_data__imm_ok$5 \op__imm_data__imm$4 } \op__fn_unit$3 \op__insn_type$2 } { \op__insn \op__is_signed \op__is_32bit \op__write_cr0 \op__invert_out \op__zero_a \op__invert_a { \op__oe__oe_ok \op__oe__oe } { \op__rc__rc_ok \op__rc__rc } { \op__imm_data__imm_ok \op__imm_data__imm } \op__fn_unit \op__insn_type }
+ sync init
+ end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe2"
+module \mul_pipe2
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
+ wire width 1 input 0 \rst
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
+ wire width 1 input 1 \clk
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153"
+ wire width 1 input 2 \p_valid_i
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154"
+ wire width 1 output 3 \p_ready_o
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+ wire width 2 input 4 \muxid
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 7 \main_op__insn_type$43
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 7 input 5 \op__insn_type
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00000000010 "ALU"
attribute \enum_value_00100000000 "MUL"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 11 \main_op__fn_unit$44
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 64 \main_op__imm_data__imm$45
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 \main_op__imm_data__imm_ok$46
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 \main_op__rc__rc$47
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 \main_op__rc__rc_ok$48
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 \main_op__oe__oe$49
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 \main_op__oe__oe_ok$50
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 3 \main_op__write_cr__data$51
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 \main_op__write_cr__ok$52
- attribute \enum_base_type "CryIn"
- attribute \enum_value_00 "ZERO"
- attribute \enum_value_01 "ONE"
- attribute \enum_value_10 "CA"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 2 \main_op__input_carry$53
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 \main_op__output_carry$54
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 \main_op__input_cr$55
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 \main_op__output_cr$56
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 \main_op__is_32bit$57
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 \main_op__is_signed$58
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 32 \main_op__insn$59
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 \main_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 \main_o_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 2 \main_xer_ca
- cell \main$76 \main
- connect \muxid \main_muxid
- connect \op__insn_type \main_op__insn_type
- connect \op__fn_unit \main_op__fn_unit
- connect \op__imm_data__imm \main_op__imm_data__imm
- connect \op__imm_data__imm_ok \main_op__imm_data__imm_ok
- connect \op__rc__rc \main_op__rc__rc
- connect \op__rc__rc_ok \main_op__rc__rc_ok
- connect \op__oe__oe \main_op__oe__oe
- connect \op__oe__oe_ok \main_op__oe__oe_ok
- connect \op__write_cr__data \main_op__write_cr__data
- connect \op__write_cr__ok \main_op__write_cr__ok
- connect \op__input_carry \main_op__input_carry
- connect \op__output_carry \main_op__output_carry
- connect \op__input_cr \main_op__input_cr
- connect \op__output_cr \main_op__output_cr
- connect \op__is_32bit \main_op__is_32bit
- connect \op__is_signed \main_op__is_signed
- connect \op__insn \main_op__insn
- connect \ra \main_ra
- connect \rb \main_rb
- connect \rc \main_rc
- connect \muxid$1 \main_muxid$42
- connect \op__insn_type$2 \main_op__insn_type$43
- connect \op__fn_unit$3 \main_op__fn_unit$44
- connect \op__imm_data__imm$4 \main_op__imm_data__imm$45
- connect \op__imm_data__imm_ok$5 \main_op__imm_data__imm_ok$46
- connect \op__rc__rc$6 \main_op__rc__rc$47
- connect \op__rc__rc_ok$7 \main_op__rc__rc_ok$48
- connect \op__oe__oe$8 \main_op__oe__oe$49
- connect \op__oe__oe_ok$9 \main_op__oe__oe_ok$50
- connect \op__write_cr__data$10 \main_op__write_cr__data$51
- connect \op__write_cr__ok$11 \main_op__write_cr__ok$52
- connect \op__input_carry$12 \main_op__input_carry$53
- connect \op__output_carry$13 \main_op__output_carry$54
- connect \op__input_cr$14 \main_op__input_cr$55
- connect \op__output_cr$15 \main_op__output_cr$56
- connect \op__is_32bit$16 \main_op__is_32bit$57
- connect \op__is_signed$17 \main_op__is_signed$58
- connect \op__insn$18 \main_op__insn$59
- connect \o \main_o
- connect \o_ok \main_o_ok
- connect \xer_ca \main_xer_ca
- end
- attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
- wire width 2 \output_muxid
- attribute \enum_base_type "InternalOp"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 11 input 6 \op__fn_unit
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 input 7 \op__imm_data__imm
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 8 \op__imm_data__imm_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 9 \op__rc__rc
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 10 \op__rc__rc_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 11 \op__oe__oe
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 12 \op__oe__oe_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 13 \op__invert_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 14 \op__zero_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 15 \op__invert_out
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 16 \op__write_cr0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 17 \op__is_32bit
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 18 \op__is_signed
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 input 19 \op__insn
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 64 input 20 \ra
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 64 input 21 \rb
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 1 input 22 \xer_so
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11"
+ wire width 1 input 23 \neg_res
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12"
+ wire width 1 input 24 \neg_res32
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
+ wire width 1 output 25 \n_valid_o
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
+ wire width 1 input 26 \n_ready_i
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+ wire width 2 output 27 \muxid$1
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+ wire width 2 \muxid$1$next
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 7 \output_op__insn_type
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 7 output 28 \op__insn_type$2
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 7 \op__insn_type$2$next
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00000000010 "ALU"
attribute \enum_value_00100000000 "MUL"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 11 \output_op__fn_unit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 64 \output_op__imm_data__imm
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 \output_op__imm_data__imm_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 \output_op__rc__rc
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 \output_op__rc__rc_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 \output_op__oe__oe
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 \output_op__oe__oe_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 3 \output_op__write_cr__data
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 \output_op__write_cr__ok
- attribute \enum_base_type "CryIn"
- attribute \enum_value_00 "ZERO"
- attribute \enum_value_01 "ONE"
- attribute \enum_value_10 "CA"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 2 \output_op__input_carry
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 \output_op__output_carry
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 \output_op__input_cr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 \output_op__output_cr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 \output_op__is_32bit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 \output_op__is_signed
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 32 \output_op__insn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 \output_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 \output_o_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 4 \output_cr_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 2 \output_xer_ca
- attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
- wire width 2 \output_muxid$60
- attribute \enum_base_type "InternalOp"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 11 output 29 \op__fn_unit$3
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 11 \op__fn_unit$3$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 output 30 \op__imm_data__imm$4
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 \op__imm_data__imm$4$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 31 \op__imm_data__imm_ok$5
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__imm_data__imm_ok$5$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 32 \op__rc__rc$6
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__rc__rc$6$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 33 \op__rc__rc_ok$7
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__rc__rc_ok$7$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 34 \op__oe__oe$8
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__oe__oe$8$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 35 \op__oe__oe_ok$9
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__oe__oe_ok$9$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 36 \op__invert_a$10
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__invert_a$10$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 37 \op__zero_a$11
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__zero_a$11$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 38 \op__invert_out$12
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__invert_out$12$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 39 \op__write_cr0$13
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__write_cr0$13$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 40 \op__is_32bit$14
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__is_32bit$14$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 41 \op__is_signed$15
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__is_signed$15$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 output 42 \op__insn$16
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 \op__insn$16$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 129 output 43 \o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 129 \o$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 1 output 44 \xer_so$17
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 1 \xer_so$17$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23"
+ wire width 1 output 45 \neg_res$18
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23"
+ wire width 1 \neg_res$18$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24"
+ wire width 1 output 46 \neg_res32$19
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24"
+ wire width 1 \neg_res32$19$next
+ cell \p$75 \p
+ connect \p_valid_i \p_valid_i
+ connect \p_ready_o \p_ready_o
+ end
+ cell \n$76 \n
+ connect \n_valid_o \n_valid_o
+ connect \n_ready_i \n_ready_i
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+ wire width 2 \mul2_muxid
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 7 \output_op__insn_type$61
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 7 \mul2_op__insn_type
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00000000010 "ALU"
attribute \enum_value_00100000000 "MUL"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 11 \output_op__fn_unit$62
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 64 \output_op__imm_data__imm$63
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 \output_op__imm_data__imm_ok$64
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 \output_op__rc__rc$65
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 \output_op__rc__rc_ok$66
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 \output_op__oe__oe$67
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 \output_op__oe__oe_ok$68
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 3 \output_op__write_cr__data$69
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 \output_op__write_cr__ok$70
- attribute \enum_base_type "CryIn"
- attribute \enum_value_00 "ZERO"
- attribute \enum_value_01 "ONE"
- attribute \enum_value_10 "CA"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 2 \output_op__input_carry$71
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 \output_op__output_carry$72
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 \output_op__input_cr$73
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 \output_op__output_cr$74
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 \output_op__is_32bit$75
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 \output_op__is_signed$76
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 32 \output_op__insn$77
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 \output_o$78
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 \output_o_ok$79
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 4 \output_cr_a$80
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 \output_cr_a_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 2 \output_xer_ca$81
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 \output_xer_ca_ok
- cell \output$77 \output
- connect \muxid \output_muxid
- connect \op__insn_type \output_op__insn_type
- connect \op__fn_unit \output_op__fn_unit
- connect \op__imm_data__imm \output_op__imm_data__imm
- connect \op__imm_data__imm_ok \output_op__imm_data__imm_ok
- connect \op__rc__rc \output_op__rc__rc
- connect \op__rc__rc_ok \output_op__rc__rc_ok
- connect \op__oe__oe \output_op__oe__oe
- connect \op__oe__oe_ok \output_op__oe__oe_ok
- connect \op__write_cr__data \output_op__write_cr__data
- connect \op__write_cr__ok \output_op__write_cr__ok
- connect \op__input_carry \output_op__input_carry
- connect \op__output_carry \output_op__output_carry
- connect \op__input_cr \output_op__input_cr
- connect \op__output_cr \output_op__output_cr
- connect \op__is_32bit \output_op__is_32bit
- connect \op__is_signed \output_op__is_signed
- connect \op__insn \output_op__insn
- connect \o \output_o
- connect \o_ok \output_o_ok
- connect \cr_a \output_cr_a
- connect \xer_ca \output_xer_ca
- connect \muxid$1 \output_muxid$60
- connect \op__insn_type$2 \output_op__insn_type$61
- connect \op__fn_unit$3 \output_op__fn_unit$62
- connect \op__imm_data__imm$4 \output_op__imm_data__imm$63
- connect \op__imm_data__imm_ok$5 \output_op__imm_data__imm_ok$64
- connect \op__rc__rc$6 \output_op__rc__rc$65
- connect \op__rc__rc_ok$7 \output_op__rc__rc_ok$66
- connect \op__oe__oe$8 \output_op__oe__oe$67
- connect \op__oe__oe_ok$9 \output_op__oe__oe_ok$68
- connect \op__write_cr__data$10 \output_op__write_cr__data$69
- connect \op__write_cr__ok$11 \output_op__write_cr__ok$70
- connect \op__input_carry$12 \output_op__input_carry$71
- connect \op__output_carry$13 \output_op__output_carry$72
- connect \op__input_cr$14 \output_op__input_cr$73
- connect \op__output_cr$15 \output_op__output_cr$74
- connect \op__is_32bit$16 \output_op__is_32bit$75
- connect \op__is_signed$17 \output_op__is_signed$76
- connect \op__insn$18 \output_op__insn$77
- connect \o$19 \output_o$78
- connect \o_ok$20 \output_o_ok$79
- connect \cr_a$21 \output_cr_a$80
- connect \cr_a_ok \output_cr_a_ok
- connect \xer_ca$22 \output_xer_ca$81
- connect \xer_ca_ok \output_xer_ca_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 11 \mul2_op__fn_unit
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 \mul2_op__imm_data__imm
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \mul2_op__imm_data__imm_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \mul2_op__rc__rc
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \mul2_op__rc__rc_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \mul2_op__oe__oe
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \mul2_op__oe__oe_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \mul2_op__invert_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \mul2_op__zero_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \mul2_op__invert_out
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \mul2_op__write_cr0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \mul2_op__is_32bit
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \mul2_op__is_signed
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 \mul2_op__insn
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 64 \mul2_ra
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 64 \mul2_rb
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 1 \mul2_xer_so
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11"
+ wire width 1 \mul2_neg_res
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12"
+ wire width 1 \mul2_neg_res32
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+ wire width 2 \mul2_muxid$20
+ attribute \enum_base_type "MicrOp"
+ attribute \enum_value_0000000 "OP_ILLEGAL"
+ attribute \enum_value_0000001 "OP_NOP"
+ attribute \enum_value_0000010 "OP_ADD"
+ attribute \enum_value_0000011 "OP_ADDPCIS"
+ attribute \enum_value_0000100 "OP_AND"
+ attribute \enum_value_0000101 "OP_ATTN"
+ attribute \enum_value_0000110 "OP_B"
+ attribute \enum_value_0000111 "OP_BC"
+ attribute \enum_value_0001000 "OP_BCREG"
+ attribute \enum_value_0001001 "OP_BPERM"
+ attribute \enum_value_0001010 "OP_CMP"
+ attribute \enum_value_0001011 "OP_CMPB"
+ attribute \enum_value_0001100 "OP_CMPEQB"
+ attribute \enum_value_0001101 "OP_CMPRB"
+ attribute \enum_value_0001110 "OP_CNTZ"
+ attribute \enum_value_0001111 "OP_CRAND"
+ attribute \enum_value_0010000 "OP_CRANDC"
+ attribute \enum_value_0010001 "OP_CREQV"
+ attribute \enum_value_0010010 "OP_CRNAND"
+ attribute \enum_value_0010011 "OP_CRNOR"
+ attribute \enum_value_0010100 "OP_CROR"
+ attribute \enum_value_0010101 "OP_CRORC"
+ attribute \enum_value_0010110 "OP_CRXOR"
+ attribute \enum_value_0010111 "OP_DARN"
+ attribute \enum_value_0011000 "OP_DCBF"
+ attribute \enum_value_0011001 "OP_DCBST"
+ attribute \enum_value_0011010 "OP_DCBT"
+ attribute \enum_value_0011011 "OP_DCBTST"
+ attribute \enum_value_0011100 "OP_DCBZ"
+ attribute \enum_value_0011101 "OP_DIV"
+ attribute \enum_value_0011110 "OP_DIVE"
+ attribute \enum_value_0011111 "OP_EXTS"
+ attribute \enum_value_0100000 "OP_EXTSWSLI"
+ attribute \enum_value_0100001 "OP_ICBI"
+ attribute \enum_value_0100010 "OP_ICBT"
+ attribute \enum_value_0100011 "OP_ISEL"
+ attribute \enum_value_0100100 "OP_ISYNC"
+ attribute \enum_value_0100101 "OP_LOAD"
+ attribute \enum_value_0100110 "OP_STORE"
+ attribute \enum_value_0100111 "OP_MADDHD"
+ attribute \enum_value_0101000 "OP_MADDHDU"
+ attribute \enum_value_0101001 "OP_MADDLD"
+ attribute \enum_value_0101010 "OP_MCRF"
+ attribute \enum_value_0101011 "OP_MCRXR"
+ attribute \enum_value_0101100 "OP_MCRXRX"
+ attribute \enum_value_0101101 "OP_MFCR"
+ attribute \enum_value_0101110 "OP_MFSPR"
+ attribute \enum_value_0101111 "OP_MOD"
+ attribute \enum_value_0110000 "OP_MTCRF"
+ attribute \enum_value_0110001 "OP_MTSPR"
+ attribute \enum_value_0110010 "OP_MUL_L64"
+ attribute \enum_value_0110011 "OP_MUL_H64"
+ attribute \enum_value_0110100 "OP_MUL_H32"
+ attribute \enum_value_0110101 "OP_OR"
+ attribute \enum_value_0110110 "OP_POPCNT"
+ attribute \enum_value_0110111 "OP_PRTY"
+ attribute \enum_value_0111000 "OP_RLC"
+ attribute \enum_value_0111001 "OP_RLCL"
+ attribute \enum_value_0111010 "OP_RLCR"
+ attribute \enum_value_0111011 "OP_SETB"
+ attribute \enum_value_0111100 "OP_SHL"
+ attribute \enum_value_0111101 "OP_SHR"
+ attribute \enum_value_0111110 "OP_SYNC"
+ attribute \enum_value_0111111 "OP_TRAP"
+ attribute \enum_value_1000011 "OP_XOR"
+ attribute \enum_value_1000100 "OP_SIM_CONFIG"
+ attribute \enum_value_1000101 "OP_CROP"
+ attribute \enum_value_1000110 "OP_RFID"
+ attribute \enum_value_1000111 "OP_MFMSR"
+ attribute \enum_value_1001000 "OP_MTMSRD"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 7 \mul2_op__insn_type$21
+ attribute \enum_base_type "Function"
+ attribute \enum_value_00000000000 "NONE"
+ attribute \enum_value_00000000010 "ALU"
+ attribute \enum_value_00000000100 "LDST"
+ attribute \enum_value_00000001000 "SHIFT_ROT"
+ attribute \enum_value_00000010000 "LOGICAL"
+ attribute \enum_value_00000100000 "BRANCH"
+ attribute \enum_value_00001000000 "CR"
+ attribute \enum_value_00010000000 "TRAP"
+ attribute \enum_value_00100000000 "MUL"
+ attribute \enum_value_01000000000 "DIV"
+ attribute \enum_value_10000000000 "SPR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 11 \mul2_op__fn_unit$22
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 \mul2_op__imm_data__imm$23
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \mul2_op__imm_data__imm_ok$24
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \mul2_op__rc__rc$25
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \mul2_op__rc__rc_ok$26
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \mul2_op__oe__oe$27
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \mul2_op__oe__oe_ok$28
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \mul2_op__invert_a$29
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \mul2_op__zero_a$30
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \mul2_op__invert_out$31
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \mul2_op__write_cr0$32
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \mul2_op__is_32bit$33
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \mul2_op__is_signed$34
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 \mul2_op__insn$35
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 129 \mul2_o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 1 \mul2_xer_so$36
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23"
+ wire width 1 \mul2_neg_res$37
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24"
+ wire width 1 \mul2_neg_res32$38
+ cell \mul2 \mul2
+ connect \muxid \mul2_muxid
+ connect \op__insn_type \mul2_op__insn_type
+ connect \op__fn_unit \mul2_op__fn_unit
+ connect \op__imm_data__imm \mul2_op__imm_data__imm
+ connect \op__imm_data__imm_ok \mul2_op__imm_data__imm_ok
+ connect \op__rc__rc \mul2_op__rc__rc
+ connect \op__rc__rc_ok \mul2_op__rc__rc_ok
+ connect \op__oe__oe \mul2_op__oe__oe
+ connect \op__oe__oe_ok \mul2_op__oe__oe_ok
+ connect \op__invert_a \mul2_op__invert_a
+ connect \op__zero_a \mul2_op__zero_a
+ connect \op__invert_out \mul2_op__invert_out
+ connect \op__write_cr0 \mul2_op__write_cr0
+ connect \op__is_32bit \mul2_op__is_32bit
+ connect \op__is_signed \mul2_op__is_signed
+ connect \op__insn \mul2_op__insn
+ connect \ra \mul2_ra
+ connect \rb \mul2_rb
+ connect \xer_so \mul2_xer_so
+ connect \neg_res \mul2_neg_res
+ connect \neg_res32 \mul2_neg_res32
+ connect \muxid$1 \mul2_muxid$20
+ connect \op__insn_type$2 \mul2_op__insn_type$21
+ connect \op__fn_unit$3 \mul2_op__fn_unit$22
+ connect \op__imm_data__imm$4 \mul2_op__imm_data__imm$23
+ connect \op__imm_data__imm_ok$5 \mul2_op__imm_data__imm_ok$24
+ connect \op__rc__rc$6 \mul2_op__rc__rc$25
+ connect \op__rc__rc_ok$7 \mul2_op__rc__rc_ok$26
+ connect \op__oe__oe$8 \mul2_op__oe__oe$27
+ connect \op__oe__oe_ok$9 \mul2_op__oe__oe_ok$28
+ connect \op__invert_a$10 \mul2_op__invert_a$29
+ connect \op__zero_a$11 \mul2_op__zero_a$30
+ connect \op__invert_out$12 \mul2_op__invert_out$31
+ connect \op__write_cr0$13 \mul2_op__write_cr0$32
+ connect \op__is_32bit$14 \mul2_op__is_32bit$33
+ connect \op__is_signed$15 \mul2_op__is_signed$34
+ connect \op__insn$16 \mul2_op__insn$35
+ connect \o \mul2_o
+ connect \xer_so$17 \mul2_xer_so$36
+ connect \neg_res$18 \mul2_neg_res$37
+ connect \neg_res32$19 \mul2_neg_res32$38
end
process $group_0
- assign \input_muxid 2'00
- assign \input_muxid \muxid
+ assign \mul2_muxid 2'00
+ assign \mul2_muxid \muxid
sync init
end
process $group_1
- assign \input_op__insn_type 7'0000000
- assign \input_op__fn_unit 11'00000000000
- assign \input_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \input_op__imm_data__imm_ok 1'0
- assign \input_op__rc__rc 1'0
- assign \input_op__rc__rc_ok 1'0
- assign \input_op__oe__oe 1'0
- assign \input_op__oe__oe_ok 1'0
- assign \input_op__write_cr__data 3'000
- assign \input_op__write_cr__ok 1'0
- assign \input_op__input_carry 2'00
- assign \input_op__output_carry 1'0
- assign \input_op__input_cr 1'0
- assign \input_op__output_cr 1'0
- assign \input_op__is_32bit 1'0
- assign \input_op__is_signed 1'0
- assign \input_op__insn 32'00000000000000000000000000000000
- assign { \input_op__insn \input_op__is_signed \input_op__is_32bit \input_op__output_cr \input_op__input_cr \input_op__output_carry \input_op__input_carry { \input_op__write_cr__ok \input_op__write_cr__data } { \input_op__oe__oe_ok \input_op__oe__oe } { \input_op__rc__rc_ok \input_op__rc__rc } { \input_op__imm_data__imm_ok \input_op__imm_data__imm } \input_op__fn_unit \input_op__insn_type } { \op__insn \op__is_signed \op__is_32bit \op__output_cr \op__input_cr \op__output_carry \op__input_carry { \op__write_cr__ok \op__write_cr__data } { \op__oe__oe_ok \op__oe__oe } { \op__rc__rc_ok \op__rc__rc } { \op__imm_data__imm_ok \op__imm_data__imm } \op__fn_unit \op__insn_type }
- sync init
- end
- process $group_18
- assign \input_ra 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \input_ra \ra
+ assign \mul2_op__insn_type 7'0000000
+ assign \mul2_op__fn_unit 11'00000000000
+ assign \mul2_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \mul2_op__imm_data__imm_ok 1'0
+ assign \mul2_op__rc__rc 1'0
+ assign \mul2_op__rc__rc_ok 1'0
+ assign \mul2_op__oe__oe 1'0
+ assign \mul2_op__oe__oe_ok 1'0
+ assign \mul2_op__invert_a 1'0
+ assign \mul2_op__zero_a 1'0
+ assign \mul2_op__invert_out 1'0
+ assign \mul2_op__write_cr0 1'0
+ assign \mul2_op__is_32bit 1'0
+ assign \mul2_op__is_signed 1'0
+ assign \mul2_op__insn 32'00000000000000000000000000000000
+ assign { \mul2_op__insn \mul2_op__is_signed \mul2_op__is_32bit \mul2_op__write_cr0 \mul2_op__invert_out \mul2_op__zero_a \mul2_op__invert_a { \mul2_op__oe__oe_ok \mul2_op__oe__oe } { \mul2_op__rc__rc_ok \mul2_op__rc__rc } { \mul2_op__imm_data__imm_ok \mul2_op__imm_data__imm } \mul2_op__fn_unit \mul2_op__insn_type } { \op__insn \op__is_signed \op__is_32bit \op__write_cr0 \op__invert_out \op__zero_a \op__invert_a { \op__oe__oe_ok \op__oe__oe } { \op__rc__rc_ok \op__rc__rc } { \op__imm_data__imm_ok \op__imm_data__imm } \op__fn_unit \op__insn_type }
sync init
end
- process $group_19
- assign \input_rb 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \input_rb \rb
- sync init
- end
- process $group_20
- assign \input_rc 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \input_rc \rc
- sync init
- end
- process $group_21
- assign \input_xer_ca 2'00
- assign \input_xer_ca \xer_ca
- sync init
- end
- process $group_22
- assign \main_muxid 2'00
- assign \main_muxid \input_muxid$20
- sync init
- end
- process $group_23
- assign \main_op__insn_type 7'0000000
- assign \main_op__fn_unit 11'00000000000
- assign \main_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \main_op__imm_data__imm_ok 1'0
- assign \main_op__rc__rc 1'0
- assign \main_op__rc__rc_ok 1'0
- assign \main_op__oe__oe 1'0
- assign \main_op__oe__oe_ok 1'0
- assign \main_op__write_cr__data 3'000
- assign \main_op__write_cr__ok 1'0
- assign \main_op__input_carry 2'00
- assign \main_op__output_carry 1'0
- assign \main_op__input_cr 1'0
- assign \main_op__output_cr 1'0
- assign \main_op__is_32bit 1'0
- assign \main_op__is_signed 1'0
- assign \main_op__insn 32'00000000000000000000000000000000
- assign { \main_op__insn \main_op__is_signed \main_op__is_32bit \main_op__output_cr \main_op__input_cr \main_op__output_carry \main_op__input_carry { \main_op__write_cr__ok \main_op__write_cr__data } { \main_op__oe__oe_ok \main_op__oe__oe } { \main_op__rc__rc_ok \main_op__rc__rc } { \main_op__imm_data__imm_ok \main_op__imm_data__imm } \main_op__fn_unit \main_op__insn_type } { \input_op__insn$37 \input_op__is_signed$36 \input_op__is_32bit$35 \input_op__output_cr$34 \input_op__input_cr$33 \input_op__output_carry$32 \input_op__input_carry$31 { \input_op__write_cr__ok$30 \input_op__write_cr__data$29 } { \input_op__oe__oe_ok$28 \input_op__oe__oe$27 } { \input_op__rc__rc_ok$26 \input_op__rc__rc$25 } { \input_op__imm_data__imm_ok$24 \input_op__imm_data__imm$23 } \input_op__fn_unit$22 \input_op__insn_type$21 }
- sync init
- end
- process $group_40
- assign \main_ra 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \main_ra \input_ra$38
- sync init
- end
- process $group_41
- assign \main_rb 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \main_rb \input_rb$39
- sync init
- end
- process $group_42
- assign \main_rc 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \main_rc \input_rc$40
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
- wire width 2 \xer_ca$82
- process $group_43
- assign \xer_ca$82 2'00
- assign \xer_ca$82 \input_xer_ca$41
- sync init
- end
- process $group_44
- assign \output_muxid 2'00
- assign \output_muxid \main_muxid$42
+ process $group_16
+ assign \mul2_ra 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \mul2_ra \ra
sync init
end
- process $group_45
- assign \output_op__insn_type 7'0000000
- assign \output_op__fn_unit 11'00000000000
- assign \output_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \output_op__imm_data__imm_ok 1'0
- assign \output_op__rc__rc 1'0
- assign \output_op__rc__rc_ok 1'0
- assign \output_op__oe__oe 1'0
- assign \output_op__oe__oe_ok 1'0
- assign \output_op__write_cr__data 3'000
- assign \output_op__write_cr__ok 1'0
- assign \output_op__input_carry 2'00
- assign \output_op__output_carry 1'0
- assign \output_op__input_cr 1'0
- assign \output_op__output_cr 1'0
- assign \output_op__is_32bit 1'0
- assign \output_op__is_signed 1'0
- assign \output_op__insn 32'00000000000000000000000000000000
- assign { \output_op__insn \output_op__is_signed \output_op__is_32bit \output_op__output_cr \output_op__input_cr \output_op__output_carry \output_op__input_carry { \output_op__write_cr__ok \output_op__write_cr__data } { \output_op__oe__oe_ok \output_op__oe__oe } { \output_op__rc__rc_ok \output_op__rc__rc } { \output_op__imm_data__imm_ok \output_op__imm_data__imm } \output_op__fn_unit \output_op__insn_type } { \main_op__insn$59 \main_op__is_signed$58 \main_op__is_32bit$57 \main_op__output_cr$56 \main_op__input_cr$55 \main_op__output_carry$54 \main_op__input_carry$53 { \main_op__write_cr__ok$52 \main_op__write_cr__data$51 } { \main_op__oe__oe_ok$50 \main_op__oe__oe$49 } { \main_op__rc__rc_ok$48 \main_op__rc__rc$47 } { \main_op__imm_data__imm_ok$46 \main_op__imm_data__imm$45 } \main_op__fn_unit$44 \main_op__insn_type$43 }
+ process $group_17
+ assign \mul2_rb 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \mul2_rb \rb
sync init
end
- process $group_62
- assign \output_o 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \output_o_ok 1'0
- assign { \output_o_ok \output_o } { \main_o_ok \main_o }
+ process $group_18
+ assign \mul2_xer_so 1'0
+ assign \mul2_xer_so \xer_so
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 \cr_a_ok$83
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 4 \cr_a$84
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 \cr_a_ok$85
- process $group_64
- assign \output_cr_a 4'0000
- assign \cr_a_ok$83 1'0
- assign { \cr_a_ok$83 \output_cr_a } { \cr_a_ok$85 \cr_a$84 }
+ process $group_19
+ assign \mul2_neg_res 1'0
+ assign \mul2_neg_res \neg_res
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 \xer_ca_ok$86
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 \xer_ca_ok$87
- process $group_66
- assign \output_xer_ca 2'00
- assign \xer_ca_ok$86 1'0
- assign { \xer_ca_ok$86 \output_xer_ca } { \xer_ca_ok$87 \main_xer_ca }
+ process $group_20
+ assign \mul2_neg_res32 1'0
+ assign \mul2_neg_res32 \neg_res32
sync init
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621"
- wire width 1 \p_valid_i$88
- process $group_68
- assign \p_valid_i$88 1'0
- assign \p_valid_i$88 \p_valid_i
+ wire width 1 \p_valid_i$39
+ process $group_21
+ assign \p_valid_i$39 1'0
+ assign \p_valid_i$39 \p_valid_i
sync init
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619"
wire width 1 \n_i_rdy_data
- process $group_69
+ process $group_22
assign \n_i_rdy_data 1'0
assign \n_i_rdy_data \n_ready_i
sync init
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620"
wire width 1 \p_valid_i_p_ready_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624"
- wire width 1 $89
+ wire width 1 $40
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624"
- cell $and $90
+ cell $and $41
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \p_valid_i$88
+ connect \A \p_valid_i$39
connect \B \p_ready_o
- connect \Y $89
+ connect \Y $40
end
- process $group_70
+ process $group_23
assign \p_valid_i_p_ready_o 1'0
- assign \p_valid_i_p_ready_o $89
+ assign \p_valid_i_p_ready_o $40
sync init
end
- attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
- wire width 2 \muxid$91
- process $group_71
- assign \muxid$91 2'00
- assign \muxid$91 \output_muxid$60
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+ wire width 2 \muxid$42
+ process $group_24
+ assign \muxid$42 2'00
+ assign \muxid$42 \mul2_muxid$20
sync init
end
- attribute \enum_base_type "InternalOp"
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 7 \op__insn_type$92
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 7 \op__insn_type$43
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00000000010 "ALU"
attribute \enum_value_00100000000 "MUL"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 11 \op__fn_unit$93
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 64 \op__imm_data__imm$94
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 \op__imm_data__imm_ok$95
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 \op__rc__rc$96
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 \op__rc__rc_ok$97
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 \op__oe__oe$98
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 \op__oe__oe_ok$99
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 3 \op__write_cr__data$100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 \op__write_cr__ok$101
- attribute \enum_base_type "CryIn"
- attribute \enum_value_00 "ZERO"
- attribute \enum_value_01 "ONE"
- attribute \enum_value_10 "CA"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 2 \op__input_carry$102
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 \op__output_carry$103
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 \op__input_cr$104
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 \op__output_cr$105
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 \op__is_32bit$106
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 \op__is_signed$107
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 32 \op__insn$108
- process $group_72
- assign \op__insn_type$92 7'0000000
- assign \op__fn_unit$93 11'00000000000
- assign \op__imm_data__imm$94 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \op__imm_data__imm_ok$95 1'0
- assign \op__rc__rc$96 1'0
- assign \op__rc__rc_ok$97 1'0
- assign \op__oe__oe$98 1'0
- assign \op__oe__oe_ok$99 1'0
- assign \op__write_cr__data$100 3'000
- assign \op__write_cr__ok$101 1'0
- assign \op__input_carry$102 2'00
- assign \op__output_carry$103 1'0
- assign \op__input_cr$104 1'0
- assign \op__output_cr$105 1'0
- assign \op__is_32bit$106 1'0
- assign \op__is_signed$107 1'0
- assign \op__insn$108 32'00000000000000000000000000000000
- assign { \op__insn$108 \op__is_signed$107 \op__is_32bit$106 \op__output_cr$105 \op__input_cr$104 \op__output_carry$103 \op__input_carry$102 { \op__write_cr__ok$101 \op__write_cr__data$100 } { \op__oe__oe_ok$99 \op__oe__oe$98 } { \op__rc__rc_ok$97 \op__rc__rc$96 } { \op__imm_data__imm_ok$95 \op__imm_data__imm$94 } \op__fn_unit$93 \op__insn_type$92 } { \output_op__insn$77 \output_op__is_signed$76 \output_op__is_32bit$75 \output_op__output_cr$74 \output_op__input_cr$73 \output_op__output_carry$72 \output_op__input_carry$71 { \output_op__write_cr__ok$70 \output_op__write_cr__data$69 } { \output_op__oe__oe_ok$68 \output_op__oe__oe$67 } { \output_op__rc__rc_ok$66 \output_op__rc__rc$65 } { \output_op__imm_data__imm_ok$64 \output_op__imm_data__imm$63 } \output_op__fn_unit$62 \output_op__insn_type$61 }
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 \o$109
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 \o_ok$110
- process $group_89
- assign \o$109 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \o_ok$110 1'0
- assign { \o_ok$110 \o$109 } { \output_o_ok$79 \output_o$78 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 11 \op__fn_unit$44
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 \op__imm_data__imm$45
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__imm_data__imm_ok$46
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__rc__rc$47
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__rc__rc_ok$48
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__oe__oe$49
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__oe__oe_ok$50
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__invert_a$51
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__zero_a$52
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__invert_out$53
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__write_cr0$54
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__is_32bit$55
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__is_signed$56
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 \op__insn$57
+ process $group_25
+ assign \op__insn_type$43 7'0000000
+ assign \op__fn_unit$44 11'00000000000
+ assign \op__imm_data__imm$45 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \op__imm_data__imm_ok$46 1'0
+ assign \op__rc__rc$47 1'0
+ assign \op__rc__rc_ok$48 1'0
+ assign \op__oe__oe$49 1'0
+ assign \op__oe__oe_ok$50 1'0
+ assign \op__invert_a$51 1'0
+ assign \op__zero_a$52 1'0
+ assign \op__invert_out$53 1'0
+ assign \op__write_cr0$54 1'0
+ assign \op__is_32bit$55 1'0
+ assign \op__is_signed$56 1'0
+ assign \op__insn$57 32'00000000000000000000000000000000
+ assign { \op__insn$57 \op__is_signed$56 \op__is_32bit$55 \op__write_cr0$54 \op__invert_out$53 \op__zero_a$52 \op__invert_a$51 { \op__oe__oe_ok$50 \op__oe__oe$49 } { \op__rc__rc_ok$48 \op__rc__rc$47 } { \op__imm_data__imm_ok$46 \op__imm_data__imm$45 } \op__fn_unit$44 \op__insn_type$43 } { \mul2_op__insn$35 \mul2_op__is_signed$34 \mul2_op__is_32bit$33 \mul2_op__write_cr0$32 \mul2_op__invert_out$31 \mul2_op__zero_a$30 \mul2_op__invert_a$29 { \mul2_op__oe__oe_ok$28 \mul2_op__oe__oe$27 } { \mul2_op__rc__rc_ok$26 \mul2_op__rc__rc$25 } { \mul2_op__imm_data__imm_ok$24 \mul2_op__imm_data__imm$23 } \mul2_op__fn_unit$22 \mul2_op__insn_type$21 }
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 129 \o$58
+ process $group_40
+ assign \o$58 129'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
+ assign \o$58 \mul2_o
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 4 \cr_a$111
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 \cr_a_ok$112
- process $group_91
- assign \cr_a$111 4'0000
- assign \cr_a_ok$112 1'0
- assign { \cr_a_ok$112 \cr_a$111 } { \output_cr_a_ok \output_cr_a$80 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 1 \xer_so$59
+ process $group_41
+ assign \xer_so$59 1'0
+ assign \xer_so$59 \mul2_xer_so$36
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 2 \xer_ca$113
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 \xer_ca_ok$114
- process $group_93
- assign \xer_ca$113 2'00
- assign \xer_ca_ok$114 1'0
- assign { \xer_ca_ok$114 \xer_ca$113 } { \output_xer_ca_ok \output_xer_ca$81 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23"
+ wire width 1 \neg_res$60
+ process $group_42
+ assign \neg_res$60 1'0
+ assign \neg_res$60 \mul2_neg_res$37
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24"
+ wire width 1 \neg_res32$61
+ process $group_43
+ assign \neg_res32$61 1'0
+ assign \neg_res32$61 \mul2_neg_res32$38
sync init
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615"
wire width 1 \r_busy
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615"
wire width 1 \r_busy$next
- process $group_95
+ process $group_44
assign \r_busy$next \r_busy
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
switch { \n_i_rdy_data \p_valid_i_p_ready_o }
sync posedge \clk
update \r_busy \r_busy$next
end
- process $group_96
+ process $group_45
assign \muxid$1$next \muxid$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
switch { \n_i_rdy_data \p_valid_i_p_ready_o }
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
case 2'-1
- assign \muxid$1$next \muxid$91
+ assign \muxid$1$next \muxid$42
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
case 2'1-
- assign \muxid$1$next \muxid$91
+ assign \muxid$1$next \muxid$42
end
sync init
update \muxid$1 2'00
sync posedge \clk
update \muxid$1 \muxid$1$next
end
- process $group_97
+ process $group_46
assign \op__insn_type$2$next \op__insn_type$2
assign \op__fn_unit$3$next \op__fn_unit$3
assign \op__imm_data__imm$4$next \op__imm_data__imm$4
assign \op__rc__rc_ok$7$next \op__rc__rc_ok$7
assign \op__oe__oe$8$next \op__oe__oe$8
assign \op__oe__oe_ok$9$next \op__oe__oe_ok$9
- assign \op__write_cr__data$10$next \op__write_cr__data$10
- assign \op__write_cr__ok$11$next \op__write_cr__ok$11
- assign \op__input_carry$12$next \op__input_carry$12
- assign \op__output_carry$13$next \op__output_carry$13
- assign \op__input_cr$14$next \op__input_cr$14
- assign \op__output_cr$15$next \op__output_cr$15
- assign \op__is_32bit$16$next \op__is_32bit$16
- assign \op__is_signed$17$next \op__is_signed$17
- assign \op__insn$18$next \op__insn$18
+ assign \op__invert_a$10$next \op__invert_a$10
+ assign \op__zero_a$11$next \op__zero_a$11
+ assign \op__invert_out$12$next \op__invert_out$12
+ assign \op__write_cr0$13$next \op__write_cr0$13
+ assign \op__is_32bit$14$next \op__is_32bit$14
+ assign \op__is_signed$15$next \op__is_signed$15
+ assign \op__insn$16$next \op__insn$16
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
switch { \n_i_rdy_data \p_valid_i_p_ready_o }
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
case 2'-1
- assign { \op__insn$18$next \op__is_signed$17$next \op__is_32bit$16$next \op__output_cr$15$next \op__input_cr$14$next \op__output_carry$13$next \op__input_carry$12$next { \op__write_cr__ok$11$next \op__write_cr__data$10$next } { \op__oe__oe_ok$9$next \op__oe__oe$8$next } { \op__rc__rc_ok$7$next \op__rc__rc$6$next } { \op__imm_data__imm_ok$5$next \op__imm_data__imm$4$next } \op__fn_unit$3$next \op__insn_type$2$next } { \op__insn$108 \op__is_signed$107 \op__is_32bit$106 \op__output_cr$105 \op__input_cr$104 \op__output_carry$103 \op__input_carry$102 { \op__write_cr__ok$101 \op__write_cr__data$100 } { \op__oe__oe_ok$99 \op__oe__oe$98 } { \op__rc__rc_ok$97 \op__rc__rc$96 } { \op__imm_data__imm_ok$95 \op__imm_data__imm$94 } \op__fn_unit$93 \op__insn_type$92 }
+ assign { \op__insn$16$next \op__is_signed$15$next \op__is_32bit$14$next \op__write_cr0$13$next \op__invert_out$12$next \op__zero_a$11$next \op__invert_a$10$next { \op__oe__oe_ok$9$next \op__oe__oe$8$next } { \op__rc__rc_ok$7$next \op__rc__rc$6$next } { \op__imm_data__imm_ok$5$next \op__imm_data__imm$4$next } \op__fn_unit$3$next \op__insn_type$2$next } { \op__insn$57 \op__is_signed$56 \op__is_32bit$55 \op__write_cr0$54 \op__invert_out$53 \op__zero_a$52 \op__invert_a$51 { \op__oe__oe_ok$50 \op__oe__oe$49 } { \op__rc__rc_ok$48 \op__rc__rc$47 } { \op__imm_data__imm_ok$46 \op__imm_data__imm$45 } \op__fn_unit$44 \op__insn_type$43 }
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
case 2'1-
- assign { \op__insn$18$next \op__is_signed$17$next \op__is_32bit$16$next \op__output_cr$15$next \op__input_cr$14$next \op__output_carry$13$next \op__input_carry$12$next { \op__write_cr__ok$11$next \op__write_cr__data$10$next } { \op__oe__oe_ok$9$next \op__oe__oe$8$next } { \op__rc__rc_ok$7$next \op__rc__rc$6$next } { \op__imm_data__imm_ok$5$next \op__imm_data__imm$4$next } \op__fn_unit$3$next \op__insn_type$2$next } { \op__insn$108 \op__is_signed$107 \op__is_32bit$106 \op__output_cr$105 \op__input_cr$104 \op__output_carry$103 \op__input_carry$102 { \op__write_cr__ok$101 \op__write_cr__data$100 } { \op__oe__oe_ok$99 \op__oe__oe$98 } { \op__rc__rc_ok$97 \op__rc__rc$96 } { \op__imm_data__imm_ok$95 \op__imm_data__imm$94 } \op__fn_unit$93 \op__insn_type$92 }
+ assign { \op__insn$16$next \op__is_signed$15$next \op__is_32bit$14$next \op__write_cr0$13$next \op__invert_out$12$next \op__zero_a$11$next \op__invert_a$10$next { \op__oe__oe_ok$9$next \op__oe__oe$8$next } { \op__rc__rc_ok$7$next \op__rc__rc$6$next } { \op__imm_data__imm_ok$5$next \op__imm_data__imm$4$next } \op__fn_unit$3$next \op__insn_type$2$next } { \op__insn$57 \op__is_signed$56 \op__is_32bit$55 \op__write_cr0$54 \op__invert_out$53 \op__zero_a$52 \op__invert_a$51 { \op__oe__oe_ok$50 \op__oe__oe$49 } { \op__rc__rc_ok$48 \op__rc__rc$47 } { \op__imm_data__imm_ok$46 \op__imm_data__imm$45 } \op__fn_unit$44 \op__insn_type$43 }
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
assign \op__rc__rc_ok$7$next 1'0
assign \op__oe__oe$8$next 1'0
assign \op__oe__oe_ok$9$next 1'0
- assign \op__write_cr__data$10$next 3'000
- assign \op__write_cr__ok$11$next 1'0
- assign \op__insn$18$next 32'00000000000000000000000000000000
end
sync init
update \op__insn_type$2 7'0000000
update \op__rc__rc_ok$7 1'0
update \op__oe__oe$8 1'0
update \op__oe__oe_ok$9 1'0
- update \op__write_cr__data$10 3'000
- update \op__write_cr__ok$11 1'0
- update \op__input_carry$12 2'00
- update \op__output_carry$13 1'0
- update \op__input_cr$14 1'0
- update \op__output_cr$15 1'0
- update \op__is_32bit$16 1'0
- update \op__is_signed$17 1'0
- update \op__insn$18 32'00000000000000000000000000000000
+ update \op__invert_a$10 1'0
+ update \op__zero_a$11 1'0
+ update \op__invert_out$12 1'0
+ update \op__write_cr0$13 1'0
+ update \op__is_32bit$14 1'0
+ update \op__is_signed$15 1'0
+ update \op__insn$16 32'00000000000000000000000000000000
sync posedge \clk
update \op__insn_type$2 \op__insn_type$2$next
update \op__fn_unit$3 \op__fn_unit$3$next
update \op__rc__rc_ok$7 \op__rc__rc_ok$7$next
update \op__oe__oe$8 \op__oe__oe$8$next
update \op__oe__oe_ok$9 \op__oe__oe_ok$9$next
- update \op__write_cr__data$10 \op__write_cr__data$10$next
- update \op__write_cr__ok$11 \op__write_cr__ok$11$next
- update \op__input_carry$12 \op__input_carry$12$next
- update \op__output_carry$13 \op__output_carry$13$next
- update \op__input_cr$14 \op__input_cr$14$next
- update \op__output_cr$15 \op__output_cr$15$next
- update \op__is_32bit$16 \op__is_32bit$16$next
- update \op__is_signed$17 \op__is_signed$17$next
- update \op__insn$18 \op__insn$18$next
+ update \op__invert_a$10 \op__invert_a$10$next
+ update \op__zero_a$11 \op__zero_a$11$next
+ update \op__invert_out$12 \op__invert_out$12$next
+ update \op__write_cr0$13 \op__write_cr0$13$next
+ update \op__is_32bit$14 \op__is_32bit$14$next
+ update \op__is_signed$15 \op__is_signed$15$next
+ update \op__insn$16 \op__insn$16$next
end
- process $group_114
+ process $group_61
assign \o$next \o
- assign \o_ok$next \o_ok
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
switch { \n_i_rdy_data \p_valid_i_p_ready_o }
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
case 2'-1
- assign { \o_ok$next \o$next } { \o_ok$110 \o$109 }
+ assign \o$next \o$58
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
case 2'1-
- assign { \o_ok$next \o$next } { \o_ok$110 \o$109 }
- end
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
- switch \rst
- case 1'1
- assign \o_ok$next 1'0
+ assign \o$next \o$58
end
sync init
- update \o 64'0000000000000000000000000000000000000000000000000000000000000000
- update \o_ok 1'0
+ update \o 129'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
sync posedge \clk
update \o \o$next
- update \o_ok \o_ok$next
end
- process $group_116
- assign \cr_a$next \cr_a
- assign \cr_a_ok$next \cr_a_ok
+ process $group_62
+ assign \xer_so$17$next \xer_so$17
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
switch { \n_i_rdy_data \p_valid_i_p_ready_o }
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
case 2'-1
- assign { \cr_a_ok$next \cr_a$next } { \cr_a_ok$112 \cr_a$111 }
+ assign \xer_so$17$next \xer_so$59
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
case 2'1-
- assign { \cr_a_ok$next \cr_a$next } { \cr_a_ok$112 \cr_a$111 }
- end
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
- switch \rst
- case 1'1
- assign \cr_a_ok$next 1'0
+ assign \xer_so$17$next \xer_so$59
end
sync init
- update \cr_a 4'0000
- update \cr_a_ok 1'0
+ update \xer_so$17 1'0
sync posedge \clk
- update \cr_a \cr_a$next
- update \cr_a_ok \cr_a_ok$next
+ update \xer_so$17 \xer_so$17$next
end
- process $group_118
- assign \xer_ca$19$next \xer_ca$19
- assign \xer_ca_ok$next \xer_ca_ok
+ process $group_63
+ assign \neg_res$18$next \neg_res$18
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
switch { \n_i_rdy_data \p_valid_i_p_ready_o }
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
case 2'-1
- assign { \xer_ca_ok$next \xer_ca$19$next } { \xer_ca_ok$114 \xer_ca$113 }
+ assign \neg_res$18$next \neg_res$60
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
case 2'1-
- assign { \xer_ca_ok$next \xer_ca$19$next } { \xer_ca_ok$114 \xer_ca$113 }
+ assign \neg_res$18$next \neg_res$60
end
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
- switch \rst
- case 1'1
- assign \xer_ca_ok$next 1'0
+ sync init
+ update \neg_res$18 1'0
+ sync posedge \clk
+ update \neg_res$18 \neg_res$18$next
+ end
+ process $group_64
+ assign \neg_res32$19$next \neg_res32$19
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+ switch { \n_i_rdy_data \p_valid_i_p_ready_o }
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+ case 2'-1
+ assign \neg_res32$19$next \neg_res32$61
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
+ case 2'1-
+ assign \neg_res32$19$next \neg_res32$61
end
sync init
- update \xer_ca$19 2'00
- update \xer_ca_ok 1'0
+ update \neg_res32$19 1'0
sync posedge \clk
- update \xer_ca$19 \xer_ca$19$next
- update \xer_ca_ok \xer_ca_ok$next
+ update \neg_res32$19 \neg_res32$19$next
end
- process $group_120
+ process $group_65
assign \n_valid_o 1'0
assign \n_valid_o \r_busy
sync init
end
- process $group_121
+ process $group_66
assign \p_ready_o 1'0
assign \p_ready_o \n_i_rdy_data
sync init
end
- connect \cr_a$84 4'0000
- connect \cr_a_ok$85 1'0
- connect \xer_ca_ok$87 1'0
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0"
-module \alu_shift_rot0
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
- wire width 1 input 0 \rst
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
- wire width 1 input 1 \clk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 2 \o_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 output 3 \o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 4 \cr_a_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 4 output 5 \cr_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 6 \xer_ca_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 2 output 7 \xer_ca
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244"
- wire width 1 output 8 \n_valid_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245"
- wire width 1 input 9 \n_ready_i
- attribute \enum_base_type "InternalOp"
+attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe3.p"
+module \p$77
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153"
+ wire width 1 input 0 \p_valid_i
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154"
+ wire width 1 input 1 \p_ready_o
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158"
+ wire width 1 \trigger
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205"
+ wire width 1 $1
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205"
+ cell $and $2
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \p_valid_i
+ connect \B \p_ready_o
+ connect \Y $1
+ end
+ process $group_0
+ assign \trigger 1'0
+ assign \trigger $1
+ sync init
+ end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe3.n"
+module \n$78
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
+ wire width 1 input 0 \n_valid_o
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
+ wire width 1 input 1 \n_ready_i
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251"
+ wire width 1 \trigger
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:297"
+ wire width 1 $1
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:297"
+ cell $and $2
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \n_ready_i
+ connect \B \n_valid_o
+ connect \Y $1
+ end
+ process $group_0
+ assign \trigger 1'0
+ assign \trigger $1
+ sync init
+ end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe3.mul3"
+module \mul3
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+ wire width 2 input 0 \muxid
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 7 input 10 \op__insn_type
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 7 input 1 \op__insn_type
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00000000010 "ALU"
attribute \enum_value_00100000000 "MUL"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 11 input 11 \op__fn_unit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 64 input 12 \op__imm_data__imm
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 input 13 \op__imm_data__imm_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 input 14 \op__rc__rc
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 input 15 \op__rc__rc_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 input 16 \op__oe__oe
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 input 17 \op__oe__oe_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 3 input 18 \op__write_cr__data
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 input 19 \op__write_cr__ok
- attribute \enum_base_type "CryIn"
- attribute \enum_value_00 "ZERO"
- attribute \enum_value_01 "ONE"
- attribute \enum_value_10 "CA"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 2 input 20 \op__input_carry
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 input 21 \op__output_carry
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 input 22 \op__input_cr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 input 23 \op__output_cr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 input 24 \op__is_32bit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 input 25 \op__is_signed
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 32 input 26 \op__insn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
- wire width 64 input 27 \ra
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
- wire width 64 input 28 \rb
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
- wire width 64 input 29 \rc
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
- wire width 2 input 30 \xer_ca$1
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151"
- wire width 1 input 31 \p_valid_i
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152"
- wire width 1 output 32 \p_ready_o
- cell \p$70 \p
- connect \p_valid_i \p_valid_i
- connect \p_ready_o \p_ready_o
- end
- cell \n$71 \n
- connect \n_valid_o \n_valid_o
- connect \n_ready_i \n_ready_i
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151"
- wire width 1 \pipe_p_valid_i
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152"
- wire width 1 \pipe_p_ready_o
- attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
- wire width 2 \pipe_muxid
- attribute \enum_base_type "InternalOp"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 11 input 2 \op__fn_unit
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 input 3 \op__imm_data__imm
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 4 \op__imm_data__imm_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 5 \op__rc__rc
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 6 \op__rc__rc_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 7 \op__oe__oe
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 8 \op__oe__oe_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 9 \op__invert_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 10 \op__zero_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 11 \op__invert_out
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 12 \op__write_cr0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 13 \op__is_32bit
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 14 \op__is_signed
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 input 15 \op__insn
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 129 input 16 \o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 1 input 17 \xer_so
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23"
+ wire width 1 input 18 \neg_res
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+ wire width 2 output 19 \muxid$1
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 7 \pipe_op__insn_type
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 7 output 20 \op__insn_type$2
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00000000010 "ALU"
attribute \enum_value_00100000000 "MUL"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 11 \pipe_op__fn_unit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 64 \pipe_op__imm_data__imm
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 \pipe_op__imm_data__imm_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 \pipe_op__rc__rc
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 \pipe_op__rc__rc_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 \pipe_op__oe__oe
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 \pipe_op__oe__oe_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 3 \pipe_op__write_cr__data
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 \pipe_op__write_cr__ok
- attribute \enum_base_type "CryIn"
- attribute \enum_value_00 "ZERO"
- attribute \enum_value_01 "ONE"
- attribute \enum_value_10 "CA"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 2 \pipe_op__input_carry
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 \pipe_op__output_carry
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 \pipe_op__input_cr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 \pipe_op__output_cr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 \pipe_op__is_32bit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 \pipe_op__is_signed
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 32 \pipe_op__insn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
- wire width 64 \pipe_ra
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
- wire width 64 \pipe_rb
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
- wire width 64 \pipe_rc
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
- wire width 2 \pipe_xer_ca
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244"
- wire width 1 \pipe_n_valid_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245"
- wire width 1 \pipe_n_ready_i
- attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
- wire width 2 \pipe_muxid$2
- attribute \enum_base_type "InternalOp"
- attribute \enum_value_0000000 "OP_ILLEGAL"
- attribute \enum_value_0000001 "OP_NOP"
- attribute \enum_value_0000010 "OP_ADD"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 11 output 21 \op__fn_unit$3
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 output 22 \op__imm_data__imm$4
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 23 \op__imm_data__imm_ok$5
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 24 \op__rc__rc$6
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 25 \op__rc__rc_ok$7
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 26 \op__oe__oe$8
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 27 \op__oe__oe_ok$9
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 28 \op__invert_a$10
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 29 \op__zero_a$11
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 30 \op__invert_out$12
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 31 \op__write_cr0$13
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 32 \op__is_32bit$14
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 33 \op__is_signed$15
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 output 34 \op__insn$16
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 64 output 35 \o$17
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 36 \o_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 2 output 37 \xer_ov
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 38 \xer_ov_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 39 \xer_so$18
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:36"
+ wire width 1 \is_32bit
+ process $group_0
+ assign \is_32bit 1'0
+ assign \is_32bit \op__is_32bit
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:40"
+ wire width 129 \mul_o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41"
+ wire width 130 $19
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41"
+ wire width 130 $20
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41"
+ cell $neg $21
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 129
+ parameter \Y_WIDTH 130
+ connect \A \o
+ connect \Y $20
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 130 $22
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ cell $pos $23
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 129
+ parameter \Y_WIDTH 130
+ connect \A \o
+ connect \Y $22
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41"
+ wire width 130 $24
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41"
+ cell $mux $25
+ parameter \WIDTH 130
+ connect \A $22
+ connect \B $20
+ connect \S \neg_res
+ connect \Y $24
+ end
+ connect $19 $24
+ process $group_1
+ assign \mul_o 129'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
+ assign \mul_o $19 [128:0]
+ sync init
+ end
+ wire width 1 $verilog_initial_trigger
+ process $group_2
+ assign \o_ok 1'0
+ assign \o_ok 1'1
+ assign $verilog_initial_trigger $verilog_initial_trigger
+ sync init
+ update $verilog_initial_trigger 1'0
+ end
+ process $group_3
+ assign \o$17 64'0000000000000000000000000000000000000000000000000000000000000000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:45"
+ switch \op__insn_type
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:47"
+ attribute \nmigen.decoding "OP_MUL_H32/52"
+ case 7'0110100
+ assign \o$17 { \mul_o [63:32] \mul_o [63:32] }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:50"
+ attribute \nmigen.decoding "OP_MUL_H64/51"
+ case 7'0110011
+ assign \o$17 \mul_o [127:64]
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:53"
+ attribute \nmigen.decoding ""
+ case
+ assign \o$17 \mul_o [63:0]
+ end
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:58"
+ wire width 1 \mul_ov
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:63"
+ wire width 1 $26
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:63"
+ cell $reduce_bool $27
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 33
+ parameter \Y_WIDTH 1
+ connect \A \mul_o [63:31]
+ connect \Y $26
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:63"
+ wire width 1 $28
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:63"
+ wire width 1 $29
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:63"
+ cell $reduce_and $30
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 33
+ parameter \Y_WIDTH 1
+ connect \A \mul_o [63:31]
+ connect \Y $29
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:63"
+ cell $not $31
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A $29
+ connect \Y $28
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:63"
+ wire width 1 $32
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:63"
+ cell $and $33
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A $26
+ connect \B $28
+ connect \Y $32
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:68"
+ wire width 1 $34
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:68"
+ cell $reduce_bool $35
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 65
+ parameter \Y_WIDTH 1
+ connect \A \mul_o [127:63]
+ connect \Y $34
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:68"
+ wire width 1 $36
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:68"
+ wire width 1 $37
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:68"
+ cell $reduce_and $38
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 65
+ parameter \Y_WIDTH 1
+ connect \A \mul_o [127:63]
+ connect \Y $37
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:68"
+ cell $not $39
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A $37
+ connect \Y $36
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:68"
+ wire width 1 $40
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:68"
+ cell $and $41
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A $34
+ connect \B $36
+ connect \Y $40
+ end
+ process $group_4
+ assign \mul_ov 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:45"
+ switch \op__insn_type
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:47"
+ attribute \nmigen.decoding "OP_MUL_H32/52"
+ case 7'0110100
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:50"
+ attribute \nmigen.decoding "OP_MUL_H64/51"
+ case 7'0110011
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:53"
+ attribute \nmigen.decoding ""
+ case
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:59"
+ switch { \is_32bit }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:59"
+ case 1'1
+ assign \mul_ov $32
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:64"
+ case
+ assign \mul_ov $40
+ end
+ end
+ sync init
+ end
+ process $group_5
+ assign \xer_ov 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:45"
+ switch \op__insn_type
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:47"
+ attribute \nmigen.decoding "OP_MUL_H32/52"
+ case 7'0110100
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:50"
+ attribute \nmigen.decoding "OP_MUL_H64/51"
+ case 7'0110011
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:53"
+ attribute \nmigen.decoding ""
+ case
+ assign \xer_ov { \mul_ov \mul_ov }
+ end
+ sync init
+ end
+ process $group_6
+ assign \xer_ov_ok 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:45"
+ switch \op__insn_type
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:47"
+ attribute \nmigen.decoding "OP_MUL_H32/52"
+ case 7'0110100
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:50"
+ attribute \nmigen.decoding "OP_MUL_H64/51"
+ case 7'0110011
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:53"
+ attribute \nmigen.decoding ""
+ case
+ assign \xer_ov_ok 1'1
+ end
+ sync init
+ end
+ process $group_7
+ assign \xer_so$18 1'0
+ assign \xer_so$18 \xer_so
+ sync init
+ end
+ process $group_8
+ assign \muxid$1 2'00
+ assign \muxid$1 \muxid
+ sync init
+ end
+ process $group_9
+ assign \op__insn_type$2 7'0000000
+ assign \op__fn_unit$3 11'00000000000
+ assign \op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \op__imm_data__imm_ok$5 1'0
+ assign \op__rc__rc$6 1'0
+ assign \op__rc__rc_ok$7 1'0
+ assign \op__oe__oe$8 1'0
+ assign \op__oe__oe_ok$9 1'0
+ assign \op__invert_a$10 1'0
+ assign \op__zero_a$11 1'0
+ assign \op__invert_out$12 1'0
+ assign \op__write_cr0$13 1'0
+ assign \op__is_32bit$14 1'0
+ assign \op__is_signed$15 1'0
+ assign \op__insn$16 32'00000000000000000000000000000000
+ assign { \op__insn$16 \op__is_signed$15 \op__is_32bit$14 \op__write_cr0$13 \op__invert_out$12 \op__zero_a$11 \op__invert_a$10 { \op__oe__oe_ok$9 \op__oe__oe$8 } { \op__rc__rc_ok$7 \op__rc__rc$6 } { \op__imm_data__imm_ok$5 \op__imm_data__imm$4 } \op__fn_unit$3 \op__insn_type$2 } { \op__insn \op__is_signed \op__is_32bit \op__write_cr0 \op__invert_out \op__zero_a \op__invert_a { \op__oe__oe_ok \op__oe__oe } { \op__rc__rc_ok \op__rc__rc } { \op__imm_data__imm_ok \op__imm_data__imm } \op__fn_unit \op__insn_type }
+ sync init
+ end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe3.output"
+module \output$79
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+ wire width 2 input 0 \muxid
+ attribute \enum_base_type "MicrOp"
+ attribute \enum_value_0000000 "OP_ILLEGAL"
+ attribute \enum_value_0000001 "OP_NOP"
+ attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_0000011 "OP_ADDPCIS"
attribute \enum_value_0000100 "OP_AND"
attribute \enum_value_0000101 "OP_ATTN"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 7 \pipe_op__insn_type$3
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 7 input 1 \op__insn_type
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00000000010 "ALU"
attribute \enum_value_00100000000 "MUL"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 11 \pipe_op__fn_unit$4
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 64 \pipe_op__imm_data__imm$5
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 \pipe_op__imm_data__imm_ok$6
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 \pipe_op__rc__rc$7
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 \pipe_op__rc__rc_ok$8
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 \pipe_op__oe__oe$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 \pipe_op__oe__oe_ok$10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 3 \pipe_op__write_cr__data$11
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 \pipe_op__write_cr__ok$12
- attribute \enum_base_type "CryIn"
- attribute \enum_value_00 "ZERO"
- attribute \enum_value_01 "ONE"
- attribute \enum_value_10 "CA"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 2 \pipe_op__input_carry$13
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 \pipe_op__output_carry$14
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 \pipe_op__input_cr$15
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 \pipe_op__output_cr$16
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 \pipe_op__is_32bit$17
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 \pipe_op__is_signed$18
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 32 \pipe_op__insn$19
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 \pipe_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 \pipe_o_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 4 \pipe_cr_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 \pipe_cr_a_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 2 \pipe_xer_ca$20
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 \pipe_xer_ca_ok
- cell \pipe$72 \pipe
- connect \rst \rst
- connect \clk \clk
- connect \p_valid_i \pipe_p_valid_i
- connect \p_ready_o \pipe_p_ready_o
- connect \muxid \pipe_muxid
- connect \op__insn_type \pipe_op__insn_type
- connect \op__fn_unit \pipe_op__fn_unit
- connect \op__imm_data__imm \pipe_op__imm_data__imm
- connect \op__imm_data__imm_ok \pipe_op__imm_data__imm_ok
- connect \op__rc__rc \pipe_op__rc__rc
- connect \op__rc__rc_ok \pipe_op__rc__rc_ok
- connect \op__oe__oe \pipe_op__oe__oe
- connect \op__oe__oe_ok \pipe_op__oe__oe_ok
- connect \op__write_cr__data \pipe_op__write_cr__data
- connect \op__write_cr__ok \pipe_op__write_cr__ok
- connect \op__input_carry \pipe_op__input_carry
- connect \op__output_carry \pipe_op__output_carry
- connect \op__input_cr \pipe_op__input_cr
- connect \op__output_cr \pipe_op__output_cr
- connect \op__is_32bit \pipe_op__is_32bit
- connect \op__is_signed \pipe_op__is_signed
- connect \op__insn \pipe_op__insn
- connect \ra \pipe_ra
- connect \rb \pipe_rb
- connect \rc \pipe_rc
- connect \xer_ca \pipe_xer_ca
- connect \n_valid_o \pipe_n_valid_o
- connect \n_ready_i \pipe_n_ready_i
- connect \muxid$1 \pipe_muxid$2
- connect \op__insn_type$2 \pipe_op__insn_type$3
- connect \op__fn_unit$3 \pipe_op__fn_unit$4
- connect \op__imm_data__imm$4 \pipe_op__imm_data__imm$5
- connect \op__imm_data__imm_ok$5 \pipe_op__imm_data__imm_ok$6
- connect \op__rc__rc$6 \pipe_op__rc__rc$7
- connect \op__rc__rc_ok$7 \pipe_op__rc__rc_ok$8
- connect \op__oe__oe$8 \pipe_op__oe__oe$9
- connect \op__oe__oe_ok$9 \pipe_op__oe__oe_ok$10
- connect \op__write_cr__data$10 \pipe_op__write_cr__data$11
- connect \op__write_cr__ok$11 \pipe_op__write_cr__ok$12
- connect \op__input_carry$12 \pipe_op__input_carry$13
- connect \op__output_carry$13 \pipe_op__output_carry$14
- connect \op__input_cr$14 \pipe_op__input_cr$15
- connect \op__output_cr$15 \pipe_op__output_cr$16
- connect \op__is_32bit$16 \pipe_op__is_32bit$17
- connect \op__is_signed$17 \pipe_op__is_signed$18
- connect \op__insn$18 \pipe_op__insn$19
- connect \o \pipe_o
- connect \o_ok \pipe_o_ok
- connect \cr_a \pipe_cr_a
- connect \cr_a_ok \pipe_cr_a_ok
- connect \xer_ca$19 \pipe_xer_ca$20
- connect \xer_ca_ok \pipe_xer_ca_ok
- end
- process $group_0
- assign \pipe_p_valid_i 1'0
- assign \pipe_p_valid_i \p_valid_i
- sync init
- end
- process $group_1
- assign \p_ready_o 1'0
- assign \p_ready_o \pipe_p_ready_o
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
- wire width 2 \muxid
- process $group_2
- assign \pipe_muxid 2'00
- assign \pipe_muxid \muxid
- sync init
- end
- process $group_3
- assign \pipe_op__insn_type 7'0000000
- assign \pipe_op__fn_unit 11'00000000000
- assign \pipe_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \pipe_op__imm_data__imm_ok 1'0
- assign \pipe_op__rc__rc 1'0
- assign \pipe_op__rc__rc_ok 1'0
- assign \pipe_op__oe__oe 1'0
- assign \pipe_op__oe__oe_ok 1'0
- assign \pipe_op__write_cr__data 3'000
- assign \pipe_op__write_cr__ok 1'0
- assign \pipe_op__input_carry 2'00
- assign \pipe_op__output_carry 1'0
- assign \pipe_op__input_cr 1'0
- assign \pipe_op__output_cr 1'0
- assign \pipe_op__is_32bit 1'0
- assign \pipe_op__is_signed 1'0
- assign \pipe_op__insn 32'00000000000000000000000000000000
- assign { \pipe_op__insn \pipe_op__is_signed \pipe_op__is_32bit \pipe_op__output_cr \pipe_op__input_cr \pipe_op__output_carry \pipe_op__input_carry { \pipe_op__write_cr__ok \pipe_op__write_cr__data } { \pipe_op__oe__oe_ok \pipe_op__oe__oe } { \pipe_op__rc__rc_ok \pipe_op__rc__rc } { \pipe_op__imm_data__imm_ok \pipe_op__imm_data__imm } \pipe_op__fn_unit \pipe_op__insn_type } { \op__insn \op__is_signed \op__is_32bit \op__output_cr \op__input_cr \op__output_carry \op__input_carry { \op__write_cr__ok \op__write_cr__data } { \op__oe__oe_ok \op__oe__oe } { \op__rc__rc_ok \op__rc__rc } { \op__imm_data__imm_ok \op__imm_data__imm } \op__fn_unit \op__insn_type }
- sync init
- end
- process $group_20
- assign \pipe_ra 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \pipe_ra \ra
- sync init
- end
- process $group_21
- assign \pipe_rb 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \pipe_rb \rb
- sync init
- end
- process $group_22
- assign \pipe_rc 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \pipe_rc \rc
- sync init
- end
- process $group_23
- assign \pipe_xer_ca 2'00
- assign \pipe_xer_ca \xer_ca$1
- sync init
- end
- process $group_24
- assign \n_valid_o 1'0
- assign \n_valid_o \pipe_n_valid_o
- sync init
- end
- process $group_25
- assign \pipe_n_ready_i 1'0
- assign \pipe_n_ready_i \n_ready_i
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/ieee754fpu/src/ieee754/fpcommon/getop.py:60"
- wire width 2 \muxid$21
- process $group_26
- assign \muxid$21 2'00
- assign \muxid$21 \pipe_muxid$2
- sync init
- end
- attribute \enum_base_type "InternalOp"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 11 input 2 \op__fn_unit
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 input 3 \op__imm_data__imm
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 4 \op__imm_data__imm_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 5 \op__rc__rc
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 6 \op__rc__rc_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 7 \op__oe__oe
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 8 \op__oe__oe_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 9 \op__invert_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 10 \op__zero_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 11 \op__invert_out
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 12 \op__write_cr0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 13 \op__is_32bit
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 14 \op__is_signed
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 input 15 \op__insn
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 64 input 16 \o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 input 17 \o_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 4 input 18 \cr_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 2 input 19 \xer_ov
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 input 20 \xer_so
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+ wire width 2 output 21 \muxid$1
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 7 \op__insn_type$22
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 7 output 22 \op__insn_type$2
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00000000010 "ALU"
attribute \enum_value_00100000000 "MUL"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 11 \op__fn_unit$23
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 64 \op__imm_data__imm$24
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 \op__imm_data__imm_ok$25
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 \op__rc__rc$26
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 \op__rc__rc_ok$27
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 \op__oe__oe$28
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 \op__oe__oe_ok$29
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 3 \op__write_cr__data$30
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 \op__write_cr__ok$31
- attribute \enum_base_type "CryIn"
- attribute \enum_value_00 "ZERO"
- attribute \enum_value_01 "ONE"
- attribute \enum_value_10 "CA"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 2 \op__input_carry$32
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 \op__output_carry$33
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 \op__input_cr$34
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 \op__output_cr$35
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 \op__is_32bit$36
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 \op__is_signed$37
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 32 \op__insn$38
- process $group_27
- assign \op__insn_type$22 7'0000000
- assign \op__fn_unit$23 11'00000000000
- assign \op__imm_data__imm$24 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \op__imm_data__imm_ok$25 1'0
- assign \op__rc__rc$26 1'0
- assign \op__rc__rc_ok$27 1'0
- assign \op__oe__oe$28 1'0
- assign \op__oe__oe_ok$29 1'0
- assign \op__write_cr__data$30 3'000
- assign \op__write_cr__ok$31 1'0
- assign \op__input_carry$32 2'00
- assign \op__output_carry$33 1'0
- assign \op__input_cr$34 1'0
- assign \op__output_cr$35 1'0
- assign \op__is_32bit$36 1'0
- assign \op__is_signed$37 1'0
- assign \op__insn$38 32'00000000000000000000000000000000
- assign { \op__insn$38 \op__is_signed$37 \op__is_32bit$36 \op__output_cr$35 \op__input_cr$34 \op__output_carry$33 \op__input_carry$32 { \op__write_cr__ok$31 \op__write_cr__data$30 } { \op__oe__oe_ok$29 \op__oe__oe$28 } { \op__rc__rc_ok$27 \op__rc__rc$26 } { \op__imm_data__imm_ok$25 \op__imm_data__imm$24 } \op__fn_unit$23 \op__insn_type$22 } { \pipe_op__insn$19 \pipe_op__is_signed$18 \pipe_op__is_32bit$17 \pipe_op__output_cr$16 \pipe_op__input_cr$15 \pipe_op__output_carry$14 \pipe_op__input_carry$13 { \pipe_op__write_cr__ok$12 \pipe_op__write_cr__data$11 } { \pipe_op__oe__oe_ok$10 \pipe_op__oe__oe$9 } { \pipe_op__rc__rc_ok$8 \pipe_op__rc__rc$7 } { \pipe_op__imm_data__imm_ok$6 \pipe_op__imm_data__imm$5 } \pipe_op__fn_unit$4 \pipe_op__insn_type$3 }
- sync init
- end
- process $group_44
- assign \o 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \o_ok 1'0
- assign { \o_ok \o } { \pipe_o_ok \pipe_o }
- sync init
- end
- process $group_46
- assign \cr_a 4'0000
- assign \cr_a_ok 1'0
- assign { \cr_a_ok \cr_a } { \pipe_cr_a_ok \pipe_cr_a }
- sync init
- end
- process $group_48
- assign \xer_ca 2'00
- assign \xer_ca_ok 1'0
- assign { \xer_ca_ok \xer_ca } { \pipe_xer_ca_ok \pipe_xer_ca$20 }
- sync init
- end
- connect \muxid 2'00
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.src_l"
-module \src_l$78
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
- wire width 1 input 0 \rst
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
- wire width 1 input 1 \clk
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
- wire width 4 input 2 \s_src
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
- wire width 4 input 3 \r_src
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
- wire width 4 output 4 \q_src
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
- wire width 4 \q_int
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
- wire width 4 \q_int$next
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
- wire width 4 $1
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
- cell $not $2
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 11 output 23 \op__fn_unit$3
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 output 24 \op__imm_data__imm$4
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 25 \op__imm_data__imm_ok$5
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 26 \op__rc__rc$6
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 27 \op__rc__rc_ok$7
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 28 \op__oe__oe$8
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 29 \op__oe__oe_ok$9
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 30 \op__invert_a$10
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 31 \op__zero_a$11
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 32 \op__invert_out$12
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 33 \op__write_cr0$13
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 34 \op__is_32bit$14
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 35 \op__is_signed$15
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 output 36 \op__insn$16
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 64 output 37 \o$17
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 38 \o_ok$18
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 4 output 39 \cr_a$19
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 40 \cr_a_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 2 output 41 \xer_ov$20
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 42 \xer_ov_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 43 \xer_so$21
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 44 \xer_so_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:23"
+ wire width 65 \o$22
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:26"
+ wire width 65 $23
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:26"
+ wire width 64 $24
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:26"
+ cell $not $25
parameter \A_SIGNED 0
- parameter \A_WIDTH 4
- parameter \Y_WIDTH 4
- connect \A \r_src
- connect \Y $1
+ parameter \A_WIDTH 64
+ parameter \Y_WIDTH 64
+ connect \A \o
+ connect \Y $24
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
- wire width 4 $3
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
- cell $and $4
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:26"
+ cell $pos $26
parameter \A_SIGNED 0
- parameter \A_WIDTH 4
- parameter \B_SIGNED 0
- parameter \B_WIDTH 4
- parameter \Y_WIDTH 4
- connect \A \q_int
- connect \B $1
- connect \Y $3
+ parameter \A_WIDTH 64
+ parameter \Y_WIDTH 65
+ connect \A $24
+ connect \Y $23
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
- wire width 4 $5
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
- cell $or $6
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 65 $27
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ cell $pos $28
parameter \A_SIGNED 0
- parameter \A_WIDTH 4
- parameter \B_SIGNED 0
- parameter \B_WIDTH 4
- parameter \Y_WIDTH 4
- connect \A $3
- connect \B \s_src
- connect \Y $5
+ parameter \A_WIDTH 64
+ parameter \Y_WIDTH 65
+ connect \A \o
+ connect \Y $27
end
process $group_0
- assign \q_int$next \q_int
- assign \q_int$next $5
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
- switch \rst
+ assign \o$22 65'00000000000000000000000000000000000000000000000000000000000000000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:25"
+ switch { \op__invert_out }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:25"
case 1'1
- assign \q_int$next 4'0000
+ assign \o$22 $23
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:27"
+ case
+ assign \o$22 $27
end
sync init
- update \q_int 4'0000
- sync posedge \clk
- update \q_int \q_int$next
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
- wire width 4 $7
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
- cell $not $8
- parameter \A_SIGNED 0
- parameter \A_WIDTH 4
- parameter \Y_WIDTH 4
- connect \A \r_src
- connect \Y $7
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
- wire width 4 $9
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
- cell $and $10
- parameter \A_SIGNED 0
- parameter \A_WIDTH 4
- parameter \B_SIGNED 0
- parameter \B_WIDTH 4
- parameter \Y_WIDTH 4
- connect \A \q_int
- connect \B $7
- connect \Y $9
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
- wire width 4 $11
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
- cell $or $12
- parameter \A_SIGNED 0
- parameter \A_WIDTH 4
- parameter \B_SIGNED 0
- parameter \B_WIDTH 4
- parameter \Y_WIDTH 4
- connect \A $9
- connect \B \s_src
- connect \Y $11
end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:35"
+ wire width 64 \target
process $group_1
- assign \q_src 4'0000
- assign \q_src $11
+ assign \target 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \target \o$22 [63:0]
sync init
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
- wire width 4 \qn_src
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
- wire width 4 $13
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
- cell $not $14
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:54"
+ wire width 1 \is_cmp
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:63"
+ wire width 1 $29
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:63"
+ cell $eq $30
parameter \A_SIGNED 0
- parameter \A_WIDTH 4
- parameter \Y_WIDTH 4
- connect \A \q_src
- connect \Y $13
+ parameter \A_WIDTH 7
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 7
+ parameter \Y_WIDTH 1
+ connect \A \op__insn_type
+ connect \B 7'0001010
+ connect \Y $29
end
process $group_2
- assign \qn_src 4'0000
- assign \qn_src $13
+ assign \is_cmp 1'0
+ assign \is_cmp $29
sync init
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62"
- wire width 4 \qlq_src
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
- wire width 4 $15
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
- cell $or $16
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:55"
+ wire width 1 \is_cmpeqb
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:64"
+ wire width 1 $31
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:64"
+ cell $eq $32
parameter \A_SIGNED 0
- parameter \A_WIDTH 4
+ parameter \A_WIDTH 7
parameter \B_SIGNED 0
- parameter \B_WIDTH 4
- parameter \Y_WIDTH 4
- connect \A \q_src
- connect \B \q_int
- connect \Y $15
+ parameter \B_WIDTH 7
+ parameter \Y_WIDTH 1
+ connect \A \op__insn_type
+ connect \B 7'0001100
+ connect \Y $31
end
process $group_3
- assign \qlq_src 4'0000
- assign \qlq_src $15
+ assign \is_cmpeqb 1'0
+ assign \is_cmpeqb $31
sync init
end
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.opc_l"
-module \opc_l$79
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
- wire width 1 input 0 \rst
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
- wire width 1 input 1 \clk
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
- wire width 1 input 2 \s_opc
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
- wire width 1 input 3 \r_opc
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:53"
+ wire width 1 \msb_test
+ process $group_4
+ assign \msb_test 1'0
+ assign \msb_test \target [63]
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:50"
+ wire width 1 \is_nzero
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71"
+ wire width 1 $33
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71"
+ cell $reduce_bool $34
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 64
+ parameter \Y_WIDTH 1
+ connect \A \target
+ connect \Y $33
+ end
+ process $group_5
+ assign \is_nzero 1'0
+ assign \is_nzero $33
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:51"
+ wire width 1 \is_positive
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77"
+ wire width 1 $35
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77"
+ cell $not $36
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \msb_test
+ connect \Y $35
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77"
+ wire width 1 $37
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77"
+ cell $and $38
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \is_nzero
+ connect \B $35
+ connect \Y $37
+ end
+ process $group_6
+ assign \is_positive 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:72"
+ switch { \is_cmp }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:72"
+ case 1'1
+ assign \is_positive \msb_test
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:75"
+ case
+ assign \is_positive $37
+ end
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:52"
+ wire width 1 \is_negative
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:74"
+ wire width 1 $39
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:74"
+ cell $not $40
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \msb_test
+ connect \Y $39
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:74"
+ wire width 1 $41
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:74"
+ cell $and $42
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \is_nzero
+ connect \B $39
+ connect \Y $41
+ end
+ process $group_7
+ assign \is_negative 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:72"
+ switch { \is_cmp }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:72"
+ case 1'1
+ assign \is_negative $41
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:75"
+ case
+ assign \is_negative \msb_test
+ end
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:57"
+ wire width 4 \cr0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:82"
+ wire width 1 $43
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:82"
+ cell $not $44
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \is_nzero
+ connect \Y $43
+ end
+ process $group_8
+ assign \cr0 4'0000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:79"
+ switch { \is_cmpeqb }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:79"
+ case 1'1
+ assign \cr0 \cr_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81"
+ case
+ assign \cr0 { \is_negative \is_positive $43 \xer_so$21 }
+ end
+ sync init
+ end
+ process $group_9
+ assign \o$17 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \o$17 \o$22 [63:0]
+ sync init
+ end
+ process $group_10
+ assign \o_ok$18 1'0
+ assign \o_ok$18 \o_ok
+ sync init
+ end
+ process $group_11
+ assign \cr_a$19 4'0000
+ assign \cr_a$19 \cr0
+ sync init
+ end
+ process $group_12
+ assign \cr_a_ok 1'0
+ assign \cr_a_ok \op__write_cr0
+ sync init
+ end
+ process $group_13
+ assign \muxid$1 2'00
+ assign \muxid$1 \muxid
+ sync init
+ end
+ process $group_14
+ assign \op__insn_type$2 7'0000000
+ assign \op__fn_unit$3 11'00000000000
+ assign \op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \op__imm_data__imm_ok$5 1'0
+ assign \op__rc__rc$6 1'0
+ assign \op__rc__rc_ok$7 1'0
+ assign \op__oe__oe$8 1'0
+ assign \op__oe__oe_ok$9 1'0
+ assign \op__invert_a$10 1'0
+ assign \op__zero_a$11 1'0
+ assign \op__invert_out$12 1'0
+ assign \op__write_cr0$13 1'0
+ assign \op__is_32bit$14 1'0
+ assign \op__is_signed$15 1'0
+ assign \op__insn$16 32'00000000000000000000000000000000
+ assign { \op__insn$16 \op__is_signed$15 \op__is_32bit$14 \op__write_cr0$13 \op__invert_out$12 \op__zero_a$11 \op__invert_a$10 { \op__oe__oe_ok$9 \op__oe__oe$8 } { \op__rc__rc_ok$7 \op__rc__rc$6 } { \op__imm_data__imm_ok$5 \op__imm_data__imm$4 } \op__fn_unit$3 \op__insn_type$2 } { \op__insn \op__is_signed \op__is_32bit \op__write_cr0 \op__invert_out \op__zero_a \op__invert_a { \op__oe__oe_ok \op__oe__oe } { \op__rc__rc_ok \op__rc__rc } { \op__imm_data__imm_ok \op__imm_data__imm } \op__fn_unit \op__insn_type }
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:28"
+ wire width 1 \oe
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:29"
+ wire width 1 $45
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:29"
+ cell $and $46
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \op__oe__oe
+ connect \B \op__oe__oe_ok
+ connect \Y $45
+ end
+ process $group_29
+ assign \oe 1'0
+ assign \oe $45
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:56"
+ wire width 1 \so
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:32"
+ wire width 1 $47
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:32"
+ cell $or $48
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \xer_so
+ connect \B \xer_ov [0]
+ connect \Y $47
+ end
+ process $group_30
+ assign \so 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30"
+ switch { \oe }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30"
+ case 1'1
+ assign \so $47
+ end
+ sync init
+ end
+ process $group_31
+ assign \xer_so$21 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30"
+ switch { \oe }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30"
+ case 1'1
+ assign \xer_so$21 \so
+ end
+ sync init
+ end
+ process $group_32
+ assign \xer_so_ok 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30"
+ switch { \oe }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30"
+ case 1'1
+ assign \xer_so_ok 1'1
+ end
+ sync init
+ end
+ process $group_33
+ assign \xer_ov$20 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30"
+ switch { \oe }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30"
+ case 1'1
+ assign \xer_ov$20 \xer_ov
+ end
+ sync init
+ end
+ process $group_34
+ assign \xer_ov_ok 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30"
+ switch { \oe }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30"
+ case 1'1
+ assign \xer_ov_ok 1'1
+ end
+ sync init
+ end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe3"
+module \mul_pipe3
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
+ wire width 1 input 0 \rst
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
+ wire width 1 input 1 \clk
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153"
+ wire width 1 input 2 \p_valid_i
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154"
+ wire width 1 output 3 \p_ready_o
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+ wire width 2 input 4 \muxid
+ attribute \enum_base_type "MicrOp"
+ attribute \enum_value_0000000 "OP_ILLEGAL"
+ attribute \enum_value_0000001 "OP_NOP"
+ attribute \enum_value_0000010 "OP_ADD"
+ attribute \enum_value_0000011 "OP_ADDPCIS"
+ attribute \enum_value_0000100 "OP_AND"
+ attribute \enum_value_0000101 "OP_ATTN"
+ attribute \enum_value_0000110 "OP_B"
+ attribute \enum_value_0000111 "OP_BC"
+ attribute \enum_value_0001000 "OP_BCREG"
+ attribute \enum_value_0001001 "OP_BPERM"
+ attribute \enum_value_0001010 "OP_CMP"
+ attribute \enum_value_0001011 "OP_CMPB"
+ attribute \enum_value_0001100 "OP_CMPEQB"
+ attribute \enum_value_0001101 "OP_CMPRB"
+ attribute \enum_value_0001110 "OP_CNTZ"
+ attribute \enum_value_0001111 "OP_CRAND"
+ attribute \enum_value_0010000 "OP_CRANDC"
+ attribute \enum_value_0010001 "OP_CREQV"
+ attribute \enum_value_0010010 "OP_CRNAND"
+ attribute \enum_value_0010011 "OP_CRNOR"
+ attribute \enum_value_0010100 "OP_CROR"
+ attribute \enum_value_0010101 "OP_CRORC"
+ attribute \enum_value_0010110 "OP_CRXOR"
+ attribute \enum_value_0010111 "OP_DARN"
+ attribute \enum_value_0011000 "OP_DCBF"
+ attribute \enum_value_0011001 "OP_DCBST"
+ attribute \enum_value_0011010 "OP_DCBT"
+ attribute \enum_value_0011011 "OP_DCBTST"
+ attribute \enum_value_0011100 "OP_DCBZ"
+ attribute \enum_value_0011101 "OP_DIV"
+ attribute \enum_value_0011110 "OP_DIVE"
+ attribute \enum_value_0011111 "OP_EXTS"
+ attribute \enum_value_0100000 "OP_EXTSWSLI"
+ attribute \enum_value_0100001 "OP_ICBI"
+ attribute \enum_value_0100010 "OP_ICBT"
+ attribute \enum_value_0100011 "OP_ISEL"
+ attribute \enum_value_0100100 "OP_ISYNC"
+ attribute \enum_value_0100101 "OP_LOAD"
+ attribute \enum_value_0100110 "OP_STORE"
+ attribute \enum_value_0100111 "OP_MADDHD"
+ attribute \enum_value_0101000 "OP_MADDHDU"
+ attribute \enum_value_0101001 "OP_MADDLD"
+ attribute \enum_value_0101010 "OP_MCRF"
+ attribute \enum_value_0101011 "OP_MCRXR"
+ attribute \enum_value_0101100 "OP_MCRXRX"
+ attribute \enum_value_0101101 "OP_MFCR"
+ attribute \enum_value_0101110 "OP_MFSPR"
+ attribute \enum_value_0101111 "OP_MOD"
+ attribute \enum_value_0110000 "OP_MTCRF"
+ attribute \enum_value_0110001 "OP_MTSPR"
+ attribute \enum_value_0110010 "OP_MUL_L64"
+ attribute \enum_value_0110011 "OP_MUL_H64"
+ attribute \enum_value_0110100 "OP_MUL_H32"
+ attribute \enum_value_0110101 "OP_OR"
+ attribute \enum_value_0110110 "OP_POPCNT"
+ attribute \enum_value_0110111 "OP_PRTY"
+ attribute \enum_value_0111000 "OP_RLC"
+ attribute \enum_value_0111001 "OP_RLCL"
+ attribute \enum_value_0111010 "OP_RLCR"
+ attribute \enum_value_0111011 "OP_SETB"
+ attribute \enum_value_0111100 "OP_SHL"
+ attribute \enum_value_0111101 "OP_SHR"
+ attribute \enum_value_0111110 "OP_SYNC"
+ attribute \enum_value_0111111 "OP_TRAP"
+ attribute \enum_value_1000011 "OP_XOR"
+ attribute \enum_value_1000100 "OP_SIM_CONFIG"
+ attribute \enum_value_1000101 "OP_CROP"
+ attribute \enum_value_1000110 "OP_RFID"
+ attribute \enum_value_1000111 "OP_MFMSR"
+ attribute \enum_value_1001000 "OP_MTMSRD"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 7 input 5 \op__insn_type
+ attribute \enum_base_type "Function"
+ attribute \enum_value_00000000000 "NONE"
+ attribute \enum_value_00000000010 "ALU"
+ attribute \enum_value_00000000100 "LDST"
+ attribute \enum_value_00000001000 "SHIFT_ROT"
+ attribute \enum_value_00000010000 "LOGICAL"
+ attribute \enum_value_00000100000 "BRANCH"
+ attribute \enum_value_00001000000 "CR"
+ attribute \enum_value_00010000000 "TRAP"
+ attribute \enum_value_00100000000 "MUL"
+ attribute \enum_value_01000000000 "DIV"
+ attribute \enum_value_10000000000 "SPR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 11 input 6 \op__fn_unit
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 input 7 \op__imm_data__imm
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 8 \op__imm_data__imm_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 9 \op__rc__rc
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 10 \op__rc__rc_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 11 \op__oe__oe
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 12 \op__oe__oe_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 13 \op__invert_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 14 \op__zero_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 15 \op__invert_out
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 16 \op__write_cr0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 17 \op__is_32bit
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 18 \op__is_signed
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 input 19 \op__insn
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 129 input 20 \o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 1 input 21 \xer_so
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23"
+ wire width 1 input 22 \neg_res
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24"
+ wire width 1 input 23 \neg_res32
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
+ wire width 1 output 24 \n_valid_o
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
+ wire width 1 input 25 \n_ready_i
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+ wire width 2 output 26 \muxid$1
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+ wire width 2 \muxid$1$next
+ attribute \enum_base_type "MicrOp"
+ attribute \enum_value_0000000 "OP_ILLEGAL"
+ attribute \enum_value_0000001 "OP_NOP"
+ attribute \enum_value_0000010 "OP_ADD"
+ attribute \enum_value_0000011 "OP_ADDPCIS"
+ attribute \enum_value_0000100 "OP_AND"
+ attribute \enum_value_0000101 "OP_ATTN"
+ attribute \enum_value_0000110 "OP_B"
+ attribute \enum_value_0000111 "OP_BC"
+ attribute \enum_value_0001000 "OP_BCREG"
+ attribute \enum_value_0001001 "OP_BPERM"
+ attribute \enum_value_0001010 "OP_CMP"
+ attribute \enum_value_0001011 "OP_CMPB"
+ attribute \enum_value_0001100 "OP_CMPEQB"
+ attribute \enum_value_0001101 "OP_CMPRB"
+ attribute \enum_value_0001110 "OP_CNTZ"
+ attribute \enum_value_0001111 "OP_CRAND"
+ attribute \enum_value_0010000 "OP_CRANDC"
+ attribute \enum_value_0010001 "OP_CREQV"
+ attribute \enum_value_0010010 "OP_CRNAND"
+ attribute \enum_value_0010011 "OP_CRNOR"
+ attribute \enum_value_0010100 "OP_CROR"
+ attribute \enum_value_0010101 "OP_CRORC"
+ attribute \enum_value_0010110 "OP_CRXOR"
+ attribute \enum_value_0010111 "OP_DARN"
+ attribute \enum_value_0011000 "OP_DCBF"
+ attribute \enum_value_0011001 "OP_DCBST"
+ attribute \enum_value_0011010 "OP_DCBT"
+ attribute \enum_value_0011011 "OP_DCBTST"
+ attribute \enum_value_0011100 "OP_DCBZ"
+ attribute \enum_value_0011101 "OP_DIV"
+ attribute \enum_value_0011110 "OP_DIVE"
+ attribute \enum_value_0011111 "OP_EXTS"
+ attribute \enum_value_0100000 "OP_EXTSWSLI"
+ attribute \enum_value_0100001 "OP_ICBI"
+ attribute \enum_value_0100010 "OP_ICBT"
+ attribute \enum_value_0100011 "OP_ISEL"
+ attribute \enum_value_0100100 "OP_ISYNC"
+ attribute \enum_value_0100101 "OP_LOAD"
+ attribute \enum_value_0100110 "OP_STORE"
+ attribute \enum_value_0100111 "OP_MADDHD"
+ attribute \enum_value_0101000 "OP_MADDHDU"
+ attribute \enum_value_0101001 "OP_MADDLD"
+ attribute \enum_value_0101010 "OP_MCRF"
+ attribute \enum_value_0101011 "OP_MCRXR"
+ attribute \enum_value_0101100 "OP_MCRXRX"
+ attribute \enum_value_0101101 "OP_MFCR"
+ attribute \enum_value_0101110 "OP_MFSPR"
+ attribute \enum_value_0101111 "OP_MOD"
+ attribute \enum_value_0110000 "OP_MTCRF"
+ attribute \enum_value_0110001 "OP_MTSPR"
+ attribute \enum_value_0110010 "OP_MUL_L64"
+ attribute \enum_value_0110011 "OP_MUL_H64"
+ attribute \enum_value_0110100 "OP_MUL_H32"
+ attribute \enum_value_0110101 "OP_OR"
+ attribute \enum_value_0110110 "OP_POPCNT"
+ attribute \enum_value_0110111 "OP_PRTY"
+ attribute \enum_value_0111000 "OP_RLC"
+ attribute \enum_value_0111001 "OP_RLCL"
+ attribute \enum_value_0111010 "OP_RLCR"
+ attribute \enum_value_0111011 "OP_SETB"
+ attribute \enum_value_0111100 "OP_SHL"
+ attribute \enum_value_0111101 "OP_SHR"
+ attribute \enum_value_0111110 "OP_SYNC"
+ attribute \enum_value_0111111 "OP_TRAP"
+ attribute \enum_value_1000011 "OP_XOR"
+ attribute \enum_value_1000100 "OP_SIM_CONFIG"
+ attribute \enum_value_1000101 "OP_CROP"
+ attribute \enum_value_1000110 "OP_RFID"
+ attribute \enum_value_1000111 "OP_MFMSR"
+ attribute \enum_value_1001000 "OP_MTMSRD"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 7 output 27 \op__insn_type$2
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 7 \op__insn_type$2$next
+ attribute \enum_base_type "Function"
+ attribute \enum_value_00000000000 "NONE"
+ attribute \enum_value_00000000010 "ALU"
+ attribute \enum_value_00000000100 "LDST"
+ attribute \enum_value_00000001000 "SHIFT_ROT"
+ attribute \enum_value_00000010000 "LOGICAL"
+ attribute \enum_value_00000100000 "BRANCH"
+ attribute \enum_value_00001000000 "CR"
+ attribute \enum_value_00010000000 "TRAP"
+ attribute \enum_value_00100000000 "MUL"
+ attribute \enum_value_01000000000 "DIV"
+ attribute \enum_value_10000000000 "SPR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 11 output 28 \op__fn_unit$3
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 11 \op__fn_unit$3$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 output 29 \op__imm_data__imm$4
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 \op__imm_data__imm$4$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 30 \op__imm_data__imm_ok$5
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__imm_data__imm_ok$5$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 31 \op__rc__rc$6
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__rc__rc$6$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 32 \op__rc__rc_ok$7
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__rc__rc_ok$7$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 33 \op__oe__oe$8
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__oe__oe$8$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 34 \op__oe__oe_ok$9
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__oe__oe_ok$9$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 35 \op__invert_a$10
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__invert_a$10$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 36 \op__zero_a$11
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__zero_a$11$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 37 \op__invert_out$12
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__invert_out$12$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 38 \op__write_cr0$13
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__write_cr0$13$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 39 \op__is_32bit$14
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__is_32bit$14$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 40 \op__is_signed$15
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__is_signed$15$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 output 41 \op__insn$16
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 \op__insn$16$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 64 output 42 \o$17
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 64 \o$17$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 43 \o_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 \o_ok$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 4 output 44 \cr_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 4 \cr_a$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 45 \cr_a_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 \cr_a_ok$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 2 output 46 \xer_ov
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 2 \xer_ov$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 47 \xer_ov_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 \xer_ov_ok$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 48 \xer_so$18
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 \xer_so$18$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 49 \xer_so_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 \xer_so_ok$next
+ cell \p$77 \p
+ connect \p_valid_i \p_valid_i
+ connect \p_ready_o \p_ready_o
+ end
+ cell \n$78 \n
+ connect \n_valid_o \n_valid_o
+ connect \n_ready_i \n_ready_i
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+ wire width 2 \mul3_muxid
+ attribute \enum_base_type "MicrOp"
+ attribute \enum_value_0000000 "OP_ILLEGAL"
+ attribute \enum_value_0000001 "OP_NOP"
+ attribute \enum_value_0000010 "OP_ADD"
+ attribute \enum_value_0000011 "OP_ADDPCIS"
+ attribute \enum_value_0000100 "OP_AND"
+ attribute \enum_value_0000101 "OP_ATTN"
+ attribute \enum_value_0000110 "OP_B"
+ attribute \enum_value_0000111 "OP_BC"
+ attribute \enum_value_0001000 "OP_BCREG"
+ attribute \enum_value_0001001 "OP_BPERM"
+ attribute \enum_value_0001010 "OP_CMP"
+ attribute \enum_value_0001011 "OP_CMPB"
+ attribute \enum_value_0001100 "OP_CMPEQB"
+ attribute \enum_value_0001101 "OP_CMPRB"
+ attribute \enum_value_0001110 "OP_CNTZ"
+ attribute \enum_value_0001111 "OP_CRAND"
+ attribute \enum_value_0010000 "OP_CRANDC"
+ attribute \enum_value_0010001 "OP_CREQV"
+ attribute \enum_value_0010010 "OP_CRNAND"
+ attribute \enum_value_0010011 "OP_CRNOR"
+ attribute \enum_value_0010100 "OP_CROR"
+ attribute \enum_value_0010101 "OP_CRORC"
+ attribute \enum_value_0010110 "OP_CRXOR"
+ attribute \enum_value_0010111 "OP_DARN"
+ attribute \enum_value_0011000 "OP_DCBF"
+ attribute \enum_value_0011001 "OP_DCBST"
+ attribute \enum_value_0011010 "OP_DCBT"
+ attribute \enum_value_0011011 "OP_DCBTST"
+ attribute \enum_value_0011100 "OP_DCBZ"
+ attribute \enum_value_0011101 "OP_DIV"
+ attribute \enum_value_0011110 "OP_DIVE"
+ attribute \enum_value_0011111 "OP_EXTS"
+ attribute \enum_value_0100000 "OP_EXTSWSLI"
+ attribute \enum_value_0100001 "OP_ICBI"
+ attribute \enum_value_0100010 "OP_ICBT"
+ attribute \enum_value_0100011 "OP_ISEL"
+ attribute \enum_value_0100100 "OP_ISYNC"
+ attribute \enum_value_0100101 "OP_LOAD"
+ attribute \enum_value_0100110 "OP_STORE"
+ attribute \enum_value_0100111 "OP_MADDHD"
+ attribute \enum_value_0101000 "OP_MADDHDU"
+ attribute \enum_value_0101001 "OP_MADDLD"
+ attribute \enum_value_0101010 "OP_MCRF"
+ attribute \enum_value_0101011 "OP_MCRXR"
+ attribute \enum_value_0101100 "OP_MCRXRX"
+ attribute \enum_value_0101101 "OP_MFCR"
+ attribute \enum_value_0101110 "OP_MFSPR"
+ attribute \enum_value_0101111 "OP_MOD"
+ attribute \enum_value_0110000 "OP_MTCRF"
+ attribute \enum_value_0110001 "OP_MTSPR"
+ attribute \enum_value_0110010 "OP_MUL_L64"
+ attribute \enum_value_0110011 "OP_MUL_H64"
+ attribute \enum_value_0110100 "OP_MUL_H32"
+ attribute \enum_value_0110101 "OP_OR"
+ attribute \enum_value_0110110 "OP_POPCNT"
+ attribute \enum_value_0110111 "OP_PRTY"
+ attribute \enum_value_0111000 "OP_RLC"
+ attribute \enum_value_0111001 "OP_RLCL"
+ attribute \enum_value_0111010 "OP_RLCR"
+ attribute \enum_value_0111011 "OP_SETB"
+ attribute \enum_value_0111100 "OP_SHL"
+ attribute \enum_value_0111101 "OP_SHR"
+ attribute \enum_value_0111110 "OP_SYNC"
+ attribute \enum_value_0111111 "OP_TRAP"
+ attribute \enum_value_1000011 "OP_XOR"
+ attribute \enum_value_1000100 "OP_SIM_CONFIG"
+ attribute \enum_value_1000101 "OP_CROP"
+ attribute \enum_value_1000110 "OP_RFID"
+ attribute \enum_value_1000111 "OP_MFMSR"
+ attribute \enum_value_1001000 "OP_MTMSRD"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 7 \mul3_op__insn_type
+ attribute \enum_base_type "Function"
+ attribute \enum_value_00000000000 "NONE"
+ attribute \enum_value_00000000010 "ALU"
+ attribute \enum_value_00000000100 "LDST"
+ attribute \enum_value_00000001000 "SHIFT_ROT"
+ attribute \enum_value_00000010000 "LOGICAL"
+ attribute \enum_value_00000100000 "BRANCH"
+ attribute \enum_value_00001000000 "CR"
+ attribute \enum_value_00010000000 "TRAP"
+ attribute \enum_value_00100000000 "MUL"
+ attribute \enum_value_01000000000 "DIV"
+ attribute \enum_value_10000000000 "SPR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 11 \mul3_op__fn_unit
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 \mul3_op__imm_data__imm
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \mul3_op__imm_data__imm_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \mul3_op__rc__rc
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \mul3_op__rc__rc_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \mul3_op__oe__oe
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \mul3_op__oe__oe_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \mul3_op__invert_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \mul3_op__zero_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \mul3_op__invert_out
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \mul3_op__write_cr0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \mul3_op__is_32bit
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \mul3_op__is_signed
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 \mul3_op__insn
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 129 \mul3_o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 1 \mul3_xer_so
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23"
+ wire width 1 \mul3_neg_res
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+ wire width 2 \mul3_muxid$19
+ attribute \enum_base_type "MicrOp"
+ attribute \enum_value_0000000 "OP_ILLEGAL"
+ attribute \enum_value_0000001 "OP_NOP"
+ attribute \enum_value_0000010 "OP_ADD"
+ attribute \enum_value_0000011 "OP_ADDPCIS"
+ attribute \enum_value_0000100 "OP_AND"
+ attribute \enum_value_0000101 "OP_ATTN"
+ attribute \enum_value_0000110 "OP_B"
+ attribute \enum_value_0000111 "OP_BC"
+ attribute \enum_value_0001000 "OP_BCREG"
+ attribute \enum_value_0001001 "OP_BPERM"
+ attribute \enum_value_0001010 "OP_CMP"
+ attribute \enum_value_0001011 "OP_CMPB"
+ attribute \enum_value_0001100 "OP_CMPEQB"
+ attribute \enum_value_0001101 "OP_CMPRB"
+ attribute \enum_value_0001110 "OP_CNTZ"
+ attribute \enum_value_0001111 "OP_CRAND"
+ attribute \enum_value_0010000 "OP_CRANDC"
+ attribute \enum_value_0010001 "OP_CREQV"
+ attribute \enum_value_0010010 "OP_CRNAND"
+ attribute \enum_value_0010011 "OP_CRNOR"
+ attribute \enum_value_0010100 "OP_CROR"
+ attribute \enum_value_0010101 "OP_CRORC"
+ attribute \enum_value_0010110 "OP_CRXOR"
+ attribute \enum_value_0010111 "OP_DARN"
+ attribute \enum_value_0011000 "OP_DCBF"
+ attribute \enum_value_0011001 "OP_DCBST"
+ attribute \enum_value_0011010 "OP_DCBT"
+ attribute \enum_value_0011011 "OP_DCBTST"
+ attribute \enum_value_0011100 "OP_DCBZ"
+ attribute \enum_value_0011101 "OP_DIV"
+ attribute \enum_value_0011110 "OP_DIVE"
+ attribute \enum_value_0011111 "OP_EXTS"
+ attribute \enum_value_0100000 "OP_EXTSWSLI"
+ attribute \enum_value_0100001 "OP_ICBI"
+ attribute \enum_value_0100010 "OP_ICBT"
+ attribute \enum_value_0100011 "OP_ISEL"
+ attribute \enum_value_0100100 "OP_ISYNC"
+ attribute \enum_value_0100101 "OP_LOAD"
+ attribute \enum_value_0100110 "OP_STORE"
+ attribute \enum_value_0100111 "OP_MADDHD"
+ attribute \enum_value_0101000 "OP_MADDHDU"
+ attribute \enum_value_0101001 "OP_MADDLD"
+ attribute \enum_value_0101010 "OP_MCRF"
+ attribute \enum_value_0101011 "OP_MCRXR"
+ attribute \enum_value_0101100 "OP_MCRXRX"
+ attribute \enum_value_0101101 "OP_MFCR"
+ attribute \enum_value_0101110 "OP_MFSPR"
+ attribute \enum_value_0101111 "OP_MOD"
+ attribute \enum_value_0110000 "OP_MTCRF"
+ attribute \enum_value_0110001 "OP_MTSPR"
+ attribute \enum_value_0110010 "OP_MUL_L64"
+ attribute \enum_value_0110011 "OP_MUL_H64"
+ attribute \enum_value_0110100 "OP_MUL_H32"
+ attribute \enum_value_0110101 "OP_OR"
+ attribute \enum_value_0110110 "OP_POPCNT"
+ attribute \enum_value_0110111 "OP_PRTY"
+ attribute \enum_value_0111000 "OP_RLC"
+ attribute \enum_value_0111001 "OP_RLCL"
+ attribute \enum_value_0111010 "OP_RLCR"
+ attribute \enum_value_0111011 "OP_SETB"
+ attribute \enum_value_0111100 "OP_SHL"
+ attribute \enum_value_0111101 "OP_SHR"
+ attribute \enum_value_0111110 "OP_SYNC"
+ attribute \enum_value_0111111 "OP_TRAP"
+ attribute \enum_value_1000011 "OP_XOR"
+ attribute \enum_value_1000100 "OP_SIM_CONFIG"
+ attribute \enum_value_1000101 "OP_CROP"
+ attribute \enum_value_1000110 "OP_RFID"
+ attribute \enum_value_1000111 "OP_MFMSR"
+ attribute \enum_value_1001000 "OP_MTMSRD"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 7 \mul3_op__insn_type$20
+ attribute \enum_base_type "Function"
+ attribute \enum_value_00000000000 "NONE"
+ attribute \enum_value_00000000010 "ALU"
+ attribute \enum_value_00000000100 "LDST"
+ attribute \enum_value_00000001000 "SHIFT_ROT"
+ attribute \enum_value_00000010000 "LOGICAL"
+ attribute \enum_value_00000100000 "BRANCH"
+ attribute \enum_value_00001000000 "CR"
+ attribute \enum_value_00010000000 "TRAP"
+ attribute \enum_value_00100000000 "MUL"
+ attribute \enum_value_01000000000 "DIV"
+ attribute \enum_value_10000000000 "SPR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 11 \mul3_op__fn_unit$21
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 \mul3_op__imm_data__imm$22
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \mul3_op__imm_data__imm_ok$23
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \mul3_op__rc__rc$24
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \mul3_op__rc__rc_ok$25
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \mul3_op__oe__oe$26
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \mul3_op__oe__oe_ok$27
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \mul3_op__invert_a$28
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \mul3_op__zero_a$29
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \mul3_op__invert_out$30
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \mul3_op__write_cr0$31
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \mul3_op__is_32bit$32
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \mul3_op__is_signed$33
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 \mul3_op__insn$34
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 64 \mul3_o$35
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 \mul3_o_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 2 \mul3_xer_ov
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 \mul3_xer_ov_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 \mul3_xer_so$36
+ cell \mul3 \mul3
+ connect \muxid \mul3_muxid
+ connect \op__insn_type \mul3_op__insn_type
+ connect \op__fn_unit \mul3_op__fn_unit
+ connect \op__imm_data__imm \mul3_op__imm_data__imm
+ connect \op__imm_data__imm_ok \mul3_op__imm_data__imm_ok
+ connect \op__rc__rc \mul3_op__rc__rc
+ connect \op__rc__rc_ok \mul3_op__rc__rc_ok
+ connect \op__oe__oe \mul3_op__oe__oe
+ connect \op__oe__oe_ok \mul3_op__oe__oe_ok
+ connect \op__invert_a \mul3_op__invert_a
+ connect \op__zero_a \mul3_op__zero_a
+ connect \op__invert_out \mul3_op__invert_out
+ connect \op__write_cr0 \mul3_op__write_cr0
+ connect \op__is_32bit \mul3_op__is_32bit
+ connect \op__is_signed \mul3_op__is_signed
+ connect \op__insn \mul3_op__insn
+ connect \o \mul3_o
+ connect \xer_so \mul3_xer_so
+ connect \neg_res \mul3_neg_res
+ connect \muxid$1 \mul3_muxid$19
+ connect \op__insn_type$2 \mul3_op__insn_type$20
+ connect \op__fn_unit$3 \mul3_op__fn_unit$21
+ connect \op__imm_data__imm$4 \mul3_op__imm_data__imm$22
+ connect \op__imm_data__imm_ok$5 \mul3_op__imm_data__imm_ok$23
+ connect \op__rc__rc$6 \mul3_op__rc__rc$24
+ connect \op__rc__rc_ok$7 \mul3_op__rc__rc_ok$25
+ connect \op__oe__oe$8 \mul3_op__oe__oe$26
+ connect \op__oe__oe_ok$9 \mul3_op__oe__oe_ok$27
+ connect \op__invert_a$10 \mul3_op__invert_a$28
+ connect \op__zero_a$11 \mul3_op__zero_a$29
+ connect \op__invert_out$12 \mul3_op__invert_out$30
+ connect \op__write_cr0$13 \mul3_op__write_cr0$31
+ connect \op__is_32bit$14 \mul3_op__is_32bit$32
+ connect \op__is_signed$15 \mul3_op__is_signed$33
+ connect \op__insn$16 \mul3_op__insn$34
+ connect \o$17 \mul3_o$35
+ connect \o_ok \mul3_o_ok
+ connect \xer_ov \mul3_xer_ov
+ connect \xer_ov_ok \mul3_xer_ov_ok
+ connect \xer_so$18 \mul3_xer_so$36
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+ wire width 2 \output_muxid
+ attribute \enum_base_type "MicrOp"
+ attribute \enum_value_0000000 "OP_ILLEGAL"
+ attribute \enum_value_0000001 "OP_NOP"
+ attribute \enum_value_0000010 "OP_ADD"
+ attribute \enum_value_0000011 "OP_ADDPCIS"
+ attribute \enum_value_0000100 "OP_AND"
+ attribute \enum_value_0000101 "OP_ATTN"
+ attribute \enum_value_0000110 "OP_B"
+ attribute \enum_value_0000111 "OP_BC"
+ attribute \enum_value_0001000 "OP_BCREG"
+ attribute \enum_value_0001001 "OP_BPERM"
+ attribute \enum_value_0001010 "OP_CMP"
+ attribute \enum_value_0001011 "OP_CMPB"
+ attribute \enum_value_0001100 "OP_CMPEQB"
+ attribute \enum_value_0001101 "OP_CMPRB"
+ attribute \enum_value_0001110 "OP_CNTZ"
+ attribute \enum_value_0001111 "OP_CRAND"
+ attribute \enum_value_0010000 "OP_CRANDC"
+ attribute \enum_value_0010001 "OP_CREQV"
+ attribute \enum_value_0010010 "OP_CRNAND"
+ attribute \enum_value_0010011 "OP_CRNOR"
+ attribute \enum_value_0010100 "OP_CROR"
+ attribute \enum_value_0010101 "OP_CRORC"
+ attribute \enum_value_0010110 "OP_CRXOR"
+ attribute \enum_value_0010111 "OP_DARN"
+ attribute \enum_value_0011000 "OP_DCBF"
+ attribute \enum_value_0011001 "OP_DCBST"
+ attribute \enum_value_0011010 "OP_DCBT"
+ attribute \enum_value_0011011 "OP_DCBTST"
+ attribute \enum_value_0011100 "OP_DCBZ"
+ attribute \enum_value_0011101 "OP_DIV"
+ attribute \enum_value_0011110 "OP_DIVE"
+ attribute \enum_value_0011111 "OP_EXTS"
+ attribute \enum_value_0100000 "OP_EXTSWSLI"
+ attribute \enum_value_0100001 "OP_ICBI"
+ attribute \enum_value_0100010 "OP_ICBT"
+ attribute \enum_value_0100011 "OP_ISEL"
+ attribute \enum_value_0100100 "OP_ISYNC"
+ attribute \enum_value_0100101 "OP_LOAD"
+ attribute \enum_value_0100110 "OP_STORE"
+ attribute \enum_value_0100111 "OP_MADDHD"
+ attribute \enum_value_0101000 "OP_MADDHDU"
+ attribute \enum_value_0101001 "OP_MADDLD"
+ attribute \enum_value_0101010 "OP_MCRF"
+ attribute \enum_value_0101011 "OP_MCRXR"
+ attribute \enum_value_0101100 "OP_MCRXRX"
+ attribute \enum_value_0101101 "OP_MFCR"
+ attribute \enum_value_0101110 "OP_MFSPR"
+ attribute \enum_value_0101111 "OP_MOD"
+ attribute \enum_value_0110000 "OP_MTCRF"
+ attribute \enum_value_0110001 "OP_MTSPR"
+ attribute \enum_value_0110010 "OP_MUL_L64"
+ attribute \enum_value_0110011 "OP_MUL_H64"
+ attribute \enum_value_0110100 "OP_MUL_H32"
+ attribute \enum_value_0110101 "OP_OR"
+ attribute \enum_value_0110110 "OP_POPCNT"
+ attribute \enum_value_0110111 "OP_PRTY"
+ attribute \enum_value_0111000 "OP_RLC"
+ attribute \enum_value_0111001 "OP_RLCL"
+ attribute \enum_value_0111010 "OP_RLCR"
+ attribute \enum_value_0111011 "OP_SETB"
+ attribute \enum_value_0111100 "OP_SHL"
+ attribute \enum_value_0111101 "OP_SHR"
+ attribute \enum_value_0111110 "OP_SYNC"
+ attribute \enum_value_0111111 "OP_TRAP"
+ attribute \enum_value_1000011 "OP_XOR"
+ attribute \enum_value_1000100 "OP_SIM_CONFIG"
+ attribute \enum_value_1000101 "OP_CROP"
+ attribute \enum_value_1000110 "OP_RFID"
+ attribute \enum_value_1000111 "OP_MFMSR"
+ attribute \enum_value_1001000 "OP_MTMSRD"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 7 \output_op__insn_type
+ attribute \enum_base_type "Function"
+ attribute \enum_value_00000000000 "NONE"
+ attribute \enum_value_00000000010 "ALU"
+ attribute \enum_value_00000000100 "LDST"
+ attribute \enum_value_00000001000 "SHIFT_ROT"
+ attribute \enum_value_00000010000 "LOGICAL"
+ attribute \enum_value_00000100000 "BRANCH"
+ attribute \enum_value_00001000000 "CR"
+ attribute \enum_value_00010000000 "TRAP"
+ attribute \enum_value_00100000000 "MUL"
+ attribute \enum_value_01000000000 "DIV"
+ attribute \enum_value_10000000000 "SPR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 11 \output_op__fn_unit
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 \output_op__imm_data__imm
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \output_op__imm_data__imm_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \output_op__rc__rc
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \output_op__rc__rc_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \output_op__oe__oe
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \output_op__oe__oe_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \output_op__invert_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \output_op__zero_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \output_op__invert_out
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \output_op__write_cr0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \output_op__is_32bit
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \output_op__is_signed
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 \output_op__insn
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 64 \output_o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 \output_o_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 4 \output_cr_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 2 \output_xer_ov
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 \output_xer_so
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+ wire width 2 \output_muxid$37
+ attribute \enum_base_type "MicrOp"
+ attribute \enum_value_0000000 "OP_ILLEGAL"
+ attribute \enum_value_0000001 "OP_NOP"
+ attribute \enum_value_0000010 "OP_ADD"
+ attribute \enum_value_0000011 "OP_ADDPCIS"
+ attribute \enum_value_0000100 "OP_AND"
+ attribute \enum_value_0000101 "OP_ATTN"
+ attribute \enum_value_0000110 "OP_B"
+ attribute \enum_value_0000111 "OP_BC"
+ attribute \enum_value_0001000 "OP_BCREG"
+ attribute \enum_value_0001001 "OP_BPERM"
+ attribute \enum_value_0001010 "OP_CMP"
+ attribute \enum_value_0001011 "OP_CMPB"
+ attribute \enum_value_0001100 "OP_CMPEQB"
+ attribute \enum_value_0001101 "OP_CMPRB"
+ attribute \enum_value_0001110 "OP_CNTZ"
+ attribute \enum_value_0001111 "OP_CRAND"
+ attribute \enum_value_0010000 "OP_CRANDC"
+ attribute \enum_value_0010001 "OP_CREQV"
+ attribute \enum_value_0010010 "OP_CRNAND"
+ attribute \enum_value_0010011 "OP_CRNOR"
+ attribute \enum_value_0010100 "OP_CROR"
+ attribute \enum_value_0010101 "OP_CRORC"
+ attribute \enum_value_0010110 "OP_CRXOR"
+ attribute \enum_value_0010111 "OP_DARN"
+ attribute \enum_value_0011000 "OP_DCBF"
+ attribute \enum_value_0011001 "OP_DCBST"
+ attribute \enum_value_0011010 "OP_DCBT"
+ attribute \enum_value_0011011 "OP_DCBTST"
+ attribute \enum_value_0011100 "OP_DCBZ"
+ attribute \enum_value_0011101 "OP_DIV"
+ attribute \enum_value_0011110 "OP_DIVE"
+ attribute \enum_value_0011111 "OP_EXTS"
+ attribute \enum_value_0100000 "OP_EXTSWSLI"
+ attribute \enum_value_0100001 "OP_ICBI"
+ attribute \enum_value_0100010 "OP_ICBT"
+ attribute \enum_value_0100011 "OP_ISEL"
+ attribute \enum_value_0100100 "OP_ISYNC"
+ attribute \enum_value_0100101 "OP_LOAD"
+ attribute \enum_value_0100110 "OP_STORE"
+ attribute \enum_value_0100111 "OP_MADDHD"
+ attribute \enum_value_0101000 "OP_MADDHDU"
+ attribute \enum_value_0101001 "OP_MADDLD"
+ attribute \enum_value_0101010 "OP_MCRF"
+ attribute \enum_value_0101011 "OP_MCRXR"
+ attribute \enum_value_0101100 "OP_MCRXRX"
+ attribute \enum_value_0101101 "OP_MFCR"
+ attribute \enum_value_0101110 "OP_MFSPR"
+ attribute \enum_value_0101111 "OP_MOD"
+ attribute \enum_value_0110000 "OP_MTCRF"
+ attribute \enum_value_0110001 "OP_MTSPR"
+ attribute \enum_value_0110010 "OP_MUL_L64"
+ attribute \enum_value_0110011 "OP_MUL_H64"
+ attribute \enum_value_0110100 "OP_MUL_H32"
+ attribute \enum_value_0110101 "OP_OR"
+ attribute \enum_value_0110110 "OP_POPCNT"
+ attribute \enum_value_0110111 "OP_PRTY"
+ attribute \enum_value_0111000 "OP_RLC"
+ attribute \enum_value_0111001 "OP_RLCL"
+ attribute \enum_value_0111010 "OP_RLCR"
+ attribute \enum_value_0111011 "OP_SETB"
+ attribute \enum_value_0111100 "OP_SHL"
+ attribute \enum_value_0111101 "OP_SHR"
+ attribute \enum_value_0111110 "OP_SYNC"
+ attribute \enum_value_0111111 "OP_TRAP"
+ attribute \enum_value_1000011 "OP_XOR"
+ attribute \enum_value_1000100 "OP_SIM_CONFIG"
+ attribute \enum_value_1000101 "OP_CROP"
+ attribute \enum_value_1000110 "OP_RFID"
+ attribute \enum_value_1000111 "OP_MFMSR"
+ attribute \enum_value_1001000 "OP_MTMSRD"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 7 \output_op__insn_type$38
+ attribute \enum_base_type "Function"
+ attribute \enum_value_00000000000 "NONE"
+ attribute \enum_value_00000000010 "ALU"
+ attribute \enum_value_00000000100 "LDST"
+ attribute \enum_value_00000001000 "SHIFT_ROT"
+ attribute \enum_value_00000010000 "LOGICAL"
+ attribute \enum_value_00000100000 "BRANCH"
+ attribute \enum_value_00001000000 "CR"
+ attribute \enum_value_00010000000 "TRAP"
+ attribute \enum_value_00100000000 "MUL"
+ attribute \enum_value_01000000000 "DIV"
+ attribute \enum_value_10000000000 "SPR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 11 \output_op__fn_unit$39
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 \output_op__imm_data__imm$40
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \output_op__imm_data__imm_ok$41
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \output_op__rc__rc$42
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \output_op__rc__rc_ok$43
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \output_op__oe__oe$44
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \output_op__oe__oe_ok$45
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \output_op__invert_a$46
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \output_op__zero_a$47
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \output_op__invert_out$48
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \output_op__write_cr0$49
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \output_op__is_32bit$50
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \output_op__is_signed$51
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 \output_op__insn$52
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 64 \output_o$53
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 \output_o_ok$54
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 4 \output_cr_a$55
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 \output_cr_a_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 2 \output_xer_ov$56
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 \output_xer_ov_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 \output_xer_so$57
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 \output_xer_so_ok
+ cell \output$79 \output
+ connect \muxid \output_muxid
+ connect \op__insn_type \output_op__insn_type
+ connect \op__fn_unit \output_op__fn_unit
+ connect \op__imm_data__imm \output_op__imm_data__imm
+ connect \op__imm_data__imm_ok \output_op__imm_data__imm_ok
+ connect \op__rc__rc \output_op__rc__rc
+ connect \op__rc__rc_ok \output_op__rc__rc_ok
+ connect \op__oe__oe \output_op__oe__oe
+ connect \op__oe__oe_ok \output_op__oe__oe_ok
+ connect \op__invert_a \output_op__invert_a
+ connect \op__zero_a \output_op__zero_a
+ connect \op__invert_out \output_op__invert_out
+ connect \op__write_cr0 \output_op__write_cr0
+ connect \op__is_32bit \output_op__is_32bit
+ connect \op__is_signed \output_op__is_signed
+ connect \op__insn \output_op__insn
+ connect \o \output_o
+ connect \o_ok \output_o_ok
+ connect \cr_a \output_cr_a
+ connect \xer_ov \output_xer_ov
+ connect \xer_so \output_xer_so
+ connect \muxid$1 \output_muxid$37
+ connect \op__insn_type$2 \output_op__insn_type$38
+ connect \op__fn_unit$3 \output_op__fn_unit$39
+ connect \op__imm_data__imm$4 \output_op__imm_data__imm$40
+ connect \op__imm_data__imm_ok$5 \output_op__imm_data__imm_ok$41
+ connect \op__rc__rc$6 \output_op__rc__rc$42
+ connect \op__rc__rc_ok$7 \output_op__rc__rc_ok$43
+ connect \op__oe__oe$8 \output_op__oe__oe$44
+ connect \op__oe__oe_ok$9 \output_op__oe__oe_ok$45
+ connect \op__invert_a$10 \output_op__invert_a$46
+ connect \op__zero_a$11 \output_op__zero_a$47
+ connect \op__invert_out$12 \output_op__invert_out$48
+ connect \op__write_cr0$13 \output_op__write_cr0$49
+ connect \op__is_32bit$14 \output_op__is_32bit$50
+ connect \op__is_signed$15 \output_op__is_signed$51
+ connect \op__insn$16 \output_op__insn$52
+ connect \o$17 \output_o$53
+ connect \o_ok$18 \output_o_ok$54
+ connect \cr_a$19 \output_cr_a$55
+ connect \cr_a_ok \output_cr_a_ok
+ connect \xer_ov$20 \output_xer_ov$56
+ connect \xer_ov_ok \output_xer_ov_ok
+ connect \xer_so$21 \output_xer_so$57
+ connect \xer_so_ok \output_xer_so_ok
+ end
+ process $group_0
+ assign \mul3_muxid 2'00
+ assign \mul3_muxid \muxid
+ sync init
+ end
+ process $group_1
+ assign \mul3_op__insn_type 7'0000000
+ assign \mul3_op__fn_unit 11'00000000000
+ assign \mul3_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \mul3_op__imm_data__imm_ok 1'0
+ assign \mul3_op__rc__rc 1'0
+ assign \mul3_op__rc__rc_ok 1'0
+ assign \mul3_op__oe__oe 1'0
+ assign \mul3_op__oe__oe_ok 1'0
+ assign \mul3_op__invert_a 1'0
+ assign \mul3_op__zero_a 1'0
+ assign \mul3_op__invert_out 1'0
+ assign \mul3_op__write_cr0 1'0
+ assign \mul3_op__is_32bit 1'0
+ assign \mul3_op__is_signed 1'0
+ assign \mul3_op__insn 32'00000000000000000000000000000000
+ assign { \mul3_op__insn \mul3_op__is_signed \mul3_op__is_32bit \mul3_op__write_cr0 \mul3_op__invert_out \mul3_op__zero_a \mul3_op__invert_a { \mul3_op__oe__oe_ok \mul3_op__oe__oe } { \mul3_op__rc__rc_ok \mul3_op__rc__rc } { \mul3_op__imm_data__imm_ok \mul3_op__imm_data__imm } \mul3_op__fn_unit \mul3_op__insn_type } { \op__insn \op__is_signed \op__is_32bit \op__write_cr0 \op__invert_out \op__zero_a \op__invert_a { \op__oe__oe_ok \op__oe__oe } { \op__rc__rc_ok \op__rc__rc } { \op__imm_data__imm_ok \op__imm_data__imm } \op__fn_unit \op__insn_type }
+ sync init
+ end
+ process $group_16
+ assign \mul3_o 129'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
+ assign \mul3_o \o
+ sync init
+ end
+ process $group_17
+ assign \mul3_xer_so 1'0
+ assign \mul3_xer_so \xer_so
+ sync init
+ end
+ process $group_18
+ assign \mul3_neg_res 1'0
+ assign \mul3_neg_res \neg_res
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24"
+ wire width 1 \neg_res32$58
+ process $group_19
+ assign \neg_res32$58 1'0
+ assign \neg_res32$58 \neg_res32
+ sync init
+ end
+ process $group_20
+ assign \output_muxid 2'00
+ assign \output_muxid \mul3_muxid$19
+ sync init
+ end
+ process $group_21
+ assign \output_op__insn_type 7'0000000
+ assign \output_op__fn_unit 11'00000000000
+ assign \output_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \output_op__imm_data__imm_ok 1'0
+ assign \output_op__rc__rc 1'0
+ assign \output_op__rc__rc_ok 1'0
+ assign \output_op__oe__oe 1'0
+ assign \output_op__oe__oe_ok 1'0
+ assign \output_op__invert_a 1'0
+ assign \output_op__zero_a 1'0
+ assign \output_op__invert_out 1'0
+ assign \output_op__write_cr0 1'0
+ assign \output_op__is_32bit 1'0
+ assign \output_op__is_signed 1'0
+ assign \output_op__insn 32'00000000000000000000000000000000
+ assign { \output_op__insn \output_op__is_signed \output_op__is_32bit \output_op__write_cr0 \output_op__invert_out \output_op__zero_a \output_op__invert_a { \output_op__oe__oe_ok \output_op__oe__oe } { \output_op__rc__rc_ok \output_op__rc__rc } { \output_op__imm_data__imm_ok \output_op__imm_data__imm } \output_op__fn_unit \output_op__insn_type } { \mul3_op__insn$34 \mul3_op__is_signed$33 \mul3_op__is_32bit$32 \mul3_op__write_cr0$31 \mul3_op__invert_out$30 \mul3_op__zero_a$29 \mul3_op__invert_a$28 { \mul3_op__oe__oe_ok$27 \mul3_op__oe__oe$26 } { \mul3_op__rc__rc_ok$25 \mul3_op__rc__rc$24 } { \mul3_op__imm_data__imm_ok$23 \mul3_op__imm_data__imm$22 } \mul3_op__fn_unit$21 \mul3_op__insn_type$20 }
+ sync init
+ end
+ process $group_36
+ assign \output_o 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \output_o_ok 1'0
+ assign { \output_o_ok \output_o } { \mul3_o_ok \mul3_o$35 }
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 \cr_a_ok$59
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 4 \cr_a$60
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 \cr_a_ok$61
+ process $group_38
+ assign \output_cr_a 4'0000
+ assign \cr_a_ok$59 1'0
+ assign { \cr_a_ok$59 \output_cr_a } { \cr_a_ok$61 \cr_a$60 }
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 \xer_ov_ok$62
+ process $group_40
+ assign \output_xer_ov 2'00
+ assign \xer_ov_ok$62 1'0
+ assign { \xer_ov_ok$62 \output_xer_ov } { \mul3_xer_ov_ok \mul3_xer_ov }
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 \xer_so_ok$63
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 \xer_so_ok$64
+ process $group_42
+ assign \output_xer_so 1'0
+ assign \xer_so_ok$63 1'0
+ assign { \xer_so_ok$63 \output_xer_so } { \xer_so_ok$64 \mul3_xer_so$36 }
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621"
+ wire width 1 \p_valid_i$65
+ process $group_44
+ assign \p_valid_i$65 1'0
+ assign \p_valid_i$65 \p_valid_i
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619"
+ wire width 1 \n_i_rdy_data
+ process $group_45
+ assign \n_i_rdy_data 1'0
+ assign \n_i_rdy_data \n_ready_i
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620"
+ wire width 1 \p_valid_i_p_ready_o
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624"
+ wire width 1 $66
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624"
+ cell $and $67
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \p_valid_i$65
+ connect \B \p_ready_o
+ connect \Y $66
+ end
+ process $group_46
+ assign \p_valid_i_p_ready_o 1'0
+ assign \p_valid_i_p_ready_o $66
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+ wire width 2 \muxid$68
+ process $group_47
+ assign \muxid$68 2'00
+ assign \muxid$68 \output_muxid$37
+ sync init
+ end
+ attribute \enum_base_type "MicrOp"
+ attribute \enum_value_0000000 "OP_ILLEGAL"
+ attribute \enum_value_0000001 "OP_NOP"
+ attribute \enum_value_0000010 "OP_ADD"
+ attribute \enum_value_0000011 "OP_ADDPCIS"
+ attribute \enum_value_0000100 "OP_AND"
+ attribute \enum_value_0000101 "OP_ATTN"
+ attribute \enum_value_0000110 "OP_B"
+ attribute \enum_value_0000111 "OP_BC"
+ attribute \enum_value_0001000 "OP_BCREG"
+ attribute \enum_value_0001001 "OP_BPERM"
+ attribute \enum_value_0001010 "OP_CMP"
+ attribute \enum_value_0001011 "OP_CMPB"
+ attribute \enum_value_0001100 "OP_CMPEQB"
+ attribute \enum_value_0001101 "OP_CMPRB"
+ attribute \enum_value_0001110 "OP_CNTZ"
+ attribute \enum_value_0001111 "OP_CRAND"
+ attribute \enum_value_0010000 "OP_CRANDC"
+ attribute \enum_value_0010001 "OP_CREQV"
+ attribute \enum_value_0010010 "OP_CRNAND"
+ attribute \enum_value_0010011 "OP_CRNOR"
+ attribute \enum_value_0010100 "OP_CROR"
+ attribute \enum_value_0010101 "OP_CRORC"
+ attribute \enum_value_0010110 "OP_CRXOR"
+ attribute \enum_value_0010111 "OP_DARN"
+ attribute \enum_value_0011000 "OP_DCBF"
+ attribute \enum_value_0011001 "OP_DCBST"
+ attribute \enum_value_0011010 "OP_DCBT"
+ attribute \enum_value_0011011 "OP_DCBTST"
+ attribute \enum_value_0011100 "OP_DCBZ"
+ attribute \enum_value_0011101 "OP_DIV"
+ attribute \enum_value_0011110 "OP_DIVE"
+ attribute \enum_value_0011111 "OP_EXTS"
+ attribute \enum_value_0100000 "OP_EXTSWSLI"
+ attribute \enum_value_0100001 "OP_ICBI"
+ attribute \enum_value_0100010 "OP_ICBT"
+ attribute \enum_value_0100011 "OP_ISEL"
+ attribute \enum_value_0100100 "OP_ISYNC"
+ attribute \enum_value_0100101 "OP_LOAD"
+ attribute \enum_value_0100110 "OP_STORE"
+ attribute \enum_value_0100111 "OP_MADDHD"
+ attribute \enum_value_0101000 "OP_MADDHDU"
+ attribute \enum_value_0101001 "OP_MADDLD"
+ attribute \enum_value_0101010 "OP_MCRF"
+ attribute \enum_value_0101011 "OP_MCRXR"
+ attribute \enum_value_0101100 "OP_MCRXRX"
+ attribute \enum_value_0101101 "OP_MFCR"
+ attribute \enum_value_0101110 "OP_MFSPR"
+ attribute \enum_value_0101111 "OP_MOD"
+ attribute \enum_value_0110000 "OP_MTCRF"
+ attribute \enum_value_0110001 "OP_MTSPR"
+ attribute \enum_value_0110010 "OP_MUL_L64"
+ attribute \enum_value_0110011 "OP_MUL_H64"
+ attribute \enum_value_0110100 "OP_MUL_H32"
+ attribute \enum_value_0110101 "OP_OR"
+ attribute \enum_value_0110110 "OP_POPCNT"
+ attribute \enum_value_0110111 "OP_PRTY"
+ attribute \enum_value_0111000 "OP_RLC"
+ attribute \enum_value_0111001 "OP_RLCL"
+ attribute \enum_value_0111010 "OP_RLCR"
+ attribute \enum_value_0111011 "OP_SETB"
+ attribute \enum_value_0111100 "OP_SHL"
+ attribute \enum_value_0111101 "OP_SHR"
+ attribute \enum_value_0111110 "OP_SYNC"
+ attribute \enum_value_0111111 "OP_TRAP"
+ attribute \enum_value_1000011 "OP_XOR"
+ attribute \enum_value_1000100 "OP_SIM_CONFIG"
+ attribute \enum_value_1000101 "OP_CROP"
+ attribute \enum_value_1000110 "OP_RFID"
+ attribute \enum_value_1000111 "OP_MFMSR"
+ attribute \enum_value_1001000 "OP_MTMSRD"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 7 \op__insn_type$69
+ attribute \enum_base_type "Function"
+ attribute \enum_value_00000000000 "NONE"
+ attribute \enum_value_00000000010 "ALU"
+ attribute \enum_value_00000000100 "LDST"
+ attribute \enum_value_00000001000 "SHIFT_ROT"
+ attribute \enum_value_00000010000 "LOGICAL"
+ attribute \enum_value_00000100000 "BRANCH"
+ attribute \enum_value_00001000000 "CR"
+ attribute \enum_value_00010000000 "TRAP"
+ attribute \enum_value_00100000000 "MUL"
+ attribute \enum_value_01000000000 "DIV"
+ attribute \enum_value_10000000000 "SPR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 11 \op__fn_unit$70
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 \op__imm_data__imm$71
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__imm_data__imm_ok$72
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__rc__rc$73
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__rc__rc_ok$74
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__oe__oe$75
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__oe__oe_ok$76
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__invert_a$77
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__zero_a$78
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__invert_out$79
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__write_cr0$80
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__is_32bit$81
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__is_signed$82
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 \op__insn$83
+ process $group_48
+ assign \op__insn_type$69 7'0000000
+ assign \op__fn_unit$70 11'00000000000
+ assign \op__imm_data__imm$71 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \op__imm_data__imm_ok$72 1'0
+ assign \op__rc__rc$73 1'0
+ assign \op__rc__rc_ok$74 1'0
+ assign \op__oe__oe$75 1'0
+ assign \op__oe__oe_ok$76 1'0
+ assign \op__invert_a$77 1'0
+ assign \op__zero_a$78 1'0
+ assign \op__invert_out$79 1'0
+ assign \op__write_cr0$80 1'0
+ assign \op__is_32bit$81 1'0
+ assign \op__is_signed$82 1'0
+ assign \op__insn$83 32'00000000000000000000000000000000
+ assign { \op__insn$83 \op__is_signed$82 \op__is_32bit$81 \op__write_cr0$80 \op__invert_out$79 \op__zero_a$78 \op__invert_a$77 { \op__oe__oe_ok$76 \op__oe__oe$75 } { \op__rc__rc_ok$74 \op__rc__rc$73 } { \op__imm_data__imm_ok$72 \op__imm_data__imm$71 } \op__fn_unit$70 \op__insn_type$69 } { \output_op__insn$52 \output_op__is_signed$51 \output_op__is_32bit$50 \output_op__write_cr0$49 \output_op__invert_out$48 \output_op__zero_a$47 \output_op__invert_a$46 { \output_op__oe__oe_ok$45 \output_op__oe__oe$44 } { \output_op__rc__rc_ok$43 \output_op__rc__rc$42 } { \output_op__imm_data__imm_ok$41 \output_op__imm_data__imm$40 } \output_op__fn_unit$39 \output_op__insn_type$38 }
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 64 \o$84
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 \o_ok$85
+ process $group_63
+ assign \o$84 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \o_ok$85 1'0
+ assign { \o_ok$85 \o$84 } { \output_o_ok$54 \output_o$53 }
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 4 \cr_a$86
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 \cr_a_ok$87
+ process $group_65
+ assign \cr_a$86 4'0000
+ assign \cr_a_ok$87 1'0
+ assign { \cr_a_ok$87 \cr_a$86 } { \output_cr_a_ok \output_cr_a$55 }
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 2 \xer_ov$88
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 \xer_ov_ok$89
+ process $group_67
+ assign \xer_ov$88 2'00
+ assign \xer_ov_ok$89 1'0
+ assign { \xer_ov_ok$89 \xer_ov$88 } { \output_xer_ov_ok \output_xer_ov$56 }
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 \xer_so$90
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 \xer_so_ok$91
+ process $group_69
+ assign \xer_so$90 1'0
+ assign \xer_so_ok$91 1'0
+ assign { \xer_so_ok$91 \xer_so$90 } { \output_xer_so_ok \output_xer_so$57 }
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615"
+ wire width 1 \r_busy
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615"
+ wire width 1 \r_busy$next
+ process $group_71
+ assign \r_busy$next \r_busy
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+ switch { \n_i_rdy_data \p_valid_i_p_ready_o }
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+ case 2'-1
+ assign \r_busy$next 1'1
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
+ case 2'1-
+ assign \r_busy$next 1'0
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+ switch \rst
+ case 1'1
+ assign \r_busy$next 1'0
+ end
+ sync init
+ update \r_busy 1'0
+ sync posedge \clk
+ update \r_busy \r_busy$next
+ end
+ process $group_72
+ assign \muxid$1$next \muxid$1
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+ switch { \n_i_rdy_data \p_valid_i_p_ready_o }
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+ case 2'-1
+ assign \muxid$1$next \muxid$68
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
+ case 2'1-
+ assign \muxid$1$next \muxid$68
+ end
+ sync init
+ update \muxid$1 2'00
+ sync posedge \clk
+ update \muxid$1 \muxid$1$next
+ end
+ process $group_73
+ assign \op__insn_type$2$next \op__insn_type$2
+ assign \op__fn_unit$3$next \op__fn_unit$3
+ assign \op__imm_data__imm$4$next \op__imm_data__imm$4
+ assign \op__imm_data__imm_ok$5$next \op__imm_data__imm_ok$5
+ assign \op__rc__rc$6$next \op__rc__rc$6
+ assign \op__rc__rc_ok$7$next \op__rc__rc_ok$7
+ assign \op__oe__oe$8$next \op__oe__oe$8
+ assign \op__oe__oe_ok$9$next \op__oe__oe_ok$9
+ assign \op__invert_a$10$next \op__invert_a$10
+ assign \op__zero_a$11$next \op__zero_a$11
+ assign \op__invert_out$12$next \op__invert_out$12
+ assign \op__write_cr0$13$next \op__write_cr0$13
+ assign \op__is_32bit$14$next \op__is_32bit$14
+ assign \op__is_signed$15$next \op__is_signed$15
+ assign \op__insn$16$next \op__insn$16
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+ switch { \n_i_rdy_data \p_valid_i_p_ready_o }
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+ case 2'-1
+ assign { \op__insn$16$next \op__is_signed$15$next \op__is_32bit$14$next \op__write_cr0$13$next \op__invert_out$12$next \op__zero_a$11$next \op__invert_a$10$next { \op__oe__oe_ok$9$next \op__oe__oe$8$next } { \op__rc__rc_ok$7$next \op__rc__rc$6$next } { \op__imm_data__imm_ok$5$next \op__imm_data__imm$4$next } \op__fn_unit$3$next \op__insn_type$2$next } { \op__insn$83 \op__is_signed$82 \op__is_32bit$81 \op__write_cr0$80 \op__invert_out$79 \op__zero_a$78 \op__invert_a$77 { \op__oe__oe_ok$76 \op__oe__oe$75 } { \op__rc__rc_ok$74 \op__rc__rc$73 } { \op__imm_data__imm_ok$72 \op__imm_data__imm$71 } \op__fn_unit$70 \op__insn_type$69 }
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
+ case 2'1-
+ assign { \op__insn$16$next \op__is_signed$15$next \op__is_32bit$14$next \op__write_cr0$13$next \op__invert_out$12$next \op__zero_a$11$next \op__invert_a$10$next { \op__oe__oe_ok$9$next \op__oe__oe$8$next } { \op__rc__rc_ok$7$next \op__rc__rc$6$next } { \op__imm_data__imm_ok$5$next \op__imm_data__imm$4$next } \op__fn_unit$3$next \op__insn_type$2$next } { \op__insn$83 \op__is_signed$82 \op__is_32bit$81 \op__write_cr0$80 \op__invert_out$79 \op__zero_a$78 \op__invert_a$77 { \op__oe__oe_ok$76 \op__oe__oe$75 } { \op__rc__rc_ok$74 \op__rc__rc$73 } { \op__imm_data__imm_ok$72 \op__imm_data__imm$71 } \op__fn_unit$70 \op__insn_type$69 }
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+ switch \rst
+ case 1'1
+ assign \op__imm_data__imm$4$next 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \op__imm_data__imm_ok$5$next 1'0
+ assign \op__rc__rc$6$next 1'0
+ assign \op__rc__rc_ok$7$next 1'0
+ assign \op__oe__oe$8$next 1'0
+ assign \op__oe__oe_ok$9$next 1'0
+ end
+ sync init
+ update \op__insn_type$2 7'0000000
+ update \op__fn_unit$3 11'00000000000
+ update \op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000
+ update \op__imm_data__imm_ok$5 1'0
+ update \op__rc__rc$6 1'0
+ update \op__rc__rc_ok$7 1'0
+ update \op__oe__oe$8 1'0
+ update \op__oe__oe_ok$9 1'0
+ update \op__invert_a$10 1'0
+ update \op__zero_a$11 1'0
+ update \op__invert_out$12 1'0
+ update \op__write_cr0$13 1'0
+ update \op__is_32bit$14 1'0
+ update \op__is_signed$15 1'0
+ update \op__insn$16 32'00000000000000000000000000000000
+ sync posedge \clk
+ update \op__insn_type$2 \op__insn_type$2$next
+ update \op__fn_unit$3 \op__fn_unit$3$next
+ update \op__imm_data__imm$4 \op__imm_data__imm$4$next
+ update \op__imm_data__imm_ok$5 \op__imm_data__imm_ok$5$next
+ update \op__rc__rc$6 \op__rc__rc$6$next
+ update \op__rc__rc_ok$7 \op__rc__rc_ok$7$next
+ update \op__oe__oe$8 \op__oe__oe$8$next
+ update \op__oe__oe_ok$9 \op__oe__oe_ok$9$next
+ update \op__invert_a$10 \op__invert_a$10$next
+ update \op__zero_a$11 \op__zero_a$11$next
+ update \op__invert_out$12 \op__invert_out$12$next
+ update \op__write_cr0$13 \op__write_cr0$13$next
+ update \op__is_32bit$14 \op__is_32bit$14$next
+ update \op__is_signed$15 \op__is_signed$15$next
+ update \op__insn$16 \op__insn$16$next
+ end
+ process $group_88
+ assign \o$17$next \o$17
+ assign \o_ok$next \o_ok
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+ switch { \n_i_rdy_data \p_valid_i_p_ready_o }
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+ case 2'-1
+ assign { \o_ok$next \o$17$next } { \o_ok$85 \o$84 }
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
+ case 2'1-
+ assign { \o_ok$next \o$17$next } { \o_ok$85 \o$84 }
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+ switch \rst
+ case 1'1
+ assign \o_ok$next 1'0
+ end
+ sync init
+ update \o$17 64'0000000000000000000000000000000000000000000000000000000000000000
+ update \o_ok 1'0
+ sync posedge \clk
+ update \o$17 \o$17$next
+ update \o_ok \o_ok$next
+ end
+ process $group_90
+ assign \cr_a$next \cr_a
+ assign \cr_a_ok$next \cr_a_ok
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+ switch { \n_i_rdy_data \p_valid_i_p_ready_o }
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+ case 2'-1
+ assign { \cr_a_ok$next \cr_a$next } { \cr_a_ok$87 \cr_a$86 }
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
+ case 2'1-
+ assign { \cr_a_ok$next \cr_a$next } { \cr_a_ok$87 \cr_a$86 }
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+ switch \rst
+ case 1'1
+ assign \cr_a_ok$next 1'0
+ end
+ sync init
+ update \cr_a 4'0000
+ update \cr_a_ok 1'0
+ sync posedge \clk
+ update \cr_a \cr_a$next
+ update \cr_a_ok \cr_a_ok$next
+ end
+ process $group_92
+ assign \xer_ov$next \xer_ov
+ assign \xer_ov_ok$next \xer_ov_ok
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+ switch { \n_i_rdy_data \p_valid_i_p_ready_o }
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+ case 2'-1
+ assign { \xer_ov_ok$next \xer_ov$next } { \xer_ov_ok$89 \xer_ov$88 }
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
+ case 2'1-
+ assign { \xer_ov_ok$next \xer_ov$next } { \xer_ov_ok$89 \xer_ov$88 }
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+ switch \rst
+ case 1'1
+ assign \xer_ov_ok$next 1'0
+ end
+ sync init
+ update \xer_ov 2'00
+ update \xer_ov_ok 1'0
+ sync posedge \clk
+ update \xer_ov \xer_ov$next
+ update \xer_ov_ok \xer_ov_ok$next
+ end
+ process $group_94
+ assign \xer_so$18$next \xer_so$18
+ assign \xer_so_ok$next \xer_so_ok
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+ switch { \n_i_rdy_data \p_valid_i_p_ready_o }
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+ case 2'-1
+ assign { \xer_so_ok$next \xer_so$18$next } { \xer_so_ok$91 \xer_so$90 }
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
+ case 2'1-
+ assign { \xer_so_ok$next \xer_so$18$next } { \xer_so_ok$91 \xer_so$90 }
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+ switch \rst
+ case 1'1
+ assign \xer_so_ok$next 1'0
+ end
+ sync init
+ update \xer_so$18 1'0
+ update \xer_so_ok 1'0
+ sync posedge \clk
+ update \xer_so$18 \xer_so$18$next
+ update \xer_so_ok \xer_so_ok$next
+ end
+ process $group_96
+ assign \n_valid_o 1'0
+ assign \n_valid_o \r_busy
+ sync init
+ end
+ process $group_97
+ assign \p_ready_o 1'0
+ assign \p_ready_o \n_i_rdy_data
+ sync init
+ end
+ connect \cr_a$60 4'0000
+ connect \cr_a_ok$61 1'0
+ connect \xer_so_ok$64 1'0
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0"
+module \alu_mul0
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
+ wire width 1 input 0 \rst
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
+ wire width 1 input 1 \clk
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 2 \o_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 3 \cr_a_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 4 \xer_ov_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 5 \xer_so_ok
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
+ wire width 1 output 6 \n_valid_o
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
+ wire width 1 input 7 \n_ready_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 64 output 8 \o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 4 output 9 \cr_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 2 output 10 \xer_ov
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 11 \xer_so
+ attribute \enum_base_type "MicrOp"
+ attribute \enum_value_0000000 "OP_ILLEGAL"
+ attribute \enum_value_0000001 "OP_NOP"
+ attribute \enum_value_0000010 "OP_ADD"
+ attribute \enum_value_0000011 "OP_ADDPCIS"
+ attribute \enum_value_0000100 "OP_AND"
+ attribute \enum_value_0000101 "OP_ATTN"
+ attribute \enum_value_0000110 "OP_B"
+ attribute \enum_value_0000111 "OP_BC"
+ attribute \enum_value_0001000 "OP_BCREG"
+ attribute \enum_value_0001001 "OP_BPERM"
+ attribute \enum_value_0001010 "OP_CMP"
+ attribute \enum_value_0001011 "OP_CMPB"
+ attribute \enum_value_0001100 "OP_CMPEQB"
+ attribute \enum_value_0001101 "OP_CMPRB"
+ attribute \enum_value_0001110 "OP_CNTZ"
+ attribute \enum_value_0001111 "OP_CRAND"
+ attribute \enum_value_0010000 "OP_CRANDC"
+ attribute \enum_value_0010001 "OP_CREQV"
+ attribute \enum_value_0010010 "OP_CRNAND"
+ attribute \enum_value_0010011 "OP_CRNOR"
+ attribute \enum_value_0010100 "OP_CROR"
+ attribute \enum_value_0010101 "OP_CRORC"
+ attribute \enum_value_0010110 "OP_CRXOR"
+ attribute \enum_value_0010111 "OP_DARN"
+ attribute \enum_value_0011000 "OP_DCBF"
+ attribute \enum_value_0011001 "OP_DCBST"
+ attribute \enum_value_0011010 "OP_DCBT"
+ attribute \enum_value_0011011 "OP_DCBTST"
+ attribute \enum_value_0011100 "OP_DCBZ"
+ attribute \enum_value_0011101 "OP_DIV"
+ attribute \enum_value_0011110 "OP_DIVE"
+ attribute \enum_value_0011111 "OP_EXTS"
+ attribute \enum_value_0100000 "OP_EXTSWSLI"
+ attribute \enum_value_0100001 "OP_ICBI"
+ attribute \enum_value_0100010 "OP_ICBT"
+ attribute \enum_value_0100011 "OP_ISEL"
+ attribute \enum_value_0100100 "OP_ISYNC"
+ attribute \enum_value_0100101 "OP_LOAD"
+ attribute \enum_value_0100110 "OP_STORE"
+ attribute \enum_value_0100111 "OP_MADDHD"
+ attribute \enum_value_0101000 "OP_MADDHDU"
+ attribute \enum_value_0101001 "OP_MADDLD"
+ attribute \enum_value_0101010 "OP_MCRF"
+ attribute \enum_value_0101011 "OP_MCRXR"
+ attribute \enum_value_0101100 "OP_MCRXRX"
+ attribute \enum_value_0101101 "OP_MFCR"
+ attribute \enum_value_0101110 "OP_MFSPR"
+ attribute \enum_value_0101111 "OP_MOD"
+ attribute \enum_value_0110000 "OP_MTCRF"
+ attribute \enum_value_0110001 "OP_MTSPR"
+ attribute \enum_value_0110010 "OP_MUL_L64"
+ attribute \enum_value_0110011 "OP_MUL_H64"
+ attribute \enum_value_0110100 "OP_MUL_H32"
+ attribute \enum_value_0110101 "OP_OR"
+ attribute \enum_value_0110110 "OP_POPCNT"
+ attribute \enum_value_0110111 "OP_PRTY"
+ attribute \enum_value_0111000 "OP_RLC"
+ attribute \enum_value_0111001 "OP_RLCL"
+ attribute \enum_value_0111010 "OP_RLCR"
+ attribute \enum_value_0111011 "OP_SETB"
+ attribute \enum_value_0111100 "OP_SHL"
+ attribute \enum_value_0111101 "OP_SHR"
+ attribute \enum_value_0111110 "OP_SYNC"
+ attribute \enum_value_0111111 "OP_TRAP"
+ attribute \enum_value_1000011 "OP_XOR"
+ attribute \enum_value_1000100 "OP_SIM_CONFIG"
+ attribute \enum_value_1000101 "OP_CROP"
+ attribute \enum_value_1000110 "OP_RFID"
+ attribute \enum_value_1000111 "OP_MFMSR"
+ attribute \enum_value_1001000 "OP_MTMSRD"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 7 input 12 \op__insn_type
+ attribute \enum_base_type "Function"
+ attribute \enum_value_00000000000 "NONE"
+ attribute \enum_value_00000000010 "ALU"
+ attribute \enum_value_00000000100 "LDST"
+ attribute \enum_value_00000001000 "SHIFT_ROT"
+ attribute \enum_value_00000010000 "LOGICAL"
+ attribute \enum_value_00000100000 "BRANCH"
+ attribute \enum_value_00001000000 "CR"
+ attribute \enum_value_00010000000 "TRAP"
+ attribute \enum_value_00100000000 "MUL"
+ attribute \enum_value_01000000000 "DIV"
+ attribute \enum_value_10000000000 "SPR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 11 input 13 \op__fn_unit
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 input 14 \op__imm_data__imm
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 15 \op__imm_data__imm_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 16 \op__rc__rc
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 17 \op__rc__rc_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 18 \op__oe__oe
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 19 \op__oe__oe_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 20 \op__invert_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 21 \op__zero_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 22 \op__invert_out
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 23 \op__write_cr0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 24 \op__is_32bit
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 25 \op__is_signed
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 input 26 \op__insn
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 64 input 27 \ra
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 64 input 28 \rb
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 1 input 29 \xer_so$1
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153"
+ wire width 1 input 30 \p_valid_i
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154"
+ wire width 1 output 31 \p_ready_o
+ cell \p$70 \p
+ connect \p_valid_i \p_valid_i
+ connect \p_ready_o \p_ready_o
+ end
+ cell \n$71 \n
+ connect \n_valid_o \n_valid_o
+ connect \n_ready_i \n_ready_i
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
+ wire width 1 \mul_pipe1_n_valid_o
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
+ wire width 1 \mul_pipe1_n_ready_i
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+ wire width 2 \mul_pipe1_muxid
+ attribute \enum_base_type "MicrOp"
+ attribute \enum_value_0000000 "OP_ILLEGAL"
+ attribute \enum_value_0000001 "OP_NOP"
+ attribute \enum_value_0000010 "OP_ADD"
+ attribute \enum_value_0000011 "OP_ADDPCIS"
+ attribute \enum_value_0000100 "OP_AND"
+ attribute \enum_value_0000101 "OP_ATTN"
+ attribute \enum_value_0000110 "OP_B"
+ attribute \enum_value_0000111 "OP_BC"
+ attribute \enum_value_0001000 "OP_BCREG"
+ attribute \enum_value_0001001 "OP_BPERM"
+ attribute \enum_value_0001010 "OP_CMP"
+ attribute \enum_value_0001011 "OP_CMPB"
+ attribute \enum_value_0001100 "OP_CMPEQB"
+ attribute \enum_value_0001101 "OP_CMPRB"
+ attribute \enum_value_0001110 "OP_CNTZ"
+ attribute \enum_value_0001111 "OP_CRAND"
+ attribute \enum_value_0010000 "OP_CRANDC"
+ attribute \enum_value_0010001 "OP_CREQV"
+ attribute \enum_value_0010010 "OP_CRNAND"
+ attribute \enum_value_0010011 "OP_CRNOR"
+ attribute \enum_value_0010100 "OP_CROR"
+ attribute \enum_value_0010101 "OP_CRORC"
+ attribute \enum_value_0010110 "OP_CRXOR"
+ attribute \enum_value_0010111 "OP_DARN"
+ attribute \enum_value_0011000 "OP_DCBF"
+ attribute \enum_value_0011001 "OP_DCBST"
+ attribute \enum_value_0011010 "OP_DCBT"
+ attribute \enum_value_0011011 "OP_DCBTST"
+ attribute \enum_value_0011100 "OP_DCBZ"
+ attribute \enum_value_0011101 "OP_DIV"
+ attribute \enum_value_0011110 "OP_DIVE"
+ attribute \enum_value_0011111 "OP_EXTS"
+ attribute \enum_value_0100000 "OP_EXTSWSLI"
+ attribute \enum_value_0100001 "OP_ICBI"
+ attribute \enum_value_0100010 "OP_ICBT"
+ attribute \enum_value_0100011 "OP_ISEL"
+ attribute \enum_value_0100100 "OP_ISYNC"
+ attribute \enum_value_0100101 "OP_LOAD"
+ attribute \enum_value_0100110 "OP_STORE"
+ attribute \enum_value_0100111 "OP_MADDHD"
+ attribute \enum_value_0101000 "OP_MADDHDU"
+ attribute \enum_value_0101001 "OP_MADDLD"
+ attribute \enum_value_0101010 "OP_MCRF"
+ attribute \enum_value_0101011 "OP_MCRXR"
+ attribute \enum_value_0101100 "OP_MCRXRX"
+ attribute \enum_value_0101101 "OP_MFCR"
+ attribute \enum_value_0101110 "OP_MFSPR"
+ attribute \enum_value_0101111 "OP_MOD"
+ attribute \enum_value_0110000 "OP_MTCRF"
+ attribute \enum_value_0110001 "OP_MTSPR"
+ attribute \enum_value_0110010 "OP_MUL_L64"
+ attribute \enum_value_0110011 "OP_MUL_H64"
+ attribute \enum_value_0110100 "OP_MUL_H32"
+ attribute \enum_value_0110101 "OP_OR"
+ attribute \enum_value_0110110 "OP_POPCNT"
+ attribute \enum_value_0110111 "OP_PRTY"
+ attribute \enum_value_0111000 "OP_RLC"
+ attribute \enum_value_0111001 "OP_RLCL"
+ attribute \enum_value_0111010 "OP_RLCR"
+ attribute \enum_value_0111011 "OP_SETB"
+ attribute \enum_value_0111100 "OP_SHL"
+ attribute \enum_value_0111101 "OP_SHR"
+ attribute \enum_value_0111110 "OP_SYNC"
+ attribute \enum_value_0111111 "OP_TRAP"
+ attribute \enum_value_1000011 "OP_XOR"
+ attribute \enum_value_1000100 "OP_SIM_CONFIG"
+ attribute \enum_value_1000101 "OP_CROP"
+ attribute \enum_value_1000110 "OP_RFID"
+ attribute \enum_value_1000111 "OP_MFMSR"
+ attribute \enum_value_1001000 "OP_MTMSRD"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 7 \mul_pipe1_op__insn_type
+ attribute \enum_base_type "Function"
+ attribute \enum_value_00000000000 "NONE"
+ attribute \enum_value_00000000010 "ALU"
+ attribute \enum_value_00000000100 "LDST"
+ attribute \enum_value_00000001000 "SHIFT_ROT"
+ attribute \enum_value_00000010000 "LOGICAL"
+ attribute \enum_value_00000100000 "BRANCH"
+ attribute \enum_value_00001000000 "CR"
+ attribute \enum_value_00010000000 "TRAP"
+ attribute \enum_value_00100000000 "MUL"
+ attribute \enum_value_01000000000 "DIV"
+ attribute \enum_value_10000000000 "SPR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 11 \mul_pipe1_op__fn_unit
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 \mul_pipe1_op__imm_data__imm
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \mul_pipe1_op__imm_data__imm_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \mul_pipe1_op__rc__rc
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \mul_pipe1_op__rc__rc_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \mul_pipe1_op__oe__oe
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \mul_pipe1_op__oe__oe_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \mul_pipe1_op__invert_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \mul_pipe1_op__zero_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \mul_pipe1_op__invert_out
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \mul_pipe1_op__write_cr0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \mul_pipe1_op__is_32bit
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \mul_pipe1_op__is_signed
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 \mul_pipe1_op__insn
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 64 \mul_pipe1_ra
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 64 \mul_pipe1_rb
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 1 \mul_pipe1_xer_so
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11"
+ wire width 1 \mul_pipe1_neg_res
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12"
+ wire width 1 \mul_pipe1_neg_res32
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153"
+ wire width 1 \mul_pipe1_p_valid_i
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154"
+ wire width 1 \mul_pipe1_p_ready_o
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+ wire width 2 \mul_pipe1_muxid$2
+ attribute \enum_base_type "MicrOp"
+ attribute \enum_value_0000000 "OP_ILLEGAL"
+ attribute \enum_value_0000001 "OP_NOP"
+ attribute \enum_value_0000010 "OP_ADD"
+ attribute \enum_value_0000011 "OP_ADDPCIS"
+ attribute \enum_value_0000100 "OP_AND"
+ attribute \enum_value_0000101 "OP_ATTN"
+ attribute \enum_value_0000110 "OP_B"
+ attribute \enum_value_0000111 "OP_BC"
+ attribute \enum_value_0001000 "OP_BCREG"
+ attribute \enum_value_0001001 "OP_BPERM"
+ attribute \enum_value_0001010 "OP_CMP"
+ attribute \enum_value_0001011 "OP_CMPB"
+ attribute \enum_value_0001100 "OP_CMPEQB"
+ attribute \enum_value_0001101 "OP_CMPRB"
+ attribute \enum_value_0001110 "OP_CNTZ"
+ attribute \enum_value_0001111 "OP_CRAND"
+ attribute \enum_value_0010000 "OP_CRANDC"
+ attribute \enum_value_0010001 "OP_CREQV"
+ attribute \enum_value_0010010 "OP_CRNAND"
+ attribute \enum_value_0010011 "OP_CRNOR"
+ attribute \enum_value_0010100 "OP_CROR"
+ attribute \enum_value_0010101 "OP_CRORC"
+ attribute \enum_value_0010110 "OP_CRXOR"
+ attribute \enum_value_0010111 "OP_DARN"
+ attribute \enum_value_0011000 "OP_DCBF"
+ attribute \enum_value_0011001 "OP_DCBST"
+ attribute \enum_value_0011010 "OP_DCBT"
+ attribute \enum_value_0011011 "OP_DCBTST"
+ attribute \enum_value_0011100 "OP_DCBZ"
+ attribute \enum_value_0011101 "OP_DIV"
+ attribute \enum_value_0011110 "OP_DIVE"
+ attribute \enum_value_0011111 "OP_EXTS"
+ attribute \enum_value_0100000 "OP_EXTSWSLI"
+ attribute \enum_value_0100001 "OP_ICBI"
+ attribute \enum_value_0100010 "OP_ICBT"
+ attribute \enum_value_0100011 "OP_ISEL"
+ attribute \enum_value_0100100 "OP_ISYNC"
+ attribute \enum_value_0100101 "OP_LOAD"
+ attribute \enum_value_0100110 "OP_STORE"
+ attribute \enum_value_0100111 "OP_MADDHD"
+ attribute \enum_value_0101000 "OP_MADDHDU"
+ attribute \enum_value_0101001 "OP_MADDLD"
+ attribute \enum_value_0101010 "OP_MCRF"
+ attribute \enum_value_0101011 "OP_MCRXR"
+ attribute \enum_value_0101100 "OP_MCRXRX"
+ attribute \enum_value_0101101 "OP_MFCR"
+ attribute \enum_value_0101110 "OP_MFSPR"
+ attribute \enum_value_0101111 "OP_MOD"
+ attribute \enum_value_0110000 "OP_MTCRF"
+ attribute \enum_value_0110001 "OP_MTSPR"
+ attribute \enum_value_0110010 "OP_MUL_L64"
+ attribute \enum_value_0110011 "OP_MUL_H64"
+ attribute \enum_value_0110100 "OP_MUL_H32"
+ attribute \enum_value_0110101 "OP_OR"
+ attribute \enum_value_0110110 "OP_POPCNT"
+ attribute \enum_value_0110111 "OP_PRTY"
+ attribute \enum_value_0111000 "OP_RLC"
+ attribute \enum_value_0111001 "OP_RLCL"
+ attribute \enum_value_0111010 "OP_RLCR"
+ attribute \enum_value_0111011 "OP_SETB"
+ attribute \enum_value_0111100 "OP_SHL"
+ attribute \enum_value_0111101 "OP_SHR"
+ attribute \enum_value_0111110 "OP_SYNC"
+ attribute \enum_value_0111111 "OP_TRAP"
+ attribute \enum_value_1000011 "OP_XOR"
+ attribute \enum_value_1000100 "OP_SIM_CONFIG"
+ attribute \enum_value_1000101 "OP_CROP"
+ attribute \enum_value_1000110 "OP_RFID"
+ attribute \enum_value_1000111 "OP_MFMSR"
+ attribute \enum_value_1001000 "OP_MTMSRD"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 7 \mul_pipe1_op__insn_type$3
+ attribute \enum_base_type "Function"
+ attribute \enum_value_00000000000 "NONE"
+ attribute \enum_value_00000000010 "ALU"
+ attribute \enum_value_00000000100 "LDST"
+ attribute \enum_value_00000001000 "SHIFT_ROT"
+ attribute \enum_value_00000010000 "LOGICAL"
+ attribute \enum_value_00000100000 "BRANCH"
+ attribute \enum_value_00001000000 "CR"
+ attribute \enum_value_00010000000 "TRAP"
+ attribute \enum_value_00100000000 "MUL"
+ attribute \enum_value_01000000000 "DIV"
+ attribute \enum_value_10000000000 "SPR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 11 \mul_pipe1_op__fn_unit$4
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 \mul_pipe1_op__imm_data__imm$5
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \mul_pipe1_op__imm_data__imm_ok$6
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \mul_pipe1_op__rc__rc$7
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \mul_pipe1_op__rc__rc_ok$8
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \mul_pipe1_op__oe__oe$9
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \mul_pipe1_op__oe__oe_ok$10
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \mul_pipe1_op__invert_a$11
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \mul_pipe1_op__zero_a$12
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \mul_pipe1_op__invert_out$13
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \mul_pipe1_op__write_cr0$14
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \mul_pipe1_op__is_32bit$15
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \mul_pipe1_op__is_signed$16
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 \mul_pipe1_op__insn$17
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 64 \mul_pipe1_ra$18
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 64 \mul_pipe1_rb$19
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 1 \mul_pipe1_xer_so$20
+ cell \mul_pipe1 \mul_pipe1
+ connect \rst \rst
+ connect \clk \clk
+ connect \n_valid_o \mul_pipe1_n_valid_o
+ connect \n_ready_i \mul_pipe1_n_ready_i
+ connect \muxid \mul_pipe1_muxid
+ connect \op__insn_type \mul_pipe1_op__insn_type
+ connect \op__fn_unit \mul_pipe1_op__fn_unit
+ connect \op__imm_data__imm \mul_pipe1_op__imm_data__imm
+ connect \op__imm_data__imm_ok \mul_pipe1_op__imm_data__imm_ok
+ connect \op__rc__rc \mul_pipe1_op__rc__rc
+ connect \op__rc__rc_ok \mul_pipe1_op__rc__rc_ok
+ connect \op__oe__oe \mul_pipe1_op__oe__oe
+ connect \op__oe__oe_ok \mul_pipe1_op__oe__oe_ok
+ connect \op__invert_a \mul_pipe1_op__invert_a
+ connect \op__zero_a \mul_pipe1_op__zero_a
+ connect \op__invert_out \mul_pipe1_op__invert_out
+ connect \op__write_cr0 \mul_pipe1_op__write_cr0
+ connect \op__is_32bit \mul_pipe1_op__is_32bit
+ connect \op__is_signed \mul_pipe1_op__is_signed
+ connect \op__insn \mul_pipe1_op__insn
+ connect \ra \mul_pipe1_ra
+ connect \rb \mul_pipe1_rb
+ connect \xer_so \mul_pipe1_xer_so
+ connect \neg_res \mul_pipe1_neg_res
+ connect \neg_res32 \mul_pipe1_neg_res32
+ connect \p_valid_i \mul_pipe1_p_valid_i
+ connect \p_ready_o \mul_pipe1_p_ready_o
+ connect \muxid$1 \mul_pipe1_muxid$2
+ connect \op__insn_type$2 \mul_pipe1_op__insn_type$3
+ connect \op__fn_unit$3 \mul_pipe1_op__fn_unit$4
+ connect \op__imm_data__imm$4 \mul_pipe1_op__imm_data__imm$5
+ connect \op__imm_data__imm_ok$5 \mul_pipe1_op__imm_data__imm_ok$6
+ connect \op__rc__rc$6 \mul_pipe1_op__rc__rc$7
+ connect \op__rc__rc_ok$7 \mul_pipe1_op__rc__rc_ok$8
+ connect \op__oe__oe$8 \mul_pipe1_op__oe__oe$9
+ connect \op__oe__oe_ok$9 \mul_pipe1_op__oe__oe_ok$10
+ connect \op__invert_a$10 \mul_pipe1_op__invert_a$11
+ connect \op__zero_a$11 \mul_pipe1_op__zero_a$12
+ connect \op__invert_out$12 \mul_pipe1_op__invert_out$13
+ connect \op__write_cr0$13 \mul_pipe1_op__write_cr0$14
+ connect \op__is_32bit$14 \mul_pipe1_op__is_32bit$15
+ connect \op__is_signed$15 \mul_pipe1_op__is_signed$16
+ connect \op__insn$16 \mul_pipe1_op__insn$17
+ connect \ra$17 \mul_pipe1_ra$18
+ connect \rb$18 \mul_pipe1_rb$19
+ connect \xer_so$19 \mul_pipe1_xer_so$20
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153"
+ wire width 1 \mul_pipe2_p_valid_i
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154"
+ wire width 1 \mul_pipe2_p_ready_o
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+ wire width 2 \mul_pipe2_muxid
+ attribute \enum_base_type "MicrOp"
+ attribute \enum_value_0000000 "OP_ILLEGAL"
+ attribute \enum_value_0000001 "OP_NOP"
+ attribute \enum_value_0000010 "OP_ADD"
+ attribute \enum_value_0000011 "OP_ADDPCIS"
+ attribute \enum_value_0000100 "OP_AND"
+ attribute \enum_value_0000101 "OP_ATTN"
+ attribute \enum_value_0000110 "OP_B"
+ attribute \enum_value_0000111 "OP_BC"
+ attribute \enum_value_0001000 "OP_BCREG"
+ attribute \enum_value_0001001 "OP_BPERM"
+ attribute \enum_value_0001010 "OP_CMP"
+ attribute \enum_value_0001011 "OP_CMPB"
+ attribute \enum_value_0001100 "OP_CMPEQB"
+ attribute \enum_value_0001101 "OP_CMPRB"
+ attribute \enum_value_0001110 "OP_CNTZ"
+ attribute \enum_value_0001111 "OP_CRAND"
+ attribute \enum_value_0010000 "OP_CRANDC"
+ attribute \enum_value_0010001 "OP_CREQV"
+ attribute \enum_value_0010010 "OP_CRNAND"
+ attribute \enum_value_0010011 "OP_CRNOR"
+ attribute \enum_value_0010100 "OP_CROR"
+ attribute \enum_value_0010101 "OP_CRORC"
+ attribute \enum_value_0010110 "OP_CRXOR"
+ attribute \enum_value_0010111 "OP_DARN"
+ attribute \enum_value_0011000 "OP_DCBF"
+ attribute \enum_value_0011001 "OP_DCBST"
+ attribute \enum_value_0011010 "OP_DCBT"
+ attribute \enum_value_0011011 "OP_DCBTST"
+ attribute \enum_value_0011100 "OP_DCBZ"
+ attribute \enum_value_0011101 "OP_DIV"
+ attribute \enum_value_0011110 "OP_DIVE"
+ attribute \enum_value_0011111 "OP_EXTS"
+ attribute \enum_value_0100000 "OP_EXTSWSLI"
+ attribute \enum_value_0100001 "OP_ICBI"
+ attribute \enum_value_0100010 "OP_ICBT"
+ attribute \enum_value_0100011 "OP_ISEL"
+ attribute \enum_value_0100100 "OP_ISYNC"
+ attribute \enum_value_0100101 "OP_LOAD"
+ attribute \enum_value_0100110 "OP_STORE"
+ attribute \enum_value_0100111 "OP_MADDHD"
+ attribute \enum_value_0101000 "OP_MADDHDU"
+ attribute \enum_value_0101001 "OP_MADDLD"
+ attribute \enum_value_0101010 "OP_MCRF"
+ attribute \enum_value_0101011 "OP_MCRXR"
+ attribute \enum_value_0101100 "OP_MCRXRX"
+ attribute \enum_value_0101101 "OP_MFCR"
+ attribute \enum_value_0101110 "OP_MFSPR"
+ attribute \enum_value_0101111 "OP_MOD"
+ attribute \enum_value_0110000 "OP_MTCRF"
+ attribute \enum_value_0110001 "OP_MTSPR"
+ attribute \enum_value_0110010 "OP_MUL_L64"
+ attribute \enum_value_0110011 "OP_MUL_H64"
+ attribute \enum_value_0110100 "OP_MUL_H32"
+ attribute \enum_value_0110101 "OP_OR"
+ attribute \enum_value_0110110 "OP_POPCNT"
+ attribute \enum_value_0110111 "OP_PRTY"
+ attribute \enum_value_0111000 "OP_RLC"
+ attribute \enum_value_0111001 "OP_RLCL"
+ attribute \enum_value_0111010 "OP_RLCR"
+ attribute \enum_value_0111011 "OP_SETB"
+ attribute \enum_value_0111100 "OP_SHL"
+ attribute \enum_value_0111101 "OP_SHR"
+ attribute \enum_value_0111110 "OP_SYNC"
+ attribute \enum_value_0111111 "OP_TRAP"
+ attribute \enum_value_1000011 "OP_XOR"
+ attribute \enum_value_1000100 "OP_SIM_CONFIG"
+ attribute \enum_value_1000101 "OP_CROP"
+ attribute \enum_value_1000110 "OP_RFID"
+ attribute \enum_value_1000111 "OP_MFMSR"
+ attribute \enum_value_1001000 "OP_MTMSRD"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 7 \mul_pipe2_op__insn_type
+ attribute \enum_base_type "Function"
+ attribute \enum_value_00000000000 "NONE"
+ attribute \enum_value_00000000010 "ALU"
+ attribute \enum_value_00000000100 "LDST"
+ attribute \enum_value_00000001000 "SHIFT_ROT"
+ attribute \enum_value_00000010000 "LOGICAL"
+ attribute \enum_value_00000100000 "BRANCH"
+ attribute \enum_value_00001000000 "CR"
+ attribute \enum_value_00010000000 "TRAP"
+ attribute \enum_value_00100000000 "MUL"
+ attribute \enum_value_01000000000 "DIV"
+ attribute \enum_value_10000000000 "SPR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 11 \mul_pipe2_op__fn_unit
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 \mul_pipe2_op__imm_data__imm
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \mul_pipe2_op__imm_data__imm_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \mul_pipe2_op__rc__rc
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \mul_pipe2_op__rc__rc_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \mul_pipe2_op__oe__oe
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \mul_pipe2_op__oe__oe_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \mul_pipe2_op__invert_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \mul_pipe2_op__zero_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \mul_pipe2_op__invert_out
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \mul_pipe2_op__write_cr0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \mul_pipe2_op__is_32bit
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \mul_pipe2_op__is_signed
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 \mul_pipe2_op__insn
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 64 \mul_pipe2_ra
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 64 \mul_pipe2_rb
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 1 \mul_pipe2_xer_so
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11"
+ wire width 1 \mul_pipe2_neg_res
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12"
+ wire width 1 \mul_pipe2_neg_res32
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
+ wire width 1 \mul_pipe2_n_valid_o
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
+ wire width 1 \mul_pipe2_n_ready_i
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+ wire width 2 \mul_pipe2_muxid$21
+ attribute \enum_base_type "MicrOp"
+ attribute \enum_value_0000000 "OP_ILLEGAL"
+ attribute \enum_value_0000001 "OP_NOP"
+ attribute \enum_value_0000010 "OP_ADD"
+ attribute \enum_value_0000011 "OP_ADDPCIS"
+ attribute \enum_value_0000100 "OP_AND"
+ attribute \enum_value_0000101 "OP_ATTN"
+ attribute \enum_value_0000110 "OP_B"
+ attribute \enum_value_0000111 "OP_BC"
+ attribute \enum_value_0001000 "OP_BCREG"
+ attribute \enum_value_0001001 "OP_BPERM"
+ attribute \enum_value_0001010 "OP_CMP"
+ attribute \enum_value_0001011 "OP_CMPB"
+ attribute \enum_value_0001100 "OP_CMPEQB"
+ attribute \enum_value_0001101 "OP_CMPRB"
+ attribute \enum_value_0001110 "OP_CNTZ"
+ attribute \enum_value_0001111 "OP_CRAND"
+ attribute \enum_value_0010000 "OP_CRANDC"
+ attribute \enum_value_0010001 "OP_CREQV"
+ attribute \enum_value_0010010 "OP_CRNAND"
+ attribute \enum_value_0010011 "OP_CRNOR"
+ attribute \enum_value_0010100 "OP_CROR"
+ attribute \enum_value_0010101 "OP_CRORC"
+ attribute \enum_value_0010110 "OP_CRXOR"
+ attribute \enum_value_0010111 "OP_DARN"
+ attribute \enum_value_0011000 "OP_DCBF"
+ attribute \enum_value_0011001 "OP_DCBST"
+ attribute \enum_value_0011010 "OP_DCBT"
+ attribute \enum_value_0011011 "OP_DCBTST"
+ attribute \enum_value_0011100 "OP_DCBZ"
+ attribute \enum_value_0011101 "OP_DIV"
+ attribute \enum_value_0011110 "OP_DIVE"
+ attribute \enum_value_0011111 "OP_EXTS"
+ attribute \enum_value_0100000 "OP_EXTSWSLI"
+ attribute \enum_value_0100001 "OP_ICBI"
+ attribute \enum_value_0100010 "OP_ICBT"
+ attribute \enum_value_0100011 "OP_ISEL"
+ attribute \enum_value_0100100 "OP_ISYNC"
+ attribute \enum_value_0100101 "OP_LOAD"
+ attribute \enum_value_0100110 "OP_STORE"
+ attribute \enum_value_0100111 "OP_MADDHD"
+ attribute \enum_value_0101000 "OP_MADDHDU"
+ attribute \enum_value_0101001 "OP_MADDLD"
+ attribute \enum_value_0101010 "OP_MCRF"
+ attribute \enum_value_0101011 "OP_MCRXR"
+ attribute \enum_value_0101100 "OP_MCRXRX"
+ attribute \enum_value_0101101 "OP_MFCR"
+ attribute \enum_value_0101110 "OP_MFSPR"
+ attribute \enum_value_0101111 "OP_MOD"
+ attribute \enum_value_0110000 "OP_MTCRF"
+ attribute \enum_value_0110001 "OP_MTSPR"
+ attribute \enum_value_0110010 "OP_MUL_L64"
+ attribute \enum_value_0110011 "OP_MUL_H64"
+ attribute \enum_value_0110100 "OP_MUL_H32"
+ attribute \enum_value_0110101 "OP_OR"
+ attribute \enum_value_0110110 "OP_POPCNT"
+ attribute \enum_value_0110111 "OP_PRTY"
+ attribute \enum_value_0111000 "OP_RLC"
+ attribute \enum_value_0111001 "OP_RLCL"
+ attribute \enum_value_0111010 "OP_RLCR"
+ attribute \enum_value_0111011 "OP_SETB"
+ attribute \enum_value_0111100 "OP_SHL"
+ attribute \enum_value_0111101 "OP_SHR"
+ attribute \enum_value_0111110 "OP_SYNC"
+ attribute \enum_value_0111111 "OP_TRAP"
+ attribute \enum_value_1000011 "OP_XOR"
+ attribute \enum_value_1000100 "OP_SIM_CONFIG"
+ attribute \enum_value_1000101 "OP_CROP"
+ attribute \enum_value_1000110 "OP_RFID"
+ attribute \enum_value_1000111 "OP_MFMSR"
+ attribute \enum_value_1001000 "OP_MTMSRD"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 7 \mul_pipe2_op__insn_type$22
+ attribute \enum_base_type "Function"
+ attribute \enum_value_00000000000 "NONE"
+ attribute \enum_value_00000000010 "ALU"
+ attribute \enum_value_00000000100 "LDST"
+ attribute \enum_value_00000001000 "SHIFT_ROT"
+ attribute \enum_value_00000010000 "LOGICAL"
+ attribute \enum_value_00000100000 "BRANCH"
+ attribute \enum_value_00001000000 "CR"
+ attribute \enum_value_00010000000 "TRAP"
+ attribute \enum_value_00100000000 "MUL"
+ attribute \enum_value_01000000000 "DIV"
+ attribute \enum_value_10000000000 "SPR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 11 \mul_pipe2_op__fn_unit$23
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 \mul_pipe2_op__imm_data__imm$24
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \mul_pipe2_op__imm_data__imm_ok$25
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \mul_pipe2_op__rc__rc$26
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \mul_pipe2_op__rc__rc_ok$27
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \mul_pipe2_op__oe__oe$28
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \mul_pipe2_op__oe__oe_ok$29
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \mul_pipe2_op__invert_a$30
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \mul_pipe2_op__zero_a$31
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \mul_pipe2_op__invert_out$32
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \mul_pipe2_op__write_cr0$33
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \mul_pipe2_op__is_32bit$34
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \mul_pipe2_op__is_signed$35
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 \mul_pipe2_op__insn$36
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 129 \mul_pipe2_o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 1 \mul_pipe2_xer_so$37
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23"
+ wire width 1 \mul_pipe2_neg_res$38
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24"
+ wire width 1 \mul_pipe2_neg_res32$39
+ cell \mul_pipe2 \mul_pipe2
+ connect \rst \rst
+ connect \clk \clk
+ connect \p_valid_i \mul_pipe2_p_valid_i
+ connect \p_ready_o \mul_pipe2_p_ready_o
+ connect \muxid \mul_pipe2_muxid
+ connect \op__insn_type \mul_pipe2_op__insn_type
+ connect \op__fn_unit \mul_pipe2_op__fn_unit
+ connect \op__imm_data__imm \mul_pipe2_op__imm_data__imm
+ connect \op__imm_data__imm_ok \mul_pipe2_op__imm_data__imm_ok
+ connect \op__rc__rc \mul_pipe2_op__rc__rc
+ connect \op__rc__rc_ok \mul_pipe2_op__rc__rc_ok
+ connect \op__oe__oe \mul_pipe2_op__oe__oe
+ connect \op__oe__oe_ok \mul_pipe2_op__oe__oe_ok
+ connect \op__invert_a \mul_pipe2_op__invert_a
+ connect \op__zero_a \mul_pipe2_op__zero_a
+ connect \op__invert_out \mul_pipe2_op__invert_out
+ connect \op__write_cr0 \mul_pipe2_op__write_cr0
+ connect \op__is_32bit \mul_pipe2_op__is_32bit
+ connect \op__is_signed \mul_pipe2_op__is_signed
+ connect \op__insn \mul_pipe2_op__insn
+ connect \ra \mul_pipe2_ra
+ connect \rb \mul_pipe2_rb
+ connect \xer_so \mul_pipe2_xer_so
+ connect \neg_res \mul_pipe2_neg_res
+ connect \neg_res32 \mul_pipe2_neg_res32
+ connect \n_valid_o \mul_pipe2_n_valid_o
+ connect \n_ready_i \mul_pipe2_n_ready_i
+ connect \muxid$1 \mul_pipe2_muxid$21
+ connect \op__insn_type$2 \mul_pipe2_op__insn_type$22
+ connect \op__fn_unit$3 \mul_pipe2_op__fn_unit$23
+ connect \op__imm_data__imm$4 \mul_pipe2_op__imm_data__imm$24
+ connect \op__imm_data__imm_ok$5 \mul_pipe2_op__imm_data__imm_ok$25
+ connect \op__rc__rc$6 \mul_pipe2_op__rc__rc$26
+ connect \op__rc__rc_ok$7 \mul_pipe2_op__rc__rc_ok$27
+ connect \op__oe__oe$8 \mul_pipe2_op__oe__oe$28
+ connect \op__oe__oe_ok$9 \mul_pipe2_op__oe__oe_ok$29
+ connect \op__invert_a$10 \mul_pipe2_op__invert_a$30
+ connect \op__zero_a$11 \mul_pipe2_op__zero_a$31
+ connect \op__invert_out$12 \mul_pipe2_op__invert_out$32
+ connect \op__write_cr0$13 \mul_pipe2_op__write_cr0$33
+ connect \op__is_32bit$14 \mul_pipe2_op__is_32bit$34
+ connect \op__is_signed$15 \mul_pipe2_op__is_signed$35
+ connect \op__insn$16 \mul_pipe2_op__insn$36
+ connect \o \mul_pipe2_o
+ connect \xer_so$17 \mul_pipe2_xer_so$37
+ connect \neg_res$18 \mul_pipe2_neg_res$38
+ connect \neg_res32$19 \mul_pipe2_neg_res32$39
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153"
+ wire width 1 \mul_pipe3_p_valid_i
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154"
+ wire width 1 \mul_pipe3_p_ready_o
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+ wire width 2 \mul_pipe3_muxid
+ attribute \enum_base_type "MicrOp"
+ attribute \enum_value_0000000 "OP_ILLEGAL"
+ attribute \enum_value_0000001 "OP_NOP"
+ attribute \enum_value_0000010 "OP_ADD"
+ attribute \enum_value_0000011 "OP_ADDPCIS"
+ attribute \enum_value_0000100 "OP_AND"
+ attribute \enum_value_0000101 "OP_ATTN"
+ attribute \enum_value_0000110 "OP_B"
+ attribute \enum_value_0000111 "OP_BC"
+ attribute \enum_value_0001000 "OP_BCREG"
+ attribute \enum_value_0001001 "OP_BPERM"
+ attribute \enum_value_0001010 "OP_CMP"
+ attribute \enum_value_0001011 "OP_CMPB"
+ attribute \enum_value_0001100 "OP_CMPEQB"
+ attribute \enum_value_0001101 "OP_CMPRB"
+ attribute \enum_value_0001110 "OP_CNTZ"
+ attribute \enum_value_0001111 "OP_CRAND"
+ attribute \enum_value_0010000 "OP_CRANDC"
+ attribute \enum_value_0010001 "OP_CREQV"
+ attribute \enum_value_0010010 "OP_CRNAND"
+ attribute \enum_value_0010011 "OP_CRNOR"
+ attribute \enum_value_0010100 "OP_CROR"
+ attribute \enum_value_0010101 "OP_CRORC"
+ attribute \enum_value_0010110 "OP_CRXOR"
+ attribute \enum_value_0010111 "OP_DARN"
+ attribute \enum_value_0011000 "OP_DCBF"
+ attribute \enum_value_0011001 "OP_DCBST"
+ attribute \enum_value_0011010 "OP_DCBT"
+ attribute \enum_value_0011011 "OP_DCBTST"
+ attribute \enum_value_0011100 "OP_DCBZ"
+ attribute \enum_value_0011101 "OP_DIV"
+ attribute \enum_value_0011110 "OP_DIVE"
+ attribute \enum_value_0011111 "OP_EXTS"
+ attribute \enum_value_0100000 "OP_EXTSWSLI"
+ attribute \enum_value_0100001 "OP_ICBI"
+ attribute \enum_value_0100010 "OP_ICBT"
+ attribute \enum_value_0100011 "OP_ISEL"
+ attribute \enum_value_0100100 "OP_ISYNC"
+ attribute \enum_value_0100101 "OP_LOAD"
+ attribute \enum_value_0100110 "OP_STORE"
+ attribute \enum_value_0100111 "OP_MADDHD"
+ attribute \enum_value_0101000 "OP_MADDHDU"
+ attribute \enum_value_0101001 "OP_MADDLD"
+ attribute \enum_value_0101010 "OP_MCRF"
+ attribute \enum_value_0101011 "OP_MCRXR"
+ attribute \enum_value_0101100 "OP_MCRXRX"
+ attribute \enum_value_0101101 "OP_MFCR"
+ attribute \enum_value_0101110 "OP_MFSPR"
+ attribute \enum_value_0101111 "OP_MOD"
+ attribute \enum_value_0110000 "OP_MTCRF"
+ attribute \enum_value_0110001 "OP_MTSPR"
+ attribute \enum_value_0110010 "OP_MUL_L64"
+ attribute \enum_value_0110011 "OP_MUL_H64"
+ attribute \enum_value_0110100 "OP_MUL_H32"
+ attribute \enum_value_0110101 "OP_OR"
+ attribute \enum_value_0110110 "OP_POPCNT"
+ attribute \enum_value_0110111 "OP_PRTY"
+ attribute \enum_value_0111000 "OP_RLC"
+ attribute \enum_value_0111001 "OP_RLCL"
+ attribute \enum_value_0111010 "OP_RLCR"
+ attribute \enum_value_0111011 "OP_SETB"
+ attribute \enum_value_0111100 "OP_SHL"
+ attribute \enum_value_0111101 "OP_SHR"
+ attribute \enum_value_0111110 "OP_SYNC"
+ attribute \enum_value_0111111 "OP_TRAP"
+ attribute \enum_value_1000011 "OP_XOR"
+ attribute \enum_value_1000100 "OP_SIM_CONFIG"
+ attribute \enum_value_1000101 "OP_CROP"
+ attribute \enum_value_1000110 "OP_RFID"
+ attribute \enum_value_1000111 "OP_MFMSR"
+ attribute \enum_value_1001000 "OP_MTMSRD"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 7 \mul_pipe3_op__insn_type
+ attribute \enum_base_type "Function"
+ attribute \enum_value_00000000000 "NONE"
+ attribute \enum_value_00000000010 "ALU"
+ attribute \enum_value_00000000100 "LDST"
+ attribute \enum_value_00000001000 "SHIFT_ROT"
+ attribute \enum_value_00000010000 "LOGICAL"
+ attribute \enum_value_00000100000 "BRANCH"
+ attribute \enum_value_00001000000 "CR"
+ attribute \enum_value_00010000000 "TRAP"
+ attribute \enum_value_00100000000 "MUL"
+ attribute \enum_value_01000000000 "DIV"
+ attribute \enum_value_10000000000 "SPR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 11 \mul_pipe3_op__fn_unit
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 \mul_pipe3_op__imm_data__imm
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \mul_pipe3_op__imm_data__imm_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \mul_pipe3_op__rc__rc
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \mul_pipe3_op__rc__rc_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \mul_pipe3_op__oe__oe
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \mul_pipe3_op__oe__oe_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \mul_pipe3_op__invert_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \mul_pipe3_op__zero_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \mul_pipe3_op__invert_out
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \mul_pipe3_op__write_cr0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \mul_pipe3_op__is_32bit
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \mul_pipe3_op__is_signed
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 \mul_pipe3_op__insn
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 129 \mul_pipe3_o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 1 \mul_pipe3_xer_so
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23"
+ wire width 1 \mul_pipe3_neg_res
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24"
+ wire width 1 \mul_pipe3_neg_res32
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
+ wire width 1 \mul_pipe3_n_valid_o
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
+ wire width 1 \mul_pipe3_n_ready_i
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+ wire width 2 \mul_pipe3_muxid$40
+ attribute \enum_base_type "MicrOp"
+ attribute \enum_value_0000000 "OP_ILLEGAL"
+ attribute \enum_value_0000001 "OP_NOP"
+ attribute \enum_value_0000010 "OP_ADD"
+ attribute \enum_value_0000011 "OP_ADDPCIS"
+ attribute \enum_value_0000100 "OP_AND"
+ attribute \enum_value_0000101 "OP_ATTN"
+ attribute \enum_value_0000110 "OP_B"
+ attribute \enum_value_0000111 "OP_BC"
+ attribute \enum_value_0001000 "OP_BCREG"
+ attribute \enum_value_0001001 "OP_BPERM"
+ attribute \enum_value_0001010 "OP_CMP"
+ attribute \enum_value_0001011 "OP_CMPB"
+ attribute \enum_value_0001100 "OP_CMPEQB"
+ attribute \enum_value_0001101 "OP_CMPRB"
+ attribute \enum_value_0001110 "OP_CNTZ"
+ attribute \enum_value_0001111 "OP_CRAND"
+ attribute \enum_value_0010000 "OP_CRANDC"
+ attribute \enum_value_0010001 "OP_CREQV"
+ attribute \enum_value_0010010 "OP_CRNAND"
+ attribute \enum_value_0010011 "OP_CRNOR"
+ attribute \enum_value_0010100 "OP_CROR"
+ attribute \enum_value_0010101 "OP_CRORC"
+ attribute \enum_value_0010110 "OP_CRXOR"
+ attribute \enum_value_0010111 "OP_DARN"
+ attribute \enum_value_0011000 "OP_DCBF"
+ attribute \enum_value_0011001 "OP_DCBST"
+ attribute \enum_value_0011010 "OP_DCBT"
+ attribute \enum_value_0011011 "OP_DCBTST"
+ attribute \enum_value_0011100 "OP_DCBZ"
+ attribute \enum_value_0011101 "OP_DIV"
+ attribute \enum_value_0011110 "OP_DIVE"
+ attribute \enum_value_0011111 "OP_EXTS"
+ attribute \enum_value_0100000 "OP_EXTSWSLI"
+ attribute \enum_value_0100001 "OP_ICBI"
+ attribute \enum_value_0100010 "OP_ICBT"
+ attribute \enum_value_0100011 "OP_ISEL"
+ attribute \enum_value_0100100 "OP_ISYNC"
+ attribute \enum_value_0100101 "OP_LOAD"
+ attribute \enum_value_0100110 "OP_STORE"
+ attribute \enum_value_0100111 "OP_MADDHD"
+ attribute \enum_value_0101000 "OP_MADDHDU"
+ attribute \enum_value_0101001 "OP_MADDLD"
+ attribute \enum_value_0101010 "OP_MCRF"
+ attribute \enum_value_0101011 "OP_MCRXR"
+ attribute \enum_value_0101100 "OP_MCRXRX"
+ attribute \enum_value_0101101 "OP_MFCR"
+ attribute \enum_value_0101110 "OP_MFSPR"
+ attribute \enum_value_0101111 "OP_MOD"
+ attribute \enum_value_0110000 "OP_MTCRF"
+ attribute \enum_value_0110001 "OP_MTSPR"
+ attribute \enum_value_0110010 "OP_MUL_L64"
+ attribute \enum_value_0110011 "OP_MUL_H64"
+ attribute \enum_value_0110100 "OP_MUL_H32"
+ attribute \enum_value_0110101 "OP_OR"
+ attribute \enum_value_0110110 "OP_POPCNT"
+ attribute \enum_value_0110111 "OP_PRTY"
+ attribute \enum_value_0111000 "OP_RLC"
+ attribute \enum_value_0111001 "OP_RLCL"
+ attribute \enum_value_0111010 "OP_RLCR"
+ attribute \enum_value_0111011 "OP_SETB"
+ attribute \enum_value_0111100 "OP_SHL"
+ attribute \enum_value_0111101 "OP_SHR"
+ attribute \enum_value_0111110 "OP_SYNC"
+ attribute \enum_value_0111111 "OP_TRAP"
+ attribute \enum_value_1000011 "OP_XOR"
+ attribute \enum_value_1000100 "OP_SIM_CONFIG"
+ attribute \enum_value_1000101 "OP_CROP"
+ attribute \enum_value_1000110 "OP_RFID"
+ attribute \enum_value_1000111 "OP_MFMSR"
+ attribute \enum_value_1001000 "OP_MTMSRD"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 7 \mul_pipe3_op__insn_type$41
+ attribute \enum_base_type "Function"
+ attribute \enum_value_00000000000 "NONE"
+ attribute \enum_value_00000000010 "ALU"
+ attribute \enum_value_00000000100 "LDST"
+ attribute \enum_value_00000001000 "SHIFT_ROT"
+ attribute \enum_value_00000010000 "LOGICAL"
+ attribute \enum_value_00000100000 "BRANCH"
+ attribute \enum_value_00001000000 "CR"
+ attribute \enum_value_00010000000 "TRAP"
+ attribute \enum_value_00100000000 "MUL"
+ attribute \enum_value_01000000000 "DIV"
+ attribute \enum_value_10000000000 "SPR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 11 \mul_pipe3_op__fn_unit$42
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 \mul_pipe3_op__imm_data__imm$43
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \mul_pipe3_op__imm_data__imm_ok$44
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \mul_pipe3_op__rc__rc$45
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \mul_pipe3_op__rc__rc_ok$46
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \mul_pipe3_op__oe__oe$47
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \mul_pipe3_op__oe__oe_ok$48
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \mul_pipe3_op__invert_a$49
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \mul_pipe3_op__zero_a$50
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \mul_pipe3_op__invert_out$51
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \mul_pipe3_op__write_cr0$52
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \mul_pipe3_op__is_32bit$53
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \mul_pipe3_op__is_signed$54
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 \mul_pipe3_op__insn$55
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 64 \mul_pipe3_o$56
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 \mul_pipe3_o_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 4 \mul_pipe3_cr_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 \mul_pipe3_cr_a_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 2 \mul_pipe3_xer_ov
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 \mul_pipe3_xer_ov_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 \mul_pipe3_xer_so$57
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 \mul_pipe3_xer_so_ok
+ cell \mul_pipe3 \mul_pipe3
+ connect \rst \rst
+ connect \clk \clk
+ connect \p_valid_i \mul_pipe3_p_valid_i
+ connect \p_ready_o \mul_pipe3_p_ready_o
+ connect \muxid \mul_pipe3_muxid
+ connect \op__insn_type \mul_pipe3_op__insn_type
+ connect \op__fn_unit \mul_pipe3_op__fn_unit
+ connect \op__imm_data__imm \mul_pipe3_op__imm_data__imm
+ connect \op__imm_data__imm_ok \mul_pipe3_op__imm_data__imm_ok
+ connect \op__rc__rc \mul_pipe3_op__rc__rc
+ connect \op__rc__rc_ok \mul_pipe3_op__rc__rc_ok
+ connect \op__oe__oe \mul_pipe3_op__oe__oe
+ connect \op__oe__oe_ok \mul_pipe3_op__oe__oe_ok
+ connect \op__invert_a \mul_pipe3_op__invert_a
+ connect \op__zero_a \mul_pipe3_op__zero_a
+ connect \op__invert_out \mul_pipe3_op__invert_out
+ connect \op__write_cr0 \mul_pipe3_op__write_cr0
+ connect \op__is_32bit \mul_pipe3_op__is_32bit
+ connect \op__is_signed \mul_pipe3_op__is_signed
+ connect \op__insn \mul_pipe3_op__insn
+ connect \o \mul_pipe3_o
+ connect \xer_so \mul_pipe3_xer_so
+ connect \neg_res \mul_pipe3_neg_res
+ connect \neg_res32 \mul_pipe3_neg_res32
+ connect \n_valid_o \mul_pipe3_n_valid_o
+ connect \n_ready_i \mul_pipe3_n_ready_i
+ connect \muxid$1 \mul_pipe3_muxid$40
+ connect \op__insn_type$2 \mul_pipe3_op__insn_type$41
+ connect \op__fn_unit$3 \mul_pipe3_op__fn_unit$42
+ connect \op__imm_data__imm$4 \mul_pipe3_op__imm_data__imm$43
+ connect \op__imm_data__imm_ok$5 \mul_pipe3_op__imm_data__imm_ok$44
+ connect \op__rc__rc$6 \mul_pipe3_op__rc__rc$45
+ connect \op__rc__rc_ok$7 \mul_pipe3_op__rc__rc_ok$46
+ connect \op__oe__oe$8 \mul_pipe3_op__oe__oe$47
+ connect \op__oe__oe_ok$9 \mul_pipe3_op__oe__oe_ok$48
+ connect \op__invert_a$10 \mul_pipe3_op__invert_a$49
+ connect \op__zero_a$11 \mul_pipe3_op__zero_a$50
+ connect \op__invert_out$12 \mul_pipe3_op__invert_out$51
+ connect \op__write_cr0$13 \mul_pipe3_op__write_cr0$52
+ connect \op__is_32bit$14 \mul_pipe3_op__is_32bit$53
+ connect \op__is_signed$15 \mul_pipe3_op__is_signed$54
+ connect \op__insn$16 \mul_pipe3_op__insn$55
+ connect \o$17 \mul_pipe3_o$56
+ connect \o_ok \mul_pipe3_o_ok
+ connect \cr_a \mul_pipe3_cr_a
+ connect \cr_a_ok \mul_pipe3_cr_a_ok
+ connect \xer_ov \mul_pipe3_xer_ov
+ connect \xer_ov_ok \mul_pipe3_xer_ov_ok
+ connect \xer_so$18 \mul_pipe3_xer_so$57
+ connect \xer_so_ok \mul_pipe3_xer_so_ok
+ end
+ process $group_0
+ assign \mul_pipe2_p_valid_i 1'0
+ assign \mul_pipe2_p_valid_i \mul_pipe1_n_valid_o
+ sync init
+ end
+ process $group_1
+ assign \mul_pipe1_n_ready_i 1'0
+ assign \mul_pipe1_n_ready_i \mul_pipe2_p_ready_o
+ sync init
+ end
+ process $group_2
+ assign \mul_pipe2_muxid 2'00
+ assign \mul_pipe2_muxid \mul_pipe1_muxid
+ sync init
+ end
+ process $group_3
+ assign \mul_pipe2_op__insn_type 7'0000000
+ assign \mul_pipe2_op__fn_unit 11'00000000000
+ assign \mul_pipe2_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \mul_pipe2_op__imm_data__imm_ok 1'0
+ assign \mul_pipe2_op__rc__rc 1'0
+ assign \mul_pipe2_op__rc__rc_ok 1'0
+ assign \mul_pipe2_op__oe__oe 1'0
+ assign \mul_pipe2_op__oe__oe_ok 1'0
+ assign \mul_pipe2_op__invert_a 1'0
+ assign \mul_pipe2_op__zero_a 1'0
+ assign \mul_pipe2_op__invert_out 1'0
+ assign \mul_pipe2_op__write_cr0 1'0
+ assign \mul_pipe2_op__is_32bit 1'0
+ assign \mul_pipe2_op__is_signed 1'0
+ assign \mul_pipe2_op__insn 32'00000000000000000000000000000000
+ assign { \mul_pipe2_op__insn \mul_pipe2_op__is_signed \mul_pipe2_op__is_32bit \mul_pipe2_op__write_cr0 \mul_pipe2_op__invert_out \mul_pipe2_op__zero_a \mul_pipe2_op__invert_a { \mul_pipe2_op__oe__oe_ok \mul_pipe2_op__oe__oe } { \mul_pipe2_op__rc__rc_ok \mul_pipe2_op__rc__rc } { \mul_pipe2_op__imm_data__imm_ok \mul_pipe2_op__imm_data__imm } \mul_pipe2_op__fn_unit \mul_pipe2_op__insn_type } { \mul_pipe1_op__insn \mul_pipe1_op__is_signed \mul_pipe1_op__is_32bit \mul_pipe1_op__write_cr0 \mul_pipe1_op__invert_out \mul_pipe1_op__zero_a \mul_pipe1_op__invert_a { \mul_pipe1_op__oe__oe_ok \mul_pipe1_op__oe__oe } { \mul_pipe1_op__rc__rc_ok \mul_pipe1_op__rc__rc } { \mul_pipe1_op__imm_data__imm_ok \mul_pipe1_op__imm_data__imm } \mul_pipe1_op__fn_unit \mul_pipe1_op__insn_type }
+ sync init
+ end
+ process $group_18
+ assign \mul_pipe2_ra 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \mul_pipe2_ra \mul_pipe1_ra
+ sync init
+ end
+ process $group_19
+ assign \mul_pipe2_rb 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \mul_pipe2_rb \mul_pipe1_rb
+ sync init
+ end
+ process $group_20
+ assign \mul_pipe2_xer_so 1'0
+ assign \mul_pipe2_xer_so \mul_pipe1_xer_so
+ sync init
+ end
+ process $group_21
+ assign \mul_pipe2_neg_res 1'0
+ assign \mul_pipe2_neg_res \mul_pipe1_neg_res
+ sync init
+ end
+ process $group_22
+ assign \mul_pipe2_neg_res32 1'0
+ assign \mul_pipe2_neg_res32 \mul_pipe1_neg_res32
+ sync init
+ end
+ process $group_23
+ assign \mul_pipe3_p_valid_i 1'0
+ assign \mul_pipe3_p_valid_i \mul_pipe2_n_valid_o
+ sync init
+ end
+ process $group_24
+ assign \mul_pipe2_n_ready_i 1'0
+ assign \mul_pipe2_n_ready_i \mul_pipe3_p_ready_o
+ sync init
+ end
+ process $group_25
+ assign \mul_pipe3_muxid 2'00
+ assign \mul_pipe3_muxid \mul_pipe2_muxid$21
+ sync init
+ end
+ process $group_26
+ assign \mul_pipe3_op__insn_type 7'0000000
+ assign \mul_pipe3_op__fn_unit 11'00000000000
+ assign \mul_pipe3_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \mul_pipe3_op__imm_data__imm_ok 1'0
+ assign \mul_pipe3_op__rc__rc 1'0
+ assign \mul_pipe3_op__rc__rc_ok 1'0
+ assign \mul_pipe3_op__oe__oe 1'0
+ assign \mul_pipe3_op__oe__oe_ok 1'0
+ assign \mul_pipe3_op__invert_a 1'0
+ assign \mul_pipe3_op__zero_a 1'0
+ assign \mul_pipe3_op__invert_out 1'0
+ assign \mul_pipe3_op__write_cr0 1'0
+ assign \mul_pipe3_op__is_32bit 1'0
+ assign \mul_pipe3_op__is_signed 1'0
+ assign \mul_pipe3_op__insn 32'00000000000000000000000000000000
+ assign { \mul_pipe3_op__insn \mul_pipe3_op__is_signed \mul_pipe3_op__is_32bit \mul_pipe3_op__write_cr0 \mul_pipe3_op__invert_out \mul_pipe3_op__zero_a \mul_pipe3_op__invert_a { \mul_pipe3_op__oe__oe_ok \mul_pipe3_op__oe__oe } { \mul_pipe3_op__rc__rc_ok \mul_pipe3_op__rc__rc } { \mul_pipe3_op__imm_data__imm_ok \mul_pipe3_op__imm_data__imm } \mul_pipe3_op__fn_unit \mul_pipe3_op__insn_type } { \mul_pipe2_op__insn$36 \mul_pipe2_op__is_signed$35 \mul_pipe2_op__is_32bit$34 \mul_pipe2_op__write_cr0$33 \mul_pipe2_op__invert_out$32 \mul_pipe2_op__zero_a$31 \mul_pipe2_op__invert_a$30 { \mul_pipe2_op__oe__oe_ok$29 \mul_pipe2_op__oe__oe$28 } { \mul_pipe2_op__rc__rc_ok$27 \mul_pipe2_op__rc__rc$26 } { \mul_pipe2_op__imm_data__imm_ok$25 \mul_pipe2_op__imm_data__imm$24 } \mul_pipe2_op__fn_unit$23 \mul_pipe2_op__insn_type$22 }
+ sync init
+ end
+ process $group_41
+ assign \mul_pipe3_o 129'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
+ assign \mul_pipe3_o \mul_pipe2_o
+ sync init
+ end
+ process $group_42
+ assign \mul_pipe3_xer_so 1'0
+ assign \mul_pipe3_xer_so \mul_pipe2_xer_so$37
+ sync init
+ end
+ process $group_43
+ assign \mul_pipe3_neg_res 1'0
+ assign \mul_pipe3_neg_res \mul_pipe2_neg_res$38
+ sync init
+ end
+ process $group_44
+ assign \mul_pipe3_neg_res32 1'0
+ assign \mul_pipe3_neg_res32 \mul_pipe2_neg_res32$39
+ sync init
+ end
+ process $group_45
+ assign \mul_pipe1_p_valid_i 1'0
+ assign \mul_pipe1_p_valid_i \p_valid_i
+ sync init
+ end
+ process $group_46
+ assign \p_ready_o 1'0
+ assign \p_ready_o \mul_pipe1_p_ready_o
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+ wire width 2 \muxid
+ process $group_47
+ assign \mul_pipe1_muxid$2 2'00
+ assign \mul_pipe1_muxid$2 \muxid
+ sync init
+ end
+ process $group_48
+ assign \mul_pipe1_op__insn_type$3 7'0000000
+ assign \mul_pipe1_op__fn_unit$4 11'00000000000
+ assign \mul_pipe1_op__imm_data__imm$5 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \mul_pipe1_op__imm_data__imm_ok$6 1'0
+ assign \mul_pipe1_op__rc__rc$7 1'0
+ assign \mul_pipe1_op__rc__rc_ok$8 1'0
+ assign \mul_pipe1_op__oe__oe$9 1'0
+ assign \mul_pipe1_op__oe__oe_ok$10 1'0
+ assign \mul_pipe1_op__invert_a$11 1'0
+ assign \mul_pipe1_op__zero_a$12 1'0
+ assign \mul_pipe1_op__invert_out$13 1'0
+ assign \mul_pipe1_op__write_cr0$14 1'0
+ assign \mul_pipe1_op__is_32bit$15 1'0
+ assign \mul_pipe1_op__is_signed$16 1'0
+ assign \mul_pipe1_op__insn$17 32'00000000000000000000000000000000
+ assign { \mul_pipe1_op__insn$17 \mul_pipe1_op__is_signed$16 \mul_pipe1_op__is_32bit$15 \mul_pipe1_op__write_cr0$14 \mul_pipe1_op__invert_out$13 \mul_pipe1_op__zero_a$12 \mul_pipe1_op__invert_a$11 { \mul_pipe1_op__oe__oe_ok$10 \mul_pipe1_op__oe__oe$9 } { \mul_pipe1_op__rc__rc_ok$8 \mul_pipe1_op__rc__rc$7 } { \mul_pipe1_op__imm_data__imm_ok$6 \mul_pipe1_op__imm_data__imm$5 } \mul_pipe1_op__fn_unit$4 \mul_pipe1_op__insn_type$3 } { \op__insn \op__is_signed \op__is_32bit \op__write_cr0 \op__invert_out \op__zero_a \op__invert_a { \op__oe__oe_ok \op__oe__oe } { \op__rc__rc_ok \op__rc__rc } { \op__imm_data__imm_ok \op__imm_data__imm } \op__fn_unit \op__insn_type }
+ sync init
+ end
+ process $group_63
+ assign \mul_pipe1_ra$18 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \mul_pipe1_ra$18 \ra
+ sync init
+ end
+ process $group_64
+ assign \mul_pipe1_rb$19 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \mul_pipe1_rb$19 \rb
+ sync init
+ end
+ process $group_65
+ assign \mul_pipe1_xer_so$20 1'0
+ assign \mul_pipe1_xer_so$20 \xer_so$1
+ sync init
+ end
+ process $group_66
+ assign \n_valid_o 1'0
+ assign \n_valid_o \mul_pipe3_n_valid_o
+ sync init
+ end
+ process $group_67
+ assign \mul_pipe3_n_ready_i 1'0
+ assign \mul_pipe3_n_ready_i \n_ready_i
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+ wire width 2 \muxid$58
+ process $group_68
+ assign \muxid$58 2'00
+ assign \muxid$58 \mul_pipe3_muxid$40
+ sync init
+ end
+ attribute \enum_base_type "MicrOp"
+ attribute \enum_value_0000000 "OP_ILLEGAL"
+ attribute \enum_value_0000001 "OP_NOP"
+ attribute \enum_value_0000010 "OP_ADD"
+ attribute \enum_value_0000011 "OP_ADDPCIS"
+ attribute \enum_value_0000100 "OP_AND"
+ attribute \enum_value_0000101 "OP_ATTN"
+ attribute \enum_value_0000110 "OP_B"
+ attribute \enum_value_0000111 "OP_BC"
+ attribute \enum_value_0001000 "OP_BCREG"
+ attribute \enum_value_0001001 "OP_BPERM"
+ attribute \enum_value_0001010 "OP_CMP"
+ attribute \enum_value_0001011 "OP_CMPB"
+ attribute \enum_value_0001100 "OP_CMPEQB"
+ attribute \enum_value_0001101 "OP_CMPRB"
+ attribute \enum_value_0001110 "OP_CNTZ"
+ attribute \enum_value_0001111 "OP_CRAND"
+ attribute \enum_value_0010000 "OP_CRANDC"
+ attribute \enum_value_0010001 "OP_CREQV"
+ attribute \enum_value_0010010 "OP_CRNAND"
+ attribute \enum_value_0010011 "OP_CRNOR"
+ attribute \enum_value_0010100 "OP_CROR"
+ attribute \enum_value_0010101 "OP_CRORC"
+ attribute \enum_value_0010110 "OP_CRXOR"
+ attribute \enum_value_0010111 "OP_DARN"
+ attribute \enum_value_0011000 "OP_DCBF"
+ attribute \enum_value_0011001 "OP_DCBST"
+ attribute \enum_value_0011010 "OP_DCBT"
+ attribute \enum_value_0011011 "OP_DCBTST"
+ attribute \enum_value_0011100 "OP_DCBZ"
+ attribute \enum_value_0011101 "OP_DIV"
+ attribute \enum_value_0011110 "OP_DIVE"
+ attribute \enum_value_0011111 "OP_EXTS"
+ attribute \enum_value_0100000 "OP_EXTSWSLI"
+ attribute \enum_value_0100001 "OP_ICBI"
+ attribute \enum_value_0100010 "OP_ICBT"
+ attribute \enum_value_0100011 "OP_ISEL"
+ attribute \enum_value_0100100 "OP_ISYNC"
+ attribute \enum_value_0100101 "OP_LOAD"
+ attribute \enum_value_0100110 "OP_STORE"
+ attribute \enum_value_0100111 "OP_MADDHD"
+ attribute \enum_value_0101000 "OP_MADDHDU"
+ attribute \enum_value_0101001 "OP_MADDLD"
+ attribute \enum_value_0101010 "OP_MCRF"
+ attribute \enum_value_0101011 "OP_MCRXR"
+ attribute \enum_value_0101100 "OP_MCRXRX"
+ attribute \enum_value_0101101 "OP_MFCR"
+ attribute \enum_value_0101110 "OP_MFSPR"
+ attribute \enum_value_0101111 "OP_MOD"
+ attribute \enum_value_0110000 "OP_MTCRF"
+ attribute \enum_value_0110001 "OP_MTSPR"
+ attribute \enum_value_0110010 "OP_MUL_L64"
+ attribute \enum_value_0110011 "OP_MUL_H64"
+ attribute \enum_value_0110100 "OP_MUL_H32"
+ attribute \enum_value_0110101 "OP_OR"
+ attribute \enum_value_0110110 "OP_POPCNT"
+ attribute \enum_value_0110111 "OP_PRTY"
+ attribute \enum_value_0111000 "OP_RLC"
+ attribute \enum_value_0111001 "OP_RLCL"
+ attribute \enum_value_0111010 "OP_RLCR"
+ attribute \enum_value_0111011 "OP_SETB"
+ attribute \enum_value_0111100 "OP_SHL"
+ attribute \enum_value_0111101 "OP_SHR"
+ attribute \enum_value_0111110 "OP_SYNC"
+ attribute \enum_value_0111111 "OP_TRAP"
+ attribute \enum_value_1000011 "OP_XOR"
+ attribute \enum_value_1000100 "OP_SIM_CONFIG"
+ attribute \enum_value_1000101 "OP_CROP"
+ attribute \enum_value_1000110 "OP_RFID"
+ attribute \enum_value_1000111 "OP_MFMSR"
+ attribute \enum_value_1001000 "OP_MTMSRD"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 7 \op__insn_type$59
+ attribute \enum_base_type "Function"
+ attribute \enum_value_00000000000 "NONE"
+ attribute \enum_value_00000000010 "ALU"
+ attribute \enum_value_00000000100 "LDST"
+ attribute \enum_value_00000001000 "SHIFT_ROT"
+ attribute \enum_value_00000010000 "LOGICAL"
+ attribute \enum_value_00000100000 "BRANCH"
+ attribute \enum_value_00001000000 "CR"
+ attribute \enum_value_00010000000 "TRAP"
+ attribute \enum_value_00100000000 "MUL"
+ attribute \enum_value_01000000000 "DIV"
+ attribute \enum_value_10000000000 "SPR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 11 \op__fn_unit$60
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 \op__imm_data__imm$61
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__imm_data__imm_ok$62
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__rc__rc$63
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__rc__rc_ok$64
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__oe__oe$65
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__oe__oe_ok$66
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__invert_a$67
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__zero_a$68
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__invert_out$69
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__write_cr0$70
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__is_32bit$71
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__is_signed$72
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 \op__insn$73
+ process $group_69
+ assign \op__insn_type$59 7'0000000
+ assign \op__fn_unit$60 11'00000000000
+ assign \op__imm_data__imm$61 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \op__imm_data__imm_ok$62 1'0
+ assign \op__rc__rc$63 1'0
+ assign \op__rc__rc_ok$64 1'0
+ assign \op__oe__oe$65 1'0
+ assign \op__oe__oe_ok$66 1'0
+ assign \op__invert_a$67 1'0
+ assign \op__zero_a$68 1'0
+ assign \op__invert_out$69 1'0
+ assign \op__write_cr0$70 1'0
+ assign \op__is_32bit$71 1'0
+ assign \op__is_signed$72 1'0
+ assign \op__insn$73 32'00000000000000000000000000000000
+ assign { \op__insn$73 \op__is_signed$72 \op__is_32bit$71 \op__write_cr0$70 \op__invert_out$69 \op__zero_a$68 \op__invert_a$67 { \op__oe__oe_ok$66 \op__oe__oe$65 } { \op__rc__rc_ok$64 \op__rc__rc$63 } { \op__imm_data__imm_ok$62 \op__imm_data__imm$61 } \op__fn_unit$60 \op__insn_type$59 } { \mul_pipe3_op__insn$55 \mul_pipe3_op__is_signed$54 \mul_pipe3_op__is_32bit$53 \mul_pipe3_op__write_cr0$52 \mul_pipe3_op__invert_out$51 \mul_pipe3_op__zero_a$50 \mul_pipe3_op__invert_a$49 { \mul_pipe3_op__oe__oe_ok$48 \mul_pipe3_op__oe__oe$47 } { \mul_pipe3_op__rc__rc_ok$46 \mul_pipe3_op__rc__rc$45 } { \mul_pipe3_op__imm_data__imm_ok$44 \mul_pipe3_op__imm_data__imm$43 } \mul_pipe3_op__fn_unit$42 \mul_pipe3_op__insn_type$41 }
+ sync init
+ end
+ process $group_84
+ assign \o 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \o_ok 1'0
+ assign { \o_ok \o } { \mul_pipe3_o_ok \mul_pipe3_o$56 }
+ sync init
+ end
+ process $group_86
+ assign \cr_a 4'0000
+ assign \cr_a_ok 1'0
+ assign { \cr_a_ok \cr_a } { \mul_pipe3_cr_a_ok \mul_pipe3_cr_a }
+ sync init
+ end
+ process $group_88
+ assign \xer_ov 2'00
+ assign \xer_ov_ok 1'0
+ assign { \xer_ov_ok \xer_ov } { \mul_pipe3_xer_ov_ok \mul_pipe3_xer_ov }
+ sync init
+ end
+ process $group_90
+ assign \xer_so 1'0
+ assign \xer_so_ok 1'0
+ assign { \xer_so_ok \xer_so } { \mul_pipe3_xer_so_ok \mul_pipe3_xer_so$57 }
+ sync init
+ end
+ connect \muxid 2'00
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.src_l"
+module \src_l$80
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
+ wire width 1 input 0 \rst
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
+ wire width 1 input 1 \clk
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+ wire width 3 input 2 \s_src
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+ wire width 3 input 3 \r_src
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
+ wire width 3 output 4 \q_src
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
+ wire width 3 \q_int
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
+ wire width 3 \q_int$next
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+ wire width 3 $1
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+ cell $not $2
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 3
+ parameter \Y_WIDTH 3
+ connect \A \r_src
+ connect \Y $1
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+ wire width 3 $3
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+ cell $and $4
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 3
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 3
+ parameter \Y_WIDTH 3
+ connect \A \q_int
+ connect \B $1
+ connect \Y $3
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+ wire width 3 $5
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+ cell $or $6
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 3
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 3
+ parameter \Y_WIDTH 3
+ connect \A $3
+ connect \B \s_src
+ connect \Y $5
+ end
+ process $group_0
+ assign \q_int$next \q_int
+ assign \q_int$next $5
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+ switch \rst
+ case 1'1
+ assign \q_int$next 3'000
+ end
+ sync init
+ update \q_int 3'000
+ sync posedge \clk
+ update \q_int \q_int$next
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+ wire width 3 $7
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+ cell $not $8
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 3
+ parameter \Y_WIDTH 3
+ connect \A \r_src
+ connect \Y $7
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+ wire width 3 $9
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+ cell $and $10
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 3
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 3
+ parameter \Y_WIDTH 3
+ connect \A \q_int
+ connect \B $7
+ connect \Y $9
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+ wire width 3 $11
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+ cell $or $12
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 3
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 3
+ parameter \Y_WIDTH 3
+ connect \A $9
+ connect \B \s_src
+ connect \Y $11
+ end
+ process $group_1
+ assign \q_src 3'000
+ assign \q_src $11
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
+ wire width 3 \qn_src
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
+ wire width 3 $13
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
+ cell $not $14
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 3
+ parameter \Y_WIDTH 3
+ connect \A \q_src
+ connect \Y $13
+ end
+ process $group_2
+ assign \qn_src 3'000
+ assign \qn_src $13
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62"
+ wire width 3 \qlq_src
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
+ wire width 3 $15
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
+ cell $or $16
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 3
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 3
+ parameter \Y_WIDTH 3
+ connect \A \q_src
+ connect \B \q_int
+ connect \Y $15
+ end
+ process $group_3
+ assign \qlq_src 3'000
+ assign \qlq_src $15
+ sync init
+ end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.opc_l"
+module \opc_l$81
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
+ wire width 1 input 0 \rst
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
+ wire width 1 input 1 \clk
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+ wire width 1 input 2 \s_opc
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+ wire width 1 input 3 \r_opc
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
+ wire width 1 output 4 \q_opc
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
+ wire width 1 \q_int
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
+ wire width 1 \q_int$next
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+ wire width 1 $1
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+ cell $not $2
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \r_opc
+ connect \Y $1
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+ wire width 1 $3
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+ cell $and $4
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \q_int
+ connect \B $1
+ connect \Y $3
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+ wire width 1 $5
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+ cell $or $6
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A $3
+ connect \B \s_opc
+ connect \Y $5
+ end
+ process $group_0
+ assign \q_int$next \q_int
+ assign \q_int$next $5
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+ switch \rst
+ case 1'1
+ assign \q_int$next 1'0
+ end
+ sync init
+ update \q_int 1'0
+ sync posedge \clk
+ update \q_int \q_int$next
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+ wire width 1 $7
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+ cell $not $8
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \r_opc
+ connect \Y $7
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+ wire width 1 $9
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+ cell $and $10
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \q_int
+ connect \B $7
+ connect \Y $9
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+ wire width 1 $11
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+ cell $or $12
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A $9
+ connect \B \s_opc
+ connect \Y $11
+ end
+ process $group_1
+ assign \q_opc 1'0
+ assign \q_opc $11
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
+ wire width 1 \qn_opc
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
+ wire width 1 $13
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
+ cell $not $14
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \q_opc
+ connect \Y $13
+ end
+ process $group_2
+ assign \qn_opc 1'0
+ assign \qn_opc $13
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62"
+ wire width 1 \qlq_opc
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
+ wire width 1 $15
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
+ cell $or $16
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \q_opc
+ connect \B \q_int
+ connect \Y $15
+ end
+ process $group_3
+ assign \qlq_opc 1'0
+ assign \qlq_opc $15
+ sync init
+ end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.req_l"
+module \req_l$82
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
+ wire width 1 input 0 \rst
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
+ wire width 1 input 1 \clk
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
+ wire width 4 output 2 \q_req
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+ wire width 4 input 3 \s_req
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+ wire width 4 input 4 \r_req
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
+ wire width 4 \q_int
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
+ wire width 4 \q_int$next
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+ wire width 4 $1
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+ cell $not $2
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 4
+ parameter \Y_WIDTH 4
+ connect \A \r_req
+ connect \Y $1
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+ wire width 4 $3
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+ cell $and $4
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 4
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 4
+ parameter \Y_WIDTH 4
+ connect \A \q_int
+ connect \B $1
+ connect \Y $3
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+ wire width 4 $5
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+ cell $or $6
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 4
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 4
+ parameter \Y_WIDTH 4
+ connect \A $3
+ connect \B \s_req
+ connect \Y $5
+ end
+ process $group_0
+ assign \q_int$next \q_int
+ assign \q_int$next $5
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+ switch \rst
+ case 1'1
+ assign \q_int$next 4'0000
+ end
+ sync init
+ update \q_int 4'0000
+ sync posedge \clk
+ update \q_int \q_int$next
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+ wire width 4 $7
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+ cell $not $8
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 4
+ parameter \Y_WIDTH 4
+ connect \A \r_req
+ connect \Y $7
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+ wire width 4 $9
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+ cell $and $10
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 4
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 4
+ parameter \Y_WIDTH 4
+ connect \A \q_int
+ connect \B $7
+ connect \Y $9
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+ wire width 4 $11
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+ cell $or $12
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 4
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 4
+ parameter \Y_WIDTH 4
+ connect \A $9
+ connect \B \s_req
+ connect \Y $11
+ end
+ process $group_1
+ assign \q_req 4'0000
+ assign \q_req $11
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
+ wire width 4 \qn_req
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
+ wire width 4 $13
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
+ cell $not $14
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 4
+ parameter \Y_WIDTH 4
+ connect \A \q_req
+ connect \Y $13
+ end
+ process $group_2
+ assign \qn_req 4'0000
+ assign \qn_req $13
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62"
+ wire width 4 \qlq_req
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
+ wire width 4 $15
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
+ cell $or $16
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 4
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 4
+ parameter \Y_WIDTH 4
+ connect \A \q_req
+ connect \B \q_int
+ connect \Y $15
+ end
+ process $group_3
+ assign \qlq_req 4'0000
+ assign \qlq_req $15
+ sync init
+ end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.rst_l"
+module \rst_l$83
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
+ wire width 1 input 0 \rst
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
+ wire width 1 input 1 \clk
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+ wire width 1 input 2 \s_rst
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+ wire width 1 input 3 \r_rst
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
+ wire width 1 \q_int
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
+ wire width 1 \q_int$next
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+ wire width 1 $1
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+ cell $not $2
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \r_rst
+ connect \Y $1
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+ wire width 1 $3
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+ cell $and $4
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \q_int
+ connect \B $1
+ connect \Y $3
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+ wire width 1 $5
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+ cell $or $6
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A $3
+ connect \B \s_rst
+ connect \Y $5
+ end
+ process $group_0
+ assign \q_int$next \q_int
+ assign \q_int$next $5
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+ switch \rst
+ case 1'1
+ assign \q_int$next 1'0
+ end
+ sync init
+ update \q_int 1'0
+ sync posedge \clk
+ update \q_int \q_int$next
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
+ wire width 1 \q_rst
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+ wire width 1 $7
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+ cell $not $8
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \r_rst
+ connect \Y $7
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+ wire width 1 $9
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+ cell $and $10
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \q_int
+ connect \B $7
+ connect \Y $9
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+ wire width 1 $11
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+ cell $or $12
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A $9
+ connect \B \s_rst
+ connect \Y $11
+ end
+ process $group_1
+ assign \q_rst 1'0
+ assign \q_rst $11
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
+ wire width 1 \qn_rst
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
+ wire width 1 $13
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
+ cell $not $14
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \q_rst
+ connect \Y $13
+ end
+ process $group_2
+ assign \qn_rst 1'0
+ assign \qn_rst $13
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62"
+ wire width 1 \qlq_rst
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
+ wire width 1 $15
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
+ cell $or $16
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \q_rst
+ connect \B \q_int
+ connect \Y $15
+ end
+ process $group_3
+ assign \qlq_rst 1'0
+ assign \qlq_rst $15
+ sync init
+ end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.rok_l"
+module \rok_l$84
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
+ wire width 1 input 0 \rst
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
+ wire width 1 input 1 \clk
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
+ wire width 1 output 2 \q_rdok
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+ wire width 1 input 3 \s_rdok
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+ wire width 1 input 4 \r_rdok
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
+ wire width 1 \q_int
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
+ wire width 1 \q_int$next
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+ wire width 1 $1
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+ cell $not $2
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \r_rdok
+ connect \Y $1
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+ wire width 1 $3
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+ cell $and $4
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \q_int
+ connect \B $1
+ connect \Y $3
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+ wire width 1 $5
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+ cell $or $6
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A $3
+ connect \B \s_rdok
+ connect \Y $5
+ end
+ process $group_0
+ assign \q_int$next \q_int
+ assign \q_int$next $5
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+ switch \rst
+ case 1'1
+ assign \q_int$next 1'0
+ end
+ sync init
+ update \q_int 1'0
+ sync posedge \clk
+ update \q_int \q_int$next
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+ wire width 1 $7
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+ cell $not $8
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \r_rdok
+ connect \Y $7
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+ wire width 1 $9
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+ cell $and $10
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \q_int
+ connect \B $7
+ connect \Y $9
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+ wire width 1 $11
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+ cell $or $12
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A $9
+ connect \B \s_rdok
+ connect \Y $11
+ end
+ process $group_1
+ assign \q_rdok 1'0
+ assign \q_rdok $11
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
+ wire width 1 \qn_rdok
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
+ wire width 1 $13
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
+ cell $not $14
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \q_rdok
+ connect \Y $13
+ end
+ process $group_2
+ assign \qn_rdok 1'0
+ assign \qn_rdok $13
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62"
+ wire width 1 \qlq_rdok
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
+ wire width 1 $15
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
+ cell $or $16
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \q_rdok
+ connect \B \q_int
+ connect \Y $15
+ end
+ process $group_3
+ assign \qlq_rdok 1'0
+ assign \qlq_rdok $15
+ sync init
+ end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alui_l"
+module \alui_l$85
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
+ wire width 1 input 0 \rst
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
+ wire width 1 input 1 \clk
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
+ wire width 1 output 2 \q_alui
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+ wire width 1 input 3 \r_alui
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+ wire width 1 input 4 \s_alui
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
+ wire width 1 \q_int
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
+ wire width 1 \q_int$next
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+ wire width 1 $1
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+ cell $not $2
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \r_alui
+ connect \Y $1
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+ wire width 1 $3
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+ cell $and $4
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \q_int
+ connect \B $1
+ connect \Y $3
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+ wire width 1 $5
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+ cell $or $6
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A $3
+ connect \B \s_alui
+ connect \Y $5
+ end
+ process $group_0
+ assign \q_int$next \q_int
+ assign \q_int$next $5
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+ switch \rst
+ case 1'1
+ assign \q_int$next 1'0
+ end
+ sync init
+ update \q_int 1'0
+ sync posedge \clk
+ update \q_int \q_int$next
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+ wire width 1 $7
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+ cell $not $8
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \r_alui
+ connect \Y $7
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+ wire width 1 $9
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+ cell $and $10
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \q_int
+ connect \B $7
+ connect \Y $9
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+ wire width 1 $11
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+ cell $or $12
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A $9
+ connect \B \s_alui
+ connect \Y $11
+ end
+ process $group_1
+ assign \q_alui 1'0
+ assign \q_alui $11
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
+ wire width 1 \qn_alui
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
+ wire width 1 $13
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
+ cell $not $14
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \q_alui
+ connect \Y $13
+ end
+ process $group_2
+ assign \qn_alui 1'0
+ assign \qn_alui $13
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62"
+ wire width 1 \qlq_alui
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
+ wire width 1 $15
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
+ cell $or $16
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \q_alui
+ connect \B \q_int
+ connect \Y $15
+ end
+ process $group_3
+ assign \qlq_alui 1'0
+ assign \qlq_alui $15
+ sync init
+ end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_l"
+module \alu_l$86
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
+ wire width 1 input 0 \rst
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
+ wire width 1 input 1 \clk
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
+ wire width 1 output 2 \q_alu
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+ wire width 1 input 3 \r_alu
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+ wire width 1 input 4 \s_alu
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
+ wire width 1 \q_int
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
+ wire width 1 \q_int$next
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+ wire width 1 $1
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+ cell $not $2
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \r_alu
+ connect \Y $1
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+ wire width 1 $3
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+ cell $and $4
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \q_int
+ connect \B $1
+ connect \Y $3
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+ wire width 1 $5
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+ cell $or $6
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A $3
+ connect \B \s_alu
+ connect \Y $5
+ end
+ process $group_0
+ assign \q_int$next \q_int
+ assign \q_int$next $5
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+ switch \rst
+ case 1'1
+ assign \q_int$next 1'0
+ end
+ sync init
+ update \q_int 1'0
+ sync posedge \clk
+ update \q_int \q_int$next
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+ wire width 1 $7
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+ cell $not $8
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \r_alu
+ connect \Y $7
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+ wire width 1 $9
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+ cell $and $10
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \q_int
+ connect \B $7
+ connect \Y $9
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+ wire width 1 $11
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+ cell $or $12
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A $9
+ connect \B \s_alu
+ connect \Y $11
+ end
+ process $group_1
+ assign \q_alu 1'0
+ assign \q_alu $11
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
+ wire width 1 \qn_alu
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
+ wire width 1 $13
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
+ cell $not $14
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \q_alu
+ connect \Y $13
+ end
+ process $group_2
+ assign \qn_alu 1'0
+ assign \qn_alu $13
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62"
+ wire width 1 \qlq_alu
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
+ wire width 1 $15
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
+ cell $or $16
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \q_alu
+ connect \B \q_int
+ connect \Y $15
+ end
+ process $group_3
+ assign \qlq_alu 1'0
+ assign \qlq_alu $15
+ sync init
+ end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.fus.mul0"
+module \mul0
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
+ wire width 1 input 0 \rst
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
+ wire width 1 input 1 \clk
+ attribute \enum_base_type "MicrOp"
+ attribute \enum_value_0000000 "OP_ILLEGAL"
+ attribute \enum_value_0000001 "OP_NOP"
+ attribute \enum_value_0000010 "OP_ADD"
+ attribute \enum_value_0000011 "OP_ADDPCIS"
+ attribute \enum_value_0000100 "OP_AND"
+ attribute \enum_value_0000101 "OP_ATTN"
+ attribute \enum_value_0000110 "OP_B"
+ attribute \enum_value_0000111 "OP_BC"
+ attribute \enum_value_0001000 "OP_BCREG"
+ attribute \enum_value_0001001 "OP_BPERM"
+ attribute \enum_value_0001010 "OP_CMP"
+ attribute \enum_value_0001011 "OP_CMPB"
+ attribute \enum_value_0001100 "OP_CMPEQB"
+ attribute \enum_value_0001101 "OP_CMPRB"
+ attribute \enum_value_0001110 "OP_CNTZ"
+ attribute \enum_value_0001111 "OP_CRAND"
+ attribute \enum_value_0010000 "OP_CRANDC"
+ attribute \enum_value_0010001 "OP_CREQV"
+ attribute \enum_value_0010010 "OP_CRNAND"
+ attribute \enum_value_0010011 "OP_CRNOR"
+ attribute \enum_value_0010100 "OP_CROR"
+ attribute \enum_value_0010101 "OP_CRORC"
+ attribute \enum_value_0010110 "OP_CRXOR"
+ attribute \enum_value_0010111 "OP_DARN"
+ attribute \enum_value_0011000 "OP_DCBF"
+ attribute \enum_value_0011001 "OP_DCBST"
+ attribute \enum_value_0011010 "OP_DCBT"
+ attribute \enum_value_0011011 "OP_DCBTST"
+ attribute \enum_value_0011100 "OP_DCBZ"
+ attribute \enum_value_0011101 "OP_DIV"
+ attribute \enum_value_0011110 "OP_DIVE"
+ attribute \enum_value_0011111 "OP_EXTS"
+ attribute \enum_value_0100000 "OP_EXTSWSLI"
+ attribute \enum_value_0100001 "OP_ICBI"
+ attribute \enum_value_0100010 "OP_ICBT"
+ attribute \enum_value_0100011 "OP_ISEL"
+ attribute \enum_value_0100100 "OP_ISYNC"
+ attribute \enum_value_0100101 "OP_LOAD"
+ attribute \enum_value_0100110 "OP_STORE"
+ attribute \enum_value_0100111 "OP_MADDHD"
+ attribute \enum_value_0101000 "OP_MADDHDU"
+ attribute \enum_value_0101001 "OP_MADDLD"
+ attribute \enum_value_0101010 "OP_MCRF"
+ attribute \enum_value_0101011 "OP_MCRXR"
+ attribute \enum_value_0101100 "OP_MCRXRX"
+ attribute \enum_value_0101101 "OP_MFCR"
+ attribute \enum_value_0101110 "OP_MFSPR"
+ attribute \enum_value_0101111 "OP_MOD"
+ attribute \enum_value_0110000 "OP_MTCRF"
+ attribute \enum_value_0110001 "OP_MTSPR"
+ attribute \enum_value_0110010 "OP_MUL_L64"
+ attribute \enum_value_0110011 "OP_MUL_H64"
+ attribute \enum_value_0110100 "OP_MUL_H32"
+ attribute \enum_value_0110101 "OP_OR"
+ attribute \enum_value_0110110 "OP_POPCNT"
+ attribute \enum_value_0110111 "OP_PRTY"
+ attribute \enum_value_0111000 "OP_RLC"
+ attribute \enum_value_0111001 "OP_RLCL"
+ attribute \enum_value_0111010 "OP_RLCR"
+ attribute \enum_value_0111011 "OP_SETB"
+ attribute \enum_value_0111100 "OP_SHL"
+ attribute \enum_value_0111101 "OP_SHR"
+ attribute \enum_value_0111110 "OP_SYNC"
+ attribute \enum_value_0111111 "OP_TRAP"
+ attribute \enum_value_1000011 "OP_XOR"
+ attribute \enum_value_1000100 "OP_SIM_CONFIG"
+ attribute \enum_value_1000101 "OP_CROP"
+ attribute \enum_value_1000110 "OP_RFID"
+ attribute \enum_value_1000111 "OP_MFMSR"
+ attribute \enum_value_1001000 "OP_MTMSRD"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 7 input 2 \oper_i__insn_type
+ attribute \enum_base_type "Function"
+ attribute \enum_value_00000000000 "NONE"
+ attribute \enum_value_00000000010 "ALU"
+ attribute \enum_value_00000000100 "LDST"
+ attribute \enum_value_00000001000 "SHIFT_ROT"
+ attribute \enum_value_00000010000 "LOGICAL"
+ attribute \enum_value_00000100000 "BRANCH"
+ attribute \enum_value_00001000000 "CR"
+ attribute \enum_value_00010000000 "TRAP"
+ attribute \enum_value_00100000000 "MUL"
+ attribute \enum_value_01000000000 "DIV"
+ attribute \enum_value_10000000000 "SPR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 11 input 3 \oper_i__fn_unit
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 input 4 \oper_i__imm_data__imm
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 5 \oper_i__imm_data__imm_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 6 \oper_i__rc__rc
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 7 \oper_i__rc__rc_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 8 \oper_i__oe__oe
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 9 \oper_i__oe__oe_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 10 \oper_i__invert_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 11 \oper_i__zero_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 12 \oper_i__invert_out
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 13 \oper_i__write_cr0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 14 \oper_i__is_32bit
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 15 \oper_i__is_signed
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 input 16 \oper_i__insn
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94"
+ wire width 1 input 17 \issue_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
+ wire width 1 output 18 \busy_o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:92"
+ wire width 3 input 19 \rdmaskn
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+ wire width 3 output 20 \rd__rel
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+ wire width 3 input 21 \rd__go
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
+ wire width 64 input 22 \src1_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
+ wire width 64 input 23 \src2_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
+ wire width 1 input 24 \src3_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 25 \o_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+ wire width 4 output 26 \wr__rel
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+ wire width 4 input 27 \wr__go
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
+ wire width 64 output 28 \dest1_o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 29 \cr_a_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
+ wire width 4 output 30 \dest2_o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 31 \xer_ov_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
+ wire width 2 output 32 \dest3_o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 33 \xer_so_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
+ wire width 1 output 34 \dest4_o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96"
+ wire width 1 input 35 \go_die_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
+ wire width 1 input 36 \shadown_i
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
+ wire width 1 \alu_mul0_n_valid_o
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
+ wire width 1 \alu_mul0_n_ready_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 64 \alu_mul0_o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 4 \alu_mul0_cr_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 2 \alu_mul0_xer_ov
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 \alu_mul0_xer_so
+ attribute \enum_base_type "MicrOp"
+ attribute \enum_value_0000000 "OP_ILLEGAL"
+ attribute \enum_value_0000001 "OP_NOP"
+ attribute \enum_value_0000010 "OP_ADD"
+ attribute \enum_value_0000011 "OP_ADDPCIS"
+ attribute \enum_value_0000100 "OP_AND"
+ attribute \enum_value_0000101 "OP_ATTN"
+ attribute \enum_value_0000110 "OP_B"
+ attribute \enum_value_0000111 "OP_BC"
+ attribute \enum_value_0001000 "OP_BCREG"
+ attribute \enum_value_0001001 "OP_BPERM"
+ attribute \enum_value_0001010 "OP_CMP"
+ attribute \enum_value_0001011 "OP_CMPB"
+ attribute \enum_value_0001100 "OP_CMPEQB"
+ attribute \enum_value_0001101 "OP_CMPRB"
+ attribute \enum_value_0001110 "OP_CNTZ"
+ attribute \enum_value_0001111 "OP_CRAND"
+ attribute \enum_value_0010000 "OP_CRANDC"
+ attribute \enum_value_0010001 "OP_CREQV"
+ attribute \enum_value_0010010 "OP_CRNAND"
+ attribute \enum_value_0010011 "OP_CRNOR"
+ attribute \enum_value_0010100 "OP_CROR"
+ attribute \enum_value_0010101 "OP_CRORC"
+ attribute \enum_value_0010110 "OP_CRXOR"
+ attribute \enum_value_0010111 "OP_DARN"
+ attribute \enum_value_0011000 "OP_DCBF"
+ attribute \enum_value_0011001 "OP_DCBST"
+ attribute \enum_value_0011010 "OP_DCBT"
+ attribute \enum_value_0011011 "OP_DCBTST"
+ attribute \enum_value_0011100 "OP_DCBZ"
+ attribute \enum_value_0011101 "OP_DIV"
+ attribute \enum_value_0011110 "OP_DIVE"
+ attribute \enum_value_0011111 "OP_EXTS"
+ attribute \enum_value_0100000 "OP_EXTSWSLI"
+ attribute \enum_value_0100001 "OP_ICBI"
+ attribute \enum_value_0100010 "OP_ICBT"
+ attribute \enum_value_0100011 "OP_ISEL"
+ attribute \enum_value_0100100 "OP_ISYNC"
+ attribute \enum_value_0100101 "OP_LOAD"
+ attribute \enum_value_0100110 "OP_STORE"
+ attribute \enum_value_0100111 "OP_MADDHD"
+ attribute \enum_value_0101000 "OP_MADDHDU"
+ attribute \enum_value_0101001 "OP_MADDLD"
+ attribute \enum_value_0101010 "OP_MCRF"
+ attribute \enum_value_0101011 "OP_MCRXR"
+ attribute \enum_value_0101100 "OP_MCRXRX"
+ attribute \enum_value_0101101 "OP_MFCR"
+ attribute \enum_value_0101110 "OP_MFSPR"
+ attribute \enum_value_0101111 "OP_MOD"
+ attribute \enum_value_0110000 "OP_MTCRF"
+ attribute \enum_value_0110001 "OP_MTSPR"
+ attribute \enum_value_0110010 "OP_MUL_L64"
+ attribute \enum_value_0110011 "OP_MUL_H64"
+ attribute \enum_value_0110100 "OP_MUL_H32"
+ attribute \enum_value_0110101 "OP_OR"
+ attribute \enum_value_0110110 "OP_POPCNT"
+ attribute \enum_value_0110111 "OP_PRTY"
+ attribute \enum_value_0111000 "OP_RLC"
+ attribute \enum_value_0111001 "OP_RLCL"
+ attribute \enum_value_0111010 "OP_RLCR"
+ attribute \enum_value_0111011 "OP_SETB"
+ attribute \enum_value_0111100 "OP_SHL"
+ attribute \enum_value_0111101 "OP_SHR"
+ attribute \enum_value_0111110 "OP_SYNC"
+ attribute \enum_value_0111111 "OP_TRAP"
+ attribute \enum_value_1000011 "OP_XOR"
+ attribute \enum_value_1000100 "OP_SIM_CONFIG"
+ attribute \enum_value_1000101 "OP_CROP"
+ attribute \enum_value_1000110 "OP_RFID"
+ attribute \enum_value_1000111 "OP_MFMSR"
+ attribute \enum_value_1001000 "OP_MTMSRD"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 7 \alu_mul0_op__insn_type
+ attribute \enum_base_type "Function"
+ attribute \enum_value_00000000000 "NONE"
+ attribute \enum_value_00000000010 "ALU"
+ attribute \enum_value_00000000100 "LDST"
+ attribute \enum_value_00000001000 "SHIFT_ROT"
+ attribute \enum_value_00000010000 "LOGICAL"
+ attribute \enum_value_00000100000 "BRANCH"
+ attribute \enum_value_00001000000 "CR"
+ attribute \enum_value_00010000000 "TRAP"
+ attribute \enum_value_00100000000 "MUL"
+ attribute \enum_value_01000000000 "DIV"
+ attribute \enum_value_10000000000 "SPR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 11 \alu_mul0_op__fn_unit
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 \alu_mul0_op__imm_data__imm
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \alu_mul0_op__imm_data__imm_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \alu_mul0_op__rc__rc
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \alu_mul0_op__rc__rc_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \alu_mul0_op__oe__oe
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \alu_mul0_op__oe__oe_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \alu_mul0_op__invert_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \alu_mul0_op__zero_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \alu_mul0_op__invert_out
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \alu_mul0_op__write_cr0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \alu_mul0_op__is_32bit
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \alu_mul0_op__is_signed
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 \alu_mul0_op__insn
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 64 \alu_mul0_ra
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 64 \alu_mul0_rb
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 1 \alu_mul0_xer_so$1
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153"
+ wire width 1 \alu_mul0_p_valid_i
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154"
+ wire width 1 \alu_mul0_p_ready_o
+ cell \alu_mul0 \alu_mul0
+ connect \rst \rst
+ connect \clk \clk
+ connect \o_ok \o_ok
+ connect \cr_a_ok \cr_a_ok
+ connect \xer_ov_ok \xer_ov_ok
+ connect \xer_so_ok \xer_so_ok
+ connect \n_valid_o \alu_mul0_n_valid_o
+ connect \n_ready_i \alu_mul0_n_ready_i
+ connect \o \alu_mul0_o
+ connect \cr_a \alu_mul0_cr_a
+ connect \xer_ov \alu_mul0_xer_ov
+ connect \xer_so \alu_mul0_xer_so
+ connect \op__insn_type \alu_mul0_op__insn_type
+ connect \op__fn_unit \alu_mul0_op__fn_unit
+ connect \op__imm_data__imm \alu_mul0_op__imm_data__imm
+ connect \op__imm_data__imm_ok \alu_mul0_op__imm_data__imm_ok
+ connect \op__rc__rc \alu_mul0_op__rc__rc
+ connect \op__rc__rc_ok \alu_mul0_op__rc__rc_ok
+ connect \op__oe__oe \alu_mul0_op__oe__oe
+ connect \op__oe__oe_ok \alu_mul0_op__oe__oe_ok
+ connect \op__invert_a \alu_mul0_op__invert_a
+ connect \op__zero_a \alu_mul0_op__zero_a
+ connect \op__invert_out \alu_mul0_op__invert_out
+ connect \op__write_cr0 \alu_mul0_op__write_cr0
+ connect \op__is_32bit \alu_mul0_op__is_32bit
+ connect \op__is_signed \alu_mul0_op__is_signed
+ connect \op__insn \alu_mul0_op__insn
+ connect \ra \alu_mul0_ra
+ connect \rb \alu_mul0_rb
+ connect \xer_so$1 \alu_mul0_xer_so$1
+ connect \p_valid_i \alu_mul0_p_valid_i
+ connect \p_ready_o \alu_mul0_p_ready_o
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+ wire width 3 \src_l_s_src
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+ wire width 3 \src_l_s_src$next
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+ wire width 3 \src_l_r_src
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+ wire width 3 \src_l_r_src$next
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
+ wire width 3 \src_l_q_src
+ cell \src_l$80 \src_l
+ connect \rst \rst
+ connect \clk \clk
+ connect \s_src \src_l_s_src
+ connect \r_src \src_l_r_src
+ connect \q_src \src_l_q_src
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+ wire width 1 \opc_l_s_opc
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+ wire width 1 \opc_l_s_opc$next
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+ wire width 1 \opc_l_r_opc
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+ wire width 1 \opc_l_r_opc$next
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
+ wire width 1 \opc_l_q_opc
+ cell \opc_l$81 \opc_l
+ connect \rst \rst
+ connect \clk \clk
+ connect \s_opc \opc_l_s_opc
+ connect \r_opc \opc_l_r_opc
+ connect \q_opc \opc_l_q_opc
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
+ wire width 4 \req_l_q_req
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+ wire width 4 \req_l_s_req
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+ wire width 4 \req_l_r_req
+ cell \req_l$82 \req_l
+ connect \rst \rst
+ connect \clk \clk
+ connect \q_req \req_l_q_req
+ connect \s_req \req_l_s_req
+ connect \r_req \req_l_r_req
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+ wire width 1 \rst_l_s_rst
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+ wire width 1 \rst_l_r_rst
+ cell \rst_l$83 \rst_l
+ connect \rst \rst
+ connect \clk \clk
+ connect \s_rst \rst_l_s_rst
+ connect \r_rst \rst_l_r_rst
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
+ wire width 1 \rok_l_q_rdok
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+ wire width 1 \rok_l_s_rdok
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+ wire width 1 \rok_l_r_rdok
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+ wire width 1 \rok_l_r_rdok$next
+ cell \rok_l$84 \rok_l
+ connect \rst \rst
+ connect \clk \clk
+ connect \q_rdok \rok_l_q_rdok
+ connect \s_rdok \rok_l_s_rdok
+ connect \r_rdok \rok_l_r_rdok
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
+ wire width 1 \alui_l_q_alui
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+ wire width 1 \alui_l_r_alui
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+ wire width 1 \alui_l_r_alui$next
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+ wire width 1 \alui_l_s_alui
+ cell \alui_l$85 \alui_l
+ connect \rst \rst
+ connect \clk \clk
+ connect \q_alui \alui_l_q_alui
+ connect \r_alui \alui_l_r_alui
+ connect \s_alui \alui_l_s_alui
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
+ wire width 1 \alu_l_q_alu
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+ wire width 1 \alu_l_r_alu
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+ wire width 1 \alu_l_r_alu$next
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+ wire width 1 \alu_l_s_alu
+ cell \alu_l$86 \alu_l
+ connect \rst \rst
+ connect \clk \clk
+ connect \q_alu \alu_l_q_alu
+ connect \r_alu \alu_l_r_alu
+ connect \s_alu \alu_l_s_alu
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:178"
+ wire width 1 \all_rd
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179"
+ wire width 1 $2
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179"
+ cell $and $3
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \busy_o
+ connect \B \rok_l_q_rdok
+ connect \Y $2
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180"
+ wire width 1 $4
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180"
+ wire width 3 $5
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180"
+ cell $not $6
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 3
+ parameter \Y_WIDTH 3
+ connect \A \rd__rel
+ connect \Y $5
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180"
+ wire width 3 $7
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180"
+ cell $or $8
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 3
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 3
+ parameter \Y_WIDTH 3
+ connect \A $5
+ connect \B \rd__go
+ connect \Y $7
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180"
+ cell $reduce_and $9
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 3
+ parameter \Y_WIDTH 1
+ connect \A $7
+ connect \Y $4
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180"
+ wire width 1 $10
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180"
+ cell $and $11
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A $2
+ connect \B $4
+ connect \Y $10
+ end
+ process $group_0
+ assign \all_rd 1'0
+ assign \all_rd $10
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:183"
+ wire width 1 \all_rd_dly
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:183"
+ wire width 1 \all_rd_dly$next
+ process $group_1
+ assign \all_rd_dly$next \all_rd_dly
+ assign \all_rd_dly$next \all_rd
+ sync init
+ update \all_rd_dly 1'0
+ sync posedge \clk
+ update \all_rd_dly \all_rd_dly$next
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:184"
+ wire width 1 \all_rd_pulse
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:186"
+ wire width 1 $12
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:186"
+ cell $not $13
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \all_rd_dly
+ connect \Y $12
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:186"
+ wire width 1 $14
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:186"
+ cell $and $15
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \all_rd
+ connect \B $12
+ connect \Y $14
+ end
+ process $group_2
+ assign \all_rd_pulse 1'0
+ assign \all_rd_pulse $14
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189"
+ wire width 1 \alu_done
+ process $group_3
+ assign \alu_done 1'0
+ assign \alu_done \alu_mul0_n_valid_o
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:190"
+ wire width 1 \alu_done_dly
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:190"
+ wire width 1 \alu_done_dly$next
+ process $group_4
+ assign \alu_done_dly$next \alu_done_dly
+ assign \alu_done_dly$next \alu_done
+ sync init
+ update \alu_done_dly 1'0
+ sync posedge \clk
+ update \alu_done_dly \alu_done_dly$next
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:191"
+ wire width 1 \alu_pulse
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:195"
+ wire width 1 $16
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:195"
+ cell $not $17
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \alu_done_dly
+ connect \Y $16
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:195"
+ wire width 1 $18
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:195"
+ cell $and $19
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \alu_done
+ connect \B $16
+ connect \Y $18
+ end
+ process $group_5
+ assign \alu_pulse 1'0
+ assign \alu_pulse $18
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:192"
+ wire width 4 \alu_pulsem
+ process $group_6
+ assign \alu_pulsem 4'0000
+ assign \alu_pulsem { \alu_pulse \alu_pulse \alu_pulse \alu_pulse }
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:199"
+ wire width 4 \prev_wr_go
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:199"
+ wire width 4 \prev_wr_go$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:201"
+ wire width 4 $20
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:201"
+ cell $and $21
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 4
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 4
+ parameter \Y_WIDTH 4
+ connect \A \wr__go
+ connect \B { \busy_o \busy_o \busy_o \busy_o }
+ connect \Y $20
+ end
+ process $group_7
+ assign \prev_wr_go$next \prev_wr_go
+ assign \prev_wr_go$next $20
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+ switch \rst
+ case 1'1
+ assign \prev_wr_go$next 4'0000
+ end
+ sync init
+ update \prev_wr_go 4'0000
+ sync posedge \clk
+ update \prev_wr_go \prev_wr_go$next
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100"
+ wire width 1 \done_o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
+ wire width 1 $22
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
+ wire width 1 $23
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
+ wire width 4 $24
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:93"
+ wire width 4 \wrmask
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
+ cell $not $25
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 4
+ parameter \Y_WIDTH 4
+ connect \A \wrmask
+ connect \Y $24
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
+ wire width 4 $26
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
+ cell $and $27
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 4
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 4
+ parameter \Y_WIDTH 4
+ connect \A \wr__rel
+ connect \B $24
+ connect \Y $26
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
+ cell $reduce_bool $28
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 4
+ parameter \Y_WIDTH 1
+ connect \A $26
+ connect \Y $23
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
+ cell $not $29
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A $23
+ connect \Y $22
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
+ wire width 1 $30
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
+ cell $and $31
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \busy_o
+ connect \B $22
+ connect \Y $30
+ end
+ process $group_8
+ assign \done_o 1'0
+ assign \done_o $30
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206"
+ wire width 1 \wr_any
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210"
+ wire width 1 $32
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210"
+ cell $reduce_bool $33
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 4
+ parameter \Y_WIDTH 1
+ connect \A \wr__go
+ connect \Y $32
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210"
+ wire width 1 $34
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210"
+ cell $reduce_bool $35
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 4
+ parameter \Y_WIDTH 1
+ connect \A \prev_wr_go
+ connect \Y $34
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210"
+ wire width 1 $36
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210"
+ cell $or $37
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A $32
+ connect \B $34
+ connect \Y $36
+ end
+ process $group_9
+ assign \wr_any 1'0
+ assign \wr_any $36
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:207"
+ wire width 1 \req_done
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211"
+ wire width 1 $38
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211"
+ cell $not $39
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \alu_mul0_n_ready_i
+ connect \Y $38
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211"
+ wire width 1 $40
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211"
+ cell $and $41
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \wr_any
+ connect \B $38
+ connect \Y $40
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212"
+ wire width 4 $42
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212"
+ cell $and $43
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 4
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 4
+ parameter \Y_WIDTH 4
+ connect \A \req_l_q_req
+ connect \B \wrmask
+ connect \Y $42
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212"
+ wire width 1 $44
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212"
+ cell $eq $45
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 4
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A $42
+ connect \B 1'0
+ connect \Y $44
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212"
+ wire width 1 $46
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212"
+ cell $and $47
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A $40
+ connect \B $44
+ connect \Y $46
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
+ wire width 1 $48
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
+ cell $eq $49
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 4
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \wrmask
+ connect \B 1'0
+ connect \Y $48
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
+ wire width 1 $50
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
+ cell $and $51
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A $48
+ connect \B \alu_mul0_n_ready_i
+ connect \Y $50
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
+ wire width 1 $52
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
+ cell $and $53
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A $50
+ connect \B \alu_mul0_n_valid_o
+ connect \Y $52
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
+ wire width 1 $54
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
+ cell $and $55
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A $52
+ connect \B \busy_o
+ connect \Y $54
+ end
+ process $group_10
+ assign \req_done 1'0
+ assign \req_done $46
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
+ switch { $54 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
+ case 1'1
+ assign \req_done 1'1
+ end
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:221"
+ wire width 1 \reset
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
+ wire width 1 $56
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
+ cell $or $57
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \req_done
+ connect \B \go_die_i
+ connect \Y $56
+ end
+ process $group_11
+ assign \reset 1'0
+ assign \reset $56
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222"
+ wire width 1 \rst_r
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226"
+ wire width 1 $58
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226"
+ cell $or $59
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \issue_i
+ connect \B \go_die_i
+ connect \Y $58
+ end
+ process $group_12
+ assign \rst_r 1'0
+ assign \rst_r $58
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:223"
+ wire width 4 \reset_w
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227"
+ wire width 4 $60
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227"
+ cell $or $61
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 4
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 4
+ parameter \Y_WIDTH 4
+ connect \A \wr__go
+ connect \B { \go_die_i \go_die_i \go_die_i \go_die_i }
+ connect \Y $60
+ end
+ process $group_13
+ assign \reset_w 4'0000
+ assign \reset_w $60
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:224"
+ wire width 3 \reset_r
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:228"
+ wire width 3 $62
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:228"
+ cell $or $63
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 3
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 3
+ parameter \Y_WIDTH 3
+ connect \A \rd__go
+ connect \B { \go_die_i \go_die_i \go_die_i }
+ connect \Y $62
+ end
+ process $group_14
+ assign \reset_r 3'000
+ assign \reset_r $62
+ sync init
+ end
+ process $group_15
+ assign \rok_l_s_rdok 1'0
+ assign \rok_l_s_rdok \issue_i
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232"
+ wire width 1 $64
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232"
+ cell $and $65
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \alu_mul0_n_valid_o
+ connect \B \busy_o
+ connect \Y $64
+ end
+ process $group_16
+ assign \rok_l_r_rdok$next \rok_l_r_rdok
+ assign \rok_l_r_rdok$next $64
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+ switch \rst
+ case 1'1
+ assign \rok_l_r_rdok$next 1'1
+ end
+ sync init
+ update \rok_l_r_rdok 1'1
+ sync posedge \clk
+ update \rok_l_r_rdok \rok_l_r_rdok$next
+ end
+ process $group_17
+ assign \rst_l_s_rst 1'0
+ assign \rst_l_s_rst \all_rd
+ sync init
+ end
+ process $group_18
+ assign \rst_l_r_rst 1'1
+ assign \rst_l_r_rst \rst_r
+ sync init
+ end
+ process $group_19
+ assign \opc_l_s_opc$next \opc_l_s_opc
+ assign \opc_l_s_opc$next \issue_i
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+ switch \rst
+ case 1'1
+ assign \opc_l_s_opc$next 1'0
+ end
+ sync init
+ update \opc_l_s_opc 1'0
+ sync posedge \clk
+ update \opc_l_s_opc \opc_l_s_opc$next
+ end
+ process $group_20
+ assign \opc_l_r_opc$next \opc_l_r_opc
+ assign \opc_l_r_opc$next \req_done
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+ switch \rst
+ case 1'1
+ assign \opc_l_r_opc$next 1'1
+ end
+ sync init
+ update \opc_l_r_opc 1'1
+ sync posedge \clk
+ update \opc_l_r_opc \opc_l_r_opc$next
+ end
+ process $group_21
+ assign \src_l_s_src$next \src_l_s_src
+ assign \src_l_s_src$next { \issue_i \issue_i \issue_i }
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+ switch \rst
+ case 1'1
+ assign \src_l_s_src$next 3'000
+ end
+ sync init
+ update \src_l_s_src 3'000
+ sync posedge \clk
+ update \src_l_s_src \src_l_s_src$next
+ end
+ process $group_22
+ assign \src_l_r_src$next \src_l_r_src
+ assign \src_l_r_src$next \reset_r
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+ switch \rst
+ case 1'1
+ assign \src_l_r_src$next 3'111
+ end
+ sync init
+ update \src_l_r_src 3'111
+ sync posedge \clk
+ update \src_l_r_src \src_l_r_src$next
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:247"
+ wire width 4 $66
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:247"
+ cell $and $67
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 4
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 4
+ parameter \Y_WIDTH 4
+ connect \A \alu_pulsem
+ connect \B \wrmask
+ connect \Y $66
+ end
+ process $group_23
+ assign \req_l_s_req 4'0000
+ assign \req_l_s_req $66
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:248"
+ wire width 4 $68
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:248"
+ cell $or $69
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 4
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 4
+ parameter \Y_WIDTH 4
+ connect \A \reset_w
+ connect \B \prev_wr_go
+ connect \Y $68
+ end
+ process $group_24
+ assign \req_l_r_req 4'1111
+ assign \req_l_r_req $68
+ sync init
+ end
+ attribute \enum_base_type "MicrOp"
+ attribute \enum_value_0000000 "OP_ILLEGAL"
+ attribute \enum_value_0000001 "OP_NOP"
+ attribute \enum_value_0000010 "OP_ADD"
+ attribute \enum_value_0000011 "OP_ADDPCIS"
+ attribute \enum_value_0000100 "OP_AND"
+ attribute \enum_value_0000101 "OP_ATTN"
+ attribute \enum_value_0000110 "OP_B"
+ attribute \enum_value_0000111 "OP_BC"
+ attribute \enum_value_0001000 "OP_BCREG"
+ attribute \enum_value_0001001 "OP_BPERM"
+ attribute \enum_value_0001010 "OP_CMP"
+ attribute \enum_value_0001011 "OP_CMPB"
+ attribute \enum_value_0001100 "OP_CMPEQB"
+ attribute \enum_value_0001101 "OP_CMPRB"
+ attribute \enum_value_0001110 "OP_CNTZ"
+ attribute \enum_value_0001111 "OP_CRAND"
+ attribute \enum_value_0010000 "OP_CRANDC"
+ attribute \enum_value_0010001 "OP_CREQV"
+ attribute \enum_value_0010010 "OP_CRNAND"
+ attribute \enum_value_0010011 "OP_CRNOR"
+ attribute \enum_value_0010100 "OP_CROR"
+ attribute \enum_value_0010101 "OP_CRORC"
+ attribute \enum_value_0010110 "OP_CRXOR"
+ attribute \enum_value_0010111 "OP_DARN"
+ attribute \enum_value_0011000 "OP_DCBF"
+ attribute \enum_value_0011001 "OP_DCBST"
+ attribute \enum_value_0011010 "OP_DCBT"
+ attribute \enum_value_0011011 "OP_DCBTST"
+ attribute \enum_value_0011100 "OP_DCBZ"
+ attribute \enum_value_0011101 "OP_DIV"
+ attribute \enum_value_0011110 "OP_DIVE"
+ attribute \enum_value_0011111 "OP_EXTS"
+ attribute \enum_value_0100000 "OP_EXTSWSLI"
+ attribute \enum_value_0100001 "OP_ICBI"
+ attribute \enum_value_0100010 "OP_ICBT"
+ attribute \enum_value_0100011 "OP_ISEL"
+ attribute \enum_value_0100100 "OP_ISYNC"
+ attribute \enum_value_0100101 "OP_LOAD"
+ attribute \enum_value_0100110 "OP_STORE"
+ attribute \enum_value_0100111 "OP_MADDHD"
+ attribute \enum_value_0101000 "OP_MADDHDU"
+ attribute \enum_value_0101001 "OP_MADDLD"
+ attribute \enum_value_0101010 "OP_MCRF"
+ attribute \enum_value_0101011 "OP_MCRXR"
+ attribute \enum_value_0101100 "OP_MCRXRX"
+ attribute \enum_value_0101101 "OP_MFCR"
+ attribute \enum_value_0101110 "OP_MFSPR"
+ attribute \enum_value_0101111 "OP_MOD"
+ attribute \enum_value_0110000 "OP_MTCRF"
+ attribute \enum_value_0110001 "OP_MTSPR"
+ attribute \enum_value_0110010 "OP_MUL_L64"
+ attribute \enum_value_0110011 "OP_MUL_H64"
+ attribute \enum_value_0110100 "OP_MUL_H32"
+ attribute \enum_value_0110101 "OP_OR"
+ attribute \enum_value_0110110 "OP_POPCNT"
+ attribute \enum_value_0110111 "OP_PRTY"
+ attribute \enum_value_0111000 "OP_RLC"
+ attribute \enum_value_0111001 "OP_RLCL"
+ attribute \enum_value_0111010 "OP_RLCR"
+ attribute \enum_value_0111011 "OP_SETB"
+ attribute \enum_value_0111100 "OP_SHL"
+ attribute \enum_value_0111101 "OP_SHR"
+ attribute \enum_value_0111110 "OP_SYNC"
+ attribute \enum_value_0111111 "OP_TRAP"
+ attribute \enum_value_1000011 "OP_XOR"
+ attribute \enum_value_1000100 "OP_SIM_CONFIG"
+ attribute \enum_value_1000101 "OP_CROP"
+ attribute \enum_value_1000110 "OP_RFID"
+ attribute \enum_value_1000111 "OP_MFMSR"
+ attribute \enum_value_1001000 "OP_MTMSRD"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 7 \oper_r__insn_type
+ attribute \enum_base_type "Function"
+ attribute \enum_value_00000000000 "NONE"
+ attribute \enum_value_00000000010 "ALU"
+ attribute \enum_value_00000000100 "LDST"
+ attribute \enum_value_00000001000 "SHIFT_ROT"
+ attribute \enum_value_00000010000 "LOGICAL"
+ attribute \enum_value_00000100000 "BRANCH"
+ attribute \enum_value_00001000000 "CR"
+ attribute \enum_value_00010000000 "TRAP"
+ attribute \enum_value_00100000000 "MUL"
+ attribute \enum_value_01000000000 "DIV"
+ attribute \enum_value_10000000000 "SPR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 11 \oper_r__fn_unit
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 \oper_r__imm_data__imm
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \oper_r__imm_data__imm_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \oper_r__rc__rc
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \oper_r__rc__rc_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \oper_r__oe__oe
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \oper_r__oe__oe_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \oper_r__invert_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \oper_r__zero_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \oper_r__invert_out
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \oper_r__write_cr0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \oper_r__is_32bit
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \oper_r__is_signed
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 \oper_r__insn
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+ wire width 7 \oper_l__insn_type
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+ wire width 7 \oper_l__insn_type$next
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+ wire width 11 \oper_l__fn_unit
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+ wire width 11 \oper_l__fn_unit$next
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+ wire width 64 \oper_l__imm_data__imm
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+ wire width 64 \oper_l__imm_data__imm$next
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+ wire width 1 \oper_l__imm_data__imm_ok
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+ wire width 1 \oper_l__imm_data__imm_ok$next
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+ wire width 1 \oper_l__rc__rc
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+ wire width 1 \oper_l__rc__rc$next
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+ wire width 1 \oper_l__rc__rc_ok
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+ wire width 1 \oper_l__rc__rc_ok$next
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+ wire width 1 \oper_l__oe__oe
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+ wire width 1 \oper_l__oe__oe$next
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+ wire width 1 \oper_l__oe__oe_ok
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+ wire width 1 \oper_l__oe__oe_ok$next
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+ wire width 1 \oper_l__invert_a
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+ wire width 1 \oper_l__invert_a$next
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+ wire width 1 \oper_l__zero_a
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+ wire width 1 \oper_l__zero_a$next
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+ wire width 1 \oper_l__invert_out
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+ wire width 1 \oper_l__invert_out$next
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+ wire width 1 \oper_l__write_cr0
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+ wire width 1 \oper_l__write_cr0$next
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+ wire width 1 \oper_l__is_32bit
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+ wire width 1 \oper_l__is_32bit$next
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+ wire width 1 \oper_l__is_signed
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+ wire width 1 \oper_l__is_signed$next
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+ wire width 32 \oper_l__insn
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+ wire width 32 \oper_l__insn$next
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
+ wire width 125 $70
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
+ cell $mux $71
+ parameter \WIDTH 125
+ connect \A { \oper_l__insn \oper_l__is_signed \oper_l__is_32bit \oper_l__write_cr0 \oper_l__invert_out \oper_l__zero_a \oper_l__invert_a { \oper_l__oe__oe_ok \oper_l__oe__oe } { \oper_l__rc__rc_ok \oper_l__rc__rc } { \oper_l__imm_data__imm_ok \oper_l__imm_data__imm } \oper_l__fn_unit \oper_l__insn_type }
+ connect \B { \oper_i__insn \oper_i__is_signed \oper_i__is_32bit \oper_i__write_cr0 \oper_i__invert_out \oper_i__zero_a \oper_i__invert_a { \oper_i__oe__oe_ok \oper_i__oe__oe } { \oper_i__rc__rc_ok \oper_i__rc__rc } { \oper_i__imm_data__imm_ok \oper_i__imm_data__imm } \oper_i__fn_unit \oper_i__insn_type }
+ connect \S \issue_i
+ connect \Y $70
+ end
+ process $group_25
+ assign \oper_r__insn_type 7'0000000
+ assign \oper_r__fn_unit 11'00000000000
+ assign \oper_r__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \oper_r__imm_data__imm_ok 1'0
+ assign \oper_r__rc__rc 1'0
+ assign \oper_r__rc__rc_ok 1'0
+ assign \oper_r__oe__oe 1'0
+ assign \oper_r__oe__oe_ok 1'0
+ assign \oper_r__invert_a 1'0
+ assign \oper_r__zero_a 1'0
+ assign \oper_r__invert_out 1'0
+ assign \oper_r__write_cr0 1'0
+ assign \oper_r__is_32bit 1'0
+ assign \oper_r__is_signed 1'0
+ assign \oper_r__insn 32'00000000000000000000000000000000
+ assign { \oper_r__insn \oper_r__is_signed \oper_r__is_32bit \oper_r__write_cr0 \oper_r__invert_out \oper_r__zero_a \oper_r__invert_a { \oper_r__oe__oe_ok \oper_r__oe__oe } { \oper_r__rc__rc_ok \oper_r__rc__rc } { \oper_r__imm_data__imm_ok \oper_r__imm_data__imm } \oper_r__fn_unit \oper_r__insn_type } $70
+ sync init
+ end
+ process $group_40
+ assign \oper_l__insn_type$next \oper_l__insn_type
+ assign \oper_l__fn_unit$next \oper_l__fn_unit
+ assign \oper_l__imm_data__imm$next \oper_l__imm_data__imm
+ assign \oper_l__imm_data__imm_ok$next \oper_l__imm_data__imm_ok
+ assign \oper_l__rc__rc$next \oper_l__rc__rc
+ assign \oper_l__rc__rc_ok$next \oper_l__rc__rc_ok
+ assign \oper_l__oe__oe$next \oper_l__oe__oe
+ assign \oper_l__oe__oe_ok$next \oper_l__oe__oe_ok
+ assign \oper_l__invert_a$next \oper_l__invert_a
+ assign \oper_l__zero_a$next \oper_l__zero_a
+ assign \oper_l__invert_out$next \oper_l__invert_out
+ assign \oper_l__write_cr0$next \oper_l__write_cr0
+ assign \oper_l__is_32bit$next \oper_l__is_32bit
+ assign \oper_l__is_signed$next \oper_l__is_signed
+ assign \oper_l__insn$next \oper_l__insn
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
+ switch { \issue_i }
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
+ case 1'1
+ assign { \oper_l__insn$next \oper_l__is_signed$next \oper_l__is_32bit$next \oper_l__write_cr0$next \oper_l__invert_out$next \oper_l__zero_a$next \oper_l__invert_a$next { \oper_l__oe__oe_ok$next \oper_l__oe__oe$next } { \oper_l__rc__rc_ok$next \oper_l__rc__rc$next } { \oper_l__imm_data__imm_ok$next \oper_l__imm_data__imm$next } \oper_l__fn_unit$next \oper_l__insn_type$next } { \oper_i__insn \oper_i__is_signed \oper_i__is_32bit \oper_i__write_cr0 \oper_i__invert_out \oper_i__zero_a \oper_i__invert_a { \oper_i__oe__oe_ok \oper_i__oe__oe } { \oper_i__rc__rc_ok \oper_i__rc__rc } { \oper_i__imm_data__imm_ok \oper_i__imm_data__imm } \oper_i__fn_unit \oper_i__insn_type }
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+ switch \rst
+ case 1'1
+ assign \oper_l__imm_data__imm$next 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \oper_l__imm_data__imm_ok$next 1'0
+ assign \oper_l__rc__rc$next 1'0
+ assign \oper_l__rc__rc_ok$next 1'0
+ assign \oper_l__oe__oe$next 1'0
+ assign \oper_l__oe__oe_ok$next 1'0
+ end
+ sync init
+ update \oper_l__insn_type 7'0000000
+ update \oper_l__fn_unit 11'00000000000
+ update \oper_l__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
+ update \oper_l__imm_data__imm_ok 1'0
+ update \oper_l__rc__rc 1'0
+ update \oper_l__rc__rc_ok 1'0
+ update \oper_l__oe__oe 1'0
+ update \oper_l__oe__oe_ok 1'0
+ update \oper_l__invert_a 1'0
+ update \oper_l__zero_a 1'0
+ update \oper_l__invert_out 1'0
+ update \oper_l__write_cr0 1'0
+ update \oper_l__is_32bit 1'0
+ update \oper_l__is_signed 1'0
+ update \oper_l__insn 32'00000000000000000000000000000000
+ sync posedge \clk
+ update \oper_l__insn_type \oper_l__insn_type$next
+ update \oper_l__fn_unit \oper_l__fn_unit$next
+ update \oper_l__imm_data__imm \oper_l__imm_data__imm$next
+ update \oper_l__imm_data__imm_ok \oper_l__imm_data__imm_ok$next
+ update \oper_l__rc__rc \oper_l__rc__rc$next
+ update \oper_l__rc__rc_ok \oper_l__rc__rc_ok$next
+ update \oper_l__oe__oe \oper_l__oe__oe$next
+ update \oper_l__oe__oe_ok \oper_l__oe__oe_ok$next
+ update \oper_l__invert_a \oper_l__invert_a$next
+ update \oper_l__zero_a \oper_l__zero_a$next
+ update \oper_l__invert_out \oper_l__invert_out$next
+ update \oper_l__write_cr0 \oper_l__write_cr0$next
+ update \oper_l__is_32bit \oper_l__is_32bit$next
+ update \oper_l__is_signed \oper_l__is_signed$next
+ update \oper_l__insn \oper_l__insn$next
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262"
+ wire width 64 \data_r0__o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262"
+ wire width 1 \data_r0__o_ok
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+ wire width 64 \data_r0_l__o
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+ wire width 64 \data_r0_l__o$next
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+ wire width 1 \data_r0_l__o_ok
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+ wire width 1 \data_r0_l__o_ok$next
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
+ wire width 65 $72
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744"
+ wire width 1 $73
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744"
+ cell $reduce_bool $74
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 4
+ parameter \Y_WIDTH 1
+ connect \A \alu_pulsem
+ connect \Y $73
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
+ cell $mux $75
+ parameter \WIDTH 65
+ connect \A { \data_r0_l__o_ok \data_r0_l__o }
+ connect \B { \o_ok \alu_mul0_o }
+ connect \S $73
+ connect \Y $72
+ end
+ process $group_55
+ assign \data_r0__o 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \data_r0__o_ok 1'0
+ assign { \data_r0__o_ok \data_r0__o } $72
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
+ wire width 1 $76
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
+ cell $reduce_bool $77
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 4
+ parameter \Y_WIDTH 1
+ connect \A \alu_pulsem
+ connect \Y $76
+ end
+ process $group_57
+ assign \data_r0_l__o$next \data_r0_l__o
+ assign \data_r0_l__o_ok$next \data_r0_l__o_ok
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
+ switch { $76 }
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
+ case 1'1
+ assign { \data_r0_l__o_ok$next \data_r0_l__o$next } { \o_ok \alu_mul0_o }
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+ switch \rst
+ case 1'1
+ assign \data_r0_l__o_ok$next 1'0
+ end
+ sync init
+ update \data_r0_l__o 64'0000000000000000000000000000000000000000000000000000000000000000
+ update \data_r0_l__o_ok 1'0
+ sync posedge \clk
+ update \data_r0_l__o \data_r0_l__o$next
+ update \data_r0_l__o_ok \data_r0_l__o_ok$next
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262"
+ wire width 4 \data_r1__cr_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262"
+ wire width 1 \data_r1__cr_a_ok
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+ wire width 4 \data_r1_l__cr_a
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+ wire width 4 \data_r1_l__cr_a$next
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+ wire width 1 \data_r1_l__cr_a_ok
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+ wire width 1 \data_r1_l__cr_a_ok$next
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
+ wire width 5 $78
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744"
+ wire width 1 $79
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744"
+ cell $reduce_bool $80
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 4
+ parameter \Y_WIDTH 1
+ connect \A \alu_pulsem
+ connect \Y $79
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
+ cell $mux $81
+ parameter \WIDTH 5
+ connect \A { \data_r1_l__cr_a_ok \data_r1_l__cr_a }
+ connect \B { \cr_a_ok \alu_mul0_cr_a }
+ connect \S $79
+ connect \Y $78
+ end
+ process $group_59
+ assign \data_r1__cr_a 4'0000
+ assign \data_r1__cr_a_ok 1'0
+ assign { \data_r1__cr_a_ok \data_r1__cr_a } $78
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
+ wire width 1 $82
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
+ cell $reduce_bool $83
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 4
+ parameter \Y_WIDTH 1
+ connect \A \alu_pulsem
+ connect \Y $82
+ end
+ process $group_61
+ assign \data_r1_l__cr_a$next \data_r1_l__cr_a
+ assign \data_r1_l__cr_a_ok$next \data_r1_l__cr_a_ok
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
+ switch { $82 }
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
+ case 1'1
+ assign { \data_r1_l__cr_a_ok$next \data_r1_l__cr_a$next } { \cr_a_ok \alu_mul0_cr_a }
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+ switch \rst
+ case 1'1
+ assign \data_r1_l__cr_a_ok$next 1'0
+ end
+ sync init
+ update \data_r1_l__cr_a 4'0000
+ update \data_r1_l__cr_a_ok 1'0
+ sync posedge \clk
+ update \data_r1_l__cr_a \data_r1_l__cr_a$next
+ update \data_r1_l__cr_a_ok \data_r1_l__cr_a_ok$next
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262"
+ wire width 2 \data_r2__xer_ov
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262"
+ wire width 1 \data_r2__xer_ov_ok
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+ wire width 2 \data_r2_l__xer_ov
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+ wire width 2 \data_r2_l__xer_ov$next
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+ wire width 1 \data_r2_l__xer_ov_ok
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+ wire width 1 \data_r2_l__xer_ov_ok$next
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
+ wire width 3 $84
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744"
+ wire width 1 $85
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744"
+ cell $reduce_bool $86
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 4
+ parameter \Y_WIDTH 1
+ connect \A \alu_pulsem
+ connect \Y $85
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
+ cell $mux $87
+ parameter \WIDTH 3
+ connect \A { \data_r2_l__xer_ov_ok \data_r2_l__xer_ov }
+ connect \B { \xer_ov_ok \alu_mul0_xer_ov }
+ connect \S $85
+ connect \Y $84
+ end
+ process $group_63
+ assign \data_r2__xer_ov 2'00
+ assign \data_r2__xer_ov_ok 1'0
+ assign { \data_r2__xer_ov_ok \data_r2__xer_ov } $84
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
+ wire width 1 $88
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
+ cell $reduce_bool $89
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 4
+ parameter \Y_WIDTH 1
+ connect \A \alu_pulsem
+ connect \Y $88
+ end
+ process $group_65
+ assign \data_r2_l__xer_ov$next \data_r2_l__xer_ov
+ assign \data_r2_l__xer_ov_ok$next \data_r2_l__xer_ov_ok
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
+ switch { $88 }
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
+ case 1'1
+ assign { \data_r2_l__xer_ov_ok$next \data_r2_l__xer_ov$next } { \xer_ov_ok \alu_mul0_xer_ov }
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+ switch \rst
+ case 1'1
+ assign \data_r2_l__xer_ov_ok$next 1'0
+ end
+ sync init
+ update \data_r2_l__xer_ov 2'00
+ update \data_r2_l__xer_ov_ok 1'0
+ sync posedge \clk
+ update \data_r2_l__xer_ov \data_r2_l__xer_ov$next
+ update \data_r2_l__xer_ov_ok \data_r2_l__xer_ov_ok$next
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262"
+ wire width 1 \data_r3__xer_so
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:262"
+ wire width 1 \data_r3__xer_so_ok
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+ wire width 1 \data_r3_l__xer_so
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+ wire width 1 \data_r3_l__xer_so$next
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+ wire width 1 \data_r3_l__xer_so_ok
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+ wire width 1 \data_r3_l__xer_so_ok$next
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
+ wire width 2 $90
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744"
+ wire width 1 $91
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744"
+ cell $reduce_bool $92
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 4
+ parameter \Y_WIDTH 1
+ connect \A \alu_pulsem
+ connect \Y $91
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
+ cell $mux $93
+ parameter \WIDTH 2
+ connect \A { \data_r3_l__xer_so_ok \data_r3_l__xer_so }
+ connect \B { \xer_so_ok \alu_mul0_xer_so }
+ connect \S $91
+ connect \Y $90
+ end
+ process $group_67
+ assign \data_r3__xer_so 1'0
+ assign \data_r3__xer_so_ok 1'0
+ assign { \data_r3__xer_so_ok \data_r3__xer_so } $90
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
+ wire width 1 $94
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
+ cell $reduce_bool $95
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 4
+ parameter \Y_WIDTH 1
+ connect \A \alu_pulsem
+ connect \Y $94
+ end
+ process $group_69
+ assign \data_r3_l__xer_so$next \data_r3_l__xer_so
+ assign \data_r3_l__xer_so_ok$next \data_r3_l__xer_so_ok
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
+ switch { $94 }
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
+ case 1'1
+ assign { \data_r3_l__xer_so_ok$next \data_r3_l__xer_so$next } { \xer_so_ok \alu_mul0_xer_so }
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+ switch \rst
+ case 1'1
+ assign \data_r3_l__xer_so_ok$next 1'0
+ end
+ sync init
+ update \data_r3_l__xer_so 1'0
+ update \data_r3_l__xer_so_ok 1'0
+ sync posedge \clk
+ update \data_r3_l__xer_so \data_r3_l__xer_so$next
+ update \data_r3_l__xer_so_ok \data_r3_l__xer_so_ok$next
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+ wire width 1 $96
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+ cell $and $97
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \data_r0__o_ok
+ connect \B \busy_o
+ connect \Y $96
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+ wire width 1 $98
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+ cell $and $99
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \data_r1__cr_a_ok
+ connect \B \busy_o
+ connect \Y $98
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+ wire width 1 $100
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+ cell $and $101
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \data_r2__xer_ov_ok
+ connect \B \busy_o
+ connect \Y $100
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+ wire width 1 $102
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+ cell $and $103
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \data_r3__xer_so_ok
+ connect \B \busy_o
+ connect \Y $102
+ end
+ process $group_71
+ assign \wrmask 4'0000
+ assign \wrmask { $102 $100 $98 $96 }
+ sync init
+ end
+ process $group_72
+ assign \alu_mul0_op__insn_type 7'0000000
+ assign \alu_mul0_op__fn_unit 11'00000000000
+ assign \alu_mul0_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \alu_mul0_op__imm_data__imm_ok 1'0
+ assign \alu_mul0_op__rc__rc 1'0
+ assign \alu_mul0_op__rc__rc_ok 1'0
+ assign \alu_mul0_op__oe__oe 1'0
+ assign \alu_mul0_op__oe__oe_ok 1'0
+ assign \alu_mul0_op__invert_a 1'0
+ assign \alu_mul0_op__zero_a 1'0
+ assign \alu_mul0_op__invert_out 1'0
+ assign \alu_mul0_op__write_cr0 1'0
+ assign \alu_mul0_op__is_32bit 1'0
+ assign \alu_mul0_op__is_signed 1'0
+ assign \alu_mul0_op__insn 32'00000000000000000000000000000000
+ assign { \alu_mul0_op__insn \alu_mul0_op__is_signed \alu_mul0_op__is_32bit \alu_mul0_op__write_cr0 \alu_mul0_op__invert_out \alu_mul0_op__zero_a \alu_mul0_op__invert_a { \alu_mul0_op__oe__oe_ok \alu_mul0_op__oe__oe } { \alu_mul0_op__rc__rc_ok \alu_mul0_op__rc__rc } { \alu_mul0_op__imm_data__imm_ok \alu_mul0_op__imm_data__imm } \alu_mul0_op__fn_unit \alu_mul0_op__insn_type } { \oper_r__insn \oper_r__is_signed \oper_r__is_32bit \oper_r__write_cr0 \oper_r__invert_out \oper_r__zero_a \oper_r__invert_a { \oper_r__oe__oe_ok \oper_r__oe__oe } { \oper_r__rc__rc_ok \oper_r__rc__rc } { \oper_r__imm_data__imm_ok \oper_r__imm_data__imm } \oper_r__fn_unit \oper_r__insn_type }
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:158"
+ wire width 1 \src_sel
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:159"
+ wire width 1 $104
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:159"
+ cell $mux $105
+ parameter \WIDTH 1
+ connect \A \src_l_q_src [0]
+ connect \B \opc_l_q_opc
+ connect \S \oper_r__zero_a
+ connect \Y $104
+ end
+ process $group_87
+ assign \src_sel 1'0
+ assign \src_sel $104
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:157"
+ wire width 64 \src_or_imm
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:160"
+ wire width 64 $106
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:160"
+ cell $mux $107
+ parameter \WIDTH 64
+ connect \A \src1_i
+ connect \B 64'0000000000000000000000000000000000000000000000000000000000000000
+ connect \S \oper_r__zero_a
+ connect \Y $106
+ end
+ process $group_88
+ assign \src_or_imm 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \src_or_imm $106
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:158"
+ wire width 1 \src_sel$108
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:159"
+ wire width 1 $109
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:159"
+ cell $mux $110
+ parameter \WIDTH 1
+ connect \A \src_l_q_src [1]
+ connect \B \opc_l_q_opc
+ connect \S \oper_r__imm_data__imm_ok
+ connect \Y $109
+ end
+ process $group_89
+ assign \src_sel$108 1'0
+ assign \src_sel$108 $109
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:157"
+ wire width 64 \src_or_imm$111
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:160"
+ wire width 64 $112
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:160"
+ cell $mux $113
+ parameter \WIDTH 64
+ connect \A \src2_i
+ connect \B \oper_r__imm_data__imm
+ connect \S \oper_r__imm_data__imm_ok
+ connect \Y $112
+ end
+ process $group_90
+ assign \src_or_imm$111 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \src_or_imm$111 $112
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
+ wire width 64 \src_r0
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
+ wire width 64 \src_r0$next
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
+ wire width 64 $114
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
+ cell $mux $115
+ parameter \WIDTH 64
+ connect \A \src_r0
+ connect \B \src_or_imm
+ connect \S \src_sel
+ connect \Y $114
+ end
+ process $group_91
+ assign \alu_mul0_ra 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \alu_mul0_ra $114
+ sync init
+ end
+ process $group_92
+ assign \src_r0$next \src_r0
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
+ switch { \src_sel }
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
+ case 1'1
+ assign \src_r0$next \src_or_imm
+ end
+ sync init
+ update \src_r0 64'0000000000000000000000000000000000000000000000000000000000000000
+ sync posedge \clk
+ update \src_r0 \src_r0$next
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
+ wire width 64 \src_r1
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
+ wire width 64 \src_r1$next
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
+ wire width 64 $116
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
+ cell $mux $117
+ parameter \WIDTH 64
+ connect \A \src_r1
+ connect \B \src_or_imm$111
+ connect \S \src_sel$108
+ connect \Y $116
+ end
+ process $group_93
+ assign \alu_mul0_rb 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \alu_mul0_rb $116
+ sync init
+ end
+ process $group_94
+ assign \src_r1$next \src_r1
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
+ switch { \src_sel$108 }
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
+ case 1'1
+ assign \src_r1$next \src_or_imm$111
+ end
+ sync init
+ update \src_r1 64'0000000000000000000000000000000000000000000000000000000000000000
+ sync posedge \clk
+ update \src_r1 \src_r1$next
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
+ wire width 1 \src_r2
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
+ wire width 1 \src_r2$next
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
+ wire width 1 $118
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
+ cell $mux $119
+ parameter \WIDTH 1
+ connect \A \src_r2
+ connect \B \src3_i
+ connect \S \src_l_q_src [2]
+ connect \Y $118
+ end
+ process $group_95
+ assign \alu_mul0_xer_so$1 1'0
+ assign \alu_mul0_xer_so$1 $118
+ sync init
+ end
+ process $group_96
+ assign \src_r2$next \src_r2
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
+ switch { \src_l_q_src [2] }
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
+ case 1'1
+ assign \src_r2$next \src3_i
+ end
+ sync init
+ update \src_r2 1'0
+ sync posedge \clk
+ update \src_r2 \src_r2$next
+ end
+ process $group_97
+ assign \alu_mul0_p_valid_i 1'0
+ assign \alu_mul0_p_valid_i \alui_l_q_alui
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:321"
+ wire width 1 $120
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:321"
+ cell $and $121
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \alu_mul0_p_ready_o
+ connect \B \alui_l_q_alui
+ connect \Y $120
+ end
+ process $group_98
+ assign \alui_l_r_alui$next \alui_l_r_alui
+ assign \alui_l_r_alui$next $120
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+ switch \rst
+ case 1'1
+ assign \alui_l_r_alui$next 1'1
+ end
+ sync init
+ update \alui_l_r_alui 1'1
+ sync posedge \clk
+ update \alui_l_r_alui \alui_l_r_alui$next
+ end
+ process $group_99
+ assign \alui_l_s_alui 1'0
+ assign \alui_l_s_alui \all_rd_pulse
+ sync init
+ end
+ process $group_100
+ assign \alu_mul0_n_ready_i 1'0
+ assign \alu_mul0_n_ready_i \alu_l_q_alu
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:328"
+ wire width 1 $122
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:328"
+ cell $and $123
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \alu_mul0_n_valid_o
+ connect \B \alu_l_q_alu
+ connect \Y $122
+ end
+ process $group_101
+ assign \alu_l_r_alu$next \alu_l_r_alu
+ assign \alu_l_r_alu$next $122
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+ switch \rst
+ case 1'1
+ assign \alu_l_r_alu$next 1'1
+ end
+ sync init
+ update \alu_l_r_alu 1'1
+ sync posedge \clk
+ update \alu_l_r_alu \alu_l_r_alu$next
+ end
+ process $group_102
+ assign \alu_l_s_alu 1'0
+ assign \alu_l_s_alu \all_rd_pulse
+ sync init
+ end
+ process $group_103
+ assign \busy_o 1'0
+ assign \busy_o \opc_l_q_opc
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341"
+ wire width 3 $124
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341"
+ cell $and $125
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 3
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 3
+ parameter \Y_WIDTH 3
+ connect \A \src_l_q_src
+ connect \B { \busy_o \busy_o \busy_o }
+ connect \Y $124
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:164"
+ wire width 1 $126
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:164"
+ cell $not $127
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \oper_r__zero_a
+ connect \Y $126
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:164"
+ wire width 1 $128
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:164"
+ cell $not $129
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \oper_r__imm_data__imm_ok
+ connect \Y $128
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341"
+ wire width 3 $130
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341"
+ cell $and $131
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 3
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 3
+ parameter \Y_WIDTH 3
+ connect \A $124
+ connect \B { 1'1 $128 $126 }
+ connect \Y $130
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341"
+ wire width 3 $132
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341"
+ cell $not $133
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 3
+ parameter \Y_WIDTH 3
+ connect \A \rdmaskn
+ connect \Y $132
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341"
+ wire width 3 $134
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341"
+ cell $and $135
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 3
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 3
+ parameter \Y_WIDTH 3
+ connect \A $130
+ connect \B $132
+ connect \Y $134
+ end
+ process $group_104
+ assign \rd__rel 3'000
+ assign \rd__rel $134
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
+ wire width 1 $136
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
+ cell $and $137
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \busy_o
+ connect \B \shadown_i
+ connect \Y $136
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
+ wire width 1 $138
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
+ cell $and $139
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \busy_o
+ connect \B \shadown_i
+ connect \Y $138
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
+ wire width 1 $140
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
+ cell $and $141
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \busy_o
+ connect \B \shadown_i
+ connect \Y $140
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
+ wire width 1 $142
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
+ cell $and $143
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \busy_o
+ connect \B \shadown_i
+ connect \Y $142
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:345"
+ wire width 4 $144
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:345"
+ cell $and $145
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 4
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 4
+ parameter \Y_WIDTH 4
+ connect \A \req_l_q_req
+ connect \B { $136 $138 $140 $142 }
+ connect \Y $144
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:345"
+ wire width 4 $146
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:345"
+ cell $and $147
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 4
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 4
+ parameter \Y_WIDTH 4
+ connect \A $144
+ connect \B \wrmask
+ connect \Y $146
+ end
+ process $group_105
+ assign \wr__rel 4'0000
+ assign \wr__rel $146
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+ wire width 1 $148
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+ cell $and $149
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \wr__go [0]
+ connect \B \busy_o
+ connect \Y $148
+ end
+ process $group_106
+ assign \dest1_o 64'0000000000000000000000000000000000000000000000000000000000000000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+ switch { $148 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+ case 1'1
+ assign \dest1_o { \data_r0__o_ok \data_r0__o } [63:0]
+ end
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+ wire width 1 $150
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+ cell $and $151
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \wr__go [1]
+ connect \B \busy_o
+ connect \Y $150
+ end
+ process $group_107
+ assign \dest2_o 4'0000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+ switch { $150 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+ case 1'1
+ assign \dest2_o { \data_r1__cr_a_ok \data_r1__cr_a } [3:0]
+ end
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+ wire width 1 $152
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+ cell $and $153
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \wr__go [2]
+ connect \B \busy_o
+ connect \Y $152
+ end
+ process $group_108
+ assign \dest3_o 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+ switch { $152 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+ case 1'1
+ assign \dest3_o { \data_r2__xer_ov_ok \data_r2__xer_ov } [1:0]
+ end
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+ wire width 1 $154
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+ cell $and $155
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \wr__go [3]
+ connect \B \busy_o
+ connect \Y $154
+ end
+ process $group_109
+ assign \dest4_o 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+ switch { $154 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+ case 1'1
+ assign \dest4_o { \data_r3__xer_so_ok \data_r3__xer_so } [0]
+ end
+ sync init
+ end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.p"
+module \p$87
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153"
+ wire width 1 input 0 \p_valid_i
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154"
+ wire width 1 input 1 \p_ready_o
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158"
+ wire width 1 \trigger
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205"
+ wire width 1 $1
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205"
+ cell $and $2
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \p_valid_i
+ connect \B \p_ready_o
+ connect \Y $1
+ end
+ process $group_0
+ assign \trigger 1'0
+ assign \trigger $1
+ sync init
+ end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.n"
+module \n$88
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
+ wire width 1 input 0 \n_valid_o
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
+ wire width 1 input 1 \n_ready_i
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251"
+ wire width 1 \trigger
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:297"
+ wire width 1 $1
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:297"
+ cell $and $2
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \n_ready_i
+ connect \B \n_valid_o
+ connect \Y $1
+ end
+ process $group_0
+ assign \trigger 1'0
+ assign \trigger $1
+ sync init
+ end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe.p"
+module \p$90
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153"
+ wire width 1 input 0 \p_valid_i
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154"
+ wire width 1 input 1 \p_ready_o
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158"
+ wire width 1 \trigger
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205"
+ wire width 1 $1
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205"
+ cell $and $2
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \p_valid_i
+ connect \B \p_ready_o
+ connect \Y $1
+ end
+ process $group_0
+ assign \trigger 1'0
+ assign \trigger $1
+ sync init
+ end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe.n"
+module \n$91
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
+ wire width 1 input 0 \n_valid_o
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
+ wire width 1 input 1 \n_ready_i
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251"
+ wire width 1 \trigger
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:297"
+ wire width 1 $1
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:297"
+ cell $and $2
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \n_ready_i
+ connect \B \n_valid_o
+ connect \Y $1
+ end
+ process $group_0
+ assign \trigger 1'0
+ assign \trigger $1
+ sync init
+ end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe.input"
+module \input$92
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+ wire width 2 input 0 \muxid
+ attribute \enum_base_type "MicrOp"
+ attribute \enum_value_0000000 "OP_ILLEGAL"
+ attribute \enum_value_0000001 "OP_NOP"
+ attribute \enum_value_0000010 "OP_ADD"
+ attribute \enum_value_0000011 "OP_ADDPCIS"
+ attribute \enum_value_0000100 "OP_AND"
+ attribute \enum_value_0000101 "OP_ATTN"
+ attribute \enum_value_0000110 "OP_B"
+ attribute \enum_value_0000111 "OP_BC"
+ attribute \enum_value_0001000 "OP_BCREG"
+ attribute \enum_value_0001001 "OP_BPERM"
+ attribute \enum_value_0001010 "OP_CMP"
+ attribute \enum_value_0001011 "OP_CMPB"
+ attribute \enum_value_0001100 "OP_CMPEQB"
+ attribute \enum_value_0001101 "OP_CMPRB"
+ attribute \enum_value_0001110 "OP_CNTZ"
+ attribute \enum_value_0001111 "OP_CRAND"
+ attribute \enum_value_0010000 "OP_CRANDC"
+ attribute \enum_value_0010001 "OP_CREQV"
+ attribute \enum_value_0010010 "OP_CRNAND"
+ attribute \enum_value_0010011 "OP_CRNOR"
+ attribute \enum_value_0010100 "OP_CROR"
+ attribute \enum_value_0010101 "OP_CRORC"
+ attribute \enum_value_0010110 "OP_CRXOR"
+ attribute \enum_value_0010111 "OP_DARN"
+ attribute \enum_value_0011000 "OP_DCBF"
+ attribute \enum_value_0011001 "OP_DCBST"
+ attribute \enum_value_0011010 "OP_DCBT"
+ attribute \enum_value_0011011 "OP_DCBTST"
+ attribute \enum_value_0011100 "OP_DCBZ"
+ attribute \enum_value_0011101 "OP_DIV"
+ attribute \enum_value_0011110 "OP_DIVE"
+ attribute \enum_value_0011111 "OP_EXTS"
+ attribute \enum_value_0100000 "OP_EXTSWSLI"
+ attribute \enum_value_0100001 "OP_ICBI"
+ attribute \enum_value_0100010 "OP_ICBT"
+ attribute \enum_value_0100011 "OP_ISEL"
+ attribute \enum_value_0100100 "OP_ISYNC"
+ attribute \enum_value_0100101 "OP_LOAD"
+ attribute \enum_value_0100110 "OP_STORE"
+ attribute \enum_value_0100111 "OP_MADDHD"
+ attribute \enum_value_0101000 "OP_MADDHDU"
+ attribute \enum_value_0101001 "OP_MADDLD"
+ attribute \enum_value_0101010 "OP_MCRF"
+ attribute \enum_value_0101011 "OP_MCRXR"
+ attribute \enum_value_0101100 "OP_MCRXRX"
+ attribute \enum_value_0101101 "OP_MFCR"
+ attribute \enum_value_0101110 "OP_MFSPR"
+ attribute \enum_value_0101111 "OP_MOD"
+ attribute \enum_value_0110000 "OP_MTCRF"
+ attribute \enum_value_0110001 "OP_MTSPR"
+ attribute \enum_value_0110010 "OP_MUL_L64"
+ attribute \enum_value_0110011 "OP_MUL_H64"
+ attribute \enum_value_0110100 "OP_MUL_H32"
+ attribute \enum_value_0110101 "OP_OR"
+ attribute \enum_value_0110110 "OP_POPCNT"
+ attribute \enum_value_0110111 "OP_PRTY"
+ attribute \enum_value_0111000 "OP_RLC"
+ attribute \enum_value_0111001 "OP_RLCL"
+ attribute \enum_value_0111010 "OP_RLCR"
+ attribute \enum_value_0111011 "OP_SETB"
+ attribute \enum_value_0111100 "OP_SHL"
+ attribute \enum_value_0111101 "OP_SHR"
+ attribute \enum_value_0111110 "OP_SYNC"
+ attribute \enum_value_0111111 "OP_TRAP"
+ attribute \enum_value_1000011 "OP_XOR"
+ attribute \enum_value_1000100 "OP_SIM_CONFIG"
+ attribute \enum_value_1000101 "OP_CROP"
+ attribute \enum_value_1000110 "OP_RFID"
+ attribute \enum_value_1000111 "OP_MFMSR"
+ attribute \enum_value_1001000 "OP_MTMSRD"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 7 input 1 \op__insn_type
+ attribute \enum_base_type "Function"
+ attribute \enum_value_00000000000 "NONE"
+ attribute \enum_value_00000000010 "ALU"
+ attribute \enum_value_00000000100 "LDST"
+ attribute \enum_value_00000001000 "SHIFT_ROT"
+ attribute \enum_value_00000010000 "LOGICAL"
+ attribute \enum_value_00000100000 "BRANCH"
+ attribute \enum_value_00001000000 "CR"
+ attribute \enum_value_00010000000 "TRAP"
+ attribute \enum_value_00100000000 "MUL"
+ attribute \enum_value_01000000000 "DIV"
+ attribute \enum_value_10000000000 "SPR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 11 input 2 \op__fn_unit
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 input 3 \op__imm_data__imm
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 4 \op__imm_data__imm_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 5 \op__rc__rc
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 6 \op__rc__rc_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 7 \op__oe__oe
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 8 \op__oe__oe_ok
+ attribute \enum_base_type "CryIn"
+ attribute \enum_value_00 "ZERO"
+ attribute \enum_value_01 "ONE"
+ attribute \enum_value_10 "CA"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 2 input 10 \op__input_carry
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 11 \op__output_carry
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 12 \op__input_cr
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 13 \op__output_cr
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 14 \op__is_32bit
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 15 \op__is_signed
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 input 16 \op__insn
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 64 input 17 \ra
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 64 input 18 \rb
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 64 input 19 \rc
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 2 input 20 \xer_ca
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+ wire width 2 output 21 \muxid$1
+ attribute \enum_base_type "MicrOp"
+ attribute \enum_value_0000000 "OP_ILLEGAL"
+ attribute \enum_value_0000001 "OP_NOP"
+ attribute \enum_value_0000010 "OP_ADD"
+ attribute \enum_value_0000011 "OP_ADDPCIS"
+ attribute \enum_value_0000100 "OP_AND"
+ attribute \enum_value_0000101 "OP_ATTN"
+ attribute \enum_value_0000110 "OP_B"
+ attribute \enum_value_0000111 "OP_BC"
+ attribute \enum_value_0001000 "OP_BCREG"
+ attribute \enum_value_0001001 "OP_BPERM"
+ attribute \enum_value_0001010 "OP_CMP"
+ attribute \enum_value_0001011 "OP_CMPB"
+ attribute \enum_value_0001100 "OP_CMPEQB"
+ attribute \enum_value_0001101 "OP_CMPRB"
+ attribute \enum_value_0001110 "OP_CNTZ"
+ attribute \enum_value_0001111 "OP_CRAND"
+ attribute \enum_value_0010000 "OP_CRANDC"
+ attribute \enum_value_0010001 "OP_CREQV"
+ attribute \enum_value_0010010 "OP_CRNAND"
+ attribute \enum_value_0010011 "OP_CRNOR"
+ attribute \enum_value_0010100 "OP_CROR"
+ attribute \enum_value_0010101 "OP_CRORC"
+ attribute \enum_value_0010110 "OP_CRXOR"
+ attribute \enum_value_0010111 "OP_DARN"
+ attribute \enum_value_0011000 "OP_DCBF"
+ attribute \enum_value_0011001 "OP_DCBST"
+ attribute \enum_value_0011010 "OP_DCBT"
+ attribute \enum_value_0011011 "OP_DCBTST"
+ attribute \enum_value_0011100 "OP_DCBZ"
+ attribute \enum_value_0011101 "OP_DIV"
+ attribute \enum_value_0011110 "OP_DIVE"
+ attribute \enum_value_0011111 "OP_EXTS"
+ attribute \enum_value_0100000 "OP_EXTSWSLI"
+ attribute \enum_value_0100001 "OP_ICBI"
+ attribute \enum_value_0100010 "OP_ICBT"
+ attribute \enum_value_0100011 "OP_ISEL"
+ attribute \enum_value_0100100 "OP_ISYNC"
+ attribute \enum_value_0100101 "OP_LOAD"
+ attribute \enum_value_0100110 "OP_STORE"
+ attribute \enum_value_0100111 "OP_MADDHD"
+ attribute \enum_value_0101000 "OP_MADDHDU"
+ attribute \enum_value_0101001 "OP_MADDLD"
+ attribute \enum_value_0101010 "OP_MCRF"
+ attribute \enum_value_0101011 "OP_MCRXR"
+ attribute \enum_value_0101100 "OP_MCRXRX"
+ attribute \enum_value_0101101 "OP_MFCR"
+ attribute \enum_value_0101110 "OP_MFSPR"
+ attribute \enum_value_0101111 "OP_MOD"
+ attribute \enum_value_0110000 "OP_MTCRF"
+ attribute \enum_value_0110001 "OP_MTSPR"
+ attribute \enum_value_0110010 "OP_MUL_L64"
+ attribute \enum_value_0110011 "OP_MUL_H64"
+ attribute \enum_value_0110100 "OP_MUL_H32"
+ attribute \enum_value_0110101 "OP_OR"
+ attribute \enum_value_0110110 "OP_POPCNT"
+ attribute \enum_value_0110111 "OP_PRTY"
+ attribute \enum_value_0111000 "OP_RLC"
+ attribute \enum_value_0111001 "OP_RLCL"
+ attribute \enum_value_0111010 "OP_RLCR"
+ attribute \enum_value_0111011 "OP_SETB"
+ attribute \enum_value_0111100 "OP_SHL"
+ attribute \enum_value_0111101 "OP_SHR"
+ attribute \enum_value_0111110 "OP_SYNC"
+ attribute \enum_value_0111111 "OP_TRAP"
+ attribute \enum_value_1000011 "OP_XOR"
+ attribute \enum_value_1000100 "OP_SIM_CONFIG"
+ attribute \enum_value_1000101 "OP_CROP"
+ attribute \enum_value_1000110 "OP_RFID"
+ attribute \enum_value_1000111 "OP_MFMSR"
+ attribute \enum_value_1001000 "OP_MTMSRD"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 7 output 22 \op__insn_type$2
+ attribute \enum_base_type "Function"
+ attribute \enum_value_00000000000 "NONE"
+ attribute \enum_value_00000000010 "ALU"
+ attribute \enum_value_00000000100 "LDST"
+ attribute \enum_value_00000001000 "SHIFT_ROT"
+ attribute \enum_value_00000010000 "LOGICAL"
+ attribute \enum_value_00000100000 "BRANCH"
+ attribute \enum_value_00001000000 "CR"
+ attribute \enum_value_00010000000 "TRAP"
+ attribute \enum_value_00100000000 "MUL"
+ attribute \enum_value_01000000000 "DIV"
+ attribute \enum_value_10000000000 "SPR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 11 output 23 \op__fn_unit$3
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 output 24 \op__imm_data__imm$4
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 25 \op__imm_data__imm_ok$5
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 26 \op__rc__rc$6
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 27 \op__rc__rc_ok$7
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 28 \op__oe__oe$8
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 29 \op__oe__oe_ok$9
+ attribute \enum_base_type "CryIn"
+ attribute \enum_value_00 "ZERO"
+ attribute \enum_value_01 "ONE"
+ attribute \enum_value_10 "CA"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 2 output 31 \op__input_carry$10
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 32 \op__output_carry$11
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 33 \op__input_cr$12
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 34 \op__output_cr$13
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 35 \op__is_32bit$14
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 36 \op__is_signed$15
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 output 37 \op__insn$16
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 64 output 38 \ra$17
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 64 output 39 \rb$18
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 64 output 40 \rc$19
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 2 output 41 \xer_ca$20
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20"
+ wire width 64 \a
+ process $group_0
+ assign \a 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \a \ra
+ sync init
+ end
+ process $group_1
+ assign \ra$17 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \ra$17 \a
+ sync init
+ end
+ process $group_2
+ assign \xer_ca$20 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:36"
+ switch \op__input_carry
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:37"
+ attribute \nmigen.decoding "ZERO/0"
+ case 2'00
+ assign \xer_ca$20 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:39"
+ attribute \nmigen.decoding "ONE/1"
+ case 2'01
+ assign \xer_ca$20 2'11
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:41"
+ attribute \nmigen.decoding "CA/2"
+ case 2'10
+ assign \xer_ca$20 \xer_ca
+ end
+ sync init
+ end
+ process $group_3
+ assign \muxid$1 2'00
+ assign \muxid$1 \muxid
+ sync init
+ end
+ process $group_4
+ assign \op__insn_type$2 7'0000000
+ assign \op__fn_unit$3 11'00000000000
+ assign \op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \op__imm_data__imm_ok$5 1'0
+ assign \op__rc__rc$6 1'0
+ assign \op__rc__rc_ok$7 1'0
+ assign \op__oe__oe$8 1'0
+ assign \op__oe__oe_ok$9 1'0
+ assign { } 0'0
+ assign \op__input_carry$10 2'00
+ assign \op__output_carry$11 1'0
+ assign \op__input_cr$12 1'0
+ assign \op__output_cr$13 1'0
+ assign \op__is_32bit$14 1'0
+ assign \op__is_signed$15 1'0
+ assign \op__insn$16 32'00000000000000000000000000000000
+ assign { \op__insn$16 \op__is_signed$15 \op__is_32bit$14 \op__output_cr$13 \op__input_cr$12 \op__output_carry$11 \op__input_carry$10 { } { \op__oe__oe_ok$9 \op__oe__oe$8 } { \op__rc__rc_ok$7 \op__rc__rc$6 } { \op__imm_data__imm_ok$5 \op__imm_data__imm$4 } \op__fn_unit$3 \op__insn_type$2 } { \op__insn \op__is_signed \op__is_32bit \op__output_cr \op__input_cr \op__output_carry \op__input_carry { } { \op__oe__oe_ok \op__oe__oe } { \op__rc__rc_ok \op__rc__rc } { \op__imm_data__imm_ok \op__imm_data__imm } \op__fn_unit \op__insn_type }
+ sync init
+ end
+ process $group_20
+ assign \rb$18 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \rb$18 \rb
+ sync init
+ end
+ process $group_21
+ assign \rc$19 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \rc$19 \rc
+ sync init
+ end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe.main.rotator.rotl"
+module \rotl
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:8"
+ wire width 64 input 0 \a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:9"
+ wire width 6 input 1 \b
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:11"
+ wire width 64 output 2 \o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:19"
+ wire width 64 $1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:18"
+ wire width 8 $2
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:18"
+ cell $sub $3
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 7
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 6
+ parameter \Y_WIDTH 8
+ connect \A 7'1000000
+ connect \B \b
+ connect \Y $2
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:19"
+ cell $shift $4
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 128
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 8
+ parameter \Y_WIDTH 64
+ connect \A { \a \a }
+ connect \B $2
+ connect \Y $1
+ end
+ process $group_0
+ assign \o 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \o $1
+ sync init
+ end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe.main.rotator"
+module \rotator
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:45"
+ wire width 5 input 0 \me
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:46"
+ wire width 5 input 1 \mb
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:47"
+ wire width 1 input 2 \mb_extra
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:49"
+ wire width 64 input 3 \rs
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:48"
+ wire width 64 input 4 \ra
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:50"
+ wire width 7 input 5 \shift
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:51"
+ wire width 1 input 6 \is_32bit
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:53"
+ wire width 1 input 7 \arith
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:52"
+ wire width 1 input 8 \right_shift
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:54"
+ wire width 1 input 9 \clear_left
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:55"
+ wire width 1 input 10 \clear_right
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:56"
+ wire width 1 input 11 \sign_ext_rs
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:58"
+ wire width 64 output 12 \result_o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:59"
+ wire width 1 output 13 \carry_out_o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:8"
+ wire width 64 \rotl_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:9"
+ wire width 6 \rotl_b
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:11"
+ wire width 64 \rotl_o
+ cell \rotl \rotl
+ connect \a \rotl_a
+ connect \b \rotl_b
+ connect \o \rotl_o
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:75"
+ wire width 32 \hi32
+ process $group_0
+ assign \hi32 32'00000000000000000000000000000000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:79"
+ switch { \sign_ext_rs \is_32bit }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:79"
+ case 2'-1
+ assign \hi32 \rs [31:0]
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:81"
+ case 2'1-
+ assign \hi32 { \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:84"
+ case
+ assign \hi32 \rs [63:32]
+ end
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:76"
+ wire width 64 \repl32
+ process $group_1
+ assign \repl32 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \repl32 { \hi32 \rs [31:0] }
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:88"
+ wire width 6 \shift_signed
+ process $group_2
+ assign \shift_signed 6'000000
+ assign \shift_signed \shift [5:0]
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:67"
+ wire width 6 \rot_count
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:93"
+ wire width 7 $1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:93"
+ wire width 7 $2
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:93"
+ cell $neg $3
+ parameter \A_SIGNED 1
+ parameter \A_WIDTH 6
+ parameter \Y_WIDTH 7
+ connect \A \shift_signed
+ connect \Y $2
+ end
+ connect $1 $2
+ process $group_3
+ assign \rot_count 6'000000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:92"
+ switch { \right_shift }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:92"
+ case 1'1
+ assign \rot_count $1 [5:0]
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:94"
+ case
+ assign \rot_count \shift [5:0]
+ end
+ sync init
+ end
+ process $group_4
+ assign \rotl_a 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \rotl_a \repl32
+ sync init
+ end
+ process $group_5
+ assign \rotl_b 6'000000
+ assign \rotl_b \rot_count
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:68"
+ wire width 64 \rot
+ process $group_6
+ assign \rot 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \rot \rotl_o
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:69"
+ wire width 7 \sh
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:104"
+ wire width 1 $4
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:104"
+ cell $not $5
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \is_32bit
+ connect \Y $4
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:104"
+ wire width 1 $6
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:104"
+ cell $and $7
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \shift [6]
+ connect \B $4
+ connect \Y $6
+ end
+ process $group_7
+ assign \sh 7'0000000
+ assign \sh { $6 \shift [5:0] }
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:70"
+ wire width 7 \mb$8
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:46"
+ wire width 7 $9
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:46"
+ cell $pos $10
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 5
+ parameter \Y_WIDTH 7
+ connect \A \mb
+ connect \Y $9
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:120"
+ wire width 1 $11
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:120"
+ cell $not $12
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \sh [5]
+ connect \Y $11
+ end
+ process $group_8
+ assign \mb$8 7'0000000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:110"
+ switch { \right_shift \clear_left }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:110"
+ case 2'-1
+ assign \mb$8 $9
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:112"
+ switch { \is_32bit }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:112"
+ case 1'1
+ assign \mb$8 [6:5] 2'01
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:114"
+ case
+ assign \mb$8 [6:5] { 1'0 \mb_extra }
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:116"
+ case 2'1-
+ assign \mb$8 \sh
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:119"
+ switch { \is_32bit }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:119"
+ case 1'1
+ assign \mb$8 [6:5] { \sh [5] $11 }
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:121"
+ case
+ assign \mb$8 { 1'0 \is_32bit 5'00000 }
+ end
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:71"
+ wire width 7 \me$13
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:125"
+ wire width 1 $14
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:125"
+ cell $and $15
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \clear_right
+ connect \B \is_32bit
+ connect \Y $14
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:128"
+ wire width 1 $16
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:128"
+ cell $not $17
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \clear_left
+ connect \Y $16
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:128"
+ wire width 1 $18
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:128"
+ cell $and $19
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \clear_right
+ connect \B $16
+ connect \Y $18
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:133"
+ wire width 6 $20
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:133"
+ cell $not $21
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 6
+ parameter \Y_WIDTH 6
+ connect \A \sh [5:0]
+ connect \Y $20
+ end
+ process $group_9
+ assign \me$13 7'0000000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:125"
+ switch { $18 $14 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:125"
+ case 2'-1
+ assign \me$13 { 2'01 \me }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:128"
+ case 2'1-
+ assign \me$13 { 1'0 \mb_extra \mb }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:131"
+ case
+ assign \me$13 { \sh [6] $20 }
+ end
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:14"
+ wire width 64 \right_mask
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:15"
+ wire width 1 $22
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:15"
+ cell $le $23
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 7
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 7
+ parameter \Y_WIDTH 1
+ connect \A \mb$8
+ connect \B 7'1000000
+ connect \Y $22
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:16"
+ wire width 257 $24
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:16"
+ wire width 8 $25
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:16"
+ cell $sub $26
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 7
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 7
+ parameter \Y_WIDTH 8
+ connect \A 7'1000000
+ connect \B \mb$8
+ connect \Y $25
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:16"
+ wire width 256 $27
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:16"
+ cell $sshl $28
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 8
+ parameter \Y_WIDTH 256
+ connect \A 1'1
+ connect \B $25
+ connect \Y $27
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:16"
+ wire width 257 $29
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:16"
+ cell $sub $30
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 256
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 257
+ connect \A $27
+ connect \B 1'1
+ connect \Y $29
+ end
+ connect $24 $29
+ process $group_10
+ assign \right_mask 64'0000000000000000000000000000000000000000000000000000000000000000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:15"
+ switch { $22 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:15"
+ case 1'1
+ assign \right_mask $24 [63:0]
+ end
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:72"
+ wire width 64 \mr
+ process $group_11
+ assign \mr 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \mr \right_mask
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:20"
+ wire width 64 \left_mask
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:21"
+ wire width 257 $31
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:21"
+ wire width 257 $32
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:21"
+ wire width 8 $33
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:21"
+ cell $sub $34
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 6
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 7
+ parameter \Y_WIDTH 8
+ connect \A 6'111111
+ connect \B \me$13
+ connect \Y $33
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:21"
+ wire width 256 $35
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:21"
+ cell $sshl $36
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 8
+ parameter \Y_WIDTH 256
+ connect \A 1'1
+ connect \B $33
+ connect \Y $35
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:21"
+ wire width 257 $37
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:21"
+ cell $sub $38
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 256
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 257
+ connect \A $35
+ connect \B 1'1
+ connect \Y $37
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:21"
+ cell $not $39
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 257
+ parameter \Y_WIDTH 257
+ connect \A $37
+ connect \Y $32
+ end
+ connect $31 $32
+ process $group_12
+ assign \left_mask 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \left_mask $31 [63:0]
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:73"
+ wire width 64 \ml
+ process $group_13
+ assign \ml 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \ml \left_mask
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:74"
+ wire width 2 \output_mode
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:144"
+ wire width 1 $40
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:144"
+ cell $not $41
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \clear_right
+ connect \Y $40
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:144"
+ wire width 1 $42
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:144"
+ cell $and $43
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \clear_left
+ connect \B $40
+ connect \Y $42
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:144"
+ wire width 1 $44
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:144"
+ cell $or $45
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A $42
+ connect \B \right_shift
+ connect \Y $44
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:145"
+ wire width 1 $46
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:145"
+ cell $and $47
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \arith
+ connect \B \repl32 [63]
+ connect \Y $46
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:147"
+ wire width 1 $48
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:147"
+ cell $gt $49
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 6
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 6
+ parameter \Y_WIDTH 1
+ connect \A \mb$8 [5:0]
+ connect \B \me$13 [5:0]
+ connect \Y $48
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:147"
+ wire width 1 $50
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:147"
+ cell $and $51
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \clear_right
+ connect \B $48
+ connect \Y $50
+ end
+ process $group_14
+ assign \output_mode 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:144"
+ switch { $44 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:144"
+ case 1'1
+ assign \output_mode { 1'1 $46 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:146"
+ case
+ assign \output_mode { 1'0 $50 }
+ end
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:153"
+ wire width 64 $52
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:153"
+ cell $and $53
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 64
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 64
+ parameter \Y_WIDTH 64
+ connect \A \mr
+ connect \B \ml
+ connect \Y $52
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:153"
+ wire width 64 $54
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:153"
+ cell $and $55
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 64
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 64
+ parameter \Y_WIDTH 64
+ connect \A \rot
+ connect \B $52
+ connect \Y $54
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:153"
+ wire width 64 $56
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:153"
+ wire width 64 $57
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:153"
+ cell $and $58
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 64
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 64
+ parameter \Y_WIDTH 64
+ connect \A \mr
+ connect \B \ml
+ connect \Y $57
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:153"
+ cell $not $59
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 64
+ parameter \Y_WIDTH 64
+ connect \A $57
+ connect \Y $56
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:153"
+ wire width 64 $60
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:153"
+ cell $and $61
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 64
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 64
+ parameter \Y_WIDTH 64
+ connect \A \ra
+ connect \B $56
+ connect \Y $60
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:153"
+ wire width 64 $62
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:153"
+ cell $or $63
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 64
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 64
+ parameter \Y_WIDTH 64
+ connect \A $54
+ connect \B $60
+ connect \Y $62
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:155"
+ wire width 64 $64
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:155"
+ cell $or $65
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 64
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 64
+ parameter \Y_WIDTH 64
+ connect \A \mr
+ connect \B \ml
+ connect \Y $64
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:155"
+ wire width 64 $66
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:155"
+ cell $and $67
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 64
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 64
+ parameter \Y_WIDTH 64
+ connect \A \rot
+ connect \B $64
+ connect \Y $66
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:155"
+ wire width 64 $68
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:155"
+ wire width 64 $69
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:155"
+ cell $or $70
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 64
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 64
+ parameter \Y_WIDTH 64
+ connect \A \mr
+ connect \B \ml
+ connect \Y $69
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:155"
+ cell $not $71
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 64
+ parameter \Y_WIDTH 64
+ connect \A $69
+ connect \Y $68
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:155"
+ wire width 64 $72
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:155"
+ cell $and $73
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 64
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 64
+ parameter \Y_WIDTH 64
+ connect \A \ra
+ connect \B $68
+ connect \Y $72
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:155"
+ wire width 64 $74
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:155"
+ cell $or $75
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 64
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 64
+ parameter \Y_WIDTH 64
+ connect \A $66
+ connect \B $72
+ connect \Y $74
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:157"
+ wire width 64 $76
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:157"
+ cell $and $77
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 64
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 64
+ parameter \Y_WIDTH 64
+ connect \A \rot
+ connect \B \mr
+ connect \Y $76
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:159"
+ wire width 64 $78
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:159"
+ cell $not $79
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 64
+ parameter \Y_WIDTH 64
+ connect \A \mr
+ connect \Y $78
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:159"
+ wire width 64 $80
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:159"
+ cell $or $81
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 64
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 64
+ parameter \Y_WIDTH 64
+ connect \A \rot
+ connect \B $78
+ connect \Y $80
+ end
+ process $group_15
+ assign \result_o 64'0000000000000000000000000000000000000000000000000000000000000000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:151"
+ switch \output_mode
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:152"
+ case 2'00
+ assign \result_o $62
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:154"
+ case 2'01
+ assign \result_o $74
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:156"
+ case 2'10
+ assign \result_o $76
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:158"
+ case 2'11
+ assign \result_o $80
+ end
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:161"
+ wire width 1 $82
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:161"
+ wire width 64 $83
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:161"
+ cell $not $84
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 64
+ parameter \Y_WIDTH 64
+ connect \A \ml
+ connect \Y $83
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:161"
+ wire width 64 $85
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:161"
+ cell $and $86
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 64
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 64
+ parameter \Y_WIDTH 64
+ connect \A \rs
+ connect \B $83
+ connect \Y $85
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:161"
+ cell $reduce_bool $87
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 64
+ parameter \Y_WIDTH 1
+ connect \A $85
+ connect \Y $82
+ end
+ process $group_16
+ assign \carry_out_o 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:151"
+ switch \output_mode
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:152"
+ case 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:154"
+ case 2'01
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:156"
+ case 2'10
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:158"
+ case 2'11
+ assign \carry_out_o $82
+ end
+ sync init
+ end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe.main"
+module \main$93
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+ wire width 2 input 0 \muxid
+ attribute \enum_base_type "MicrOp"
+ attribute \enum_value_0000000 "OP_ILLEGAL"
+ attribute \enum_value_0000001 "OP_NOP"
+ attribute \enum_value_0000010 "OP_ADD"
+ attribute \enum_value_0000011 "OP_ADDPCIS"
+ attribute \enum_value_0000100 "OP_AND"
+ attribute \enum_value_0000101 "OP_ATTN"
+ attribute \enum_value_0000110 "OP_B"
+ attribute \enum_value_0000111 "OP_BC"
+ attribute \enum_value_0001000 "OP_BCREG"
+ attribute \enum_value_0001001 "OP_BPERM"
+ attribute \enum_value_0001010 "OP_CMP"
+ attribute \enum_value_0001011 "OP_CMPB"
+ attribute \enum_value_0001100 "OP_CMPEQB"
+ attribute \enum_value_0001101 "OP_CMPRB"
+ attribute \enum_value_0001110 "OP_CNTZ"
+ attribute \enum_value_0001111 "OP_CRAND"
+ attribute \enum_value_0010000 "OP_CRANDC"
+ attribute \enum_value_0010001 "OP_CREQV"
+ attribute \enum_value_0010010 "OP_CRNAND"
+ attribute \enum_value_0010011 "OP_CRNOR"
+ attribute \enum_value_0010100 "OP_CROR"
+ attribute \enum_value_0010101 "OP_CRORC"
+ attribute \enum_value_0010110 "OP_CRXOR"
+ attribute \enum_value_0010111 "OP_DARN"
+ attribute \enum_value_0011000 "OP_DCBF"
+ attribute \enum_value_0011001 "OP_DCBST"
+ attribute \enum_value_0011010 "OP_DCBT"
+ attribute \enum_value_0011011 "OP_DCBTST"
+ attribute \enum_value_0011100 "OP_DCBZ"
+ attribute \enum_value_0011101 "OP_DIV"
+ attribute \enum_value_0011110 "OP_DIVE"
+ attribute \enum_value_0011111 "OP_EXTS"
+ attribute \enum_value_0100000 "OP_EXTSWSLI"
+ attribute \enum_value_0100001 "OP_ICBI"
+ attribute \enum_value_0100010 "OP_ICBT"
+ attribute \enum_value_0100011 "OP_ISEL"
+ attribute \enum_value_0100100 "OP_ISYNC"
+ attribute \enum_value_0100101 "OP_LOAD"
+ attribute \enum_value_0100110 "OP_STORE"
+ attribute \enum_value_0100111 "OP_MADDHD"
+ attribute \enum_value_0101000 "OP_MADDHDU"
+ attribute \enum_value_0101001 "OP_MADDLD"
+ attribute \enum_value_0101010 "OP_MCRF"
+ attribute \enum_value_0101011 "OP_MCRXR"
+ attribute \enum_value_0101100 "OP_MCRXRX"
+ attribute \enum_value_0101101 "OP_MFCR"
+ attribute \enum_value_0101110 "OP_MFSPR"
+ attribute \enum_value_0101111 "OP_MOD"
+ attribute \enum_value_0110000 "OP_MTCRF"
+ attribute \enum_value_0110001 "OP_MTSPR"
+ attribute \enum_value_0110010 "OP_MUL_L64"
+ attribute \enum_value_0110011 "OP_MUL_H64"
+ attribute \enum_value_0110100 "OP_MUL_H32"
+ attribute \enum_value_0110101 "OP_OR"
+ attribute \enum_value_0110110 "OP_POPCNT"
+ attribute \enum_value_0110111 "OP_PRTY"
+ attribute \enum_value_0111000 "OP_RLC"
+ attribute \enum_value_0111001 "OP_RLCL"
+ attribute \enum_value_0111010 "OP_RLCR"
+ attribute \enum_value_0111011 "OP_SETB"
+ attribute \enum_value_0111100 "OP_SHL"
+ attribute \enum_value_0111101 "OP_SHR"
+ attribute \enum_value_0111110 "OP_SYNC"
+ attribute \enum_value_0111111 "OP_TRAP"
+ attribute \enum_value_1000011 "OP_XOR"
+ attribute \enum_value_1000100 "OP_SIM_CONFIG"
+ attribute \enum_value_1000101 "OP_CROP"
+ attribute \enum_value_1000110 "OP_RFID"
+ attribute \enum_value_1000111 "OP_MFMSR"
+ attribute \enum_value_1001000 "OP_MTMSRD"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 7 input 1 \op__insn_type
+ attribute \enum_base_type "Function"
+ attribute \enum_value_00000000000 "NONE"
+ attribute \enum_value_00000000010 "ALU"
+ attribute \enum_value_00000000100 "LDST"
+ attribute \enum_value_00000001000 "SHIFT_ROT"
+ attribute \enum_value_00000010000 "LOGICAL"
+ attribute \enum_value_00000100000 "BRANCH"
+ attribute \enum_value_00001000000 "CR"
+ attribute \enum_value_00010000000 "TRAP"
+ attribute \enum_value_00100000000 "MUL"
+ attribute \enum_value_01000000000 "DIV"
+ attribute \enum_value_10000000000 "SPR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 11 input 2 \op__fn_unit
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 input 3 \op__imm_data__imm
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 4 \op__imm_data__imm_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 5 \op__rc__rc
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 6 \op__rc__rc_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 7 \op__oe__oe
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 8 \op__oe__oe_ok
+ attribute \enum_base_type "CryIn"
+ attribute \enum_value_00 "ZERO"
+ attribute \enum_value_01 "ONE"
+ attribute \enum_value_10 "CA"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 2 input 10 \op__input_carry
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 11 \op__output_carry
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 12 \op__input_cr
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 13 \op__output_cr
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 14 \op__is_32bit
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 15 \op__is_signed
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 input 16 \op__insn
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 64 input 17 \ra
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 64 input 18 \rb
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 64 input 19 \rc
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+ wire width 2 output 20 \muxid$1
+ attribute \enum_base_type "MicrOp"
+ attribute \enum_value_0000000 "OP_ILLEGAL"
+ attribute \enum_value_0000001 "OP_NOP"
+ attribute \enum_value_0000010 "OP_ADD"
+ attribute \enum_value_0000011 "OP_ADDPCIS"
+ attribute \enum_value_0000100 "OP_AND"
+ attribute \enum_value_0000101 "OP_ATTN"
+ attribute \enum_value_0000110 "OP_B"
+ attribute \enum_value_0000111 "OP_BC"
+ attribute \enum_value_0001000 "OP_BCREG"
+ attribute \enum_value_0001001 "OP_BPERM"
+ attribute \enum_value_0001010 "OP_CMP"
+ attribute \enum_value_0001011 "OP_CMPB"
+ attribute \enum_value_0001100 "OP_CMPEQB"
+ attribute \enum_value_0001101 "OP_CMPRB"
+ attribute \enum_value_0001110 "OP_CNTZ"
+ attribute \enum_value_0001111 "OP_CRAND"
+ attribute \enum_value_0010000 "OP_CRANDC"
+ attribute \enum_value_0010001 "OP_CREQV"
+ attribute \enum_value_0010010 "OP_CRNAND"
+ attribute \enum_value_0010011 "OP_CRNOR"
+ attribute \enum_value_0010100 "OP_CROR"
+ attribute \enum_value_0010101 "OP_CRORC"
+ attribute \enum_value_0010110 "OP_CRXOR"
+ attribute \enum_value_0010111 "OP_DARN"
+ attribute \enum_value_0011000 "OP_DCBF"
+ attribute \enum_value_0011001 "OP_DCBST"
+ attribute \enum_value_0011010 "OP_DCBT"
+ attribute \enum_value_0011011 "OP_DCBTST"
+ attribute \enum_value_0011100 "OP_DCBZ"
+ attribute \enum_value_0011101 "OP_DIV"
+ attribute \enum_value_0011110 "OP_DIVE"
+ attribute \enum_value_0011111 "OP_EXTS"
+ attribute \enum_value_0100000 "OP_EXTSWSLI"
+ attribute \enum_value_0100001 "OP_ICBI"
+ attribute \enum_value_0100010 "OP_ICBT"
+ attribute \enum_value_0100011 "OP_ISEL"
+ attribute \enum_value_0100100 "OP_ISYNC"
+ attribute \enum_value_0100101 "OP_LOAD"
+ attribute \enum_value_0100110 "OP_STORE"
+ attribute \enum_value_0100111 "OP_MADDHD"
+ attribute \enum_value_0101000 "OP_MADDHDU"
+ attribute \enum_value_0101001 "OP_MADDLD"
+ attribute \enum_value_0101010 "OP_MCRF"
+ attribute \enum_value_0101011 "OP_MCRXR"
+ attribute \enum_value_0101100 "OP_MCRXRX"
+ attribute \enum_value_0101101 "OP_MFCR"
+ attribute \enum_value_0101110 "OP_MFSPR"
+ attribute \enum_value_0101111 "OP_MOD"
+ attribute \enum_value_0110000 "OP_MTCRF"
+ attribute \enum_value_0110001 "OP_MTSPR"
+ attribute \enum_value_0110010 "OP_MUL_L64"
+ attribute \enum_value_0110011 "OP_MUL_H64"
+ attribute \enum_value_0110100 "OP_MUL_H32"
+ attribute \enum_value_0110101 "OP_OR"
+ attribute \enum_value_0110110 "OP_POPCNT"
+ attribute \enum_value_0110111 "OP_PRTY"
+ attribute \enum_value_0111000 "OP_RLC"
+ attribute \enum_value_0111001 "OP_RLCL"
+ attribute \enum_value_0111010 "OP_RLCR"
+ attribute \enum_value_0111011 "OP_SETB"
+ attribute \enum_value_0111100 "OP_SHL"
+ attribute \enum_value_0111101 "OP_SHR"
+ attribute \enum_value_0111110 "OP_SYNC"
+ attribute \enum_value_0111111 "OP_TRAP"
+ attribute \enum_value_1000011 "OP_XOR"
+ attribute \enum_value_1000100 "OP_SIM_CONFIG"
+ attribute \enum_value_1000101 "OP_CROP"
+ attribute \enum_value_1000110 "OP_RFID"
+ attribute \enum_value_1000111 "OP_MFMSR"
+ attribute \enum_value_1001000 "OP_MTMSRD"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 7 output 21 \op__insn_type$2
+ attribute \enum_base_type "Function"
+ attribute \enum_value_00000000000 "NONE"
+ attribute \enum_value_00000000010 "ALU"
+ attribute \enum_value_00000000100 "LDST"
+ attribute \enum_value_00000001000 "SHIFT_ROT"
+ attribute \enum_value_00000010000 "LOGICAL"
+ attribute \enum_value_00000100000 "BRANCH"
+ attribute \enum_value_00001000000 "CR"
+ attribute \enum_value_00010000000 "TRAP"
+ attribute \enum_value_00100000000 "MUL"
+ attribute \enum_value_01000000000 "DIV"
+ attribute \enum_value_10000000000 "SPR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 11 output 22 \op__fn_unit$3
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 output 23 \op__imm_data__imm$4
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 24 \op__imm_data__imm_ok$5
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 25 \op__rc__rc$6
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 26 \op__rc__rc_ok$7
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 27 \op__oe__oe$8
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 28 \op__oe__oe_ok$9
+ attribute \enum_base_type "CryIn"
+ attribute \enum_value_00 "ZERO"
+ attribute \enum_value_01 "ONE"
+ attribute \enum_value_10 "CA"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 2 output 30 \op__input_carry$10
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 31 \op__output_carry$11
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 32 \op__input_cr$12
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 33 \op__output_cr$13
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 34 \op__is_32bit$14
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 35 \op__is_signed$15
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 output 36 \op__insn$16
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 64 output 37 \o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 38 \o_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 2 output 39 \xer_ca
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:45"
+ wire width 5 \rotator_me
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:46"
+ wire width 5 \rotator_mb
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:47"
+ wire width 1 \rotator_mb_extra
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:49"
+ wire width 64 \rotator_rs
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:48"
+ wire width 64 \rotator_ra
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:50"
+ wire width 7 \rotator_shift
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:51"
+ wire width 1 \rotator_is_32bit
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:53"
+ wire width 1 \rotator_arith
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:52"
+ wire width 1 \rotator_right_shift
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:54"
+ wire width 1 \rotator_clear_left
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:55"
+ wire width 1 \rotator_clear_right
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:56"
+ wire width 1 \rotator_sign_ext_rs
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:58"
+ wire width 64 \rotator_result_o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:59"
+ wire width 1 \rotator_carry_out_o
+ cell \rotator \rotator
+ connect \me \rotator_me
+ connect \mb \rotator_mb
+ connect \mb_extra \rotator_mb_extra
+ connect \rs \rotator_rs
+ connect \ra \rotator_ra
+ connect \shift \rotator_shift
+ connect \is_32bit \rotator_is_32bit
+ connect \arith \rotator_arith
+ connect \right_shift \rotator_right_shift
+ connect \clear_left \rotator_clear_left
+ connect \clear_right \rotator_clear_right
+ connect \sign_ext_rs \rotator_sign_ext_rs
+ connect \result_o \rotator_result_o
+ connect \carry_out_o \rotator_carry_out_o
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:42"
+ wire width 5 \mb
+ process $group_0
+ assign \mb 5'00000
+ assign \mb { \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] }
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:43"
+ wire width 5 \me
+ process $group_1
+ assign \me 5'00000
+ assign \me { \op__insn [5] \op__insn [4] \op__insn [3] \op__insn [2] \op__insn [1] }
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:44"
+ wire width 1 \mb_extra
+ process $group_2
+ assign \mb_extra 1'0
+ assign \mb_extra { \op__insn [10] \op__insn [9] \op__insn [8] \op__insn [7] \op__insn [6] \op__insn [5] } [0]
+ sync init
+ end
+ process $group_3
+ assign \rotator_me 5'00000
+ assign \rotator_me \me
+ sync init
+ end
+ process $group_4
+ assign \rotator_mb 5'00000
+ assign \rotator_mb \mb
+ sync init
+ end
+ process $group_5
+ assign \rotator_mb_extra 1'0
+ assign \rotator_mb_extra \mb_extra
+ sync init
+ end
+ process $group_6
+ assign \rotator_rs 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \rotator_rs \rc
+ sync init
+ end
+ process $group_7
+ assign \rotator_ra 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \rotator_ra \ra
+ sync init
+ end
+ process $group_8
+ assign \rotator_shift 7'0000000
+ assign \rotator_shift \rb [6:0]
+ sync init
+ end
+ process $group_9
+ assign \rotator_is_32bit 1'0
+ assign \rotator_is_32bit \op__is_32bit
+ sync init
+ end
+ process $group_10
+ assign \rotator_arith 1'0
+ assign \rotator_arith \op__is_signed
+ sync init
+ end
+ process $group_11
+ assign \o_ok 1'0
+ assign \o_ok 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:66"
+ switch \op__insn_type
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:67"
+ attribute \nmigen.decoding "OP_SHL/60"
+ case 7'0111100
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:68"
+ attribute \nmigen.decoding "OP_SHR/61"
+ case 7'0111101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:69"
+ attribute \nmigen.decoding "OP_RLC/56"
+ case 7'0111000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:70"
+ attribute \nmigen.decoding "OP_RLCL/57"
+ case 7'0111001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:71"
+ attribute \nmigen.decoding "OP_RLCR/58"
+ case 7'0111010
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:72"
+ attribute \nmigen.decoding "OP_EXTSWSLI/32"
+ case 7'0100000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:73"
+ attribute \nmigen.decoding ""
+ case
+ assign \o_ok 1'0
+ end
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:65"
+ wire width 4 \mode
+ process $group_12
+ assign \mode 4'0000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:66"
+ switch \op__insn_type
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:67"
+ attribute \nmigen.decoding "OP_SHL/60"
+ case 7'0111100
+ assign \mode 4'0000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:68"
+ attribute \nmigen.decoding "OP_SHR/61"
+ case 7'0111101
+ assign \mode 4'0001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:69"
+ attribute \nmigen.decoding "OP_RLC/56"
+ case 7'0111000
+ assign \mode 4'0110
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:70"
+ attribute \nmigen.decoding "OP_RLCL/57"
+ case 7'0111001
+ assign \mode 4'0010
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:71"
+ attribute \nmigen.decoding "OP_RLCR/58"
+ case 7'0111010
+ assign \mode 4'0100
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:72"
+ attribute \nmigen.decoding "OP_EXTSWSLI/32"
+ case 7'0100000
+ assign \mode 4'1000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:73"
+ attribute \nmigen.decoding ""
+ case
+ end
+ sync init
+ end
+ process $group_13
+ assign \rotator_right_shift 1'0
+ assign \rotator_clear_left 1'0
+ assign \rotator_clear_right 1'0
+ assign \rotator_sign_ext_rs 1'0
+ assign { \rotator_sign_ext_rs \rotator_clear_right \rotator_clear_left \rotator_right_shift } \mode
+ sync init
+ end
+ process $group_17
+ assign \o 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \o \rotator_result_o
+ sync init
+ end
+ process $group_18
+ assign \xer_ca 2'00
+ assign \xer_ca { \rotator_carry_out_o \rotator_carry_out_o }
+ sync init
+ end
+ process $group_19
+ assign \muxid$1 2'00
+ assign \muxid$1 \muxid
+ sync init
+ end
+ process $group_20
+ assign \op__insn_type$2 7'0000000
+ assign \op__fn_unit$3 11'00000000000
+ assign \op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \op__imm_data__imm_ok$5 1'0
+ assign \op__rc__rc$6 1'0
+ assign \op__rc__rc_ok$7 1'0
+ assign \op__oe__oe$8 1'0
+ assign \op__oe__oe_ok$9 1'0
+ assign { } 0'0
+ assign \op__input_carry$10 2'00
+ assign \op__output_carry$11 1'0
+ assign \op__input_cr$12 1'0
+ assign \op__output_cr$13 1'0
+ assign \op__is_32bit$14 1'0
+ assign \op__is_signed$15 1'0
+ assign \op__insn$16 32'00000000000000000000000000000000
+ assign { \op__insn$16 \op__is_signed$15 \op__is_32bit$14 \op__output_cr$13 \op__input_cr$12 \op__output_carry$11 \op__input_carry$10 { } { \op__oe__oe_ok$9 \op__oe__oe$8 } { \op__rc__rc_ok$7 \op__rc__rc$6 } { \op__imm_data__imm_ok$5 \op__imm_data__imm$4 } \op__fn_unit$3 \op__insn_type$2 } { \op__insn \op__is_signed \op__is_32bit \op__output_cr \op__input_cr \op__output_carry \op__input_carry { } { \op__oe__oe_ok \op__oe__oe } { \op__rc__rc_ok \op__rc__rc } { \op__imm_data__imm_ok \op__imm_data__imm } \op__fn_unit \op__insn_type }
+ sync init
+ end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe.output"
+module \output$94
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+ wire width 2 input 0 \muxid
+ attribute \enum_base_type "MicrOp"
+ attribute \enum_value_0000000 "OP_ILLEGAL"
+ attribute \enum_value_0000001 "OP_NOP"
+ attribute \enum_value_0000010 "OP_ADD"
+ attribute \enum_value_0000011 "OP_ADDPCIS"
+ attribute \enum_value_0000100 "OP_AND"
+ attribute \enum_value_0000101 "OP_ATTN"
+ attribute \enum_value_0000110 "OP_B"
+ attribute \enum_value_0000111 "OP_BC"
+ attribute \enum_value_0001000 "OP_BCREG"
+ attribute \enum_value_0001001 "OP_BPERM"
+ attribute \enum_value_0001010 "OP_CMP"
+ attribute \enum_value_0001011 "OP_CMPB"
+ attribute \enum_value_0001100 "OP_CMPEQB"
+ attribute \enum_value_0001101 "OP_CMPRB"
+ attribute \enum_value_0001110 "OP_CNTZ"
+ attribute \enum_value_0001111 "OP_CRAND"
+ attribute \enum_value_0010000 "OP_CRANDC"
+ attribute \enum_value_0010001 "OP_CREQV"
+ attribute \enum_value_0010010 "OP_CRNAND"
+ attribute \enum_value_0010011 "OP_CRNOR"
+ attribute \enum_value_0010100 "OP_CROR"
+ attribute \enum_value_0010101 "OP_CRORC"
+ attribute \enum_value_0010110 "OP_CRXOR"
+ attribute \enum_value_0010111 "OP_DARN"
+ attribute \enum_value_0011000 "OP_DCBF"
+ attribute \enum_value_0011001 "OP_DCBST"
+ attribute \enum_value_0011010 "OP_DCBT"
+ attribute \enum_value_0011011 "OP_DCBTST"
+ attribute \enum_value_0011100 "OP_DCBZ"
+ attribute \enum_value_0011101 "OP_DIV"
+ attribute \enum_value_0011110 "OP_DIVE"
+ attribute \enum_value_0011111 "OP_EXTS"
+ attribute \enum_value_0100000 "OP_EXTSWSLI"
+ attribute \enum_value_0100001 "OP_ICBI"
+ attribute \enum_value_0100010 "OP_ICBT"
+ attribute \enum_value_0100011 "OP_ISEL"
+ attribute \enum_value_0100100 "OP_ISYNC"
+ attribute \enum_value_0100101 "OP_LOAD"
+ attribute \enum_value_0100110 "OP_STORE"
+ attribute \enum_value_0100111 "OP_MADDHD"
+ attribute \enum_value_0101000 "OP_MADDHDU"
+ attribute \enum_value_0101001 "OP_MADDLD"
+ attribute \enum_value_0101010 "OP_MCRF"
+ attribute \enum_value_0101011 "OP_MCRXR"
+ attribute \enum_value_0101100 "OP_MCRXRX"
+ attribute \enum_value_0101101 "OP_MFCR"
+ attribute \enum_value_0101110 "OP_MFSPR"
+ attribute \enum_value_0101111 "OP_MOD"
+ attribute \enum_value_0110000 "OP_MTCRF"
+ attribute \enum_value_0110001 "OP_MTSPR"
+ attribute \enum_value_0110010 "OP_MUL_L64"
+ attribute \enum_value_0110011 "OP_MUL_H64"
+ attribute \enum_value_0110100 "OP_MUL_H32"
+ attribute \enum_value_0110101 "OP_OR"
+ attribute \enum_value_0110110 "OP_POPCNT"
+ attribute \enum_value_0110111 "OP_PRTY"
+ attribute \enum_value_0111000 "OP_RLC"
+ attribute \enum_value_0111001 "OP_RLCL"
+ attribute \enum_value_0111010 "OP_RLCR"
+ attribute \enum_value_0111011 "OP_SETB"
+ attribute \enum_value_0111100 "OP_SHL"
+ attribute \enum_value_0111101 "OP_SHR"
+ attribute \enum_value_0111110 "OP_SYNC"
+ attribute \enum_value_0111111 "OP_TRAP"
+ attribute \enum_value_1000011 "OP_XOR"
+ attribute \enum_value_1000100 "OP_SIM_CONFIG"
+ attribute \enum_value_1000101 "OP_CROP"
+ attribute \enum_value_1000110 "OP_RFID"
+ attribute \enum_value_1000111 "OP_MFMSR"
+ attribute \enum_value_1001000 "OP_MTMSRD"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 7 input 1 \op__insn_type
+ attribute \enum_base_type "Function"
+ attribute \enum_value_00000000000 "NONE"
+ attribute \enum_value_00000000010 "ALU"
+ attribute \enum_value_00000000100 "LDST"
+ attribute \enum_value_00000001000 "SHIFT_ROT"
+ attribute \enum_value_00000010000 "LOGICAL"
+ attribute \enum_value_00000100000 "BRANCH"
+ attribute \enum_value_00001000000 "CR"
+ attribute \enum_value_00010000000 "TRAP"
+ attribute \enum_value_00100000000 "MUL"
+ attribute \enum_value_01000000000 "DIV"
+ attribute \enum_value_10000000000 "SPR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 11 input 2 \op__fn_unit
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 input 3 \op__imm_data__imm
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 4 \op__imm_data__imm_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 5 \op__rc__rc
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 6 \op__rc__rc_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 7 \op__oe__oe
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 8 \op__oe__oe_ok
+ attribute \enum_base_type "CryIn"
+ attribute \enum_value_00 "ZERO"
+ attribute \enum_value_01 "ONE"
+ attribute \enum_value_10 "CA"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 2 input 10 \op__input_carry
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 11 \op__output_carry
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 12 \op__input_cr
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 13 \op__output_cr
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 14 \op__is_32bit
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 15 \op__is_signed
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 input 16 \op__insn
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 64 input 17 \o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 input 18 \o_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 4 input 19 \cr_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 2 input 20 \xer_ca
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+ wire width 2 output 21 \muxid$1
+ attribute \enum_base_type "MicrOp"
+ attribute \enum_value_0000000 "OP_ILLEGAL"
+ attribute \enum_value_0000001 "OP_NOP"
+ attribute \enum_value_0000010 "OP_ADD"
+ attribute \enum_value_0000011 "OP_ADDPCIS"
+ attribute \enum_value_0000100 "OP_AND"
+ attribute \enum_value_0000101 "OP_ATTN"
+ attribute \enum_value_0000110 "OP_B"
+ attribute \enum_value_0000111 "OP_BC"
+ attribute \enum_value_0001000 "OP_BCREG"
+ attribute \enum_value_0001001 "OP_BPERM"
+ attribute \enum_value_0001010 "OP_CMP"
+ attribute \enum_value_0001011 "OP_CMPB"
+ attribute \enum_value_0001100 "OP_CMPEQB"
+ attribute \enum_value_0001101 "OP_CMPRB"
+ attribute \enum_value_0001110 "OP_CNTZ"
+ attribute \enum_value_0001111 "OP_CRAND"
+ attribute \enum_value_0010000 "OP_CRANDC"
+ attribute \enum_value_0010001 "OP_CREQV"
+ attribute \enum_value_0010010 "OP_CRNAND"
+ attribute \enum_value_0010011 "OP_CRNOR"
+ attribute \enum_value_0010100 "OP_CROR"
+ attribute \enum_value_0010101 "OP_CRORC"
+ attribute \enum_value_0010110 "OP_CRXOR"
+ attribute \enum_value_0010111 "OP_DARN"
+ attribute \enum_value_0011000 "OP_DCBF"
+ attribute \enum_value_0011001 "OP_DCBST"
+ attribute \enum_value_0011010 "OP_DCBT"
+ attribute \enum_value_0011011 "OP_DCBTST"
+ attribute \enum_value_0011100 "OP_DCBZ"
+ attribute \enum_value_0011101 "OP_DIV"
+ attribute \enum_value_0011110 "OP_DIVE"
+ attribute \enum_value_0011111 "OP_EXTS"
+ attribute \enum_value_0100000 "OP_EXTSWSLI"
+ attribute \enum_value_0100001 "OP_ICBI"
+ attribute \enum_value_0100010 "OP_ICBT"
+ attribute \enum_value_0100011 "OP_ISEL"
+ attribute \enum_value_0100100 "OP_ISYNC"
+ attribute \enum_value_0100101 "OP_LOAD"
+ attribute \enum_value_0100110 "OP_STORE"
+ attribute \enum_value_0100111 "OP_MADDHD"
+ attribute \enum_value_0101000 "OP_MADDHDU"
+ attribute \enum_value_0101001 "OP_MADDLD"
+ attribute \enum_value_0101010 "OP_MCRF"
+ attribute \enum_value_0101011 "OP_MCRXR"
+ attribute \enum_value_0101100 "OP_MCRXRX"
+ attribute \enum_value_0101101 "OP_MFCR"
+ attribute \enum_value_0101110 "OP_MFSPR"
+ attribute \enum_value_0101111 "OP_MOD"
+ attribute \enum_value_0110000 "OP_MTCRF"
+ attribute \enum_value_0110001 "OP_MTSPR"
+ attribute \enum_value_0110010 "OP_MUL_L64"
+ attribute \enum_value_0110011 "OP_MUL_H64"
+ attribute \enum_value_0110100 "OP_MUL_H32"
+ attribute \enum_value_0110101 "OP_OR"
+ attribute \enum_value_0110110 "OP_POPCNT"
+ attribute \enum_value_0110111 "OP_PRTY"
+ attribute \enum_value_0111000 "OP_RLC"
+ attribute \enum_value_0111001 "OP_RLCL"
+ attribute \enum_value_0111010 "OP_RLCR"
+ attribute \enum_value_0111011 "OP_SETB"
+ attribute \enum_value_0111100 "OP_SHL"
+ attribute \enum_value_0111101 "OP_SHR"
+ attribute \enum_value_0111110 "OP_SYNC"
+ attribute \enum_value_0111111 "OP_TRAP"
+ attribute \enum_value_1000011 "OP_XOR"
+ attribute \enum_value_1000100 "OP_SIM_CONFIG"
+ attribute \enum_value_1000101 "OP_CROP"
+ attribute \enum_value_1000110 "OP_RFID"
+ attribute \enum_value_1000111 "OP_MFMSR"
+ attribute \enum_value_1001000 "OP_MTMSRD"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 7 output 22 \op__insn_type$2
+ attribute \enum_base_type "Function"
+ attribute \enum_value_00000000000 "NONE"
+ attribute \enum_value_00000000010 "ALU"
+ attribute \enum_value_00000000100 "LDST"
+ attribute \enum_value_00000001000 "SHIFT_ROT"
+ attribute \enum_value_00000010000 "LOGICAL"
+ attribute \enum_value_00000100000 "BRANCH"
+ attribute \enum_value_00001000000 "CR"
+ attribute \enum_value_00010000000 "TRAP"
+ attribute \enum_value_00100000000 "MUL"
+ attribute \enum_value_01000000000 "DIV"
+ attribute \enum_value_10000000000 "SPR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 11 output 23 \op__fn_unit$3
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 output 24 \op__imm_data__imm$4
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 25 \op__imm_data__imm_ok$5
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 26 \op__rc__rc$6
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 27 \op__rc__rc_ok$7
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 28 \op__oe__oe$8
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 29 \op__oe__oe_ok$9
+ attribute \enum_base_type "CryIn"
+ attribute \enum_value_00 "ZERO"
+ attribute \enum_value_01 "ONE"
+ attribute \enum_value_10 "CA"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 2 output 31 \op__input_carry$10
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 32 \op__output_carry$11
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 33 \op__input_cr$12
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 34 \op__output_cr$13
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 35 \op__is_32bit$14
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 36 \op__is_signed$15
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 output 37 \op__insn$16
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 64 output 38 \o$17
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 39 \o_ok$18
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 4 output 40 \cr_a$19
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 41 \cr_a_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 2 output 42 \xer_ca$20
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 43 \xer_ca_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:23"
+ wire width 65 \o$21
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 65 $22
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ cell $pos $23
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 64
+ parameter \Y_WIDTH 65
+ connect \A \o
+ connect \Y $22
+ end
+ process $group_0
+ assign \o$21 65'00000000000000000000000000000000000000000000000000000000000000000
+ assign \o$21 $22
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:35"
+ wire width 64 \target
+ process $group_1
+ assign \target 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \target \o$21 [63:0]
+ sync init
+ end
+ process $group_2
+ assign \xer_ca$20 2'00
+ assign \xer_ca$20 \xer_ca
+ sync init
+ end
+ process $group_3
+ assign \xer_ca_ok 1'0
+ assign \xer_ca_ok \op__output_carry
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:54"
+ wire width 1 \is_cmp
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:63"
+ wire width 1 $24
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:63"
+ cell $eq $25
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 7
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 7
+ parameter \Y_WIDTH 1
+ connect \A \op__insn_type
+ connect \B 7'0001010
+ connect \Y $24
+ end
+ process $group_4
+ assign \is_cmp 1'0
+ assign \is_cmp $24
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:55"
+ wire width 1 \is_cmpeqb
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:64"
+ wire width 1 $26
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:64"
+ cell $eq $27
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 7
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 7
+ parameter \Y_WIDTH 1
+ connect \A \op__insn_type
+ connect \B 7'0001100
+ connect \Y $26
+ end
+ process $group_5
+ assign \is_cmpeqb 1'0
+ assign \is_cmpeqb $26
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:53"
+ wire width 1 \msb_test
+ process $group_6
+ assign \msb_test 1'0
+ assign \msb_test \target [63]
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:50"
+ wire width 1 \is_nzero
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71"
+ wire width 1 $28
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71"
+ cell $reduce_bool $29
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 64
+ parameter \Y_WIDTH 1
+ connect \A \target
+ connect \Y $28
+ end
+ process $group_7
+ assign \is_nzero 1'0
+ assign \is_nzero $28
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:51"
+ wire width 1 \is_positive
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77"
+ wire width 1 $30
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77"
+ cell $not $31
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \msb_test
+ connect \Y $30
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77"
+ wire width 1 $32
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77"
+ cell $and $33
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \is_nzero
+ connect \B $30
+ connect \Y $32
+ end
+ process $group_8
+ assign \is_positive 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:72"
+ switch { \is_cmp }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:72"
+ case 1'1
+ assign \is_positive \msb_test
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:75"
+ case
+ assign \is_positive $32
+ end
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:52"
+ wire width 1 \is_negative
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:74"
+ wire width 1 $34
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:74"
+ cell $not $35
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \msb_test
+ connect \Y $34
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:74"
+ wire width 1 $36
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:74"
+ cell $and $37
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \is_nzero
+ connect \B $34
+ connect \Y $36
+ end
+ process $group_9
+ assign \is_negative 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:72"
+ switch { \is_cmp }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:72"
+ case 1'1
+ assign \is_negative $36
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:75"
+ case
+ assign \is_negative \msb_test
+ end
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:57"
+ wire width 4 \cr0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:82"
+ wire width 1 $38
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:82"
+ cell $not $39
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \is_nzero
+ connect \Y $38
+ end
+ process $group_10
+ assign \cr0 4'0000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:79"
+ switch { \is_cmpeqb }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:79"
+ case 1'1
+ assign \cr0 \cr_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81"
+ case
+ assign \cr0 { \is_negative \is_positive $38 1'0 }
+ end
+ sync init
+ end
+ process $group_11
+ assign \o$17 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \o$17 \o$21 [63:0]
+ sync init
+ end
+ process $group_12
+ assign \o_ok$18 1'0
+ assign \o_ok$18 \o_ok
+ sync init
+ end
+ process $group_13
+ assign \cr_a$19 4'0000
+ assign \cr_a$19 \cr0
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 $40
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ cell $pos $41
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 0
+ parameter \Y_WIDTH 1
+ connect \A { }
+ connect \Y $40
+ end
+ process $group_14
+ assign \cr_a_ok 1'0
+ assign \cr_a_ok $40
+ sync init
+ end
+ process $group_15
+ assign \muxid$1 2'00
+ assign \muxid$1 \muxid
+ sync init
+ end
+ process $group_16
+ assign \op__insn_type$2 7'0000000
+ assign \op__fn_unit$3 11'00000000000
+ assign \op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \op__imm_data__imm_ok$5 1'0
+ assign \op__rc__rc$6 1'0
+ assign \op__rc__rc_ok$7 1'0
+ assign \op__oe__oe$8 1'0
+ assign \op__oe__oe_ok$9 1'0
+ assign { } 0'0
+ assign \op__input_carry$10 2'00
+ assign \op__output_carry$11 1'0
+ assign \op__input_cr$12 1'0
+ assign \op__output_cr$13 1'0
+ assign \op__is_32bit$14 1'0
+ assign \op__is_signed$15 1'0
+ assign \op__insn$16 32'00000000000000000000000000000000
+ assign { \op__insn$16 \op__is_signed$15 \op__is_32bit$14 \op__output_cr$13 \op__input_cr$12 \op__output_carry$11 \op__input_carry$10 { } { \op__oe__oe_ok$9 \op__oe__oe$8 } { \op__rc__rc_ok$7 \op__rc__rc$6 } { \op__imm_data__imm_ok$5 \op__imm_data__imm$4 } \op__fn_unit$3 \op__insn_type$2 } { \op__insn \op__is_signed \op__is_32bit \op__output_cr \op__input_cr \op__output_carry \op__input_carry { } { \op__oe__oe_ok \op__oe__oe } { \op__rc__rc_ok \op__rc__rc } { \op__imm_data__imm_ok \op__imm_data__imm } \op__fn_unit \op__insn_type }
+ sync init
+ end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe"
+module \pipe$89
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
+ wire width 1 input 0 \rst
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
+ wire width 1 input 1 \clk
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153"
+ wire width 1 input 2 \p_valid_i
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154"
+ wire width 1 output 3 \p_ready_o
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+ wire width 2 input 4 \muxid
+ attribute \enum_base_type "MicrOp"
+ attribute \enum_value_0000000 "OP_ILLEGAL"
+ attribute \enum_value_0000001 "OP_NOP"
+ attribute \enum_value_0000010 "OP_ADD"
+ attribute \enum_value_0000011 "OP_ADDPCIS"
+ attribute \enum_value_0000100 "OP_AND"
+ attribute \enum_value_0000101 "OP_ATTN"
+ attribute \enum_value_0000110 "OP_B"
+ attribute \enum_value_0000111 "OP_BC"
+ attribute \enum_value_0001000 "OP_BCREG"
+ attribute \enum_value_0001001 "OP_BPERM"
+ attribute \enum_value_0001010 "OP_CMP"
+ attribute \enum_value_0001011 "OP_CMPB"
+ attribute \enum_value_0001100 "OP_CMPEQB"
+ attribute \enum_value_0001101 "OP_CMPRB"
+ attribute \enum_value_0001110 "OP_CNTZ"
+ attribute \enum_value_0001111 "OP_CRAND"
+ attribute \enum_value_0010000 "OP_CRANDC"
+ attribute \enum_value_0010001 "OP_CREQV"
+ attribute \enum_value_0010010 "OP_CRNAND"
+ attribute \enum_value_0010011 "OP_CRNOR"
+ attribute \enum_value_0010100 "OP_CROR"
+ attribute \enum_value_0010101 "OP_CRORC"
+ attribute \enum_value_0010110 "OP_CRXOR"
+ attribute \enum_value_0010111 "OP_DARN"
+ attribute \enum_value_0011000 "OP_DCBF"
+ attribute \enum_value_0011001 "OP_DCBST"
+ attribute \enum_value_0011010 "OP_DCBT"
+ attribute \enum_value_0011011 "OP_DCBTST"
+ attribute \enum_value_0011100 "OP_DCBZ"
+ attribute \enum_value_0011101 "OP_DIV"
+ attribute \enum_value_0011110 "OP_DIVE"
+ attribute \enum_value_0011111 "OP_EXTS"
+ attribute \enum_value_0100000 "OP_EXTSWSLI"
+ attribute \enum_value_0100001 "OP_ICBI"
+ attribute \enum_value_0100010 "OP_ICBT"
+ attribute \enum_value_0100011 "OP_ISEL"
+ attribute \enum_value_0100100 "OP_ISYNC"
+ attribute \enum_value_0100101 "OP_LOAD"
+ attribute \enum_value_0100110 "OP_STORE"
+ attribute \enum_value_0100111 "OP_MADDHD"
+ attribute \enum_value_0101000 "OP_MADDHDU"
+ attribute \enum_value_0101001 "OP_MADDLD"
+ attribute \enum_value_0101010 "OP_MCRF"
+ attribute \enum_value_0101011 "OP_MCRXR"
+ attribute \enum_value_0101100 "OP_MCRXRX"
+ attribute \enum_value_0101101 "OP_MFCR"
+ attribute \enum_value_0101110 "OP_MFSPR"
+ attribute \enum_value_0101111 "OP_MOD"
+ attribute \enum_value_0110000 "OP_MTCRF"
+ attribute \enum_value_0110001 "OP_MTSPR"
+ attribute \enum_value_0110010 "OP_MUL_L64"
+ attribute \enum_value_0110011 "OP_MUL_H64"
+ attribute \enum_value_0110100 "OP_MUL_H32"
+ attribute \enum_value_0110101 "OP_OR"
+ attribute \enum_value_0110110 "OP_POPCNT"
+ attribute \enum_value_0110111 "OP_PRTY"
+ attribute \enum_value_0111000 "OP_RLC"
+ attribute \enum_value_0111001 "OP_RLCL"
+ attribute \enum_value_0111010 "OP_RLCR"
+ attribute \enum_value_0111011 "OP_SETB"
+ attribute \enum_value_0111100 "OP_SHL"
+ attribute \enum_value_0111101 "OP_SHR"
+ attribute \enum_value_0111110 "OP_SYNC"
+ attribute \enum_value_0111111 "OP_TRAP"
+ attribute \enum_value_1000011 "OP_XOR"
+ attribute \enum_value_1000100 "OP_SIM_CONFIG"
+ attribute \enum_value_1000101 "OP_CROP"
+ attribute \enum_value_1000110 "OP_RFID"
+ attribute \enum_value_1000111 "OP_MFMSR"
+ attribute \enum_value_1001000 "OP_MTMSRD"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 7 input 5 \op__insn_type
+ attribute \enum_base_type "Function"
+ attribute \enum_value_00000000000 "NONE"
+ attribute \enum_value_00000000010 "ALU"
+ attribute \enum_value_00000000100 "LDST"
+ attribute \enum_value_00000001000 "SHIFT_ROT"
+ attribute \enum_value_00000010000 "LOGICAL"
+ attribute \enum_value_00000100000 "BRANCH"
+ attribute \enum_value_00001000000 "CR"
+ attribute \enum_value_00010000000 "TRAP"
+ attribute \enum_value_00100000000 "MUL"
+ attribute \enum_value_01000000000 "DIV"
+ attribute \enum_value_10000000000 "SPR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 11 input 6 \op__fn_unit
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 input 7 \op__imm_data__imm
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 8 \op__imm_data__imm_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 9 \op__rc__rc
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 10 \op__rc__rc_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 11 \op__oe__oe
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 12 \op__oe__oe_ok
+ attribute \enum_base_type "CryIn"
+ attribute \enum_value_00 "ZERO"
+ attribute \enum_value_01 "ONE"
+ attribute \enum_value_10 "CA"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 2 input 14 \op__input_carry
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 15 \op__output_carry
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 16 \op__input_cr
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 17 \op__output_cr
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 18 \op__is_32bit
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 19 \op__is_signed
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 input 20 \op__insn
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 64 input 21 \ra
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 64 input 22 \rb
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 64 input 23 \rc
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 2 input 24 \xer_ca
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
+ wire width 1 output 25 \n_valid_o
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
+ wire width 1 input 26 \n_ready_i
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+ wire width 2 output 27 \muxid$1
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+ wire width 2 \muxid$1$next
+ attribute \enum_base_type "MicrOp"
+ attribute \enum_value_0000000 "OP_ILLEGAL"
+ attribute \enum_value_0000001 "OP_NOP"
+ attribute \enum_value_0000010 "OP_ADD"
+ attribute \enum_value_0000011 "OP_ADDPCIS"
+ attribute \enum_value_0000100 "OP_AND"
+ attribute \enum_value_0000101 "OP_ATTN"
+ attribute \enum_value_0000110 "OP_B"
+ attribute \enum_value_0000111 "OP_BC"
+ attribute \enum_value_0001000 "OP_BCREG"
+ attribute \enum_value_0001001 "OP_BPERM"
+ attribute \enum_value_0001010 "OP_CMP"
+ attribute \enum_value_0001011 "OP_CMPB"
+ attribute \enum_value_0001100 "OP_CMPEQB"
+ attribute \enum_value_0001101 "OP_CMPRB"
+ attribute \enum_value_0001110 "OP_CNTZ"
+ attribute \enum_value_0001111 "OP_CRAND"
+ attribute \enum_value_0010000 "OP_CRANDC"
+ attribute \enum_value_0010001 "OP_CREQV"
+ attribute \enum_value_0010010 "OP_CRNAND"
+ attribute \enum_value_0010011 "OP_CRNOR"
+ attribute \enum_value_0010100 "OP_CROR"
+ attribute \enum_value_0010101 "OP_CRORC"
+ attribute \enum_value_0010110 "OP_CRXOR"
+ attribute \enum_value_0010111 "OP_DARN"
+ attribute \enum_value_0011000 "OP_DCBF"
+ attribute \enum_value_0011001 "OP_DCBST"
+ attribute \enum_value_0011010 "OP_DCBT"
+ attribute \enum_value_0011011 "OP_DCBTST"
+ attribute \enum_value_0011100 "OP_DCBZ"
+ attribute \enum_value_0011101 "OP_DIV"
+ attribute \enum_value_0011110 "OP_DIVE"
+ attribute \enum_value_0011111 "OP_EXTS"
+ attribute \enum_value_0100000 "OP_EXTSWSLI"
+ attribute \enum_value_0100001 "OP_ICBI"
+ attribute \enum_value_0100010 "OP_ICBT"
+ attribute \enum_value_0100011 "OP_ISEL"
+ attribute \enum_value_0100100 "OP_ISYNC"
+ attribute \enum_value_0100101 "OP_LOAD"
+ attribute \enum_value_0100110 "OP_STORE"
+ attribute \enum_value_0100111 "OP_MADDHD"
+ attribute \enum_value_0101000 "OP_MADDHDU"
+ attribute \enum_value_0101001 "OP_MADDLD"
+ attribute \enum_value_0101010 "OP_MCRF"
+ attribute \enum_value_0101011 "OP_MCRXR"
+ attribute \enum_value_0101100 "OP_MCRXRX"
+ attribute \enum_value_0101101 "OP_MFCR"
+ attribute \enum_value_0101110 "OP_MFSPR"
+ attribute \enum_value_0101111 "OP_MOD"
+ attribute \enum_value_0110000 "OP_MTCRF"
+ attribute \enum_value_0110001 "OP_MTSPR"
+ attribute \enum_value_0110010 "OP_MUL_L64"
+ attribute \enum_value_0110011 "OP_MUL_H64"
+ attribute \enum_value_0110100 "OP_MUL_H32"
+ attribute \enum_value_0110101 "OP_OR"
+ attribute \enum_value_0110110 "OP_POPCNT"
+ attribute \enum_value_0110111 "OP_PRTY"
+ attribute \enum_value_0111000 "OP_RLC"
+ attribute \enum_value_0111001 "OP_RLCL"
+ attribute \enum_value_0111010 "OP_RLCR"
+ attribute \enum_value_0111011 "OP_SETB"
+ attribute \enum_value_0111100 "OP_SHL"
+ attribute \enum_value_0111101 "OP_SHR"
+ attribute \enum_value_0111110 "OP_SYNC"
+ attribute \enum_value_0111111 "OP_TRAP"
+ attribute \enum_value_1000011 "OP_XOR"
+ attribute \enum_value_1000100 "OP_SIM_CONFIG"
+ attribute \enum_value_1000101 "OP_CROP"
+ attribute \enum_value_1000110 "OP_RFID"
+ attribute \enum_value_1000111 "OP_MFMSR"
+ attribute \enum_value_1001000 "OP_MTMSRD"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 7 output 28 \op__insn_type$2
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 7 \op__insn_type$2$next
+ attribute \enum_base_type "Function"
+ attribute \enum_value_00000000000 "NONE"
+ attribute \enum_value_00000000010 "ALU"
+ attribute \enum_value_00000000100 "LDST"
+ attribute \enum_value_00000001000 "SHIFT_ROT"
+ attribute \enum_value_00000010000 "LOGICAL"
+ attribute \enum_value_00000100000 "BRANCH"
+ attribute \enum_value_00001000000 "CR"
+ attribute \enum_value_00010000000 "TRAP"
+ attribute \enum_value_00100000000 "MUL"
+ attribute \enum_value_01000000000 "DIV"
+ attribute \enum_value_10000000000 "SPR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 11 output 29 \op__fn_unit$3
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 11 \op__fn_unit$3$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 output 30 \op__imm_data__imm$4
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 \op__imm_data__imm$4$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 31 \op__imm_data__imm_ok$5
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__imm_data__imm_ok$5$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 32 \op__rc__rc$6
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__rc__rc$6$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 33 \op__rc__rc_ok$7
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__rc__rc_ok$7$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 34 \op__oe__oe$8
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__oe__oe$8$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 35 \op__oe__oe_ok$9
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__oe__oe_ok$9$next
+ attribute \enum_base_type "CryIn"
+ attribute \enum_value_00 "ZERO"
+ attribute \enum_value_01 "ONE"
+ attribute \enum_value_10 "CA"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 2 output 37 \op__input_carry$10
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 2 \op__input_carry$10$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 38 \op__output_carry$11
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__output_carry$11$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 39 \op__input_cr$12
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__input_cr$12$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 40 \op__output_cr$13
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__output_cr$13$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 41 \op__is_32bit$14
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__is_32bit$14$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 42 \op__is_signed$15
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__is_signed$15$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 output 43 \op__insn$16
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 \op__insn$16$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 64 output 44 \o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 64 \o$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 45 \o_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 \o_ok$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 4 output 46 \cr_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 4 \cr_a$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 47 \cr_a_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 \cr_a_ok$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 2 output 48 \xer_ca$17
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 2 \xer_ca$17$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 49 \xer_ca_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 \xer_ca_ok$next
+ cell \p$90 \p
+ connect \p_valid_i \p_valid_i
+ connect \p_ready_o \p_ready_o
+ end
+ cell \n$91 \n
+ connect \n_valid_o \n_valid_o
+ connect \n_ready_i \n_ready_i
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+ wire width 2 \input_muxid
+ attribute \enum_base_type "MicrOp"
+ attribute \enum_value_0000000 "OP_ILLEGAL"
+ attribute \enum_value_0000001 "OP_NOP"
+ attribute \enum_value_0000010 "OP_ADD"
+ attribute \enum_value_0000011 "OP_ADDPCIS"
+ attribute \enum_value_0000100 "OP_AND"
+ attribute \enum_value_0000101 "OP_ATTN"
+ attribute \enum_value_0000110 "OP_B"
+ attribute \enum_value_0000111 "OP_BC"
+ attribute \enum_value_0001000 "OP_BCREG"
+ attribute \enum_value_0001001 "OP_BPERM"
+ attribute \enum_value_0001010 "OP_CMP"
+ attribute \enum_value_0001011 "OP_CMPB"
+ attribute \enum_value_0001100 "OP_CMPEQB"
+ attribute \enum_value_0001101 "OP_CMPRB"
+ attribute \enum_value_0001110 "OP_CNTZ"
+ attribute \enum_value_0001111 "OP_CRAND"
+ attribute \enum_value_0010000 "OP_CRANDC"
+ attribute \enum_value_0010001 "OP_CREQV"
+ attribute \enum_value_0010010 "OP_CRNAND"
+ attribute \enum_value_0010011 "OP_CRNOR"
+ attribute \enum_value_0010100 "OP_CROR"
+ attribute \enum_value_0010101 "OP_CRORC"
+ attribute \enum_value_0010110 "OP_CRXOR"
+ attribute \enum_value_0010111 "OP_DARN"
+ attribute \enum_value_0011000 "OP_DCBF"
+ attribute \enum_value_0011001 "OP_DCBST"
+ attribute \enum_value_0011010 "OP_DCBT"
+ attribute \enum_value_0011011 "OP_DCBTST"
+ attribute \enum_value_0011100 "OP_DCBZ"
+ attribute \enum_value_0011101 "OP_DIV"
+ attribute \enum_value_0011110 "OP_DIVE"
+ attribute \enum_value_0011111 "OP_EXTS"
+ attribute \enum_value_0100000 "OP_EXTSWSLI"
+ attribute \enum_value_0100001 "OP_ICBI"
+ attribute \enum_value_0100010 "OP_ICBT"
+ attribute \enum_value_0100011 "OP_ISEL"
+ attribute \enum_value_0100100 "OP_ISYNC"
+ attribute \enum_value_0100101 "OP_LOAD"
+ attribute \enum_value_0100110 "OP_STORE"
+ attribute \enum_value_0100111 "OP_MADDHD"
+ attribute \enum_value_0101000 "OP_MADDHDU"
+ attribute \enum_value_0101001 "OP_MADDLD"
+ attribute \enum_value_0101010 "OP_MCRF"
+ attribute \enum_value_0101011 "OP_MCRXR"
+ attribute \enum_value_0101100 "OP_MCRXRX"
+ attribute \enum_value_0101101 "OP_MFCR"
+ attribute \enum_value_0101110 "OP_MFSPR"
+ attribute \enum_value_0101111 "OP_MOD"
+ attribute \enum_value_0110000 "OP_MTCRF"
+ attribute \enum_value_0110001 "OP_MTSPR"
+ attribute \enum_value_0110010 "OP_MUL_L64"
+ attribute \enum_value_0110011 "OP_MUL_H64"
+ attribute \enum_value_0110100 "OP_MUL_H32"
+ attribute \enum_value_0110101 "OP_OR"
+ attribute \enum_value_0110110 "OP_POPCNT"
+ attribute \enum_value_0110111 "OP_PRTY"
+ attribute \enum_value_0111000 "OP_RLC"
+ attribute \enum_value_0111001 "OP_RLCL"
+ attribute \enum_value_0111010 "OP_RLCR"
+ attribute \enum_value_0111011 "OP_SETB"
+ attribute \enum_value_0111100 "OP_SHL"
+ attribute \enum_value_0111101 "OP_SHR"
+ attribute \enum_value_0111110 "OP_SYNC"
+ attribute \enum_value_0111111 "OP_TRAP"
+ attribute \enum_value_1000011 "OP_XOR"
+ attribute \enum_value_1000100 "OP_SIM_CONFIG"
+ attribute \enum_value_1000101 "OP_CROP"
+ attribute \enum_value_1000110 "OP_RFID"
+ attribute \enum_value_1000111 "OP_MFMSR"
+ attribute \enum_value_1001000 "OP_MTMSRD"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 7 \input_op__insn_type
+ attribute \enum_base_type "Function"
+ attribute \enum_value_00000000000 "NONE"
+ attribute \enum_value_00000000010 "ALU"
+ attribute \enum_value_00000000100 "LDST"
+ attribute \enum_value_00000001000 "SHIFT_ROT"
+ attribute \enum_value_00000010000 "LOGICAL"
+ attribute \enum_value_00000100000 "BRANCH"
+ attribute \enum_value_00001000000 "CR"
+ attribute \enum_value_00010000000 "TRAP"
+ attribute \enum_value_00100000000 "MUL"
+ attribute \enum_value_01000000000 "DIV"
+ attribute \enum_value_10000000000 "SPR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 11 \input_op__fn_unit
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 \input_op__imm_data__imm
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \input_op__imm_data__imm_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \input_op__rc__rc
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \input_op__rc__rc_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \input_op__oe__oe
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \input_op__oe__oe_ok
+ attribute \enum_base_type "CryIn"
+ attribute \enum_value_00 "ZERO"
+ attribute \enum_value_01 "ONE"
+ attribute \enum_value_10 "CA"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 2 \input_op__input_carry
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \input_op__output_carry
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \input_op__input_cr
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \input_op__output_cr
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \input_op__is_32bit
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \input_op__is_signed
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 \input_op__insn
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 64 \input_ra
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 64 \input_rb
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 64 \input_rc
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 2 \input_xer_ca
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+ wire width 2 \input_muxid$18
+ attribute \enum_base_type "MicrOp"
+ attribute \enum_value_0000000 "OP_ILLEGAL"
+ attribute \enum_value_0000001 "OP_NOP"
+ attribute \enum_value_0000010 "OP_ADD"
+ attribute \enum_value_0000011 "OP_ADDPCIS"
+ attribute \enum_value_0000100 "OP_AND"
+ attribute \enum_value_0000101 "OP_ATTN"
+ attribute \enum_value_0000110 "OP_B"
+ attribute \enum_value_0000111 "OP_BC"
+ attribute \enum_value_0001000 "OP_BCREG"
+ attribute \enum_value_0001001 "OP_BPERM"
+ attribute \enum_value_0001010 "OP_CMP"
+ attribute \enum_value_0001011 "OP_CMPB"
+ attribute \enum_value_0001100 "OP_CMPEQB"
+ attribute \enum_value_0001101 "OP_CMPRB"
+ attribute \enum_value_0001110 "OP_CNTZ"
+ attribute \enum_value_0001111 "OP_CRAND"
+ attribute \enum_value_0010000 "OP_CRANDC"
+ attribute \enum_value_0010001 "OP_CREQV"
+ attribute \enum_value_0010010 "OP_CRNAND"
+ attribute \enum_value_0010011 "OP_CRNOR"
+ attribute \enum_value_0010100 "OP_CROR"
+ attribute \enum_value_0010101 "OP_CRORC"
+ attribute \enum_value_0010110 "OP_CRXOR"
+ attribute \enum_value_0010111 "OP_DARN"
+ attribute \enum_value_0011000 "OP_DCBF"
+ attribute \enum_value_0011001 "OP_DCBST"
+ attribute \enum_value_0011010 "OP_DCBT"
+ attribute \enum_value_0011011 "OP_DCBTST"
+ attribute \enum_value_0011100 "OP_DCBZ"
+ attribute \enum_value_0011101 "OP_DIV"
+ attribute \enum_value_0011110 "OP_DIVE"
+ attribute \enum_value_0011111 "OP_EXTS"
+ attribute \enum_value_0100000 "OP_EXTSWSLI"
+ attribute \enum_value_0100001 "OP_ICBI"
+ attribute \enum_value_0100010 "OP_ICBT"
+ attribute \enum_value_0100011 "OP_ISEL"
+ attribute \enum_value_0100100 "OP_ISYNC"
+ attribute \enum_value_0100101 "OP_LOAD"
+ attribute \enum_value_0100110 "OP_STORE"
+ attribute \enum_value_0100111 "OP_MADDHD"
+ attribute \enum_value_0101000 "OP_MADDHDU"
+ attribute \enum_value_0101001 "OP_MADDLD"
+ attribute \enum_value_0101010 "OP_MCRF"
+ attribute \enum_value_0101011 "OP_MCRXR"
+ attribute \enum_value_0101100 "OP_MCRXRX"
+ attribute \enum_value_0101101 "OP_MFCR"
+ attribute \enum_value_0101110 "OP_MFSPR"
+ attribute \enum_value_0101111 "OP_MOD"
+ attribute \enum_value_0110000 "OP_MTCRF"
+ attribute \enum_value_0110001 "OP_MTSPR"
+ attribute \enum_value_0110010 "OP_MUL_L64"
+ attribute \enum_value_0110011 "OP_MUL_H64"
+ attribute \enum_value_0110100 "OP_MUL_H32"
+ attribute \enum_value_0110101 "OP_OR"
+ attribute \enum_value_0110110 "OP_POPCNT"
+ attribute \enum_value_0110111 "OP_PRTY"
+ attribute \enum_value_0111000 "OP_RLC"
+ attribute \enum_value_0111001 "OP_RLCL"
+ attribute \enum_value_0111010 "OP_RLCR"
+ attribute \enum_value_0111011 "OP_SETB"
+ attribute \enum_value_0111100 "OP_SHL"
+ attribute \enum_value_0111101 "OP_SHR"
+ attribute \enum_value_0111110 "OP_SYNC"
+ attribute \enum_value_0111111 "OP_TRAP"
+ attribute \enum_value_1000011 "OP_XOR"
+ attribute \enum_value_1000100 "OP_SIM_CONFIG"
+ attribute \enum_value_1000101 "OP_CROP"
+ attribute \enum_value_1000110 "OP_RFID"
+ attribute \enum_value_1000111 "OP_MFMSR"
+ attribute \enum_value_1001000 "OP_MTMSRD"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 7 \input_op__insn_type$19
+ attribute \enum_base_type "Function"
+ attribute \enum_value_00000000000 "NONE"
+ attribute \enum_value_00000000010 "ALU"
+ attribute \enum_value_00000000100 "LDST"
+ attribute \enum_value_00000001000 "SHIFT_ROT"
+ attribute \enum_value_00000010000 "LOGICAL"
+ attribute \enum_value_00000100000 "BRANCH"
+ attribute \enum_value_00001000000 "CR"
+ attribute \enum_value_00010000000 "TRAP"
+ attribute \enum_value_00100000000 "MUL"
+ attribute \enum_value_01000000000 "DIV"
+ attribute \enum_value_10000000000 "SPR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 11 \input_op__fn_unit$20
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 \input_op__imm_data__imm$21
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \input_op__imm_data__imm_ok$22
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \input_op__rc__rc$23
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \input_op__rc__rc_ok$24
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \input_op__oe__oe$25
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \input_op__oe__oe_ok$26
+ attribute \enum_base_type "CryIn"
+ attribute \enum_value_00 "ZERO"
+ attribute \enum_value_01 "ONE"
+ attribute \enum_value_10 "CA"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 2 \input_op__input_carry$27
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \input_op__output_carry$28
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \input_op__input_cr$29
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \input_op__output_cr$30
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \input_op__is_32bit$31
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \input_op__is_signed$32
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 \input_op__insn$33
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 64 \input_ra$34
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 64 \input_rb$35
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 64 \input_rc$36
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 2 \input_xer_ca$37
+ cell \input$92 \input
+ connect \muxid \input_muxid
+ connect \op__insn_type \input_op__insn_type
+ connect \op__fn_unit \input_op__fn_unit
+ connect \op__imm_data__imm \input_op__imm_data__imm
+ connect \op__imm_data__imm_ok \input_op__imm_data__imm_ok
+ connect \op__rc__rc \input_op__rc__rc
+ connect \op__rc__rc_ok \input_op__rc__rc_ok
+ connect \op__oe__oe \input_op__oe__oe
+ connect \op__oe__oe_ok \input_op__oe__oe_ok
+ connect \op__input_carry \input_op__input_carry
+ connect \op__output_carry \input_op__output_carry
+ connect \op__input_cr \input_op__input_cr
+ connect \op__output_cr \input_op__output_cr
+ connect \op__is_32bit \input_op__is_32bit
+ connect \op__is_signed \input_op__is_signed
+ connect \op__insn \input_op__insn
+ connect \ra \input_ra
+ connect \rb \input_rb
+ connect \rc \input_rc
+ connect \xer_ca \input_xer_ca
+ connect \muxid$1 \input_muxid$18
+ connect \op__insn_type$2 \input_op__insn_type$19
+ connect \op__fn_unit$3 \input_op__fn_unit$20
+ connect \op__imm_data__imm$4 \input_op__imm_data__imm$21
+ connect \op__imm_data__imm_ok$5 \input_op__imm_data__imm_ok$22
+ connect \op__rc__rc$6 \input_op__rc__rc$23
+ connect \op__rc__rc_ok$7 \input_op__rc__rc_ok$24
+ connect \op__oe__oe$8 \input_op__oe__oe$25
+ connect \op__oe__oe_ok$9 \input_op__oe__oe_ok$26
+ connect \op__input_carry$10 \input_op__input_carry$27
+ connect \op__output_carry$11 \input_op__output_carry$28
+ connect \op__input_cr$12 \input_op__input_cr$29
+ connect \op__output_cr$13 \input_op__output_cr$30
+ connect \op__is_32bit$14 \input_op__is_32bit$31
+ connect \op__is_signed$15 \input_op__is_signed$32
+ connect \op__insn$16 \input_op__insn$33
+ connect \ra$17 \input_ra$34
+ connect \rb$18 \input_rb$35
+ connect \rc$19 \input_rc$36
+ connect \xer_ca$20 \input_xer_ca$37
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+ wire width 2 \main_muxid
+ attribute \enum_base_type "MicrOp"
+ attribute \enum_value_0000000 "OP_ILLEGAL"
+ attribute \enum_value_0000001 "OP_NOP"
+ attribute \enum_value_0000010 "OP_ADD"
+ attribute \enum_value_0000011 "OP_ADDPCIS"
+ attribute \enum_value_0000100 "OP_AND"
+ attribute \enum_value_0000101 "OP_ATTN"
+ attribute \enum_value_0000110 "OP_B"
+ attribute \enum_value_0000111 "OP_BC"
+ attribute \enum_value_0001000 "OP_BCREG"
+ attribute \enum_value_0001001 "OP_BPERM"
+ attribute \enum_value_0001010 "OP_CMP"
+ attribute \enum_value_0001011 "OP_CMPB"
+ attribute \enum_value_0001100 "OP_CMPEQB"
+ attribute \enum_value_0001101 "OP_CMPRB"
+ attribute \enum_value_0001110 "OP_CNTZ"
+ attribute \enum_value_0001111 "OP_CRAND"
+ attribute \enum_value_0010000 "OP_CRANDC"
+ attribute \enum_value_0010001 "OP_CREQV"
+ attribute \enum_value_0010010 "OP_CRNAND"
+ attribute \enum_value_0010011 "OP_CRNOR"
+ attribute \enum_value_0010100 "OP_CROR"
+ attribute \enum_value_0010101 "OP_CRORC"
+ attribute \enum_value_0010110 "OP_CRXOR"
+ attribute \enum_value_0010111 "OP_DARN"
+ attribute \enum_value_0011000 "OP_DCBF"
+ attribute \enum_value_0011001 "OP_DCBST"
+ attribute \enum_value_0011010 "OP_DCBT"
+ attribute \enum_value_0011011 "OP_DCBTST"
+ attribute \enum_value_0011100 "OP_DCBZ"
+ attribute \enum_value_0011101 "OP_DIV"
+ attribute \enum_value_0011110 "OP_DIVE"
+ attribute \enum_value_0011111 "OP_EXTS"
+ attribute \enum_value_0100000 "OP_EXTSWSLI"
+ attribute \enum_value_0100001 "OP_ICBI"
+ attribute \enum_value_0100010 "OP_ICBT"
+ attribute \enum_value_0100011 "OP_ISEL"
+ attribute \enum_value_0100100 "OP_ISYNC"
+ attribute \enum_value_0100101 "OP_LOAD"
+ attribute \enum_value_0100110 "OP_STORE"
+ attribute \enum_value_0100111 "OP_MADDHD"
+ attribute \enum_value_0101000 "OP_MADDHDU"
+ attribute \enum_value_0101001 "OP_MADDLD"
+ attribute \enum_value_0101010 "OP_MCRF"
+ attribute \enum_value_0101011 "OP_MCRXR"
+ attribute \enum_value_0101100 "OP_MCRXRX"
+ attribute \enum_value_0101101 "OP_MFCR"
+ attribute \enum_value_0101110 "OP_MFSPR"
+ attribute \enum_value_0101111 "OP_MOD"
+ attribute \enum_value_0110000 "OP_MTCRF"
+ attribute \enum_value_0110001 "OP_MTSPR"
+ attribute \enum_value_0110010 "OP_MUL_L64"
+ attribute \enum_value_0110011 "OP_MUL_H64"
+ attribute \enum_value_0110100 "OP_MUL_H32"
+ attribute \enum_value_0110101 "OP_OR"
+ attribute \enum_value_0110110 "OP_POPCNT"
+ attribute \enum_value_0110111 "OP_PRTY"
+ attribute \enum_value_0111000 "OP_RLC"
+ attribute \enum_value_0111001 "OP_RLCL"
+ attribute \enum_value_0111010 "OP_RLCR"
+ attribute \enum_value_0111011 "OP_SETB"
+ attribute \enum_value_0111100 "OP_SHL"
+ attribute \enum_value_0111101 "OP_SHR"
+ attribute \enum_value_0111110 "OP_SYNC"
+ attribute \enum_value_0111111 "OP_TRAP"
+ attribute \enum_value_1000011 "OP_XOR"
+ attribute \enum_value_1000100 "OP_SIM_CONFIG"
+ attribute \enum_value_1000101 "OP_CROP"
+ attribute \enum_value_1000110 "OP_RFID"
+ attribute \enum_value_1000111 "OP_MFMSR"
+ attribute \enum_value_1001000 "OP_MTMSRD"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 7 \main_op__insn_type
+ attribute \enum_base_type "Function"
+ attribute \enum_value_00000000000 "NONE"
+ attribute \enum_value_00000000010 "ALU"
+ attribute \enum_value_00000000100 "LDST"
+ attribute \enum_value_00000001000 "SHIFT_ROT"
+ attribute \enum_value_00000010000 "LOGICAL"
+ attribute \enum_value_00000100000 "BRANCH"
+ attribute \enum_value_00001000000 "CR"
+ attribute \enum_value_00010000000 "TRAP"
+ attribute \enum_value_00100000000 "MUL"
+ attribute \enum_value_01000000000 "DIV"
+ attribute \enum_value_10000000000 "SPR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 11 \main_op__fn_unit
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 \main_op__imm_data__imm
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \main_op__imm_data__imm_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \main_op__rc__rc
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \main_op__rc__rc_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \main_op__oe__oe
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \main_op__oe__oe_ok
+ attribute \enum_base_type "CryIn"
+ attribute \enum_value_00 "ZERO"
+ attribute \enum_value_01 "ONE"
+ attribute \enum_value_10 "CA"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 2 \main_op__input_carry
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \main_op__output_carry
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \main_op__input_cr
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \main_op__output_cr
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \main_op__is_32bit
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \main_op__is_signed
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 \main_op__insn
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 64 \main_ra
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 64 \main_rb
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 64 \main_rc
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+ wire width 2 \main_muxid$38
+ attribute \enum_base_type "MicrOp"
+ attribute \enum_value_0000000 "OP_ILLEGAL"
+ attribute \enum_value_0000001 "OP_NOP"
+ attribute \enum_value_0000010 "OP_ADD"
+ attribute \enum_value_0000011 "OP_ADDPCIS"
+ attribute \enum_value_0000100 "OP_AND"
+ attribute \enum_value_0000101 "OP_ATTN"
+ attribute \enum_value_0000110 "OP_B"
+ attribute \enum_value_0000111 "OP_BC"
+ attribute \enum_value_0001000 "OP_BCREG"
+ attribute \enum_value_0001001 "OP_BPERM"
+ attribute \enum_value_0001010 "OP_CMP"
+ attribute \enum_value_0001011 "OP_CMPB"
+ attribute \enum_value_0001100 "OP_CMPEQB"
+ attribute \enum_value_0001101 "OP_CMPRB"
+ attribute \enum_value_0001110 "OP_CNTZ"
+ attribute \enum_value_0001111 "OP_CRAND"
+ attribute \enum_value_0010000 "OP_CRANDC"
+ attribute \enum_value_0010001 "OP_CREQV"
+ attribute \enum_value_0010010 "OP_CRNAND"
+ attribute \enum_value_0010011 "OP_CRNOR"
+ attribute \enum_value_0010100 "OP_CROR"
+ attribute \enum_value_0010101 "OP_CRORC"
+ attribute \enum_value_0010110 "OP_CRXOR"
+ attribute \enum_value_0010111 "OP_DARN"
+ attribute \enum_value_0011000 "OP_DCBF"
+ attribute \enum_value_0011001 "OP_DCBST"
+ attribute \enum_value_0011010 "OP_DCBT"
+ attribute \enum_value_0011011 "OP_DCBTST"
+ attribute \enum_value_0011100 "OP_DCBZ"
+ attribute \enum_value_0011101 "OP_DIV"
+ attribute \enum_value_0011110 "OP_DIVE"
+ attribute \enum_value_0011111 "OP_EXTS"
+ attribute \enum_value_0100000 "OP_EXTSWSLI"
+ attribute \enum_value_0100001 "OP_ICBI"
+ attribute \enum_value_0100010 "OP_ICBT"
+ attribute \enum_value_0100011 "OP_ISEL"
+ attribute \enum_value_0100100 "OP_ISYNC"
+ attribute \enum_value_0100101 "OP_LOAD"
+ attribute \enum_value_0100110 "OP_STORE"
+ attribute \enum_value_0100111 "OP_MADDHD"
+ attribute \enum_value_0101000 "OP_MADDHDU"
+ attribute \enum_value_0101001 "OP_MADDLD"
+ attribute \enum_value_0101010 "OP_MCRF"
+ attribute \enum_value_0101011 "OP_MCRXR"
+ attribute \enum_value_0101100 "OP_MCRXRX"
+ attribute \enum_value_0101101 "OP_MFCR"
+ attribute \enum_value_0101110 "OP_MFSPR"
+ attribute \enum_value_0101111 "OP_MOD"
+ attribute \enum_value_0110000 "OP_MTCRF"
+ attribute \enum_value_0110001 "OP_MTSPR"
+ attribute \enum_value_0110010 "OP_MUL_L64"
+ attribute \enum_value_0110011 "OP_MUL_H64"
+ attribute \enum_value_0110100 "OP_MUL_H32"
+ attribute \enum_value_0110101 "OP_OR"
+ attribute \enum_value_0110110 "OP_POPCNT"
+ attribute \enum_value_0110111 "OP_PRTY"
+ attribute \enum_value_0111000 "OP_RLC"
+ attribute \enum_value_0111001 "OP_RLCL"
+ attribute \enum_value_0111010 "OP_RLCR"
+ attribute \enum_value_0111011 "OP_SETB"
+ attribute \enum_value_0111100 "OP_SHL"
+ attribute \enum_value_0111101 "OP_SHR"
+ attribute \enum_value_0111110 "OP_SYNC"
+ attribute \enum_value_0111111 "OP_TRAP"
+ attribute \enum_value_1000011 "OP_XOR"
+ attribute \enum_value_1000100 "OP_SIM_CONFIG"
+ attribute \enum_value_1000101 "OP_CROP"
+ attribute \enum_value_1000110 "OP_RFID"
+ attribute \enum_value_1000111 "OP_MFMSR"
+ attribute \enum_value_1001000 "OP_MTMSRD"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 7 \main_op__insn_type$39
+ attribute \enum_base_type "Function"
+ attribute \enum_value_00000000000 "NONE"
+ attribute \enum_value_00000000010 "ALU"
+ attribute \enum_value_00000000100 "LDST"
+ attribute \enum_value_00000001000 "SHIFT_ROT"
+ attribute \enum_value_00000010000 "LOGICAL"
+ attribute \enum_value_00000100000 "BRANCH"
+ attribute \enum_value_00001000000 "CR"
+ attribute \enum_value_00010000000 "TRAP"
+ attribute \enum_value_00100000000 "MUL"
+ attribute \enum_value_01000000000 "DIV"
+ attribute \enum_value_10000000000 "SPR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 11 \main_op__fn_unit$40
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 \main_op__imm_data__imm$41
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \main_op__imm_data__imm_ok$42
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \main_op__rc__rc$43
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \main_op__rc__rc_ok$44
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \main_op__oe__oe$45
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \main_op__oe__oe_ok$46
+ attribute \enum_base_type "CryIn"
+ attribute \enum_value_00 "ZERO"
+ attribute \enum_value_01 "ONE"
+ attribute \enum_value_10 "CA"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 2 \main_op__input_carry$47
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \main_op__output_carry$48
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \main_op__input_cr$49
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \main_op__output_cr$50
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \main_op__is_32bit$51
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \main_op__is_signed$52
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 \main_op__insn$53
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 64 \main_o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 \main_o_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 2 \main_xer_ca
+ cell \main$93 \main
+ connect \muxid \main_muxid
+ connect \op__insn_type \main_op__insn_type
+ connect \op__fn_unit \main_op__fn_unit
+ connect \op__imm_data__imm \main_op__imm_data__imm
+ connect \op__imm_data__imm_ok \main_op__imm_data__imm_ok
+ connect \op__rc__rc \main_op__rc__rc
+ connect \op__rc__rc_ok \main_op__rc__rc_ok
+ connect \op__oe__oe \main_op__oe__oe
+ connect \op__oe__oe_ok \main_op__oe__oe_ok
+ connect \op__input_carry \main_op__input_carry
+ connect \op__output_carry \main_op__output_carry
+ connect \op__input_cr \main_op__input_cr
+ connect \op__output_cr \main_op__output_cr
+ connect \op__is_32bit \main_op__is_32bit
+ connect \op__is_signed \main_op__is_signed
+ connect \op__insn \main_op__insn
+ connect \ra \main_ra
+ connect \rb \main_rb
+ connect \rc \main_rc
+ connect \muxid$1 \main_muxid$38
+ connect \op__insn_type$2 \main_op__insn_type$39
+ connect \op__fn_unit$3 \main_op__fn_unit$40
+ connect \op__imm_data__imm$4 \main_op__imm_data__imm$41
+ connect \op__imm_data__imm_ok$5 \main_op__imm_data__imm_ok$42
+ connect \op__rc__rc$6 \main_op__rc__rc$43
+ connect \op__rc__rc_ok$7 \main_op__rc__rc_ok$44
+ connect \op__oe__oe$8 \main_op__oe__oe$45
+ connect \op__oe__oe_ok$9 \main_op__oe__oe_ok$46
+ connect \op__input_carry$10 \main_op__input_carry$47
+ connect \op__output_carry$11 \main_op__output_carry$48
+ connect \op__input_cr$12 \main_op__input_cr$49
+ connect \op__output_cr$13 \main_op__output_cr$50
+ connect \op__is_32bit$14 \main_op__is_32bit$51
+ connect \op__is_signed$15 \main_op__is_signed$52
+ connect \op__insn$16 \main_op__insn$53
+ connect \o \main_o
+ connect \o_ok \main_o_ok
+ connect \xer_ca \main_xer_ca
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+ wire width 2 \output_muxid
+ attribute \enum_base_type "MicrOp"
+ attribute \enum_value_0000000 "OP_ILLEGAL"
+ attribute \enum_value_0000001 "OP_NOP"
+ attribute \enum_value_0000010 "OP_ADD"
+ attribute \enum_value_0000011 "OP_ADDPCIS"
+ attribute \enum_value_0000100 "OP_AND"
+ attribute \enum_value_0000101 "OP_ATTN"
+ attribute \enum_value_0000110 "OP_B"
+ attribute \enum_value_0000111 "OP_BC"
+ attribute \enum_value_0001000 "OP_BCREG"
+ attribute \enum_value_0001001 "OP_BPERM"
+ attribute \enum_value_0001010 "OP_CMP"
+ attribute \enum_value_0001011 "OP_CMPB"
+ attribute \enum_value_0001100 "OP_CMPEQB"
+ attribute \enum_value_0001101 "OP_CMPRB"
+ attribute \enum_value_0001110 "OP_CNTZ"
+ attribute \enum_value_0001111 "OP_CRAND"
+ attribute \enum_value_0010000 "OP_CRANDC"
+ attribute \enum_value_0010001 "OP_CREQV"
+ attribute \enum_value_0010010 "OP_CRNAND"
+ attribute \enum_value_0010011 "OP_CRNOR"
+ attribute \enum_value_0010100 "OP_CROR"
+ attribute \enum_value_0010101 "OP_CRORC"
+ attribute \enum_value_0010110 "OP_CRXOR"
+ attribute \enum_value_0010111 "OP_DARN"
+ attribute \enum_value_0011000 "OP_DCBF"
+ attribute \enum_value_0011001 "OP_DCBST"
+ attribute \enum_value_0011010 "OP_DCBT"
+ attribute \enum_value_0011011 "OP_DCBTST"
+ attribute \enum_value_0011100 "OP_DCBZ"
+ attribute \enum_value_0011101 "OP_DIV"
+ attribute \enum_value_0011110 "OP_DIVE"
+ attribute \enum_value_0011111 "OP_EXTS"
+ attribute \enum_value_0100000 "OP_EXTSWSLI"
+ attribute \enum_value_0100001 "OP_ICBI"
+ attribute \enum_value_0100010 "OP_ICBT"
+ attribute \enum_value_0100011 "OP_ISEL"
+ attribute \enum_value_0100100 "OP_ISYNC"
+ attribute \enum_value_0100101 "OP_LOAD"
+ attribute \enum_value_0100110 "OP_STORE"
+ attribute \enum_value_0100111 "OP_MADDHD"
+ attribute \enum_value_0101000 "OP_MADDHDU"
+ attribute \enum_value_0101001 "OP_MADDLD"
+ attribute \enum_value_0101010 "OP_MCRF"
+ attribute \enum_value_0101011 "OP_MCRXR"
+ attribute \enum_value_0101100 "OP_MCRXRX"
+ attribute \enum_value_0101101 "OP_MFCR"
+ attribute \enum_value_0101110 "OP_MFSPR"
+ attribute \enum_value_0101111 "OP_MOD"
+ attribute \enum_value_0110000 "OP_MTCRF"
+ attribute \enum_value_0110001 "OP_MTSPR"
+ attribute \enum_value_0110010 "OP_MUL_L64"
+ attribute \enum_value_0110011 "OP_MUL_H64"
+ attribute \enum_value_0110100 "OP_MUL_H32"
+ attribute \enum_value_0110101 "OP_OR"
+ attribute \enum_value_0110110 "OP_POPCNT"
+ attribute \enum_value_0110111 "OP_PRTY"
+ attribute \enum_value_0111000 "OP_RLC"
+ attribute \enum_value_0111001 "OP_RLCL"
+ attribute \enum_value_0111010 "OP_RLCR"
+ attribute \enum_value_0111011 "OP_SETB"
+ attribute \enum_value_0111100 "OP_SHL"
+ attribute \enum_value_0111101 "OP_SHR"
+ attribute \enum_value_0111110 "OP_SYNC"
+ attribute \enum_value_0111111 "OP_TRAP"
+ attribute \enum_value_1000011 "OP_XOR"
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+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 7 \output_op__insn_type
+ attribute \enum_base_type "Function"
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+ attribute \enum_value_00000000100 "LDST"
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+ attribute \enum_value_10000000000 "SPR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 11 \output_op__fn_unit
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 \output_op__imm_data__imm
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \output_op__imm_data__imm_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \output_op__rc__rc
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \output_op__rc__rc_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \output_op__oe__oe
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \output_op__oe__oe_ok
+ attribute \enum_base_type "CryIn"
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+ attribute \enum_value_01 "ONE"
+ attribute \enum_value_10 "CA"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 2 \output_op__input_carry
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \output_op__output_carry
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \output_op__input_cr
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \output_op__output_cr
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \output_op__is_32bit
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \output_op__is_signed
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 \output_op__insn
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 64 \output_o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 \output_o_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 4 \output_cr_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 2 \output_xer_ca
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+ wire width 2 \output_muxid$54
+ attribute \enum_base_type "MicrOp"
+ attribute \enum_value_0000000 "OP_ILLEGAL"
+ attribute \enum_value_0000001 "OP_NOP"
+ attribute \enum_value_0000010 "OP_ADD"
+ attribute \enum_value_0000011 "OP_ADDPCIS"
+ attribute \enum_value_0000100 "OP_AND"
+ attribute \enum_value_0000101 "OP_ATTN"
+ attribute \enum_value_0000110 "OP_B"
+ attribute \enum_value_0000111 "OP_BC"
+ attribute \enum_value_0001000 "OP_BCREG"
+ attribute \enum_value_0001001 "OP_BPERM"
+ attribute \enum_value_0001010 "OP_CMP"
+ attribute \enum_value_0001011 "OP_CMPB"
+ attribute \enum_value_0001100 "OP_CMPEQB"
+ attribute \enum_value_0001101 "OP_CMPRB"
+ attribute \enum_value_0001110 "OP_CNTZ"
+ attribute \enum_value_0001111 "OP_CRAND"
+ attribute \enum_value_0010000 "OP_CRANDC"
+ attribute \enum_value_0010001 "OP_CREQV"
+ attribute \enum_value_0010010 "OP_CRNAND"
+ attribute \enum_value_0010011 "OP_CRNOR"
+ attribute \enum_value_0010100 "OP_CROR"
+ attribute \enum_value_0010101 "OP_CRORC"
+ attribute \enum_value_0010110 "OP_CRXOR"
+ attribute \enum_value_0010111 "OP_DARN"
+ attribute \enum_value_0011000 "OP_DCBF"
+ attribute \enum_value_0011001 "OP_DCBST"
+ attribute \enum_value_0011010 "OP_DCBT"
+ attribute \enum_value_0011011 "OP_DCBTST"
+ attribute \enum_value_0011100 "OP_DCBZ"
+ attribute \enum_value_0011101 "OP_DIV"
+ attribute \enum_value_0011110 "OP_DIVE"
+ attribute \enum_value_0011111 "OP_EXTS"
+ attribute \enum_value_0100000 "OP_EXTSWSLI"
+ attribute \enum_value_0100001 "OP_ICBI"
+ attribute \enum_value_0100010 "OP_ICBT"
+ attribute \enum_value_0100011 "OP_ISEL"
+ attribute \enum_value_0100100 "OP_ISYNC"
+ attribute \enum_value_0100101 "OP_LOAD"
+ attribute \enum_value_0100110 "OP_STORE"
+ attribute \enum_value_0100111 "OP_MADDHD"
+ attribute \enum_value_0101000 "OP_MADDHDU"
+ attribute \enum_value_0101001 "OP_MADDLD"
+ attribute \enum_value_0101010 "OP_MCRF"
+ attribute \enum_value_0101011 "OP_MCRXR"
+ attribute \enum_value_0101100 "OP_MCRXRX"
+ attribute \enum_value_0101101 "OP_MFCR"
+ attribute \enum_value_0101110 "OP_MFSPR"
+ attribute \enum_value_0101111 "OP_MOD"
+ attribute \enum_value_0110000 "OP_MTCRF"
+ attribute \enum_value_0110001 "OP_MTSPR"
+ attribute \enum_value_0110010 "OP_MUL_L64"
+ attribute \enum_value_0110011 "OP_MUL_H64"
+ attribute \enum_value_0110100 "OP_MUL_H32"
+ attribute \enum_value_0110101 "OP_OR"
+ attribute \enum_value_0110110 "OP_POPCNT"
+ attribute \enum_value_0110111 "OP_PRTY"
+ attribute \enum_value_0111000 "OP_RLC"
+ attribute \enum_value_0111001 "OP_RLCL"
+ attribute \enum_value_0111010 "OP_RLCR"
+ attribute \enum_value_0111011 "OP_SETB"
+ attribute \enum_value_0111100 "OP_SHL"
+ attribute \enum_value_0111101 "OP_SHR"
+ attribute \enum_value_0111110 "OP_SYNC"
+ attribute \enum_value_0111111 "OP_TRAP"
+ attribute \enum_value_1000011 "OP_XOR"
+ attribute \enum_value_1000100 "OP_SIM_CONFIG"
+ attribute \enum_value_1000101 "OP_CROP"
+ attribute \enum_value_1000110 "OP_RFID"
+ attribute \enum_value_1000111 "OP_MFMSR"
+ attribute \enum_value_1001000 "OP_MTMSRD"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 7 \output_op__insn_type$55
+ attribute \enum_base_type "Function"
+ attribute \enum_value_00000000000 "NONE"
+ attribute \enum_value_00000000010 "ALU"
+ attribute \enum_value_00000000100 "LDST"
+ attribute \enum_value_00000001000 "SHIFT_ROT"
+ attribute \enum_value_00000010000 "LOGICAL"
+ attribute \enum_value_00000100000 "BRANCH"
+ attribute \enum_value_00001000000 "CR"
+ attribute \enum_value_00010000000 "TRAP"
+ attribute \enum_value_00100000000 "MUL"
+ attribute \enum_value_01000000000 "DIV"
+ attribute \enum_value_10000000000 "SPR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 11 \output_op__fn_unit$56
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 \output_op__imm_data__imm$57
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \output_op__imm_data__imm_ok$58
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \output_op__rc__rc$59
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \output_op__rc__rc_ok$60
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \output_op__oe__oe$61
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \output_op__oe__oe_ok$62
+ attribute \enum_base_type "CryIn"
+ attribute \enum_value_00 "ZERO"
+ attribute \enum_value_01 "ONE"
+ attribute \enum_value_10 "CA"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 2 \output_op__input_carry$63
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \output_op__output_carry$64
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \output_op__input_cr$65
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \output_op__output_cr$66
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \output_op__is_32bit$67
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \output_op__is_signed$68
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 \output_op__insn$69
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 64 \output_o$70
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 \output_o_ok$71
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 4 \output_cr_a$72
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 \output_cr_a_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 2 \output_xer_ca$73
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 \output_xer_ca_ok
+ cell \output$94 \output
+ connect \muxid \output_muxid
+ connect \op__insn_type \output_op__insn_type
+ connect \op__fn_unit \output_op__fn_unit
+ connect \op__imm_data__imm \output_op__imm_data__imm
+ connect \op__imm_data__imm_ok \output_op__imm_data__imm_ok
+ connect \op__rc__rc \output_op__rc__rc
+ connect \op__rc__rc_ok \output_op__rc__rc_ok
+ connect \op__oe__oe \output_op__oe__oe
+ connect \op__oe__oe_ok \output_op__oe__oe_ok
+ connect \op__input_carry \output_op__input_carry
+ connect \op__output_carry \output_op__output_carry
+ connect \op__input_cr \output_op__input_cr
+ connect \op__output_cr \output_op__output_cr
+ connect \op__is_32bit \output_op__is_32bit
+ connect \op__is_signed \output_op__is_signed
+ connect \op__insn \output_op__insn
+ connect \o \output_o
+ connect \o_ok \output_o_ok
+ connect \cr_a \output_cr_a
+ connect \xer_ca \output_xer_ca
+ connect \muxid$1 \output_muxid$54
+ connect \op__insn_type$2 \output_op__insn_type$55
+ connect \op__fn_unit$3 \output_op__fn_unit$56
+ connect \op__imm_data__imm$4 \output_op__imm_data__imm$57
+ connect \op__imm_data__imm_ok$5 \output_op__imm_data__imm_ok$58
+ connect \op__rc__rc$6 \output_op__rc__rc$59
+ connect \op__rc__rc_ok$7 \output_op__rc__rc_ok$60
+ connect \op__oe__oe$8 \output_op__oe__oe$61
+ connect \op__oe__oe_ok$9 \output_op__oe__oe_ok$62
+ connect \op__input_carry$10 \output_op__input_carry$63
+ connect \op__output_carry$11 \output_op__output_carry$64
+ connect \op__input_cr$12 \output_op__input_cr$65
+ connect \op__output_cr$13 \output_op__output_cr$66
+ connect \op__is_32bit$14 \output_op__is_32bit$67
+ connect \op__is_signed$15 \output_op__is_signed$68
+ connect \op__insn$16 \output_op__insn$69
+ connect \o$17 \output_o$70
+ connect \o_ok$18 \output_o_ok$71
+ connect \cr_a$19 \output_cr_a$72
+ connect \cr_a_ok \output_cr_a_ok
+ connect \xer_ca$20 \output_xer_ca$73
+ connect \xer_ca_ok \output_xer_ca_ok
+ end
+ process $group_0
+ assign \input_muxid 2'00
+ assign \input_muxid \muxid
+ sync init
+ end
+ process $group_1
+ assign \input_op__insn_type 7'0000000
+ assign \input_op__fn_unit 11'00000000000
+ assign \input_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \input_op__imm_data__imm_ok 1'0
+ assign \input_op__rc__rc 1'0
+ assign \input_op__rc__rc_ok 1'0
+ assign \input_op__oe__oe 1'0
+ assign \input_op__oe__oe_ok 1'0
+ assign { } 0'0
+ assign \input_op__input_carry 2'00
+ assign \input_op__output_carry 1'0
+ assign \input_op__input_cr 1'0
+ assign \input_op__output_cr 1'0
+ assign \input_op__is_32bit 1'0
+ assign \input_op__is_signed 1'0
+ assign \input_op__insn 32'00000000000000000000000000000000
+ assign { \input_op__insn \input_op__is_signed \input_op__is_32bit \input_op__output_cr \input_op__input_cr \input_op__output_carry \input_op__input_carry { } { \input_op__oe__oe_ok \input_op__oe__oe } { \input_op__rc__rc_ok \input_op__rc__rc } { \input_op__imm_data__imm_ok \input_op__imm_data__imm } \input_op__fn_unit \input_op__insn_type } { \op__insn \op__is_signed \op__is_32bit \op__output_cr \op__input_cr \op__output_carry \op__input_carry { } { \op__oe__oe_ok \op__oe__oe } { \op__rc__rc_ok \op__rc__rc } { \op__imm_data__imm_ok \op__imm_data__imm } \op__fn_unit \op__insn_type }
+ sync init
+ end
+ process $group_17
+ assign \input_ra 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \input_ra \ra
+ sync init
+ end
+ process $group_18
+ assign \input_rb 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \input_rb \rb
+ sync init
+ end
+ process $group_19
+ assign \input_rc 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \input_rc \rc
+ sync init
+ end
+ process $group_20
+ assign \input_xer_ca 2'00
+ assign \input_xer_ca \xer_ca
+ sync init
+ end
+ process $group_21
+ assign \main_muxid 2'00
+ assign \main_muxid \input_muxid$18
+ sync init
+ end
+ process $group_22
+ assign \main_op__insn_type 7'0000000
+ assign \main_op__fn_unit 11'00000000000
+ assign \main_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \main_op__imm_data__imm_ok 1'0
+ assign \main_op__rc__rc 1'0
+ assign \main_op__rc__rc_ok 1'0
+ assign \main_op__oe__oe 1'0
+ assign \main_op__oe__oe_ok 1'0
+ assign { } 0'0
+ assign \main_op__input_carry 2'00
+ assign \main_op__output_carry 1'0
+ assign \main_op__input_cr 1'0
+ assign \main_op__output_cr 1'0
+ assign \main_op__is_32bit 1'0
+ assign \main_op__is_signed 1'0
+ assign \main_op__insn 32'00000000000000000000000000000000
+ assign { \main_op__insn \main_op__is_signed \main_op__is_32bit \main_op__output_cr \main_op__input_cr \main_op__output_carry \main_op__input_carry { } { \main_op__oe__oe_ok \main_op__oe__oe } { \main_op__rc__rc_ok \main_op__rc__rc } { \main_op__imm_data__imm_ok \main_op__imm_data__imm } \main_op__fn_unit \main_op__insn_type } { \input_op__insn$33 \input_op__is_signed$32 \input_op__is_32bit$31 \input_op__output_cr$30 \input_op__input_cr$29 \input_op__output_carry$28 \input_op__input_carry$27 { } { \input_op__oe__oe_ok$26 \input_op__oe__oe$25 } { \input_op__rc__rc_ok$24 \input_op__rc__rc$23 } { \input_op__imm_data__imm_ok$22 \input_op__imm_data__imm$21 } \input_op__fn_unit$20 \input_op__insn_type$19 }
+ sync init
+ end
+ process $group_38
+ assign \main_ra 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \main_ra \input_ra$34
+ sync init
+ end
+ process $group_39
+ assign \main_rb 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \main_rb \input_rb$35
+ sync init
+ end
+ process $group_40
+ assign \main_rc 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \main_rc \input_rc$36
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 2 \xer_ca$74
+ process $group_41
+ assign \xer_ca$74 2'00
+ assign \xer_ca$74 \input_xer_ca$37
+ sync init
+ end
+ process $group_42
+ assign \output_muxid 2'00
+ assign \output_muxid \main_muxid$38
+ sync init
+ end
+ process $group_43
+ assign \output_op__insn_type 7'0000000
+ assign \output_op__fn_unit 11'00000000000
+ assign \output_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \output_op__imm_data__imm_ok 1'0
+ assign \output_op__rc__rc 1'0
+ assign \output_op__rc__rc_ok 1'0
+ assign \output_op__oe__oe 1'0
+ assign \output_op__oe__oe_ok 1'0
+ assign { } 0'0
+ assign \output_op__input_carry 2'00
+ assign \output_op__output_carry 1'0
+ assign \output_op__input_cr 1'0
+ assign \output_op__output_cr 1'0
+ assign \output_op__is_32bit 1'0
+ assign \output_op__is_signed 1'0
+ assign \output_op__insn 32'00000000000000000000000000000000
+ assign { \output_op__insn \output_op__is_signed \output_op__is_32bit \output_op__output_cr \output_op__input_cr \output_op__output_carry \output_op__input_carry { } { \output_op__oe__oe_ok \output_op__oe__oe } { \output_op__rc__rc_ok \output_op__rc__rc } { \output_op__imm_data__imm_ok \output_op__imm_data__imm } \output_op__fn_unit \output_op__insn_type } { \main_op__insn$53 \main_op__is_signed$52 \main_op__is_32bit$51 \main_op__output_cr$50 \main_op__input_cr$49 \main_op__output_carry$48 \main_op__input_carry$47 { } { \main_op__oe__oe_ok$46 \main_op__oe__oe$45 } { \main_op__rc__rc_ok$44 \main_op__rc__rc$43 } { \main_op__imm_data__imm_ok$42 \main_op__imm_data__imm$41 } \main_op__fn_unit$40 \main_op__insn_type$39 }
+ sync init
+ end
+ process $group_59
+ assign \output_o 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \output_o_ok 1'0
+ assign { \output_o_ok \output_o } { \main_o_ok \main_o }
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 \cr_a_ok$75
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 4 \cr_a$76
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 \cr_a_ok$77
+ process $group_61
+ assign \output_cr_a 4'0000
+ assign \cr_a_ok$75 1'0
+ assign { \cr_a_ok$75 \output_cr_a } { \cr_a_ok$77 \cr_a$76 }
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 \xer_ca_ok$78
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 \xer_ca_ok$79
+ process $group_63
+ assign \output_xer_ca 2'00
+ assign \xer_ca_ok$78 1'0
+ assign { \xer_ca_ok$78 \output_xer_ca } { \xer_ca_ok$79 \main_xer_ca }
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621"
+ wire width 1 \p_valid_i$80
+ process $group_65
+ assign \p_valid_i$80 1'0
+ assign \p_valid_i$80 \p_valid_i
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619"
+ wire width 1 \n_i_rdy_data
+ process $group_66
+ assign \n_i_rdy_data 1'0
+ assign \n_i_rdy_data \n_ready_i
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620"
+ wire width 1 \p_valid_i_p_ready_o
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624"
+ wire width 1 $81
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624"
+ cell $and $82
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \p_valid_i$80
+ connect \B \p_ready_o
+ connect \Y $81
+ end
+ process $group_67
+ assign \p_valid_i_p_ready_o 1'0
+ assign \p_valid_i_p_ready_o $81
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+ wire width 2 \muxid$83
+ process $group_68
+ assign \muxid$83 2'00
+ assign \muxid$83 \output_muxid$54
+ sync init
+ end
+ attribute \enum_base_type "MicrOp"
+ attribute \enum_value_0000000 "OP_ILLEGAL"
+ attribute \enum_value_0000001 "OP_NOP"
+ attribute \enum_value_0000010 "OP_ADD"
+ attribute \enum_value_0000011 "OP_ADDPCIS"
+ attribute \enum_value_0000100 "OP_AND"
+ attribute \enum_value_0000101 "OP_ATTN"
+ attribute \enum_value_0000110 "OP_B"
+ attribute \enum_value_0000111 "OP_BC"
+ attribute \enum_value_0001000 "OP_BCREG"
+ attribute \enum_value_0001001 "OP_BPERM"
+ attribute \enum_value_0001010 "OP_CMP"
+ attribute \enum_value_0001011 "OP_CMPB"
+ attribute \enum_value_0001100 "OP_CMPEQB"
+ attribute \enum_value_0001101 "OP_CMPRB"
+ attribute \enum_value_0001110 "OP_CNTZ"
+ attribute \enum_value_0001111 "OP_CRAND"
+ attribute \enum_value_0010000 "OP_CRANDC"
+ attribute \enum_value_0010001 "OP_CREQV"
+ attribute \enum_value_0010010 "OP_CRNAND"
+ attribute \enum_value_0010011 "OP_CRNOR"
+ attribute \enum_value_0010100 "OP_CROR"
+ attribute \enum_value_0010101 "OP_CRORC"
+ attribute \enum_value_0010110 "OP_CRXOR"
+ attribute \enum_value_0010111 "OP_DARN"
+ attribute \enum_value_0011000 "OP_DCBF"
+ attribute \enum_value_0011001 "OP_DCBST"
+ attribute \enum_value_0011010 "OP_DCBT"
+ attribute \enum_value_0011011 "OP_DCBTST"
+ attribute \enum_value_0011100 "OP_DCBZ"
+ attribute \enum_value_0011101 "OP_DIV"
+ attribute \enum_value_0011110 "OP_DIVE"
+ attribute \enum_value_0011111 "OP_EXTS"
+ attribute \enum_value_0100000 "OP_EXTSWSLI"
+ attribute \enum_value_0100001 "OP_ICBI"
+ attribute \enum_value_0100010 "OP_ICBT"
+ attribute \enum_value_0100011 "OP_ISEL"
+ attribute \enum_value_0100100 "OP_ISYNC"
+ attribute \enum_value_0100101 "OP_LOAD"
+ attribute \enum_value_0100110 "OP_STORE"
+ attribute \enum_value_0100111 "OP_MADDHD"
+ attribute \enum_value_0101000 "OP_MADDHDU"
+ attribute \enum_value_0101001 "OP_MADDLD"
+ attribute \enum_value_0101010 "OP_MCRF"
+ attribute \enum_value_0101011 "OP_MCRXR"
+ attribute \enum_value_0101100 "OP_MCRXRX"
+ attribute \enum_value_0101101 "OP_MFCR"
+ attribute \enum_value_0101110 "OP_MFSPR"
+ attribute \enum_value_0101111 "OP_MOD"
+ attribute \enum_value_0110000 "OP_MTCRF"
+ attribute \enum_value_0110001 "OP_MTSPR"
+ attribute \enum_value_0110010 "OP_MUL_L64"
+ attribute \enum_value_0110011 "OP_MUL_H64"
+ attribute \enum_value_0110100 "OP_MUL_H32"
+ attribute \enum_value_0110101 "OP_OR"
+ attribute \enum_value_0110110 "OP_POPCNT"
+ attribute \enum_value_0110111 "OP_PRTY"
+ attribute \enum_value_0111000 "OP_RLC"
+ attribute \enum_value_0111001 "OP_RLCL"
+ attribute \enum_value_0111010 "OP_RLCR"
+ attribute \enum_value_0111011 "OP_SETB"
+ attribute \enum_value_0111100 "OP_SHL"
+ attribute \enum_value_0111101 "OP_SHR"
+ attribute \enum_value_0111110 "OP_SYNC"
+ attribute \enum_value_0111111 "OP_TRAP"
+ attribute \enum_value_1000011 "OP_XOR"
+ attribute \enum_value_1000100 "OP_SIM_CONFIG"
+ attribute \enum_value_1000101 "OP_CROP"
+ attribute \enum_value_1000110 "OP_RFID"
+ attribute \enum_value_1000111 "OP_MFMSR"
+ attribute \enum_value_1001000 "OP_MTMSRD"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 7 \op__insn_type$84
+ attribute \enum_base_type "Function"
+ attribute \enum_value_00000000000 "NONE"
+ attribute \enum_value_00000000010 "ALU"
+ attribute \enum_value_00000000100 "LDST"
+ attribute \enum_value_00000001000 "SHIFT_ROT"
+ attribute \enum_value_00000010000 "LOGICAL"
+ attribute \enum_value_00000100000 "BRANCH"
+ attribute \enum_value_00001000000 "CR"
+ attribute \enum_value_00010000000 "TRAP"
+ attribute \enum_value_00100000000 "MUL"
+ attribute \enum_value_01000000000 "DIV"
+ attribute \enum_value_10000000000 "SPR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 11 \op__fn_unit$85
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 \op__imm_data__imm$86
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__imm_data__imm_ok$87
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__rc__rc$88
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__rc__rc_ok$89
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__oe__oe$90
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__oe__oe_ok$91
+ attribute \enum_base_type "CryIn"
+ attribute \enum_value_00 "ZERO"
+ attribute \enum_value_01 "ONE"
+ attribute \enum_value_10 "CA"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 2 \op__input_carry$92
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__output_carry$93
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__input_cr$94
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__output_cr$95
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__is_32bit$96
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__is_signed$97
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 \op__insn$98
+ process $group_69
+ assign \op__insn_type$84 7'0000000
+ assign \op__fn_unit$85 11'00000000000
+ assign \op__imm_data__imm$86 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \op__imm_data__imm_ok$87 1'0
+ assign \op__rc__rc$88 1'0
+ assign \op__rc__rc_ok$89 1'0
+ assign \op__oe__oe$90 1'0
+ assign \op__oe__oe_ok$91 1'0
+ assign { } 0'0
+ assign \op__input_carry$92 2'00
+ assign \op__output_carry$93 1'0
+ assign \op__input_cr$94 1'0
+ assign \op__output_cr$95 1'0
+ assign \op__is_32bit$96 1'0
+ assign \op__is_signed$97 1'0
+ assign \op__insn$98 32'00000000000000000000000000000000
+ assign { \op__insn$98 \op__is_signed$97 \op__is_32bit$96 \op__output_cr$95 \op__input_cr$94 \op__output_carry$93 \op__input_carry$92 { } { \op__oe__oe_ok$91 \op__oe__oe$90 } { \op__rc__rc_ok$89 \op__rc__rc$88 } { \op__imm_data__imm_ok$87 \op__imm_data__imm$86 } \op__fn_unit$85 \op__insn_type$84 } { \output_op__insn$69 \output_op__is_signed$68 \output_op__is_32bit$67 \output_op__output_cr$66 \output_op__input_cr$65 \output_op__output_carry$64 \output_op__input_carry$63 { } { \output_op__oe__oe_ok$62 \output_op__oe__oe$61 } { \output_op__rc__rc_ok$60 \output_op__rc__rc$59 } { \output_op__imm_data__imm_ok$58 \output_op__imm_data__imm$57 } \output_op__fn_unit$56 \output_op__insn_type$55 }
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 64 \o$99
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 \o_ok$100
+ process $group_85
+ assign \o$99 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \o_ok$100 1'0
+ assign { \o_ok$100 \o$99 } { \output_o_ok$71 \output_o$70 }
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 4 \cr_a$101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 \cr_a_ok$102
+ process $group_87
+ assign \cr_a$101 4'0000
+ assign \cr_a_ok$102 1'0
+ assign { \cr_a_ok$102 \cr_a$101 } { \output_cr_a_ok \output_cr_a$72 }
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 2 \xer_ca$103
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 \xer_ca_ok$104
+ process $group_89
+ assign \xer_ca$103 2'00
+ assign \xer_ca_ok$104 1'0
+ assign { \xer_ca_ok$104 \xer_ca$103 } { \output_xer_ca_ok \output_xer_ca$73 }
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615"
+ wire width 1 \r_busy
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615"
+ wire width 1 \r_busy$next
+ process $group_91
+ assign \r_busy$next \r_busy
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+ switch { \n_i_rdy_data \p_valid_i_p_ready_o }
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+ case 2'-1
+ assign \r_busy$next 1'1
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
+ case 2'1-
+ assign \r_busy$next 1'0
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+ switch \rst
+ case 1'1
+ assign \r_busy$next 1'0
+ end
+ sync init
+ update \r_busy 1'0
+ sync posedge \clk
+ update \r_busy \r_busy$next
+ end
+ process $group_92
+ assign \muxid$1$next \muxid$1
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+ switch { \n_i_rdy_data \p_valid_i_p_ready_o }
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+ case 2'-1
+ assign \muxid$1$next \muxid$83
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
+ case 2'1-
+ assign \muxid$1$next \muxid$83
+ end
+ sync init
+ update \muxid$1 2'00
+ sync posedge \clk
+ update \muxid$1 \muxid$1$next
+ end
+ process $group_93
+ assign \op__insn_type$2$next \op__insn_type$2
+ assign \op__fn_unit$3$next \op__fn_unit$3
+ assign \op__imm_data__imm$4$next \op__imm_data__imm$4
+ assign \op__imm_data__imm_ok$5$next \op__imm_data__imm_ok$5
+ assign \op__rc__rc$6$next \op__rc__rc$6
+ assign \op__rc__rc_ok$7$next \op__rc__rc_ok$7
+ assign \op__oe__oe$8$next \op__oe__oe$8
+ assign \op__oe__oe_ok$9$next \op__oe__oe_ok$9
+ assign { } { }
+ assign \op__input_carry$10$next \op__input_carry$10
+ assign \op__output_carry$11$next \op__output_carry$11
+ assign \op__input_cr$12$next \op__input_cr$12
+ assign \op__output_cr$13$next \op__output_cr$13
+ assign \op__is_32bit$14$next \op__is_32bit$14
+ assign \op__is_signed$15$next \op__is_signed$15
+ assign \op__insn$16$next \op__insn$16
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+ switch { \n_i_rdy_data \p_valid_i_p_ready_o }
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+ case 2'-1
+ assign { \op__insn$16$next \op__is_signed$15$next \op__is_32bit$14$next \op__output_cr$13$next \op__input_cr$12$next \op__output_carry$11$next \op__input_carry$10$next { } { \op__oe__oe_ok$9$next \op__oe__oe$8$next } { \op__rc__rc_ok$7$next \op__rc__rc$6$next } { \op__imm_data__imm_ok$5$next \op__imm_data__imm$4$next } \op__fn_unit$3$next \op__insn_type$2$next } { \op__insn$98 \op__is_signed$97 \op__is_32bit$96 \op__output_cr$95 \op__input_cr$94 \op__output_carry$93 \op__input_carry$92 { } { \op__oe__oe_ok$91 \op__oe__oe$90 } { \op__rc__rc_ok$89 \op__rc__rc$88 } { \op__imm_data__imm_ok$87 \op__imm_data__imm$86 } \op__fn_unit$85 \op__insn_type$84 }
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
+ case 2'1-
+ assign { \op__insn$16$next \op__is_signed$15$next \op__is_32bit$14$next \op__output_cr$13$next \op__input_cr$12$next \op__output_carry$11$next \op__input_carry$10$next { } { \op__oe__oe_ok$9$next \op__oe__oe$8$next } { \op__rc__rc_ok$7$next \op__rc__rc$6$next } { \op__imm_data__imm_ok$5$next \op__imm_data__imm$4$next } \op__fn_unit$3$next \op__insn_type$2$next } { \op__insn$98 \op__is_signed$97 \op__is_32bit$96 \op__output_cr$95 \op__input_cr$94 \op__output_carry$93 \op__input_carry$92 { } { \op__oe__oe_ok$91 \op__oe__oe$90 } { \op__rc__rc_ok$89 \op__rc__rc$88 } { \op__imm_data__imm_ok$87 \op__imm_data__imm$86 } \op__fn_unit$85 \op__insn_type$84 }
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+ switch \rst
+ case 1'1
+ assign \op__imm_data__imm$4$next 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \op__imm_data__imm_ok$5$next 1'0
+ assign \op__rc__rc$6$next 1'0
+ assign \op__rc__rc_ok$7$next 1'0
+ assign \op__oe__oe$8$next 1'0
+ assign \op__oe__oe_ok$9$next 1'0
+ end
+ sync init
+ update \op__insn_type$2 7'0000000
+ update \op__fn_unit$3 11'00000000000
+ update \op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000
+ update \op__imm_data__imm_ok$5 1'0
+ update \op__rc__rc$6 1'0
+ update \op__rc__rc_ok$7 1'0
+ update \op__oe__oe$8 1'0
+ update \op__oe__oe_ok$9 1'0
+ update { } 0'0
+ update \op__input_carry$10 2'00
+ update \op__output_carry$11 1'0
+ update \op__input_cr$12 1'0
+ update \op__output_cr$13 1'0
+ update \op__is_32bit$14 1'0
+ update \op__is_signed$15 1'0
+ update \op__insn$16 32'00000000000000000000000000000000
+ sync posedge \clk
+ update \op__insn_type$2 \op__insn_type$2$next
+ update \op__fn_unit$3 \op__fn_unit$3$next
+ update \op__imm_data__imm$4 \op__imm_data__imm$4$next
+ update \op__imm_data__imm_ok$5 \op__imm_data__imm_ok$5$next
+ update \op__rc__rc$6 \op__rc__rc$6$next
+ update \op__rc__rc_ok$7 \op__rc__rc_ok$7$next
+ update \op__oe__oe$8 \op__oe__oe$8$next
+ update \op__oe__oe_ok$9 \op__oe__oe_ok$9$next
+ update { } { }
+ update \op__input_carry$10 \op__input_carry$10$next
+ update \op__output_carry$11 \op__output_carry$11$next
+ update \op__input_cr$12 \op__input_cr$12$next
+ update \op__output_cr$13 \op__output_cr$13$next
+ update \op__is_32bit$14 \op__is_32bit$14$next
+ update \op__is_signed$15 \op__is_signed$15$next
+ update \op__insn$16 \op__insn$16$next
+ end
+ process $group_109
+ assign \o$next \o
+ assign \o_ok$next \o_ok
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+ switch { \n_i_rdy_data \p_valid_i_p_ready_o }
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+ case 2'-1
+ assign { \o_ok$next \o$next } { \o_ok$100 \o$99 }
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
+ case 2'1-
+ assign { \o_ok$next \o$next } { \o_ok$100 \o$99 }
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+ switch \rst
+ case 1'1
+ assign \o_ok$next 1'0
+ end
+ sync init
+ update \o 64'0000000000000000000000000000000000000000000000000000000000000000
+ update \o_ok 1'0
+ sync posedge \clk
+ update \o \o$next
+ update \o_ok \o_ok$next
+ end
+ process $group_111
+ assign \cr_a$next \cr_a
+ assign \cr_a_ok$next \cr_a_ok
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+ switch { \n_i_rdy_data \p_valid_i_p_ready_o }
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+ case 2'-1
+ assign { \cr_a_ok$next \cr_a$next } { \cr_a_ok$102 \cr_a$101 }
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
+ case 2'1-
+ assign { \cr_a_ok$next \cr_a$next } { \cr_a_ok$102 \cr_a$101 }
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+ switch \rst
+ case 1'1
+ assign \cr_a_ok$next 1'0
+ end
+ sync init
+ update \cr_a 4'0000
+ update \cr_a_ok 1'0
+ sync posedge \clk
+ update \cr_a \cr_a$next
+ update \cr_a_ok \cr_a_ok$next
+ end
+ process $group_113
+ assign \xer_ca$17$next \xer_ca$17
+ assign \xer_ca_ok$next \xer_ca_ok
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+ switch { \n_i_rdy_data \p_valid_i_p_ready_o }
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+ case 2'-1
+ assign { \xer_ca_ok$next \xer_ca$17$next } { \xer_ca_ok$104 \xer_ca$103 }
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
+ case 2'1-
+ assign { \xer_ca_ok$next \xer_ca$17$next } { \xer_ca_ok$104 \xer_ca$103 }
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+ switch \rst
+ case 1'1
+ assign \xer_ca_ok$next 1'0
+ end
+ sync init
+ update \xer_ca$17 2'00
+ update \xer_ca_ok 1'0
+ sync posedge \clk
+ update \xer_ca$17 \xer_ca$17$next
+ update \xer_ca_ok \xer_ca_ok$next
+ end
+ process $group_115
+ assign \n_valid_o 1'0
+ assign \n_valid_o \r_busy
+ sync init
+ end
+ process $group_116
+ assign \p_ready_o 1'0
+ assign \p_ready_o \n_i_rdy_data
+ sync init
+ end
+ connect \cr_a$76 4'0000
+ connect \cr_a_ok$77 1'0
+ connect \xer_ca_ok$79 1'0
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0"
+module \alu_shift_rot0
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
+ wire width 1 input 0 \rst
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
+ wire width 1 input 1 \clk
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 2 \o_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 3 \cr_a_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 4 \xer_ca_ok
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
+ wire width 1 output 5 \n_valid_o
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
+ wire width 1 input 6 \n_ready_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 64 output 7 \o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 4 output 8 \cr_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 2 output 9 \xer_ca
+ attribute \enum_base_type "MicrOp"
+ attribute \enum_value_0000000 "OP_ILLEGAL"
+ attribute \enum_value_0000001 "OP_NOP"
+ attribute \enum_value_0000010 "OP_ADD"
+ attribute \enum_value_0000011 "OP_ADDPCIS"
+ attribute \enum_value_0000100 "OP_AND"
+ attribute \enum_value_0000101 "OP_ATTN"
+ attribute \enum_value_0000110 "OP_B"
+ attribute \enum_value_0000111 "OP_BC"
+ attribute \enum_value_0001000 "OP_BCREG"
+ attribute \enum_value_0001001 "OP_BPERM"
+ attribute \enum_value_0001010 "OP_CMP"
+ attribute \enum_value_0001011 "OP_CMPB"
+ attribute \enum_value_0001100 "OP_CMPEQB"
+ attribute \enum_value_0001101 "OP_CMPRB"
+ attribute \enum_value_0001110 "OP_CNTZ"
+ attribute \enum_value_0001111 "OP_CRAND"
+ attribute \enum_value_0010000 "OP_CRANDC"
+ attribute \enum_value_0010001 "OP_CREQV"
+ attribute \enum_value_0010010 "OP_CRNAND"
+ attribute \enum_value_0010011 "OP_CRNOR"
+ attribute \enum_value_0010100 "OP_CROR"
+ attribute \enum_value_0010101 "OP_CRORC"
+ attribute \enum_value_0010110 "OP_CRXOR"
+ attribute \enum_value_0010111 "OP_DARN"
+ attribute \enum_value_0011000 "OP_DCBF"
+ attribute \enum_value_0011001 "OP_DCBST"
+ attribute \enum_value_0011010 "OP_DCBT"
+ attribute \enum_value_0011011 "OP_DCBTST"
+ attribute \enum_value_0011100 "OP_DCBZ"
+ attribute \enum_value_0011101 "OP_DIV"
+ attribute \enum_value_0011110 "OP_DIVE"
+ attribute \enum_value_0011111 "OP_EXTS"
+ attribute \enum_value_0100000 "OP_EXTSWSLI"
+ attribute \enum_value_0100001 "OP_ICBI"
+ attribute \enum_value_0100010 "OP_ICBT"
+ attribute \enum_value_0100011 "OP_ISEL"
+ attribute \enum_value_0100100 "OP_ISYNC"
+ attribute \enum_value_0100101 "OP_LOAD"
+ attribute \enum_value_0100110 "OP_STORE"
+ attribute \enum_value_0100111 "OP_MADDHD"
+ attribute \enum_value_0101000 "OP_MADDHDU"
+ attribute \enum_value_0101001 "OP_MADDLD"
+ attribute \enum_value_0101010 "OP_MCRF"
+ attribute \enum_value_0101011 "OP_MCRXR"
+ attribute \enum_value_0101100 "OP_MCRXRX"
+ attribute \enum_value_0101101 "OP_MFCR"
+ attribute \enum_value_0101110 "OP_MFSPR"
+ attribute \enum_value_0101111 "OP_MOD"
+ attribute \enum_value_0110000 "OP_MTCRF"
+ attribute \enum_value_0110001 "OP_MTSPR"
+ attribute \enum_value_0110010 "OP_MUL_L64"
+ attribute \enum_value_0110011 "OP_MUL_H64"
+ attribute \enum_value_0110100 "OP_MUL_H32"
+ attribute \enum_value_0110101 "OP_OR"
+ attribute \enum_value_0110110 "OP_POPCNT"
+ attribute \enum_value_0110111 "OP_PRTY"
+ attribute \enum_value_0111000 "OP_RLC"
+ attribute \enum_value_0111001 "OP_RLCL"
+ attribute \enum_value_0111010 "OP_RLCR"
+ attribute \enum_value_0111011 "OP_SETB"
+ attribute \enum_value_0111100 "OP_SHL"
+ attribute \enum_value_0111101 "OP_SHR"
+ attribute \enum_value_0111110 "OP_SYNC"
+ attribute \enum_value_0111111 "OP_TRAP"
+ attribute \enum_value_1000011 "OP_XOR"
+ attribute \enum_value_1000100 "OP_SIM_CONFIG"
+ attribute \enum_value_1000101 "OP_CROP"
+ attribute \enum_value_1000110 "OP_RFID"
+ attribute \enum_value_1000111 "OP_MFMSR"
+ attribute \enum_value_1001000 "OP_MTMSRD"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 7 input 10 \op__insn_type
+ attribute \enum_base_type "Function"
+ attribute \enum_value_00000000000 "NONE"
+ attribute \enum_value_00000000010 "ALU"
+ attribute \enum_value_00000000100 "LDST"
+ attribute \enum_value_00000001000 "SHIFT_ROT"
+ attribute \enum_value_00000010000 "LOGICAL"
+ attribute \enum_value_00000100000 "BRANCH"
+ attribute \enum_value_00001000000 "CR"
+ attribute \enum_value_00010000000 "TRAP"
+ attribute \enum_value_00100000000 "MUL"
+ attribute \enum_value_01000000000 "DIV"
+ attribute \enum_value_10000000000 "SPR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 11 input 11 \op__fn_unit
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 input 12 \op__imm_data__imm
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 13 \op__imm_data__imm_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 14 \op__rc__rc
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 15 \op__rc__rc_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 16 \op__oe__oe
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 17 \op__oe__oe_ok
+ attribute \enum_base_type "CryIn"
+ attribute \enum_value_00 "ZERO"
+ attribute \enum_value_01 "ONE"
+ attribute \enum_value_10 "CA"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 2 input 19 \op__input_carry
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 20 \op__output_carry
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 21 \op__input_cr
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 22 \op__output_cr
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 23 \op__is_32bit
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 24 \op__is_signed
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 input 25 \op__insn
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 64 input 26 \ra
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 64 input 27 \rb
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 64 input 28 \rc
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 2 input 29 \xer_ca$1
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153"
+ wire width 1 input 30 \p_valid_i
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154"
+ wire width 1 output 31 \p_ready_o
+ cell \p$87 \p
+ connect \p_valid_i \p_valid_i
+ connect \p_ready_o \p_ready_o
+ end
+ cell \n$88 \n
+ connect \n_valid_o \n_valid_o
+ connect \n_ready_i \n_ready_i
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153"
+ wire width 1 \pipe_p_valid_i
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154"
+ wire width 1 \pipe_p_ready_o
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+ wire width 2 \pipe_muxid
+ attribute \enum_base_type "MicrOp"
+ attribute \enum_value_0000000 "OP_ILLEGAL"
+ attribute \enum_value_0000001 "OP_NOP"
+ attribute \enum_value_0000010 "OP_ADD"
+ attribute \enum_value_0000011 "OP_ADDPCIS"
+ attribute \enum_value_0000100 "OP_AND"
+ attribute \enum_value_0000101 "OP_ATTN"
+ attribute \enum_value_0000110 "OP_B"
+ attribute \enum_value_0000111 "OP_BC"
+ attribute \enum_value_0001000 "OP_BCREG"
+ attribute \enum_value_0001001 "OP_BPERM"
+ attribute \enum_value_0001010 "OP_CMP"
+ attribute \enum_value_0001011 "OP_CMPB"
+ attribute \enum_value_0001100 "OP_CMPEQB"
+ attribute \enum_value_0001101 "OP_CMPRB"
+ attribute \enum_value_0001110 "OP_CNTZ"
+ attribute \enum_value_0001111 "OP_CRAND"
+ attribute \enum_value_0010000 "OP_CRANDC"
+ attribute \enum_value_0010001 "OP_CREQV"
+ attribute \enum_value_0010010 "OP_CRNAND"
+ attribute \enum_value_0010011 "OP_CRNOR"
+ attribute \enum_value_0010100 "OP_CROR"
+ attribute \enum_value_0010101 "OP_CRORC"
+ attribute \enum_value_0010110 "OP_CRXOR"
+ attribute \enum_value_0010111 "OP_DARN"
+ attribute \enum_value_0011000 "OP_DCBF"
+ attribute \enum_value_0011001 "OP_DCBST"
+ attribute \enum_value_0011010 "OP_DCBT"
+ attribute \enum_value_0011011 "OP_DCBTST"
+ attribute \enum_value_0011100 "OP_DCBZ"
+ attribute \enum_value_0011101 "OP_DIV"
+ attribute \enum_value_0011110 "OP_DIVE"
+ attribute \enum_value_0011111 "OP_EXTS"
+ attribute \enum_value_0100000 "OP_EXTSWSLI"
+ attribute \enum_value_0100001 "OP_ICBI"
+ attribute \enum_value_0100010 "OP_ICBT"
+ attribute \enum_value_0100011 "OP_ISEL"
+ attribute \enum_value_0100100 "OP_ISYNC"
+ attribute \enum_value_0100101 "OP_LOAD"
+ attribute \enum_value_0100110 "OP_STORE"
+ attribute \enum_value_0100111 "OP_MADDHD"
+ attribute \enum_value_0101000 "OP_MADDHDU"
+ attribute \enum_value_0101001 "OP_MADDLD"
+ attribute \enum_value_0101010 "OP_MCRF"
+ attribute \enum_value_0101011 "OP_MCRXR"
+ attribute \enum_value_0101100 "OP_MCRXRX"
+ attribute \enum_value_0101101 "OP_MFCR"
+ attribute \enum_value_0101110 "OP_MFSPR"
+ attribute \enum_value_0101111 "OP_MOD"
+ attribute \enum_value_0110000 "OP_MTCRF"
+ attribute \enum_value_0110001 "OP_MTSPR"
+ attribute \enum_value_0110010 "OP_MUL_L64"
+ attribute \enum_value_0110011 "OP_MUL_H64"
+ attribute \enum_value_0110100 "OP_MUL_H32"
+ attribute \enum_value_0110101 "OP_OR"
+ attribute \enum_value_0110110 "OP_POPCNT"
+ attribute \enum_value_0110111 "OP_PRTY"
+ attribute \enum_value_0111000 "OP_RLC"
+ attribute \enum_value_0111001 "OP_RLCL"
+ attribute \enum_value_0111010 "OP_RLCR"
+ attribute \enum_value_0111011 "OP_SETB"
+ attribute \enum_value_0111100 "OP_SHL"
+ attribute \enum_value_0111101 "OP_SHR"
+ attribute \enum_value_0111110 "OP_SYNC"
+ attribute \enum_value_0111111 "OP_TRAP"
+ attribute \enum_value_1000011 "OP_XOR"
+ attribute \enum_value_1000100 "OP_SIM_CONFIG"
+ attribute \enum_value_1000101 "OP_CROP"
+ attribute \enum_value_1000110 "OP_RFID"
+ attribute \enum_value_1000111 "OP_MFMSR"
+ attribute \enum_value_1001000 "OP_MTMSRD"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 7 \pipe_op__insn_type
+ attribute \enum_base_type "Function"
+ attribute \enum_value_00000000000 "NONE"
+ attribute \enum_value_00000000010 "ALU"
+ attribute \enum_value_00000000100 "LDST"
+ attribute \enum_value_00000001000 "SHIFT_ROT"
+ attribute \enum_value_00000010000 "LOGICAL"
+ attribute \enum_value_00000100000 "BRANCH"
+ attribute \enum_value_00001000000 "CR"
+ attribute \enum_value_00010000000 "TRAP"
+ attribute \enum_value_00100000000 "MUL"
+ attribute \enum_value_01000000000 "DIV"
+ attribute \enum_value_10000000000 "SPR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 11 \pipe_op__fn_unit
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 \pipe_op__imm_data__imm
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \pipe_op__imm_data__imm_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \pipe_op__rc__rc
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \pipe_op__rc__rc_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \pipe_op__oe__oe
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \pipe_op__oe__oe_ok
+ attribute \enum_base_type "CryIn"
+ attribute \enum_value_00 "ZERO"
+ attribute \enum_value_01 "ONE"
+ attribute \enum_value_10 "CA"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 2 \pipe_op__input_carry
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \pipe_op__output_carry
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \pipe_op__input_cr
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \pipe_op__output_cr
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \pipe_op__is_32bit
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \pipe_op__is_signed
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 \pipe_op__insn
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 64 \pipe_ra
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 64 \pipe_rb
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 64 \pipe_rc
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 2 \pipe_xer_ca
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
+ wire width 1 \pipe_n_valid_o
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
+ wire width 1 \pipe_n_ready_i
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+ wire width 2 \pipe_muxid$2
+ attribute \enum_base_type "MicrOp"
+ attribute \enum_value_0000000 "OP_ILLEGAL"
+ attribute \enum_value_0000001 "OP_NOP"
+ attribute \enum_value_0000010 "OP_ADD"
+ attribute \enum_value_0000011 "OP_ADDPCIS"
+ attribute \enum_value_0000100 "OP_AND"
+ attribute \enum_value_0000101 "OP_ATTN"
+ attribute \enum_value_0000110 "OP_B"
+ attribute \enum_value_0000111 "OP_BC"
+ attribute \enum_value_0001000 "OP_BCREG"
+ attribute \enum_value_0001001 "OP_BPERM"
+ attribute \enum_value_0001010 "OP_CMP"
+ attribute \enum_value_0001011 "OP_CMPB"
+ attribute \enum_value_0001100 "OP_CMPEQB"
+ attribute \enum_value_0001101 "OP_CMPRB"
+ attribute \enum_value_0001110 "OP_CNTZ"
+ attribute \enum_value_0001111 "OP_CRAND"
+ attribute \enum_value_0010000 "OP_CRANDC"
+ attribute \enum_value_0010001 "OP_CREQV"
+ attribute \enum_value_0010010 "OP_CRNAND"
+ attribute \enum_value_0010011 "OP_CRNOR"
+ attribute \enum_value_0010100 "OP_CROR"
+ attribute \enum_value_0010101 "OP_CRORC"
+ attribute \enum_value_0010110 "OP_CRXOR"
+ attribute \enum_value_0010111 "OP_DARN"
+ attribute \enum_value_0011000 "OP_DCBF"
+ attribute \enum_value_0011001 "OP_DCBST"
+ attribute \enum_value_0011010 "OP_DCBT"
+ attribute \enum_value_0011011 "OP_DCBTST"
+ attribute \enum_value_0011100 "OP_DCBZ"
+ attribute \enum_value_0011101 "OP_DIV"
+ attribute \enum_value_0011110 "OP_DIVE"
+ attribute \enum_value_0011111 "OP_EXTS"
+ attribute \enum_value_0100000 "OP_EXTSWSLI"
+ attribute \enum_value_0100001 "OP_ICBI"
+ attribute \enum_value_0100010 "OP_ICBT"
+ attribute \enum_value_0100011 "OP_ISEL"
+ attribute \enum_value_0100100 "OP_ISYNC"
+ attribute \enum_value_0100101 "OP_LOAD"
+ attribute \enum_value_0100110 "OP_STORE"
+ attribute \enum_value_0100111 "OP_MADDHD"
+ attribute \enum_value_0101000 "OP_MADDHDU"
+ attribute \enum_value_0101001 "OP_MADDLD"
+ attribute \enum_value_0101010 "OP_MCRF"
+ attribute \enum_value_0101011 "OP_MCRXR"
+ attribute \enum_value_0101100 "OP_MCRXRX"
+ attribute \enum_value_0101101 "OP_MFCR"
+ attribute \enum_value_0101110 "OP_MFSPR"
+ attribute \enum_value_0101111 "OP_MOD"
+ attribute \enum_value_0110000 "OP_MTCRF"
+ attribute \enum_value_0110001 "OP_MTSPR"
+ attribute \enum_value_0110010 "OP_MUL_L64"
+ attribute \enum_value_0110011 "OP_MUL_H64"
+ attribute \enum_value_0110100 "OP_MUL_H32"
+ attribute \enum_value_0110101 "OP_OR"
+ attribute \enum_value_0110110 "OP_POPCNT"
+ attribute \enum_value_0110111 "OP_PRTY"
+ attribute \enum_value_0111000 "OP_RLC"
+ attribute \enum_value_0111001 "OP_RLCL"
+ attribute \enum_value_0111010 "OP_RLCR"
+ attribute \enum_value_0111011 "OP_SETB"
+ attribute \enum_value_0111100 "OP_SHL"
+ attribute \enum_value_0111101 "OP_SHR"
+ attribute \enum_value_0111110 "OP_SYNC"
+ attribute \enum_value_0111111 "OP_TRAP"
+ attribute \enum_value_1000011 "OP_XOR"
+ attribute \enum_value_1000100 "OP_SIM_CONFIG"
+ attribute \enum_value_1000101 "OP_CROP"
+ attribute \enum_value_1000110 "OP_RFID"
+ attribute \enum_value_1000111 "OP_MFMSR"
+ attribute \enum_value_1001000 "OP_MTMSRD"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 7 \pipe_op__insn_type$3
+ attribute \enum_base_type "Function"
+ attribute \enum_value_00000000000 "NONE"
+ attribute \enum_value_00000000010 "ALU"
+ attribute \enum_value_00000000100 "LDST"
+ attribute \enum_value_00000001000 "SHIFT_ROT"
+ attribute \enum_value_00000010000 "LOGICAL"
+ attribute \enum_value_00000100000 "BRANCH"
+ attribute \enum_value_00001000000 "CR"
+ attribute \enum_value_00010000000 "TRAP"
+ attribute \enum_value_00100000000 "MUL"
+ attribute \enum_value_01000000000 "DIV"
+ attribute \enum_value_10000000000 "SPR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 11 \pipe_op__fn_unit$4
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 \pipe_op__imm_data__imm$5
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \pipe_op__imm_data__imm_ok$6
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \pipe_op__rc__rc$7
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \pipe_op__rc__rc_ok$8
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \pipe_op__oe__oe$9
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \pipe_op__oe__oe_ok$10
+ attribute \enum_base_type "CryIn"
+ attribute \enum_value_00 "ZERO"
+ attribute \enum_value_01 "ONE"
+ attribute \enum_value_10 "CA"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 2 \pipe_op__input_carry$11
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \pipe_op__output_carry$12
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \pipe_op__input_cr$13
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \pipe_op__output_cr$14
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \pipe_op__is_32bit$15
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \pipe_op__is_signed$16
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 \pipe_op__insn$17
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 64 \pipe_o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 \pipe_o_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 4 \pipe_cr_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 \pipe_cr_a_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 2 \pipe_xer_ca$18
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 \pipe_xer_ca_ok
+ cell \pipe$89 \pipe
+ connect \rst \rst
+ connect \clk \clk
+ connect \p_valid_i \pipe_p_valid_i
+ connect \p_ready_o \pipe_p_ready_o
+ connect \muxid \pipe_muxid
+ connect \op__insn_type \pipe_op__insn_type
+ connect \op__fn_unit \pipe_op__fn_unit
+ connect \op__imm_data__imm \pipe_op__imm_data__imm
+ connect \op__imm_data__imm_ok \pipe_op__imm_data__imm_ok
+ connect \op__rc__rc \pipe_op__rc__rc
+ connect \op__rc__rc_ok \pipe_op__rc__rc_ok
+ connect \op__oe__oe \pipe_op__oe__oe
+ connect \op__oe__oe_ok \pipe_op__oe__oe_ok
+ connect \op__input_carry \pipe_op__input_carry
+ connect \op__output_carry \pipe_op__output_carry
+ connect \op__input_cr \pipe_op__input_cr
+ connect \op__output_cr \pipe_op__output_cr
+ connect \op__is_32bit \pipe_op__is_32bit
+ connect \op__is_signed \pipe_op__is_signed
+ connect \op__insn \pipe_op__insn
+ connect \ra \pipe_ra
+ connect \rb \pipe_rb
+ connect \rc \pipe_rc
+ connect \xer_ca \pipe_xer_ca
+ connect \n_valid_o \pipe_n_valid_o
+ connect \n_ready_i \pipe_n_ready_i
+ connect \muxid$1 \pipe_muxid$2
+ connect \op__insn_type$2 \pipe_op__insn_type$3
+ connect \op__fn_unit$3 \pipe_op__fn_unit$4
+ connect \op__imm_data__imm$4 \pipe_op__imm_data__imm$5
+ connect \op__imm_data__imm_ok$5 \pipe_op__imm_data__imm_ok$6
+ connect \op__rc__rc$6 \pipe_op__rc__rc$7
+ connect \op__rc__rc_ok$7 \pipe_op__rc__rc_ok$8
+ connect \op__oe__oe$8 \pipe_op__oe__oe$9
+ connect \op__oe__oe_ok$9 \pipe_op__oe__oe_ok$10
+ connect \op__input_carry$10 \pipe_op__input_carry$11
+ connect \op__output_carry$11 \pipe_op__output_carry$12
+ connect \op__input_cr$12 \pipe_op__input_cr$13
+ connect \op__output_cr$13 \pipe_op__output_cr$14
+ connect \op__is_32bit$14 \pipe_op__is_32bit$15
+ connect \op__is_signed$15 \pipe_op__is_signed$16
+ connect \op__insn$16 \pipe_op__insn$17
+ connect \o \pipe_o
+ connect \o_ok \pipe_o_ok
+ connect \cr_a \pipe_cr_a
+ connect \cr_a_ok \pipe_cr_a_ok
+ connect \xer_ca$17 \pipe_xer_ca$18
+ connect \xer_ca_ok \pipe_xer_ca_ok
+ end
+ process $group_0
+ assign \pipe_p_valid_i 1'0
+ assign \pipe_p_valid_i \p_valid_i
+ sync init
+ end
+ process $group_1
+ assign \p_ready_o 1'0
+ assign \p_ready_o \pipe_p_ready_o
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+ wire width 2 \muxid
+ process $group_2
+ assign \pipe_muxid 2'00
+ assign \pipe_muxid \muxid
+ sync init
+ end
+ process $group_3
+ assign \pipe_op__insn_type 7'0000000
+ assign \pipe_op__fn_unit 11'00000000000
+ assign \pipe_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \pipe_op__imm_data__imm_ok 1'0
+ assign \pipe_op__rc__rc 1'0
+ assign \pipe_op__rc__rc_ok 1'0
+ assign \pipe_op__oe__oe 1'0
+ assign \pipe_op__oe__oe_ok 1'0
+ assign { } 0'0
+ assign \pipe_op__input_carry 2'00
+ assign \pipe_op__output_carry 1'0
+ assign \pipe_op__input_cr 1'0
+ assign \pipe_op__output_cr 1'0
+ assign \pipe_op__is_32bit 1'0
+ assign \pipe_op__is_signed 1'0
+ assign \pipe_op__insn 32'00000000000000000000000000000000
+ assign { \pipe_op__insn \pipe_op__is_signed \pipe_op__is_32bit \pipe_op__output_cr \pipe_op__input_cr \pipe_op__output_carry \pipe_op__input_carry { } { \pipe_op__oe__oe_ok \pipe_op__oe__oe } { \pipe_op__rc__rc_ok \pipe_op__rc__rc } { \pipe_op__imm_data__imm_ok \pipe_op__imm_data__imm } \pipe_op__fn_unit \pipe_op__insn_type } { \op__insn \op__is_signed \op__is_32bit \op__output_cr \op__input_cr \op__output_carry \op__input_carry { } { \op__oe__oe_ok \op__oe__oe } { \op__rc__rc_ok \op__rc__rc } { \op__imm_data__imm_ok \op__imm_data__imm } \op__fn_unit \op__insn_type }
+ sync init
+ end
+ process $group_19
+ assign \pipe_ra 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \pipe_ra \ra
+ sync init
+ end
+ process $group_20
+ assign \pipe_rb 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \pipe_rb \rb
+ sync init
+ end
+ process $group_21
+ assign \pipe_rc 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \pipe_rc \rc
+ sync init
+ end
+ process $group_22
+ assign \pipe_xer_ca 2'00
+ assign \pipe_xer_ca \xer_ca$1
+ sync init
+ end
+ process $group_23
+ assign \n_valid_o 1'0
+ assign \n_valid_o \pipe_n_valid_o
+ sync init
+ end
+ process $group_24
+ assign \pipe_n_ready_i 1'0
+ assign \pipe_n_ready_i \n_ready_i
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:34"
+ wire width 2 \muxid$19
+ process $group_25
+ assign \muxid$19 2'00
+ assign \muxid$19 \pipe_muxid$2
+ sync init
+ end
+ attribute \enum_base_type "MicrOp"
+ attribute \enum_value_0000000 "OP_ILLEGAL"
+ attribute \enum_value_0000001 "OP_NOP"
+ attribute \enum_value_0000010 "OP_ADD"
+ attribute \enum_value_0000011 "OP_ADDPCIS"
+ attribute \enum_value_0000100 "OP_AND"
+ attribute \enum_value_0000101 "OP_ATTN"
+ attribute \enum_value_0000110 "OP_B"
+ attribute \enum_value_0000111 "OP_BC"
+ attribute \enum_value_0001000 "OP_BCREG"
+ attribute \enum_value_0001001 "OP_BPERM"
+ attribute \enum_value_0001010 "OP_CMP"
+ attribute \enum_value_0001011 "OP_CMPB"
+ attribute \enum_value_0001100 "OP_CMPEQB"
+ attribute \enum_value_0001101 "OP_CMPRB"
+ attribute \enum_value_0001110 "OP_CNTZ"
+ attribute \enum_value_0001111 "OP_CRAND"
+ attribute \enum_value_0010000 "OP_CRANDC"
+ attribute \enum_value_0010001 "OP_CREQV"
+ attribute \enum_value_0010010 "OP_CRNAND"
+ attribute \enum_value_0010011 "OP_CRNOR"
+ attribute \enum_value_0010100 "OP_CROR"
+ attribute \enum_value_0010101 "OP_CRORC"
+ attribute \enum_value_0010110 "OP_CRXOR"
+ attribute \enum_value_0010111 "OP_DARN"
+ attribute \enum_value_0011000 "OP_DCBF"
+ attribute \enum_value_0011001 "OP_DCBST"
+ attribute \enum_value_0011010 "OP_DCBT"
+ attribute \enum_value_0011011 "OP_DCBTST"
+ attribute \enum_value_0011100 "OP_DCBZ"
+ attribute \enum_value_0011101 "OP_DIV"
+ attribute \enum_value_0011110 "OP_DIVE"
+ attribute \enum_value_0011111 "OP_EXTS"
+ attribute \enum_value_0100000 "OP_EXTSWSLI"
+ attribute \enum_value_0100001 "OP_ICBI"
+ attribute \enum_value_0100010 "OP_ICBT"
+ attribute \enum_value_0100011 "OP_ISEL"
+ attribute \enum_value_0100100 "OP_ISYNC"
+ attribute \enum_value_0100101 "OP_LOAD"
+ attribute \enum_value_0100110 "OP_STORE"
+ attribute \enum_value_0100111 "OP_MADDHD"
+ attribute \enum_value_0101000 "OP_MADDHDU"
+ attribute \enum_value_0101001 "OP_MADDLD"
+ attribute \enum_value_0101010 "OP_MCRF"
+ attribute \enum_value_0101011 "OP_MCRXR"
+ attribute \enum_value_0101100 "OP_MCRXRX"
+ attribute \enum_value_0101101 "OP_MFCR"
+ attribute \enum_value_0101110 "OP_MFSPR"
+ attribute \enum_value_0101111 "OP_MOD"
+ attribute \enum_value_0110000 "OP_MTCRF"
+ attribute \enum_value_0110001 "OP_MTSPR"
+ attribute \enum_value_0110010 "OP_MUL_L64"
+ attribute \enum_value_0110011 "OP_MUL_H64"
+ attribute \enum_value_0110100 "OP_MUL_H32"
+ attribute \enum_value_0110101 "OP_OR"
+ attribute \enum_value_0110110 "OP_POPCNT"
+ attribute \enum_value_0110111 "OP_PRTY"
+ attribute \enum_value_0111000 "OP_RLC"
+ attribute \enum_value_0111001 "OP_RLCL"
+ attribute \enum_value_0111010 "OP_RLCR"
+ attribute \enum_value_0111011 "OP_SETB"
+ attribute \enum_value_0111100 "OP_SHL"
+ attribute \enum_value_0111101 "OP_SHR"
+ attribute \enum_value_0111110 "OP_SYNC"
+ attribute \enum_value_0111111 "OP_TRAP"
+ attribute \enum_value_1000011 "OP_XOR"
+ attribute \enum_value_1000100 "OP_SIM_CONFIG"
+ attribute \enum_value_1000101 "OP_CROP"
+ attribute \enum_value_1000110 "OP_RFID"
+ attribute \enum_value_1000111 "OP_MFMSR"
+ attribute \enum_value_1001000 "OP_MTMSRD"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 7 \op__insn_type$20
+ attribute \enum_base_type "Function"
+ attribute \enum_value_00000000000 "NONE"
+ attribute \enum_value_00000000010 "ALU"
+ attribute \enum_value_00000000100 "LDST"
+ attribute \enum_value_00000001000 "SHIFT_ROT"
+ attribute \enum_value_00000010000 "LOGICAL"
+ attribute \enum_value_00000100000 "BRANCH"
+ attribute \enum_value_00001000000 "CR"
+ attribute \enum_value_00010000000 "TRAP"
+ attribute \enum_value_00100000000 "MUL"
+ attribute \enum_value_01000000000 "DIV"
+ attribute \enum_value_10000000000 "SPR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 11 \op__fn_unit$21
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 \op__imm_data__imm$22
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__imm_data__imm_ok$23
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__rc__rc$24
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__rc__rc_ok$25
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__oe__oe$26
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__oe__oe_ok$27
+ attribute \enum_base_type "CryIn"
+ attribute \enum_value_00 "ZERO"
+ attribute \enum_value_01 "ONE"
+ attribute \enum_value_10 "CA"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 2 \op__input_carry$28
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__output_carry$29
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__input_cr$30
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__output_cr$31
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__is_32bit$32
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \op__is_signed$33
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 \op__insn$34
+ process $group_26
+ assign \op__insn_type$20 7'0000000
+ assign \op__fn_unit$21 11'00000000000
+ assign \op__imm_data__imm$22 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \op__imm_data__imm_ok$23 1'0
+ assign \op__rc__rc$24 1'0
+ assign \op__rc__rc_ok$25 1'0
+ assign \op__oe__oe$26 1'0
+ assign \op__oe__oe_ok$27 1'0
+ assign { } 0'0
+ assign \op__input_carry$28 2'00
+ assign \op__output_carry$29 1'0
+ assign \op__input_cr$30 1'0
+ assign \op__output_cr$31 1'0
+ assign \op__is_32bit$32 1'0
+ assign \op__is_signed$33 1'0
+ assign \op__insn$34 32'00000000000000000000000000000000
+ assign { \op__insn$34 \op__is_signed$33 \op__is_32bit$32 \op__output_cr$31 \op__input_cr$30 \op__output_carry$29 \op__input_carry$28 { } { \op__oe__oe_ok$27 \op__oe__oe$26 } { \op__rc__rc_ok$25 \op__rc__rc$24 } { \op__imm_data__imm_ok$23 \op__imm_data__imm$22 } \op__fn_unit$21 \op__insn_type$20 } { \pipe_op__insn$17 \pipe_op__is_signed$16 \pipe_op__is_32bit$15 \pipe_op__output_cr$14 \pipe_op__input_cr$13 \pipe_op__output_carry$12 \pipe_op__input_carry$11 { } { \pipe_op__oe__oe_ok$10 \pipe_op__oe__oe$9 } { \pipe_op__rc__rc_ok$8 \pipe_op__rc__rc$7 } { \pipe_op__imm_data__imm_ok$6 \pipe_op__imm_data__imm$5 } \pipe_op__fn_unit$4 \pipe_op__insn_type$3 }
+ sync init
+ end
+ process $group_42
+ assign \o 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \o_ok 1'0
+ assign { \o_ok \o } { \pipe_o_ok \pipe_o }
+ sync init
+ end
+ process $group_44
+ assign \cr_a 4'0000
+ assign \cr_a_ok 1'0
+ assign { \cr_a_ok \cr_a } { \pipe_cr_a_ok \pipe_cr_a }
+ sync init
+ end
+ process $group_46
+ assign \xer_ca 2'00
+ assign \xer_ca_ok 1'0
+ assign { \xer_ca_ok \xer_ca } { \pipe_xer_ca_ok \pipe_xer_ca$18 }
+ sync init
+ end
+ connect \muxid 2'00
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.src_l"
+module \src_l$95
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
+ wire width 1 input 0 \rst
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
+ wire width 1 input 1 \clk
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+ wire width 4 input 2 \s_src
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+ wire width 4 input 3 \r_src
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
+ wire width 4 output 4 \q_src
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
+ wire width 4 \q_int
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
+ wire width 4 \q_int$next
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+ wire width 4 $1
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+ cell $not $2
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 4
+ parameter \Y_WIDTH 4
+ connect \A \r_src
+ connect \Y $1
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+ wire width 4 $3
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+ cell $and $4
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 4
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 4
+ parameter \Y_WIDTH 4
+ connect \A \q_int
+ connect \B $1
+ connect \Y $3
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+ wire width 4 $5
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+ cell $or $6
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 4
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 4
+ parameter \Y_WIDTH 4
+ connect \A $3
+ connect \B \s_src
+ connect \Y $5
+ end
+ process $group_0
+ assign \q_int$next \q_int
+ assign \q_int$next $5
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+ switch \rst
+ case 1'1
+ assign \q_int$next 4'0000
+ end
+ sync init
+ update \q_int 4'0000
+ sync posedge \clk
+ update \q_int \q_int$next
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+ wire width 4 $7
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+ cell $not $8
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 4
+ parameter \Y_WIDTH 4
+ connect \A \r_src
+ connect \Y $7
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+ wire width 4 $9
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+ cell $and $10
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 4
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 4
+ parameter \Y_WIDTH 4
+ connect \A \q_int
+ connect \B $7
+ connect \Y $9
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+ wire width 4 $11
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+ cell $or $12
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 4
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 4
+ parameter \Y_WIDTH 4
+ connect \A $9
+ connect \B \s_src
+ connect \Y $11
+ end
+ process $group_1
+ assign \q_src 4'0000
+ assign \q_src $11
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
+ wire width 4 \qn_src
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
+ wire width 4 $13
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
+ cell $not $14
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 4
+ parameter \Y_WIDTH 4
+ connect \A \q_src
+ connect \Y $13
+ end
+ process $group_2
+ assign \qn_src 4'0000
+ assign \qn_src $13
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62"
+ wire width 4 \qlq_src
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
+ wire width 4 $15
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
+ cell $or $16
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 4
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 4
+ parameter \Y_WIDTH 4
+ connect \A \q_src
+ connect \B \q_int
+ connect \Y $15
+ end
+ process $group_3
+ assign \qlq_src 4'0000
+ assign \qlq_src $15
+ sync init
+ end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.opc_l"
+module \opc_l$96
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
+ wire width 1 input 0 \rst
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
+ wire width 1 input 1 \clk
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+ wire width 1 input 2 \s_opc
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+ wire width 1 input 3 \r_opc
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
wire width 1 output 4 \q_opc
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.req_l"
-module \req_l$80
+module \req_l$97
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.rst_l"
-module \rst_l$81
+module \rst_l$98
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.rok_l"
-module \rok_l$82
+module \rok_l$99
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alui_l"
-module \alui_l$83
+module \alui_l$100
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_l"
-module \alu_l$84
+module \alu_l$101
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
- attribute \enum_base_type "InternalOp"
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 7 input 2 \oper_i__insn_type
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00100000000 "MUL"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 11 input 3 \oper_i__fn_unit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 64 input 4 \oper_i__imm_data__imm
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 input 5 \oper_i__imm_data__imm_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 input 6 \oper_i__rc__rc
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 input 7 \oper_i__rc__rc_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 input 8 \oper_i__oe__oe
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 input 9 \oper_i__oe__oe_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 3 input 10 \oper_i__write_cr__data
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 input 11 \oper_i__write_cr__ok
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 2 input 12 \oper_i__input_carry
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 input 13 \oper_i__output_carry
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 input 14 \oper_i__input_cr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 input 15 \oper_i__output_cr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 input 16 \oper_i__is_32bit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 input 17 \oper_i__is_signed
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 32 input 18 \oper_i__insn
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 2 input 11 \oper_i__input_carry
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 12 \oper_i__output_carry
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 13 \oper_i__input_cr
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 14 \oper_i__output_cr
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 15 \oper_i__is_32bit
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 16 \oper_i__is_signed
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 input 17 \oper_i__insn
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94"
- wire width 1 input 19 \issue_i
+ wire width 1 input 18 \issue_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
- wire width 1 output 20 \busy_o
+ wire width 1 output 19 \busy_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:92"
- wire width 4 input 21 \rdmaskn
+ wire width 4 input 20 \rdmaskn
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 4 output 22 \rd__rel
+ wire width 4 output 21 \rd__rel
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 4 input 23 \rd__go
+ wire width 4 input 22 \rd__go
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
- wire width 64 input 24 \src1_i
+ wire width 64 input 23 \src1_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
- wire width 64 input 25 \src2_i
+ wire width 64 input 24 \src2_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
- wire width 64 input 26 \src3_i
+ wire width 64 input 25 \src3_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
- wire width 2 input 27 \src4_i
+ wire width 2 input 26 \src4_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 28 \o_ok
+ wire width 1 output 27 \o_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 3 output 29 \wr__rel
+ wire width 3 output 28 \wr__rel
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 3 input 30 \wr__go
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 output 31 \o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 32 \cr_a_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 4 output 33 \cr_a
+ wire width 3 input 29 \wr__go
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
+ wire width 64 output 30 \dest1_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 34 \xer_ca_ok
+ wire width 1 output 31 \cr_a_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
+ wire width 4 output 32 \dest2_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 2 output 35 \xer_ca
+ wire width 1 output 33 \xer_ca_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
+ wire width 2 output 34 \dest3_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96"
- wire width 1 input 36 \go_die_i
+ wire width 1 input 35 \go_die_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
- wire width 1 input 37 \shadown_i
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
- wire width 64 output 38 \dest1_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:244"
+ wire width 1 input 36 \shadown_i
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
wire width 1 \alu_shift_rot0_n_valid_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:245"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
wire width 1 \alu_shift_rot0_n_ready_i
- attribute \enum_base_type "InternalOp"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 64 \alu_shift_rot0_o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 4 \alu_shift_rot0_cr_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 2 \alu_shift_rot0_xer_ca
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 7 \alu_shift_rot0_op__insn_type
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00100000000 "MUL"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 11 \alu_shift_rot0_op__fn_unit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 64 \alu_shift_rot0_op__imm_data__imm
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \alu_shift_rot0_op__imm_data__imm_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \alu_shift_rot0_op__rc__rc
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \alu_shift_rot0_op__rc__rc_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \alu_shift_rot0_op__oe__oe
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \alu_shift_rot0_op__oe__oe_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 3 \alu_shift_rot0_op__write_cr__data
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 \alu_shift_rot0_op__write_cr__ok
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 2 \alu_shift_rot0_op__input_carry
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \alu_shift_rot0_op__output_carry
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \alu_shift_rot0_op__input_cr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \alu_shift_rot0_op__output_cr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \alu_shift_rot0_op__is_32bit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \alu_shift_rot0_op__is_signed
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 32 \alu_shift_rot0_op__insn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
wire width 64 \alu_shift_rot0_ra
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
wire width 64 \alu_shift_rot0_rb
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
wire width 64 \alu_shift_rot0_rc
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:19"
- wire width 2 \alu_shift_rot0_xer_ca
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:151"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:43"
+ wire width 2 \alu_shift_rot0_xer_ca$1
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153"
wire width 1 \alu_shift_rot0_p_valid_i
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:152"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154"
wire width 1 \alu_shift_rot0_p_ready_o
cell \alu_shift_rot0 \alu_shift_rot0
connect \rst \rst
connect \clk \clk
connect \o_ok \o_ok
- connect \o \o
connect \cr_a_ok \cr_a_ok
- connect \cr_a \cr_a
connect \xer_ca_ok \xer_ca_ok
- connect \xer_ca \xer_ca
connect \n_valid_o \alu_shift_rot0_n_valid_o
connect \n_ready_i \alu_shift_rot0_n_ready_i
+ connect \o \alu_shift_rot0_o
+ connect \cr_a \alu_shift_rot0_cr_a
+ connect \xer_ca \alu_shift_rot0_xer_ca
connect \op__insn_type \alu_shift_rot0_op__insn_type
connect \op__fn_unit \alu_shift_rot0_op__fn_unit
connect \op__imm_data__imm \alu_shift_rot0_op__imm_data__imm
connect \op__rc__rc_ok \alu_shift_rot0_op__rc__rc_ok
connect \op__oe__oe \alu_shift_rot0_op__oe__oe
connect \op__oe__oe_ok \alu_shift_rot0_op__oe__oe_ok
- connect \op__write_cr__data \alu_shift_rot0_op__write_cr__data
- connect \op__write_cr__ok \alu_shift_rot0_op__write_cr__ok
connect \op__input_carry \alu_shift_rot0_op__input_carry
connect \op__output_carry \alu_shift_rot0_op__output_carry
connect \op__input_cr \alu_shift_rot0_op__input_cr
connect \ra \alu_shift_rot0_ra
connect \rb \alu_shift_rot0_rb
connect \rc \alu_shift_rot0_rc
- connect \xer_ca$1 \alu_shift_rot0_xer_ca
+ connect \xer_ca$1 \alu_shift_rot0_xer_ca$1
connect \p_valid_i \alu_shift_rot0_p_valid_i
connect \p_ready_o \alu_shift_rot0_p_ready_o
end
wire width 4 \src_l_r_src$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
wire width 4 \src_l_q_src
- cell \src_l$78 \src_l
+ cell \src_l$95 \src_l
connect \rst \rst
connect \clk \clk
connect \s_src \src_l_s_src
wire width 1 \opc_l_r_opc$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
wire width 1 \opc_l_q_opc
- cell \opc_l$79 \opc_l
+ cell \opc_l$96 \opc_l
connect \rst \rst
connect \clk \clk
connect \s_opc \opc_l_s_opc
wire width 3 \req_l_s_req
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
wire width 3 \req_l_r_req
- cell \req_l$80 \req_l
+ cell \req_l$97 \req_l
connect \rst \rst
connect \clk \clk
connect \q_req \req_l_q_req
wire width 1 \rst_l_s_rst
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
wire width 1 \rst_l_r_rst
- cell \rst_l$81 \rst_l
+ cell \rst_l$98 \rst_l
connect \rst \rst
connect \clk \clk
connect \s_rst \rst_l_s_rst
wire width 1 \rok_l_r_rdok
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
wire width 1 \rok_l_r_rdok$next
- cell \rok_l$82 \rok_l
+ cell \rok_l$99 \rok_l
connect \rst \rst
connect \clk \clk
connect \q_rdok \rok_l_q_rdok
wire width 1 \alui_l_r_alui$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
wire width 1 \alui_l_s_alui
- cell \alui_l$83 \alui_l
+ cell \alui_l$100 \alui_l
connect \rst \rst
connect \clk \clk
connect \q_alui \alui_l_q_alui
wire width 1 \alu_l_r_alu$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
wire width 1 \alu_l_s_alu
- cell \alu_l$84 \alu_l
+ cell \alu_l$101 \alu_l
connect \rst \rst
connect \clk \clk
connect \q_alu \alu_l_q_alu
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:178"
wire width 1 \all_rd
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179"
- wire width 1 $1
+ wire width 1 $2
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:179"
- cell $and $2
+ cell $and $3
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \busy_o
connect \B \rok_l_q_rdok
- connect \Y $1
+ connect \Y $2
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180"
- wire width 1 $3
+ wire width 1 $4
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180"
- wire width 4 $4
+ wire width 4 $5
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180"
- cell $not $5
+ cell $not $6
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 4
connect \A \rd__rel
- connect \Y $4
+ connect \Y $5
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180"
- wire width 4 $6
+ wire width 4 $7
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180"
- cell $or $7
+ cell $or $8
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 4
- connect \A $4
+ connect \A $5
connect \B \rd__go
- connect \Y $6
+ connect \Y $7
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180"
- cell $reduce_and $8
+ cell $reduce_and $9
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 1
- connect \A $6
- connect \Y $3
+ connect \A $7
+ connect \Y $4
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180"
- wire width 1 $9
+ wire width 1 $10
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:180"
- cell $and $10
+ cell $and $11
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $1
- connect \B $3
- connect \Y $9
+ connect \A $2
+ connect \B $4
+ connect \Y $10
end
process $group_0
assign \all_rd 1'0
- assign \all_rd $9
+ assign \all_rd $10
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:183"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:184"
wire width 1 \all_rd_pulse
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:186"
- wire width 1 $11
+ wire width 1 $12
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:186"
- cell $not $12
+ cell $not $13
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \all_rd_dly
- connect \Y $11
+ connect \Y $12
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:186"
- wire width 1 $13
+ wire width 1 $14
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:186"
- cell $and $14
+ cell $and $15
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \all_rd
- connect \B $11
- connect \Y $13
+ connect \B $12
+ connect \Y $14
end
process $group_2
assign \all_rd_pulse 1'0
- assign \all_rd_pulse $13
+ assign \all_rd_pulse $14
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:191"
wire width 1 \alu_pulse
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:195"
- wire width 1 $15
+ wire width 1 $16
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:195"
- cell $not $16
+ cell $not $17
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \alu_done_dly
- connect \Y $15
+ connect \Y $16
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:195"
- wire width 1 $17
+ wire width 1 $18
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:195"
- cell $and $18
+ cell $and $19
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \alu_done
- connect \B $15
- connect \Y $17
+ connect \B $16
+ connect \Y $18
end
process $group_5
assign \alu_pulse 1'0
- assign \alu_pulse $17
+ assign \alu_pulse $18
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:192"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:199"
wire width 3 \prev_wr_go$next
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:201"
- wire width 3 $19
+ wire width 3 $20
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:201"
- cell $and $20
+ cell $and $21
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \wr__go
connect \B { \busy_o \busy_o \busy_o }
- connect \Y $19
+ connect \Y $20
end
process $group_7
assign \prev_wr_go$next \prev_wr_go
- assign \prev_wr_go$next $19
+ assign \prev_wr_go$next $20
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100"
wire width 1 \done_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
- wire width 1 $21
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
wire width 1 $22
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
- wire width 3 $23
+ wire width 1 $23
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
+ wire width 3 $24
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:93"
wire width 3 \wrmask
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
- cell $not $24
+ cell $not $25
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 3
connect \A \wrmask
- connect \Y $23
+ connect \Y $24
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
- wire width 3 $25
+ wire width 3 $26
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
- cell $and $26
+ cell $and $27
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \B_WIDTH 3
parameter \Y_WIDTH 3
connect \A \wr__rel
- connect \B $23
- connect \Y $25
+ connect \B $24
+ connect \Y $26
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
- cell $reduce_bool $27
+ cell $reduce_bool $28
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 1
- connect \A $25
- connect \Y $22
+ connect \A $26
+ connect \Y $23
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
- cell $not $28
+ cell $not $29
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $22
- connect \Y $21
+ connect \A $23
+ connect \Y $22
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
- wire width 1 $29
+ wire width 1 $30
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
- cell $and $30
+ cell $and $31
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \busy_o
- connect \B $21
- connect \Y $29
+ connect \B $22
+ connect \Y $30
end
process $group_8
assign \done_o 1'0
- assign \done_o $29
+ assign \done_o $30
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206"
wire width 1 \wr_any
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210"
- wire width 1 $31
+ wire width 1 $32
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210"
- cell $reduce_bool $32
+ cell $reduce_bool $33
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 1
connect \A \wr__go
- connect \Y $31
+ connect \Y $32
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210"
- wire width 1 $33
+ wire width 1 $34
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210"
- cell $reduce_bool $34
+ cell $reduce_bool $35
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 1
connect \A \prev_wr_go
- connect \Y $33
+ connect \Y $34
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210"
- wire width 1 $35
+ wire width 1 $36
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:210"
- cell $or $36
+ cell $or $37
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $31
- connect \B $33
- connect \Y $35
+ connect \A $32
+ connect \B $34
+ connect \Y $36
end
process $group_9
assign \wr_any 1'0
- assign \wr_any $35
+ assign \wr_any $36
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:207"
wire width 1 \req_done
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211"
- wire width 1 $37
+ wire width 1 $38
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211"
- cell $not $38
+ cell $not $39
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \alu_shift_rot0_n_ready_i
- connect \Y $37
+ connect \Y $38
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211"
- wire width 1 $39
+ wire width 1 $40
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211"
- cell $and $40
+ cell $and $41
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \wr_any
- connect \B $37
- connect \Y $39
+ connect \B $38
+ connect \Y $40
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212"
- wire width 3 $41
+ wire width 3 $42
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212"
- cell $and $42
+ cell $and $43
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \req_l_q_req
connect \B \wrmask
- connect \Y $41
+ connect \Y $42
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212"
- wire width 1 $43
+ wire width 1 $44
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212"
- cell $eq $44
+ cell $eq $45
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $41
+ connect \A $42
connect \B 1'0
- connect \Y $43
+ connect \Y $44
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212"
- wire width 1 $45
+ wire width 1 $46
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212"
- cell $and $46
+ cell $and $47
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $39
- connect \B $43
- connect \Y $45
+ connect \A $40
+ connect \B $44
+ connect \Y $46
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
- wire width 1 $47
+ wire width 1 $48
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
- cell $eq $48
+ cell $eq $49
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wrmask
connect \B 1'0
- connect \Y $47
+ connect \Y $48
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
- wire width 1 $49
+ wire width 1 $50
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
- cell $and $50
+ cell $and $51
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $47
+ connect \A $48
connect \B \alu_shift_rot0_n_ready_i
- connect \Y $49
+ connect \Y $50
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
- wire width 1 $51
+ wire width 1 $52
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
- cell $and $52
+ cell $and $53
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $49
+ connect \A $50
connect \B \alu_shift_rot0_n_valid_o
- connect \Y $51
+ connect \Y $52
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
- wire width 1 $53
+ wire width 1 $54
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
- cell $and $54
+ cell $and $55
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $51
+ connect \A $52
connect \B \busy_o
- connect \Y $53
+ connect \Y $54
end
process $group_10
assign \req_done 1'0
- assign \req_done $45
+ assign \req_done $46
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
- switch { $53 }
+ switch { $54 }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
case 1'1
assign \req_done 1'1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:221"
wire width 1 \reset
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
- wire width 1 $55
+ wire width 1 $56
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
- cell $or $56
+ cell $or $57
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \req_done
connect \B \go_die_i
- connect \Y $55
+ connect \Y $56
end
process $group_11
assign \reset 1'0
- assign \reset $55
+ assign \reset $56
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222"
wire width 1 \rst_r
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226"
- wire width 1 $57
+ wire width 1 $58
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226"
- cell $or $58
+ cell $or $59
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \issue_i
connect \B \go_die_i
- connect \Y $57
+ connect \Y $58
end
process $group_12
assign \rst_r 1'0
- assign \rst_r $57
+ assign \rst_r $58
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:223"
wire width 3 \reset_w
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227"
- wire width 3 $59
+ wire width 3 $60
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227"
- cell $or $60
+ cell $or $61
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \wr__go
connect \B { \go_die_i \go_die_i \go_die_i }
- connect \Y $59
+ connect \Y $60
end
process $group_13
assign \reset_w 3'000
- assign \reset_w $59
+ assign \reset_w $60
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:224"
wire width 4 \reset_r
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:228"
- wire width 4 $61
+ wire width 4 $62
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:228"
- cell $or $62
+ cell $or $63
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \rd__go
connect \B { \go_die_i \go_die_i \go_die_i \go_die_i }
- connect \Y $61
+ connect \Y $62
end
process $group_14
assign \reset_r 4'0000
- assign \reset_r $61
+ assign \reset_r $62
sync init
end
process $group_15
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232"
- wire width 1 $63
+ wire width 1 $64
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232"
- cell $and $64
+ cell $and $65
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \alu_shift_rot0_n_valid_o
connect \B \busy_o
- connect \Y $63
+ connect \Y $64
end
process $group_16
assign \rok_l_r_rdok$next \rok_l_r_rdok
- assign \rok_l_r_rdok$next $63
+ assign \rok_l_r_rdok$next $64
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
update \src_l_r_src \src_l_r_src$next
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:247"
- wire width 3 $65
+ wire width 3 $66
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:247"
- cell $and $66
+ cell $and $67
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \alu_pulsem
connect \B \wrmask
- connect \Y $65
+ connect \Y $66
end
process $group_23
assign \req_l_s_req 3'000
- assign \req_l_s_req $65
+ assign \req_l_s_req $66
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:248"
- wire width 3 $67
+ wire width 3 $68
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:248"
- cell $or $68
+ cell $or $69
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 3
connect \A \reset_w
connect \B \prev_wr_go
- connect \Y $67
+ connect \Y $68
end
process $group_24
assign \req_l_r_req 3'111
- assign \req_l_r_req $67
+ assign \req_l_r_req $68
sync init
end
- attribute \enum_base_type "InternalOp"
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 7 \oper_r__insn_type
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00100000000 "MUL"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 11 \oper_r__fn_unit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 64 \oper_r__imm_data__imm
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \oper_r__imm_data__imm_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \oper_r__rc__rc
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \oper_r__rc__rc_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \oper_r__oe__oe
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \oper_r__oe__oe_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 3 \oper_r__write_cr__data
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 \oper_r__write_cr__ok
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 2 \oper_r__input_carry
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \oper_r__output_carry
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \oper_r__input_cr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \oper_r__output_cr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \oper_r__is_32bit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \oper_r__is_signed
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 32 \oper_r__insn
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
wire width 7 \oper_l__insn_type
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
wire width 1 \oper_l__oe__oe_ok$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
- wire width 3 \oper_l__write_cr__data
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
- wire width 3 \oper_l__write_cr__data$next
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
- wire width 1 \oper_l__write_cr__ok
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
- wire width 1 \oper_l__write_cr__ok$next
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
wire width 2 \oper_l__input_carry
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
wire width 2 \oper_l__input_carry$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
wire width 32 \oper_l__insn$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
- wire width 130 $69
+ wire width 126 $70
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
- cell $mux $70
- parameter \WIDTH 130
- connect \A { \oper_l__insn \oper_l__is_signed \oper_l__is_32bit \oper_l__output_cr \oper_l__input_cr \oper_l__output_carry \oper_l__input_carry { \oper_l__write_cr__ok \oper_l__write_cr__data } { \oper_l__oe__oe_ok \oper_l__oe__oe } { \oper_l__rc__rc_ok \oper_l__rc__rc } { \oper_l__imm_data__imm_ok \oper_l__imm_data__imm } \oper_l__fn_unit \oper_l__insn_type }
- connect \B { \oper_i__insn \oper_i__is_signed \oper_i__is_32bit \oper_i__output_cr \oper_i__input_cr \oper_i__output_carry \oper_i__input_carry { \oper_i__write_cr__ok \oper_i__write_cr__data } { \oper_i__oe__oe_ok \oper_i__oe__oe } { \oper_i__rc__rc_ok \oper_i__rc__rc } { \oper_i__imm_data__imm_ok \oper_i__imm_data__imm } \oper_i__fn_unit \oper_i__insn_type }
+ cell $mux $71
+ parameter \WIDTH 126
+ connect \A { \oper_l__insn \oper_l__is_signed \oper_l__is_32bit \oper_l__output_cr \oper_l__input_cr \oper_l__output_carry \oper_l__input_carry { } { \oper_l__oe__oe_ok \oper_l__oe__oe } { \oper_l__rc__rc_ok \oper_l__rc__rc } { \oper_l__imm_data__imm_ok \oper_l__imm_data__imm } \oper_l__fn_unit \oper_l__insn_type }
+ connect \B { \oper_i__insn \oper_i__is_signed \oper_i__is_32bit \oper_i__output_cr \oper_i__input_cr \oper_i__output_carry \oper_i__input_carry { } { \oper_i__oe__oe_ok \oper_i__oe__oe } { \oper_i__rc__rc_ok \oper_i__rc__rc } { \oper_i__imm_data__imm_ok \oper_i__imm_data__imm } \oper_i__fn_unit \oper_i__insn_type }
connect \S \issue_i
- connect \Y $69
+ connect \Y $70
end
process $group_25
assign \oper_r__insn_type 7'0000000
assign \oper_r__rc__rc_ok 1'0
assign \oper_r__oe__oe 1'0
assign \oper_r__oe__oe_ok 1'0
- assign \oper_r__write_cr__data 3'000
- assign \oper_r__write_cr__ok 1'0
+ assign { } 0'0
assign \oper_r__input_carry 2'00
assign \oper_r__output_carry 1'0
assign \oper_r__input_cr 1'0
assign \oper_r__is_32bit 1'0
assign \oper_r__is_signed 1'0
assign \oper_r__insn 32'00000000000000000000000000000000
- assign { \oper_r__insn \oper_r__is_signed \oper_r__is_32bit \oper_r__output_cr \oper_r__input_cr \oper_r__output_carry \oper_r__input_carry { \oper_r__write_cr__ok \oper_r__write_cr__data } { \oper_r__oe__oe_ok \oper_r__oe__oe } { \oper_r__rc__rc_ok \oper_r__rc__rc } { \oper_r__imm_data__imm_ok \oper_r__imm_data__imm } \oper_r__fn_unit \oper_r__insn_type } $69
+ assign { \oper_r__insn \oper_r__is_signed \oper_r__is_32bit \oper_r__output_cr \oper_r__input_cr \oper_r__output_carry \oper_r__input_carry { } { \oper_r__oe__oe_ok \oper_r__oe__oe } { \oper_r__rc__rc_ok \oper_r__rc__rc } { \oper_r__imm_data__imm_ok \oper_r__imm_data__imm } \oper_r__fn_unit \oper_r__insn_type } $70
sync init
end
- process $group_42
+ process $group_41
assign \oper_l__insn_type$next \oper_l__insn_type
assign \oper_l__fn_unit$next \oper_l__fn_unit
assign \oper_l__imm_data__imm$next \oper_l__imm_data__imm
assign \oper_l__rc__rc_ok$next \oper_l__rc__rc_ok
assign \oper_l__oe__oe$next \oper_l__oe__oe
assign \oper_l__oe__oe_ok$next \oper_l__oe__oe_ok
- assign \oper_l__write_cr__data$next \oper_l__write_cr__data
- assign \oper_l__write_cr__ok$next \oper_l__write_cr__ok
+ assign { } { }
assign \oper_l__input_carry$next \oper_l__input_carry
assign \oper_l__output_carry$next \oper_l__output_carry
assign \oper_l__input_cr$next \oper_l__input_cr
switch { \issue_i }
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
case 1'1
- assign { \oper_l__insn$next \oper_l__is_signed$next \oper_l__is_32bit$next \oper_l__output_cr$next \oper_l__input_cr$next \oper_l__output_carry$next \oper_l__input_carry$next { \oper_l__write_cr__ok$next \oper_l__write_cr__data$next } { \oper_l__oe__oe_ok$next \oper_l__oe__oe$next } { \oper_l__rc__rc_ok$next \oper_l__rc__rc$next } { \oper_l__imm_data__imm_ok$next \oper_l__imm_data__imm$next } \oper_l__fn_unit$next \oper_l__insn_type$next } { \oper_i__insn \oper_i__is_signed \oper_i__is_32bit \oper_i__output_cr \oper_i__input_cr \oper_i__output_carry \oper_i__input_carry { \oper_i__write_cr__ok \oper_i__write_cr__data } { \oper_i__oe__oe_ok \oper_i__oe__oe } { \oper_i__rc__rc_ok \oper_i__rc__rc } { \oper_i__imm_data__imm_ok \oper_i__imm_data__imm } \oper_i__fn_unit \oper_i__insn_type }
+ assign { \oper_l__insn$next \oper_l__is_signed$next \oper_l__is_32bit$next \oper_l__output_cr$next \oper_l__input_cr$next \oper_l__output_carry$next \oper_l__input_carry$next { } { \oper_l__oe__oe_ok$next \oper_l__oe__oe$next } { \oper_l__rc__rc_ok$next \oper_l__rc__rc$next } { \oper_l__imm_data__imm_ok$next \oper_l__imm_data__imm$next } \oper_l__fn_unit$next \oper_l__insn_type$next } { \oper_i__insn \oper_i__is_signed \oper_i__is_32bit \oper_i__output_cr \oper_i__input_cr \oper_i__output_carry \oper_i__input_carry { } { \oper_i__oe__oe_ok \oper_i__oe__oe } { \oper_i__rc__rc_ok \oper_i__rc__rc } { \oper_i__imm_data__imm_ok \oper_i__imm_data__imm } \oper_i__fn_unit \oper_i__insn_type }
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
assign \oper_l__rc__rc_ok$next 1'0
assign \oper_l__oe__oe$next 1'0
assign \oper_l__oe__oe_ok$next 1'0
- assign \oper_l__write_cr__data$next 3'000
- assign \oper_l__write_cr__ok$next 1'0
- assign \oper_l__insn$next 32'00000000000000000000000000000000
end
sync init
update \oper_l__insn_type 7'0000000
update \oper_l__rc__rc_ok 1'0
update \oper_l__oe__oe 1'0
update \oper_l__oe__oe_ok 1'0
- update \oper_l__write_cr__data 3'000
- update \oper_l__write_cr__ok 1'0
+ update { } 0'0
update \oper_l__input_carry 2'00
update \oper_l__output_carry 1'0
update \oper_l__input_cr 1'0
update \oper_l__rc__rc_ok \oper_l__rc__rc_ok$next
update \oper_l__oe__oe \oper_l__oe__oe$next
update \oper_l__oe__oe_ok \oper_l__oe__oe_ok$next
- update \oper_l__write_cr__data \oper_l__write_cr__data$next
- update \oper_l__write_cr__ok \oper_l__write_cr__ok$next
+ update { } { }
update \oper_l__input_carry \oper_l__input_carry$next
update \oper_l__output_carry \oper_l__output_carry$next
update \oper_l__input_cr \oper_l__input_cr$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
wire width 1 \data_r0_l__o_ok$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
- wire width 65 $71
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:730"
- wire width 1 $72
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:730"
- cell $reduce_bool $73
+ wire width 65 $72
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744"
+ wire width 1 $73
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744"
+ cell $reduce_bool $74
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 1
connect \A \alu_pulsem
- connect \Y $72
+ connect \Y $73
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
- cell $mux $74
+ cell $mux $75
parameter \WIDTH 65
connect \A { \data_r0_l__o_ok \data_r0_l__o }
- connect \B { \o_ok \o }
- connect \S $72
- connect \Y $71
+ connect \B { \o_ok \alu_shift_rot0_o }
+ connect \S $73
+ connect \Y $72
end
- process $group_59
+ process $group_57
assign \data_r0__o 64'0000000000000000000000000000000000000000000000000000000000000000
assign \data_r0__o_ok 1'0
- assign { \data_r0__o_ok \data_r0__o } $71
+ assign { \data_r0__o_ok \data_r0__o } $72
sync init
end
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
- wire width 1 $75
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
- cell $reduce_bool $76
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
+ wire width 1 $76
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
+ cell $reduce_bool $77
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 1
connect \A \alu_pulsem
- connect \Y $75
+ connect \Y $76
end
- process $group_61
+ process $group_59
assign \data_r0_l__o$next \data_r0_l__o
assign \data_r0_l__o_ok$next \data_r0_l__o_ok
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
- switch { $75 }
+ switch { $76 }
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
case 1'1
- assign { \data_r0_l__o_ok$next \data_r0_l__o$next } { \o_ok \o }
+ assign { \data_r0_l__o_ok$next \data_r0_l__o$next } { \o_ok \alu_shift_rot0_o }
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
wire width 1 \data_r1_l__cr_a_ok$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
- wire width 5 $77
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:730"
- wire width 1 $78
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:730"
- cell $reduce_bool $79
+ wire width 5 $78
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744"
+ wire width 1 $79
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744"
+ cell $reduce_bool $80
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 1
connect \A \alu_pulsem
- connect \Y $78
+ connect \Y $79
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
- cell $mux $80
+ cell $mux $81
parameter \WIDTH 5
connect \A { \data_r1_l__cr_a_ok \data_r1_l__cr_a }
- connect \B { \cr_a_ok \cr_a }
- connect \S $78
- connect \Y $77
+ connect \B { \cr_a_ok \alu_shift_rot0_cr_a }
+ connect \S $79
+ connect \Y $78
end
- process $group_63
+ process $group_61
assign \data_r1__cr_a 4'0000
assign \data_r1__cr_a_ok 1'0
- assign { \data_r1__cr_a_ok \data_r1__cr_a } $77
+ assign { \data_r1__cr_a_ok \data_r1__cr_a } $78
sync init
end
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
- wire width 1 $81
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
- cell $reduce_bool $82
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
+ wire width 1 $82
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
+ cell $reduce_bool $83
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 1
connect \A \alu_pulsem
- connect \Y $81
+ connect \Y $82
end
- process $group_65
+ process $group_63
assign \data_r1_l__cr_a$next \data_r1_l__cr_a
assign \data_r1_l__cr_a_ok$next \data_r1_l__cr_a_ok
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
- switch { $81 }
+ switch { $82 }
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
case 1'1
- assign { \data_r1_l__cr_a_ok$next \data_r1_l__cr_a$next } { \cr_a_ok \cr_a }
+ assign { \data_r1_l__cr_a_ok$next \data_r1_l__cr_a$next } { \cr_a_ok \alu_shift_rot0_cr_a }
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
wire width 1 \data_r2_l__xer_ca_ok$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
- wire width 3 $83
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:730"
- wire width 1 $84
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:730"
- cell $reduce_bool $85
+ wire width 3 $84
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744"
+ wire width 1 $85
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744"
+ cell $reduce_bool $86
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 1
connect \A \alu_pulsem
- connect \Y $84
+ connect \Y $85
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
- cell $mux $86
+ cell $mux $87
parameter \WIDTH 3
connect \A { \data_r2_l__xer_ca_ok \data_r2_l__xer_ca }
- connect \B { \xer_ca_ok \xer_ca }
- connect \S $84
- connect \Y $83
+ connect \B { \xer_ca_ok \alu_shift_rot0_xer_ca }
+ connect \S $85
+ connect \Y $84
end
- process $group_67
+ process $group_65
assign \data_r2__xer_ca 2'00
assign \data_r2__xer_ca_ok 1'0
- assign { \data_r2__xer_ca_ok \data_r2__xer_ca } $83
+ assign { \data_r2__xer_ca_ok \data_r2__xer_ca } $84
sync init
end
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
- wire width 1 $87
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
- cell $reduce_bool $88
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
+ wire width 1 $88
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
+ cell $reduce_bool $89
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 1
connect \A \alu_pulsem
- connect \Y $87
+ connect \Y $88
end
- process $group_69
+ process $group_67
assign \data_r2_l__xer_ca$next \data_r2_l__xer_ca
assign \data_r2_l__xer_ca_ok$next \data_r2_l__xer_ca_ok
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
- switch { $87 }
+ switch { $88 }
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
case 1'1
- assign { \data_r2_l__xer_ca_ok$next \data_r2_l__xer_ca$next } { \xer_ca_ok \xer_ca }
+ assign { \data_r2_l__xer_ca_ok$next \data_r2_l__xer_ca$next } { \xer_ca_ok \alu_shift_rot0_xer_ca }
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
update \data_r2_l__xer_ca \data_r2_l__xer_ca$next
update \data_r2_l__xer_ca_ok \data_r2_l__xer_ca_ok$next
end
- process $group_71
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+ wire width 1 $90
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+ cell $and $91
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \data_r0__o_ok
+ connect \B \busy_o
+ connect \Y $90
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+ wire width 1 $92
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+ cell $and $93
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \data_r1__cr_a_ok
+ connect \B \busy_o
+ connect \Y $92
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+ wire width 1 $94
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+ cell $and $95
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \data_r2__xer_ca_ok
+ connect \B \busy_o
+ connect \Y $94
+ end
+ process $group_69
assign \wrmask 3'000
- assign \wrmask { \data_r2__xer_ca_ok \data_r1__cr_a_ok \data_r0__o_ok }
+ assign \wrmask { $94 $92 $90 }
sync init
end
- process $group_72
+ process $group_70
assign \alu_shift_rot0_op__insn_type 7'0000000
assign \alu_shift_rot0_op__fn_unit 11'00000000000
assign \alu_shift_rot0_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
assign \alu_shift_rot0_op__rc__rc_ok 1'0
assign \alu_shift_rot0_op__oe__oe 1'0
assign \alu_shift_rot0_op__oe__oe_ok 1'0
- assign \alu_shift_rot0_op__write_cr__data 3'000
- assign \alu_shift_rot0_op__write_cr__ok 1'0
+ assign { } 0'0
assign \alu_shift_rot0_op__input_carry 2'00
assign \alu_shift_rot0_op__output_carry 1'0
assign \alu_shift_rot0_op__input_cr 1'0
assign \alu_shift_rot0_op__is_32bit 1'0
assign \alu_shift_rot0_op__is_signed 1'0
assign \alu_shift_rot0_op__insn 32'00000000000000000000000000000000
- assign { \alu_shift_rot0_op__insn \alu_shift_rot0_op__is_signed \alu_shift_rot0_op__is_32bit \alu_shift_rot0_op__output_cr \alu_shift_rot0_op__input_cr \alu_shift_rot0_op__output_carry \alu_shift_rot0_op__input_carry { \alu_shift_rot0_op__write_cr__ok \alu_shift_rot0_op__write_cr__data } { \alu_shift_rot0_op__oe__oe_ok \alu_shift_rot0_op__oe__oe } { \alu_shift_rot0_op__rc__rc_ok \alu_shift_rot0_op__rc__rc } { \alu_shift_rot0_op__imm_data__imm_ok \alu_shift_rot0_op__imm_data__imm } \alu_shift_rot0_op__fn_unit \alu_shift_rot0_op__insn_type } { \oper_r__insn \oper_r__is_signed \oper_r__is_32bit \oper_r__output_cr \oper_r__input_cr \oper_r__output_carry \oper_r__input_carry { \oper_r__write_cr__ok \oper_r__write_cr__data } { \oper_r__oe__oe_ok \oper_r__oe__oe } { \oper_r__rc__rc_ok \oper_r__rc__rc } { \oper_r__imm_data__imm_ok \oper_r__imm_data__imm } \oper_r__fn_unit \oper_r__insn_type }
+ assign { \alu_shift_rot0_op__insn \alu_shift_rot0_op__is_signed \alu_shift_rot0_op__is_32bit \alu_shift_rot0_op__output_cr \alu_shift_rot0_op__input_cr \alu_shift_rot0_op__output_carry \alu_shift_rot0_op__input_carry { } { \alu_shift_rot0_op__oe__oe_ok \alu_shift_rot0_op__oe__oe } { \alu_shift_rot0_op__rc__rc_ok \alu_shift_rot0_op__rc__rc } { \alu_shift_rot0_op__imm_data__imm_ok \alu_shift_rot0_op__imm_data__imm } \alu_shift_rot0_op__fn_unit \alu_shift_rot0_op__insn_type } { \oper_r__insn \oper_r__is_signed \oper_r__is_32bit \oper_r__output_cr \oper_r__input_cr \oper_r__output_carry \oper_r__input_carry { } { \oper_r__oe__oe_ok \oper_r__oe__oe } { \oper_r__rc__rc_ok \oper_r__rc__rc } { \oper_r__imm_data__imm_ok \oper_r__imm_data__imm } \oper_r__fn_unit \oper_r__insn_type }
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:158"
wire width 1 \src_sel
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:159"
- wire width 1 $89
+ wire width 1 $96
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:159"
- cell $mux $90
+ cell $mux $97
parameter \WIDTH 1
connect \A \src_l_q_src [1]
connect \B \opc_l_q_opc
connect \S \oper_r__imm_data__imm_ok
- connect \Y $89
+ connect \Y $96
end
- process $group_89
+ process $group_86
assign \src_sel 1'0
- assign \src_sel $89
+ assign \src_sel $96
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:157"
wire width 64 \src_or_imm
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:160"
- wire width 64 $91
+ wire width 64 $98
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:160"
- cell $mux $92
+ cell $mux $99
parameter \WIDTH 64
connect \A \src2_i
connect \B \oper_r__imm_data__imm
connect \S \oper_r__imm_data__imm_ok
- connect \Y $91
+ connect \Y $98
end
- process $group_90
+ process $group_87
assign \src_or_imm 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \src_or_imm $91
+ assign \src_or_imm $98
sync init
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
wire width 64 \src_r0$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
- wire width 64 $93
+ wire width 64 $100
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
- cell $mux $94
+ cell $mux $101
parameter \WIDTH 64
connect \A \src_r0
connect \B \src1_i
connect \S \src_l_q_src [0]
- connect \Y $93
+ connect \Y $100
end
- process $group_91
+ process $group_88
assign \alu_shift_rot0_ra 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \alu_shift_rot0_ra $93
+ assign \alu_shift_rot0_ra $100
sync init
end
- process $group_92
+ process $group_89
assign \src_r0$next \src_r0
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
switch { \src_l_q_src [0] }
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
wire width 64 \src_r1$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
- wire width 64 $95
+ wire width 64 $102
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
- cell $mux $96
+ cell $mux $103
parameter \WIDTH 64
connect \A \src_r1
connect \B \src_or_imm
connect \S \src_sel
- connect \Y $95
+ connect \Y $102
end
- process $group_93
+ process $group_90
assign \alu_shift_rot0_rb 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \alu_shift_rot0_rb $95
+ assign \alu_shift_rot0_rb $102
sync init
end
- process $group_94
+ process $group_91
assign \src_r1$next \src_r1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
switch { \src_sel }
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
wire width 64 \src_r2$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
- wire width 64 $97
+ wire width 64 $104
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
- cell $mux $98
+ cell $mux $105
parameter \WIDTH 64
connect \A \src_r2
connect \B \src3_i
connect \S \src_l_q_src [2]
- connect \Y $97
+ connect \Y $104
end
- process $group_95
+ process $group_92
assign \alu_shift_rot0_rc 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \alu_shift_rot0_rc $97
+ assign \alu_shift_rot0_rc $104
sync init
end
- process $group_96
+ process $group_93
assign \src_r2$next \src_r2
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
switch { \src_l_q_src [2] }
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
wire width 2 \src_r3$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
- wire width 2 $99
+ wire width 2 $106
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
- cell $mux $100
+ cell $mux $107
parameter \WIDTH 2
connect \A \src_r3
connect \B \src4_i
connect \S \src_l_q_src [3]
- connect \Y $99
+ connect \Y $106
end
- process $group_97
- assign \alu_shift_rot0_xer_ca 2'00
- assign \alu_shift_rot0_xer_ca $99
+ process $group_94
+ assign \alu_shift_rot0_xer_ca$1 2'00
+ assign \alu_shift_rot0_xer_ca$1 $106
sync init
end
- process $group_98
+ process $group_95
assign \src_r3$next \src_r3
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
switch { \src_l_q_src [3] }
sync posedge \clk
update \src_r3 \src_r3$next
end
- process $group_99
+ process $group_96
assign \alu_shift_rot0_p_valid_i 1'0
assign \alu_shift_rot0_p_valid_i \alui_l_q_alui
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:321"
- wire width 1 $101
+ wire width 1 $108
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:321"
- cell $and $102
+ cell $and $109
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \alu_shift_rot0_p_ready_o
connect \B \alui_l_q_alui
- connect \Y $101
+ connect \Y $108
end
- process $group_100
+ process $group_97
assign \alui_l_r_alui$next \alui_l_r_alui
- assign \alui_l_r_alui$next $101
+ assign \alui_l_r_alui$next $108
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
sync posedge \clk
update \alui_l_r_alui \alui_l_r_alui$next
end
- process $group_101
+ process $group_98
assign \alui_l_s_alui 1'0
assign \alui_l_s_alui \all_rd_pulse
sync init
end
- process $group_102
+ process $group_99
assign \alu_shift_rot0_n_ready_i 1'0
assign \alu_shift_rot0_n_ready_i \alu_l_q_alu
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:328"
- wire width 1 $103
+ wire width 1 $110
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:328"
- cell $and $104
+ cell $and $111
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \alu_shift_rot0_n_valid_o
connect \B \alu_l_q_alu
- connect \Y $103
+ connect \Y $110
end
- process $group_103
+ process $group_100
assign \alu_l_r_alu$next \alu_l_r_alu
- assign \alu_l_r_alu$next $103
+ assign \alu_l_r_alu$next $110
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
sync posedge \clk
update \alu_l_r_alu \alu_l_r_alu$next
end
- process $group_104
+ process $group_101
assign \alu_l_s_alu 1'0
assign \alu_l_s_alu \all_rd_pulse
sync init
end
- process $group_105
+ process $group_102
assign \busy_o 1'0
assign \busy_o \opc_l_q_opc
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341"
- wire width 4 $105
+ wire width 4 $112
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341"
- cell $and $106
+ cell $and $113
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A \src_l_q_src
connect \B { \busy_o \busy_o \busy_o \busy_o }
- connect \Y $105
+ connect \Y $112
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:164"
- wire width 1 $107
+ wire width 1 $114
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:164"
- cell $not $108
+ cell $not $115
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \oper_r__imm_data__imm_ok
- connect \Y $107
+ connect \Y $114
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341"
- wire width 4 $109
+ wire width 4 $116
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341"
- cell $and $110
+ cell $and $117
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 4
- connect \A $105
- connect \B { 1'1 1'1 $107 1'1 }
- connect \Y $109
+ connect \A $112
+ connect \B { 1'1 1'1 $114 1'1 }
+ connect \Y $116
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341"
- wire width 4 $111
+ wire width 4 $118
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341"
- cell $not $112
+ cell $not $119
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 4
connect \A \rdmaskn
- connect \Y $111
+ connect \Y $118
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341"
- wire width 4 $113
+ wire width 4 $120
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:341"
- cell $and $114
+ cell $and $121
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 4
- connect \A $109
- connect \B $111
- connect \Y $113
+ connect \A $116
+ connect \B $118
+ connect \Y $120
end
- process $group_106
+ process $group_103
assign \rd__rel 4'0000
- assign \rd__rel $113
+ assign \rd__rel $120
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
- wire width 1 $115
+ wire width 1 $122
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
- cell $and $116
+ cell $and $123
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \busy_o
connect \B \shadown_i
- connect \Y $115
+ connect \Y $122
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
- wire width 1 $117
+ wire width 1 $124
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
- cell $and $118
+ cell $and $125
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \busy_o
connect \B \shadown_i
- connect \Y $117
+ connect \Y $124
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
- wire width 1 $119
+ wire width 1 $126
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:344"
- cell $and $120
+ cell $and $127
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \busy_o
connect \B \shadown_i
- connect \Y $119
+ connect \Y $126
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:345"
- wire width 3 $121
+ wire width 3 $128
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:345"
- cell $and $122
+ cell $and $129
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \B_WIDTH 3
parameter \Y_WIDTH 3
connect \A \req_l_q_req
- connect \B { $115 $117 $119 }
- connect \Y $121
+ connect \B { $122 $124 $126 }
+ connect \Y $128
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:345"
- wire width 3 $123
+ wire width 3 $130
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:345"
- cell $and $124
+ cell $and $131
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \B_WIDTH 3
parameter \Y_WIDTH 3
- connect \A $121
+ connect \A $128
connect \B \wrmask
- connect \Y $123
+ connect \Y $130
end
- process $group_107
+ process $group_104
assign \wr__rel 3'000
- assign \wr__rel $123
+ assign \wr__rel $130
sync init
end
- process $group_108
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+ wire width 1 $132
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+ cell $and $133
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \wr__go [0]
+ connect \B \busy_o
+ connect \Y $132
+ end
+ process $group_105
assign \dest1_o 64'0000000000000000000000000000000000000000000000000000000000000000
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
- switch { \wr__go [0] }
+ switch { $132 }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
case 1'1
assign \dest1_o { \data_r0__o_ok \data_r0__o } [63:0]
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
- wire width 4 \dest2_o
- process $group_109
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+ wire width 1 $134
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+ cell $and $135
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \wr__go [1]
+ connect \B \busy_o
+ connect \Y $134
+ end
+ process $group_106
assign \dest2_o 4'0000
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
- switch { \wr__go [1] }
+ switch { $134 }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
case 1'1
assign \dest2_o { \data_r1__cr_a_ok \data_r1__cr_a } [3:0]
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
- wire width 2 \dest3_o
- process $group_110
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+ wire width 1 $136
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+ cell $and $137
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \wr__go [2]
+ connect \B \busy_o
+ connect \Y $136
+ end
+ process $group_107
assign \dest3_o 2'00
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
- switch { \wr__go [2] }
+ switch { $136 }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
case 1'1
assign \dest3_o { \data_r2__xer_ca_ok \data_r2__xer_ca } [1:0]
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.opc_l"
-module \opc_l$85
+module \opc_l$102
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.src_l"
-module \src_l$86
+module \src_l$103
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.alu_l"
-module \alu_l$87
+module \alu_l$104
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.rst_l"
-module \rst_l$88
+module \rst_l$105
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 4 \rst
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 5 \clk
- attribute \enum_base_type "InternalOp"
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 7 input 6 \oper_i__insn_type
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 64 input 7 \oper_i__imm_data__imm
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 input 8 \oper_i__imm_data__imm_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 input 9 \oper_i__zero_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
- wire width 1 input 10 \oper_i__is_32bit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
- wire width 1 input 11 \oper_i__is_signed
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
- wire width 4 input 12 \oper_i__data_len
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
- wire width 1 input 13 \oper_i__byte_reverse
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
- wire width 1 input 14 \oper_i__sign_extend
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
- wire width 1 input 15 \oper_i__update
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 10 \oper_i__rc__rc
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 11 \oper_i__rc__rc_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 12 \oper_i__oe__oe
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 13 \oper_i__oe__oe_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 14 \oper_i__is_32bit
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 15 \oper_i__is_signed
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 4 input 16 \oper_i__data_len
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 17 \oper_i__byte_reverse
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 18 \oper_i__sign_extend
+ attribute \enum_base_type "LDSTMode"
+ attribute \enum_value_00 "NONE"
+ attribute \enum_value_01 "update"
+ attribute \enum_value_10 "cix"
+ attribute \enum_value_11 "cx"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 2 input 19 \oper_i__ldst_mode
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94"
- wire width 1 input 16 \issue_i
+ wire width 1 input 20 \issue_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
- wire width 1 output 17 \busy_o
+ wire width 1 output 21 \busy_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:92"
- wire width 3 input 18 \rdmaskn
+ wire width 3 input 22 \rdmaskn
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 3 output 19 \rd__rel
+ wire width 3 output 23 \rd__rel
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 3 input 20 \rd__go
+ wire width 3 input 24 \rd__go
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
- wire width 64 input 21 \src1_i
+ wire width 64 input 25 \src1_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
- wire width 64 input 22 \src2_i
+ wire width 64 input 26 \src2_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
- wire width 64 input 23 \src3_i
+ wire width 64 input 27 \src3_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 2 output 24 \wr__rel
+ wire width 2 output 28 \wr__rel
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 2 input 25 \wr__go
+ wire width 2 input 29 \wr__go
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 output 26 \o
+ wire width 64 output 30 \o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 output 27 \ea
+ wire width 64 output 31 \ea
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96"
- wire width 1 input 28 \go_die_i
+ wire width 1 input 32 \go_die_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:112"
- wire width 1 output 29 \load_mem_o
+ wire width 1 output 33 \load_mem_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:113"
- wire width 1 output 30 \stwd_mem_o
+ wire width 1 output 34 \stwd_mem_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
- wire width 1 input 31 \shadown_i
+ wire width 1 input 35 \shadown_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:95"
- wire width 1 output 32 \ldst_port0_is_ld_i
+ wire width 1 output 36 \ldst_port0_is_ld_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:96"
- wire width 1 output 33 \ldst_port0_is_st_i
+ wire width 1 output 37 \ldst_port0_is_st_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99"
- wire width 4 output 34 \ldst_port0_data_len
+ wire width 4 output 38 \ldst_port0_data_len
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 96 output 35 \ldst_port0_addr_i
+ wire width 96 output 39 \ldst_port0_addr_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 36 \ldst_port0_addr_i_ok
+ wire width 1 output 40 \ldst_port0_addr_i_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:107"
- wire width 1 input 37 \ldst_port0_addr_exc_o
+ wire width 1 input 41 \ldst_port0_addr_exc_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:106"
- wire width 1 input 38 \ldst_port0_addr_ok_o
+ wire width 1 input 42 \ldst_port0_addr_ok_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 input 39 \ldst_port0_ld_data_o
+ wire width 64 input 43 \ldst_port0_ld_data_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 input 40 \ldst_port0_ld_data_o_ok
+ wire width 1 input 44 \ldst_port0_ld_data_o_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 output 41 \ldst_port0_st_data_i
+ wire width 64 output 45 \ldst_port0_st_data_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 42 \ldst_port0_st_data_i_ok
+ wire width 1 output 46 \ldst_port0_st_data_i_ok
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
wire width 1 \opc_l_s_opc
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
wire width 1 \opc_l_r_opc$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
wire width 1 \opc_l_q_opc
- cell \opc_l$85 \opc_l
+ cell \opc_l$102 \opc_l
connect \rst \rst
connect \clk \clk
connect \s_opc \opc_l_s_opc
wire width 3 \src_l_r_src$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
wire width 3 \src_l_q_src
- cell \src_l$86 \src_l
+ cell \src_l$103 \src_l
connect \rst \rst
connect \clk \clk
connect \s_src \src_l_s_src
wire width 1 \alu_l_r_alu
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
wire width 1 \alu_l_q_alu
- cell \alu_l$87 \alu_l
+ cell \alu_l$104 \alu_l
connect \rst \rst
connect \clk \clk
connect \s_alu \alu_l_s_alu
wire width 1 \rst_l_r_rst
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
wire width 1 \rst_l_q_rst
- cell \rst_l$88 \rst_l
+ cell \rst_l$105 \rst_l
connect \rst \rst
connect \clk \clk
connect \s_rst \rst_l_s_rst
assign \rst_l_r_rst \issue_i
sync init
end
- attribute \enum_base_type "InternalOp"
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 7 \oper_r__insn_type
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 64 \oper_r__imm_data__imm
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \oper_r__imm_data__imm_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \oper_r__zero_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \oper_r__rc__rc
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \oper_r__rc__rc_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \oper_r__oe__oe
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 \oper_r__oe__oe_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \oper_r__is_32bit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \oper_r__is_signed
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 4 \oper_r__data_len
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \oper_r__byte_reverse
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 \oper_r__sign_extend
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
- wire width 1 \oper_r__update
+ attribute \enum_base_type "LDSTMode"
+ attribute \enum_value_00 "NONE"
+ attribute \enum_value_01 "update"
+ attribute \enum_value_10 "cix"
+ attribute \enum_value_11 "cx"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 2 \oper_r__ldst_mode
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
wire width 7 \oper_l__insn_type
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
wire width 1 \oper_l__zero_a$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+ wire width 1 \oper_l__rc__rc
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+ wire width 1 \oper_l__rc__rc$next
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+ wire width 1 \oper_l__rc__rc_ok
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+ wire width 1 \oper_l__rc__rc_ok$next
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+ wire width 1 \oper_l__oe__oe
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+ wire width 1 \oper_l__oe__oe$next
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+ wire width 1 \oper_l__oe__oe_ok
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+ wire width 1 \oper_l__oe__oe_ok$next
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
wire width 1 \oper_l__is_32bit
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
wire width 1 \oper_l__is_32bit$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
wire width 1 \oper_l__sign_extend$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
- wire width 1 \oper_l__update
+ wire width 2 \oper_l__ldst_mode
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
- wire width 1 \oper_l__update$next
+ wire width 2 \oper_l__ldst_mode$next
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
- wire width 82 $30
+ wire width 87 $30
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
cell $mux $31
- parameter \WIDTH 82
- connect \A { \oper_l__update \oper_l__sign_extend \oper_l__byte_reverse \oper_l__data_len \oper_l__is_signed \oper_l__is_32bit \oper_l__zero_a { \oper_l__imm_data__imm_ok \oper_l__imm_data__imm } \oper_l__insn_type }
- connect \B { \oper_i__update \oper_i__sign_extend \oper_i__byte_reverse \oper_i__data_len \oper_i__is_signed \oper_i__is_32bit \oper_i__zero_a { \oper_i__imm_data__imm_ok \oper_i__imm_data__imm } \oper_i__insn_type }
+ parameter \WIDTH 87
+ connect \A { \oper_l__ldst_mode \oper_l__sign_extend \oper_l__byte_reverse \oper_l__data_len \oper_l__is_signed \oper_l__is_32bit { \oper_l__oe__oe_ok \oper_l__oe__oe } { \oper_l__rc__rc_ok \oper_l__rc__rc } \oper_l__zero_a { \oper_l__imm_data__imm_ok \oper_l__imm_data__imm } \oper_l__insn_type }
+ connect \B { \oper_i__ldst_mode \oper_i__sign_extend \oper_i__byte_reverse \oper_i__data_len \oper_i__is_signed \oper_i__is_32bit { \oper_i__oe__oe_ok \oper_i__oe__oe } { \oper_i__rc__rc_ok \oper_i__rc__rc } \oper_i__zero_a { \oper_i__imm_data__imm_ok \oper_i__imm_data__imm } \oper_i__insn_type }
connect \S \issue_i
connect \Y $30
end
assign \oper_r__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
assign \oper_r__imm_data__imm_ok 1'0
assign \oper_r__zero_a 1'0
+ assign \oper_r__rc__rc 1'0
+ assign \oper_r__rc__rc_ok 1'0
+ assign \oper_r__oe__oe 1'0
+ assign \oper_r__oe__oe_ok 1'0
assign \oper_r__is_32bit 1'0
assign \oper_r__is_signed 1'0
assign \oper_r__data_len 4'0000
assign \oper_r__byte_reverse 1'0
assign \oper_r__sign_extend 1'0
- assign \oper_r__update 1'0
- assign { \oper_r__update \oper_r__sign_extend \oper_r__byte_reverse \oper_r__data_len \oper_r__is_signed \oper_r__is_32bit \oper_r__zero_a { \oper_r__imm_data__imm_ok \oper_r__imm_data__imm } \oper_r__insn_type } $30
+ assign \oper_r__ldst_mode 2'00
+ assign { \oper_r__ldst_mode \oper_r__sign_extend \oper_r__byte_reverse \oper_r__data_len \oper_r__is_signed \oper_r__is_32bit { \oper_r__oe__oe_ok \oper_r__oe__oe } { \oper_r__rc__rc_ok \oper_r__rc__rc } \oper_r__zero_a { \oper_r__imm_data__imm_ok \oper_r__imm_data__imm } \oper_r__insn_type } $30
sync init
end
- process $group_36
+ process $group_40
assign \oper_l__insn_type$next \oper_l__insn_type
assign \oper_l__imm_data__imm$next \oper_l__imm_data__imm
assign \oper_l__imm_data__imm_ok$next \oper_l__imm_data__imm_ok
assign \oper_l__zero_a$next \oper_l__zero_a
+ assign \oper_l__rc__rc$next \oper_l__rc__rc
+ assign \oper_l__rc__rc_ok$next \oper_l__rc__rc_ok
+ assign \oper_l__oe__oe$next \oper_l__oe__oe
+ assign \oper_l__oe__oe_ok$next \oper_l__oe__oe_ok
assign \oper_l__is_32bit$next \oper_l__is_32bit
assign \oper_l__is_signed$next \oper_l__is_signed
assign \oper_l__data_len$next \oper_l__data_len
assign \oper_l__byte_reverse$next \oper_l__byte_reverse
assign \oper_l__sign_extend$next \oper_l__sign_extend
- assign \oper_l__update$next \oper_l__update
+ assign \oper_l__ldst_mode$next \oper_l__ldst_mode
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
switch { \issue_i }
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
case 1'1
- assign { \oper_l__update$next \oper_l__sign_extend$next \oper_l__byte_reverse$next \oper_l__data_len$next \oper_l__is_signed$next \oper_l__is_32bit$next \oper_l__zero_a$next { \oper_l__imm_data__imm_ok$next \oper_l__imm_data__imm$next } \oper_l__insn_type$next } { \oper_i__update \oper_i__sign_extend \oper_i__byte_reverse \oper_i__data_len \oper_i__is_signed \oper_i__is_32bit \oper_i__zero_a { \oper_i__imm_data__imm_ok \oper_i__imm_data__imm } \oper_i__insn_type }
+ assign { \oper_l__ldst_mode$next \oper_l__sign_extend$next \oper_l__byte_reverse$next \oper_l__data_len$next \oper_l__is_signed$next \oper_l__is_32bit$next { \oper_l__oe__oe_ok$next \oper_l__oe__oe$next } { \oper_l__rc__rc_ok$next \oper_l__rc__rc$next } \oper_l__zero_a$next { \oper_l__imm_data__imm_ok$next \oper_l__imm_data__imm$next } \oper_l__insn_type$next } { \oper_i__ldst_mode \oper_i__sign_extend \oper_i__byte_reverse \oper_i__data_len \oper_i__is_signed \oper_i__is_32bit { \oper_i__oe__oe_ok \oper_i__oe__oe } { \oper_i__rc__rc_ok \oper_i__rc__rc } \oper_i__zero_a { \oper_i__imm_data__imm_ok \oper_i__imm_data__imm } \oper_i__insn_type }
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
assign \oper_l__imm_data__imm$next 64'0000000000000000000000000000000000000000000000000000000000000000
assign \oper_l__imm_data__imm_ok$next 1'0
+ assign \oper_l__rc__rc$next 1'0
+ assign \oper_l__rc__rc_ok$next 1'0
+ assign \oper_l__oe__oe$next 1'0
+ assign \oper_l__oe__oe_ok$next 1'0
end
sync init
update \oper_l__insn_type 7'0000000
update \oper_l__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
update \oper_l__imm_data__imm_ok 1'0
update \oper_l__zero_a 1'0
+ update \oper_l__rc__rc 1'0
+ update \oper_l__rc__rc_ok 1'0
+ update \oper_l__oe__oe 1'0
+ update \oper_l__oe__oe_ok 1'0
update \oper_l__is_32bit 1'0
update \oper_l__is_signed 1'0
update \oper_l__data_len 4'0000
update \oper_l__byte_reverse 1'0
update \oper_l__sign_extend 1'0
- update \oper_l__update 1'0
+ update \oper_l__ldst_mode 2'00
sync posedge \clk
update \oper_l__insn_type \oper_l__insn_type$next
update \oper_l__imm_data__imm \oper_l__imm_data__imm$next
update \oper_l__imm_data__imm_ok \oper_l__imm_data__imm_ok$next
update \oper_l__zero_a \oper_l__zero_a$next
+ update \oper_l__rc__rc \oper_l__rc__rc$next
+ update \oper_l__rc__rc_ok \oper_l__rc__rc_ok$next
+ update \oper_l__oe__oe \oper_l__oe__oe$next
+ update \oper_l__oe__oe_ok \oper_l__oe__oe_ok$next
update \oper_l__is_32bit \oper_l__is_32bit$next
update \oper_l__is_signed \oper_l__is_signed$next
update \oper_l__data_len \oper_l__data_len$next
update \oper_l__byte_reverse \oper_l__byte_reverse$next
update \oper_l__sign_extend \oper_l__sign_extend$next
- update \oper_l__update \oper_l__update$next
+ update \oper_l__ldst_mode \oper_l__ldst_mode$next
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:361"
wire width 64 \ldd_r
connect \S \ld_ok
connect \Y $32
end
- process $group_46
+ process $group_54
assign \ldd_r 64'0000000000000000000000000000000000000000000000000000000000000000
assign \ldd_r $32
sync init
end
- process $group_47
+ process $group_55
assign \ldo_r$next \ldo_r
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
switch { \ld_ok }
connect \S \src_l_q_src [0]
connect \Y $34
end
- process $group_48
+ process $group_56
assign \src_r0 64'0000000000000000000000000000000000000000000000000000000000000000
assign \src_r0 $34
sync init
end
- process $group_49
+ process $group_57
assign \src_r0_l$next \src_r0_l
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
switch { \src_l_q_src [0] }
connect \S \src_l_q_src [1]
connect \Y $36
end
- process $group_50
+ process $group_58
assign \src_r1 64'0000000000000000000000000000000000000000000000000000000000000000
assign \src_r1 $36
sync init
end
- process $group_51
+ process $group_59
assign \src_r1_l$next \src_r1_l
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
switch { \src_l_q_src [1] }
connect \S \src_l_q_src [2]
connect \Y $38
end
- process $group_52
+ process $group_60
assign \src_r2 64'0000000000000000000000000000000000000000000000000000000000000000
assign \src_r2 $38
sync init
end
- process $group_53
+ process $group_61
assign \src_r2_l$next \src_r2_l
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
switch { \src_l_q_src [2] }
connect \S \alu_l_q_alu
connect \Y $40
end
- process $group_54
+ process $group_62
assign \addr_r 64'0000000000000000000000000000000000000000000000000000000000000000
assign \addr_r $40
sync init
end
- process $group_55
+ process $group_63
assign \ea_r$next \ea_r
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
switch { \alu_l_q_alu }
connect \S \oper_r__zero_a
connect \Y $42
end
- process $group_56
+ process $group_64
assign \src1_or_z 64'0000000000000000000000000000000000000000000000000000000000000000
assign \src1_or_z $42
sync init
connect \S \oper_r__imm_data__imm_ok
connect \Y $44
end
- process $group_57
+ process $group_65
assign \src2_or_imm 64'0000000000000000000000000000000000000000000000000000000000000000
assign \src2_or_imm $44
sync init
connect \Y $47
end
connect $46 $47
- process $group_58
+ process $group_66
assign \alu_o$next \alu_o
assign \alu_o$next $46 [63:0]
sync init
sync posedge \clk
update \alu_o \alu_o$next
end
- process $group_59
+ process $group_67
assign \alu_ok$next \alu_ok
assign \alu_ok$next \alu_valid
sync init
connect \B 7'0100110
connect \Y $49
end
- process $group_60
+ process $group_68
assign \op_is_st 1'0
assign \op_is_st $49
sync init
connect \B 7'0100101
connect \Y $51
end
- process $group_61
+ process $group_69
assign \op_is_ld 1'0
assign \op_is_ld $51
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:394"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:395"
wire width 1 $53
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:394"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:395"
cell $and $54
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \ad__go
connect \Y $53
end
- process $group_62
+ process $group_70
assign \load_mem_o 1'0
assign \load_mem_o $53
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:395"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:396"
wire width 1 $55
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:395"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:396"
cell $and $56
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \st__go
connect \Y $55
end
- process $group_63
+ process $group_71
assign \stwd_mem_o 1'0
assign \stwd_mem_o $55
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:108"
wire width 1 \ld_o
- process $group_64
+ process $group_72
assign \ld_o 1'0
assign \ld_o \op_is_ld
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:109"
wire width 1 \st_o
- process $group_65
+ process $group_73
assign \st_o 1'0
assign \st_o \op_is_st
sync init
end
- process $group_66
+ process $group_74
assign \busy_o 1'0
assign \busy_o \opc_l_q_opc
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:410"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:411"
wire width 3 $57
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:410"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:411"
cell $and $58
parameter \A_SIGNED 0
parameter \A_WIDTH 3
connect \B { \busy_o \busy_o \busy_o }
connect \Y $57
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:410"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:411"
wire width 2 $59
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:410"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:411"
cell $not $60
parameter \A_SIGNED 0
parameter \A_WIDTH 2
connect \A { \oper_r__imm_data__imm_ok \oper_r__zero_a }
connect \Y $59
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:410"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:411"
wire width 3 $61
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:410"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:411"
cell $and $62
parameter \A_SIGNED 0
parameter \A_WIDTH 3
connect \B $59
connect \Y $61
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:410"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:411"
wire width 3 $63
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:410"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:411"
cell $not $64
parameter \A_SIGNED 0
parameter \A_WIDTH 3
connect \A \rdmaskn
connect \Y $63
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:410"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:411"
wire width 3 $65
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:410"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:411"
cell $and $66
parameter \A_SIGNED 0
parameter \A_WIDTH 3
connect \B $63
connect \Y $65
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:419"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:420"
wire width 1 $67
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:419"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:420"
cell $and $68
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \busy_o
connect \Y $67
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:419"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:420"
wire width 1 $69
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:419"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:420"
cell $and $70
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \op_is_st
connect \Y $69
end
- process $group_67
+ process $group_75
assign \rd__rel 3'000
assign \rd__rel $65
assign \rd__rel [2] $69
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:413"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:414"
wire width 1 $71
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:413"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:414"
cell $or $72
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \rd__go [1]
connect \Y $71
end
- process $group_68
+ process $group_76
assign \rda_any 1'0
assign \rda_any $71
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:416"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:417"
wire width 1 $73
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:416"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:417"
wire width 1 $74
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:416"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:417"
cell $or $75
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \rd__rel [1]
connect \Y $74
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:416"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:417"
cell $not $76
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A $74
connect \Y $73
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:416"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:417"
wire width 1 $77
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:416"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:417"
cell $and $78
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B $73
connect \Y $77
end
- process $group_69
+ process $group_77
assign \alu_valid 1'0
assign \alu_valid $77
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:273"
wire width 1 \rd_done
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:422"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:423"
wire width 1 $79
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:422"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:423"
cell $not $80
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \A \rd__rel [2]
connect \Y $79
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:422"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:423"
wire width 1 $81
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:422"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:423"
cell $and $82
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B $79
connect \Y $81
end
- process $group_70
+ process $group_78
assign \rd_done 1'0
assign \rd_done $81
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:425"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:426"
wire width 1 $83
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:425"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:426"
cell $and $84
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \adr_l_q_adr
connect \Y $83
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:425"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:426"
wire width 1 $85
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:425"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:426"
cell $and $86
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \busy_o
connect \Y $85
end
- process $group_71
+ process $group_79
assign \ad__rel 1'0
assign \ad__rel $85
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:429"
wire width 1 $87
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:429"
cell $and $88
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \busy_o
connect \Y $87
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:429"
wire width 1 $89
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:429"
cell $and $90
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \rd_done
connect \Y $89
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:429"
wire width 1 $91
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:429"
cell $and $92
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \op_is_st
connect \Y $91
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:429"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:430"
wire width 1 $93
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:429"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:430"
cell $and $94
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \shadown_i
connect \Y $93
end
- process $group_72
+ process $group_80
assign \st__rel 1'0
assign \st__rel $93
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:433"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434"
wire width 1 $95
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:433"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434"
cell $and $96
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \wri_l_q_wri
connect \Y $95
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:433"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434"
wire width 1 $97
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:433"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434"
cell $and $98
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \busy_o
connect \Y $97
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:433"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434"
wire width 1 $99
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:433"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434"
cell $and $100
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \lod_l_qn_lod
connect \Y $99
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:433"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434"
wire width 1 $101
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:433"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434"
cell $and $102
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \op_is_ld
connect \Y $101
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:433"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434"
wire width 1 $103
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:433"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434"
cell $and $104
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \shadown_i
connect \Y $103
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:436"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:437"
wire width 1 $105
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:436"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:437"
cell $and $106
parameter \A_SIGNED 0
parameter \A_WIDTH 1
connect \B \busy_o
connect \Y $105
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:436"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:393"
wire width 1 $107
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:436"
- cell $and $108
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:393"
+ cell $eq $108
parameter \A_SIGNED 0
- parameter \A_WIDTH 1
+ parameter \A_WIDTH 2
parameter \B_SIGNED 0
- parameter \B_WIDTH 1
+ parameter \B_WIDTH 2
parameter \Y_WIDTH 1
- connect \A $105
- connect \B \oper_r__update
+ connect \A \oper_r__ldst_mode
+ connect \B 2'01
connect \Y $107
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:437"
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $107
- connect \B \shadown_i
+ connect \A $105
+ connect \B $107
connect \Y $109
end
- process $group_73
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:437"
+ wire width 1 $111
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:437"
+ cell $and $112
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A $109
+ connect \B \alu_valid
+ connect \Y $111
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:438"
+ wire width 1 $113
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:438"
+ cell $and $114
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A $111
+ connect \B \shadown_i
+ connect \Y $113
+ end
+ process $group_81
assign \wr__rel 2'00
assign \wr__rel [0] $103
- assign \wr__rel [1] $109
+ assign \wr__rel [1] $113
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:271"
wire width 1 \wr_any
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:440"
- wire width 1 $111
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:440"
- cell $or $112
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:441"
+ wire width 1 $115
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:441"
+ cell $or $116
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \st__go
connect \B \p_st_go
- connect \Y $111
+ connect \Y $115
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:440"
- wire width 1 $113
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:440"
- cell $or $114
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:441"
+ wire width 1 $117
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:441"
+ cell $or $118
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $111
+ connect \A $115
connect \B \wr__go [0]
- connect \Y $113
+ connect \Y $117
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:440"
- wire width 1 $115
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:440"
- cell $or $116
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:441"
+ wire width 1 $119
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:441"
+ cell $or $120
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $113
+ connect \A $117
connect \B \wr__go [1]
- connect \Y $115
+ connect \Y $119
end
- process $group_74
+ process $group_82
assign \wr_any 1'0
- assign \wr_any $115
+ assign \wr_any $119
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:442"
- wire width 1 $117
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:442"
- cell $and $118
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:443"
+ wire width 1 $121
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:443"
+ cell $and $122
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \rst_l_q_rst
connect \B \busy_o
- connect \Y $117
+ connect \Y $121
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:442"
- wire width 1 $119
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:442"
- cell $and $120
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:443"
+ wire width 1 $123
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:443"
+ cell $and $124
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $117
+ connect \A $121
connect \B \shadown_i
- connect \Y $119
+ connect \Y $123
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:442"
- wire width 1 $121
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:442"
- wire width 1 $122
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:442"
- cell $or $123
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:443"
+ wire width 1 $125
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:443"
+ wire width 1 $126
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:443"
+ cell $or $127
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \st__rel
connect \B \wr__rel [0]
- connect \Y $122
+ connect \Y $126
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:442"
- wire width 1 $124
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:442"
- cell $or $125
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:443"
+ wire width 1 $128
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:443"
+ cell $or $129
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $122
+ connect \A $126
connect \B \wr__rel [1]
- connect \Y $124
+ connect \Y $128
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:442"
- cell $not $126
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:443"
+ cell $not $130
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $124
- connect \Y $121
+ connect \A $128
+ connect \Y $125
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:442"
- wire width 1 $127
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:442"
- cell $and $128
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:443"
+ wire width 1 $131
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:443"
+ cell $and $132
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $119
- connect \B $121
- connect \Y $127
+ connect \A $123
+ connect \B $125
+ connect \Y $131
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:443"
- wire width 1 $129
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:443"
- cell $or $130
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:444"
+ wire width 1 $133
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:444"
+ cell $or $134
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \lod_l_qn_lod
connect \B \op_is_st
- connect \Y $129
+ connect \Y $133
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:443"
- wire width 1 $131
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:443"
- cell $and $132
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:444"
+ wire width 1 $135
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:444"
+ cell $and $136
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $127
- connect \B $129
- connect \Y $131
+ connect \A $131
+ connect \B $133
+ connect \Y $135
end
- process $group_75
+ process $group_83
assign \wr_reset 1'0
- assign \wr_reset $131
+ assign \wr_reset $135
sync init
end
- process $group_76
+ process $group_84
assign \done_o 1'0
assign \done_o \wr_reset
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
wire width 64 \dest1_o
- process $group_77
+ process $group_85
assign \o 64'0000000000000000000000000000000000000000000000000000000000000000
assign \o \dest1_o
sync init
end
- process $group_78
+ process $group_86
assign \dest1_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:451"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:452"
switch { \wr__go [0] }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:451"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:452"
case 1'1
assign \dest1_o \ldd_r
end
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
wire width 64 \dest2_o
- process $group_79
+ process $group_87
assign \ea 64'0000000000000000000000000000000000000000000000000000000000000000
assign \ea \dest2_o
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:456"
- wire width 1 $133
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:456"
- cell $and $134
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:393"
+ wire width 1 $137
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:393"
+ cell $eq $138
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 2
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 2
+ parameter \Y_WIDTH 1
+ connect \A \oper_r__ldst_mode
+ connect \B 2'01
+ connect \Y $137
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:457"
+ wire width 1 $139
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:457"
+ cell $and $140
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \oper_r__update
+ connect \A $137
connect \B \wr__go [1]
- connect \Y $133
+ connect \Y $139
end
- process $group_80
+ process $group_88
assign \dest2_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:456"
- switch { $133 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:456"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:457"
+ switch { $139 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:457"
case 1'1
assign \dest2_o \addr_r
end
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:93"
wire width 2 \wrmask
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:461"
- wire width 3 $135
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:461"
- wire width 3 $136
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:461"
- cell $and $137
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462"
+ wire width 3 $141
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:393"
+ wire width 1 $142
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:393"
+ cell $eq $143
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 2
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 2
+ parameter \Y_WIDTH 1
+ connect \A \oper_r__ldst_mode
+ connect \B 2'01
+ connect \Y $142
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462"
+ wire width 3 $144
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462"
+ cell $and $145
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \B_WIDTH 2
parameter \Y_WIDTH 3
connect \A { \busy_o \busy_o \busy_o }
- connect \B { \oper_r__update \op_is_ld }
- connect \Y $136
+ connect \B { $142 \op_is_ld }
+ connect \Y $144
end
- connect $135 $136
- process $group_81
+ connect $141 $144
+ process $group_89
assign \wrmask 2'00
- assign \wrmask $135 [1:0]
+ assign \wrmask $141 [1:0]
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:468"
- wire width 1 $138
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:468"
- cell $and $139
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:469"
+ wire width 1 $146
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:469"
+ cell $and $147
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \op_is_ld
connect \B \busy_o
- connect \Y $138
+ connect \Y $146
end
- process $group_82
+ process $group_90
assign \ldst_port0_is_ld_i 1'0
- assign \ldst_port0_is_ld_i $138
+ assign \ldst_port0_is_ld_i $146
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:469"
- wire width 1 $140
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:469"
- cell $and $141
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:470"
+ wire width 1 $148
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:470"
+ cell $and $149
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \op_is_st
connect \B \busy_o
- connect \Y $140
+ connect \Y $148
end
- process $group_83
+ process $group_91
assign \ldst_port0_is_st_i 1'0
- assign \ldst_port0_is_st_i $140
+ assign \ldst_port0_is_st_i $148
sync init
end
- process $group_84
+ process $group_92
assign \ldst_port0_data_len 4'0000
assign \ldst_port0_data_len \oper_i__data_len
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:373"
- wire width 96 $142
+ wire width 96 $150
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:373"
- cell $pos $143
+ cell $pos $151
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \Y_WIDTH 96
connect \A \addr_r
- connect \Y $142
+ connect \Y $150
end
- process $group_85
+ process $group_93
assign \ldst_port0_addr_i 96'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
- assign \ldst_port0_addr_i $142
+ assign \ldst_port0_addr_i $150
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:473"
- wire width 1 $144
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:473"
- cell $or $145
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:474"
+ wire width 1 $152
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:474"
+ cell $or $153
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \lod_l_q_lod
connect \B \sto_l_q_sto
- connect \Y $144
+ connect \Y $152
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:473"
- wire width 1 $146
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:473"
- cell $and $147
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:474"
+ wire width 1 $154
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:474"
+ cell $and $155
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
connect \A \alu_ok
- connect \B $144
- connect \Y $146
+ connect \B $152
+ connect \Y $154
end
- process $group_86
+ process $group_94
assign \ldst_port0_addr_i_ok 1'0
- assign \ldst_port0_addr_i_ok $146
+ assign \ldst_port0_addr_i_ok $154
sync init
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:106"
wire width 1 \addr_exc_o
- process $group_87
+ process $group_95
assign \addr_exc_o 1'0
assign \addr_exc_o \ldst_port0_addr_exc_o
sync init
end
- process $group_88
+ process $group_96
assign \addr_ok 1'0
assign \addr_ok \ldst_port0_addr_ok_o
sync init
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:11"
wire width 64 \lddata_r
- process $group_89
+ process $group_97
assign \ldd_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:478"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:479"
switch { \oper_i__byte_reverse }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:478"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:479"
case 1'1
assign \ldd_o \ldst_port0_ld_data_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:480"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:481"
case
assign \ldd_o \lddata_r
end
sync init
end
- process $group_90
+ process $group_98
assign \lddata_r 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:478"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:479"
switch { \oper_i__byte_reverse }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:478"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:479"
case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:480"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:481"
case
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:12"
switch \oper_i__data_len
end
sync init
end
- process $group_91
+ process $group_99
assign \ld_ok 1'0
assign \ld_ok \ldst_port0_ld_data_o_ok
sync init
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:11"
wire width 64 \stdata_r
- process $group_92
+ process $group_100
assign \ldst_port0_st_data_i 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:489"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:490"
switch { \oper_i__byte_reverse }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:489"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:490"
case 1'1
assign \ldst_port0_st_data_i \src_r2
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:491"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:492"
case
assign \ldst_port0_st_data_i \stdata_r
end
sync init
end
- process $group_93
+ process $group_101
assign \stdata_r 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:489"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:490"
switch { \oper_i__byte_reverse }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:489"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:490"
case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:491"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:492"
case
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:12"
switch \oper_i__data_len
end
sync init
end
- process $group_94
+ process $group_102
assign \ldst_port0_st_data_i_ok 1'0
assign \ldst_port0_st_data_i_ok \st__go
sync init
wire width 1 input 4 \rst
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 5 \clk
- attribute \enum_base_type "InternalOp"
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 7 input 6 \oper_i__insn_type
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00100000000 "MUL"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 11 input 7 \oper_i__fn_unit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 64 input 8 \oper_i__imm_data__imm
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 input 9 \oper_i__imm_data__imm_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 input 10 \oper_i__lk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 input 11 \oper_i__rc__rc
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 input 12 \oper_i__rc__rc_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 input 13 \oper_i__oe__oe
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 input 14 \oper_i__oe__oe_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 input 15 \oper_i__invert_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 input 16 \oper_i__zero_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 input 17 \oper_i__invert_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 3 input 18 \oper_i__write_cr__data
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 input 19 \oper_i__write_cr__ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 10 \oper_i__rc__rc
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 11 \oper_i__rc__rc_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 12 \oper_i__oe__oe
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 13 \oper_i__oe__oe_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 14 \oper_i__invert_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 15 \oper_i__zero_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 16 \oper_i__invert_out
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 17 \oper_i__write_cr0
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 2 input 20 \oper_i__input_carry
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 input 21 \oper_i__output_carry
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 input 22 \oper_i__input_cr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 input 23 \oper_i__output_cr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 input 24 \oper_i__is_32bit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 input 25 \oper_i__is_signed
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 4 input 26 \oper_i__data_len
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 32 input 27 \oper_i__insn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 input 28 \oper_i__byte_reverse
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 input 29 \oper_i__sign_extend
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 2 input 18 \oper_i__input_carry
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 19 \oper_i__output_carry
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 20 \oper_i__is_32bit
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 21 \oper_i__is_signed
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 4 input 22 \oper_i__data_len
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 input 23 \oper_i__insn
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94"
- wire width 1 input 30 \issue_i
+ wire width 1 input 24 \issue_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
- wire width 1 output 31 \busy_o
+ wire width 1 output 25 \busy_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:92"
- wire width 4 input 32 \rdmaskn
- attribute \enum_base_type "InternalOp"
+ wire width 4 input 26 \rdmaskn
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
- wire width 7 input 33 \oper_i__insn_type$1
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 7 input 27 \oper_i__insn_type$1
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00000000010 "ALU"
attribute \enum_value_00100000000 "MUL"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
- wire width 11 input 34 \oper_i__fn_unit$2
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
- wire width 32 input 35 \oper_i__insn$3
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
- wire width 1 input 36 \oper_i__read_cr_whole
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
- wire width 1 input 37 \oper_i__write_cr_whole
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 11 input 28 \oper_i__fn_unit$2
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 input 29 \oper_i__insn$3
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 30 \oper_i__read_cr_whole
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 31 \oper_i__write_cr_whole
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94"
- wire width 1 input 38 \issue_i$4
+ wire width 1 input 32 \issue_i$4
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
- wire width 1 output 39 \busy_o$5
+ wire width 1 output 33 \busy_o$5
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:92"
- wire width 6 input 40 \rdmaskn$6
- attribute \enum_base_type "InternalOp"
+ wire width 6 input 34 \rdmaskn$6
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 input 35 \oper_i__cia
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
- wire width 7 input 41 \oper_i__insn_type$7
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 7 input 36 \oper_i__insn_type$7
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00000000010 "ALU"
attribute \enum_value_00100000000 "MUL"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
- wire width 11 input 42 \oper_i__fn_unit$8
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
- wire width 64 input 43 \oper_i__imm_data__imm$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
- wire width 1 input 44 \oper_i__imm_data__imm_ok$10
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
- wire width 1 input 45 \oper_i__lk$11
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
- wire width 1 input 46 \oper_i__is_32bit$12
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
- wire width 32 input 47 \oper_i__insn$13
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 11 input 37 \oper_i__fn_unit$8
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 input 38 \oper_i__insn$9
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 input 39 \oper_i__imm_data__imm$10
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 40 \oper_i__imm_data__imm_ok$11
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 41 \oper_i__lk
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 42 \oper_i__is_32bit$12
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94"
- wire width 1 input 48 \issue_i$14
+ wire width 1 input 43 \issue_i$13
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
- wire width 1 output 49 \busy_o$15
+ wire width 1 output 44 \busy_o$14
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:92"
- wire width 4 input 50 \rdmaskn$16
- attribute \enum_base_type "InternalOp"
+ wire width 3 input 45 \rdmaskn$15
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
- wire width 7 input 51 \oper_i__insn_type$17
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 7 input 46 \oper_i__insn_type$16
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00000000010 "ALU"
attribute \enum_value_00100000000 "MUL"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
- wire width 11 input 52 \oper_i__fn_unit$18
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
- wire width 32 input 53 \oper_i__insn$19
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
- wire width 1 input 54 \oper_i__is_32bit$20
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
- wire width 5 input 55 \oper_i__traptype
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
- wire width 13 input 56 \oper_i__trapaddr
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 11 input 47 \oper_i__fn_unit$17
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 input 48 \oper_i__insn$18
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 input 49 \oper_i__msr
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 input 50 \oper_i__cia$19
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 51 \oper_i__is_32bit$20
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 5 input 52 \oper_i__traptype
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 13 input 53 \oper_i__trapaddr
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94"
- wire width 1 input 57 \issue_i$21
+ wire width 1 input 54 \issue_i$21
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
- wire width 1 output 58 \busy_o$22
+ wire width 1 output 55 \busy_o$22
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:92"
- wire width 6 input 59 \rdmaskn$23
- attribute \enum_base_type "InternalOp"
+ wire width 4 input 56 \rdmaskn$23
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 7 input 60 \oper_i__insn_type$24
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 7 input 57 \oper_i__insn_type$24
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00000000010 "ALU"
attribute \enum_value_00100000000 "MUL"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 11 input 61 \oper_i__fn_unit$25
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 64 input 62 \oper_i__imm_data__imm$26
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 input 63 \oper_i__imm_data__imm_ok$27
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 input 64 \oper_i__lk$28
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 input 65 \oper_i__rc__rc$29
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 input 66 \oper_i__rc__rc_ok$30
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 input 67 \oper_i__oe__oe$31
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 input 68 \oper_i__oe__oe_ok$32
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 input 69 \oper_i__invert_a$33
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 input 70 \oper_i__zero_a$34
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 11 input 58 \oper_i__fn_unit$25
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 input 59 \oper_i__imm_data__imm$26
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 60 \oper_i__imm_data__imm_ok$27
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 61 \oper_i__rc__rc$28
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 62 \oper_i__rc__rc_ok$29
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 63 \oper_i__oe__oe$30
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 64 \oper_i__oe__oe_ok$31
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 65 \oper_i__invert_a$32
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 66 \oper_i__zero_a$33
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 2 input 71 \oper_i__input_carry$35
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 input 72 \oper_i__invert_out$36
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 3 input 73 \oper_i__write_cr__data$37
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 input 74 \oper_i__write_cr__ok$38
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 input 75 \oper_i__output_carry$39
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 input 76 \oper_i__is_32bit$40
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 input 77 \oper_i__is_signed$41
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 4 input 78 \oper_i__data_len$42
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 32 input 79 \oper_i__insn$43
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 2 input 67 \oper_i__input_carry$34
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 68 \oper_i__invert_out$35
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 69 \oper_i__write_cr0$36
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 70 \oper_i__output_carry$37
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 71 \oper_i__is_32bit$38
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 72 \oper_i__is_signed$39
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 4 input 73 \oper_i__data_len$40
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 input 74 \oper_i__insn$41
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94"
+ wire width 1 input 75 \issue_i$42
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
+ wire width 1 output 76 \busy_o$43
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:92"
+ wire width 2 input 77 \rdmaskn$44
+ attribute \enum_base_type "MicrOp"
+ attribute \enum_value_0000000 "OP_ILLEGAL"
+ attribute \enum_value_0000001 "OP_NOP"
+ attribute \enum_value_0000010 "OP_ADD"
+ attribute \enum_value_0000011 "OP_ADDPCIS"
+ attribute \enum_value_0000100 "OP_AND"
+ attribute \enum_value_0000101 "OP_ATTN"
+ attribute \enum_value_0000110 "OP_B"
+ attribute \enum_value_0000111 "OP_BC"
+ attribute \enum_value_0001000 "OP_BCREG"
+ attribute \enum_value_0001001 "OP_BPERM"
+ attribute \enum_value_0001010 "OP_CMP"
+ attribute \enum_value_0001011 "OP_CMPB"
+ attribute \enum_value_0001100 "OP_CMPEQB"
+ attribute \enum_value_0001101 "OP_CMPRB"
+ attribute \enum_value_0001110 "OP_CNTZ"
+ attribute \enum_value_0001111 "OP_CRAND"
+ attribute \enum_value_0010000 "OP_CRANDC"
+ attribute \enum_value_0010001 "OP_CREQV"
+ attribute \enum_value_0010010 "OP_CRNAND"
+ attribute \enum_value_0010011 "OP_CRNOR"
+ attribute \enum_value_0010100 "OP_CROR"
+ attribute \enum_value_0010101 "OP_CRORC"
+ attribute \enum_value_0010110 "OP_CRXOR"
+ attribute \enum_value_0010111 "OP_DARN"
+ attribute \enum_value_0011000 "OP_DCBF"
+ attribute \enum_value_0011001 "OP_DCBST"
+ attribute \enum_value_0011010 "OP_DCBT"
+ attribute \enum_value_0011011 "OP_DCBTST"
+ attribute \enum_value_0011100 "OP_DCBZ"
+ attribute \enum_value_0011101 "OP_DIV"
+ attribute \enum_value_0011110 "OP_DIVE"
+ attribute \enum_value_0011111 "OP_EXTS"
+ attribute \enum_value_0100000 "OP_EXTSWSLI"
+ attribute \enum_value_0100001 "OP_ICBI"
+ attribute \enum_value_0100010 "OP_ICBT"
+ attribute \enum_value_0100011 "OP_ISEL"
+ attribute \enum_value_0100100 "OP_ISYNC"
+ attribute \enum_value_0100101 "OP_LOAD"
+ attribute \enum_value_0100110 "OP_STORE"
+ attribute \enum_value_0100111 "OP_MADDHD"
+ attribute \enum_value_0101000 "OP_MADDHDU"
+ attribute \enum_value_0101001 "OP_MADDLD"
+ attribute \enum_value_0101010 "OP_MCRF"
+ attribute \enum_value_0101011 "OP_MCRXR"
+ attribute \enum_value_0101100 "OP_MCRXRX"
+ attribute \enum_value_0101101 "OP_MFCR"
+ attribute \enum_value_0101110 "OP_MFSPR"
+ attribute \enum_value_0101111 "OP_MOD"
+ attribute \enum_value_0110000 "OP_MTCRF"
+ attribute \enum_value_0110001 "OP_MTSPR"
+ attribute \enum_value_0110010 "OP_MUL_L64"
+ attribute \enum_value_0110011 "OP_MUL_H64"
+ attribute \enum_value_0110100 "OP_MUL_H32"
+ attribute \enum_value_0110101 "OP_OR"
+ attribute \enum_value_0110110 "OP_POPCNT"
+ attribute \enum_value_0110111 "OP_PRTY"
+ attribute \enum_value_0111000 "OP_RLC"
+ attribute \enum_value_0111001 "OP_RLCL"
+ attribute \enum_value_0111010 "OP_RLCR"
+ attribute \enum_value_0111011 "OP_SETB"
+ attribute \enum_value_0111100 "OP_SHL"
+ attribute \enum_value_0111101 "OP_SHR"
+ attribute \enum_value_0111110 "OP_SYNC"
+ attribute \enum_value_0111111 "OP_TRAP"
+ attribute \enum_value_1000011 "OP_XOR"
+ attribute \enum_value_1000100 "OP_SIM_CONFIG"
+ attribute \enum_value_1000101 "OP_CROP"
+ attribute \enum_value_1000110 "OP_RFID"
+ attribute \enum_value_1000111 "OP_MFMSR"
+ attribute \enum_value_1001000 "OP_MTMSRD"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 7 input 78 \oper_i__insn_type$45
+ attribute \enum_base_type "Function"
+ attribute \enum_value_00000000000 "NONE"
+ attribute \enum_value_00000000010 "ALU"
+ attribute \enum_value_00000000100 "LDST"
+ attribute \enum_value_00000001000 "SHIFT_ROT"
+ attribute \enum_value_00000010000 "LOGICAL"
+ attribute \enum_value_00000100000 "BRANCH"
+ attribute \enum_value_00001000000 "CR"
+ attribute \enum_value_00010000000 "TRAP"
+ attribute \enum_value_00100000000 "MUL"
+ attribute \enum_value_01000000000 "DIV"
+ attribute \enum_value_10000000000 "SPR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 11 input 79 \oper_i__fn_unit$46
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 input 80 \oper_i__insn$47
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 81 \oper_i__is_32bit$48
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94"
- wire width 1 input 80 \issue_i$44
+ wire width 1 input 82 \issue_i$49
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
- wire width 1 output 81 \busy_o$45
+ wire width 1 output 83 \busy_o$50
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:92"
- wire width 2 input 82 \rdmaskn$46
- attribute \enum_base_type "InternalOp"
+ wire width 6 input 84 \rdmaskn$51
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20"
- wire width 7 input 83 \oper_i__insn_type$47
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 7 input 85 \oper_i__insn_type$52
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00000000010 "ALU"
attribute \enum_value_00100000000 "MUL"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20"
- wire width 11 input 84 \oper_i__fn_unit$48
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20"
- wire width 32 input 85 \oper_i__insn$49
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20"
- wire width 1 input 86 \oper_i__is_32bit$50
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 11 input 86 \oper_i__fn_unit$53
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 input 87 \oper_i__imm_data__imm$54
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 88 \oper_i__imm_data__imm_ok$55
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 89 \oper_i__rc__rc$56
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 90 \oper_i__rc__rc_ok$57
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 91 \oper_i__oe__oe$58
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 92 \oper_i__oe__oe_ok$59
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 93 \oper_i__invert_a$60
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 94 \oper_i__zero_a$61
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 95 \oper_i__invert_out$62
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 96 \oper_i__write_cr0$63
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 97 \oper_i__is_32bit$64
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 98 \oper_i__is_signed$65
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 input 99 \oper_i__insn$66
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94"
- wire width 1 input 87 \issue_i$51
+ wire width 1 input 100 \issue_i$67
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
- wire width 1 output 88 \busy_o$52
+ wire width 1 output 101 \busy_o$68
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:92"
- wire width 6 input 89 \rdmaskn$53
- attribute \enum_base_type "InternalOp"
+ wire width 3 input 102 \rdmaskn$69
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 7 input 90 \oper_i__insn_type$54
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 7 input 103 \oper_i__insn_type$70
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00000000010 "ALU"
attribute \enum_value_00100000000 "MUL"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 11 input 91 \oper_i__fn_unit$55
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 64 input 92 \oper_i__imm_data__imm$56
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 input 93 \oper_i__imm_data__imm_ok$57
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 input 94 \oper_i__rc__rc$58
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 input 95 \oper_i__rc__rc_ok$59
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 input 96 \oper_i__oe__oe$60
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 input 97 \oper_i__oe__oe_ok$61
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 3 input 98 \oper_i__write_cr__data$62
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 input 99 \oper_i__write_cr__ok$63
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 11 input 104 \oper_i__fn_unit$71
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 input 105 \oper_i__imm_data__imm$72
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 106 \oper_i__imm_data__imm_ok$73
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 107 \oper_i__rc__rc$74
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 108 \oper_i__rc__rc_ok$75
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 109 \oper_i__oe__oe$76
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 110 \oper_i__oe__oe_ok$77
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 2 input 100 \oper_i__input_carry$64
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 input 101 \oper_i__output_carry$65
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 input 102 \oper_i__input_cr$66
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 input 103 \oper_i__output_cr$67
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 input 104 \oper_i__is_32bit$68
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 input 105 \oper_i__is_signed$69
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 32 input 106 \oper_i__insn$70
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 2 input 112 \oper_i__input_carry$78
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 113 \oper_i__output_carry$79
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 114 \oper_i__input_cr
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 115 \oper_i__output_cr
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 116 \oper_i__is_32bit$80
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 117 \oper_i__is_signed$81
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 input 118 \oper_i__insn$82
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94"
- wire width 1 input 107 \issue_i$71
+ wire width 1 input 119 \issue_i$83
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
- wire width 1 output 108 \busy_o$72
+ wire width 1 output 120 \busy_o$84
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:92"
- wire width 4 input 109 \rdmaskn$73
- attribute \enum_base_type "InternalOp"
+ wire width 4 input 121 \rdmaskn$85
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
- wire width 7 input 110 \oper_i__insn_type$74
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
- wire width 64 input 111 \oper_i__imm_data__imm$75
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
- wire width 1 input 112 \oper_i__imm_data__imm_ok$76
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
- wire width 1 input 113 \oper_i__zero_a$77
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
- wire width 1 input 114 \oper_i__is_32bit$78
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
- wire width 1 input 115 \oper_i__is_signed$79
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
- wire width 4 input 116 \oper_i__data_len$80
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
- wire width 1 input 117 \oper_i__byte_reverse$81
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
- wire width 1 input 118 \oper_i__sign_extend$82
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
- wire width 1 input 119 \oper_i__update
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 7 input 122 \oper_i__insn_type$86
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 input 123 \oper_i__imm_data__imm$87
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 124 \oper_i__imm_data__imm_ok$88
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 125 \oper_i__zero_a$89
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 126 \oper_i__rc__rc$90
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 127 \oper_i__rc__rc_ok$91
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 128 \oper_i__oe__oe$92
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 129 \oper_i__oe__oe_ok$93
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 130 \oper_i__is_32bit$94
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 131 \oper_i__is_signed$95
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 4 input 132 \oper_i__data_len$96
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 133 \oper_i__byte_reverse
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 input 134 \oper_i__sign_extend
+ attribute \enum_base_type "LDSTMode"
+ attribute \enum_value_00 "NONE"
+ attribute \enum_value_01 "update"
+ attribute \enum_value_10 "cix"
+ attribute \enum_value_11 "cx"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 2 input 135 \oper_i__ldst_mode
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94"
- wire width 1 input 120 \issue_i$83
+ wire width 1 input 136 \issue_i$97
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
- wire width 1 output 121 \busy_o$84
+ wire width 1 output 137 \busy_o$98
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:92"
- wire width 3 input 122 \rdmaskn$85
+ wire width 3 input 138 \rdmaskn$99
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 4 output 123 \rd__rel
+ wire width 4 output 139 \rd__rel
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 4 input 124 \rd__go
+ wire width 4 input 140 \rd__go
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
- wire width 64 input 125 \src1_i
+ wire width 64 input 141 \src1_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 6 output 126 \rd__rel$86
+ wire width 6 output 142 \rd__rel$100
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 6 input 127 \rd__go$87
+ wire width 6 input 143 \rd__go$101
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
- wire width 64 input 128 \src1_i$88
+ wire width 64 input 144 \src1_i$102
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 6 input 136 \rd__go$96
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 4 input 139 \rd__go$99
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
- wire width 64 input 140 \src1_i$100
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 3 output 141 \rd__rel$101
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 3 input 142 \rd__go$102
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
- wire width 64 input 143 \src1_i$103
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+ wire width 3 output 160 \rd__rel$118
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+ wire width 3 input 161 \rd__go$119
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
- wire width 64 input 144 \src2_i
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
- wire width 64 input 146 \src2_i$105
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
- wire width 64 input 147 \src2_i$106
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
- wire width 64 input 148 \src2_i$107
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
- wire width 64 input 149 \src2_i$108
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
- wire width 64 input 150 \src3_i
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
- wire width 64 input 151 \src3_i$109
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
- wire width 1 input 152 \src3_i$110
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
- wire width 2 input 155 \src6_i
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
- wire width 2 input 156 \src4_i$112
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
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- wire width 4 input 161 \rd__go$116
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
- wire width 4 input 162 \src3_i$117
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
- wire width 4 input 163 \src5_i$118
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
- wire width 4 input 164 \src6_i$119
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+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+ wire width 3 output 181 \rd__rel$134
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+ wire width 3 input 182 \rd__go$135
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
- wire width 64 input 165 \src1_i$120
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
- wire width 64 input 166 \src3_i$121
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
- wire width 64 input 169 \src4_i$124
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
- wire width 64 input 170 \src4_i$125
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
- wire width 64 input 171 \src5_i$126
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
- wire width 64 input 172 \src6_i$127
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
- wire width 64 input 173 \src2_i$128
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 174 \o_ok
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 5 input 176 \wr__go
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 180 \o_ok$132
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 5 output 181 \wr__rel$133
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 4 output 211 \cr_a$157
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 212 \xer_ca_ok
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 2 output 223 \xer_ov$165
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
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- wire width 1 output 236 \fast2_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 237 \fast2_ok$174
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 output 238 \fast2
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 output 239 \fast2$175
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 240 \nia_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 241 \nia_ok$176
+ wire width 1 output 260 \fast1_ok$196
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
+ wire width 64 output 261 \dest1_o$197
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
+ wire width 64 output 262 \dest2_o$198
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
+ wire width 64 output 263 \dest3_o$199
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 output 242 \nia
+ wire width 1 output 264 \fast2_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 output 243 \nia$177
+ wire width 1 output 265 \fast2_ok$200
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
+ wire width 64 output 266 \dest2_o$201
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
+ wire width 64 output 267 \dest3_o$202
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 244 \msr_ok
+ wire width 1 output 268 \nia_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 output 245 \msr
+ wire width 1 output 269 \nia_ok$203
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
+ wire width 64 output 270 \dest3_o$204
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
+ wire width 64 output 271 \dest4_o$205
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 246 \spr1_ok
+ wire width 1 output 272 \msr_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
+ wire width 64 output 273 \dest5_o$206
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 output 247 \spr1
+ wire width 1 output 274 \spr1_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
+ wire width 64 output 275 \dest2_o$207
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96"
- wire width 1 input 248 \go_die_i
+ wire width 1 input 276 \go_die_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
- wire width 1 input 249 \shadown_i
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
- wire width 64 output 250 \dest1_o
+ wire width 1 input 277 \shadown_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96"
- wire width 1 input 251 \go_die_i$178
+ wire width 1 input 278 \go_die_i$208
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
- wire width 1 input 252 \shadown_i$179
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
- wire width 64 output 253 \dest1_o$180
+ wire width 1 input 279 \shadown_i$209
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96"
- wire width 1 input 254 \go_die_i$181
+ wire width 1 input 280 \go_die_i$210
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
- wire width 1 input 255 \shadown_i$182
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
- wire width 64 output 256 \dest1_o$183
+ wire width 1 input 281 \shadown_i$211
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96"
- wire width 1 input 257 \go_die_i$184
+ wire width 1 input 282 \go_die_i$212
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
- wire width 1 input 258 \shadown_i$185
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
- wire width 64 output 259 \dest1_o$186
+ wire width 1 input 283 \shadown_i$213
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96"
- wire width 1 input 260 \go_die_i$187
+ wire width 1 input 284 \go_die_i$214
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
- wire width 1 input 261 \shadown_i$188
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
- wire width 64 output 262 \dest1_o$189
+ wire width 1 input 285 \shadown_i$215
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96"
- wire width 1 input 263 \go_die_i$190
+ wire width 1 input 286 \go_die_i$216
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
- wire width 1 input 264 \shadown_i$191
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
- wire width 64 output 265 \dest1_o$192
+ wire width 1 input 287 \shadown_i$217
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96"
- wire width 1 input 266 \go_die_i$193
+ wire width 1 input 288 \go_die_i$218
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
- wire width 1 input 267 \shadown_i$194
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
- wire width 64 output 268 \dest1_o$195
+ wire width 1 input 289 \shadown_i$219
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96"
+ wire width 1 input 290 \go_die_i$220
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
+ wire width 1 input 291 \shadown_i$221
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96"
- wire width 1 input 269 \go_die_i$196
+ wire width 1 input 292 \go_die_i$222
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:112"
- wire width 1 output 270 \load_mem_o
+ wire width 1 output 293 \load_mem_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:113"
- wire width 1 output 271 \stwd_mem_o
+ wire width 1 output 294 \stwd_mem_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
- wire width 1 input 272 \shadown_i$197
+ wire width 1 input 295 \shadown_i$223
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:95"
- wire width 1 output 273 \ldst_port0_is_ld_i
+ wire width 1 output 296 \ldst_port0_is_ld_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:96"
- wire width 1 output 274 \ldst_port0_is_st_i
+ wire width 1 output 297 \ldst_port0_is_st_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99"
- wire width 4 output 275 \ldst_port0_data_len
+ wire width 4 output 298 \ldst_port0_data_len
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 96 output 276 \ldst_port0_addr_i
+ wire width 96 output 299 \ldst_port0_addr_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 277 \ldst_port0_addr_i_ok
+ wire width 1 output 300 \ldst_port0_addr_i_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:107"
- wire width 1 input 278 \ldst_port0_addr_exc_o
+ wire width 1 input 301 \ldst_port0_addr_exc_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:106"
- wire width 1 input 279 \ldst_port0_addr_ok_o
+ wire width 1 input 302 \ldst_port0_addr_ok_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 input 280 \ldst_port0_ld_data_o
+ wire width 64 input 303 \ldst_port0_ld_data_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 input 281 \ldst_port0_ld_data_o_ok
+ wire width 1 input 304 \ldst_port0_ld_data_o_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 output 282 \ldst_port0_st_data_i
+ wire width 64 output 305 \ldst_port0_st_data_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 283 \ldst_port0_st_data_i_ok
+ wire width 1 output 306 \ldst_port0_st_data_i_ok
cell \alu0 \alu0
connect \rst \rst
connect \clk \clk
connect \oper_i__fn_unit \oper_i__fn_unit
connect \oper_i__imm_data__imm \oper_i__imm_data__imm
connect \oper_i__imm_data__imm_ok \oper_i__imm_data__imm_ok
- connect \oper_i__lk \oper_i__lk
connect \oper_i__rc__rc \oper_i__rc__rc
connect \oper_i__rc__rc_ok \oper_i__rc__rc_ok
connect \oper_i__oe__oe \oper_i__oe__oe
connect \oper_i__invert_a \oper_i__invert_a
connect \oper_i__zero_a \oper_i__zero_a
connect \oper_i__invert_out \oper_i__invert_out
- connect \oper_i__write_cr__data \oper_i__write_cr__data
- connect \oper_i__write_cr__ok \oper_i__write_cr__ok
+ connect \oper_i__write_cr0 \oper_i__write_cr0
connect \oper_i__input_carry \oper_i__input_carry
connect \oper_i__output_carry \oper_i__output_carry
- connect \oper_i__input_cr \oper_i__input_cr
- connect \oper_i__output_cr \oper_i__output_cr
connect \oper_i__is_32bit \oper_i__is_32bit
connect \oper_i__is_signed \oper_i__is_signed
connect \oper_i__data_len \oper_i__data_len
connect \oper_i__insn \oper_i__insn
- connect \oper_i__byte_reverse \oper_i__byte_reverse
- connect \oper_i__sign_extend \oper_i__sign_extend
connect \issue_i \issue_i
connect \busy_o \busy_o
connect \rdmaskn \rdmaskn
connect \rd__go \rd__go
connect \src1_i \src1_i
connect \src2_i \src2_i
- connect \src3_i \src3_i$110
- connect \src4_i \src4_i$111
+ connect \src3_i \src3_i$128
+ connect \src4_i \src4_i$130
connect \o_ok \o_ok
connect \wr__rel \wr__rel
connect \wr__go \wr__go
- connect \o \o
+ connect \dest1_o \dest1_o
connect \cr_a_ok \cr_a_ok
- connect \cr_a \cr_a
+ connect \dest2_o \dest2_o$175
connect \xer_ca_ok \xer_ca_ok
- connect \xer_ca \xer_ca
+ connect \dest3_o \dest3_o$182
connect \xer_ov_ok \xer_ov_ok
- connect \xer_ov \xer_ov
+ connect \dest4_o \dest4_o
connect \xer_so_ok \xer_so_ok
- connect \xer_so \xer_so
+ connect \dest5_o \dest5_o$190
connect \go_die_i \go_die_i
connect \shadown_i \shadown_i
- connect \dest1_o \dest1_o
end
cell \cr0 \cr0
connect \rst \rst
connect \issue_i \issue_i$4
connect \busy_o \busy_o$5
connect \rdmaskn \rdmaskn$6
- connect \rd__rel \rd__rel$86
- connect \rd__go \rd__go$87
- connect \src1_i \src1_i$88
- connect \src2_i \src2_i$104
- connect \src3_i \src3_i$113
- connect \src4_i \src4_i$114
- connect \src5_i \src5_i$118
- connect \src6_i \src6_i$119
- connect \o_ok \o_ok$129
- connect \wr__rel \wr__rel$130
- connect \wr__go \wr__go$131
- connect \o \o$146
+ connect \rd__rel \rd__rel$100
+ connect \rd__go \rd__go$101
+ connect \src1_i \src1_i$102
+ connect \src2_i \src2_i$121
+ connect \src3_i \src3_i$132
+ connect \src4_i \src4_i$133
+ connect \src5_i \src5_i$137
+ connect \src6_i \src6_i$138
+ connect \o_ok \o_ok$145
+ connect \wr__rel \wr__rel$146
+ connect \wr__go \wr__go$147
+ connect \dest1_o \dest1_o$165
connect \full_cr_ok \full_cr_ok
- connect \full_cr \full_cr
- connect \cr_a_ok \cr_a_ok$152
- connect \cr_a \cr_a$155
- connect \go_die_i \go_die_i$178
- connect \shadown_i \shadown_i$179
- connect \dest1_o \dest1_o$180
+ connect \dest2_o \dest2_o
+ connect \cr_a_ok \cr_a_ok$171
+ connect \dest3_o \dest3_o
+ connect \go_die_i \go_die_i$208
+ connect \shadown_i \shadown_i$209
end
cell \branch0 \branch0
connect \rst \rst
connect \clk \clk
+ connect \oper_i__cia \oper_i__cia
connect \oper_i__insn_type \oper_i__insn_type$7
connect \oper_i__fn_unit \oper_i__fn_unit$8
- connect \oper_i__imm_data__imm \oper_i__imm_data__imm$9
- connect \oper_i__imm_data__imm_ok \oper_i__imm_data__imm_ok$10
- connect \oper_i__lk \oper_i__lk$11
+ connect \oper_i__insn \oper_i__insn$9
+ connect \oper_i__imm_data__imm \oper_i__imm_data__imm$10
+ connect \oper_i__imm_data__imm_ok \oper_i__imm_data__imm_ok$11
+ connect \oper_i__lk \oper_i__lk
connect \oper_i__is_32bit \oper_i__is_32bit$12
- connect \oper_i__insn \oper_i__insn$13
- connect \issue_i \issue_i$14
- connect \busy_o \busy_o$15
- connect \rdmaskn \rdmaskn$16
- connect \rd__rel \rd__rel$115
- connect \rd__go \rd__go$116
- connect \src3_i \src3_i$117
- connect \src1_i \src1_i$120
- connect \src2_i \src2_i$123
- connect \src4_i \src4_i$125
+ connect \issue_i \issue_i$13
+ connect \busy_o \busy_o$14
+ connect \rdmaskn \rdmaskn$15
+ connect \rd__rel \rd__rel$134
+ connect \rd__go \rd__go$135
+ connect \src3_i \src3_i$136
+ connect \src1_i \src1_i$139
+ connect \src2_i \src2_i$142
connect \fast1_ok \fast1_ok
- connect \wr__rel \wr__rel$168
- connect \wr__go \wr__go$169
- connect \fast1 \fast1
+ connect \wr__rel \wr__rel$193
+ connect \wr__go \wr__go$194
+ connect \dest1_o \dest1_o$197
connect \fast2_ok \fast2_ok
- connect \fast2 \fast2
+ connect \dest2_o \dest2_o$201
connect \nia_ok \nia_ok
- connect \nia \nia
- connect \go_die_i \go_die_i$181
- connect \shadown_i \shadown_i$182
- connect \dest1_o \dest1_o$183
+ connect \dest3_o \dest3_o$204
+ connect \go_die_i \go_die_i$210
+ connect \shadown_i \shadown_i$211
end
cell \trap0 \trap0
connect \rst \rst
connect \clk \clk
- connect \oper_i__insn_type \oper_i__insn_type$17
- connect \oper_i__fn_unit \oper_i__fn_unit$18
- connect \oper_i__insn \oper_i__insn$19
+ connect \oper_i__insn_type \oper_i__insn_type$16
+ connect \oper_i__fn_unit \oper_i__fn_unit$17
+ connect \oper_i__insn \oper_i__insn$18
+ connect \oper_i__msr \oper_i__msr
+ connect \oper_i__cia \oper_i__cia$19
connect \oper_i__is_32bit \oper_i__is_32bit$20
connect \oper_i__traptype \oper_i__traptype
connect \oper_i__trapaddr \oper_i__trapaddr
connect \issue_i \issue_i$21
connect \busy_o \busy_o$22
connect \rdmaskn \rdmaskn$23
- connect \rd__rel \rd__rel$89
- connect \rd__go \rd__go$90
- connect \src1_i \src1_i$91
- connect \src2_i \src2_i$105
- connect \src3_i \src3_i$121
- connect \src4_i \src4_i$124
- connect \src5_i \src5_i$126
- connect \src6_i \src6_i$127
- connect \o_ok \o_ok$132
- connect \wr__rel \wr__rel$133
- connect \wr__go \wr__go$134
- connect \o \o$147
- connect \fast1_ok \fast1_ok$170
- connect \fast1 \fast1$172
- connect \fast2_ok \fast2_ok$174
- connect \fast2 \fast2$175
- connect \nia_ok \nia_ok$176
- connect \nia \nia$177
+ connect \rd__rel \rd__rel$103
+ connect \rd__go \rd__go$104
+ connect \src1_i \src1_i$105
+ connect \src2_i \src2_i$122
+ connect \src3_i \src3_i$140
+ connect \src4_i \src4_i$143
+ connect \o_ok \o_ok$148
+ connect \wr__rel \wr__rel$149
+ connect \wr__go \wr__go$150
+ connect \dest1_o \dest1_o$166
+ connect \fast1_ok \fast1_ok$195
+ connect \dest2_o \dest2_o$198
+ connect \fast2_ok \fast2_ok$200
+ connect \dest3_o \dest3_o$202
+ connect \nia_ok \nia_ok$203
+ connect \dest4_o \dest4_o$205
connect \msr_ok \msr_ok
- connect \msr \msr
- connect \go_die_i \go_die_i$184
- connect \shadown_i \shadown_i$185
- connect \dest1_o \dest1_o$186
+ connect \dest5_o \dest5_o$206
+ connect \go_die_i \go_die_i$212
+ connect \shadown_i \shadown_i$213
end
cell \logical0 \logical0
connect \rst \rst
connect \oper_i__fn_unit \oper_i__fn_unit$25
connect \oper_i__imm_data__imm \oper_i__imm_data__imm$26
connect \oper_i__imm_data__imm_ok \oper_i__imm_data__imm_ok$27
- connect \oper_i__lk \oper_i__lk$28
- connect \oper_i__rc__rc \oper_i__rc__rc$29
- connect \oper_i__rc__rc_ok \oper_i__rc__rc_ok$30
- connect \oper_i__oe__oe \oper_i__oe__oe$31
- connect \oper_i__oe__oe_ok \oper_i__oe__oe_ok$32
- connect \oper_i__invert_a \oper_i__invert_a$33
- connect \oper_i__zero_a \oper_i__zero_a$34
- connect \oper_i__input_carry \oper_i__input_carry$35
- connect \oper_i__invert_out \oper_i__invert_out$36
- connect \oper_i__write_cr__data \oper_i__write_cr__data$37
- connect \oper_i__write_cr__ok \oper_i__write_cr__ok$38
- connect \oper_i__output_carry \oper_i__output_carry$39
- connect \oper_i__is_32bit \oper_i__is_32bit$40
- connect \oper_i__is_signed \oper_i__is_signed$41
- connect \oper_i__data_len \oper_i__data_len$42
- connect \oper_i__insn \oper_i__insn$43
- connect \issue_i \issue_i$44
- connect \busy_o \busy_o$45
- connect \rdmaskn \rdmaskn$46
- connect \rd__rel \rd__rel$92
- connect \rd__go \rd__go$93
- connect \src1_i \src1_i$94
- connect \src2_i \src2_i$106
- connect \o_ok \o_ok$135
- connect \wr__rel \wr__rel$136
- connect \wr__go \wr__go$137
- connect \o \o$148
- connect \cr_a_ok \cr_a_ok$153
- connect \cr_a \cr_a$156
- connect \xer_ca_ok \xer_ca_ok$158
- connect \xer_ca \xer_ca$161
- connect \go_die_i \go_die_i$187
- connect \shadown_i \shadown_i$188
- connect \dest1_o \dest1_o$189
+ connect \oper_i__rc__rc \oper_i__rc__rc$28
+ connect \oper_i__rc__rc_ok \oper_i__rc__rc_ok$29
+ connect \oper_i__oe__oe \oper_i__oe__oe$30
+ connect \oper_i__oe__oe_ok \oper_i__oe__oe_ok$31
+ connect \oper_i__invert_a \oper_i__invert_a$32
+ connect \oper_i__zero_a \oper_i__zero_a$33
+ connect \oper_i__input_carry \oper_i__input_carry$34
+ connect \oper_i__invert_out \oper_i__invert_out$35
+ connect \oper_i__write_cr0 \oper_i__write_cr0$36
+ connect \oper_i__output_carry \oper_i__output_carry$37
+ connect \oper_i__is_32bit \oper_i__is_32bit$38
+ connect \oper_i__is_signed \oper_i__is_signed$39
+ connect \oper_i__data_len \oper_i__data_len$40
+ connect \oper_i__insn \oper_i__insn$41
+ connect \issue_i \issue_i$42
+ connect \busy_o \busy_o$43
+ connect \rdmaskn \rdmaskn$44
+ connect \rd__rel \rd__rel$106
+ connect \rd__go \rd__go$107
+ connect \src1_i \src1_i$108
+ connect \src2_i \src2_i$123
+ connect \o_ok \o_ok$151
+ connect \wr__rel \wr__rel$152
+ connect \wr__go \wr__go$153
+ connect \dest1_o \dest1_o$167
+ connect \cr_a_ok \cr_a_ok$172
+ connect \dest2_o \dest2_o$176
+ connect \xer_ca_ok \xer_ca_ok$179
+ connect \dest3_o \dest3_o$183
+ connect \go_die_i \go_die_i$214
+ connect \shadown_i \shadown_i$215
end
cell \spr0 \spr0
connect \rst \rst
connect \clk \clk
- connect \oper_i__insn_type \oper_i__insn_type$47
- connect \oper_i__fn_unit \oper_i__fn_unit$48
- connect \oper_i__insn \oper_i__insn$49
- connect \oper_i__is_32bit \oper_i__is_32bit$50
- connect \issue_i \issue_i$51
- connect \busy_o \busy_o$52
- connect \rdmaskn \rdmaskn$53
- connect \rd__rel \rd__rel$95
- connect \rd__go \rd__go$96
- connect \src1_i \src1_i$97
+ connect \oper_i__insn_type \oper_i__insn_type$45
+ connect \oper_i__fn_unit \oper_i__fn_unit$46
+ connect \oper_i__insn \oper_i__insn$47
+ connect \oper_i__is_32bit \oper_i__is_32bit$48
+ connect \issue_i \issue_i$49
+ connect \busy_o \busy_o$50
+ connect \rdmaskn \rdmaskn$51
+ connect \rd__rel \rd__rel$109
+ connect \rd__go \rd__go$110
+ connect \src1_i \src1_i$111
connect \src4_i \src4_i
connect \src6_i \src6_i
connect \src5_i \src5_i
- connect \src3_i \src3_i$122
- connect \src2_i \src2_i$128
- connect \o_ok \o_ok$138
- connect \wr__rel \wr__rel$139
- connect \wr__go \wr__go$140
- connect \o \o$149
- connect \xer_ca_ok \xer_ca_ok$159
- connect \xer_ca \xer_ca$162
- connect \xer_ov_ok \xer_ov_ok$164
- connect \xer_ov \xer_ov$165
- connect \xer_so_ok \xer_so_ok$166
- connect \xer_so \xer_so$167
- connect \fast1_ok \fast1_ok$171
- connect \fast1 \fast1$173
+ connect \src3_i \src3_i$141
+ connect \src2_i \src2_i$144
+ connect \o_ok \o_ok$154
+ connect \wr__rel \wr__rel$155
+ connect \wr__go \wr__go$156
+ connect \dest1_o \dest1_o$168
+ connect \xer_ca_ok \xer_ca_ok$180
+ connect \dest6_o \dest6_o
+ connect \xer_ov_ok \xer_ov_ok$185
+ connect \dest5_o \dest5_o
+ connect \xer_so_ok \xer_so_ok$188
+ connect \dest4_o \dest4_o$191
+ connect \fast1_ok \fast1_ok$196
+ connect \dest3_o \dest3_o$199
connect \spr1_ok \spr1_ok
- connect \spr1 \spr1
- connect \go_die_i \go_die_i$190
- connect \shadown_i \shadown_i$191
- connect \dest1_o \dest1_o$192
+ connect \dest2_o \dest2_o$207
+ connect \go_die_i \go_die_i$216
+ connect \shadown_i \shadown_i$217
+ end
+ cell \mul0 \mul0
+ connect \rst \rst
+ connect \clk \clk
+ connect \oper_i__insn_type \oper_i__insn_type$52
+ connect \oper_i__fn_unit \oper_i__fn_unit$53
+ connect \oper_i__imm_data__imm \oper_i__imm_data__imm$54
+ connect \oper_i__imm_data__imm_ok \oper_i__imm_data__imm_ok$55
+ connect \oper_i__rc__rc \oper_i__rc__rc$56
+ connect \oper_i__rc__rc_ok \oper_i__rc__rc_ok$57
+ connect \oper_i__oe__oe \oper_i__oe__oe$58
+ connect \oper_i__oe__oe_ok \oper_i__oe__oe_ok$59
+ connect \oper_i__invert_a \oper_i__invert_a$60
+ connect \oper_i__zero_a \oper_i__zero_a$61
+ connect \oper_i__invert_out \oper_i__invert_out$62
+ connect \oper_i__write_cr0 \oper_i__write_cr0$63
+ connect \oper_i__is_32bit \oper_i__is_32bit$64
+ connect \oper_i__is_signed \oper_i__is_signed$65
+ connect \oper_i__insn \oper_i__insn$66
+ connect \issue_i \issue_i$67
+ connect \busy_o \busy_o$68
+ connect \rdmaskn \rdmaskn$69
+ connect \rd__rel \rd__rel$112
+ connect \rd__go \rd__go$113
+ connect \src1_i \src1_i$114
+ connect \src2_i \src2_i$124
+ connect \src3_i \src3_i$129
+ connect \o_ok \o_ok$157
+ connect \wr__rel \wr__rel$158
+ connect \wr__go \wr__go$159
+ connect \dest1_o \dest1_o$169
+ connect \cr_a_ok \cr_a_ok$173
+ connect \dest2_o \dest2_o$177
+ connect \xer_ov_ok \xer_ov_ok$186
+ connect \dest3_o \dest3_o$187
+ connect \xer_so_ok \xer_so_ok$189
+ connect \dest4_o \dest4_o$192
+ connect \go_die_i \go_die_i$218
+ connect \shadown_i \shadown_i$219
end
cell \shiftrot0 \shiftrot0
connect \rst \rst
connect \clk \clk
- connect \oper_i__insn_type \oper_i__insn_type$54
- connect \oper_i__fn_unit \oper_i__fn_unit$55
- connect \oper_i__imm_data__imm \oper_i__imm_data__imm$56
- connect \oper_i__imm_data__imm_ok \oper_i__imm_data__imm_ok$57
- connect \oper_i__rc__rc \oper_i__rc__rc$58
- connect \oper_i__rc__rc_ok \oper_i__rc__rc_ok$59
- connect \oper_i__oe__oe \oper_i__oe__oe$60
- connect \oper_i__oe__oe_ok \oper_i__oe__oe_ok$61
- connect \oper_i__write_cr__data \oper_i__write_cr__data$62
- connect \oper_i__write_cr__ok \oper_i__write_cr__ok$63
- connect \oper_i__input_carry \oper_i__input_carry$64
- connect \oper_i__output_carry \oper_i__output_carry$65
- connect \oper_i__input_cr \oper_i__input_cr$66
- connect \oper_i__output_cr \oper_i__output_cr$67
- connect \oper_i__is_32bit \oper_i__is_32bit$68
- connect \oper_i__is_signed \oper_i__is_signed$69
- connect \oper_i__insn \oper_i__insn$70
- connect \issue_i \issue_i$71
- connect \busy_o \busy_o$72
- connect \rdmaskn \rdmaskn$73
- connect \rd__rel \rd__rel$98
- connect \rd__go \rd__go$99
- connect \src1_i \src1_i$100
- connect \src2_i \src2_i$107
+ connect \oper_i__insn_type \oper_i__insn_type$70
+ connect \oper_i__fn_unit \oper_i__fn_unit$71
+ connect \oper_i__imm_data__imm \oper_i__imm_data__imm$72
+ connect \oper_i__imm_data__imm_ok \oper_i__imm_data__imm_ok$73
+ connect \oper_i__rc__rc \oper_i__rc__rc$74
+ connect \oper_i__rc__rc_ok \oper_i__rc__rc_ok$75
+ connect \oper_i__oe__oe \oper_i__oe__oe$76
+ connect \oper_i__oe__oe_ok \oper_i__oe__oe_ok$77
+ connect \oper_i__input_carry \oper_i__input_carry$78
+ connect \oper_i__output_carry \oper_i__output_carry$79
+ connect \oper_i__input_cr \oper_i__input_cr
+ connect \oper_i__output_cr \oper_i__output_cr
+ connect \oper_i__is_32bit \oper_i__is_32bit$80
+ connect \oper_i__is_signed \oper_i__is_signed$81
+ connect \oper_i__insn \oper_i__insn$82
+ connect \issue_i \issue_i$83
+ connect \busy_o \busy_o$84
+ connect \rdmaskn \rdmaskn$85
+ connect \rd__rel \rd__rel$115
+ connect \rd__go \rd__go$116
+ connect \src1_i \src1_i$117
+ connect \src2_i \src2_i$125
connect \src3_i \src3_i
- connect \src4_i \src4_i$112
- connect \o_ok \o_ok$141
- connect \wr__rel \wr__rel$142
- connect \wr__go \wr__go$143
- connect \o \o$150
- connect \cr_a_ok \cr_a_ok$154
- connect \cr_a \cr_a$157
- connect \xer_ca_ok \xer_ca_ok$160
- connect \xer_ca \xer_ca$163
- connect \go_die_i \go_die_i$193
- connect \shadown_i \shadown_i$194
- connect \dest1_o \dest1_o$195
+ connect \src4_i \src4_i$131
+ connect \o_ok \o_ok$160
+ connect \wr__rel \wr__rel$161
+ connect \wr__go \wr__go$162
+ connect \dest1_o \dest1_o$170
+ connect \cr_a_ok \cr_a_ok$174
+ connect \dest2_o \dest2_o$178
+ connect \xer_ca_ok \xer_ca_ok$181
+ connect \dest3_o \dest3_o$184
+ connect \go_die_i \go_die_i$220
+ connect \shadown_i \shadown_i$221
end
cell \ldst0 \ldst0
connect \ad__go \ad__go
connect \st__rel \st__rel
connect \rst \rst
connect \clk \clk
- connect \oper_i__insn_type \oper_i__insn_type$74
- connect \oper_i__imm_data__imm \oper_i__imm_data__imm$75
- connect \oper_i__imm_data__imm_ok \oper_i__imm_data__imm_ok$76
- connect \oper_i__zero_a \oper_i__zero_a$77
- connect \oper_i__is_32bit \oper_i__is_32bit$78
- connect \oper_i__is_signed \oper_i__is_signed$79
- connect \oper_i__data_len \oper_i__data_len$80
- connect \oper_i__byte_reverse \oper_i__byte_reverse$81
- connect \oper_i__sign_extend \oper_i__sign_extend$82
- connect \oper_i__update \oper_i__update
- connect \issue_i \issue_i$83
- connect \busy_o \busy_o$84
- connect \rdmaskn \rdmaskn$85
- connect \rd__rel \rd__rel$101
- connect \rd__go \rd__go$102
- connect \src1_i \src1_i$103
- connect \src2_i \src2_i$108
- connect \src3_i \src3_i$109
- connect \wr__rel \wr__rel$144
- connect \wr__go \wr__go$145
- connect \o \o$151
+ connect \oper_i__insn_type \oper_i__insn_type$86
+ connect \oper_i__imm_data__imm \oper_i__imm_data__imm$87
+ connect \oper_i__imm_data__imm_ok \oper_i__imm_data__imm_ok$88
+ connect \oper_i__zero_a \oper_i__zero_a$89
+ connect \oper_i__rc__rc \oper_i__rc__rc$90
+ connect \oper_i__rc__rc_ok \oper_i__rc__rc_ok$91
+ connect \oper_i__oe__oe \oper_i__oe__oe$92
+ connect \oper_i__oe__oe_ok \oper_i__oe__oe_ok$93
+ connect \oper_i__is_32bit \oper_i__is_32bit$94
+ connect \oper_i__is_signed \oper_i__is_signed$95
+ connect \oper_i__data_len \oper_i__data_len$96
+ connect \oper_i__byte_reverse \oper_i__byte_reverse
+ connect \oper_i__sign_extend \oper_i__sign_extend
+ connect \oper_i__ldst_mode \oper_i__ldst_mode
+ connect \issue_i \issue_i$97
+ connect \busy_o \busy_o$98
+ connect \rdmaskn \rdmaskn$99
+ connect \rd__rel \rd__rel$118
+ connect \rd__go \rd__go$119
+ connect \src1_i \src1_i$120
+ connect \src2_i \src2_i$126
+ connect \src3_i \src3_i$127
+ connect \wr__rel \wr__rel$163
+ connect \wr__go \wr__go$164
+ connect \o \o
connect \ea \ea
- connect \go_die_i \go_die_i$196
+ connect \go_die_i \go_die_i$222
connect \load_mem_o \load_mem_o
connect \stwd_mem_o \stwd_mem_o
- connect \shadown_i \shadown_i$197
+ connect \shadown_i \shadown_i$223
connect \ldst_port0_is_ld_i \ldst_port0_is_ld_i
connect \ldst_port0_is_st_i \ldst_port0_is_st_i
connect \ldst_port0_data_len \ldst_port0_data_len
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:251"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265"
wire width 4 $9
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:251"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265"
cell $pos $10
parameter \A_SIGNED 0
parameter \A_WIDTH 3
connect \A \ldst_port0_addr_i [2:0]
connect \Y $9
end
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:251"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265"
wire width 4 $11
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:251"
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265"
cell $pos $12
parameter \A_SIGNED 0
parameter \A_WIDTH 3
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "test_issuer.core.l0.l0.reset_l"
-module \reset_l$90
+module \reset_l$107
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "test_issuer.core.l0.l0"
-module \l0$89
+module \l0$106
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 \reset_l_r_reset
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
wire width 1 \reset_l_q_reset
- cell \reset_l$90 \reset_l
+ cell \reset_l$107 \reset_l
connect \rst \rst
connect \clk \clk
connect \s_reset \reset_l_s_reset
connect \m_valid_i \m_valid_i
connect \x_valid_i \x_valid_i
end
- cell \l0$89 \l0
+ cell \l0$106 \l0
connect \rst \rst
connect \clk \clk
connect \ldst_port0_is_ld_i \ldst_port0_is_ld_i
assign { \reg_31_src131__ren \reg_30_src130__ren \reg_29_src129__ren \reg_28_src128__ren \reg_27_src127__ren \reg_26_src126__ren \reg_25_src125__ren \reg_24_src124__ren \reg_23_src123__ren \reg_22_src122__ren \reg_21_src121__ren \reg_20_src120__ren \reg_19_src119__ren \reg_18_src118__ren \reg_17_src117__ren \reg_16_src116__ren \reg_15_src115__ren \reg_14_src114__ren \reg_13_src113__ren \reg_12_src112__ren \reg_11_src111__ren \reg_10_src110__ren \reg_9_src19__ren \reg_8_src18__ren \reg_7_src17__ren \reg_6_src16__ren \reg_5_src15__ren \reg_4_src14__ren \reg_3_src13__ren \reg_2_src12__ren \reg_1_src11__ren \reg_0_src10__ren } \src1__ren
sync init
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
wire width 64 $3
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
cell $or $4
parameter \A_SIGNED 0
parameter \A_WIDTH 64
connect \B \reg_1_src11__data_o
connect \Y $3
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
wire width 64 $5
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
cell $or $6
parameter \A_SIGNED 0
parameter \A_WIDTH 64
connect \B \reg_3_src13__data_o
connect \Y $5
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
wire width 64 $7
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
cell $or $8
parameter \A_SIGNED 0
parameter \A_WIDTH 64
connect \B $5
connect \Y $7
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
wire width 64 $9
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
cell $or $10
parameter \A_SIGNED 0
parameter \A_WIDTH 64
connect \B \reg_5_src15__data_o
connect \Y $9
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
wire width 64 $11
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
cell $or $12
parameter \A_SIGNED 0
parameter \A_WIDTH 64
connect \B \reg_7_src17__data_o
connect \Y $11
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
wire width 64 $13
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
cell $or $14
parameter \A_SIGNED 0
parameter \A_WIDTH 64
connect \B $11
connect \Y $13
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
wire width 64 $15
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
cell $or $16
parameter \A_SIGNED 0
parameter \A_WIDTH 64
connect \B $13
connect \Y $15
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
wire width 64 $17
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
cell $or $18
parameter \A_SIGNED 0
parameter \A_WIDTH 64
connect \B \reg_9_src19__data_o
connect \Y $17
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
wire width 64 $19
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
cell $or $20
parameter \A_SIGNED 0
parameter \A_WIDTH 64
connect \B \reg_11_src111__data_o
connect \Y $19
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
wire width 64 $21
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
cell $or $22
parameter \A_SIGNED 0
parameter \A_WIDTH 64
connect \B $19
connect \Y $21
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
wire width 64 $23
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
cell $or $24
parameter \A_SIGNED 0
parameter \A_WIDTH 64
connect \B \reg_13_src113__data_o
connect \Y $23
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
wire width 64 $25
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
cell $or $26
parameter \A_SIGNED 0
parameter \A_WIDTH 64
connect \B \reg_15_src115__data_o
connect \Y $25
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
wire width 64 $27
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
cell $or $28
parameter \A_SIGNED 0
parameter \A_WIDTH 64
connect \B $25
connect \Y $27
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
wire width 64 $29
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
cell $or $30
parameter \A_SIGNED 0
parameter \A_WIDTH 64
connect \B $27
connect \Y $29
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
wire width 64 $31
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
cell $or $32
parameter \A_SIGNED 0
parameter \A_WIDTH 64
connect \B $29
connect \Y $31
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
wire width 64 $33
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
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sync init
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connect \Y $119
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
wire width 64 $121
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
cell $or $122
parameter \A_SIGNED 0
parameter \A_WIDTH 64
connect \B $119
connect \Y $121
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
wire width 64 $123
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
cell $or $124
parameter \A_SIGNED 0
parameter \A_WIDTH 64
connect \B $121
connect \Y $123
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
wire width 64 $125
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
cell $or $126
parameter \A_SIGNED 0
parameter \A_WIDTH 64
assign { \reg_31_src331__ren \reg_30_src330__ren \reg_29_src329__ren \reg_28_src328__ren \reg_27_src327__ren \reg_26_src326__ren \reg_25_src325__ren \reg_24_src324__ren \reg_23_src323__ren \reg_22_src322__ren \reg_21_src321__ren \reg_20_src320__ren \reg_19_src319__ren \reg_18_src318__ren \reg_17_src317__ren \reg_16_src316__ren \reg_15_src315__ren \reg_14_src314__ren \reg_13_src313__ren \reg_12_src312__ren \reg_11_src311__ren \reg_10_src310__ren \reg_9_src39__ren \reg_8_src38__ren \reg_7_src37__ren \reg_6_src36__ren \reg_5_src35__ren \reg_4_src34__ren \reg_3_src33__ren \reg_2_src32__ren \reg_1_src31__ren \reg_0_src30__ren } \src3__ren
sync init
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
wire width 64 $127
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
cell $or $128
parameter \A_SIGNED 0
parameter \A_WIDTH 64
connect \B \reg_1_src31__data_o
connect \Y $127
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
wire width 64 $129
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
cell $or $130
parameter \A_SIGNED 0
parameter \A_WIDTH 64
connect \B \reg_3_src33__data_o
connect \Y $129
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
wire width 64 $131
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
cell $or $132
parameter \A_SIGNED 0
parameter \A_WIDTH 64
connect \B $129
connect \Y $131
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
wire width 64 $133
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
cell $or $134
parameter \A_SIGNED 0
parameter \A_WIDTH 64
connect \B \reg_5_src35__data_o
connect \Y $133
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
wire width 64 $135
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
cell $or $136
parameter \A_SIGNED 0
parameter \A_WIDTH 64
connect \B \reg_7_src37__data_o
connect \Y $135
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
wire width 64 $137
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
cell $or $138
parameter \A_SIGNED 0
parameter \A_WIDTH 64
connect \B $135
connect \Y $137
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
wire width 64 $139
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
cell $or $140
parameter \A_SIGNED 0
parameter \A_WIDTH 64
connect \B $137
connect \Y $139
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
wire width 64 $141
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
cell $or $142
parameter \A_SIGNED 0
parameter \A_WIDTH 64
connect \B \reg_9_src39__data_o
connect \Y $141
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
wire width 64 $143
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
cell $or $144
parameter \A_SIGNED 0
parameter \A_WIDTH 64
connect \B \reg_11_src311__data_o
connect \Y $143
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
wire width 64 $145
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
cell $or $146
parameter \A_SIGNED 0
parameter \A_WIDTH 64
connect \B $143
connect \Y $145
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
wire width 64 $147
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
cell $or $148
parameter \A_SIGNED 0
parameter \A_WIDTH 64
connect \B \reg_13_src313__data_o
connect \Y $147
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
wire width 64 $149
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
cell $or $150
parameter \A_SIGNED 0
parameter \A_WIDTH 64
connect \B \reg_15_src315__data_o
connect \Y $149
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
wire width 64 $151
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
cell $or $152
parameter \A_SIGNED 0
parameter \A_WIDTH 64
connect \B $149
connect \Y $151
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
wire width 64 $153
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
cell $or $154
parameter \A_SIGNED 0
parameter \A_WIDTH 64
connect \B $151
connect \Y $153
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
wire width 64 $155
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
cell $or $156
parameter \A_SIGNED 0
parameter \A_WIDTH 64
connect \B $153
connect \Y $155
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
wire width 64 $157
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
cell $or $158
parameter \A_SIGNED 0
parameter \A_WIDTH 64
connect \B \reg_17_src317__data_o
connect \Y $157
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
wire width 64 $159
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
cell $or $160
parameter \A_SIGNED 0
parameter \A_WIDTH 64
connect \B \reg_19_src319__data_o
connect \Y $159
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
wire width 64 $161
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
cell $or $162
parameter \A_SIGNED 0
parameter \A_WIDTH 64
connect \B $159
connect \Y $161
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
wire width 64 $163
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
cell $or $164
parameter \A_SIGNED 0
parameter \A_WIDTH 64
connect \B \reg_21_src321__data_o
connect \Y $163
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
wire width 64 $165
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
cell $or $166
parameter \A_SIGNED 0
parameter \A_WIDTH 64
connect \B \reg_23_src323__data_o
connect \Y $165
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
wire width 64 $167
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
cell $or $168
parameter \A_SIGNED 0
parameter \A_WIDTH 64
connect \B $165
connect \Y $167
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
wire width 64 $169
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
cell $or $170
parameter \A_SIGNED 0
parameter \A_WIDTH 64
connect \B $167
connect \Y $169
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
wire width 64 $171
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
cell $or $172
parameter \A_SIGNED 0
parameter \A_WIDTH 64
connect \B \reg_25_src325__data_o
connect \Y $171
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
wire width 64 $173
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
cell $or $174
parameter \A_SIGNED 0
parameter \A_WIDTH 64
connect \B \reg_27_src327__data_o
connect \Y $173
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
wire width 64 $175
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
cell $or $176
parameter \A_SIGNED 0
parameter \A_WIDTH 64
connect \B $173
connect \Y $175
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
wire width 64 $177
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
cell $or $178
parameter \A_SIGNED 0
parameter \A_WIDTH 64
connect \B \reg_29_src329__data_o
connect \Y $177
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
wire width 64 $179
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
cell $or $180
parameter \A_SIGNED 0
parameter \A_WIDTH 64
connect \B \reg_31_src331__data_o
connect \Y $179
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
wire width 64 $181
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
cell $or $182
parameter \A_SIGNED 0
parameter \A_WIDTH 64
connect \B $179
connect \Y $181
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
wire width 64 $183
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
cell $or $184
parameter \A_SIGNED 0
parameter \A_WIDTH 64
connect \B $181
connect \Y $183
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
wire width 64 $185
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
cell $or $186
parameter \A_SIGNED 0
parameter \A_WIDTH 64
connect \B $183
connect \Y $185
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
wire width 64 $187
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
cell $or $188
parameter \A_SIGNED 0
parameter \A_WIDTH 64
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "test_issuer.core.cr.reg_0"
-module \reg_0$91
+module \reg_0$108
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "test_issuer.core.cr.reg_1"
-module \reg_1$92
+module \reg_1$109
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "test_issuer.core.cr.reg_2"
-module \reg_2$93
+module \reg_2$110
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "test_issuer.core.cr.reg_3"
-module \reg_3$94
+module \reg_3$111
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "test_issuer.core.cr.reg_4"
-module \reg_4$95
+module \reg_4$112
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "test_issuer.core.cr.reg_5"
-module \reg_5$96
+module \reg_5$113
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "test_issuer.core.cr.reg_6"
-module \reg_6$97
+module \reg_6$114
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "test_issuer.core.cr.reg_7"
-module \reg_7$98
+module \reg_7$115
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 4 \reg_0_w0__data_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_0_w0__wen
- cell \reg_0$91 \reg_0
+ cell \reg_0$108 \reg_0
connect \rst \rst
connect \clk \clk
connect \src10__ren \reg_0_src10__ren
wire width 4 \reg_1_w1__data_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_1_w1__wen
- cell \reg_1$92 \reg_1
+ cell \reg_1$109 \reg_1
connect \rst \rst
connect \clk \clk
connect \src11__ren \reg_1_src11__ren
wire width 4 \reg_2_w2__data_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_2_w2__wen
- cell \reg_2$93 \reg_2
+ cell \reg_2$110 \reg_2
connect \rst \rst
connect \clk \clk
connect \src12__ren \reg_2_src12__ren
wire width 4 \reg_3_w3__data_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_3_w3__wen
- cell \reg_3$94 \reg_3
+ cell \reg_3$111 \reg_3
connect \rst \rst
connect \clk \clk
connect \src13__ren \reg_3_src13__ren
wire width 4 \reg_4_w4__data_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_4_w4__wen
- cell \reg_4$95 \reg_4
+ cell \reg_4$112 \reg_4
connect \rst \rst
connect \clk \clk
connect \src14__ren \reg_4_src14__ren
wire width 4 \reg_5_w5__data_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_5_w5__wen
- cell \reg_5$96 \reg_5
+ cell \reg_5$113 \reg_5
connect \rst \rst
connect \clk \clk
connect \src15__ren \reg_5_src15__ren
wire width 4 \reg_6_w6__data_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_6_w6__wen
- cell \reg_6$97 \reg_6
+ cell \reg_6$114 \reg_6
connect \rst \rst
connect \clk \clk
connect \src16__ren \reg_6_src16__ren
wire width 4 \reg_7_w7__data_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_7_w7__wen
- cell \reg_7$98 \reg_7
+ cell \reg_7$115 \reg_7
connect \rst \rst
connect \clk \clk
connect \src17__ren \reg_7_src17__ren
assign { \reg_7_src17__ren \reg_6_src16__ren \reg_5_src15__ren \reg_4_src14__ren \reg_3_src13__ren \reg_2_src12__ren \reg_1_src11__ren \reg_0_src10__ren } \src1__ren
sync init
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
wire width 4 $1
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
cell $or $2
parameter \A_SIGNED 0
parameter \A_WIDTH 4
connect \B \reg_1_src11__data_o
connect \Y $1
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
wire width 4 $3
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
cell $or $4
parameter \A_SIGNED 0
parameter \A_WIDTH 4
connect \B \reg_3_src13__data_o
connect \Y $3
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
wire width 4 $5
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
cell $or $6
parameter \A_SIGNED 0
parameter \A_WIDTH 4
connect \B $3
connect \Y $5
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
wire width 4 $7
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
cell $or $8
parameter \A_SIGNED 0
parameter \A_WIDTH 4
connect \B \reg_5_src15__data_o
connect \Y $7
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
wire width 4 $9
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
cell $or $10
parameter \A_SIGNED 0
parameter \A_WIDTH 4
connect \B \reg_7_src17__data_o
connect \Y $9
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
wire width 4 $11
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
cell $or $12
parameter \A_SIGNED 0
parameter \A_WIDTH 4
connect \B $9
connect \Y $11
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
wire width 4 $13
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
cell $or $14
parameter \A_SIGNED 0
parameter \A_WIDTH 4
assign { \reg_7_src27__ren \reg_6_src26__ren \reg_5_src25__ren \reg_4_src24__ren \reg_3_src23__ren \reg_2_src22__ren \reg_1_src21__ren \reg_0_src20__ren } \src2__ren
sync init
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
wire width 4 $15
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
cell $or $16
parameter \A_SIGNED 0
parameter \A_WIDTH 4
connect \B \reg_1_src21__data_o
connect \Y $15
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
wire width 4 $17
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
cell $or $18
parameter \A_SIGNED 0
parameter \A_WIDTH 4
connect \B \reg_3_src23__data_o
connect \Y $17
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
wire width 4 $19
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
cell $or $20
parameter \A_SIGNED 0
parameter \A_WIDTH 4
connect \B $17
connect \Y $19
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
wire width 4 $21
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
cell $or $22
parameter \A_SIGNED 0
parameter \A_WIDTH 4
connect \B \reg_5_src25__data_o
connect \Y $21
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
wire width 4 $23
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
cell $or $24
parameter \A_SIGNED 0
parameter \A_WIDTH 4
connect \B \reg_7_src27__data_o
connect \Y $23
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
wire width 4 $25
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
cell $or $26
parameter \A_SIGNED 0
parameter \A_WIDTH 4
connect \B $23
connect \Y $25
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
wire width 4 $27
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
cell $or $28
parameter \A_SIGNED 0
parameter \A_WIDTH 4
assign { \reg_7_src37__ren \reg_6_src36__ren \reg_5_src35__ren \reg_4_src34__ren \reg_3_src33__ren \reg_2_src32__ren \reg_1_src31__ren \reg_0_src30__ren } \src3__ren
sync init
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
wire width 4 $29
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
cell $or $30
parameter \A_SIGNED 0
parameter \A_WIDTH 4
connect \B \reg_1_src31__data_o
connect \Y $29
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
wire width 4 $31
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
cell $or $32
parameter \A_SIGNED 0
parameter \A_WIDTH 4
connect \B \reg_3_src33__data_o
connect \Y $31
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
wire width 4 $33
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
cell $or $34
parameter \A_SIGNED 0
parameter \A_WIDTH 4
connect \B $31
connect \Y $33
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
wire width 4 $35
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
cell $or $36
parameter \A_SIGNED 0
parameter \A_WIDTH 4
connect \B \reg_5_src35__data_o
connect \Y $35
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
wire width 4 $37
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
cell $or $38
parameter \A_SIGNED 0
parameter \A_WIDTH 4
connect \B \reg_7_src37__data_o
connect \Y $37
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
wire width 4 $39
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
cell $or $40
parameter \A_SIGNED 0
parameter \A_WIDTH 4
connect \B $37
connect \Y $39
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
wire width 4 $41
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
cell $or $42
parameter \A_SIGNED 0
parameter \A_WIDTH 4
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "test_issuer.core.xer.reg_0"
-module \reg_0$99
+module \reg_0$116
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "test_issuer.core.xer.reg_1"
-module \reg_1$100
+module \reg_1$117
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "test_issuer.core.xer.reg_2"
-module \reg_2$101
+module \reg_2$118
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 2 \reg_0_w0__data_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_0_w0__wen
- cell \reg_0$99 \reg_0
+ cell \reg_0$116 \reg_0
connect \rst \rst
connect \clk \clk
connect \src10__ren \reg_0_src10__ren
wire width 2 \reg_1_w1__data_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_1_w1__wen
- cell \reg_1$100 \reg_1
+ cell \reg_1$117 \reg_1
connect \rst \rst
connect \clk \clk
connect \src11__ren \reg_1_src11__ren
wire width 2 \reg_2_w2__data_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_2_w2__wen
- cell \reg_2$101 \reg_2
+ cell \reg_2$118 \reg_2
connect \rst \rst
connect \clk \clk
connect \src12__ren \reg_2_src12__ren
assign { \reg_2_src12__ren \reg_1_src11__ren \reg_0_src10__ren } \src1__ren
sync init
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
wire width 2 $5
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
cell $or $6
parameter \A_SIGNED 0
parameter \A_WIDTH 2
connect \B \reg_2_src12__data_o
connect \Y $5
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
wire width 2 $7
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
cell $or $8
parameter \A_SIGNED 0
parameter \A_WIDTH 2
assign { \reg_2_src22__ren \reg_1_src21__ren \reg_0_src20__ren } \src2__ren
sync init
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
wire width 2 $9
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
cell $or $10
parameter \A_SIGNED 0
parameter \A_WIDTH 2
connect \B \reg_2_src22__data_o
connect \Y $9
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
wire width 2 $11
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
cell $or $12
parameter \A_SIGNED 0
parameter \A_WIDTH 2
assign { \reg_2_src32__ren \reg_1_src31__ren \reg_0_src30__ren } \src3__ren
sync init
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
wire width 2 $13
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
cell $or $14
parameter \A_SIGNED 0
parameter \A_WIDTH 2
connect \B \reg_2_src32__data_o
connect \Y $13
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
wire width 2 $15
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
cell $or $16
parameter \A_SIGNED 0
parameter \A_WIDTH 2
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "test_issuer.core.fast.reg_0"
-module \reg_0$102
+module \reg_0$119
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 2 \src10__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 3 \src10__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 4 \src20__ren
+ wire width 1 input 2 \cia0__ren
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 5 \src20__data_o
+ wire width 64 output 3 \cia0__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 6 \src30__ren
+ wire width 1 input 4 \msr0__ren
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 7 \src30__data_o
+ wire width 64 output 5 \msr0__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 8 \src40__ren
+ wire width 1 input 6 \src10__ren
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 9 \src40__data_o
+ wire width 64 output 7 \src10__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 10 \d_rd10__ren
+ wire width 1 input 8 \src20__ren
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 11 \d_rd10__data_o
+ wire width 64 output 9 \src20__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 12 \nia0__wen
+ wire width 1 input 10 \nia0__wen
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 input 13 \nia0__data_i
+ wire width 64 input 11 \nia0__data_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 14 \dest20__wen
+ wire width 1 input 12 \dest20__wen
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 input 15 \dest20__data_i
+ wire width 64 input 13 \dest20__data_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 16 \dest30__wen
+ wire width 1 input 14 \dest30__wen
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 input 17 \dest30__data_i
+ wire width 64 input 15 \dest30__data_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 18 \dest40__wen
+ wire width 1 input 16 \dest40__wen
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 input 19 \dest40__data_i
+ wire width 64 input 17 \dest40__data_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 20 \d_wr10__wen
+ wire width 1 input 18 \d_wr10__wen
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 input 21 \d_wr10__data_i
+ wire width 64 input 19 \d_wr10__data_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \src10__ren
+ connect \A \cia0__ren
connect \B 1'1
connect \Y $1
end
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \src10__ren
+ connect \A \cia0__ren
connect \B 1'1
connect \Y $3
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
wire width 64 \reg$next
process $group_1
- assign \src10__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \cia0__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $3 }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { \nia0__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src10__data_o \nia0__data_i
+ assign \cia0__data_o \nia0__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest20__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src10__data_o \dest20__data_i
+ assign \cia0__data_o \dest20__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest30__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src10__data_o \dest30__data_i
+ assign \cia0__data_o \dest30__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest40__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src10__data_o \dest40__data_i
+ assign \cia0__data_o \dest40__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \d_wr10__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src10__data_o \d_wr10__data_i
+ assign \cia0__data_o \d_wr10__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $5 }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
- assign \src10__data_o \reg
+ assign \cia0__data_o \reg
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
- assign \src10__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \cia0__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
end
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \src20__ren
+ connect \A \msr0__ren
connect \B 1'1
connect \Y $8
end
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \src20__ren
+ connect \A \msr0__ren
connect \B 1'1
connect \Y $10
end
connect \Y $12
end
process $group_3
- assign \src20__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \msr0__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $10 }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { \nia0__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src20__data_o \nia0__data_i
+ assign \msr0__data_o \nia0__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest20__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src20__data_o \dest20__data_i
+ assign \msr0__data_o \dest20__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest30__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src20__data_o \dest30__data_i
+ assign \msr0__data_o \dest30__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest40__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src20__data_o \dest40__data_i
+ assign \msr0__data_o \dest40__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \d_wr10__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src20__data_o \d_wr10__data_i
+ assign \msr0__data_o \d_wr10__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $12 }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
- assign \src20__data_o \reg
+ assign \msr0__data_o \reg
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
- assign \src20__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \msr0__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
end
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \src30__ren
+ connect \A \src10__ren
connect \B 1'1
connect \Y $15
end
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \src30__ren
+ connect \A \src10__ren
connect \B 1'1
connect \Y $17
end
connect \Y $19
end
process $group_5
- assign \src30__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \src10__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $17 }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { \nia0__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src30__data_o \nia0__data_i
+ assign \src10__data_o \nia0__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest20__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src30__data_o \dest20__data_i
+ assign \src10__data_o \dest20__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest30__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src30__data_o \dest30__data_i
+ assign \src10__data_o \dest30__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest40__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src30__data_o \dest40__data_i
+ assign \src10__data_o \dest40__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \d_wr10__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src30__data_o \d_wr10__data_i
+ assign \src10__data_o \d_wr10__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $19 }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
- assign \src30__data_o \reg
+ assign \src10__data_o \reg
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
- assign \src30__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \src10__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
end
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \src40__ren
+ connect \A \src20__ren
connect \B 1'1
connect \Y $22
end
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \src40__ren
+ connect \A \src20__ren
connect \B 1'1
connect \Y $24
end
connect \Y $26
end
process $group_7
- assign \src40__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \src20__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $24 }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { \nia0__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src40__data_o \nia0__data_i
+ assign \src20__data_o \nia0__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest20__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src40__data_o \dest20__data_i
+ assign \src20__data_o \dest20__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest30__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src40__data_o \dest30__data_i
+ assign \src20__data_o \dest30__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest40__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src40__data_o \dest40__data_i
+ assign \src20__data_o \dest40__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \d_wr10__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src40__data_o \d_wr10__data_i
+ assign \src20__data_o \d_wr10__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $26 }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
- assign \src40__data_o \reg
+ assign \src20__data_o \reg
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
- assign \src40__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \src20__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
- wire width 1 \wr_detect$28
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $29
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $30
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \d_rd10__ren
- connect \B 1'1
- connect \Y $29
- end
process $group_8
- assign \wr_detect$28 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $29 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- assign \wr_detect$28 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \nia0__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$28 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest20__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$28 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest30__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$28 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest40__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$28 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \d_wr10__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$28 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $31
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $32
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \d_rd10__ren
- connect \B 1'1
- connect \Y $31
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- wire width 1 $33
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- cell $not $34
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \wr_detect$28
- connect \Y $33
- end
- process $group_9
- assign \d_rd10__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $31 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \nia0__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \d_rd10__data_o \nia0__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest20__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \d_rd10__data_o \dest20__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest30__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \d_rd10__data_o \dest30__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest40__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \d_rd10__data_o \dest40__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \d_wr10__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \d_rd10__data_o \d_wr10__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- switch { $33 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- case 1'1
- assign \d_rd10__data_o \reg
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- assign \d_rd10__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- sync init
- end
- process $group_10
assign \reg$next \reg
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \nia0__wen }
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "test_issuer.core.fast.reg_1"
-module \reg_1$103
+module \reg_1$120
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 2 \src11__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 3 \src11__data_o
+ wire width 1 input 2 \cia1__ren
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 4 \src21__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 5 \src21__data_o
+ wire width 64 output 3 \cia1__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 6 \src31__ren
+ wire width 1 input 4 \msr1__ren
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 7 \src31__data_o
+ wire width 64 output 5 \msr1__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 8 \src41__ren
+ wire width 1 input 6 \src11__ren
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 9 \src41__data_o
+ wire width 64 output 7 \src11__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 10 \d_rd11__ren
+ wire width 1 input 8 \src21__ren
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 11 \d_rd11__data_o
+ wire width 64 output 9 \src21__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 12 \nia1__wen
+ wire width 1 input 10 \nia1__wen
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 input 13 \nia1__data_i
+ wire width 64 input 11 \nia1__data_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 14 \dest21__wen
+ wire width 1 input 12 \dest21__wen
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 input 15 \dest21__data_i
+ wire width 64 input 13 \dest21__data_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 16 \dest31__wen
+ wire width 1 input 14 \dest31__wen
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 input 17 \dest31__data_i
+ wire width 64 input 15 \dest31__data_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 18 \dest41__wen
+ wire width 1 input 16 \dest41__wen
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 input 19 \dest41__data_i
+ wire width 64 input 17 \dest41__data_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 20 \d_wr11__wen
+ wire width 1 input 18 \d_wr11__wen
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 input 21 \d_wr11__data_i
+ wire width 64 input 19 \d_wr11__data_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \src11__ren
+ connect \A \cia1__ren
connect \B 1'1
connect \Y $1
end
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \src11__ren
+ connect \A \cia1__ren
connect \B 1'1
connect \Y $3
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
wire width 64 \reg$next
process $group_1
- assign \src11__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \cia1__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $3 }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { \nia1__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src11__data_o \nia1__data_i
+ assign \cia1__data_o \nia1__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest21__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src11__data_o \dest21__data_i
+ assign \cia1__data_o \dest21__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest31__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src11__data_o \dest31__data_i
+ assign \cia1__data_o \dest31__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest41__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src11__data_o \dest41__data_i
+ assign \cia1__data_o \dest41__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \d_wr11__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src11__data_o \d_wr11__data_i
+ assign \cia1__data_o \d_wr11__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $5 }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
- assign \src11__data_o \reg
+ assign \cia1__data_o \reg
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
- assign \src11__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \cia1__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
end
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \src21__ren
+ connect \A \msr1__ren
connect \B 1'1
connect \Y $8
end
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \src21__ren
+ connect \A \msr1__ren
connect \B 1'1
connect \Y $10
end
connect \Y $12
end
process $group_3
- assign \src21__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \msr1__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $10 }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { \nia1__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src21__data_o \nia1__data_i
+ assign \msr1__data_o \nia1__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest21__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src21__data_o \dest21__data_i
+ assign \msr1__data_o \dest21__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest31__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src21__data_o \dest31__data_i
+ assign \msr1__data_o \dest31__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest41__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src21__data_o \dest41__data_i
+ assign \msr1__data_o \dest41__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \d_wr11__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src21__data_o \d_wr11__data_i
+ assign \msr1__data_o \d_wr11__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $12 }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
- assign \src21__data_o \reg
+ assign \msr1__data_o \reg
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
- assign \src21__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \msr1__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
end
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \src31__ren
+ connect \A \src11__ren
connect \B 1'1
connect \Y $15
end
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \src31__ren
+ connect \A \src11__ren
connect \B 1'1
connect \Y $17
end
connect \Y $19
end
process $group_5
- assign \src31__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \src11__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $17 }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { \nia1__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src31__data_o \nia1__data_i
+ assign \src11__data_o \nia1__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest21__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src31__data_o \dest21__data_i
+ assign \src11__data_o \dest21__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest31__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src31__data_o \dest31__data_i
+ assign \src11__data_o \dest31__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest41__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src31__data_o \dest41__data_i
+ assign \src11__data_o \dest41__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \d_wr11__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src31__data_o \d_wr11__data_i
+ assign \src11__data_o \d_wr11__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $19 }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
- assign \src31__data_o \reg
+ assign \src11__data_o \reg
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
- assign \src31__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \src11__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
end
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \src41__ren
+ connect \A \src21__ren
connect \B 1'1
connect \Y $22
end
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \src41__ren
+ connect \A \src21__ren
connect \B 1'1
connect \Y $24
end
connect \Y $26
end
process $group_7
- assign \src41__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \src21__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $24 }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { \nia1__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src41__data_o \nia1__data_i
+ assign \src21__data_o \nia1__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest21__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src41__data_o \dest21__data_i
+ assign \src21__data_o \dest21__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest31__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src41__data_o \dest31__data_i
+ assign \src21__data_o \dest31__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest41__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src41__data_o \dest41__data_i
+ assign \src21__data_o \dest41__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \d_wr11__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src41__data_o \d_wr11__data_i
+ assign \src21__data_o \d_wr11__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $26 }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
- assign \src41__data_o \reg
+ assign \src21__data_o \reg
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
- assign \src41__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \src21__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
- wire width 1 \wr_detect$28
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $29
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $30
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \d_rd11__ren
- connect \B 1'1
- connect \Y $29
- end
process $group_8
- assign \wr_detect$28 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $29 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- assign \wr_detect$28 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \nia1__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$28 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest21__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$28 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest31__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$28 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest41__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$28 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \d_wr11__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$28 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $31
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $32
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \d_rd11__ren
- connect \B 1'1
- connect \Y $31
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- wire width 1 $33
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- cell $not $34
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \wr_detect$28
- connect \Y $33
- end
- process $group_9
- assign \d_rd11__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $31 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \nia1__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \d_rd11__data_o \nia1__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest21__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \d_rd11__data_o \dest21__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest31__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \d_rd11__data_o \dest31__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest41__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \d_rd11__data_o \dest41__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \d_wr11__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \d_rd11__data_o \d_wr11__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- switch { $33 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- case 1'1
- assign \d_rd11__data_o \reg
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- assign \d_rd11__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- sync init
- end
- process $group_10
assign \reg$next \reg
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \nia1__wen }
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "test_issuer.core.fast.reg_2"
-module \reg_2$104
+module \reg_2$121
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 2 \src12__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 3 \src12__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 4 \src22__ren
+ wire width 1 input 2 \cia2__ren
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 5 \src22__data_o
+ wire width 64 output 3 \cia2__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 6 \src32__ren
+ wire width 1 input 4 \msr2__ren
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 7 \src32__data_o
+ wire width 64 output 5 \msr2__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 8 \src42__ren
+ wire width 1 input 6 \src12__ren
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 9 \src42__data_o
+ wire width 64 output 7 \src12__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 10 \d_rd12__ren
+ wire width 1 input 8 \src22__ren
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 11 \d_rd12__data_o
+ wire width 64 output 9 \src22__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 12 \nia2__wen
+ wire width 1 input 10 \nia2__wen
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 input 13 \nia2__data_i
+ wire width 64 input 11 \nia2__data_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 14 \dest22__wen
+ wire width 1 input 12 \dest22__wen
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 input 15 \dest22__data_i
+ wire width 64 input 13 \dest22__data_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 16 \dest32__wen
+ wire width 1 input 14 \dest32__wen
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 input 17 \dest32__data_i
+ wire width 64 input 15 \dest32__data_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 18 \dest42__wen
+ wire width 1 input 16 \dest42__wen
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 input 19 \dest42__data_i
+ wire width 64 input 17 \dest42__data_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 20 \d_wr12__wen
+ wire width 1 input 18 \d_wr12__wen
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 input 21 \d_wr12__data_i
+ wire width 64 input 19 \d_wr12__data_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \src12__ren
+ connect \A \cia2__ren
connect \B 1'1
connect \Y $1
end
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \src12__ren
+ connect \A \cia2__ren
connect \B 1'1
connect \Y $3
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
wire width 64 \reg$next
process $group_1
- assign \src12__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \cia2__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $3 }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { \nia2__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src12__data_o \nia2__data_i
+ assign \cia2__data_o \nia2__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest22__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src12__data_o \dest22__data_i
+ assign \cia2__data_o \dest22__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest32__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src12__data_o \dest32__data_i
+ assign \cia2__data_o \dest32__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest42__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src12__data_o \dest42__data_i
+ assign \cia2__data_o \dest42__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \d_wr12__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src12__data_o \d_wr12__data_i
+ assign \cia2__data_o \d_wr12__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $5 }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
- assign \src12__data_o \reg
+ assign \cia2__data_o \reg
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
- assign \src12__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \cia2__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
end
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \src22__ren
+ connect \A \msr2__ren
connect \B 1'1
connect \Y $8
end
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \src22__ren
+ connect \A \msr2__ren
connect \B 1'1
connect \Y $10
end
connect \Y $12
end
process $group_3
- assign \src22__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \msr2__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $10 }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { \nia2__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src22__data_o \nia2__data_i
+ assign \msr2__data_o \nia2__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest22__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src22__data_o \dest22__data_i
+ assign \msr2__data_o \dest22__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest32__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src22__data_o \dest32__data_i
+ assign \msr2__data_o \dest32__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest42__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src22__data_o \dest42__data_i
+ assign \msr2__data_o \dest42__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \d_wr12__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src22__data_o \d_wr12__data_i
+ assign \msr2__data_o \d_wr12__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $12 }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
- assign \src22__data_o \reg
+ assign \msr2__data_o \reg
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
- assign \src22__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \msr2__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
end
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \src32__ren
+ connect \A \src12__ren
connect \B 1'1
connect \Y $15
end
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \src32__ren
+ connect \A \src12__ren
connect \B 1'1
connect \Y $17
end
connect \Y $19
end
process $group_5
- assign \src32__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \src12__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $17 }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { \nia2__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src32__data_o \nia2__data_i
+ assign \src12__data_o \nia2__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest22__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src32__data_o \dest22__data_i
+ assign \src12__data_o \dest22__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest32__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src32__data_o \dest32__data_i
+ assign \src12__data_o \dest32__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest42__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src32__data_o \dest42__data_i
+ assign \src12__data_o \dest42__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \d_wr12__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src32__data_o \d_wr12__data_i
+ assign \src12__data_o \d_wr12__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $19 }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
- assign \src32__data_o \reg
+ assign \src12__data_o \reg
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
- assign \src32__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \src12__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
end
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \src42__ren
+ connect \A \src22__ren
connect \B 1'1
connect \Y $22
end
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \src42__ren
+ connect \A \src22__ren
connect \B 1'1
connect \Y $24
end
connect \Y $26
end
process $group_7
- assign \src42__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \src22__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $24 }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { \nia2__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src42__data_o \nia2__data_i
+ assign \src22__data_o \nia2__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest22__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src42__data_o \dest22__data_i
+ assign \src22__data_o \dest22__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest32__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src42__data_o \dest32__data_i
+ assign \src22__data_o \dest32__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest42__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src42__data_o \dest42__data_i
+ assign \src22__data_o \dest42__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \d_wr12__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src42__data_o \d_wr12__data_i
+ assign \src22__data_o \d_wr12__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $26 }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
- assign \src42__data_o \reg
+ assign \src22__data_o \reg
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
- assign \src42__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \src22__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
- wire width 1 \wr_detect$28
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $29
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $30
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \d_rd12__ren
- connect \B 1'1
- connect \Y $29
- end
process $group_8
- assign \wr_detect$28 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $29 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- assign \wr_detect$28 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \nia2__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$28 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest22__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$28 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest32__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$28 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest42__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$28 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \d_wr12__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$28 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $31
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $32
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \d_rd12__ren
- connect \B 1'1
- connect \Y $31
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- wire width 1 $33
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- cell $not $34
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \wr_detect$28
- connect \Y $33
- end
- process $group_9
- assign \d_rd12__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $31 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \nia2__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \d_rd12__data_o \nia2__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest22__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \d_rd12__data_o \dest22__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest32__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \d_rd12__data_o \dest32__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest42__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \d_rd12__data_o \dest42__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \d_wr12__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \d_rd12__data_o \d_wr12__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- switch { $33 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- case 1'1
- assign \d_rd12__data_o \reg
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- assign \d_rd12__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- sync init
- end
- process $group_10
assign \reg$next \reg
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \nia2__wen }
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "test_issuer.core.fast.reg_3"
-module \reg_3$105
+module \reg_3$122
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 2 \src13__ren
+ wire width 1 input 2 \cia3__ren
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 3 \src13__data_o
+ wire width 64 output 3 \cia3__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 4 \src23__ren
+ wire width 1 input 4 \msr3__ren
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 5 \src23__data_o
+ wire width 64 output 5 \msr3__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 6 \src33__ren
+ wire width 1 input 6 \src13__ren
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 7 \src33__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 8 \src43__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 9 \src43__data_o
+ wire width 64 output 7 \src13__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 10 \d_rd13__ren
+ wire width 1 input 8 \src23__ren
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 11 \d_rd13__data_o
+ wire width 64 output 9 \src23__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 12 \nia3__wen
+ wire width 1 input 10 \nia3__wen
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 input 13 \nia3__data_i
+ wire width 64 input 11 \nia3__data_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 14 \dest23__wen
+ wire width 1 input 12 \dest23__wen
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 input 15 \dest23__data_i
+ wire width 64 input 13 \dest23__data_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 16 \dest33__wen
+ wire width 1 input 14 \dest33__wen
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 input 17 \dest33__data_i
+ wire width 64 input 15 \dest33__data_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 18 \dest43__wen
+ wire width 1 input 16 \dest43__wen
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 input 19 \dest43__data_i
+ wire width 64 input 17 \dest43__data_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 20 \d_wr13__wen
+ wire width 1 input 18 \d_wr13__wen
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 input 21 \d_wr13__data_i
+ wire width 64 input 19 \d_wr13__data_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \src13__ren
+ connect \A \cia3__ren
connect \B 1'1
connect \Y $1
end
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \src13__ren
+ connect \A \cia3__ren
connect \B 1'1
connect \Y $3
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
wire width 64 \reg$next
process $group_1
- assign \src13__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \cia3__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $3 }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { \nia3__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src13__data_o \nia3__data_i
+ assign \cia3__data_o \nia3__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest23__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src13__data_o \dest23__data_i
+ assign \cia3__data_o \dest23__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest33__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src13__data_o \dest33__data_i
+ assign \cia3__data_o \dest33__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest43__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src13__data_o \dest43__data_i
+ assign \cia3__data_o \dest43__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \d_wr13__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src13__data_o \d_wr13__data_i
+ assign \cia3__data_o \d_wr13__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $5 }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
- assign \src13__data_o \reg
+ assign \cia3__data_o \reg
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
- assign \src13__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \cia3__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
end
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \src23__ren
+ connect \A \msr3__ren
connect \B 1'1
connect \Y $8
end
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \src23__ren
+ connect \A \msr3__ren
connect \B 1'1
connect \Y $10
end
connect \Y $12
end
process $group_3
- assign \src23__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \msr3__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $10 }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { \nia3__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src23__data_o \nia3__data_i
+ assign \msr3__data_o \nia3__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest23__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src23__data_o \dest23__data_i
+ assign \msr3__data_o \dest23__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest33__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src23__data_o \dest33__data_i
+ assign \msr3__data_o \dest33__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest43__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src23__data_o \dest43__data_i
+ assign \msr3__data_o \dest43__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \d_wr13__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src23__data_o \d_wr13__data_i
+ assign \msr3__data_o \d_wr13__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $12 }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
- assign \src23__data_o \reg
+ assign \msr3__data_o \reg
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
- assign \src23__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \msr3__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
end
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \src33__ren
+ connect \A \src13__ren
connect \B 1'1
connect \Y $15
end
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \src33__ren
+ connect \A \src13__ren
connect \B 1'1
connect \Y $17
end
connect \Y $19
end
process $group_5
- assign \src33__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \src13__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $17 }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { \nia3__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src33__data_o \nia3__data_i
+ assign \src13__data_o \nia3__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest23__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src33__data_o \dest23__data_i
+ assign \src13__data_o \dest23__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest33__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src33__data_o \dest33__data_i
+ assign \src13__data_o \dest33__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest43__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src33__data_o \dest43__data_i
+ assign \src13__data_o \dest43__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \d_wr13__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src33__data_o \d_wr13__data_i
+ assign \src13__data_o \d_wr13__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $19 }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
- assign \src33__data_o \reg
+ assign \src13__data_o \reg
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
- assign \src33__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \src13__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
end
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \src43__ren
+ connect \A \src23__ren
connect \B 1'1
connect \Y $22
end
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \src43__ren
+ connect \A \src23__ren
connect \B 1'1
connect \Y $24
end
connect \Y $26
end
process $group_7
- assign \src43__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \src23__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $24 }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { \nia3__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src43__data_o \nia3__data_i
+ assign \src23__data_o \nia3__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest23__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src43__data_o \dest23__data_i
+ assign \src23__data_o \dest23__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest33__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src43__data_o \dest33__data_i
+ assign \src23__data_o \dest33__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest43__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src43__data_o \dest43__data_i
+ assign \src23__data_o \dest43__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \d_wr13__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src43__data_o \d_wr13__data_i
+ assign \src23__data_o \d_wr13__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $26 }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
- assign \src43__data_o \reg
+ assign \src23__data_o \reg
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
- assign \src43__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \src23__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
- wire width 1 \wr_detect$28
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $29
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $30
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \d_rd13__ren
- connect \B 1'1
- connect \Y $29
- end
process $group_8
- assign \wr_detect$28 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $29 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- assign \wr_detect$28 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \nia3__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$28 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest23__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$28 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest33__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$28 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest43__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$28 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \d_wr13__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$28 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $31
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $32
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \d_rd13__ren
- connect \B 1'1
- connect \Y $31
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- wire width 1 $33
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- cell $not $34
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \wr_detect$28
- connect \Y $33
- end
- process $group_9
- assign \d_rd13__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $31 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \nia3__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \d_rd13__data_o \nia3__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest23__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \d_rd13__data_o \dest23__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest33__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \d_rd13__data_o \dest33__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest43__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \d_rd13__data_o \dest43__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \d_wr13__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \d_rd13__data_o \d_wr13__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- switch { $33 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- case 1'1
- assign \d_rd13__data_o \reg
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- assign \d_rd13__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- sync init
- end
- process $group_10
assign \reg$next \reg
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \nia3__wen }
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "test_issuer.core.fast.reg_4"
-module \reg_4$106
+module \reg_4$123
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 2 \src14__ren
+ wire width 1 input 2 \cia4__ren
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 3 \src14__data_o
+ wire width 64 output 3 \cia4__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 4 \src24__ren
+ wire width 1 input 4 \msr4__ren
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 5 \src24__data_o
+ wire width 64 output 5 \msr4__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 6 \src34__ren
+ wire width 1 input 6 \src14__ren
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 7 \src34__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 8 \src44__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 9 \src44__data_o
+ wire width 64 output 7 \src14__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 10 \d_rd14__ren
+ wire width 1 input 8 \src24__ren
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 11 \d_rd14__data_o
+ wire width 64 output 9 \src24__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 12 \nia4__wen
+ wire width 1 input 10 \nia4__wen
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 input 13 \nia4__data_i
+ wire width 64 input 11 \nia4__data_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 14 \dest24__wen
+ wire width 1 input 12 \dest24__wen
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 input 15 \dest24__data_i
+ wire width 64 input 13 \dest24__data_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 16 \dest34__wen
+ wire width 1 input 14 \dest34__wen
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 input 17 \dest34__data_i
+ wire width 64 input 15 \dest34__data_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 18 \dest44__wen
+ wire width 1 input 16 \dest44__wen
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 input 19 \dest44__data_i
+ wire width 64 input 17 \dest44__data_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 20 \d_wr14__wen
+ wire width 1 input 18 \d_wr14__wen
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 input 21 \d_wr14__data_i
+ wire width 64 input 19 \d_wr14__data_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \src14__ren
+ connect \A \cia4__ren
connect \B 1'1
connect \Y $1
end
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \src14__ren
+ connect \A \cia4__ren
connect \B 1'1
connect \Y $3
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
wire width 64 \reg$next
process $group_1
- assign \src14__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \cia4__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $3 }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { \nia4__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src14__data_o \nia4__data_i
+ assign \cia4__data_o \nia4__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest24__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src14__data_o \dest24__data_i
+ assign \cia4__data_o \dest24__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest34__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src14__data_o \dest34__data_i
+ assign \cia4__data_o \dest34__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest44__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src14__data_o \dest44__data_i
+ assign \cia4__data_o \dest44__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \d_wr14__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src14__data_o \d_wr14__data_i
+ assign \cia4__data_o \d_wr14__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $5 }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
- assign \src14__data_o \reg
+ assign \cia4__data_o \reg
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
- assign \src14__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \cia4__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
end
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \src24__ren
+ connect \A \msr4__ren
connect \B 1'1
connect \Y $8
end
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \src24__ren
+ connect \A \msr4__ren
connect \B 1'1
connect \Y $10
end
connect \Y $12
end
process $group_3
- assign \src24__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \msr4__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $10 }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { \nia4__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src24__data_o \nia4__data_i
+ assign \msr4__data_o \nia4__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest24__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src24__data_o \dest24__data_i
+ assign \msr4__data_o \dest24__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest34__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src24__data_o \dest34__data_i
+ assign \msr4__data_o \dest34__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest44__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src24__data_o \dest44__data_i
+ assign \msr4__data_o \dest44__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \d_wr14__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src24__data_o \d_wr14__data_i
+ assign \msr4__data_o \d_wr14__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $12 }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
- assign \src24__data_o \reg
+ assign \msr4__data_o \reg
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
- assign \src24__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \msr4__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
end
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \src34__ren
+ connect \A \src14__ren
connect \B 1'1
connect \Y $15
end
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \src34__ren
+ connect \A \src14__ren
connect \B 1'1
connect \Y $17
end
connect \Y $19
end
process $group_5
- assign \src34__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \src14__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $17 }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { \nia4__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src34__data_o \nia4__data_i
+ assign \src14__data_o \nia4__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest24__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src34__data_o \dest24__data_i
+ assign \src14__data_o \dest24__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest34__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src34__data_o \dest34__data_i
+ assign \src14__data_o \dest34__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest44__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src34__data_o \dest44__data_i
+ assign \src14__data_o \dest44__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \d_wr14__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src34__data_o \d_wr14__data_i
+ assign \src14__data_o \d_wr14__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $19 }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
- assign \src34__data_o \reg
+ assign \src14__data_o \reg
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
- assign \src34__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \src14__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
end
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \src44__ren
+ connect \A \src24__ren
connect \B 1'1
connect \Y $22
end
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \src44__ren
+ connect \A \src24__ren
connect \B 1'1
connect \Y $24
end
connect \Y $26
end
process $group_7
- assign \src44__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \src24__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $24 }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { \nia4__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src44__data_o \nia4__data_i
+ assign \src24__data_o \nia4__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest24__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src44__data_o \dest24__data_i
+ assign \src24__data_o \dest24__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest34__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src44__data_o \dest34__data_i
+ assign \src24__data_o \dest34__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest44__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src44__data_o \dest44__data_i
+ assign \src24__data_o \dest44__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \d_wr14__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src44__data_o \d_wr14__data_i
+ assign \src24__data_o \d_wr14__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $26 }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
- assign \src44__data_o \reg
+ assign \src24__data_o \reg
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
- assign \src44__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \src24__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
- wire width 1 \wr_detect$28
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $29
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $30
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \d_rd14__ren
- connect \B 1'1
- connect \Y $29
- end
process $group_8
- assign \wr_detect$28 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $29 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- assign \wr_detect$28 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \nia4__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$28 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest24__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$28 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest34__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$28 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest44__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$28 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \d_wr14__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$28 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $31
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $32
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \d_rd14__ren
- connect \B 1'1
- connect \Y $31
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- wire width 1 $33
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- cell $not $34
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \wr_detect$28
- connect \Y $33
- end
- process $group_9
- assign \d_rd14__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $31 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \nia4__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \d_rd14__data_o \nia4__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest24__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \d_rd14__data_o \dest24__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest34__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \d_rd14__data_o \dest34__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest44__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \d_rd14__data_o \dest44__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \d_wr14__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \d_rd14__data_o \d_wr14__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- switch { $33 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- case 1'1
- assign \d_rd14__data_o \reg
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- assign \d_rd14__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- sync init
- end
- process $group_10
assign \reg$next \reg
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \nia4__wen }
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "test_issuer.core.fast.reg_5"
-module \reg_5$107
+module \reg_5$124
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 2 \src15__ren
+ wire width 1 input 2 \cia5__ren
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 3 \src15__data_o
+ wire width 64 output 3 \cia5__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 4 \src25__ren
+ wire width 1 input 4 \msr5__ren
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 5 \src25__data_o
+ wire width 64 output 5 \msr5__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 6 \src35__ren
+ wire width 1 input 6 \src15__ren
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 7 \src35__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 8 \src45__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 9 \src45__data_o
+ wire width 64 output 7 \src15__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 10 \d_rd15__ren
+ wire width 1 input 8 \src25__ren
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 11 \d_rd15__data_o
+ wire width 64 output 9 \src25__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 12 \nia5__wen
+ wire width 1 input 10 \nia5__wen
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 input 13 \nia5__data_i
+ wire width 64 input 11 \nia5__data_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 14 \dest25__wen
+ wire width 1 input 12 \dest25__wen
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 input 15 \dest25__data_i
+ wire width 64 input 13 \dest25__data_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 16 \dest35__wen
+ wire width 1 input 14 \dest35__wen
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 input 17 \dest35__data_i
+ wire width 64 input 15 \dest35__data_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 18 \dest45__wen
+ wire width 1 input 16 \dest45__wen
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 input 19 \dest45__data_i
+ wire width 64 input 17 \dest45__data_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 20 \d_wr15__wen
+ wire width 1 input 18 \d_wr15__wen
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 input 21 \d_wr15__data_i
+ wire width 64 input 19 \d_wr15__data_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \src15__ren
+ connect \A \cia5__ren
connect \B 1'1
connect \Y $1
end
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \src15__ren
+ connect \A \cia5__ren
connect \B 1'1
connect \Y $3
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
wire width 64 \reg$next
process $group_1
- assign \src15__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \cia5__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $3 }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { \nia5__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src15__data_o \nia5__data_i
+ assign \cia5__data_o \nia5__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest25__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src15__data_o \dest25__data_i
+ assign \cia5__data_o \dest25__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest35__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src15__data_o \dest35__data_i
+ assign \cia5__data_o \dest35__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest45__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src15__data_o \dest45__data_i
+ assign \cia5__data_o \dest45__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \d_wr15__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src15__data_o \d_wr15__data_i
+ assign \cia5__data_o \d_wr15__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $5 }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
- assign \src15__data_o \reg
+ assign \cia5__data_o \reg
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
- assign \src15__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \cia5__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
end
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \src25__ren
+ connect \A \msr5__ren
connect \B 1'1
connect \Y $8
end
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \src25__ren
+ connect \A \msr5__ren
connect \B 1'1
connect \Y $10
end
connect \Y $12
end
process $group_3
- assign \src25__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \msr5__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $10 }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { \nia5__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src25__data_o \nia5__data_i
+ assign \msr5__data_o \nia5__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest25__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src25__data_o \dest25__data_i
+ assign \msr5__data_o \dest25__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest35__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src25__data_o \dest35__data_i
+ assign \msr5__data_o \dest35__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest45__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src25__data_o \dest45__data_i
+ assign \msr5__data_o \dest45__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \d_wr15__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src25__data_o \d_wr15__data_i
+ assign \msr5__data_o \d_wr15__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $12 }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
- assign \src25__data_o \reg
+ assign \msr5__data_o \reg
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
- assign \src25__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \msr5__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
end
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \src35__ren
+ connect \A \src15__ren
connect \B 1'1
connect \Y $15
end
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \src35__ren
+ connect \A \src15__ren
connect \B 1'1
connect \Y $17
end
connect \Y $19
end
process $group_5
- assign \src35__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \src15__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $17 }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { \nia5__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src35__data_o \nia5__data_i
+ assign \src15__data_o \nia5__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest25__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src35__data_o \dest25__data_i
+ assign \src15__data_o \dest25__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest35__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src35__data_o \dest35__data_i
+ assign \src15__data_o \dest35__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest45__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src35__data_o \dest45__data_i
+ assign \src15__data_o \dest45__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \d_wr15__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src35__data_o \d_wr15__data_i
+ assign \src15__data_o \d_wr15__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $19 }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
- assign \src35__data_o \reg
+ assign \src15__data_o \reg
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
- assign \src35__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \src15__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
end
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \src45__ren
+ connect \A \src25__ren
connect \B 1'1
connect \Y $22
end
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \src45__ren
+ connect \A \src25__ren
connect \B 1'1
connect \Y $24
end
connect \Y $26
end
process $group_7
- assign \src45__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \src25__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $24 }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { \nia5__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src45__data_o \nia5__data_i
+ assign \src25__data_o \nia5__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest25__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src45__data_o \dest25__data_i
+ assign \src25__data_o \dest25__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest35__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src45__data_o \dest35__data_i
+ assign \src25__data_o \dest35__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest45__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src45__data_o \dest45__data_i
+ assign \src25__data_o \dest45__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \d_wr15__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src45__data_o \d_wr15__data_i
+ assign \src25__data_o \d_wr15__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $26 }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
- assign \src45__data_o \reg
+ assign \src25__data_o \reg
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
- assign \src45__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \src25__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
- wire width 1 \wr_detect$28
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $29
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $30
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \d_rd15__ren
- connect \B 1'1
- connect \Y $29
- end
process $group_8
- assign \wr_detect$28 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $29 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- assign \wr_detect$28 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \nia5__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$28 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest25__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$28 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest35__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$28 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest45__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$28 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \d_wr15__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$28 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $31
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $32
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \d_rd15__ren
- connect \B 1'1
- connect \Y $31
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- wire width 1 $33
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- cell $not $34
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \wr_detect$28
- connect \Y $33
- end
- process $group_9
- assign \d_rd15__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $31 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \nia5__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \d_rd15__data_o \nia5__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest25__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \d_rd15__data_o \dest25__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest35__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \d_rd15__data_o \dest35__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest45__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \d_rd15__data_o \dest45__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \d_wr15__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \d_rd15__data_o \d_wr15__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- switch { $33 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- case 1'1
- assign \d_rd15__data_o \reg
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- assign \d_rd15__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- sync init
- end
- process $group_10
assign \reg$next \reg
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \nia5__wen }
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "test_issuer.core.fast.reg_6"
-module \reg_6$108
+module \reg_6$125
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 2 \src16__ren
+ wire width 1 input 2 \cia6__ren
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 3 \src16__data_o
+ wire width 64 output 3 \cia6__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 4 \src26__ren
+ wire width 1 input 4 \msr6__ren
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 5 \src26__data_o
+ wire width 64 output 5 \msr6__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 6 \src36__ren
+ wire width 1 input 6 \src16__ren
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 7 \src36__data_o
+ wire width 64 output 7 \src16__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 8 \src46__ren
+ wire width 1 input 8 \src26__ren
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 9 \src46__data_o
+ wire width 64 output 9 \src26__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 10 \d_rd16__ren
+ wire width 1 input 10 \nia6__wen
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 11 \d_rd16__data_o
+ wire width 64 input 11 \nia6__data_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 12 \nia6__wen
+ wire width 1 input 12 \dest26__wen
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 input 13 \nia6__data_i
+ wire width 64 input 13 \dest26__data_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 14 \dest26__wen
+ wire width 1 input 14 \dest36__wen
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 input 15 \dest26__data_i
+ wire width 64 input 15 \dest36__data_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 16 \dest36__wen
+ wire width 1 input 16 \dest46__wen
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 input 17 \dest36__data_i
+ wire width 64 input 17 \dest46__data_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 18 \dest46__wen
+ wire width 1 input 18 \d_wr16__wen
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 input 19 \dest46__data_i
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 20 \d_wr16__wen
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 input 21 \d_wr16__data_i
+ wire width 64 input 19 \d_wr16__data_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \src16__ren
+ connect \A \cia6__ren
connect \B 1'1
connect \Y $1
end
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \src16__ren
+ connect \A \cia6__ren
connect \B 1'1
connect \Y $3
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
wire width 64 \reg$next
process $group_1
- assign \src16__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \cia6__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $3 }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { \nia6__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src16__data_o \nia6__data_i
+ assign \cia6__data_o \nia6__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest26__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src16__data_o \dest26__data_i
+ assign \cia6__data_o \dest26__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest36__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src16__data_o \dest36__data_i
+ assign \cia6__data_o \dest36__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest46__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src16__data_o \dest46__data_i
+ assign \cia6__data_o \dest46__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \d_wr16__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src16__data_o \d_wr16__data_i
+ assign \cia6__data_o \d_wr16__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $5 }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
- assign \src16__data_o \reg
+ assign \cia6__data_o \reg
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
- assign \src16__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \cia6__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
end
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \src26__ren
+ connect \A \msr6__ren
connect \B 1'1
connect \Y $8
end
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \src26__ren
+ connect \A \msr6__ren
connect \B 1'1
connect \Y $10
end
connect \Y $12
end
process $group_3
- assign \src26__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \msr6__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $10 }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { \nia6__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src26__data_o \nia6__data_i
+ assign \msr6__data_o \nia6__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest26__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src26__data_o \dest26__data_i
+ assign \msr6__data_o \dest26__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest36__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src26__data_o \dest36__data_i
+ assign \msr6__data_o \dest36__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest46__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src26__data_o \dest46__data_i
+ assign \msr6__data_o \dest46__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \d_wr16__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src26__data_o \d_wr16__data_i
+ assign \msr6__data_o \d_wr16__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $12 }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
- assign \src26__data_o \reg
+ assign \msr6__data_o \reg
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
- assign \src26__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \msr6__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
end
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \src36__ren
+ connect \A \src16__ren
connect \B 1'1
connect \Y $15
end
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \src36__ren
+ connect \A \src16__ren
connect \B 1'1
connect \Y $17
end
connect \Y $19
end
process $group_5
- assign \src36__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \src16__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $17 }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { \nia6__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src36__data_o \nia6__data_i
+ assign \src16__data_o \nia6__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest26__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src36__data_o \dest26__data_i
+ assign \src16__data_o \dest26__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest36__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src36__data_o \dest36__data_i
+ assign \src16__data_o \dest36__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest46__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src36__data_o \dest46__data_i
+ assign \src16__data_o \dest46__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \d_wr16__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src36__data_o \d_wr16__data_i
+ assign \src16__data_o \d_wr16__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $19 }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
- assign \src36__data_o \reg
+ assign \src16__data_o \reg
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
- assign \src36__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \src16__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
end
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \src46__ren
+ connect \A \src26__ren
connect \B 1'1
connect \Y $22
end
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \src46__ren
+ connect \A \src26__ren
connect \B 1'1
connect \Y $24
end
connect \Y $26
end
process $group_7
- assign \src46__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \src26__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $24 }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { \nia6__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src46__data_o \nia6__data_i
+ assign \src26__data_o \nia6__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest26__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src46__data_o \dest26__data_i
+ assign \src26__data_o \dest26__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest36__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src46__data_o \dest36__data_i
+ assign \src26__data_o \dest36__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest46__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src46__data_o \dest46__data_i
+ assign \src26__data_o \dest46__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \d_wr16__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src46__data_o \d_wr16__data_i
+ assign \src26__data_o \d_wr16__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $26 }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
- assign \src46__data_o \reg
+ assign \src26__data_o \reg
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
- assign \src46__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \src26__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
- wire width 1 \wr_detect$28
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $29
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $30
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \d_rd16__ren
- connect \B 1'1
- connect \Y $29
- end
process $group_8
- assign \wr_detect$28 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $29 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- assign \wr_detect$28 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \nia6__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$28 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest26__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$28 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest36__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$28 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest46__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$28 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \d_wr16__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$28 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $31
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $32
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \d_rd16__ren
- connect \B 1'1
- connect \Y $31
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- wire width 1 $33
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- cell $not $34
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \wr_detect$28
- connect \Y $33
- end
- process $group_9
- assign \d_rd16__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $31 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \nia6__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \d_rd16__data_o \nia6__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest26__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \d_rd16__data_o \dest26__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest36__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \d_rd16__data_o \dest36__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest46__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \d_rd16__data_o \dest46__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \d_wr16__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \d_rd16__data_o \d_wr16__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- switch { $33 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- case 1'1
- assign \d_rd16__data_o \reg
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- assign \d_rd16__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- sync init
- end
- process $group_10
assign \reg$next \reg
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \nia6__wen }
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "test_issuer.core.fast.reg_7"
-module \reg_7$109
+module \reg_7$126
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 0 \rst
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
wire width 1 input 1 \clk
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 2 \src17__ren
+ wire width 1 input 2 \cia7__ren
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 3 \src17__data_o
+ wire width 64 output 3 \cia7__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 4 \src27__ren
+ wire width 1 input 4 \msr7__ren
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 5 \src27__data_o
+ wire width 64 output 5 \msr7__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 6 \src37__ren
+ wire width 1 input 6 \src17__ren
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 7 \src37__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 8 \src47__ren
+ wire width 64 output 7 \src17__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 9 \src47__data_o
+ wire width 1 input 8 \src27__ren
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 10 \d_rd17__ren
+ wire width 64 output 9 \src27__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 11 \d_rd17__data_o
+ wire width 1 input 10 \nia7__wen
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 12 \nia7__wen
+ wire width 64 input 11 \nia7__data_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 input 13 \nia7__data_i
+ wire width 1 input 12 \dest27__wen
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 14 \dest27__wen
+ wire width 64 input 13 \dest27__data_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 input 15 \dest27__data_i
+ wire width 1 input 14 \dest37__wen
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 16 \dest37__wen
+ wire width 64 input 15 \dest37__data_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 input 17 \dest37__data_i
+ wire width 1 input 16 \dest47__wen
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 18 \dest47__wen
+ wire width 64 input 17 \dest47__data_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 input 19 \dest47__data_i
+ wire width 1 input 18 \d_wr17__wen
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 input 20 \d_wr17__wen
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 input 21 \d_wr17__data_i
+ wire width 64 input 19 \d_wr17__data_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
wire width 1 \wr_detect
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \src17__ren
+ connect \A \cia7__ren
connect \B 1'1
connect \Y $1
end
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \src17__ren
+ connect \A \cia7__ren
connect \B 1'1
connect \Y $3
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
wire width 64 \reg$next
process $group_1
- assign \src17__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \cia7__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $3 }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { \nia7__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src17__data_o \nia7__data_i
+ assign \cia7__data_o \nia7__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest27__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src17__data_o \dest27__data_i
+ assign \cia7__data_o \dest27__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest37__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src17__data_o \dest37__data_i
+ assign \cia7__data_o \dest37__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest47__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src17__data_o \dest47__data_i
+ assign \cia7__data_o \dest47__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \d_wr17__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src17__data_o \d_wr17__data_i
+ assign \cia7__data_o \d_wr17__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $5 }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
- assign \src17__data_o \reg
+ assign \cia7__data_o \reg
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
- assign \src17__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \cia7__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
end
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \src27__ren
+ connect \A \msr7__ren
connect \B 1'1
connect \Y $8
end
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \src27__ren
+ connect \A \msr7__ren
connect \B 1'1
connect \Y $10
end
connect \Y $12
end
process $group_3
- assign \src27__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \msr7__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $10 }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { \nia7__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src27__data_o \nia7__data_i
+ assign \msr7__data_o \nia7__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest27__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src27__data_o \dest27__data_i
+ assign \msr7__data_o \dest27__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest37__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src27__data_o \dest37__data_i
+ assign \msr7__data_o \dest37__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest47__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src27__data_o \dest47__data_i
+ assign \msr7__data_o \dest47__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \d_wr17__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src27__data_o \d_wr17__data_i
+ assign \msr7__data_o \d_wr17__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $12 }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
- assign \src27__data_o \reg
+ assign \msr7__data_o \reg
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
- assign \src27__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \msr7__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
end
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \src37__ren
+ connect \A \src17__ren
connect \B 1'1
connect \Y $15
end
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \src37__ren
+ connect \A \src17__ren
connect \B 1'1
connect \Y $17
end
connect \Y $19
end
process $group_5
- assign \src37__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \src17__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $17 }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { \nia7__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src37__data_o \nia7__data_i
+ assign \src17__data_o \nia7__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest27__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src37__data_o \dest27__data_i
+ assign \src17__data_o \dest27__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest37__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src37__data_o \dest37__data_i
+ assign \src17__data_o \dest37__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest47__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src37__data_o \dest47__data_i
+ assign \src17__data_o \dest47__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \d_wr17__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src37__data_o \d_wr17__data_i
+ assign \src17__data_o \d_wr17__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $19 }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
- assign \src37__data_o \reg
+ assign \src17__data_o \reg
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
- assign \src37__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \src17__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
end
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \src47__ren
+ connect \A \src27__ren
connect \B 1'1
connect \Y $22
end
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \src47__ren
+ connect \A \src27__ren
connect \B 1'1
connect \Y $24
end
connect \Y $26
end
process $group_7
- assign \src47__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \src27__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { $24 }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
switch { \nia7__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src47__data_o \nia7__data_i
+ assign \src27__data_o \nia7__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest27__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src47__data_o \dest27__data_i
+ assign \src27__data_o \dest27__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest37__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src47__data_o \dest37__data_i
+ assign \src27__data_o \dest37__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \dest47__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src47__data_o \dest47__data_i
+ assign \src27__data_o \dest47__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
switch { \d_wr17__wen }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
case 1'1
- assign \src47__data_o \d_wr17__data_i
+ assign \src27__data_o \d_wr17__data_i
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
switch { $26 }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
case 1'1
- assign \src47__data_o \reg
+ assign \src27__data_o \reg
end
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
case
- assign \src47__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \src27__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
- wire width 1 \wr_detect$28
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $29
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $30
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \d_rd17__ren
- connect \B 1'1
- connect \Y $29
- end
process $group_8
- assign \wr_detect$28 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $29 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- assign \wr_detect$28 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \nia7__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$28 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest27__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$28 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest37__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$28 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest47__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$28 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \d_wr17__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \wr_detect$28 1'1
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- wire width 1 $31
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- cell $eq $32
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \d_rd17__ren
- connect \B 1'1
- connect \Y $31
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- wire width 1 $33
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- cell $not $34
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \wr_detect$28
- connect \Y $33
- end
- process $group_9
- assign \d_rd17__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- switch { $31 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
- case 1'1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \nia7__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \d_rd17__data_o \nia7__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest27__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \d_rd17__data_o \dest27__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest37__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \d_rd17__data_o \dest37__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \dest47__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \d_rd17__data_o \dest47__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- switch { \d_wr17__wen }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
- case 1'1
- assign \d_rd17__data_o \d_wr17__data_i
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- switch { $33 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
- case 1'1
- assign \d_rd17__data_o \reg
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
- case
- assign \d_rd17__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- end
- sync init
- end
- process $group_10
assign \reg$next \reg
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
switch { \nia7__wen }
attribute \nmigen.hierarchy "test_issuer.core.fast"
module \fast
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 8 input 0 \d_rd1__ren
+ wire width 8 input 0 \cia__ren
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 1 \d_rd1__data_o
+ wire width 64 output 1 \cia__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 8 input 2 \fast_nia_wen
+ wire width 8 input 2 \msr__ren
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 8 input 3 \wen
+ wire width 64 output 3 \msr__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 input 4 \data_i
+ wire width 8 input 4 \fast_nia_wen
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+ wire width 8 input 5 \wen
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+ wire width 64 input 6 \data_i
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
- wire width 1 input 5 \rst
+ wire width 1 input 7 \rst
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
- wire width 1 input 6 \clk
+ wire width 1 input 8 \clk
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 8 input 7 \src3__ren
+ wire width 8 input 9 \src1__ren
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 8 \src3__data_o
+ wire width 64 output 10 \src1__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 8 input 9 \src4__ren
+ wire width 8 input 11 \src2__ren
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 10 \src4__data_o
+ wire width 64 output 12 \src2__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 8 input 11 \src1__ren
+ wire width 8 input 13 \wen$1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 12 \src1__data_o
+ wire width 64 input 14 \data_i$2
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 8 input 13 \src2__ren
+ wire width 8 input 15 \wen$3
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 14 \src2__data_o
+ wire width 64 input 16 \data_i$4
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 8 input 15 \wen$1
+ wire width 64 input 17 \data_i$5
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 input 16 \data_i$2
+ wire width 8 input 18 \wen$6
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 8 input 17 \wen$3
+ wire width 64 input 19 \data_i$7
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 input 18 \data_i$4
+ wire width 1 \reg_0_cia0__ren
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 input 19 \data_i$5
+ wire width 64 \reg_0_cia0__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 8 input 20 \wen$6
+ wire width 1 \reg_0_msr0__ren
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 input 21 \data_i$7
+ wire width 64 \reg_0_msr0__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_0_src10__ren
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 \reg_0_src20__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_0_src30__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_0_src30__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_0_src40__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_0_src40__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_0_d_rd10__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_0_d_rd10__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_0_nia0__wen
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 \reg_0_nia0__data_i
wire width 1 \reg_0_d_wr10__wen
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 \reg_0_d_wr10__data_i
- cell \reg_0$102 \reg_0
+ cell \reg_0$119 \reg_0
connect \rst \rst
connect \clk \clk
+ connect \cia0__ren \reg_0_cia0__ren
+ connect \cia0__data_o \reg_0_cia0__data_o
+ connect \msr0__ren \reg_0_msr0__ren
+ connect \msr0__data_o \reg_0_msr0__data_o
connect \src10__ren \reg_0_src10__ren
connect \src10__data_o \reg_0_src10__data_o
connect \src20__ren \reg_0_src20__ren
connect \src20__data_o \reg_0_src20__data_o
- connect \src30__ren \reg_0_src30__ren
- connect \src30__data_o \reg_0_src30__data_o
- connect \src40__ren \reg_0_src40__ren
- connect \src40__data_o \reg_0_src40__data_o
- connect \d_rd10__ren \reg_0_d_rd10__ren
- connect \d_rd10__data_o \reg_0_d_rd10__data_o
connect \nia0__wen \reg_0_nia0__wen
connect \nia0__data_i \reg_0_nia0__data_i
connect \dest20__wen \reg_0_dest20__wen
connect \d_wr10__data_i \reg_0_d_wr10__data_i
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_1_src11__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_1_src11__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_1_src21__ren
+ wire width 1 \reg_1_cia1__ren
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_1_src21__data_o
+ wire width 64 \reg_1_cia1__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_1_src31__ren
+ wire width 1 \reg_1_msr1__ren
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_1_src31__data_o
+ wire width 64 \reg_1_msr1__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_1_src41__ren
+ wire width 1 \reg_1_src11__ren
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_1_src41__data_o
+ wire width 64 \reg_1_src11__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_1_d_rd11__ren
+ wire width 1 \reg_1_src21__ren
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_1_d_rd11__data_o
+ wire width 64 \reg_1_src21__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_1_nia1__wen
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_1_d_wr11__wen
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 \reg_1_d_wr11__data_i
- cell \reg_1$103 \reg_1
+ cell \reg_1$120 \reg_1
connect \rst \rst
connect \clk \clk
+ connect \cia1__ren \reg_1_cia1__ren
+ connect \cia1__data_o \reg_1_cia1__data_o
+ connect \msr1__ren \reg_1_msr1__ren
+ connect \msr1__data_o \reg_1_msr1__data_o
connect \src11__ren \reg_1_src11__ren
connect \src11__data_o \reg_1_src11__data_o
connect \src21__ren \reg_1_src21__ren
connect \src21__data_o \reg_1_src21__data_o
- connect \src31__ren \reg_1_src31__ren
- connect \src31__data_o \reg_1_src31__data_o
- connect \src41__ren \reg_1_src41__ren
- connect \src41__data_o \reg_1_src41__data_o
- connect \d_rd11__ren \reg_1_d_rd11__ren
- connect \d_rd11__data_o \reg_1_d_rd11__data_o
connect \nia1__wen \reg_1_nia1__wen
connect \nia1__data_i \reg_1_nia1__data_i
connect \dest21__wen \reg_1_dest21__wen
connect \d_wr11__data_i \reg_1_d_wr11__data_i
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_2_src12__ren
+ wire width 1 \reg_2_cia2__ren
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_2_src12__data_o
+ wire width 64 \reg_2_cia2__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_2_src22__ren
+ wire width 1 \reg_2_msr2__ren
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_2_src22__data_o
+ wire width 64 \reg_2_msr2__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_2_src32__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_2_src32__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_2_src42__ren
+ wire width 1 \reg_2_src12__ren
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_2_src42__data_o
+ wire width 64 \reg_2_src12__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_2_d_rd12__ren
+ wire width 1 \reg_2_src22__ren
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_2_d_rd12__data_o
+ wire width 64 \reg_2_src22__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_2_nia2__wen
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_2_d_wr12__wen
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 \reg_2_d_wr12__data_i
- cell \reg_2$104 \reg_2
+ cell \reg_2$121 \reg_2
connect \rst \rst
connect \clk \clk
+ connect \cia2__ren \reg_2_cia2__ren
+ connect \cia2__data_o \reg_2_cia2__data_o
+ connect \msr2__ren \reg_2_msr2__ren
+ connect \msr2__data_o \reg_2_msr2__data_o
connect \src12__ren \reg_2_src12__ren
connect \src12__data_o \reg_2_src12__data_o
connect \src22__ren \reg_2_src22__ren
connect \src22__data_o \reg_2_src22__data_o
- connect \src32__ren \reg_2_src32__ren
- connect \src32__data_o \reg_2_src32__data_o
- connect \src42__ren \reg_2_src42__ren
- connect \src42__data_o \reg_2_src42__data_o
- connect \d_rd12__ren \reg_2_d_rd12__ren
- connect \d_rd12__data_o \reg_2_d_rd12__data_o
connect \nia2__wen \reg_2_nia2__wen
connect \nia2__data_i \reg_2_nia2__data_i
connect \dest22__wen \reg_2_dest22__wen
connect \d_wr12__data_i \reg_2_d_wr12__data_i
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_3_src13__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_3_src13__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_3_src23__ren
+ wire width 1 \reg_3_cia3__ren
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_3_src23__data_o
+ wire width 64 \reg_3_cia3__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_3_src33__ren
+ wire width 1 \reg_3_msr3__ren
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_3_src33__data_o
+ wire width 64 \reg_3_msr3__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_3_src43__ren
+ wire width 1 \reg_3_src13__ren
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_3_src43__data_o
+ wire width 64 \reg_3_src13__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_3_d_rd13__ren
+ wire width 1 \reg_3_src23__ren
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_3_d_rd13__data_o
+ wire width 64 \reg_3_src23__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_3_nia3__wen
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_3_d_wr13__wen
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 \reg_3_d_wr13__data_i
- cell \reg_3$105 \reg_3
+ cell \reg_3$122 \reg_3
connect \rst \rst
connect \clk \clk
+ connect \cia3__ren \reg_3_cia3__ren
+ connect \cia3__data_o \reg_3_cia3__data_o
+ connect \msr3__ren \reg_3_msr3__ren
+ connect \msr3__data_o \reg_3_msr3__data_o
connect \src13__ren \reg_3_src13__ren
connect \src13__data_o \reg_3_src13__data_o
connect \src23__ren \reg_3_src23__ren
connect \src23__data_o \reg_3_src23__data_o
- connect \src33__ren \reg_3_src33__ren
- connect \src33__data_o \reg_3_src33__data_o
- connect \src43__ren \reg_3_src43__ren
- connect \src43__data_o \reg_3_src43__data_o
- connect \d_rd13__ren \reg_3_d_rd13__ren
- connect \d_rd13__data_o \reg_3_d_rd13__data_o
connect \nia3__wen \reg_3_nia3__wen
connect \nia3__data_i \reg_3_nia3__data_i
connect \dest23__wen \reg_3_dest23__wen
connect \d_wr13__data_i \reg_3_d_wr13__data_i
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_4_src14__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_4_src14__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_4_src24__ren
+ wire width 1 \reg_4_cia4__ren
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_4_src24__data_o
+ wire width 64 \reg_4_cia4__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_4_src34__ren
+ wire width 1 \reg_4_msr4__ren
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_4_src34__data_o
+ wire width 64 \reg_4_msr4__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_4_src44__ren
+ wire width 1 \reg_4_src14__ren
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_4_src44__data_o
+ wire width 64 \reg_4_src14__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_4_d_rd14__ren
+ wire width 1 \reg_4_src24__ren
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_4_d_rd14__data_o
+ wire width 64 \reg_4_src24__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_4_nia4__wen
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_4_d_wr14__wen
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 \reg_4_d_wr14__data_i
- cell \reg_4$106 \reg_4
+ cell \reg_4$123 \reg_4
connect \rst \rst
connect \clk \clk
+ connect \cia4__ren \reg_4_cia4__ren
+ connect \cia4__data_o \reg_4_cia4__data_o
+ connect \msr4__ren \reg_4_msr4__ren
+ connect \msr4__data_o \reg_4_msr4__data_o
connect \src14__ren \reg_4_src14__ren
connect \src14__data_o \reg_4_src14__data_o
connect \src24__ren \reg_4_src24__ren
connect \src24__data_o \reg_4_src24__data_o
- connect \src34__ren \reg_4_src34__ren
- connect \src34__data_o \reg_4_src34__data_o
- connect \src44__ren \reg_4_src44__ren
- connect \src44__data_o \reg_4_src44__data_o
- connect \d_rd14__ren \reg_4_d_rd14__ren
- connect \d_rd14__data_o \reg_4_d_rd14__data_o
connect \nia4__wen \reg_4_nia4__wen
connect \nia4__data_i \reg_4_nia4__data_i
connect \dest24__wen \reg_4_dest24__wen
connect \d_wr14__data_i \reg_4_d_wr14__data_i
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_5_src15__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_5_src15__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_5_src25__ren
+ wire width 1 \reg_5_cia5__ren
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_5_src25__data_o
+ wire width 64 \reg_5_cia5__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_5_src35__ren
+ wire width 1 \reg_5_msr5__ren
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_5_src35__data_o
+ wire width 64 \reg_5_msr5__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_5_src45__ren
+ wire width 1 \reg_5_src15__ren
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_5_src45__data_o
+ wire width 64 \reg_5_src15__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_5_d_rd15__ren
+ wire width 1 \reg_5_src25__ren
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_5_d_rd15__data_o
+ wire width 64 \reg_5_src25__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_5_nia5__wen
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_5_d_wr15__wen
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 \reg_5_d_wr15__data_i
- cell \reg_5$107 \reg_5
+ cell \reg_5$124 \reg_5
connect \rst \rst
connect \clk \clk
+ connect \cia5__ren \reg_5_cia5__ren
+ connect \cia5__data_o \reg_5_cia5__data_o
+ connect \msr5__ren \reg_5_msr5__ren
+ connect \msr5__data_o \reg_5_msr5__data_o
connect \src15__ren \reg_5_src15__ren
connect \src15__data_o \reg_5_src15__data_o
connect \src25__ren \reg_5_src25__ren
connect \src25__data_o \reg_5_src25__data_o
- connect \src35__ren \reg_5_src35__ren
- connect \src35__data_o \reg_5_src35__data_o
- connect \src45__ren \reg_5_src45__ren
- connect \src45__data_o \reg_5_src45__data_o
- connect \d_rd15__ren \reg_5_d_rd15__ren
- connect \d_rd15__data_o \reg_5_d_rd15__data_o
connect \nia5__wen \reg_5_nia5__wen
connect \nia5__data_i \reg_5_nia5__data_i
connect \dest25__wen \reg_5_dest25__wen
connect \d_wr15__data_i \reg_5_d_wr15__data_i
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_6_src16__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_6_src16__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_6_src26__ren
+ wire width 1 \reg_6_cia6__ren
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_6_src26__data_o
+ wire width 64 \reg_6_cia6__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_6_src36__ren
+ wire width 1 \reg_6_msr6__ren
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_6_src36__data_o
+ wire width 64 \reg_6_msr6__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_6_src46__ren
+ wire width 1 \reg_6_src16__ren
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_6_src46__data_o
+ wire width 64 \reg_6_src16__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_6_d_rd16__ren
+ wire width 1 \reg_6_src26__ren
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_6_d_rd16__data_o
+ wire width 64 \reg_6_src26__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_6_nia6__wen
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_6_d_wr16__wen
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 \reg_6_d_wr16__data_i
- cell \reg_6$108 \reg_6
+ cell \reg_6$125 \reg_6
connect \rst \rst
connect \clk \clk
+ connect \cia6__ren \reg_6_cia6__ren
+ connect \cia6__data_o \reg_6_cia6__data_o
+ connect \msr6__ren \reg_6_msr6__ren
+ connect \msr6__data_o \reg_6_msr6__data_o
connect \src16__ren \reg_6_src16__ren
connect \src16__data_o \reg_6_src16__data_o
connect \src26__ren \reg_6_src26__ren
connect \src26__data_o \reg_6_src26__data_o
- connect \src36__ren \reg_6_src36__ren
- connect \src36__data_o \reg_6_src36__data_o
- connect \src46__ren \reg_6_src46__ren
- connect \src46__data_o \reg_6_src46__data_o
- connect \d_rd16__ren \reg_6_d_rd16__ren
- connect \d_rd16__data_o \reg_6_d_rd16__data_o
connect \nia6__wen \reg_6_nia6__wen
connect \nia6__data_i \reg_6_nia6__data_i
connect \dest26__wen \reg_6_dest26__wen
connect \d_wr16__data_i \reg_6_d_wr16__data_i
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_7_src17__ren
+ wire width 1 \reg_7_cia7__ren
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_7_src17__data_o
+ wire width 64 \reg_7_cia7__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_7_src27__ren
+ wire width 1 \reg_7_msr7__ren
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_7_src27__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_7_src37__ren
+ wire width 64 \reg_7_msr7__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_7_src37__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_7_src47__ren
+ wire width 1 \reg_7_src17__ren
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_7_src47__data_o
+ wire width 64 \reg_7_src17__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \reg_7_d_rd17__ren
+ wire width 1 \reg_7_src27__ren
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \reg_7_d_rd17__data_o
+ wire width 64 \reg_7_src27__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_7_nia7__wen
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \reg_7_d_wr17__wen
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 \reg_7_d_wr17__data_i
- cell \reg_7$109 \reg_7
+ cell \reg_7$126 \reg_7
connect \rst \rst
connect \clk \clk
+ connect \cia7__ren \reg_7_cia7__ren
+ connect \cia7__data_o \reg_7_cia7__data_o
+ connect \msr7__ren \reg_7_msr7__ren
+ connect \msr7__data_o \reg_7_msr7__data_o
connect \src17__ren \reg_7_src17__ren
connect \src17__data_o \reg_7_src17__data_o
connect \src27__ren \reg_7_src27__ren
connect \src27__data_o \reg_7_src27__data_o
- connect \src37__ren \reg_7_src37__ren
- connect \src37__data_o \reg_7_src37__data_o
- connect \src47__ren \reg_7_src47__ren
- connect \src47__data_o \reg_7_src47__data_o
- connect \d_rd17__ren \reg_7_d_rd17__ren
- connect \d_rd17__data_o \reg_7_d_rd17__data_o
connect \nia7__wen \reg_7_nia7__wen
connect \nia7__data_i \reg_7_nia7__data_i
connect \dest27__wen \reg_7_dest27__wen
connect \d_wr17__data_i \reg_7_d_wr17__data_i
end
process $group_0
- assign \reg_0_src10__ren 1'0
- assign \reg_1_src11__ren 1'0
- assign \reg_2_src12__ren 1'0
- assign \reg_3_src13__ren 1'0
- assign \reg_4_src14__ren 1'0
- assign \reg_5_src15__ren 1'0
- assign \reg_6_src16__ren 1'0
- assign \reg_7_src17__ren 1'0
- assign { \reg_7_src17__ren \reg_6_src16__ren \reg_5_src15__ren \reg_4_src14__ren \reg_3_src13__ren \reg_2_src12__ren \reg_1_src11__ren \reg_0_src10__ren } \src1__ren
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
+ assign \reg_0_cia0__ren 1'0
+ assign \reg_1_cia1__ren 1'0
+ assign \reg_2_cia2__ren 1'0
+ assign \reg_3_cia3__ren 1'0
+ assign \reg_4_cia4__ren 1'0
+ assign \reg_5_cia5__ren 1'0
+ assign \reg_6_cia6__ren 1'0
+ assign \reg_7_cia7__ren 1'0
+ assign { \reg_7_cia7__ren \reg_6_cia6__ren \reg_5_cia5__ren \reg_4_cia4__ren \reg_3_cia3__ren \reg_2_cia2__ren \reg_1_cia1__ren \reg_0_cia0__ren } \cia__ren
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
wire width 64 $8
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
cell $or $9
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \B_WIDTH 64
parameter \Y_WIDTH 64
- connect \A \reg_0_src10__data_o
- connect \B \reg_1_src11__data_o
+ connect \A \reg_0_cia0__data_o
+ connect \B \reg_1_cia1__data_o
connect \Y $8
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
wire width 64 $10
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
cell $or $11
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \B_WIDTH 64
parameter \Y_WIDTH 64
- connect \A \reg_2_src12__data_o
- connect \B \reg_3_src13__data_o
+ connect \A \reg_2_cia2__data_o
+ connect \B \reg_3_cia3__data_o
connect \Y $10
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
wire width 64 $12
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
cell $or $13
parameter \A_SIGNED 0
parameter \A_WIDTH 64
connect \B $10
connect \Y $12
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
wire width 64 $14
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
cell $or $15
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \B_WIDTH 64
parameter \Y_WIDTH 64
- connect \A \reg_4_src14__data_o
- connect \B \reg_5_src15__data_o
+ connect \A \reg_4_cia4__data_o
+ connect \B \reg_5_cia5__data_o
connect \Y $14
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
wire width 64 $16
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
cell $or $17
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \B_WIDTH 64
parameter \Y_WIDTH 64
- connect \A \reg_6_src16__data_o
- connect \B \reg_7_src17__data_o
+ connect \A \reg_6_cia6__data_o
+ connect \B \reg_7_cia7__data_o
connect \Y $16
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
wire width 64 $18
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
cell $or $19
parameter \A_SIGNED 0
parameter \A_WIDTH 64
connect \B $16
connect \Y $18
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
wire width 64 $20
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
cell $or $21
parameter \A_SIGNED 0
parameter \A_WIDTH 64
connect \Y $20
end
process $group_8
- assign \src1__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \src1__data_o $20
+ assign \cia__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \cia__data_o $20
sync init
end
process $group_9
- assign \reg_0_src20__ren 1'0
- assign \reg_1_src21__ren 1'0
- assign \reg_2_src22__ren 1'0
- assign \reg_3_src23__ren 1'0
- assign \reg_4_src24__ren 1'0
- assign \reg_5_src25__ren 1'0
- assign \reg_6_src26__ren 1'0
- assign \reg_7_src27__ren 1'0
- assign { \reg_7_src27__ren \reg_6_src26__ren \reg_5_src25__ren \reg_4_src24__ren \reg_3_src23__ren \reg_2_src22__ren \reg_1_src21__ren \reg_0_src20__ren } \src2__ren
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
+ assign \reg_0_msr0__ren 1'0
+ assign \reg_1_msr1__ren 1'0
+ assign \reg_2_msr2__ren 1'0
+ assign \reg_3_msr3__ren 1'0
+ assign \reg_4_msr4__ren 1'0
+ assign \reg_5_msr5__ren 1'0
+ assign \reg_6_msr6__ren 1'0
+ assign \reg_7_msr7__ren 1'0
+ assign { \reg_7_msr7__ren \reg_6_msr6__ren \reg_5_msr5__ren \reg_4_msr4__ren \reg_3_msr3__ren \reg_2_msr2__ren \reg_1_msr1__ren \reg_0_msr0__ren } \msr__ren
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
wire width 64 $22
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
cell $or $23
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \B_WIDTH 64
parameter \Y_WIDTH 64
- connect \A \reg_0_src20__data_o
- connect \B \reg_1_src21__data_o
+ connect \A \reg_0_msr0__data_o
+ connect \B \reg_1_msr1__data_o
connect \Y $22
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
wire width 64 $24
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
cell $or $25
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \B_WIDTH 64
parameter \Y_WIDTH 64
- connect \A \reg_2_src22__data_o
- connect \B \reg_3_src23__data_o
+ connect \A \reg_2_msr2__data_o
+ connect \B \reg_3_msr3__data_o
connect \Y $24
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
wire width 64 $26
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
cell $or $27
parameter \A_SIGNED 0
parameter \A_WIDTH 64
connect \B $24
connect \Y $26
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
wire width 64 $28
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
cell $or $29
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \B_WIDTH 64
parameter \Y_WIDTH 64
- connect \A \reg_4_src24__data_o
- connect \B \reg_5_src25__data_o
+ connect \A \reg_4_msr4__data_o
+ connect \B \reg_5_msr5__data_o
connect \Y $28
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
wire width 64 $30
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
cell $or $31
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \B_WIDTH 64
parameter \Y_WIDTH 64
- connect \A \reg_6_src26__data_o
- connect \B \reg_7_src27__data_o
+ connect \A \reg_6_msr6__data_o
+ connect \B \reg_7_msr7__data_o
connect \Y $30
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
wire width 64 $32
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
cell $or $33
parameter \A_SIGNED 0
parameter \A_WIDTH 64
connect \B $30
connect \Y $32
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
wire width 64 $34
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
cell $or $35
parameter \A_SIGNED 0
parameter \A_WIDTH 64
connect \Y $34
end
process $group_17
- assign \src2__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \src2__data_o $34
+ assign \msr__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \msr__data_o $34
sync init
end
process $group_18
- assign \reg_0_src30__ren 1'0
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- assign \reg_5_src35__ren 1'0
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- assign \reg_7_src37__ren 1'0
- assign { \reg_7_src37__ren \reg_6_src36__ren \reg_5_src35__ren \reg_4_src34__ren \reg_3_src33__ren \reg_2_src32__ren \reg_1_src31__ren \reg_0_src30__ren } \src3__ren
+ assign \reg_0_src10__ren 1'0
+ assign \reg_1_src11__ren 1'0
+ assign \reg_2_src12__ren 1'0
+ assign \reg_3_src13__ren 1'0
+ assign \reg_4_src14__ren 1'0
+ assign \reg_5_src15__ren 1'0
+ assign \reg_6_src16__ren 1'0
+ assign \reg_7_src17__ren 1'0
+ assign { \reg_7_src17__ren \reg_6_src16__ren \reg_5_src15__ren \reg_4_src14__ren \reg_3_src13__ren \reg_2_src12__ren \reg_1_src11__ren \reg_0_src10__ren } \src1__ren
sync init
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
wire width 64 $36
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
cell $or $37
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \B_WIDTH 64
parameter \Y_WIDTH 64
- connect \A \reg_0_src30__data_o
- connect \B \reg_1_src31__data_o
+ connect \A \reg_0_src10__data_o
+ connect \B \reg_1_src11__data_o
connect \Y $36
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
wire width 64 $38
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
cell $or $39
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \B_WIDTH 64
parameter \Y_WIDTH 64
- connect \A \reg_2_src32__data_o
- connect \B \reg_3_src33__data_o
+ connect \A \reg_2_src12__data_o
+ connect \B \reg_3_src13__data_o
connect \Y $38
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
wire width 64 $40
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
cell $or $41
parameter \A_SIGNED 0
parameter \A_WIDTH 64
connect \B $38
connect \Y $40
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
wire width 64 $42
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
cell $or $43
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \B_WIDTH 64
parameter \Y_WIDTH 64
- connect \A \reg_4_src34__data_o
- connect \B \reg_5_src35__data_o
+ connect \A \reg_4_src14__data_o
+ connect \B \reg_5_src15__data_o
connect \Y $42
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
wire width 64 $44
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
cell $or $45
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \B_WIDTH 64
parameter \Y_WIDTH 64
- connect \A \reg_6_src36__data_o
- connect \B \reg_7_src37__data_o
+ connect \A \reg_6_src16__data_o
+ connect \B \reg_7_src17__data_o
connect \Y $44
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
wire width 64 $46
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
cell $or $47
parameter \A_SIGNED 0
parameter \A_WIDTH 64
connect \B $44
connect \Y $46
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
wire width 64 $48
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
cell $or $49
parameter \A_SIGNED 0
parameter \A_WIDTH 64
connect \Y $48
end
process $group_26
- assign \src3__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \src3__data_o $48
+ assign \src1__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \src1__data_o $48
sync init
end
process $group_27
- assign \reg_0_src40__ren 1'0
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- assign \reg_7_src47__ren 1'0
- assign { \reg_7_src47__ren \reg_6_src46__ren \reg_5_src45__ren \reg_4_src44__ren \reg_3_src43__ren \reg_2_src42__ren \reg_1_src41__ren \reg_0_src40__ren } \src4__ren
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
+ assign \reg_0_src20__ren 1'0
+ assign \reg_1_src21__ren 1'0
+ assign \reg_2_src22__ren 1'0
+ assign \reg_3_src23__ren 1'0
+ assign \reg_4_src24__ren 1'0
+ assign \reg_5_src25__ren 1'0
+ assign \reg_6_src26__ren 1'0
+ assign \reg_7_src27__ren 1'0
+ assign { \reg_7_src27__ren \reg_6_src26__ren \reg_5_src25__ren \reg_4_src24__ren \reg_3_src23__ren \reg_2_src22__ren \reg_1_src21__ren \reg_0_src20__ren } \src2__ren
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
wire width 64 $50
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
cell $or $51
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \B_WIDTH 64
parameter \Y_WIDTH 64
- connect \A \reg_0_src40__data_o
- connect \B \reg_1_src41__data_o
+ connect \A \reg_0_src20__data_o
+ connect \B \reg_1_src21__data_o
connect \Y $50
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
wire width 64 $52
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
cell $or $53
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \B_WIDTH 64
parameter \Y_WIDTH 64
- connect \A \reg_2_src42__data_o
- connect \B \reg_3_src43__data_o
+ connect \A \reg_2_src22__data_o
+ connect \B \reg_3_src23__data_o
connect \Y $52
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
wire width 64 $54
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
cell $or $55
parameter \A_SIGNED 0
parameter \A_WIDTH 64
connect \B $52
connect \Y $54
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
wire width 64 $56
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
cell $or $57
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \B_WIDTH 64
parameter \Y_WIDTH 64
- connect \A \reg_4_src44__data_o
- connect \B \reg_5_src45__data_o
+ connect \A \reg_4_src24__data_o
+ connect \B \reg_5_src25__data_o
connect \Y $56
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
wire width 64 $58
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
cell $or $59
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \B_WIDTH 64
parameter \Y_WIDTH 64
- connect \A \reg_6_src46__data_o
- connect \B \reg_7_src47__data_o
+ connect \A \reg_6_src26__data_o
+ connect \B \reg_7_src27__data_o
connect \Y $58
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
wire width 64 $60
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
cell $or $61
parameter \A_SIGNED 0
parameter \A_WIDTH 64
connect \B $58
connect \Y $60
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
wire width 64 $62
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
cell $or $63
parameter \A_SIGNED 0
parameter \A_WIDTH 64
connect \Y $62
end
process $group_35
- assign \src4__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \src4__data_o $62
+ assign \src2__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \src2__data_o $62
sync init
end
process $group_36
- assign \reg_0_d_rd10__ren 1'0
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- assign \reg_3_d_rd13__ren 1'0
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- assign \reg_6_d_rd16__ren 1'0
- assign \reg_7_d_rd17__ren 1'0
- assign { \reg_7_d_rd17__ren \reg_6_d_rd16__ren \reg_5_d_rd15__ren \reg_4_d_rd14__ren \reg_3_d_rd13__ren \reg_2_d_rd12__ren \reg_1_d_rd11__ren \reg_0_d_rd10__ren } \d_rd1__ren
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
- wire width 64 $64
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
- cell $or $65
- parameter \A_SIGNED 0
- parameter \A_WIDTH 64
- parameter \B_SIGNED 0
- parameter \B_WIDTH 64
- parameter \Y_WIDTH 64
- connect \A \reg_0_d_rd10__data_o
- connect \B \reg_1_d_rd11__data_o
- connect \Y $64
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
- wire width 64 $66
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
- cell $or $67
- parameter \A_SIGNED 0
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- parameter \B_SIGNED 0
- parameter \B_WIDTH 64
- parameter \Y_WIDTH 64
- connect \A \reg_2_d_rd12__data_o
- connect \B \reg_3_d_rd13__data_o
- connect \Y $66
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
- wire width 64 $68
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
- cell $or $69
- parameter \A_SIGNED 0
- parameter \A_WIDTH 64
- parameter \B_SIGNED 0
- parameter \B_WIDTH 64
- parameter \Y_WIDTH 64
- connect \A $64
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- connect \Y $68
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
- wire width 64 $70
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
- cell $or $71
- parameter \A_SIGNED 0
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- parameter \B_SIGNED 0
- parameter \B_WIDTH 64
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- connect \A \reg_4_d_rd14__data_o
- connect \B \reg_5_d_rd15__data_o
- connect \Y $70
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
- wire width 64 $72
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
- cell $or $73
- parameter \A_SIGNED 0
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- parameter \B_SIGNED 0
- parameter \B_WIDTH 64
- parameter \Y_WIDTH 64
- connect \A \reg_6_d_rd16__data_o
- connect \B \reg_7_d_rd17__data_o
- connect \Y $72
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
- wire width 64 $74
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
- cell $or $75
- parameter \A_SIGNED 0
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- parameter \B_SIGNED 0
- parameter \B_WIDTH 64
- parameter \Y_WIDTH 64
- connect \A $70
- connect \B $72
- connect \Y $74
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
- wire width 64 $76
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
- cell $or $77
- parameter \A_SIGNED 0
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- parameter \B_SIGNED 0
- parameter \B_WIDTH 64
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- connect \A $68
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- connect \Y $76
- end
- process $group_44
- assign \d_rd1__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \d_rd1__data_o $76
- sync init
- end
- process $group_45
assign \reg_0_nia0__wen 1'0
assign \reg_1_nia1__wen 1'0
assign \reg_2_nia2__wen 1'0
assign { \reg_7_nia7__wen \reg_6_nia6__wen \reg_5_nia5__wen \reg_4_nia4__wen \reg_3_nia3__wen \reg_2_nia2__wen \reg_1_nia1__wen \reg_0_nia0__wen } \fast_nia_wen
sync init
end
- process $group_53
+ process $group_44
assign \reg_0_nia0__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
assign \reg_0_nia0__data_i \data_i$5
sync init
end
- process $group_54
+ process $group_45
assign \reg_1_nia1__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
assign \reg_1_nia1__data_i \data_i$5
sync init
end
- process $group_55
+ process $group_46
assign \reg_2_nia2__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
assign \reg_2_nia2__data_i \data_i$5
sync init
end
- process $group_56
+ process $group_47
assign \reg_3_nia3__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
assign \reg_3_nia3__data_i \data_i$5
sync init
end
- process $group_57
+ process $group_48
assign \reg_4_nia4__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
assign \reg_4_nia4__data_i \data_i$5
sync init
end
- process $group_58
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assign \reg_5_nia5__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
assign \reg_5_nia5__data_i \data_i$5
sync init
end
- process $group_59
+ process $group_50
assign \reg_6_nia6__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
assign \reg_6_nia6__data_i \data_i$5
sync init
end
- process $group_60
+ process $group_51
assign \reg_7_nia7__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
assign \reg_7_nia7__data_i \data_i$5
sync init
end
- process $group_61
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assign \reg_0_dest20__wen 1'0
assign \reg_1_dest21__wen 1'0
assign \reg_2_dest22__wen 1'0
assign { \reg_7_dest27__wen \reg_6_dest26__wen \reg_5_dest25__wen \reg_4_dest24__wen \reg_3_dest23__wen \reg_2_dest22__wen \reg_1_dest21__wen \reg_0_dest20__wen } \wen$6
sync init
end
- process $group_69
+ process $group_60
assign \reg_0_dest20__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
assign \reg_0_dest20__data_i \data_i$7
sync init
end
- process $group_70
+ process $group_61
assign \reg_1_dest21__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
assign \reg_1_dest21__data_i \data_i$7
sync init
end
- process $group_71
+ process $group_62
assign \reg_2_dest22__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
assign \reg_2_dest22__data_i \data_i$7
sync init
end
- process $group_72
+ process $group_63
assign \reg_3_dest23__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
assign \reg_3_dest23__data_i \data_i$7
sync init
end
- process $group_73
+ process $group_64
assign \reg_4_dest24__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
assign \reg_4_dest24__data_i \data_i$7
sync init
end
- process $group_74
+ process $group_65
assign \reg_5_dest25__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
assign \reg_5_dest25__data_i \data_i$7
sync init
end
- process $group_75
+ process $group_66
assign \reg_6_dest26__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
assign \reg_6_dest26__data_i \data_i$7
sync init
end
- process $group_76
+ process $group_67
assign \reg_7_dest27__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
assign \reg_7_dest27__data_i \data_i$7
sync init
end
- process $group_77
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assign \reg_0_dest30__wen 1'0
assign \reg_1_dest31__wen 1'0
assign \reg_2_dest32__wen 1'0
assign { \reg_7_dest37__wen \reg_6_dest36__wen \reg_5_dest35__wen \reg_4_dest34__wen \reg_3_dest33__wen \reg_2_dest32__wen \reg_1_dest31__wen \reg_0_dest30__wen } \wen$1
sync init
end
- process $group_85
+ process $group_76
assign \reg_0_dest30__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
assign \reg_0_dest30__data_i \data_i$2
sync init
end
- process $group_86
+ process $group_77
assign \reg_1_dest31__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
assign \reg_1_dest31__data_i \data_i$2
sync init
end
- process $group_87
+ process $group_78
assign \reg_2_dest32__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
assign \reg_2_dest32__data_i \data_i$2
sync init
end
- process $group_88
+ process $group_79
assign \reg_3_dest33__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
assign \reg_3_dest33__data_i \data_i$2
sync init
end
- process $group_89
+ process $group_80
assign \reg_4_dest34__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
assign \reg_4_dest34__data_i \data_i$2
sync init
end
- process $group_90
+ process $group_81
assign \reg_5_dest35__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
assign \reg_5_dest35__data_i \data_i$2
sync init
end
- process $group_91
+ process $group_82
assign \reg_6_dest36__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
assign \reg_6_dest36__data_i \data_i$2
sync init
end
- process $group_92
+ process $group_83
assign \reg_7_dest37__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
assign \reg_7_dest37__data_i \data_i$2
sync init
end
- process $group_93
+ process $group_84
assign \reg_0_dest40__wen 1'0
assign \reg_1_dest41__wen 1'0
assign \reg_2_dest42__wen 1'0
assign { \reg_7_dest47__wen \reg_6_dest46__wen \reg_5_dest45__wen \reg_4_dest44__wen \reg_3_dest43__wen \reg_2_dest42__wen \reg_1_dest41__wen \reg_0_dest40__wen } \wen$3
sync init
end
- process $group_101
+ process $group_92
assign \reg_0_dest40__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
assign \reg_0_dest40__data_i \data_i$4
sync init
end
- process $group_102
+ process $group_93
assign \reg_1_dest41__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
assign \reg_1_dest41__data_i \data_i$4
sync init
end
- process $group_103
+ process $group_94
assign \reg_2_dest42__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
assign \reg_2_dest42__data_i \data_i$4
sync init
end
- process $group_104
+ process $group_95
assign \reg_3_dest43__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
assign \reg_3_dest43__data_i \data_i$4
sync init
end
- process $group_105
+ process $group_96
assign \reg_4_dest44__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
assign \reg_4_dest44__data_i \data_i$4
sync init
end
- process $group_106
+ process $group_97
assign \reg_5_dest45__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
assign \reg_5_dest45__data_i \data_i$4
sync init
end
- process $group_107
+ process $group_98
assign \reg_6_dest46__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
assign \reg_6_dest46__data_i \data_i$4
sync init
end
- process $group_108
+ process $group_99
assign \reg_7_dest47__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
assign \reg_7_dest47__data_i \data_i$4
sync init
end
- process $group_109
+ process $group_100
assign \reg_0_d_wr10__wen 1'0
assign \reg_1_d_wr11__wen 1'0
assign \reg_2_d_wr12__wen 1'0
assign { \reg_7_d_wr17__wen \reg_6_d_wr16__wen \reg_5_d_wr15__wen \reg_4_d_wr14__wen \reg_3_d_wr13__wen \reg_2_d_wr12__wen \reg_1_d_wr11__wen \reg_0_d_wr10__wen } \wen
sync init
end
- process $group_117
+ process $group_108
assign \reg_0_d_wr10__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
assign \reg_0_d_wr10__data_i \data_i
sync init
end
- process $group_118
+ process $group_109
assign \reg_1_d_wr11__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
assign \reg_1_d_wr11__data_i \data_i
sync init
end
- process $group_119
+ process $group_110
assign \reg_2_d_wr12__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
assign \reg_2_d_wr12__data_i \data_i
sync init
end
- process $group_120
+ process $group_111
assign \reg_3_d_wr13__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
assign \reg_3_d_wr13__data_i \data_i
sync init
end
- process $group_121
+ process $group_112
assign \reg_4_d_wr14__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
assign \reg_4_d_wr14__data_i \data_i
sync init
end
- process $group_122
+ process $group_113
assign \reg_5_d_wr15__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
assign \reg_5_d_wr15__data_i \data_i
sync init
end
- process $group_123
+ process $group_114
assign \reg_6_d_wr16__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
assign \reg_6_d_wr16__data_i \data_i
sync init
end
- process $group_124
+ process $group_115
assign \reg_7_d_wr17__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
assign \reg_7_d_wr17__data_i \data_i
sync init
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
wire width 1 output 0 \en_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
- wire width 7 input 1 \i
+ wire width 8 input 1 \i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
- wire width 7 output 2 \o
+ wire width 8 output 2 \o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42"
- wire width 7 \ni
+ wire width 8 \ni
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
- wire width 7 $1
+ wire width 8 $1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
cell $not $2
parameter \A_SIGNED 0
- parameter \A_WIDTH 7
- parameter \Y_WIDTH 7
+ parameter \A_WIDTH 8
+ parameter \Y_WIDTH 8
connect \A \i
connect \Y $1
end
process $group_0
- assign \ni 7'0000000
+ assign \ni 8'00000000
assign \ni $1
sync init
end
assign \t6 $23
sync init
end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
+ wire width 1 \t7
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+ wire width 1 $27
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+ wire width 1 $28
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+ cell $reduce_bool $29
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 8
+ parameter \Y_WIDTH 1
+ connect \A { \i [6:0] [6] \i [6:0] [5] \i [6:0] [4] \i [6:0] [3] \i [6:0] [2] \i [6:0] [1] \i [6:0] [0] \ni [7] }
+ connect \Y $28
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+ cell $not $30
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A $28
+ connect \Y $27
+ end
process $group_8
- assign \o 7'0000000
- assign \o { \t6 \t5 \t4 \t3 \t2 \t1 \t0 }
+ assign \t7 1'0
+ assign \t7 $27
+ sync init
+ end
+ process $group_9
+ assign \o 8'00000000
+ assign \o { \t7 \t6 \t5 \t4 \t3 \t2 \t1 \t0 }
sync init
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
- wire width 1 $27
+ wire width 1 $31
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
- cell $reduce_bool $28
+ cell $reduce_bool $32
parameter \A_SIGNED 0
- parameter \A_WIDTH 7
+ parameter \A_WIDTH 8
parameter \Y_WIDTH 1
connect \A \o
- connect \Y $27
+ connect \Y $31
end
- process $group_9
+ process $group_10
assign \en_o 1'0
- assign \en_o $27
+ assign \en_o $31
sync init
end
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
wire width 1 output 0 \en_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
- wire width 6 input 1 \i
+ wire width 7 input 1 \i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
- wire width 6 output 2 \o
+ wire width 7 output 2 \o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42"
- wire width 6 \ni
+ wire width 7 \ni
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
- wire width 6 $1
+ wire width 7 $1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
cell $not $2
parameter \A_SIGNED 0
- parameter \A_WIDTH 6
- parameter \Y_WIDTH 6
+ parameter \A_WIDTH 7
+ parameter \Y_WIDTH 7
connect \A \i
connect \Y $1
end
process $group_0
- assign \ni 6'000000
+ assign \ni 7'0000000
assign \ni $1
sync init
end
assign \t5 $19
sync init
end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
+ wire width 1 \t6
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+ wire width 1 $23
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+ wire width 1 $24
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+ cell $reduce_bool $25
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 7
+ parameter \Y_WIDTH 1
+ connect \A { \i [5:0] [5] \i [5:0] [4] \i [5:0] [3] \i [5:0] [2] \i [5:0] [1] \i [5:0] [0] \ni [6] }
+ connect \Y $24
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+ cell $not $26
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A $24
+ connect \Y $23
+ end
process $group_7
- assign \o 6'000000
- assign \o { \t5 \t4 \t3 \t2 \t1 \t0 }
+ assign \t6 1'0
+ assign \t6 $23
+ sync init
+ end
+ process $group_8
+ assign \o 7'0000000
+ assign \o { \t6 \t5 \t4 \t3 \t2 \t1 \t0 }
sync init
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
- wire width 1 $23
+ wire width 1 $27
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
- cell $reduce_bool $24
+ cell $reduce_bool $28
parameter \A_SIGNED 0
- parameter \A_WIDTH 6
+ parameter \A_WIDTH 7
parameter \Y_WIDTH 1
connect \A \o
- connect \Y $23
+ connect \Y $27
end
- process $group_8
+ process $group_9
assign \en_o 1'0
- assign \en_o $23
+ assign \en_o $27
sync init
end
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
wire width 1 output 0 \en_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
- wire width 2 input 1 \i
+ wire width 3 input 1 \i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
- wire width 2 output 2 \o
+ wire width 3 output 2 \o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42"
- wire width 2 \ni
+ wire width 3 \ni
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
- wire width 2 $1
+ wire width 3 $1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
cell $not $2
parameter \A_SIGNED 0
- parameter \A_WIDTH 2
- parameter \Y_WIDTH 2
+ parameter \A_WIDTH 3
+ parameter \Y_WIDTH 3
connect \A \i
connect \Y $1
end
process $group_0
- assign \ni 2'00
+ assign \ni 3'000
assign \ni $1
sync init
end
assign \t1 $3
sync init
end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
+ wire width 1 \t2
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+ wire width 1 $7
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+ wire width 1 $8
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+ cell $reduce_bool $9
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 3
+ parameter \Y_WIDTH 1
+ connect \A { \i [1:0] [1] \i [1:0] [0] \ni [2] }
+ connect \Y $8
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+ cell $not $10
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A $8
+ connect \Y $7
+ end
process $group_3
- assign \o 2'00
- assign \o { \t1 \t0 }
+ assign \t2 1'0
+ assign \t2 $7
+ sync init
+ end
+ process $group_4
+ assign \o 3'000
+ assign \o { \t2 \t1 \t0 }
sync init
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
- wire width 1 $7
+ wire width 1 $11
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
- cell $reduce_bool $8
+ cell $reduce_bool $12
parameter \A_SIGNED 0
- parameter \A_WIDTH 2
+ parameter \A_WIDTH 3
parameter \Y_WIDTH 1
connect \A \o
- connect \Y $7
+ connect \Y $11
end
- process $group_4
+ process $group_5
assign \en_o 1'0
- assign \en_o $7
+ assign \en_o $11
sync init
end
end
assign \t1 $3
sync init
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
- wire width 1 \t2
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
- wire width 1 $7
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
- wire width 1 $8
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
- cell $reduce_bool $9
- parameter \A_SIGNED 0
- parameter \A_WIDTH 3
- parameter \Y_WIDTH 1
- connect \A { \i [1:0] [1] \i [1:0] [0] \ni [2] }
- connect \Y $8
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
- cell $not $10
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A $8
- connect \Y $7
- end
- process $group_3
- assign \t2 1'0
- assign \t2 $7
- sync init
- end
- process $group_4
- assign \o 3'000
- assign \o { \t2 \t1 \t0 }
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
- wire width 1 $11
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
- cell $reduce_bool $12
- parameter \A_SIGNED 0
- parameter \A_WIDTH 3
- parameter \Y_WIDTH 1
- connect \A \o
- connect \Y $11
- end
- process $group_5
- assign \en_o 1'0
- assign \en_o $11
- sync init
- end
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.rdpick_FAST_fast2"
-module \rdpick_FAST_fast2
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
- wire width 1 output 0 \en_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
- wire width 2 input 1 \i
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
- wire width 2 output 2 \o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42"
- wire width 2 \ni
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
- wire width 2 $1
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
- cell $not $2
- parameter \A_SIGNED 0
- parameter \A_WIDTH 2
- parameter \Y_WIDTH 2
- connect \A \i
- connect \Y $1
- end
- process $group_0
- assign \ni 2'00
- assign \ni $1
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
- wire width 1 \t0
- process $group_1
- assign \t0 1'0
- assign \t0 \i [0]
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
- wire width 1 \t1
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
- wire width 1 $3
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
- wire width 1 $4
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
- cell $reduce_bool $5
- parameter \A_SIGNED 0
- parameter \A_WIDTH 2
- parameter \Y_WIDTH 1
- connect \A { \i [0] \ni [1] }
- connect \Y $4
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
- cell $not $6
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A $4
- connect \Y $3
- end
- process $group_2
- assign \t1 1'0
- assign \t1 $3
- sync init
- end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
+ wire width 1 \t2
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+ wire width 1 $7
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+ wire width 1 $8
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+ cell $reduce_bool $9
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 3
+ parameter \Y_WIDTH 1
+ connect \A { \i [1:0] [1] \i [1:0] [0] \ni [2] }
+ connect \Y $8
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+ cell $not $10
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A $8
+ connect \Y $7
+ end
process $group_3
- assign \o 2'00
- assign \o { \t1 \t0 }
+ assign \t2 1'0
+ assign \t2 $7
+ sync init
+ end
+ process $group_4
+ assign \o 3'000
+ assign \o { \t2 \t1 \t0 }
sync init
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
- wire width 1 $7
+ wire width 1 $11
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
- cell $reduce_bool $8
+ cell $reduce_bool $12
parameter \A_SIGNED 0
- parameter \A_WIDTH 2
+ parameter \A_WIDTH 3
parameter \Y_WIDTH 1
connect \A \o
- connect \Y $7
+ connect \Y $11
end
- process $group_4
+ process $group_5
assign \en_o 1'0
- assign \en_o $7
+ assign \en_o $11
sync init
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.rdpick_FAST_cia"
-module \rdpick_FAST_cia
+attribute \nmigen.hierarchy "test_issuer.core.rdpick_FAST_fast2"
+module \rdpick_FAST_fast2
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
wire width 1 output 0 \en_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
end
end
attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.rdpick_FAST_msr"
-module \rdpick_FAST_msr
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
- wire width 1 output 0 \en_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
- wire width 1 input 1 \i
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
- wire width 1 output 2 \o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42"
- wire width 1 \ni
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
- wire width 1 $1
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
- cell $not $2
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \i
- connect \Y $1
- end
- process $group_0
- assign \ni 1'0
- assign \ni $1
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
- wire width 1 \t0
- process $group_1
- assign \t0 1'0
- assign \t0 \i
- sync init
- end
- process $group_2
- assign \o 1'0
- assign \o { \t0 }
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
- wire width 1 $3
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
- cell $reduce_bool $4
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \o
- connect \Y $3
- end
- process $group_3
- assign \en_o 1'0
- assign \en_o $3
- sync init
- end
-end
-attribute \generator "nMigen"
attribute \nmigen.hierarchy "test_issuer.core.rdpick_SPR_spr1"
module \rdpick_SPR_spr1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
wire width 1 output 0 \en_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
- wire width 7 input 1 \i
+ wire width 8 input 1 \i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
- wire width 7 output 2 \o
+ wire width 8 output 2 \o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42"
- wire width 7 \ni
+ wire width 8 \ni
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
- wire width 7 $1
+ wire width 8 $1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
cell $not $2
parameter \A_SIGNED 0
- parameter \A_WIDTH 7
- parameter \Y_WIDTH 7
+ parameter \A_WIDTH 8
+ parameter \Y_WIDTH 8
connect \A \i
connect \Y $1
end
process $group_0
- assign \ni 7'0000000
+ assign \ni 8'00000000
assign \ni $1
sync init
end
assign \t6 $23
sync init
end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
+ wire width 1 \t7
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+ wire width 1 $27
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+ wire width 1 $28
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+ cell $reduce_bool $29
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 8
+ parameter \Y_WIDTH 1
+ connect \A { \i [6:0] [6] \i [6:0] [5] \i [6:0] [4] \i [6:0] [3] \i [6:0] [2] \i [6:0] [1] \i [6:0] [0] \ni [7] }
+ connect \Y $28
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+ cell $not $30
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A $28
+ connect \Y $27
+ end
process $group_8
- assign \o 7'0000000
- assign \o { \t6 \t5 \t4 \t3 \t2 \t1 \t0 }
+ assign \t7 1'0
+ assign \t7 $27
+ sync init
+ end
+ process $group_9
+ assign \o 8'00000000
+ assign \o { \t7 \t6 \t5 \t4 \t3 \t2 \t1 \t0 }
sync init
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
- wire width 1 $27
+ wire width 1 $31
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
- cell $reduce_bool $28
+ cell $reduce_bool $32
parameter \A_SIGNED 0
- parameter \A_WIDTH 7
+ parameter \A_WIDTH 8
parameter \Y_WIDTH 1
connect \A \o
- connect \Y $27
+ connect \Y $31
end
- process $group_9
+ process $group_10
assign \en_o 1'0
- assign \en_o $27
+ assign \en_o $31
sync init
end
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
wire width 1 output 0 \en_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
- wire width 4 input 1 \i
+ wire width 5 input 1 \i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
- wire width 4 output 2 \o
+ wire width 5 output 2 \o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42"
- wire width 4 \ni
+ wire width 5 \ni
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
- wire width 4 $1
+ wire width 5 $1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
cell $not $2
parameter \A_SIGNED 0
- parameter \A_WIDTH 4
- parameter \Y_WIDTH 4
+ parameter \A_WIDTH 5
+ parameter \Y_WIDTH 5
connect \A \i
connect \Y $1
end
process $group_0
- assign \ni 4'0000
+ assign \ni 5'00000
assign \ni $1
sync init
end
assign \t3 $11
sync init
end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
+ wire width 1 \t4
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+ wire width 1 $15
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+ wire width 1 $16
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+ cell $reduce_bool $17
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 5
+ parameter \Y_WIDTH 1
+ connect \A { \i [3:0] [3] \i [3:0] [2] \i [3:0] [1] \i [3:0] [0] \ni [4] }
+ connect \Y $16
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+ cell $not $18
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A $16
+ connect \Y $15
+ end
process $group_5
- assign \o 4'0000
- assign \o { \t3 \t2 \t1 \t0 }
+ assign \t4 1'0
+ assign \t4 $15
+ sync init
+ end
+ process $group_6
+ assign \o 5'00000
+ assign \o { \t4 \t3 \t2 \t1 \t0 }
sync init
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
- wire width 1 $15
+ wire width 1 $19
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
- cell $reduce_bool $16
+ cell $reduce_bool $20
parameter \A_SIGNED 0
- parameter \A_WIDTH 4
+ parameter \A_WIDTH 5
parameter \Y_WIDTH 1
connect \A \o
- connect \Y $15
+ connect \Y $19
end
- process $group_6
+ process $group_7
assign \en_o 1'0
- assign \en_o $15
+ assign \en_o $19
sync init
end
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
wire width 1 output 0 \en_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
- wire width 2 input 1 \i
+ wire width 3 input 1 \i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
- wire width 2 output 2 \o
+ wire width 3 output 2 \o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42"
- wire width 2 \ni
+ wire width 3 \ni
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
- wire width 2 $1
+ wire width 3 $1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
cell $not $2
parameter \A_SIGNED 0
- parameter \A_WIDTH 2
- parameter \Y_WIDTH 2
+ parameter \A_WIDTH 3
+ parameter \Y_WIDTH 3
connect \A \i
connect \Y $1
end
process $group_0
- assign \ni 2'00
+ assign \ni 3'000
assign \ni $1
sync init
end
assign \t1 $3
sync init
end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
+ wire width 1 \t2
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+ wire width 1 $7
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+ wire width 1 $8
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+ cell $reduce_bool $9
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 3
+ parameter \Y_WIDTH 1
+ connect \A { \i [1:0] [1] \i [1:0] [0] \ni [2] }
+ connect \Y $8
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+ cell $not $10
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A $8
+ connect \Y $7
+ end
process $group_3
- assign \o 2'00
- assign \o { \t1 \t0 }
+ assign \t2 1'0
+ assign \t2 $7
+ sync init
+ end
+ process $group_4
+ assign \o 3'000
+ assign \o { \t2 \t1 \t0 }
sync init
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
- wire width 1 $7
+ wire width 1 $11
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
- cell $reduce_bool $8
+ cell $reduce_bool $12
parameter \A_SIGNED 0
- parameter \A_WIDTH 2
+ parameter \A_WIDTH 3
parameter \Y_WIDTH 1
connect \A \o
- connect \Y $7
+ connect \Y $11
end
- process $group_4
+ process $group_5
assign \en_o 1'0
- assign \en_o $7
+ assign \en_o $11
sync init
end
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
wire width 1 output 0 \en_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
- wire width 2 input 1 \i
+ wire width 3 input 1 \i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
- wire width 2 output 2 \o
+ wire width 3 output 2 \o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42"
- wire width 2 \ni
+ wire width 3 \ni
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
- wire width 2 $1
+ wire width 3 $1
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
cell $not $2
parameter \A_SIGNED 0
- parameter \A_WIDTH 2
- parameter \Y_WIDTH 2
+ parameter \A_WIDTH 3
+ parameter \Y_WIDTH 3
connect \A \i
connect \Y $1
end
process $group_0
- assign \ni 2'00
+ assign \ni 3'000
assign \ni $1
sync init
end
assign \t1 $3
sync init
end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
+ wire width 1 \t2
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+ wire width 1 $7
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+ wire width 1 $8
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+ cell $reduce_bool $9
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 3
+ parameter \Y_WIDTH 1
+ connect \A { \i [1:0] [1] \i [1:0] [0] \ni [2] }
+ connect \Y $8
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+ cell $not $10
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A $8
+ connect \Y $7
+ end
process $group_3
- assign \o 2'00
- assign \o { \t1 \t0 }
+ assign \t2 1'0
+ assign \t2 $7
+ sync init
+ end
+ process $group_4
+ assign \o 3'000
+ assign \o { \t2 \t1 \t0 }
sync init
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
- wire width 1 $7
+ wire width 1 $11
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
- cell $reduce_bool $8
+ cell $reduce_bool $12
parameter \A_SIGNED 0
- parameter \A_WIDTH 2
+ parameter \A_WIDTH 3
parameter \Y_WIDTH 1
connect \A \o
- connect \Y $7
+ connect \Y $11
end
- process $group_4
+ process $group_5
assign \en_o 1'0
- assign \en_o $7
+ assign \en_o $11
sync init
end
end
attribute \generator "nMigen"
attribute \nmigen.hierarchy "test_issuer.core"
module \core
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:79"
+ wire width 1 output 0 \corebusy_o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:88"
+ wire width 1 output 1 \core_terminated_o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:86"
+ wire width 1 input 2 \core_start_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:87"
+ wire width 1 input 3 \core_stop_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:329"
+ wire width 1 input 4 \bigendian
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 1 input 0 \ad__go
+ wire width 1 input 5 \ad__go
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 1 output 1 \ad__rel
+ wire width 1 output 6 \ad__rel
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 1 input 2 \st__go
+ wire width 1 input 7 \st__go
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 1 output 3 \st__rel
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 8 input 4 \d_rd1__ren
+ wire width 1 output 8 \st__rel
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 output 5 \d_rd1__data_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:546"
- wire width 1 input 6 \valid
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:74"
- wire width 1 input 7 \issue_i
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:319"
- wire width 1 input 8 \bigendian
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318"
- wire width 32 input 9 \raw_opcode_in
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 8 output 10 \fast_nia_wen
+ wire width 8 input 9 \cia__ren
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 8 \fast_nia_wen$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:75"
- wire width 1 output 11 \corebusy_o
+ wire width 64 output 10 \cia__data_o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:562"
+ wire width 1 input 11 \valid
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:78"
+ wire width 1 input 12 \issue_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:328"
+ wire width 32 input 13 \raw_opcode_in
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 8 input 12 \wen
+ wire width 8 input 14 \msr__ren
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 input 13 \data_i
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
- wire width 1 input 14 \rst
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
- wire width 1 input 15 \clk
- attribute \enum_base_type "Function"
- attribute \enum_value_00000000000 "NONE"
- attribute \enum_value_00000000010 "ALU"
- attribute \enum_value_00000000100 "LDST"
- attribute \enum_value_00000001000 "SHIFT_ROT"
- attribute \enum_value_00000010000 "LOGICAL"
- attribute \enum_value_00000100000 "BRANCH"
- attribute \enum_value_00001000000 "CR"
- attribute \enum_value_00010000000 "TRAP"
- attribute \enum_value_00100000000 "MUL"
- attribute \enum_value_01000000000 "DIV"
- attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:33"
- wire width 11 output 16 \fn_unit
- attribute \enum_base_type "InternalOp"
+ wire width 64 output 15 \msr__data_o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:565"
+ wire width 64 input 16 \msr
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566"
+ wire width 64 input 17 \cia
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 7 output 17 \oper_i__insn_type
- attribute \enum_base_type "InternalOp"
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:38"
+ wire width 7 output 18 \insn_type
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+ wire width 8 output 19 \fast_nia_wen
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+ wire width 8 input 20 \wen
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+ wire width 64 input 21 \data_i
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
+ wire width 1 input 22 \rst
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
+ wire width 1 input 23 \clk
+ attribute \enum_base_type "Function"
+ attribute \enum_value_00000000000 "NONE"
+ attribute \enum_value_00000000010 "ALU"
+ attribute \enum_value_00000000100 "LDST"
+ attribute \enum_value_00000001000 "SHIFT_ROT"
+ attribute \enum_value_00000010000 "LOGICAL"
+ attribute \enum_value_00000100000 "BRANCH"
+ attribute \enum_value_00001000000 "CR"
+ attribute \enum_value_00010000000 "TRAP"
+ attribute \enum_value_00100000000 "MUL"
+ attribute \enum_value_01000000000 "DIV"
+ attribute \enum_value_10000000000 "SPR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:39"
+ wire width 11 output 24 \fn_unit
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:32"
- wire width 7 output 18 \insn_type
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 output 19 \imm
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 20 \imm_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 output 21 \oper_i__lk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:58"
- wire width 1 output 22 \lk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 23 \rc
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 24 \rc_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 25 \oe
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 26 \oe_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 output 27 \oper_i__invert_a
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 7 output 25 \oper_i__insn_type
+ attribute \enum_base_type "Function"
+ attribute \enum_value_00000000000 "NONE"
+ attribute \enum_value_00000000010 "ALU"
+ attribute \enum_value_00000000100 "LDST"
+ attribute \enum_value_00000001000 "SHIFT_ROT"
+ attribute \enum_value_00000010000 "LOGICAL"
+ attribute \enum_value_00000100000 "BRANCH"
+ attribute \enum_value_00001000000 "CR"
+ attribute \enum_value_00010000000 "TRAP"
+ attribute \enum_value_00100000000 "MUL"
+ attribute \enum_value_01000000000 "DIV"
+ attribute \enum_value_10000000000 "SPR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 11 output 26 \oper_i__fn_unit
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 64 output 27 \imm
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 28 \imm_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 29 \rc
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 30 \rc_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 31 \oe
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 32 \oe_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 33 \oper_i__invert_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:44"
+ wire width 1 output 34 \invert_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 35 \oper_i__zero_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:45"
+ wire width 1 output 36 \zero_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 37 \oper_i__invert_out
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:50"
+ wire width 1 output 38 \invert_out
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 39 \oper_i__write_cr0
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:61"
- wire width 1 output 28 \invert_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:62"
- wire width 1 output 29 \zero_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 output 30 \oper_i__invert_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:63"
- wire width 1 output 31 \invert_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 3 output 32 \cr_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 33 \cr_out_ok
+ wire width 1 output 40 \write_cr0
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 2 output 34 \oper_i__input_carry
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 2 output 41 \oper_i__input_carry
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:64"
- wire width 2 output 35 \input_carry
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 output 36 \oper_i__output_carry
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:65"
- wire width 1 output 37 \output_carry
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 output 38 \oper_i__input_cr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:66"
- wire width 1 output 39 \input_cr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 output 40 \oper_i__output_cr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:67"
- wire width 1 output 41 \output_cr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 output 42 \oper_i__is_32bit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:68"
- wire width 1 output 43 \is_32bit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 output 44 \oper_i__is_signed
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:69"
- wire width 1 output 45 \is_signed
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 4 output 46 \oper_i__data_len
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:71"
- wire width 4 output 47 \data_len
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:70"
- wire width 32 output 48 \insn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 output 49 \oper_i__byte_reverse
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:72"
- wire width 1 output 50 \byte_reverse
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 output 51 \oper_i__sign_extend
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:73"
- wire width 1 output 52 \sign_extend
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:46"
+ wire width 2 output 42 \input_carry
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 43 \oper_i__output_carry
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47"
+ wire width 1 output 44 \output_carry
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 45 \oper_i__is_32bit
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:51"
+ wire width 1 output 46 \is_32bit
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 47 \oper_i__is_signed
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:52"
+ wire width 1 output 48 \is_signed
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 4 output 49 \oper_i__data_len
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53"
+ wire width 4 output 50 \data_len
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 output 51 \oper_i__insn
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:37"
+ wire width 32 output 52 \insn
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94"
wire width 1 output 53 \issue_i$1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
wire width 1 output 55 \reg1_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
wire width 1 output 56 \reg2_ok
- attribute \enum_base_type "InternalOp"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:81"
+ wire width 1 output 57 \xer_in
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
- wire width 7 output 57 \oper_i__insn_type$2
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 7 output 58 \oper_i__insn_type$2
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00000000010 "ALU"
attribute \enum_value_00100000000 "MUL"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
- wire width 11 output 58 \oper_i__fn_unit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
- wire width 32 output 59 \oper_i__insn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
- wire width 1 output 60 \oper_i__read_cr_whole
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:55"
- wire width 1 output 61 \read_cr_whole
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
- wire width 1 output 62 \oper_i__write_cr_whole
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:57"
- wire width 1 output 63 \write_cr_whole
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 11 output 59 \oper_i__fn_unit$3
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 output 60 \oper_i__insn$4
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 61 \oper_i__read_cr_whole
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:59"
+ wire width 1 output 62 \read_cr_whole
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 63 \oper_i__write_cr_whole
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:60"
+ wire width 1 output 64 \write_cr_whole
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94"
- wire width 1 output 64 \issue_i$3
+ wire width 1 output 65 \issue_i$5
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
- wire width 1 output 65 \busy_o$4
+ wire width 1 output 66 \busy_o$6
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 66 \cr_in1_ok
+ wire width 1 output 67 \cr_in1_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 67 \cr_in2_ok
+ wire width 1 output 68 \cr_in2_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 68 \cr_in2_ok$5
- attribute \enum_base_type "InternalOp"
+ wire width 1 output 69 \cr_in2_ok$7
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 output 70 \oper_i__cia
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:34"
+ wire width 64 output 71 \cia$8
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
- wire width 7 output 69 \oper_i__insn_type$6
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 7 output 72 \oper_i__insn_type$9
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00000000010 "ALU"
attribute \enum_value_00100000000 "MUL"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
- wire width 11 output 70 \oper_i__fn_unit$7
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
- wire width 1 output 71 \oper_i__lk$8
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
- wire width 1 output 72 \oper_i__is_32bit$9
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
- wire width 32 output 73 \oper_i__insn$10
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 11 output 73 \oper_i__fn_unit$10
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 output 74 \oper_i__insn$11
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 75 \oper_i__lk
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:41"
+ wire width 1 output 76 \lk
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 77 \oper_i__is_32bit$12
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94"
- wire width 1 output 74 \issue_i$11
+ wire width 1 output 78 \issue_i$13
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
- wire width 1 output 75 \busy_o$12
+ wire width 1 output 79 \busy_o$14
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 76 \fast1_ok
+ wire width 1 output 80 \fast1_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 77 \fast2_ok
- attribute \enum_base_type "InternalOp"
+ wire width 1 output 81 \fast2_ok
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
- wire width 7 output 78 \oper_i__insn_type$13
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 7 output 82 \oper_i__insn_type$15
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00000000010 "ALU"
attribute \enum_value_00100000000 "MUL"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
- wire width 11 output 79 \oper_i__fn_unit$14
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
- wire width 32 output 80 \oper_i__insn$15
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
- wire width 1 output 81 \oper_i__is_32bit$16
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
- wire width 5 output 82 \oper_i__traptype
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:75"
- wire width 5 output 83 \traptype
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
- wire width 13 output 84 \oper_i__trapaddr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:76"
- wire width 13 output 85 \trapaddr
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 11 output 83 \oper_i__fn_unit$16
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 output 84 \oper_i__insn$17
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 output 85 \oper_i__msr
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:33"
+ wire width 64 output 86 \msr$18
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 output 87 \oper_i__cia$19
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 88 \oper_i__is_32bit$20
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 5 output 89 \oper_i__traptype
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:57"
+ wire width 5 output 90 \traptype
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 13 output 91 \oper_i__trapaddr
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:58"
+ wire width 13 output 92 \trapaddr
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94"
- wire width 1 output 86 \issue_i$17
+ wire width 1 output 93 \issue_i$21
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
- wire width 1 output 87 \busy_o$18
- attribute \enum_base_type "InternalOp"
+ wire width 1 output 94 \busy_o$22
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 7 output 88 \oper_i__insn_type$19
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 7 output 95 \oper_i__insn_type$23
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00000000010 "ALU"
attribute \enum_value_00100000000 "MUL"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 11 output 89 \oper_i__fn_unit$20
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 output 90 \oper_i__lk$21
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 output 91 \oper_i__invert_a$22
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 11 output 96 \oper_i__fn_unit$24
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 97 \oper_i__invert_a$25
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 98 \oper_i__zero_a$26
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 2 output 92 \oper_i__input_carry$23
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 output 93 \oper_i__invert_out$24
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 output 94 \oper_i__output_carry$25
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 output 95 \oper_i__is_32bit$26
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 output 96 \oper_i__is_signed$27
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 4 output 97 \oper_i__data_len$28
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 2 output 99 \oper_i__input_carry$27
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 100 \oper_i__invert_out$28
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 101 \oper_i__write_cr0$29
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 102 \oper_i__output_carry$30
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 103 \oper_i__is_32bit$31
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 104 \oper_i__is_signed$32
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 4 output 105 \oper_i__data_len$33
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 output 106 \oper_i__insn$34
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94"
- wire width 1 output 98 \issue_i$29
+ wire width 1 output 107 \issue_i$35
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
- wire width 1 output 99 \busy_o$30
- attribute \enum_base_type "InternalOp"
+ wire width 1 output 108 \busy_o$36
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20"
- wire width 7 output 100 \oper_i__insn_type$31
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 7 output 109 \oper_i__insn_type$37
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00000000010 "ALU"
attribute \enum_value_00100000000 "MUL"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20"
- wire width 11 output 101 \oper_i__fn_unit$32
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20"
- wire width 32 output 102 \oper_i__insn$33
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20"
- wire width 1 output 103 \oper_i__is_32bit$34
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 11 output 110 \oper_i__fn_unit$38
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 output 111 \oper_i__insn$39
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 112 \oper_i__is_32bit$40
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94"
- wire width 1 output 104 \issue_i$35
+ wire width 1 output 113 \issue_i$41
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
- wire width 1 output 105 \busy_o$36
+ wire width 1 output 114 \busy_o$42
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 106 \spr1_ok
- attribute \enum_base_type "InternalOp"
+ wire width 1 output 115 \spr1_ok
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 7 output 107 \oper_i__insn_type$37
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 7 output 116 \oper_i__insn_type$43
+ attribute \enum_base_type "Function"
+ attribute \enum_value_00000000000 "NONE"
+ attribute \enum_value_00000000010 "ALU"
+ attribute \enum_value_00000000100 "LDST"
+ attribute \enum_value_00000001000 "SHIFT_ROT"
+ attribute \enum_value_00000010000 "LOGICAL"
+ attribute \enum_value_00000100000 "BRANCH"
+ attribute \enum_value_00001000000 "CR"
+ attribute \enum_value_00010000000 "TRAP"
+ attribute \enum_value_00100000000 "MUL"
+ attribute \enum_value_01000000000 "DIV"
+ attribute \enum_value_10000000000 "SPR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 11 output 117 \oper_i__fn_unit$44
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 118 \oper_i__invert_a$45
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 119 \oper_i__zero_a$46
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 120 \oper_i__invert_out$47
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 121 \oper_i__write_cr0$48
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 122 \oper_i__is_32bit$49
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 123 \oper_i__is_signed$50
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 output 124 \oper_i__insn$51
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94"
+ wire width 1 output 125 \issue_i$52
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
+ wire width 1 output 126 \busy_o$53
+ attribute \enum_base_type "MicrOp"
+ attribute \enum_value_0000000 "OP_ILLEGAL"
+ attribute \enum_value_0000001 "OP_NOP"
+ attribute \enum_value_0000010 "OP_ADD"
+ attribute \enum_value_0000011 "OP_ADDPCIS"
+ attribute \enum_value_0000100 "OP_AND"
+ attribute \enum_value_0000101 "OP_ATTN"
+ attribute \enum_value_0000110 "OP_B"
+ attribute \enum_value_0000111 "OP_BC"
+ attribute \enum_value_0001000 "OP_BCREG"
+ attribute \enum_value_0001001 "OP_BPERM"
+ attribute \enum_value_0001010 "OP_CMP"
+ attribute \enum_value_0001011 "OP_CMPB"
+ attribute \enum_value_0001100 "OP_CMPEQB"
+ attribute \enum_value_0001101 "OP_CMPRB"
+ attribute \enum_value_0001110 "OP_CNTZ"
+ attribute \enum_value_0001111 "OP_CRAND"
+ attribute \enum_value_0010000 "OP_CRANDC"
+ attribute \enum_value_0010001 "OP_CREQV"
+ attribute \enum_value_0010010 "OP_CRNAND"
+ attribute \enum_value_0010011 "OP_CRNOR"
+ attribute \enum_value_0010100 "OP_CROR"
+ attribute \enum_value_0010101 "OP_CRORC"
+ attribute \enum_value_0010110 "OP_CRXOR"
+ attribute \enum_value_0010111 "OP_DARN"
+ attribute \enum_value_0011000 "OP_DCBF"
+ attribute \enum_value_0011001 "OP_DCBST"
+ attribute \enum_value_0011010 "OP_DCBT"
+ attribute \enum_value_0011011 "OP_DCBTST"
+ attribute \enum_value_0011100 "OP_DCBZ"
+ attribute \enum_value_0011101 "OP_DIV"
+ attribute \enum_value_0011110 "OP_DIVE"
+ attribute \enum_value_0011111 "OP_EXTS"
+ attribute \enum_value_0100000 "OP_EXTSWSLI"
+ attribute \enum_value_0100001 "OP_ICBI"
+ attribute \enum_value_0100010 "OP_ICBT"
+ attribute \enum_value_0100011 "OP_ISEL"
+ attribute \enum_value_0100100 "OP_ISYNC"
+ attribute \enum_value_0100101 "OP_LOAD"
+ attribute \enum_value_0100110 "OP_STORE"
+ attribute \enum_value_0100111 "OP_MADDHD"
+ attribute \enum_value_0101000 "OP_MADDHDU"
+ attribute \enum_value_0101001 "OP_MADDLD"
+ attribute \enum_value_0101010 "OP_MCRF"
+ attribute \enum_value_0101011 "OP_MCRXR"
+ attribute \enum_value_0101100 "OP_MCRXRX"
+ attribute \enum_value_0101101 "OP_MFCR"
+ attribute \enum_value_0101110 "OP_MFSPR"
+ attribute \enum_value_0101111 "OP_MOD"
+ attribute \enum_value_0110000 "OP_MTCRF"
+ attribute \enum_value_0110001 "OP_MTSPR"
+ attribute \enum_value_0110010 "OP_MUL_L64"
+ attribute \enum_value_0110011 "OP_MUL_H64"
+ attribute \enum_value_0110100 "OP_MUL_H32"
+ attribute \enum_value_0110101 "OP_OR"
+ attribute \enum_value_0110110 "OP_POPCNT"
+ attribute \enum_value_0110111 "OP_PRTY"
+ attribute \enum_value_0111000 "OP_RLC"
+ attribute \enum_value_0111001 "OP_RLCL"
+ attribute \enum_value_0111010 "OP_RLCR"
+ attribute \enum_value_0111011 "OP_SETB"
+ attribute \enum_value_0111100 "OP_SHL"
+ attribute \enum_value_0111101 "OP_SHR"
+ attribute \enum_value_0111110 "OP_SYNC"
+ attribute \enum_value_0111111 "OP_TRAP"
+ attribute \enum_value_1000011 "OP_XOR"
+ attribute \enum_value_1000100 "OP_SIM_CONFIG"
+ attribute \enum_value_1000101 "OP_CROP"
+ attribute \enum_value_1000110 "OP_RFID"
+ attribute \enum_value_1000111 "OP_MFMSR"
+ attribute \enum_value_1001000 "OP_MTMSRD"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 7 output 127 \oper_i__insn_type$54
+ attribute \enum_base_type "Function"
+ attribute \enum_value_00000000000 "NONE"
+ attribute \enum_value_00000000010 "ALU"
+ attribute \enum_value_00000000100 "LDST"
+ attribute \enum_value_00000001000 "SHIFT_ROT"
+ attribute \enum_value_00000010000 "LOGICAL"
+ attribute \enum_value_00000100000 "BRANCH"
+ attribute \enum_value_00001000000 "CR"
+ attribute \enum_value_00010000000 "TRAP"
+ attribute \enum_value_00100000000 "MUL"
+ attribute \enum_value_01000000000 "DIV"
+ attribute \enum_value_10000000000 "SPR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 11 output 128 \oper_i__fn_unit$55
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 2 output 108 \oper_i__input_carry$38
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 output 109 \oper_i__output_carry$39
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 output 110 \oper_i__input_cr$40
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 output 111 \oper_i__output_cr$41
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 output 112 \oper_i__is_32bit$42
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 output 113 \oper_i__is_signed$43
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 2 output 130 \oper_i__input_carry$56
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 131 \oper_i__output_carry$57
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 132 \oper_i__input_cr
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48"
+ wire width 1 output 133 \input_cr
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 134 \oper_i__output_cr
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:49"
+ wire width 1 output 135 \output_cr
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 136 \oper_i__is_32bit$58
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 137 \oper_i__is_signed$59
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 output 138 \oper_i__insn$60
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94"
- wire width 1 output 114 \issue_i$44
+ wire width 1 output 139 \issue_i$61
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
- wire width 1 output 115 \busy_o$45
+ wire width 1 output 140 \busy_o$62
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 116 \reg3_ok
- attribute \enum_base_type "InternalOp"
+ wire width 1 output 141 \reg3_ok
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
- wire width 7 output 117 \oper_i__insn_type$46
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
- wire width 1 output 118 \oper_i__zero_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
- wire width 1 output 119 \oper_i__is_32bit$47
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
- wire width 1 output 120 \oper_i__is_signed$48
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
- wire width 4 output 121 \oper_i__data_len$49
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
- wire width 1 output 122 \oper_i__byte_reverse$50
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
- wire width 1 output 123 \oper_i__sign_extend$51
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
- wire width 1 output 124 \oper_i__update
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:74"
- wire width 1 output 125 \update
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 7 output 142 \oper_i__insn_type$63
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 143 \oper_i__zero_a$64
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 144 \oper_i__is_32bit$65
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 145 \oper_i__is_signed$66
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 4 output 146 \oper_i__data_len$67
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 147 \oper_i__byte_reverse
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:54"
+ wire width 1 output 148 \byte_reverse
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 149 \oper_i__sign_extend
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:55"
+ wire width 1 output 150 \sign_extend
+ attribute \enum_base_type "LDSTMode"
+ attribute \enum_value_00 "NONE"
+ attribute \enum_value_01 "update"
+ attribute \enum_value_10 "cix"
+ attribute \enum_value_11 "cx"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 2 output 151 \oper_i__ldst_mode
+ attribute \enum_base_type "LDSTMode"
+ attribute \enum_value_00 "NONE"
+ attribute \enum_value_01 "update"
+ attribute \enum_value_10 "cix"
+ attribute \enum_value_11 "cx"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:56"
+ wire width 2 output 152 \ldst_mode
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94"
- wire width 1 output 126 \issue_i$52
+ wire width 1 output 153 \issue_i$68
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
- wire width 1 output 127 \busy_o$53
+ wire width 1 output 154 \busy_o$69
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 5 output 128 \reg1
+ wire width 5 output 155 \reg1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 4 output 129 \rd__rel
+ wire width 4 output 156 \rd__rel
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 4 output 130 \rd__go
+ wire width 4 output 157 \rd__go
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
- wire width 64 output 131 \src1_i
+ wire width 64 output 158 \src1_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 6 output 132 \rd__rel$54
+ wire width 6 output 159 \rd__rel$70
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 6 output 133 \rd__go$55
+ wire width 6 output 160 \rd__go$71
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
- wire width 64 output 134 \src1_i$56
+ wire width 64 output 161 \src1_i$72
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 6 output 135 \rd__rel$57
+ wire width 4 output 162 \rd__rel$73
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 6 output 136 \rd__go$58
+ wire width 4 output 163 \rd__go$74
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
- wire width 64 output 137 \src1_i$59
+ wire width 64 output 164 \src1_i$75
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 2 output 138 \rd__rel$60
+ wire width 2 output 165 \rd__rel$76
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 2 output 139 \rd__go$61
+ wire width 2 output 166 \rd__go$77
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
- wire width 64 output 140 \src1_i$62
+ wire width 64 output 167 \src1_i$78
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 6 output 141 \rd__rel$63
+ wire width 6 output 168 \rd__rel$79
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 6 output 142 \rd__go$64
+ wire width 6 output 169 \rd__go$80
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
- wire width 64 output 143 \src1_i$65
+ wire width 64 output 170 \src1_i$81
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 4 output 144 \rd__rel$66
+ wire width 3 output 171 \rd__rel$82
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 4 output 145 \rd__go$67
+ wire width 3 output 172 \rd__go$83
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
- wire width 64 output 146 \src1_i$68
+ wire width 64 output 173 \src1_i$84
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 3 output 147 \rd__rel$69
+ wire width 4 output 174 \rd__rel$85
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 3 output 148 \rd__go$70
+ wire width 4 output 175 \rd__go$86
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
- wire width 64 output 149 \src1_i$71
+ wire width 64 output 176 \src1_i$87
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+ wire width 3 output 177 \rd__rel$88
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+ wire width 3 output 178 \rd__go$89
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
+ wire width 64 output 179 \src1_i$90
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 5 output 150 \reg2
+ wire width 5 output 180 \reg2
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
+ wire width 64 output 181 \src2_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
- wire width 64 output 151 \src2_i
+ wire width 64 output 182 \src2_i$91
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
- wire width 64 output 152 \src2_i$72
+ wire width 64 output 183 \src2_i$92
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
- wire width 64 output 153 \src2_i$73
+ wire width 64 output 184 \src2_i$93
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
- wire width 64 output 154 \src2_i$74
+ wire width 64 output 185 \src2_i$94
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
- wire width 64 output 155 \src2_i$75
+ wire width 64 output 186 \src2_i$95
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
- wire width 64 output 156 \src2_i$76
+ wire width 64 output 187 \src2_i$96
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 5 output 157 \reg3
+ wire width 5 output 188 \reg3
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
- wire width 64 output 158 \src3_i
+ wire width 64 output 189 \src3_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 3 output 159 \cr_in1
+ wire width 3 output 190 \cr_in1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 4 output 160 \rd__rel$77
+ wire width 3 output 191 \rd__rel$97
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 4 output 161 \rd__go$78
+ wire width 3 output 192 \rd__go$98
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 3 output 162 \cr_in2
+ wire width 3 output 193 \cr_in2
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 3 output 163 \cr_in2$79
+ wire width 3 output 194 \cr_in2$99
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 3 output 164 \fast1
+ wire width 3 output 195 \fast1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
- wire width 64 output 165 \src1_i$80
+ wire width 64 output 196 \src1_i$100
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 3 output 166 \fast2
+ wire width 3 output 197 \fast2
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
- wire width 64 output 167 \src2_i$81
+ wire width 64 output 198 \src2_i$101
attribute \enum_base_type "SPR"
attribute \enum_value_0000000001 "XER"
attribute \enum_value_0000000011 "DSCR"
attribute \enum_value_1110000010 "PPR32"
attribute \enum_value_1111111111 "PIR"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 10 output 168 \spr1
+ wire width 10 output 199 \spr1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
- wire width 64 output 169 \src2_i$82
+ wire width 64 output 200 \src2_i$102
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 5 output 170 \rego
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 5 output 171 \wr__rel
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 5 output 172 \wr__go
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 5 \wr__go$next
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 3 output 173 \wr__rel$83
+ wire width 5 output 201 \rego
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 3 output 174 \wr__go$84
+ wire width 5 output 202 \wr__rel
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 3 \wr__go$84$next
+ wire width 5 output 203 \wr__go
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 5 output 175 \wr__rel$85
+ wire width 3 output 204 \wr__rel$103
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 5 output 176 \wr__go$86
+ wire width 3 output 205 \wr__go$104
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 5 \wr__go$86$next
+ wire width 5 output 206 \wr__rel$105
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 3 output 177 \wr__rel$87
+ wire width 5 output 207 \wr__go$106
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 3 output 178 \wr__go$88
+ wire width 3 output 208 \wr__rel$107
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 3 \wr__go$88$next
+ wire width 3 output 209 \wr__go$108
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 6 output 179 \wr__rel$89
+ wire width 6 output 210 \wr__rel$109
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 6 output 180 \wr__go$90
+ wire width 6 output 211 \wr__go$110
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 6 \wr__go$90$next
+ wire width 4 output 212 \wr__rel$111
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 3 output 181 \wr__rel$91
+ wire width 4 output 213 \wr__go$112
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 3 output 182 \wr__go$92
+ wire width 3 output 214 \wr__rel$113
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 3 \wr__go$92$next
+ wire width 3 output 215 \wr__go$114
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 input 183 \o_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 2 output 184 \wr__rel$93
+ wire width 1 input 216 \o_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 2 output 185 \wr__go$94
+ wire width 2 output 217 \wr__rel$115
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 2 \wr__go$94$next
+ wire width 2 output 218 \wr__go$116
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
+ wire width 64 output 219 \dest1_o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
+ wire width 64 output 220 \dest1_o$117
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
+ wire width 64 output 221 \dest1_o$118
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
+ wire width 64 output 222 \dest1_o$119
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
+ wire width 64 output 223 \dest1_o$120
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
+ wire width 64 output 224 \dest1_o$121
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
+ wire width 64 output 225 \dest1_o$122
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 output 186 \o
+ wire width 64 output 226 \o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 5 output 187 \ea
+ wire width 5 output 227 \ea
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 input 188 \ea_ok
+ wire width 1 input 228 \ea_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 output 189 \ea$95
+ wire width 64 output 229 \ea$123
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 3 output 190 \fasto1
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 3 output 191 \wr__rel$96
+ wire width 3 output 230 \cr_out
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 3 output 231 \fasto1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 3 output 192 \wr__go$97
+ wire width 3 output 232 \wr__rel$124
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 3 \wr__go$97$next
+ wire width 3 output 233 \wr__go$125
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
+ wire width 64 output 234 \dest1_o$126
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 3 output 193 \fasto2
+ wire width 3 output 235 \fasto2
attribute \enum_base_type "SPR"
attribute \enum_value_0000000001 "XER"
attribute \enum_value_0000000011 "DSCR"
attribute \enum_value_1110000010 "PPR32"
attribute \enum_value_1111111111 "PIR"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 10 output 194 \spro
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219"
- wire width 32 output 195 \opcode_in
+ wire width 10 output 236 \spro
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:229"
+ wire width 32 output 237 \opcode_in
attribute \enum_base_type "In1Sel"
attribute \enum_value_000 "NONE"
attribute \enum_value_001 "RA"
attribute \enum_value_011 "SPR"
attribute \enum_value_100 "RS"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
- wire width 3 output 196 \in1_sel
+ wire width 3 output 238 \in1_sel
attribute \enum_base_type "In2Sel"
attribute \enum_value_0000 "NONE"
attribute \enum_value_0001 "RB"
attribute \enum_value_1100 "SPR"
attribute \enum_value_1101 "RS"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
- wire width 4 output 197 \in2_sel
+ wire width 4 output 239 \in2_sel
attribute \enum_base_type "In3Sel"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "RS"
attribute \enum_value_10 "RB"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
- wire width 2 output 198 \in3_sel
+ wire width 2 output 240 \in3_sel
attribute \enum_base_type "OutSel"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "RT"
attribute \enum_value_10 "RA"
attribute \enum_value_11 "SPR"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
- wire width 2 output 199 \out_sel
+ wire width 2 output 241 \out_sel
attribute \enum_base_type "RC"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "RC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
- wire width 2 output 200 \rc_sel
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
+ wire width 2 output 242 \rc_sel
attribute \enum_base_type "CRInSel"
attribute \enum_value_000 "NONE"
attribute \enum_value_001 "CR0"
attribute \enum_value_101 "BC"
attribute \enum_value_110 "WHOLE_REG"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
- wire width 3 output 201 \cr_in
+ wire width 3 output 243 \cr_in
attribute \enum_base_type "CROutSel"
attribute \enum_value_000 "NONE"
attribute \enum_value_001 "CR0"
attribute \enum_value_011 "BT"
attribute \enum_value_100 "WHOLE_REG"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
- wire width 3 output 202 \cr_out$98
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:36"
- wire width 64 output 203 \nia
- attribute \enum_base_type "Function"
- attribute \enum_value_00000000000 "NONE"
- attribute \enum_value_00000000010 "ALU"
- attribute \enum_value_00000000100 "LDST"
- attribute \enum_value_00000001000 "SHIFT_ROT"
- attribute \enum_value_00000010000 "LOGICAL"
- attribute \enum_value_00000100000 "BRANCH"
- attribute \enum_value_00001000000 "CR"
- attribute \enum_value_00010000000 "TRAP"
- attribute \enum_value_00100000000 "MUL"
- attribute \enum_value_01000000000 "DIV"
- attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119"
- wire width 11 output 204 \function_unit
- attribute \enum_base_type "InternalOp"
+ wire width 3 output 244 \cr_out$127
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
+ attribute \enum_value_1001010 "OP_MTMSR"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
- wire width 7 output 205 \internal_op
+ wire width 7 output 245 \internal_op
+ attribute \enum_base_type "Function"
+ attribute \enum_value_00000000000 "NONE"
+ attribute \enum_value_00000000010 "ALU"
+ attribute \enum_value_00000000100 "LDST"
+ attribute \enum_value_00000001000 "SHIFT_ROT"
+ attribute \enum_value_00000010000 "LOGICAL"
+ attribute \enum_value_00000100000 "BRANCH"
+ attribute \enum_value_00001000000 "CR"
+ attribute \enum_value_00010000000 "TRAP"
+ attribute \enum_value_00100000000 "MUL"
+ attribute \enum_value_01000000000 "DIV"
+ attribute \enum_value_10000000000 "SPR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119"
+ wire width 11 output 246 \function_unit
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 247 \rego_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 206 \rego_ok
+ wire width 1 output 248 \ea_ok$128
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 207 \ea_ok$99
+ wire width 1 output 249 \spro_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 208 \spro_ok
+ wire width 1 output 250 \fasto1_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 209 \fasto1_ok
+ wire width 1 output 251 \fasto2_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 210 \fasto2_ok
+ wire width 1 output 252 \cr_out_ok
attribute \enum_base_type "LdstLen"
attribute \enum_value_0000 "NONE"
attribute \enum_value_0001 "is1B"
attribute \enum_value_0100 "is4B"
attribute \enum_value_1000 "is8B"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
- wire width 4 output 211 \ldst_len
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 212 \inv_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 213 \inv_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 214 \cry_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 215 \is_32b
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 216 \sgn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 217 \lk$100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 218 \br
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 219 \sgn_ext
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 220 \upd
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:35"
- wire width 8 output 221 \asmcode
+ wire width 4 output 253 \ldst_len
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 254 \inv_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 255 \inv_out
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 256 \cry_out
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 257 \is_32b
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 258 \sgn
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 259 \lk$129
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 260 \br
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 261 \sgn_ext
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:82"
+ wire width 1 output 262 \xer_out
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:71"
+ wire width 8 output 263 \asmcode
attribute \enum_base_type "Form"
attribute \enum_value_00000 "NONE"
attribute \enum_value_00001 "I"
attribute \enum_value_11011 "Z22"
attribute \enum_value_11100 "Z23"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
- wire width 5 output 222 \form
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 223 \rsrv
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 224 \sgl_pipe
+ wire width 5 output 264 \form
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 265 \rsrv
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 266 \sgl_pipe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
- wire width 8 output 225 \asmcode$101
+ wire width 8 output 267 \asmcode$130
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96"
- wire width 1 input 226 \go_die_i
+ wire width 1 input 268 \go_die_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
- wire width 1 input 227 \shadown_i
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
- wire width 64 output 228 \dest1_o
+ wire width 1 input 269 \shadown_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96"
- wire width 1 input 229 \go_die_i$102
+ wire width 1 input 270 \go_die_i$131
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
- wire width 1 input 230 \shadown_i$103
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
- wire width 64 output 231 \dest1_o$104
+ wire width 1 input 271 \shadown_i$132
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96"
- wire width 1 input 232 \go_die_i$105
+ wire width 1 input 272 \go_die_i$133
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
- wire width 1 input 233 \shadown_i$106
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
- wire width 64 output 234 \dest1_o$107
+ wire width 1 input 273 \shadown_i$134
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96"
- wire width 1 input 235 \go_die_i$108
+ wire width 1 input 274 \go_die_i$135
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
- wire width 1 input 236 \shadown_i$109
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
- wire width 64 output 237 \dest1_o$110
+ wire width 1 input 275 \shadown_i$136
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96"
- wire width 1 input 238 \go_die_i$111
+ wire width 1 input 276 \go_die_i$137
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
- wire width 1 input 239 \shadown_i$112
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
- wire width 64 output 240 \dest1_o$113
+ wire width 1 input 277 \shadown_i$138
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96"
- wire width 1 input 241 \go_die_i$114
+ wire width 1 input 278 \go_die_i$139
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
- wire width 1 input 242 \shadown_i$115
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
- wire width 64 output 243 \dest1_o$116
+ wire width 1 input 279 \shadown_i$140
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96"
- wire width 1 input 244 \go_die_i$117
+ wire width 1 input 280 \go_die_i$141
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
- wire width 1 input 245 \shadown_i$118
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
- wire width 64 output 246 \dest1_o$119
+ wire width 1 input 281 \shadown_i$142
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96"
+ wire width 1 input 282 \go_die_i$143
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
+ wire width 1 input 283 \shadown_i$144
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96"
- wire width 1 input 247 \go_die_i$120
+ wire width 1 input 284 \go_die_i$145
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:112"
- wire width 1 output 248 \load_mem_o
+ wire width 1 output 285 \load_mem_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:113"
- wire width 1 output 249 \stwd_mem_o
+ wire width 1 output 286 \stwd_mem_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
- wire width 1 input 250 \shadown_i$121
+ wire width 1 input 287 \shadown_i$146
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:95"
- wire width 1 output 251 \ldst_port0_is_ld_i
+ wire width 1 output 288 \ldst_port0_is_ld_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:96"
- wire width 1 output 252 \ldst_port0_is_st_i
+ wire width 1 output 289 \ldst_port0_is_st_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99"
- wire width 4 output 253 \ldst_port0_data_len
+ wire width 4 output 290 \ldst_port0_data_len
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 96 output 254 \ldst_port0_addr_i
+ wire width 96 output 291 \ldst_port0_addr_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 255 \ldst_port0_addr_i_ok
+ wire width 1 output 292 \ldst_port0_addr_i_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:107"
- wire width 1 output 256 \ldst_port0_addr_exc_o
+ wire width 1 output 293 \ldst_port0_addr_exc_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:106"
- wire width 1 output 257 \ldst_port0_addr_ok_o
+ wire width 1 output 294 \ldst_port0_addr_ok_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 output 258 \ldst_port0_ld_data_o
+ wire width 64 output 295 \ldst_port0_ld_data_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 259 \ldst_port0_ld_data_o_ok
+ wire width 1 output 296 \ldst_port0_ld_data_o_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 output 260 \ldst_port0_st_data_i
+ wire width 64 output 297 \ldst_port0_st_data_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 261 \ldst_port0_st_data_i_ok
+ wire width 1 output 298 \ldst_port0_st_data_i_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:95"
- wire width 1 output 262 \ldst_port0_is_ld_i$122
+ wire width 1 output 299 \ldst_port0_is_ld_i$147
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102"
- wire width 1 output 263 \ldst_port0_busy_o
+ wire width 1 output 300 \ldst_port0_busy_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:96"
- wire width 1 output 264 \ldst_port0_is_st_i$123
+ wire width 1 output 301 \ldst_port0_is_st_i$148
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99"
- wire width 4 output 265 \ldst_port0_data_len$124
+ wire width 4 output 302 \ldst_port0_data_len$149
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 48 output 266 \ldst_port0_addr_i$125
+ wire width 48 output 303 \ldst_port0_addr_i$150
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 267 \ldst_port0_addr_i_ok$126
+ wire width 1 output 304 \ldst_port0_addr_i_ok$151
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:27"
- wire width 8 output 268 \x_mask_i
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:26"
- wire width 48 output 269 \x_addr_i
+ wire width 48 output 306 \x_addr_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:106"
- wire width 1 output 270 \ldst_port0_addr_ok_o$127
+ wire width 1 output 307 \ldst_port0_addr_ok_o$152
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:45"
- wire width 64 output 271 \m_ld_data_o
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 output 272 \ldst_port0_ld_data_o$128
+ wire width 64 output 309 \ldst_port0_ld_data_o$153
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 273 \ldst_port0_ld_data_o_ok$129
+ wire width 1 output 310 \ldst_port0_ld_data_o_ok$154
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:42"
- wire width 1 output 274 \x_busy_o
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 275 \ldst_port0_st_data_i_ok$130
+ wire width 1 output 312 \ldst_port0_st_data_i_ok$155
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 output 276 \ldst_port0_st_data_i$131
+ wire width 64 output 313 \ldst_port0_st_data_i$156
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:30"
- wire width 64 output 277 \x_st_data_i
+ wire width 64 output 314 \x_st_data_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:107"
- wire width 1 input 278 \ldst_port0_addr_exc_o$132
+ wire width 1 input 315 \ldst_port0_addr_exc_o$157
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:28"
- wire width 1 output 279 \x_ld_i
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:29"
- wire width 1 output 280 \x_st_i
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:37"
- wire width 1 output 281 \m_valid_i
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:33"
- wire width 1 output 282 \x_valid_i
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:103"
- wire width 1 output 283 \ldst_port0_go_die_i
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:103"
- wire width 1 input 284 \ldst_port0_go_die_i$133
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102"
- wire width 1 output 285 \ldst_port0_busy_o$134
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
- wire width 1 output 286 \dbus__cyc
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32"
- wire width 1 input 287 \x_stall_i
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
- wire width 1 input 288 \dbus__ack
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
- wire width 1 input 289 \dbus__err
+ wire width 1 input 326 \dbus__err
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
- wire width 1 output 290 \dbus__stb
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
- wire width 64 input 291 \dbus__dat_r
+ wire width 64 input 328 \dbus__dat_r
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
- wire width 45 output 292 \dbus__adr
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
- wire width 8 output 293 \dbus__sel
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
- wire width 1 output 294 \dbus__we
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
- wire width 64 output 295 \dbus__dat_w
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:36"
- wire width 1 input 296 \m_stall_i
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:50"
- wire width 1 output 297 \m_load_err_o
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:51"
- wire width 1 output 298 \m_store_err_o
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:52"
- wire width 45 output 299 \m_badaddr_o
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:43"
- wire width 1 output 300 \m_busy_o
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cell \pdecode2 \pdecode2
connect \bigendian \bigendian
connect \raw_opcode_in \raw_opcode_in
- connect \fn_unit \fn_unit
+ connect \msr \msr
+ connect \cia \cia
connect \insn_type \insn_type
+ connect \fn_unit \fn_unit
connect \imm \imm
connect \imm_ok \imm_ok
- connect \lk \lk
connect \rc \rc
connect \rc_ok \rc_ok
connect \oe \oe
connect \invert_a \invert_a
connect \zero_a \zero_a
connect \invert_out \invert_out
- connect \cr_out \cr_out
- connect \cr_out_ok \cr_out_ok
+ connect \write_cr0 \write_cr0
connect \input_carry \input_carry
connect \output_carry \output_carry
- connect \input_cr \input_cr
- connect \output_cr \output_cr
connect \is_32bit \is_32bit
connect \is_signed \is_signed
connect \data_len \data_len
connect \insn \insn
- connect \byte_reverse \byte_reverse
- connect \sign_extend \sign_extend
connect \reg1_ok \reg1_ok
connect \reg2_ok \reg2_ok
+ connect \xer_in \xer_in
connect \read_cr_whole \read_cr_whole
connect \write_cr_whole \write_cr_whole
connect \cr_in1_ok \cr_in1_ok
connect \cr_in2_ok \cr_in2_ok
- connect \cr_in2_ok$1 \cr_in2_ok$5
+ connect \cr_in2_ok$1 \cr_in2_ok$7
+ connect \cia$2 \cia$8
+ connect \lk \lk
connect \fast1_ok \fast1_ok
connect \fast2_ok \fast2_ok
+ connect \msr$3 \msr$18
connect \traptype \traptype
connect \trapaddr \trapaddr
connect \spr1_ok \spr1_ok
+ connect \input_cr \input_cr
+ connect \output_cr \output_cr
connect \reg3_ok \reg3_ok
- connect \update \update
+ connect \byte_reverse \byte_reverse
+ connect \sign_extend \sign_extend
+ connect \ldst_mode \ldst_mode
connect \reg1 \reg1
connect \reg2 \reg2
connect \reg3 \reg3
connect \cr_in1 \cr_in1
connect \cr_in2 \cr_in2
- connect \cr_in2$2 \cr_in2$79
+ connect \cr_in2$4 \cr_in2$99
connect \fast1 \fast1
connect \fast2 \fast2
connect \spr1 \spr1
connect \rego \rego
connect \ea \ea
+ connect \cr_out \cr_out
connect \fasto1 \fasto1
connect \fasto2 \fasto2
connect \spro \spro
connect \out_sel \out_sel
connect \rc_sel \rc_sel
connect \cr_in \cr_in
- connect \cr_out$3 \cr_out$98
- connect \nia \nia
- connect \function_unit \function_unit
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connect \internal_op \internal_op
+ connect \function_unit \function_unit
connect \rego_ok \rego_ok
- connect \ea_ok \ea_ok$99
+ connect \ea_ok \ea_ok$128
connect \spro_ok \spro_ok
connect \fasto1_ok \fasto1_ok
connect \fasto2_ok \fasto2_ok
+ connect \cr_out_ok \cr_out_ok
connect \ldst_len \ldst_len
connect \inv_a \inv_a
connect \inv_out \inv_out
connect \cry_out \cry_out
connect \is_32b \is_32b
connect \sgn \sgn
- connect \lk$4 \lk$100
+ connect \lk$6 \lk$129
connect \br \br
connect \sgn_ext \sgn_ext
- connect \upd \upd
+ connect \xer_out \xer_out
connect \asmcode \asmcode
connect \form \form
connect \rsrv \rsrv
connect \sgl_pipe \sgl_pipe
- connect \asmcode$5 \asmcode$101
+ connect \asmcode$7 \asmcode$130
end
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wire width 64 \fus_oper_i__imm_data__imm
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wire width 1 \fus_oper_i__imm_data__imm_ok
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wire width 1 \fus_oper_i__rc__rc
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wire width 1 \fus_oper_i__rc__rc_ok
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wire width 1 \fus_oper_i__oe__oe
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wire width 1 \fus_oper_i__oe__oe_ok
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:92"
wire width 4 \fus_rdmaskn
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:92"
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:92"
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:92"
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:92"
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- attribute \enum_base_type "Function"
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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:92"
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- connect \oper_i__fn_unit$48 \oper_i__fn_unit$32
- connect \oper_i__insn$49 \oper_i__insn$33
- connect \oper_i__is_32bit$50 \oper_i__is_32bit$34
- connect \issue_i$51 \issue_i$35
- connect \busy_o$52 \busy_o$36
- connect \rdmaskn$53 \fus_rdmaskn$151
- connect \oper_i__insn_type$54 \oper_i__insn_type$37
- connect \oper_i__fn_unit$55 \fus_oper_i__fn_unit$152
- connect \oper_i__imm_data__imm$56 \fus_oper_i__imm_data__imm$153
- connect \oper_i__imm_data__imm_ok$57 \fus_oper_i__imm_data__imm_ok$154
- connect \oper_i__rc__rc$58 \fus_oper_i__rc__rc$155
- connect \oper_i__rc__rc_ok$59 \fus_oper_i__rc__rc_ok$156
- connect \oper_i__oe__oe$60 \fus_oper_i__oe__oe$157
- connect \oper_i__oe__oe_ok$61 \fus_oper_i__oe__oe_ok$158
- connect \oper_i__write_cr__data$62 \fus_oper_i__write_cr__data$159
- connect \oper_i__write_cr__ok$63 \fus_oper_i__write_cr__ok$160
- connect \oper_i__input_carry$64 \oper_i__input_carry$38
- connect \oper_i__output_carry$65 \oper_i__output_carry$39
- connect \oper_i__input_cr$66 \oper_i__input_cr$40
- connect \oper_i__output_cr$67 \oper_i__output_cr$41
- connect \oper_i__is_32bit$68 \oper_i__is_32bit$42
- connect \oper_i__is_signed$69 \oper_i__is_signed$43
- connect \oper_i__insn$70 \fus_oper_i__insn$161
- connect \issue_i$71 \issue_i$44
- connect \busy_o$72 \busy_o$45
- connect \rdmaskn$73 \fus_rdmaskn$162
- connect \oper_i__insn_type$74 \oper_i__insn_type$46
- connect \oper_i__imm_data__imm$75 \fus_oper_i__imm_data__imm$163
- connect \oper_i__imm_data__imm_ok$76 \fus_oper_i__imm_data__imm_ok$164
- connect \oper_i__zero_a$77 \oper_i__zero_a
- connect \oper_i__is_32bit$78 \oper_i__is_32bit$47
- connect \oper_i__is_signed$79 \oper_i__is_signed$48
- connect \oper_i__data_len$80 \oper_i__data_len$49
- connect \oper_i__byte_reverse$81 \oper_i__byte_reverse$50
- connect \oper_i__sign_extend$82 \oper_i__sign_extend$51
- connect \oper_i__update \oper_i__update
- connect \issue_i$83 \issue_i$52
- connect \busy_o$84 \busy_o$53
- connect \rdmaskn$85 \fus_rdmaskn$165
+ connect \issue_i$21 \issue_i$21
+ connect \busy_o$22 \busy_o$22
+ connect \rdmaskn$23 \fus_rdmaskn$164
+ connect \oper_i__insn_type$24 \oper_i__insn_type$23
+ connect \oper_i__fn_unit$25 \oper_i__fn_unit$24
+ connect \oper_i__imm_data__imm$26 \fus_oper_i__imm_data__imm$165
+ connect \oper_i__imm_data__imm_ok$27 \fus_oper_i__imm_data__imm_ok$166
+ connect \oper_i__rc__rc$28 \fus_oper_i__rc__rc$167
+ connect \oper_i__rc__rc_ok$29 \fus_oper_i__rc__rc_ok$168
+ connect \oper_i__oe__oe$30 \fus_oper_i__oe__oe$169
+ connect \oper_i__oe__oe_ok$31 \fus_oper_i__oe__oe_ok$170
+ connect \oper_i__invert_a$32 \oper_i__invert_a$25
+ connect \oper_i__zero_a$33 \oper_i__zero_a$26
+ connect \oper_i__input_carry$34 \oper_i__input_carry$27
+ connect \oper_i__invert_out$35 \oper_i__invert_out$28
+ connect \oper_i__write_cr0$36 \oper_i__write_cr0$29
+ connect \oper_i__output_carry$37 \oper_i__output_carry$30
+ connect \oper_i__is_32bit$38 \oper_i__is_32bit$31
+ connect \oper_i__is_signed$39 \oper_i__is_signed$32
+ connect \oper_i__data_len$40 \oper_i__data_len$33
+ connect \oper_i__insn$41 \oper_i__insn$34
+ connect \issue_i$42 \issue_i$35
+ connect \busy_o$43 \busy_o$36
+ connect \rdmaskn$44 \fus_rdmaskn$171
+ connect \oper_i__insn_type$45 \oper_i__insn_type$37
+ connect \oper_i__fn_unit$46 \oper_i__fn_unit$38
+ connect \oper_i__insn$47 \oper_i__insn$39
+ connect \oper_i__is_32bit$48 \oper_i__is_32bit$40
+ connect \issue_i$49 \issue_i$41
+ connect \busy_o$50 \busy_o$42
+ connect \rdmaskn$51 \fus_rdmaskn$172
+ connect \oper_i__insn_type$52 \oper_i__insn_type$43
+ connect \oper_i__fn_unit$53 \oper_i__fn_unit$44
+ connect \oper_i__imm_data__imm$54 \fus_oper_i__imm_data__imm$173
+ connect \oper_i__imm_data__imm_ok$55 \fus_oper_i__imm_data__imm_ok$174
+ connect \oper_i__rc__rc$56 \fus_oper_i__rc__rc$175
+ connect \oper_i__rc__rc_ok$57 \fus_oper_i__rc__rc_ok$176
+ connect \oper_i__oe__oe$58 \fus_oper_i__oe__oe$177
+ connect \oper_i__oe__oe_ok$59 \fus_oper_i__oe__oe_ok$178
+ connect \oper_i__invert_a$60 \oper_i__invert_a$45
+ connect \oper_i__zero_a$61 \oper_i__zero_a$46
+ connect \oper_i__invert_out$62 \oper_i__invert_out$47
+ connect \oper_i__write_cr0$63 \oper_i__write_cr0$48
+ connect \oper_i__is_32bit$64 \oper_i__is_32bit$49
+ connect \oper_i__is_signed$65 \oper_i__is_signed$50
+ connect \oper_i__insn$66 \oper_i__insn$51
+ connect \issue_i$67 \issue_i$52
+ connect \busy_o$68 \busy_o$53
+ connect \rdmaskn$69 \fus_rdmaskn$179
+ connect \oper_i__insn_type$70 \oper_i__insn_type$54
+ connect \oper_i__fn_unit$71 \oper_i__fn_unit$55
+ connect \oper_i__imm_data__imm$72 \fus_oper_i__imm_data__imm$180
+ connect \oper_i__imm_data__imm_ok$73 \fus_oper_i__imm_data__imm_ok$181
+ connect \oper_i__rc__rc$74 \fus_oper_i__rc__rc$182
+ connect \oper_i__rc__rc_ok$75 \fus_oper_i__rc__rc_ok$183
+ connect \oper_i__oe__oe$76 \fus_oper_i__oe__oe$184
+ connect \oper_i__oe__oe_ok$77 \fus_oper_i__oe__oe_ok$185
+ connect \oper_i__input_carry$78 \oper_i__input_carry$56
+ connect \oper_i__output_carry$79 \oper_i__output_carry$57
+ connect \oper_i__input_cr \oper_i__input_cr
+ connect \oper_i__output_cr \oper_i__output_cr
+ connect \oper_i__is_32bit$80 \oper_i__is_32bit$58
+ connect \oper_i__is_signed$81 \oper_i__is_signed$59
+ connect \oper_i__insn$82 \oper_i__insn$60
+ connect \issue_i$83 \issue_i$61
+ connect \busy_o$84 \busy_o$62
+ connect \rdmaskn$85 \fus_rdmaskn$186
+ connect \oper_i__insn_type$86 \oper_i__insn_type$63
+ connect \oper_i__imm_data__imm$87 \fus_oper_i__imm_data__imm$187
+ connect \oper_i__imm_data__imm_ok$88 \fus_oper_i__imm_data__imm_ok$188
+ connect \oper_i__zero_a$89 \oper_i__zero_a$64
+ connect \oper_i__rc__rc$90 \fus_oper_i__rc__rc$189
+ connect \oper_i__rc__rc_ok$91 \fus_oper_i__rc__rc_ok$190
+ connect \oper_i__oe__oe$92 \fus_oper_i__oe__oe$191
+ connect \oper_i__oe__oe_ok$93 \fus_oper_i__oe__oe_ok$192
+ connect \oper_i__is_32bit$94 \oper_i__is_32bit$65
+ connect \oper_i__is_signed$95 \oper_i__is_signed$66
+ connect \oper_i__data_len$96 \oper_i__data_len$67
+ connect \oper_i__byte_reverse \oper_i__byte_reverse
+ connect \oper_i__sign_extend \oper_i__sign_extend
+ connect \oper_i__ldst_mode \oper_i__ldst_mode
+ connect \issue_i$97 \issue_i$68
+ connect \busy_o$98 \busy_o$69
+ connect \rdmaskn$99 \fus_rdmaskn$193
connect \rd__rel \rd__rel
connect \rd__go \rd__go
connect \src1_i \src1_i
- connect \rd__rel$86 \rd__rel$54
- connect \rd__go$87 \rd__go$55
- connect \src1_i$88 \src1_i$56
- connect \rd__rel$89 \rd__rel$57
- connect \rd__go$90 \rd__go$58
- connect \src1_i$91 \src1_i$59
- connect \rd__rel$92 \rd__rel$60
- connect \rd__go$93 \rd__go$61
- connect \src1_i$94 \src1_i$62
- connect \rd__rel$95 \rd__rel$63
- connect \rd__go$96 \rd__go$64
- connect \src1_i$97 \src1_i$65
- connect \rd__rel$98 \rd__rel$66
- connect \rd__go$99 \rd__go$67
- connect \src1_i$100 \src1_i$68
- connect \rd__rel$101 \rd__rel$69
- connect \rd__go$102 \rd__go$70
- connect \src1_i$103 \src1_i$71
+ connect \rd__rel$100 \rd__rel$70
+ connect \rd__go$101 \rd__go$71
+ connect \src1_i$102 \src1_i$72
+ connect \rd__rel$103 \rd__rel$73
+ connect \rd__go$104 \rd__go$74
+ connect \src1_i$105 \src1_i$75
+ connect \rd__rel$106 \rd__rel$76
+ connect \rd__go$107 \rd__go$77
+ connect \src1_i$108 \src1_i$78
+ connect \rd__rel$109 \rd__rel$79
+ connect \rd__go$110 \rd__go$80
+ connect \src1_i$111 \src1_i$81
+ connect \rd__rel$112 \rd__rel$82
+ connect \rd__go$113 \rd__go$83
+ connect \src1_i$114 \src1_i$84
+ connect \rd__rel$115 \rd__rel$85
+ connect \rd__go$116 \rd__go$86
+ connect \src1_i$117 \src1_i$87
+ connect \rd__rel$118 \rd__rel$88
+ connect \rd__go$119 \rd__go$89
+ connect \src1_i$120 \src1_i$90
connect \src2_i \src2_i
- connect \src2_i$104 \src2_i$72
- connect \src2_i$105 \src2_i$73
- connect \src2_i$106 \src2_i$74
- connect \src2_i$107 \src2_i$75
- connect \src2_i$108 \src2_i$76
+ connect \src2_i$121 \src2_i$91
+ connect \src2_i$122 \src2_i$92
+ connect \src2_i$123 \src2_i$93
+ connect \src2_i$124 \src2_i$94
+ connect \src2_i$125 \src2_i$95
+ connect \src2_i$126 \src2_i$96
connect \src3_i \fus_src3_i
- connect \src3_i$109 \src3_i
- connect \src3_i$110 \fus_src3_i$166
+ connect \src3_i$127 \src3_i
+ connect \src3_i$128 \fus_src3_i$194
connect \src4_i \fus_src4_i
- connect \src4_i$111 \fus_src4_i$167
+ connect \src3_i$129 \fus_src3_i$195
+ connect \src4_i$130 \fus_src4_i$196
connect \src6_i \fus_src6_i
- connect \src4_i$112 \fus_src4_i$168
+ connect \src4_i$131 \fus_src4_i$197
connect \src5_i \fus_src5_i
- connect \src3_i$113 \fus_src3_i$169
- connect \src4_i$114 \fus_src4_i$170
- connect \rd__rel$115 \rd__rel$77
- connect \rd__go$116 \rd__go$78
- connect \src3_i$117 \fus_src3_i$171
- connect \src5_i$118 \fus_src5_i$172
- connect \src6_i$119 \fus_src6_i$173
- connect \src1_i$120 \src1_i$80
- connect \src3_i$121 \fus_src3_i$174
- connect \src3_i$122 \fus_src3_i$175
- connect \src2_i$123 \src2_i$81
- connect \src4_i$124 \fus_src4_i$176
- connect \src4_i$125 \fus_src4_i$177
- connect \src5_i$126 \fus_src5_i$178
- connect \src6_i$127 \fus_src6_i$179
- connect \src2_i$128 \src2_i$82
+ connect \src3_i$132 \fus_src3_i$198
+ connect \src4_i$133 \fus_src4_i$199
+ connect \rd__rel$134 \rd__rel$97
+ connect \rd__go$135 \rd__go$98
+ connect \src3_i$136 \fus_src3_i$200
+ connect \src5_i$137 \fus_src5_i$201
+ connect \src6_i$138 \fus_src6_i$202
+ connect \src1_i$139 \src1_i$100
+ connect \src3_i$140 \fus_src3_i$203
+ connect \src3_i$141 \fus_src3_i$204
+ connect \src2_i$142 \src2_i$101
+ connect \src4_i$143 \fus_src4_i$205
+ connect \src2_i$144 \src2_i$102
connect \o_ok \fus_o_ok
connect \wr__rel \wr__rel
connect \wr__go \wr__go
- connect \o_ok$129 \fus_o_ok$180
- connect \wr__rel$130 \wr__rel$83
- connect \wr__go$131 \wr__go$84
- connect \o_ok$132 \fus_o_ok$181
- connect \wr__rel$133 \wr__rel$85
- connect \wr__go$134 \wr__go$86
- connect \o_ok$135 \fus_o_ok$182
- connect \wr__rel$136 \wr__rel$87
- connect \wr__go$137 \wr__go$88
- connect \o_ok$138 \fus_o_ok$183
- connect \wr__rel$139 \wr__rel$89
- connect \wr__go$140 \wr__go$90
- connect \o_ok$141 \fus_o_ok$184
- connect \wr__rel$142 \wr__rel$91
- connect \wr__go$143 \wr__go$92
- connect \wr__rel$144 \wr__rel$93
- connect \wr__go$145 \wr__go$94
- connect \o \fus_o
- connect \o$146 \fus_o$185
- connect \o$147 \fus_o$186
- connect \o$148 \fus_o$187
- connect \o$149 \fus_o$188
- connect \o$150 \fus_o$189
- connect \o$151 \o
- connect \ea \ea$95
+ connect \o_ok$145 \fus_o_ok$206
+ connect \wr__rel$146 \wr__rel$103
+ connect \wr__go$147 \wr__go$104
+ connect \o_ok$148 \fus_o_ok$207
+ connect \wr__rel$149 \wr__rel$105
+ connect \wr__go$150 \wr__go$106
+ connect \o_ok$151 \fus_o_ok$208
+ connect \wr__rel$152 \wr__rel$107
+ connect \wr__go$153 \wr__go$108
+ connect \o_ok$154 \fus_o_ok$209
+ connect \wr__rel$155 \wr__rel$109
+ connect \wr__go$156 \wr__go$110
+ connect \o_ok$157 \fus_o_ok$210
+ connect \wr__rel$158 \wr__rel$111
+ connect \wr__go$159 \wr__go$112
+ connect \o_ok$160 \fus_o_ok$211
+ connect \wr__rel$161 \wr__rel$113
+ connect \wr__go$162 \wr__go$114
+ connect \wr__rel$163 \wr__rel$115
+ connect \wr__go$164 \wr__go$116
+ connect \dest1_o \dest1_o
+ connect \dest1_o$165 \dest1_o$117
+ connect \dest1_o$166 \dest1_o$118
+ connect \dest1_o$167 \dest1_o$119
+ connect \dest1_o$168 \dest1_o$120
+ connect \dest1_o$169 \dest1_o$121
+ connect \dest1_o$170 \dest1_o$122
+ connect \o \o
+ connect \ea \ea$123
connect \full_cr_ok \fus_full_cr_ok
- connect \full_cr \fus_full_cr
+ connect \dest2_o \fus_dest2_o
connect \cr_a_ok \fus_cr_a_ok
- connect \cr_a_ok$152 \fus_cr_a_ok$190
- connect \cr_a_ok$153 \fus_cr_a_ok$191
- connect \cr_a_ok$154 \fus_cr_a_ok$192
- connect \cr_a \fus_cr_a
- connect \cr_a$155 \fus_cr_a$193
- connect \cr_a$156 \fus_cr_a$194
- connect \cr_a$157 \fus_cr_a$195
+ connect \cr_a_ok$171 \fus_cr_a_ok$212
+ connect \cr_a_ok$172 \fus_cr_a_ok$213
+ connect \cr_a_ok$173 \fus_cr_a_ok$214
+ connect \cr_a_ok$174 \fus_cr_a_ok$215
+ connect \dest2_o$175 \fus_dest2_o$216
+ connect \dest3_o \fus_dest3_o
+ connect \dest2_o$176 \fus_dest2_o$217
+ connect \dest2_o$177 \fus_dest2_o$218
+ connect \dest2_o$178 \fus_dest2_o$219
connect \xer_ca_ok \fus_xer_ca_ok
- connect \xer_ca_ok$158 \fus_xer_ca_ok$196
- connect \xer_ca_ok$159 \fus_xer_ca_ok$197
- connect \xer_ca_ok$160 \fus_xer_ca_ok$198
- connect \xer_ca \fus_xer_ca
- connect \xer_ca$161 \fus_xer_ca$199
- connect \xer_ca$162 \fus_xer_ca$200
- connect \xer_ca$163 \fus_xer_ca$201
+ connect \xer_ca_ok$179 \fus_xer_ca_ok$220
+ connect \xer_ca_ok$180 \fus_xer_ca_ok$221
+ connect \xer_ca_ok$181 \fus_xer_ca_ok$222
+ connect \dest3_o$182 \fus_dest3_o$223
+ connect \dest3_o$183 \fus_dest3_o$224
+ connect \dest6_o \fus_dest6_o
+ connect \dest3_o$184 \fus_dest3_o$225
connect \xer_ov_ok \fus_xer_ov_ok
- connect \xer_ov_ok$164 \fus_xer_ov_ok$202
- connect \xer_ov \fus_xer_ov
- connect \xer_ov$165 \fus_xer_ov$203
+ connect \xer_ov_ok$185 \fus_xer_ov_ok$226
+ connect \xer_ov_ok$186 \fus_xer_ov_ok$227
+ connect \dest4_o \fus_dest4_o
+ connect \dest5_o \fus_dest5_o
+ connect \dest3_o$187 \fus_dest3_o$228
connect \xer_so_ok \fus_xer_so_ok
- connect \xer_so_ok$166 \fus_xer_so_ok$204
- connect \xer_so \fus_xer_so
- connect \xer_so$167 \fus_xer_so$205
+ connect \xer_so_ok$188 \fus_xer_so_ok$229
+ connect \xer_so_ok$189 \fus_xer_so_ok$230
+ connect \dest5_o$190 \fus_dest5_o$231
+ connect \dest4_o$191 \fus_dest4_o$232
+ connect \dest4_o$192 \fus_dest4_o$233
connect \fast1_ok \fus_fast1_ok
- connect \wr__rel$168 \wr__rel$96
- connect \wr__go$169 \wr__go$97
- connect \fast1_ok$170 \fus_fast1_ok$206
- connect \fast1_ok$171 \fus_fast1_ok$207
- connect \fast1 \fus_fast1
- connect \fast1$172 \fus_fast1$208
- connect \fast1$173 \fus_fast1$209
+ connect \wr__rel$193 \wr__rel$124
+ connect \wr__go$194 \wr__go$125
+ connect \fast1_ok$195 \fus_fast1_ok$234
+ connect \fast1_ok$196 \fus_fast1_ok$235
+ connect \dest1_o$197 \dest1_o$126
+ connect \dest2_o$198 \fus_dest2_o$236
+ connect \dest3_o$199 \fus_dest3_o$237
connect \fast2_ok \fus_fast2_ok
- connect \fast2_ok$174 \fus_fast2_ok$210
- connect \fast2 \fus_fast2
- connect \fast2$175 \fus_fast2$211
+ connect \fast2_ok$200 \fus_fast2_ok$238
+ connect \dest2_o$201 \fus_dest2_o$239
+ connect \dest3_o$202 \fus_dest3_o$240
connect \nia_ok \fus_nia_ok
- connect \nia_ok$176 \fus_nia_ok$212
- connect \nia \fus_nia
- connect \nia$177 \fus_nia$213
+ connect \nia_ok$203 \fus_nia_ok$241
+ connect \dest3_o$204 \fus_dest3_o$242
+ connect \dest4_o$205 \fus_dest4_o$243
connect \msr_ok \fus_msr_ok
- connect \msr \fus_msr
+ connect \dest5_o$206 \fus_dest5_o$244
connect \spr1_ok \fus_spr1_ok
- connect \spr1 \fus_spr1
+ connect \dest2_o$207 \fus_dest2_o$245
connect \go_die_i \go_die_i
connect \shadown_i \shadown_i
- connect \dest1_o \dest1_o
- connect \go_die_i$178 \go_die_i$102
- connect \shadown_i$179 \shadown_i$103
- connect \dest1_o$180 \dest1_o$104
- connect \go_die_i$181 \go_die_i$105
- connect \shadown_i$182 \shadown_i$106
- connect \dest1_o$183 \dest1_o$107
- connect \go_die_i$184 \go_die_i$108
- connect \shadown_i$185 \shadown_i$109
- connect \dest1_o$186 \dest1_o$110
- connect \go_die_i$187 \go_die_i$111
- connect \shadown_i$188 \shadown_i$112
- connect \dest1_o$189 \dest1_o$113
- connect \go_die_i$190 \go_die_i$114
- connect \shadown_i$191 \shadown_i$115
- connect \dest1_o$192 \dest1_o$116
- connect \go_die_i$193 \go_die_i$117
- connect \shadown_i$194 \shadown_i$118
- connect \dest1_o$195 \dest1_o$119
- connect \go_die_i$196 \go_die_i$120
+ connect \go_die_i$208 \go_die_i$131
+ connect \shadown_i$209 \shadown_i$132
+ connect \go_die_i$210 \go_die_i$133
+ connect \shadown_i$211 \shadown_i$134
+ connect \go_die_i$212 \go_die_i$135
+ connect \shadown_i$213 \shadown_i$136
+ connect \go_die_i$214 \go_die_i$137
+ connect \shadown_i$215 \shadown_i$138
+ connect \go_die_i$216 \go_die_i$139
+ connect \shadown_i$217 \shadown_i$140
+ connect \go_die_i$218 \go_die_i$141
+ connect \shadown_i$219 \shadown_i$142
+ connect \go_die_i$220 \go_die_i$143
+ connect \shadown_i$221 \shadown_i$144
+ connect \go_die_i$222 \go_die_i$145
connect \load_mem_o \load_mem_o
connect \stwd_mem_o \stwd_mem_o
- connect \shadown_i$197 \shadown_i$121
+ connect \shadown_i$223 \shadown_i$146
connect \ldst_port0_is_ld_i \ldst_port0_is_ld_i
connect \ldst_port0_is_st_i \ldst_port0_is_st_i
connect \ldst_port0_data_len \ldst_port0_data_len
connect \ldst_port0_ld_data_o_ok \ldst_port0_ld_data_o_ok
connect \ldst_port0_st_data_i \ldst_port0_st_data_i
connect \ldst_port0_st_data_i_ok \ldst_port0_st_data_i_ok
- connect \ldst_port0_is_ld_i$1 \ldst_port0_is_ld_i$122
+ connect \ldst_port0_is_ld_i$1 \ldst_port0_is_ld_i$147
connect \ldst_port0_busy_o \ldst_port0_busy_o
- connect \ldst_port0_is_st_i$2 \ldst_port0_is_st_i$123
- connect \ldst_port0_data_len$3 \ldst_port0_data_len$124
- connect \ldst_port0_addr_i$4 \ldst_port0_addr_i$125
- connect \ldst_port0_addr_i_ok$5 \ldst_port0_addr_i_ok$126
+ connect \ldst_port0_is_st_i$2 \ldst_port0_is_st_i$148
+ connect \ldst_port0_data_len$3 \ldst_port0_data_len$149
+ connect \ldst_port0_addr_i$4 \ldst_port0_addr_i$150
+ connect \ldst_port0_addr_i_ok$5 \ldst_port0_addr_i_ok$151
connect \x_mask_i \x_mask_i
connect \x_addr_i \x_addr_i
- connect \ldst_port0_addr_ok_o$6 \ldst_port0_addr_ok_o$127
+ connect \ldst_port0_addr_ok_o$6 \ldst_port0_addr_ok_o$152
connect \m_ld_data_o \m_ld_data_o
- connect \ldst_port0_ld_data_o$7 \ldst_port0_ld_data_o$128
- connect \ldst_port0_ld_data_o_ok$8 \ldst_port0_ld_data_o_ok$129
+ connect \ldst_port0_ld_data_o$7 \ldst_port0_ld_data_o$153
+ connect \ldst_port0_ld_data_o_ok$8 \ldst_port0_ld_data_o_ok$154
connect \x_busy_o \x_busy_o
- connect \ldst_port0_st_data_i_ok$9 \ldst_port0_st_data_i_ok$130
- connect \ldst_port0_st_data_i$10 \ldst_port0_st_data_i$131
+ connect \ldst_port0_st_data_i_ok$9 \ldst_port0_st_data_i_ok$155
+ connect \ldst_port0_st_data_i$10 \ldst_port0_st_data_i$156
connect \x_st_data_i \x_st_data_i
- connect \ldst_port0_addr_exc_o$11 \ldst_port0_addr_exc_o$132
+ connect \ldst_port0_addr_exc_o$11 \ldst_port0_addr_exc_o$157
connect \x_ld_i \x_ld_i
connect \x_st_i \x_st_i
connect \m_valid_i \m_valid_i
connect \x_valid_i \x_valid_i
connect \ldst_port0_go_die_i \ldst_port0_go_die_i
- connect \ldst_port0_go_die_i$12 \ldst_port0_go_die_i$133
- connect \ldst_port0_busy_o$13 \ldst_port0_busy_o$134
+ connect \ldst_port0_go_die_i$12 \ldst_port0_go_die_i$158
+ connect \ldst_port0_busy_o$13 \ldst_port0_busy_o$159
connect \dbus__cyc \dbus__cyc
connect \x_stall_i \x_stall_i
connect \dbus__ack \dbus__ack
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 32 \int_wen
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 32 \int_wen$next
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 \int_data_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \int_data_i$next
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 32 \int_wen$214
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 32 \int_wen$214$next
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \int_data_i$215
+ wire width 32 \int_wen$246
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \int_data_i$215$next
+ wire width 64 \int_data_i$247
cell \int \int
connect \rst \rst
connect \clk \clk
connect \src3__data_o \int_src3__data_o
connect \wen \int_wen
connect \data_i \int_data_i
- connect \wen$1 \int_wen$214
- connect \data_i$2 \int_data_i$215
+ connect \wen$1 \int_wen$246
+ connect \data_i$2 \int_data_i$247
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 8 \cr_full_rd__ren
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 8 \cr_full_wr__wen
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 8 \cr_full_wr__wen$next
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 32 \cr_full_wr__data_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 32 \cr_full_wr__data_i$next
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 8 \cr_wen
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 8 \cr_wen$next
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 4 \cr_data_i
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 4 \cr_data_i$next
cell \cr \cr
connect \rst \rst
connect \clk \clk
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 3 \xer_wen
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 3 \xer_wen$next
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 2 \xer_data_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 2 \xer_data_i$next
+ wire width 3 \xer_wen$248
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 3 \xer_wen$216
+ wire width 2 \xer_data_i$249
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 3 \xer_wen$216$next
+ wire width 3 \xer_wen$250
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 2 \xer_data_i$217
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 2 \xer_data_i$217$next
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 3 \xer_wen$218
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 3 \xer_wen$218$next
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 2 \xer_data_i$219
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 2 \xer_data_i$219$next
+ wire width 2 \xer_data_i$251
cell \xer \xer
connect \rst \rst
connect \clk \clk
connect \src3__data_o \xer_src3__data_o
connect \wen \xer_wen
connect \data_i \xer_data_i
- connect \wen$1 \xer_wen$216
- connect \data_i$2 \xer_data_i$217
- connect \wen$3 \xer_wen$218
- connect \data_i$4 \xer_data_i$219
+ connect \wen$1 \xer_wen$248
+ connect \data_i$2 \xer_data_i$249
+ connect \wen$3 \xer_wen$250
+ connect \data_i$4 \xer_data_i$251
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 8 \fast_src3__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \fast_src3__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 8 \fast_src4__ren
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \fast_src4__data_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 8 \fast_src1__ren
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 \fast_src1__data_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 8 \fast_wen
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 8 \fast_wen$next
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 \fast_data_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \fast_data_i$next
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 8 \fast_wen$220
+ wire width 8 \fast_wen$252
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 8 \fast_wen$220$next
+ wire width 64 \fast_data_i$253
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \fast_data_i$221
+ wire width 64 \fast_data_i$254
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \fast_data_i$221$next
+ wire width 8 \fast_wen$255
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \fast_data_i$222
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \fast_data_i$222$next
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 8 \fast_wen$223
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 8 \fast_wen$223$next
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \fast_data_i$224
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \fast_data_i$224$next
+ wire width 64 \fast_data_i$256
cell \fast \fast
- connect \d_rd1__ren \d_rd1__ren
- connect \d_rd1__data_o \d_rd1__data_o
+ connect \cia__ren \cia__ren
+ connect \cia__data_o \cia__data_o
+ connect \msr__ren \msr__ren
+ connect \msr__data_o \msr__data_o
connect \fast_nia_wen \fast_nia_wen
connect \wen \wen
connect \data_i \data_i
connect \rst \rst
connect \clk \clk
- connect \src3__ren \fast_src3__ren
- connect \src3__data_o \fast_src3__data_o
- connect \src4__ren \fast_src4__ren
- connect \src4__data_o \fast_src4__data_o
connect \src1__ren \fast_src1__ren
connect \src1__data_o \fast_src1__data_o
connect \src2__ren \fast_src2__ren
connect \src2__data_o \fast_src2__data_o
connect \wen$1 \fast_wen
connect \data_i$2 \fast_data_i
- connect \wen$3 \fast_wen$220
- connect \data_i$4 \fast_data_i$221
- connect \data_i$5 \fast_data_i$222
- connect \wen$6 \fast_wen$223
- connect \data_i$7 \fast_data_i$224
+ connect \wen$3 \fast_wen$252
+ connect \data_i$4 \fast_data_i$253
+ connect \data_i$5 \fast_data_i$254
+ connect \wen$6 \fast_wen$255
+ connect \data_i$7 \fast_data_i$256
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \spr_src__ren
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 1 \spr_dest__wen
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 1 \spr_dest__wen$next
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 \spr_dest__data_i
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \spr_dest__data_i$next
cell \spr \spr
connect \rst \rst
connect \clk \clk
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
wire width 1 \rdpick_INT_ra_en_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
- wire width 7 \rdpick_INT_ra_i
+ wire width 8 \rdpick_INT_ra_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
- wire width 7 \rdpick_INT_ra_o
+ wire width 8 \rdpick_INT_ra_o
cell \rdpick_INT_ra \rdpick_INT_ra
connect \en_o \rdpick_INT_ra_en_o
connect \i \rdpick_INT_ra_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
wire width 1 \rdpick_INT_rb_en_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
- wire width 6 \rdpick_INT_rb_i
+ wire width 7 \rdpick_INT_rb_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
- wire width 6 \rdpick_INT_rb_o
+ wire width 7 \rdpick_INT_rb_o
cell \rdpick_INT_rb \rdpick_INT_rb
connect \en_o \rdpick_INT_rb_en_o
connect \i \rdpick_INT_rb_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
wire width 1 \rdpick_XER_xer_so_en_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
- wire width 2 \rdpick_XER_xer_so_i
+ wire width 3 \rdpick_XER_xer_so_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
- wire width 2 \rdpick_XER_xer_so_o
+ wire width 3 \rdpick_XER_xer_so_o
cell \rdpick_XER_xer_so \rdpick_XER_xer_so
connect \en_o \rdpick_XER_xer_so_en_o
connect \i \rdpick_XER_xer_so_i
connect \o \rdpick_FAST_fast2_o
end
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
- wire width 1 \rdpick_FAST_cia_en_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
- wire width 2 \rdpick_FAST_cia_i
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
- wire width 2 \rdpick_FAST_cia_o
- cell \rdpick_FAST_cia \rdpick_FAST_cia
- connect \en_o \rdpick_FAST_cia_en_o
- connect \i \rdpick_FAST_cia_i
- connect \o \rdpick_FAST_cia_o
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
- wire width 1 \rdpick_FAST_msr_en_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
- wire width 1 \rdpick_FAST_msr_i
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
- wire width 1 \rdpick_FAST_msr_o
- cell \rdpick_FAST_msr \rdpick_FAST_msr
- connect \en_o \rdpick_FAST_msr_en_o
- connect \i \rdpick_FAST_msr_i
- connect \o \rdpick_FAST_msr_o
- end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
wire width 1 \rdpick_SPR_spr1_en_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
wire width 1 \rdpick_SPR_spr1_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
wire width 1 \wrpick_INT_o_en_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
- wire width 7 \wrpick_INT_o_i
+ wire width 8 \wrpick_INT_o_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
- wire width 7 \wrpick_INT_o_o
+ wire width 8 \wrpick_INT_o_o
cell \wrpick_INT_o \wrpick_INT_o
connect \en_o \wrpick_INT_o_en_o
connect \i \wrpick_INT_o_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
wire width 1 \wrpick_CR_cr_a_en_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
- wire width 4 \wrpick_CR_cr_a_i
+ wire width 5 \wrpick_CR_cr_a_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
- wire width 4 \wrpick_CR_cr_a_o
+ wire width 5 \wrpick_CR_cr_a_o
cell \wrpick_CR_cr_a \wrpick_CR_cr_a
connect \en_o \wrpick_CR_cr_a_en_o
connect \i \wrpick_CR_cr_a_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
wire width 1 \wrpick_XER_xer_ov_en_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
- wire width 2 \wrpick_XER_xer_ov_i
+ wire width 3 \wrpick_XER_xer_ov_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
- wire width 2 \wrpick_XER_xer_ov_o
+ wire width 3 \wrpick_XER_xer_ov_o
cell \wrpick_XER_xer_ov \wrpick_XER_xer_ov
connect \en_o \wrpick_XER_xer_ov_en_o
connect \i \wrpick_XER_xer_ov_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
wire width 1 \wrpick_XER_xer_so_en_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
- wire width 2 \wrpick_XER_xer_so_i
+ wire width 3 \wrpick_XER_xer_so_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
- wire width 2 \wrpick_XER_xer_so_o
+ wire width 3 \wrpick_XER_xer_so_o
cell \wrpick_XER_xer_so \wrpick_XER_xer_so
connect \en_o \wrpick_XER_xer_so_en_o
connect \i \wrpick_XER_xer_so_i
connect \i \wrpick_FAST_fast1_i
connect \o \wrpick_FAST_fast1_o
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
- wire width 1 \wrpick_FAST_fast2_en_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
- wire width 2 \wrpick_FAST_fast2_i
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
- wire width 2 \wrpick_FAST_fast2_o
- cell \wrpick_FAST_fast2 \wrpick_FAST_fast2
- connect \en_o \wrpick_FAST_fast2_en_o
- connect \i \wrpick_FAST_fast2_i
- connect \o \wrpick_FAST_fast2_o
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
+ wire width 1 \wrpick_FAST_fast2_en_o
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
+ wire width 2 \wrpick_FAST_fast2_i
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
+ wire width 2 \wrpick_FAST_fast2_o
+ cell \wrpick_FAST_fast2 \wrpick_FAST_fast2
+ connect \en_o \wrpick_FAST_fast2_en_o
+ connect \i \wrpick_FAST_fast2_i
+ connect \o \wrpick_FAST_fast2_o
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
+ wire width 1 \wrpick_FAST_nia_en_o
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
+ wire width 2 \wrpick_FAST_nia_i
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
+ wire width 2 \wrpick_FAST_nia_o
+ cell \wrpick_FAST_nia \wrpick_FAST_nia
+ connect \en_o \wrpick_FAST_nia_en_o
+ connect \i \wrpick_FAST_nia_i
+ connect \o \wrpick_FAST_nia_o
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
+ wire width 1 \wrpick_FAST_msr_en_o
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
+ wire width 1 \wrpick_FAST_msr_i
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
+ wire width 1 \wrpick_FAST_msr_o
+ cell \wrpick_FAST_msr \wrpick_FAST_msr
+ connect \en_o \wrpick_FAST_msr_en_o
+ connect \i \wrpick_FAST_msr_i
+ connect \o \wrpick_FAST_msr_o
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
+ wire width 1 \wrpick_SPR_spr1_en_o
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
+ wire width 1 \wrpick_SPR_spr1_i
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
+ wire width 1 \wrpick_SPR_spr1_o
+ cell \wrpick_SPR_spr1 \wrpick_SPR_spr1
+ connect \en_o \wrpick_SPR_spr1_en_o
+ connect \i \wrpick_SPR_spr1_i
+ connect \o \wrpick_SPR_spr1_o
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:101"
+ wire width 1 \core_stopped
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:101"
+ wire width 1 \core_stopped$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:139"
+ wire width 1 \can_run
+ process $group_0
+ assign \core_stopped$next \core_stopped
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:104"
+ switch { \core_start_i }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:104"
+ case 1'1
+ assign \core_stopped$next 1'0
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:106"
+ switch { \core_stop_i }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:106"
+ case 1'1
+ assign \core_stopped$next 1'1
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ switch { \can_run }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+ switch \insn_type
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+ attribute \nmigen.decoding "OP_ATTN/5"
+ case 7'0000101
+ assign \core_stopped$next 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \nmigen.decoding "OP_NOP/1"
+ case 7'0000001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+ attribute \nmigen.decoding ""
+ case
+ end
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+ switch \rst
+ case 1'1
+ assign \core_stopped$next 1'1
+ end
+ sync init
+ update \core_stopped 1'1
+ sync posedge \clk
+ update \core_stopped \core_stopped$next
+ end
+ process $group_1
+ assign \core_terminated_o 1'0
+ assign \core_terminated_o \core_stopped
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:140"
+ wire width 1 $257
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:140"
+ cell $not $258
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \core_stopped
+ connect \Y $257
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:140"
+ wire width 1 $259
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:140"
+ cell $and $260
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \valid
+ connect \B $257
+ connect \Y $259
+ end
+ process $group_2
+ assign \can_run 1'0
+ assign \can_run $259
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147"
+ wire width 1 \en_alu0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+ wire width 1 $261
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+ wire width 11 $262
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+ cell $and $263
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 11
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 2
+ parameter \Y_WIDTH 11
+ connect \A \fn_unit
+ connect \B 2'10
+ connect \Y $262
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+ cell $reduce_bool $264
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 11
+ parameter \Y_WIDTH 1
+ connect \A $262
+ connect \Y $261
+ end
+ process $group_3
+ assign \en_alu0 1'0
+ assign \en_alu0 $261
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:134"
+ wire width 9 \fu_enable
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147"
+ wire width 1 \en_cr0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147"
+ wire width 1 \en_branch0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147"
+ wire width 1 \en_trap0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147"
+ wire width 1 \en_logical0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147"
+ wire width 1 \en_spr0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147"
+ wire width 1 \en_mul0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147"
+ wire width 1 \en_shiftrot0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:147"
+ wire width 1 \en_ldst0
+ process $group_4
+ assign \fu_enable 9'000000000
+ assign \fu_enable [0] \en_alu0
+ assign \fu_enable [1] \en_cr0
+ assign \fu_enable [2] \en_branch0
+ assign \fu_enable [3] \en_trap0
+ assign \fu_enable [4] \en_logical0
+ assign \fu_enable [5] \en_spr0
+ assign \fu_enable [6] \en_mul0
+ assign \fu_enable [7] \en_shiftrot0
+ assign \fu_enable [8] \en_ldst0
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+ wire width 1 $265
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+ wire width 11 $266
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+ cell $and $267
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 11
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 7
+ parameter \Y_WIDTH 11
+ connect \A \fn_unit
+ connect \B 7'1000000
+ connect \Y $266
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+ cell $reduce_bool $268
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 11
+ parameter \Y_WIDTH 1
+ connect \A $266
+ connect \Y $265
+ end
+ process $group_5
+ assign \en_cr0 1'0
+ assign \en_cr0 $265
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+ wire width 1 $269
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+ wire width 11 $270
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+ cell $and $271
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 11
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 6
+ parameter \Y_WIDTH 11
+ connect \A \fn_unit
+ connect \B 6'100000
+ connect \Y $270
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+ cell $reduce_bool $272
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 11
+ parameter \Y_WIDTH 1
+ connect \A $270
+ connect \Y $269
+ end
+ process $group_6
+ assign \en_branch0 1'0
+ assign \en_branch0 $269
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+ wire width 1 $273
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+ wire width 11 $274
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+ cell $and $275
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 11
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 8
+ parameter \Y_WIDTH 11
+ connect \A \fn_unit
+ connect \B 8'10000000
+ connect \Y $274
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+ cell $reduce_bool $276
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 11
+ parameter \Y_WIDTH 1
+ connect \A $274
+ connect \Y $273
+ end
+ process $group_7
+ assign \en_trap0 1'0
+ assign \en_trap0 $273
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+ wire width 1 $277
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+ wire width 11 $278
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+ cell $and $279
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 11
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 5
+ parameter \Y_WIDTH 11
+ connect \A \fn_unit
+ connect \B 5'10000
+ connect \Y $278
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+ cell $reduce_bool $280
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 11
+ parameter \Y_WIDTH 1
+ connect \A $278
+ connect \Y $277
+ end
+ process $group_8
+ assign \en_logical0 1'0
+ assign \en_logical0 $277
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+ wire width 1 $281
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+ wire width 11 $282
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+ cell $and $283
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 11
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 11
+ parameter \Y_WIDTH 11
+ connect \A \fn_unit
+ connect \B 11'10000000000
+ connect \Y $282
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+ cell $reduce_bool $284
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 11
+ parameter \Y_WIDTH 1
+ connect \A $282
+ connect \Y $281
+ end
+ process $group_9
+ assign \en_spr0 1'0
+ assign \en_spr0 $281
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+ wire width 1 $285
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+ wire width 11 $286
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+ cell $and $287
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 11
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 9
+ parameter \Y_WIDTH 11
+ connect \A \fn_unit
+ connect \B 9'100000000
+ connect \Y $286
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
- wire width 1 \wrpick_FAST_nia_en_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
- wire width 2 \wrpick_FAST_nia_i
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
- wire width 2 \wrpick_FAST_nia_o
- cell \wrpick_FAST_nia \wrpick_FAST_nia
- connect \en_o \wrpick_FAST_nia_en_o
- connect \i \wrpick_FAST_nia_i
- connect \o \wrpick_FAST_nia_o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+ cell $reduce_bool $288
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 11
+ parameter \Y_WIDTH 1
+ connect \A $286
+ connect \Y $285
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
- wire width 1 \wrpick_FAST_msr_en_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
- wire width 1 \wrpick_FAST_msr_i
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
- wire width 1 \wrpick_FAST_msr_o
- cell \wrpick_FAST_msr \wrpick_FAST_msr
- connect \en_o \wrpick_FAST_msr_en_o
- connect \i \wrpick_FAST_msr_i
- connect \o \wrpick_FAST_msr_o
+ process $group_10
+ assign \en_mul0 1'0
+ assign \en_mul0 $285
+ sync init
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
- wire width 1 \wrpick_SPR_spr1_en_o
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
- wire width 1 \wrpick_SPR_spr1_i
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
- wire width 1 \wrpick_SPR_spr1_o
- cell \wrpick_SPR_spr1 \wrpick_SPR_spr1
- connect \en_o \wrpick_SPR_spr1_en_o
- connect \i \wrpick_SPR_spr1_i
- connect \o \wrpick_SPR_spr1_o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+ wire width 1 $289
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+ wire width 11 $290
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+ cell $and $291
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 11
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 4
+ parameter \Y_WIDTH 11
+ connect \A \fn_unit
+ connect \B 4'1000
+ connect \Y $290
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:111"
- wire width 1 \en_alu0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:112"
- wire width 1 $225
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:112"
- wire width 11 $226
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:112"
- cell $and $227
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+ cell $reduce_bool $292
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 11
+ parameter \Y_WIDTH 1
+ connect \A $290
+ connect \Y $289
+ end
+ process $group_11
+ assign \en_shiftrot0 1'0
+ assign \en_shiftrot0 $289
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+ wire width 1 $293
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+ wire width 11 $294
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+ cell $and $295
parameter \A_SIGNED 0
parameter \A_WIDTH 11
parameter \B_SIGNED 0
- parameter \B_WIDTH 2
+ parameter \B_WIDTH 3
parameter \Y_WIDTH 11
connect \A \fn_unit
- connect \B 2'10
- connect \Y $226
+ connect \B 3'100
+ connect \Y $294
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:112"
- cell $reduce_bool $228
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+ cell $reduce_bool $296
parameter \A_SIGNED 0
parameter \A_WIDTH 11
parameter \Y_WIDTH 1
- connect \A $226
- connect \Y $225
+ connect \A $294
+ connect \Y $293
+ end
+ process $group_12
+ assign \en_ldst0 1'0
+ assign \en_ldst0 $293
+ sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:112"
- wire width 1 $229
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:112"
- cell $and $230
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:152"
+ wire width 2 \counter
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:152"
+ wire width 2 \counter$next
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
+ wire width 1 $297
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
+ cell $ne $298
parameter \A_SIGNED 0
- parameter \A_WIDTH 1
+ parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \valid
- connect \B $225
- connect \Y $229
+ connect \A \counter
+ connect \B 1'0
+ connect \Y $297
end
- process $group_0
- assign \en_alu0 1'0
- assign \en_alu0 $229
- sync init
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+ wire width 3 $299
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+ wire width 3 $300
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+ cell $sub $301
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 2
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 3
+ connect \A \counter
+ connect \B 1'1
+ connect \Y $300
end
- process $group_1
- assign \oper_i__insn_type 7'0000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- switch { \en_alu0 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
+ connect $299 $300
+ process $group_13
+ assign \counter$next \counter
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
+ switch { $297 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
+ case 1'1
+ assign \counter$next $299 [1:0]
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ switch { \can_run }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+ switch \insn_type
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+ attribute \nmigen.decoding "OP_ATTN/5"
+ case 7'0000101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \nmigen.decoding "OP_NOP/1"
+ case 7'0000001
+ assign \counter$next 2'10
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+ attribute \nmigen.decoding ""
+ case
+ end
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+ switch \rst
case 1'1
- assign \oper_i__insn_type \insn_type
+ assign \counter$next 2'00
end
sync init
+ update \counter 2'00
+ sync posedge \clk
+ update \counter \counter$next
end
- process $group_2
- assign \fus_oper_i__fn_unit 11'00000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- switch { \en_alu0 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- case 1'1
- assign \fus_oper_i__fn_unit \fn_unit
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
+ wire width 1 $302
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
+ cell $ne $303
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 2
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \counter
+ connect \B 1'0
+ connect \Y $302
+ end
+ process $group_14
+ assign \corebusy_o 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
+ switch { $302 }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
+ case 1'1
+ assign \corebusy_o 1'1
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ switch { \can_run }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+ switch \insn_type
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+ attribute \nmigen.decoding "OP_ATTN/5"
+ case 7'0000101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \nmigen.decoding "OP_NOP/1"
+ case 7'0000001
+ assign \corebusy_o 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+ attribute \nmigen.decoding ""
+ case
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ switch { \fu_enable [0] }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ case 1'1
+ assign \corebusy_o \busy_o
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ switch { \fu_enable [1] }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ case 1'1
+ assign \corebusy_o \busy_o$6
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ switch { \fu_enable [2] }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ case 1'1
+ assign \corebusy_o \busy_o$14
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ switch { \fu_enable [3] }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ case 1'1
+ assign \corebusy_o \busy_o$22
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ switch { \fu_enable [4] }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ case 1'1
+ assign \corebusy_o \busy_o$36
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ switch { \fu_enable [5] }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ case 1'1
+ assign \corebusy_o \busy_o$42
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ switch { \fu_enable [6] }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ case 1'1
+ assign \corebusy_o \busy_o$53
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ switch { \fu_enable [7] }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ case 1'1
+ assign \corebusy_o \busy_o$62
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ switch { \fu_enable [8] }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ case 1'1
+ assign \corebusy_o \busy_o$69
+ end
+ end
end
sync init
end
- process $group_3
- assign \fus_oper_i__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \fus_oper_i__imm_data__imm_ok 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- switch { \en_alu0 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- case 1'1
- assign { \fus_oper_i__imm_data__imm_ok \fus_oper_i__imm_data__imm } { \imm_ok \imm }
+ process $group_15
+ assign \oper_i__insn_type 7'0000000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ switch { \can_run }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+ switch \insn_type
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+ attribute \nmigen.decoding "OP_ATTN/5"
+ case 7'0000101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \nmigen.decoding "OP_NOP/1"
+ case 7'0000001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+ attribute \nmigen.decoding ""
+ case
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ switch { \fu_enable [0] }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ case 1'1
+ assign \oper_i__insn_type \insn_type
+ end
+ end
end
sync init
end
- process $group_5
- assign \oper_i__lk 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- switch { \en_alu0 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- case 1'1
- assign \oper_i__lk \lk
+ process $group_16
+ assign \oper_i__fn_unit 11'00000000000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ switch { \can_run }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+ switch \insn_type
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+ attribute \nmigen.decoding "OP_ATTN/5"
+ case 7'0000101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \nmigen.decoding "OP_NOP/1"
+ case 7'0000001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+ attribute \nmigen.decoding ""
+ case
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ switch { \fu_enable [0] }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ case 1'1
+ assign \oper_i__fn_unit \fn_unit
+ end
+ end
end
sync init
end
- process $group_6
+ process $group_17
+ assign \fus_oper_i__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \fus_oper_i__imm_data__imm_ok 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ switch { \can_run }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+ switch \insn_type
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+ attribute \nmigen.decoding "OP_ATTN/5"
+ case 7'0000101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \nmigen.decoding "OP_NOP/1"
+ case 7'0000001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+ attribute \nmigen.decoding ""
+ case
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ switch { \fu_enable [0] }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ case 1'1
+ assign { \fus_oper_i__imm_data__imm_ok \fus_oper_i__imm_data__imm } { \imm_ok \imm }
+ end
+ end
+ end
+ sync init
+ end
+ process $group_19
assign \fus_oper_i__rc__rc 1'0
assign \fus_oper_i__rc__rc_ok 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- switch { \en_alu0 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- case 1'1
- assign { \fus_oper_i__rc__rc_ok \fus_oper_i__rc__rc } { \rc_ok \rc }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ switch { \can_run }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+ switch \insn_type
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+ attribute \nmigen.decoding "OP_ATTN/5"
+ case 7'0000101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \nmigen.decoding "OP_NOP/1"
+ case 7'0000001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+ attribute \nmigen.decoding ""
+ case
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ switch { \fu_enable [0] }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ case 1'1
+ assign { \fus_oper_i__rc__rc_ok \fus_oper_i__rc__rc } { \rc_ok \rc }
+ end
+ end
end
sync init
end
- process $group_8
+ process $group_21
assign \fus_oper_i__oe__oe 1'0
assign \fus_oper_i__oe__oe_ok 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- switch { \en_alu0 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- case 1'1
- assign { \fus_oper_i__oe__oe_ok \fus_oper_i__oe__oe } { \oe_ok \oe }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ switch { \can_run }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+ switch \insn_type
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+ attribute \nmigen.decoding "OP_ATTN/5"
+ case 7'0000101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \nmigen.decoding "OP_NOP/1"
+ case 7'0000001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+ attribute \nmigen.decoding ""
+ case
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ switch { \fu_enable [0] }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ case 1'1
+ assign { \fus_oper_i__oe__oe_ok \fus_oper_i__oe__oe } { \oe_ok \oe }
+ end
+ end
end
sync init
end
- process $group_10
+ process $group_23
assign \oper_i__invert_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- switch { \en_alu0 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- case 1'1
- assign \oper_i__invert_a \invert_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ switch { \can_run }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+ switch \insn_type
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+ attribute \nmigen.decoding "OP_ATTN/5"
+ case 7'0000101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \nmigen.decoding "OP_NOP/1"
+ case 7'0000001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+ attribute \nmigen.decoding ""
+ case
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ switch { \fu_enable [0] }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ case 1'1
+ assign \oper_i__invert_a \invert_a
+ end
+ end
end
sync init
end
- process $group_11
- assign \fus_oper_i__zero_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- switch { \en_alu0 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- case 1'1
- assign \fus_oper_i__zero_a \zero_a
+ process $group_24
+ assign \oper_i__zero_a 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ switch { \can_run }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+ switch \insn_type
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+ attribute \nmigen.decoding "OP_ATTN/5"
+ case 7'0000101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \nmigen.decoding "OP_NOP/1"
+ case 7'0000001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+ attribute \nmigen.decoding ""
+ case
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ switch { \fu_enable [0] }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ case 1'1
+ assign \oper_i__zero_a \zero_a
+ end
+ end
end
sync init
end
- process $group_12
+ process $group_25
assign \oper_i__invert_out 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- switch { \en_alu0 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- case 1'1
- assign \oper_i__invert_out \invert_out
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ switch { \can_run }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+ switch \insn_type
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+ attribute \nmigen.decoding "OP_ATTN/5"
+ case 7'0000101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \nmigen.decoding "OP_NOP/1"
+ case 7'0000001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+ attribute \nmigen.decoding ""
+ case
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ switch { \fu_enable [0] }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ case 1'1
+ assign \oper_i__invert_out \invert_out
+ end
+ end
end
sync init
end
- process $group_13
- assign \fus_oper_i__write_cr__data 3'000
- assign \fus_oper_i__write_cr__ok 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- switch { \en_alu0 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- case 1'1
- assign { \fus_oper_i__write_cr__ok \fus_oper_i__write_cr__data } { \cr_out_ok \cr_out }
+ process $group_26
+ assign \oper_i__write_cr0 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ switch { \can_run }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+ switch \insn_type
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+ attribute \nmigen.decoding "OP_ATTN/5"
+ case 7'0000101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \nmigen.decoding "OP_NOP/1"
+ case 7'0000001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+ attribute \nmigen.decoding ""
+ case
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ switch { \fu_enable [0] }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ case 1'1
+ assign \oper_i__write_cr0 \write_cr0
+ end
+ end
end
sync init
end
- process $group_15
+ process $group_27
assign \oper_i__input_carry 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- switch { \en_alu0 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- case 1'1
- assign \oper_i__input_carry \input_carry
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ switch { \can_run }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+ switch \insn_type
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+ attribute \nmigen.decoding "OP_ATTN/5"
+ case 7'0000101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \nmigen.decoding "OP_NOP/1"
+ case 7'0000001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+ attribute \nmigen.decoding ""
+ case
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ switch { \fu_enable [0] }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ case 1'1
+ assign \oper_i__input_carry \input_carry
+ end
+ end
end
sync init
end
- process $group_16
+ process $group_28
assign \oper_i__output_carry 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- switch { \en_alu0 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- case 1'1
- assign \oper_i__output_carry \output_carry
- end
- sync init
- end
- process $group_17
- assign \oper_i__input_cr 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- switch { \en_alu0 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- case 1'1
- assign \oper_i__input_cr \input_cr
- end
- sync init
- end
- process $group_18
- assign \oper_i__output_cr 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- switch { \en_alu0 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- case 1'1
- assign \oper_i__output_cr \output_cr
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ switch { \can_run }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+ switch \insn_type
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+ attribute \nmigen.decoding "OP_ATTN/5"
+ case 7'0000101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \nmigen.decoding "OP_NOP/1"
+ case 7'0000001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+ attribute \nmigen.decoding ""
+ case
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ switch { \fu_enable [0] }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ case 1'1
+ assign \oper_i__output_carry \output_carry
+ end
+ end
end
sync init
end
- process $group_19
+ process $group_29
assign \oper_i__is_32bit 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- switch { \en_alu0 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- case 1'1
- assign \oper_i__is_32bit \is_32bit
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ switch { \can_run }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+ switch \insn_type
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+ attribute \nmigen.decoding "OP_ATTN/5"
+ case 7'0000101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \nmigen.decoding "OP_NOP/1"
+ case 7'0000001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+ attribute \nmigen.decoding ""
+ case
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ switch { \fu_enable [0] }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ case 1'1
+ assign \oper_i__is_32bit \is_32bit
+ end
+ end
end
sync init
end
- process $group_20
+ process $group_30
assign \oper_i__is_signed 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- switch { \en_alu0 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- case 1'1
- assign \oper_i__is_signed \is_signed
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ switch { \can_run }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+ switch \insn_type
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+ attribute \nmigen.decoding "OP_ATTN/5"
+ case 7'0000101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \nmigen.decoding "OP_NOP/1"
+ case 7'0000001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+ attribute \nmigen.decoding ""
+ case
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ switch { \fu_enable [0] }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ case 1'1
+ assign \oper_i__is_signed \is_signed
+ end
+ end
end
sync init
end
- process $group_21
+ process $group_31
assign \oper_i__data_len 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- switch { \en_alu0 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- case 1'1
- assign \oper_i__data_len \data_len
- end
- sync init
- end
- process $group_22
- assign \fus_oper_i__insn 32'00000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- switch { \en_alu0 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- case 1'1
- assign \fus_oper_i__insn \insn
- end
- sync init
- end
- process $group_23
- assign \oper_i__byte_reverse 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- switch { \en_alu0 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- case 1'1
- assign \oper_i__byte_reverse \byte_reverse
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ switch { \can_run }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+ switch \insn_type
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+ attribute \nmigen.decoding "OP_ATTN/5"
+ case 7'0000101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \nmigen.decoding "OP_NOP/1"
+ case 7'0000001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+ attribute \nmigen.decoding ""
+ case
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ switch { \fu_enable [0] }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ case 1'1
+ assign \oper_i__data_len \data_len
+ end
+ end
end
sync init
end
- process $group_24
- assign \oper_i__sign_extend 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- switch { \en_alu0 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- case 1'1
- assign \oper_i__sign_extend \sign_extend
+ process $group_32
+ assign \oper_i__insn 32'00000000000000000000000000000000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ switch { \can_run }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+ switch \insn_type
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+ attribute \nmigen.decoding "OP_ATTN/5"
+ case 7'0000101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \nmigen.decoding "OP_NOP/1"
+ case 7'0000001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+ attribute \nmigen.decoding ""
+ case
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ switch { \fu_enable [0] }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ case 1'1
+ assign \oper_i__insn \insn
+ end
+ end
end
sync init
end
- process $group_25
+ process $group_33
assign \issue_i$1 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- switch { \en_alu0 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- case 1'1
- assign \issue_i$1 \issue_i
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:111"
- wire width 1 \en_cr0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:111"
- wire width 1 \en_branch0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:111"
- wire width 1 \en_trap0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:111"
- wire width 1 \en_logical0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:111"
- wire width 1 \en_spr0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:111"
- wire width 1 \en_shiftrot0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:111"
- wire width 1 \en_ldst0
- process $group_26
- assign \corebusy_o 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- switch { \en_alu0 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- case 1'1
- assign \corebusy_o \busy_o
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- switch { \en_cr0 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- case 1'1
- assign \corebusy_o \busy_o$4
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- switch { \en_branch0 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- case 1'1
- assign \corebusy_o \busy_o$12
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- switch { \en_trap0 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- case 1'1
- assign \corebusy_o \busy_o$18
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- switch { \en_logical0 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- case 1'1
- assign \corebusy_o \busy_o$30
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- switch { \en_spr0 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- case 1'1
- assign \corebusy_o \busy_o$36
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- switch { \en_shiftrot0 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- case 1'1
- assign \corebusy_o \busy_o$45
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- switch { \en_ldst0 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- case 1'1
- assign \corebusy_o \busy_o$53
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ switch { \can_run }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+ switch \insn_type
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+ attribute \nmigen.decoding "OP_ATTN/5"
+ case 7'0000101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \nmigen.decoding "OP_NOP/1"
+ case 7'0000001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+ attribute \nmigen.decoding ""
+ case
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ switch { \fu_enable [0] }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ case 1'1
+ assign \issue_i$1 \issue_i
+ end
+ end
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:118"
- wire width 4 $231
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:71"
- wire width 1 $232
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:71"
- cell $and $233
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:179"
+ wire width 4 $304
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79"
+ wire width 1 $305
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79"
+ cell $and $306
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \oe
connect \B \oe_ok
- connect \Y $232
+ connect \Y $305
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:75"
- wire width 1 $234
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:75"
- cell $eq $235
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79"
+ wire width 1 $307
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79"
+ cell $or $308
parameter \A_SIGNED 0
- parameter \A_WIDTH 2
+ parameter \A_WIDTH 1
parameter \B_SIGNED 0
- parameter \B_WIDTH 2
+ parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \input_carry
- connect \B 2'10
- connect \Y $234
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:118"
- cell $not $236
- parameter \A_SIGNED 0
- parameter \A_WIDTH 4
- parameter \Y_WIDTH 4
- connect \A { $234 $232 \reg2_ok \reg1_ok }
- connect \Y $231
- end
- process $group_27
- assign \fus_rdmaskn 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- switch { \en_alu0 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- case 1'1
- assign \fus_rdmaskn $231
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:103"
- wire width 8 \fu_enable
- process $group_28
- assign \fu_enable 8'00000000
- assign \fu_enable [0] \en_alu0
- assign \fu_enable [1] \en_cr0
- assign \fu_enable [2] \en_branch0
- assign \fu_enable [3] \en_trap0
- assign \fu_enable [4] \en_logical0
- assign \fu_enable [5] \en_spr0
- assign \fu_enable [6] \en_shiftrot0
- assign \fu_enable [7] \en_ldst0
- sync init
+ connect \A $305
+ connect \B \xer_in
+ connect \Y $307
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:112"
- wire width 1 $237
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:112"
- wire width 11 $238
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:112"
- cell $and $239
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83"
+ wire width 1 $309
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83"
+ cell $eq $310
parameter \A_SIGNED 0
- parameter \A_WIDTH 11
+ parameter \A_WIDTH 2
parameter \B_SIGNED 0
- parameter \B_WIDTH 7
- parameter \Y_WIDTH 11
- connect \A \fn_unit
- connect \B 7'1000000
- connect \Y $238
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:112"
- cell $reduce_bool $240
- parameter \A_SIGNED 0
- parameter \A_WIDTH 11
+ parameter \B_WIDTH 2
parameter \Y_WIDTH 1
- connect \A $238
- connect \Y $237
+ connect \A \input_carry
+ connect \B 2'10
+ connect \Y $309
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:112"
- wire width 1 $241
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:112"
- cell $and $242
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83"
+ wire width 1 $311
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83"
+ cell $or $312
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \valid
- connect \B $237
- connect \Y $241
+ connect \A $309
+ connect \B \xer_in
+ connect \Y $311
end
- process $group_29
- assign \en_cr0 1'0
- assign \en_cr0 $241
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:179"
+ cell $not $313
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 4
+ parameter \Y_WIDTH 4
+ connect \A { $311 $307 \reg2_ok \reg1_ok }
+ connect \Y $304
+ end
+ process $group_34
+ assign \fus_rdmaskn 4'0000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ switch { \can_run }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+ switch \insn_type
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+ attribute \nmigen.decoding "OP_ATTN/5"
+ case 7'0000101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \nmigen.decoding "OP_NOP/1"
+ case 7'0000001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+ attribute \nmigen.decoding ""
+ case
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ switch { \fu_enable [0] }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ case 1'1
+ assign \fus_rdmaskn $304
+ end
+ end
+ end
sync init
end
- process $group_30
+ process $group_35
assign \oper_i__insn_type$2 7'0000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- switch { \en_cr0 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- case 1'1
- assign \oper_i__insn_type$2 \insn_type
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ switch { \can_run }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+ switch \insn_type
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+ attribute \nmigen.decoding "OP_ATTN/5"
+ case 7'0000101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \nmigen.decoding "OP_NOP/1"
+ case 7'0000001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+ attribute \nmigen.decoding ""
+ case
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ switch { \fu_enable [1] }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ case 1'1
+ assign \oper_i__insn_type$2 \insn_type
+ end
+ end
end
sync init
end
- process $group_31
- assign \oper_i__fn_unit 11'00000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- switch { \en_cr0 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- case 1'1
- assign \oper_i__fn_unit \fn_unit
+ process $group_36
+ assign \oper_i__fn_unit$3 11'00000000000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ switch { \can_run }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+ switch \insn_type
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+ attribute \nmigen.decoding "OP_ATTN/5"
+ case 7'0000101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \nmigen.decoding "OP_NOP/1"
+ case 7'0000001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+ attribute \nmigen.decoding ""
+ case
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ switch { \fu_enable [1] }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ case 1'1
+ assign \oper_i__fn_unit$3 \fn_unit
+ end
+ end
end
sync init
end
- process $group_32
- assign \oper_i__insn 32'00000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- switch { \en_cr0 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- case 1'1
- assign \oper_i__insn \insn
+ process $group_37
+ assign \oper_i__insn$4 32'00000000000000000000000000000000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ switch { \can_run }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+ switch \insn_type
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+ attribute \nmigen.decoding "OP_ATTN/5"
+ case 7'0000101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \nmigen.decoding "OP_NOP/1"
+ case 7'0000001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+ attribute \nmigen.decoding ""
+ case
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ switch { \fu_enable [1] }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ case 1'1
+ assign \oper_i__insn$4 \insn
+ end
+ end
end
sync init
end
- process $group_33
+ process $group_38
assign \oper_i__read_cr_whole 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- switch { \en_cr0 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- case 1'1
- assign \oper_i__read_cr_whole \read_cr_whole
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ switch { \can_run }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+ switch \insn_type
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+ attribute \nmigen.decoding "OP_ATTN/5"
+ case 7'0000101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \nmigen.decoding "OP_NOP/1"
+ case 7'0000001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+ attribute \nmigen.decoding ""
+ case
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ switch { \fu_enable [1] }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ case 1'1
+ assign \oper_i__read_cr_whole \read_cr_whole
+ end
+ end
end
sync init
end
- process $group_34
+ process $group_39
assign \oper_i__write_cr_whole 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- switch { \en_cr0 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- case 1'1
- assign \oper_i__write_cr_whole \write_cr_whole
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ switch { \can_run }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+ switch \insn_type
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+ attribute \nmigen.decoding "OP_ATTN/5"
+ case 7'0000101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \nmigen.decoding "OP_NOP/1"
+ case 7'0000001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+ attribute \nmigen.decoding ""
+ case
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ switch { \fu_enable [1] }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ case 1'1
+ assign \oper_i__write_cr_whole \write_cr_whole
+ end
+ end
end
sync init
end
- process $group_35
- assign \issue_i$3 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- switch { \en_cr0 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- case 1'1
- assign \issue_i$3 \issue_i
+ process $group_40
+ assign \issue_i$5 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ switch { \can_run }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+ switch \insn_type
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+ attribute \nmigen.decoding "OP_ATTN/5"
+ case 7'0000101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \nmigen.decoding "OP_NOP/1"
+ case 7'0000001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+ attribute \nmigen.decoding ""
+ case
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ switch { \fu_enable [1] }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ case 1'1
+ assign \issue_i$5 \issue_i
+ end
+ end
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:118"
- wire width 6 $243
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:118"
- cell $not $244
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:179"
+ wire width 6 $314
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:179"
+ cell $not $315
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \Y_WIDTH 6
- connect \A { \cr_in2_ok$5 \cr_in2_ok \cr_in1_ok \read_cr_whole \reg2_ok \reg1_ok }
- connect \Y $243
- end
- process $group_36
- assign \fus_rdmaskn$135 6'000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- switch { \en_cr0 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- case 1'1
- assign \fus_rdmaskn$135 $243
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:112"
- wire width 1 $245
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:112"
- wire width 11 $246
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:112"
- cell $and $247
- parameter \A_SIGNED 0
- parameter \A_WIDTH 11
- parameter \B_SIGNED 0
- parameter \B_WIDTH 6
- parameter \Y_WIDTH 11
- connect \A \fn_unit
- connect \B 6'100000
- connect \Y $246
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:112"
- cell $reduce_bool $248
- parameter \A_SIGNED 0
- parameter \A_WIDTH 11
- parameter \Y_WIDTH 1
- connect \A $246
- connect \Y $245
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:112"
- wire width 1 $249
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:112"
- cell $and $250
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \valid
- connect \B $245
- connect \Y $249
- end
- process $group_37
- assign \en_branch0 1'0
- assign \en_branch0 $249
- sync init
- end
- process $group_38
- assign \oper_i__insn_type$6 7'0000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- switch { \en_branch0 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- case 1'1
- assign \oper_i__insn_type$6 \insn_type
- end
- sync init
- end
- process $group_39
- assign \oper_i__fn_unit$7 11'00000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- switch { \en_branch0 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- case 1'1
- assign \oper_i__fn_unit$7 \fn_unit
- end
- sync init
+ connect \A { \cr_in2_ok$7 \cr_in2_ok \cr_in1_ok \read_cr_whole \reg2_ok \reg1_ok }
+ connect \Y $314
end
- process $group_40
- assign \fus_oper_i__imm_data__imm$136 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \fus_oper_i__imm_data__imm_ok$137 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- switch { \en_branch0 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- case 1'1
- assign { \fus_oper_i__imm_data__imm_ok$137 \fus_oper_i__imm_data__imm$136 } { \imm_ok \imm }
+ process $group_41
+ assign \fus_rdmaskn$160 6'000000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ switch { \can_run }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+ switch \insn_type
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+ attribute \nmigen.decoding "OP_ATTN/5"
+ case 7'0000101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \nmigen.decoding "OP_NOP/1"
+ case 7'0000001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+ attribute \nmigen.decoding ""
+ case
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ switch { \fu_enable [1] }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ case 1'1
+ assign \fus_rdmaskn$160 $314
+ end
+ end
end
sync init
end
process $group_42
- assign \oper_i__lk$8 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- switch { \en_branch0 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- case 1'1
- assign \oper_i__lk$8 \lk
+ assign \oper_i__cia 64'0000000000000000000000000000000000000000000000000000000000000000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ switch { \can_run }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+ switch \insn_type
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+ attribute \nmigen.decoding "OP_ATTN/5"
+ case 7'0000101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \nmigen.decoding "OP_NOP/1"
+ case 7'0000001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+ attribute \nmigen.decoding ""
+ case
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ switch { \fu_enable [2] }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ case 1'1
+ assign \oper_i__cia \cia$8
+ end
+ end
end
sync init
end
process $group_43
- assign \oper_i__is_32bit$9 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- switch { \en_branch0 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- case 1'1
- assign \oper_i__is_32bit$9 \is_32bit
+ assign \oper_i__insn_type$9 7'0000000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ switch { \can_run }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+ switch \insn_type
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+ attribute \nmigen.decoding "OP_ATTN/5"
+ case 7'0000101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \nmigen.decoding "OP_NOP/1"
+ case 7'0000001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+ attribute \nmigen.decoding ""
+ case
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ switch { \fu_enable [2] }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ case 1'1
+ assign \oper_i__insn_type$9 \insn_type
+ end
+ end
end
sync init
end
process $group_44
- assign \oper_i__insn$10 32'00000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- switch { \en_branch0 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- case 1'1
- assign \oper_i__insn$10 \insn
- end
- sync init
- end
- process $group_45
- assign \issue_i$11 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- switch { \en_branch0 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- case 1'1
- assign \issue_i$11 \issue_i
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:118"
- wire width 4 $251
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:118"
- cell $not $252
- parameter \A_SIGNED 0
- parameter \A_WIDTH 4
- parameter \Y_WIDTH 4
- connect \A { 1'1 \cr_in1_ok \fast2_ok \fast1_ok }
- connect \Y $251
- end
- process $group_46
- assign \fus_rdmaskn$138 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- switch { \en_branch0 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- case 1'1
- assign \fus_rdmaskn$138 $251
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:112"
- wire width 1 $253
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:112"
- wire width 11 $254
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:112"
- cell $and $255
- parameter \A_SIGNED 0
- parameter \A_WIDTH 11
- parameter \B_SIGNED 0
- parameter \B_WIDTH 8
- parameter \Y_WIDTH 11
- connect \A \fn_unit
- connect \B 8'10000000
- connect \Y $254
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:112"
- cell $reduce_bool $256
- parameter \A_SIGNED 0
- parameter \A_WIDTH 11
- parameter \Y_WIDTH 1
- connect \A $254
- connect \Y $253
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:112"
- wire width 1 $257
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:112"
- cell $and $258
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \valid
- connect \B $253
- connect \Y $257
+ assign \oper_i__fn_unit$10 11'00000000000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ switch { \can_run }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+ switch \insn_type
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+ attribute \nmigen.decoding "OP_ATTN/5"
+ case 7'0000101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \nmigen.decoding "OP_NOP/1"
+ case 7'0000001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+ attribute \nmigen.decoding ""
+ case
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ switch { \fu_enable [2] }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ case 1'1
+ assign \oper_i__fn_unit$10 \fn_unit
+ end
+ end
+ end
+ sync init
end
- process $group_47
- assign \en_trap0 1'0
- assign \en_trap0 $257
+ process $group_45
+ assign \oper_i__insn$11 32'00000000000000000000000000000000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ switch { \can_run }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+ switch \insn_type
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+ attribute \nmigen.decoding "OP_ATTN/5"
+ case 7'0000101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \nmigen.decoding "OP_NOP/1"
+ case 7'0000001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+ attribute \nmigen.decoding ""
+ case
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ switch { \fu_enable [2] }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ case 1'1
+ assign \oper_i__insn$11 \insn
+ end
+ end
+ end
+ sync init
+ end
+ process $group_46
+ assign \fus_oper_i__imm_data__imm$161 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \fus_oper_i__imm_data__imm_ok$162 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ switch { \can_run }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+ switch \insn_type
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+ attribute \nmigen.decoding "OP_ATTN/5"
+ case 7'0000101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \nmigen.decoding "OP_NOP/1"
+ case 7'0000001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+ attribute \nmigen.decoding ""
+ case
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ switch { \fu_enable [2] }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ case 1'1
+ assign { \fus_oper_i__imm_data__imm_ok$162 \fus_oper_i__imm_data__imm$161 } { \imm_ok \imm }
+ end
+ end
+ end
sync init
end
process $group_48
- assign \oper_i__insn_type$13 7'0000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- switch { \en_trap0 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- case 1'1
- assign \oper_i__insn_type$13 \insn_type
+ assign \oper_i__lk 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ switch { \can_run }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+ switch \insn_type
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+ attribute \nmigen.decoding "OP_ATTN/5"
+ case 7'0000101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \nmigen.decoding "OP_NOP/1"
+ case 7'0000001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+ attribute \nmigen.decoding ""
+ case
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ switch { \fu_enable [2] }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ case 1'1
+ assign \oper_i__lk \lk
+ end
+ end
end
sync init
end
process $group_49
- assign \oper_i__fn_unit$14 11'00000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- switch { \en_trap0 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- case 1'1
- assign \oper_i__fn_unit$14 \fn_unit
+ assign \oper_i__is_32bit$12 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ switch { \can_run }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+ switch \insn_type
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+ attribute \nmigen.decoding "OP_ATTN/5"
+ case 7'0000101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \nmigen.decoding "OP_NOP/1"
+ case 7'0000001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+ attribute \nmigen.decoding ""
+ case
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ switch { \fu_enable [2] }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ case 1'1
+ assign \oper_i__is_32bit$12 \is_32bit
+ end
+ end
end
sync init
end
process $group_50
- assign \oper_i__insn$15 32'00000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- switch { \en_trap0 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- case 1'1
- assign \oper_i__insn$15 \insn
+ assign \issue_i$13 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ switch { \can_run }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+ switch \insn_type
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+ attribute \nmigen.decoding "OP_ATTN/5"
+ case 7'0000101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \nmigen.decoding "OP_NOP/1"
+ case 7'0000001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+ attribute \nmigen.decoding ""
+ case
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ switch { \fu_enable [2] }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ case 1'1
+ assign \issue_i$13 \issue_i
+ end
+ end
end
sync init
end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:179"
+ wire width 3 $316
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:179"
+ cell $not $317
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 3
+ parameter \Y_WIDTH 3
+ connect \A { \cr_in1_ok \fast2_ok \fast1_ok }
+ connect \Y $316
+ end
process $group_51
- assign \oper_i__is_32bit$16 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- switch { \en_trap0 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- case 1'1
- assign \oper_i__is_32bit$16 \is_32bit
+ assign \fus_rdmaskn$163 3'000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ switch { \can_run }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+ switch \insn_type
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+ attribute \nmigen.decoding "OP_ATTN/5"
+ case 7'0000101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \nmigen.decoding "OP_NOP/1"
+ case 7'0000001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+ attribute \nmigen.decoding ""
+ case
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ switch { \fu_enable [2] }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ case 1'1
+ assign \fus_rdmaskn$163 $316
+ end
+ end
end
sync init
end
process $group_52
- assign \oper_i__traptype 5'00000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- switch { \en_trap0 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- case 1'1
- assign \oper_i__traptype \traptype
+ assign \oper_i__insn_type$15 7'0000000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ switch { \can_run }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+ switch \insn_type
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+ attribute \nmigen.decoding "OP_ATTN/5"
+ case 7'0000101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \nmigen.decoding "OP_NOP/1"
+ case 7'0000001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+ attribute \nmigen.decoding ""
+ case
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ switch { \fu_enable [3] }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ case 1'1
+ assign \oper_i__insn_type$15 \insn_type
+ end
+ end
end
sync init
end
process $group_53
- assign \oper_i__trapaddr 13'0000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- switch { \en_trap0 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- case 1'1
- assign \oper_i__trapaddr \trapaddr
+ assign \oper_i__fn_unit$16 11'00000000000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ switch { \can_run }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+ switch \insn_type
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+ attribute \nmigen.decoding "OP_ATTN/5"
+ case 7'0000101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \nmigen.decoding "OP_NOP/1"
+ case 7'0000001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+ attribute \nmigen.decoding ""
+ case
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ switch { \fu_enable [3] }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ case 1'1
+ assign \oper_i__fn_unit$16 \fn_unit
+ end
+ end
end
sync init
end
process $group_54
- assign \issue_i$17 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- switch { \en_trap0 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- case 1'1
- assign \issue_i$17 \issue_i
+ assign \oper_i__insn$17 32'00000000000000000000000000000000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ switch { \can_run }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+ switch \insn_type
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+ attribute \nmigen.decoding "OP_ATTN/5"
+ case 7'0000101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \nmigen.decoding "OP_NOP/1"
+ case 7'0000001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+ attribute \nmigen.decoding ""
+ case
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ switch { \fu_enable [3] }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ case 1'1
+ assign \oper_i__insn$17 \insn
+ end
+ end
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:118"
- wire width 6 $259
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:118"
- cell $not $260
- parameter \A_SIGNED 0
- parameter \A_WIDTH 6
- parameter \Y_WIDTH 6
- connect \A { 1'1 1'1 \fast2_ok \fast1_ok \reg2_ok \reg1_ok }
- connect \Y $259
- end
process $group_55
- assign \fus_rdmaskn$139 6'000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- switch { \en_trap0 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- case 1'1
- assign \fus_rdmaskn$139 $259
+ assign \oper_i__msr 64'0000000000000000000000000000000000000000000000000000000000000000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ switch { \can_run }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+ switch \insn_type
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+ attribute \nmigen.decoding "OP_ATTN/5"
+ case 7'0000101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \nmigen.decoding "OP_NOP/1"
+ case 7'0000001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+ attribute \nmigen.decoding ""
+ case
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ switch { \fu_enable [3] }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ case 1'1
+ assign \oper_i__msr \msr$18
+ end
+ end
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:112"
- wire width 1 $261
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:112"
- wire width 11 $262
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:112"
- cell $and $263
- parameter \A_SIGNED 0
- parameter \A_WIDTH 11
- parameter \B_SIGNED 0
- parameter \B_WIDTH 5
- parameter \Y_WIDTH 11
- connect \A \fn_unit
- connect \B 5'10000
- connect \Y $262
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:112"
- cell $reduce_bool $264
- parameter \A_SIGNED 0
- parameter \A_WIDTH 11
- parameter \Y_WIDTH 1
- connect \A $262
- connect \Y $261
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:112"
- wire width 1 $265
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:112"
- cell $and $266
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \valid
- connect \B $261
- connect \Y $265
- end
process $group_56
- assign \en_logical0 1'0
- assign \en_logical0 $265
+ assign \oper_i__cia$19 64'0000000000000000000000000000000000000000000000000000000000000000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ switch { \can_run }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+ switch \insn_type
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+ attribute \nmigen.decoding "OP_ATTN/5"
+ case 7'0000101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \nmigen.decoding "OP_NOP/1"
+ case 7'0000001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+ attribute \nmigen.decoding ""
+ case
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ switch { \fu_enable [3] }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ case 1'1
+ assign \oper_i__cia$19 \cia$8
+ end
+ end
+ end
sync init
end
process $group_57
- assign \oper_i__insn_type$19 7'0000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- switch { \en_logical0 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- case 1'1
- assign \oper_i__insn_type$19 \insn_type
+ assign \oper_i__is_32bit$20 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ switch { \can_run }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+ switch \insn_type
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+ attribute \nmigen.decoding "OP_ATTN/5"
+ case 7'0000101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \nmigen.decoding "OP_NOP/1"
+ case 7'0000001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+ attribute \nmigen.decoding ""
+ case
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ switch { \fu_enable [3] }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ case 1'1
+ assign \oper_i__is_32bit$20 \is_32bit
+ end
+ end
end
sync init
end
process $group_58
- assign \oper_i__fn_unit$20 11'00000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- switch { \en_logical0 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- case 1'1
- assign \oper_i__fn_unit$20 \fn_unit
+ assign \oper_i__traptype 5'00000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ switch { \can_run }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+ switch \insn_type
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+ attribute \nmigen.decoding "OP_ATTN/5"
+ case 7'0000101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \nmigen.decoding "OP_NOP/1"
+ case 7'0000001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+ attribute \nmigen.decoding ""
+ case
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ switch { \fu_enable [3] }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ case 1'1
+ assign \oper_i__traptype \traptype
+ end
+ end
end
sync init
end
process $group_59
- assign \fus_oper_i__imm_data__imm$140 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \fus_oper_i__imm_data__imm_ok$141 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- switch { \en_logical0 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- case 1'1
- assign { \fus_oper_i__imm_data__imm_ok$141 \fus_oper_i__imm_data__imm$140 } { \imm_ok \imm }
+ assign \oper_i__trapaddr 13'0000000000000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ switch { \can_run }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+ switch \insn_type
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+ attribute \nmigen.decoding "OP_ATTN/5"
+ case 7'0000101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \nmigen.decoding "OP_NOP/1"
+ case 7'0000001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+ attribute \nmigen.decoding ""
+ case
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ switch { \fu_enable [3] }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ case 1'1
+ assign \oper_i__trapaddr \trapaddr
+ end
+ end
+ end
+ sync init
+ end
+ process $group_60
+ assign \issue_i$21 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ switch { \can_run }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+ switch \insn_type
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+ attribute \nmigen.decoding "OP_ATTN/5"
+ case 7'0000101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \nmigen.decoding "OP_NOP/1"
+ case 7'0000001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+ attribute \nmigen.decoding ""
+ case
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ switch { \fu_enable [3] }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ case 1'1
+ assign \issue_i$21 \issue_i
+ end
+ end
end
sync init
end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:179"
+ wire width 4 $318
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:179"
+ cell $not $319
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 4
+ parameter \Y_WIDTH 4
+ connect \A { \fast2_ok \fast1_ok \reg2_ok \reg1_ok }
+ connect \Y $318
+ end
process $group_61
- assign \oper_i__lk$21 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- switch { \en_logical0 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- case 1'1
- assign \oper_i__lk$21 \lk
+ assign \fus_rdmaskn$164 4'0000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ switch { \can_run }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+ switch \insn_type
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+ attribute \nmigen.decoding "OP_ATTN/5"
+ case 7'0000101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \nmigen.decoding "OP_NOP/1"
+ case 7'0000001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+ attribute \nmigen.decoding ""
+ case
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ switch { \fu_enable [3] }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ case 1'1
+ assign \fus_rdmaskn$164 $318
+ end
+ end
end
sync init
end
process $group_62
- assign \fus_oper_i__rc__rc$142 1'0
- assign \fus_oper_i__rc__rc_ok$143 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- switch { \en_logical0 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- case 1'1
- assign { \fus_oper_i__rc__rc_ok$143 \fus_oper_i__rc__rc$142 } { \rc_ok \rc }
+ assign \oper_i__insn_type$23 7'0000000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ switch { \can_run }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+ switch \insn_type
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+ attribute \nmigen.decoding "OP_ATTN/5"
+ case 7'0000101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \nmigen.decoding "OP_NOP/1"
+ case 7'0000001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+ attribute \nmigen.decoding ""
+ case
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ switch { \fu_enable [4] }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ case 1'1
+ assign \oper_i__insn_type$23 \insn_type
+ end
+ end
end
sync init
end
- process $group_64
- assign \fus_oper_i__oe__oe$144 1'0
- assign \fus_oper_i__oe__oe_ok$145 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- switch { \en_logical0 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- case 1'1
- assign { \fus_oper_i__oe__oe_ok$145 \fus_oper_i__oe__oe$144 } { \oe_ok \oe }
+ process $group_63
+ assign \oper_i__fn_unit$24 11'00000000000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ switch { \can_run }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+ switch \insn_type
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+ attribute \nmigen.decoding "OP_ATTN/5"
+ case 7'0000101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \nmigen.decoding "OP_NOP/1"
+ case 7'0000001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+ attribute \nmigen.decoding ""
+ case
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ switch { \fu_enable [4] }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ case 1'1
+ assign \oper_i__fn_unit$24 \fn_unit
+ end
+ end
end
sync init
end
- process $group_66
- assign \oper_i__invert_a$22 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- switch { \en_logical0 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- case 1'1
- assign \oper_i__invert_a$22 \invert_a
+ process $group_64
+ assign \fus_oper_i__imm_data__imm$165 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \fus_oper_i__imm_data__imm_ok$166 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ switch { \can_run }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+ switch \insn_type
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+ attribute \nmigen.decoding "OP_ATTN/5"
+ case 7'0000101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \nmigen.decoding "OP_NOP/1"
+ case 7'0000001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+ attribute \nmigen.decoding ""
+ case
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ switch { \fu_enable [4] }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ case 1'1
+ assign { \fus_oper_i__imm_data__imm_ok$166 \fus_oper_i__imm_data__imm$165 } { \imm_ok \imm }
+ end
+ end
end
sync init
end
- process $group_67
- assign \fus_oper_i__zero_a$146 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- switch { \en_logical0 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- case 1'1
- assign \fus_oper_i__zero_a$146 \zero_a
+ process $group_66
+ assign \fus_oper_i__rc__rc$167 1'0
+ assign \fus_oper_i__rc__rc_ok$168 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ switch { \can_run }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+ switch \insn_type
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+ attribute \nmigen.decoding "OP_ATTN/5"
+ case 7'0000101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \nmigen.decoding "OP_NOP/1"
+ case 7'0000001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+ attribute \nmigen.decoding ""
+ case
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ switch { \fu_enable [4] }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ case 1'1
+ assign { \fus_oper_i__rc__rc_ok$168 \fus_oper_i__rc__rc$167 } { \rc_ok \rc }
+ end
+ end
end
sync init
end
process $group_68
- assign \oper_i__input_carry$23 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- switch { \en_logical0 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- case 1'1
- assign \oper_i__input_carry$23 \input_carry
+ assign \fus_oper_i__oe__oe$169 1'0
+ assign \fus_oper_i__oe__oe_ok$170 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ switch { \can_run }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+ switch \insn_type
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+ attribute \nmigen.decoding "OP_ATTN/5"
+ case 7'0000101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \nmigen.decoding "OP_NOP/1"
+ case 7'0000001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+ attribute \nmigen.decoding ""
+ case
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ switch { \fu_enable [4] }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ case 1'1
+ assign { \fus_oper_i__oe__oe_ok$170 \fus_oper_i__oe__oe$169 } { \oe_ok \oe }
+ end
+ end
end
sync init
end
- process $group_69
- assign \oper_i__invert_out$24 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- switch { \en_logical0 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- case 1'1
- assign \oper_i__invert_out$24 \invert_out
+ process $group_70
+ assign \oper_i__invert_a$25 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ switch { \can_run }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+ switch \insn_type
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+ attribute \nmigen.decoding "OP_ATTN/5"
+ case 7'0000101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \nmigen.decoding "OP_NOP/1"
+ case 7'0000001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+ attribute \nmigen.decoding ""
+ case
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ switch { \fu_enable [4] }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ case 1'1
+ assign \oper_i__invert_a$25 \invert_a
+ end
+ end
end
sync init
end
- process $group_70
- assign \fus_oper_i__write_cr__data$147 3'000
- assign \fus_oper_i__write_cr__ok$148 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- switch { \en_logical0 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- case 1'1
- assign { \fus_oper_i__write_cr__ok$148 \fus_oper_i__write_cr__data$147 } { \cr_out_ok \cr_out }
+ process $group_71
+ assign \oper_i__zero_a$26 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ switch { \can_run }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+ switch \insn_type
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+ attribute \nmigen.decoding "OP_ATTN/5"
+ case 7'0000101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \nmigen.decoding "OP_NOP/1"
+ case 7'0000001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+ attribute \nmigen.decoding ""
+ case
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ switch { \fu_enable [4] }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ case 1'1
+ assign \oper_i__zero_a$26 \zero_a
+ end
+ end
end
sync init
end
process $group_72
- assign \oper_i__output_carry$25 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- switch { \en_logical0 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- case 1'1
- assign \oper_i__output_carry$25 \output_carry
+ assign \oper_i__input_carry$27 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ switch { \can_run }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+ switch \insn_type
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+ attribute \nmigen.decoding "OP_ATTN/5"
+ case 7'0000101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \nmigen.decoding "OP_NOP/1"
+ case 7'0000001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+ attribute \nmigen.decoding ""
+ case
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ switch { \fu_enable [4] }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ case 1'1
+ assign \oper_i__input_carry$27 \input_carry
+ end
+ end
end
sync init
end
process $group_73
- assign \oper_i__is_32bit$26 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- switch { \en_logical0 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- case 1'1
- assign \oper_i__is_32bit$26 \is_32bit
+ assign \oper_i__invert_out$28 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ switch { \can_run }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+ switch \insn_type
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+ attribute \nmigen.decoding "OP_ATTN/5"
+ case 7'0000101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \nmigen.decoding "OP_NOP/1"
+ case 7'0000001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+ attribute \nmigen.decoding ""
+ case
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ switch { \fu_enable [4] }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ case 1'1
+ assign \oper_i__invert_out$28 \invert_out
+ end
+ end
end
sync init
end
process $group_74
- assign \oper_i__is_signed$27 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- switch { \en_logical0 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- case 1'1
- assign \oper_i__is_signed$27 \is_signed
+ assign \oper_i__write_cr0$29 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ switch { \can_run }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+ switch \insn_type
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+ attribute \nmigen.decoding "OP_ATTN/5"
+ case 7'0000101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \nmigen.decoding "OP_NOP/1"
+ case 7'0000001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+ attribute \nmigen.decoding ""
+ case
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ switch { \fu_enable [4] }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ case 1'1
+ assign \oper_i__write_cr0$29 \write_cr0
+ end
+ end
end
sync init
end
process $group_75
- assign \oper_i__data_len$28 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- switch { \en_logical0 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- case 1'1
- assign \oper_i__data_len$28 \data_len
+ assign \oper_i__output_carry$30 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ switch { \can_run }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+ switch \insn_type
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+ attribute \nmigen.decoding "OP_ATTN/5"
+ case 7'0000101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \nmigen.decoding "OP_NOP/1"
+ case 7'0000001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+ attribute \nmigen.decoding ""
+ case
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ switch { \fu_enable [4] }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ case 1'1
+ assign \oper_i__output_carry$30 \output_carry
+ end
+ end
end
sync init
end
process $group_76
- assign \fus_oper_i__insn$149 32'00000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- switch { \en_logical0 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- case 1'1
- assign \fus_oper_i__insn$149 \insn
+ assign \oper_i__is_32bit$31 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ switch { \can_run }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+ switch \insn_type
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+ attribute \nmigen.decoding "OP_ATTN/5"
+ case 7'0000101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \nmigen.decoding "OP_NOP/1"
+ case 7'0000001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+ attribute \nmigen.decoding ""
+ case
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ switch { \fu_enable [4] }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ case 1'1
+ assign \oper_i__is_32bit$31 \is_32bit
+ end
+ end
end
sync init
end
process $group_77
- assign \issue_i$29 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- switch { \en_logical0 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- case 1'1
- assign \issue_i$29 \issue_i
+ assign \oper_i__is_signed$32 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ switch { \can_run }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+ switch \insn_type
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+ attribute \nmigen.decoding "OP_ATTN/5"
+ case 7'0000101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \nmigen.decoding "OP_NOP/1"
+ case 7'0000001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+ attribute \nmigen.decoding ""
+ case
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ switch { \fu_enable [4] }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ case 1'1
+ assign \oper_i__is_signed$32 \is_signed
+ end
+ end
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:118"
- wire width 2 $267
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:118"
- cell $not $268
- parameter \A_SIGNED 0
- parameter \A_WIDTH 2
- parameter \Y_WIDTH 2
- connect \A { \reg2_ok \reg1_ok }
- connect \Y $267
- end
process $group_78
- assign \fus_rdmaskn$150 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- switch { \en_logical0 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- case 1'1
- assign \fus_rdmaskn$150 $267
+ assign \oper_i__data_len$33 4'0000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ switch { \can_run }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+ switch \insn_type
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+ attribute \nmigen.decoding "OP_ATTN/5"
+ case 7'0000101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \nmigen.decoding "OP_NOP/1"
+ case 7'0000001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+ attribute \nmigen.decoding ""
+ case
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ switch { \fu_enable [4] }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ case 1'1
+ assign \oper_i__data_len$33 \data_len
+ end
+ end
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:112"
- wire width 1 $269
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:112"
- wire width 11 $270
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:112"
- cell $and $271
- parameter \A_SIGNED 0
- parameter \A_WIDTH 11
- parameter \B_SIGNED 0
- parameter \B_WIDTH 11
- parameter \Y_WIDTH 11
- connect \A \fn_unit
- connect \B 11'10000000000
- connect \Y $270
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:112"
- cell $reduce_bool $272
- parameter \A_SIGNED 0
- parameter \A_WIDTH 11
- parameter \Y_WIDTH 1
- connect \A $270
- connect \Y $269
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:112"
- wire width 1 $273
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:112"
- cell $and $274
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \valid
- connect \B $269
- connect \Y $273
- end
process $group_79
- assign \en_spr0 1'0
- assign \en_spr0 $273
+ assign \oper_i__insn$34 32'00000000000000000000000000000000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ switch { \can_run }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+ switch \insn_type
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+ attribute \nmigen.decoding "OP_ATTN/5"
+ case 7'0000101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \nmigen.decoding "OP_NOP/1"
+ case 7'0000001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+ attribute \nmigen.decoding ""
+ case
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ switch { \fu_enable [4] }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ case 1'1
+ assign \oper_i__insn$34 \insn
+ end
+ end
+ end
sync init
end
process $group_80
- assign \oper_i__insn_type$31 7'0000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- switch { \en_spr0 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- case 1'1
- assign \oper_i__insn_type$31 \insn_type
+ assign \issue_i$35 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ switch { \can_run }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+ switch \insn_type
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+ attribute \nmigen.decoding "OP_ATTN/5"
+ case 7'0000101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \nmigen.decoding "OP_NOP/1"
+ case 7'0000001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+ attribute \nmigen.decoding ""
+ case
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ switch { \fu_enable [4] }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ case 1'1
+ assign \issue_i$35 \issue_i
+ end
+ end
end
sync init
end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:179"
+ wire width 2 $320
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:179"
+ cell $not $321
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 2
+ parameter \Y_WIDTH 2
+ connect \A { \reg2_ok \reg1_ok }
+ connect \Y $320
+ end
process $group_81
- assign \oper_i__fn_unit$32 11'00000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- switch { \en_spr0 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- case 1'1
- assign \oper_i__fn_unit$32 \fn_unit
+ assign \fus_rdmaskn$171 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ switch { \can_run }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+ switch \insn_type
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+ attribute \nmigen.decoding "OP_ATTN/5"
+ case 7'0000101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \nmigen.decoding "OP_NOP/1"
+ case 7'0000001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+ attribute \nmigen.decoding ""
+ case
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ switch { \fu_enable [4] }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ case 1'1
+ assign \fus_rdmaskn$171 $320
+ end
+ end
end
sync init
end
process $group_82
- assign \oper_i__insn$33 32'00000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- switch { \en_spr0 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- case 1'1
- assign \oper_i__insn$33 \insn
+ assign \oper_i__insn_type$37 7'0000000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ switch { \can_run }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+ switch \insn_type
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+ attribute \nmigen.decoding "OP_ATTN/5"
+ case 7'0000101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \nmigen.decoding "OP_NOP/1"
+ case 7'0000001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+ attribute \nmigen.decoding ""
+ case
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ switch { \fu_enable [5] }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ case 1'1
+ assign \oper_i__insn_type$37 \insn_type
+ end
+ end
end
sync init
end
process $group_83
- assign \oper_i__is_32bit$34 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- switch { \en_spr0 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- case 1'1
- assign \oper_i__is_32bit$34 \is_32bit
+ assign \oper_i__fn_unit$38 11'00000000000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ switch { \can_run }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+ switch \insn_type
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+ attribute \nmigen.decoding "OP_ATTN/5"
+ case 7'0000101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \nmigen.decoding "OP_NOP/1"
+ case 7'0000001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+ attribute \nmigen.decoding ""
+ case
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ switch { \fu_enable [5] }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ case 1'1
+ assign \oper_i__fn_unit$38 \fn_unit
+ end
+ end
end
sync init
end
process $group_84
- assign \issue_i$35 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- switch { \en_spr0 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- case 1'1
- assign \issue_i$35 \issue_i
+ assign \oper_i__insn$39 32'00000000000000000000000000000000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ switch { \can_run }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+ switch \insn_type
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+ attribute \nmigen.decoding "OP_ATTN/5"
+ case 7'0000101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \nmigen.decoding "OP_NOP/1"
+ case 7'0000001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+ attribute \nmigen.decoding ""
+ case
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ switch { \fu_enable [5] }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ case 1'1
+ assign \oper_i__insn$39 \insn
+ end
+ end
+ end
+ sync init
+ end
+ process $group_85
+ assign \oper_i__is_32bit$40 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ switch { \can_run }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+ switch \insn_type
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+ attribute \nmigen.decoding "OP_ATTN/5"
+ case 7'0000101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \nmigen.decoding "OP_NOP/1"
+ case 7'0000001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+ attribute \nmigen.decoding ""
+ case
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ switch { \fu_enable [5] }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ case 1'1
+ assign \oper_i__is_32bit$40 \is_32bit
+ end
+ end
+ end
+ sync init
+ end
+ process $group_86
+ assign \issue_i$41 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ switch { \can_run }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+ switch \insn_type
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+ attribute \nmigen.decoding "OP_ATTN/5"
+ case 7'0000101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \nmigen.decoding "OP_NOP/1"
+ case 7'0000001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+ attribute \nmigen.decoding ""
+ case
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ switch { \fu_enable [5] }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ case 1'1
+ assign \issue_i$41 \issue_i
+ end
+ end
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:118"
- wire width 6 $275
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:71"
- wire width 1 $276
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:71"
- cell $and $277
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:179"
+ wire width 6 $322
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79"
+ wire width 1 $323
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79"
+ cell $and $324
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \oe
connect \B \oe_ok
- connect \Y $276
+ connect \Y $323
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:73"
- wire width 1 $278
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:73"
- cell $and $279
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79"
+ wire width 1 $325
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79"
+ cell $or $326
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A $323
+ connect \B \xer_in
+ connect \Y $325
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81"
+ wire width 1 $327
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81"
+ cell $and $328
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \oe
connect \B \oe_ok
- connect \Y $278
+ connect \Y $327
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81"
+ wire width 1 $329
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81"
+ cell $or $330
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A $327
+ connect \B \xer_in
+ connect \Y $329
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:75"
- wire width 1 $280
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:75"
- cell $eq $281
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83"
+ wire width 1 $331
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83"
+ cell $eq $332
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \input_carry
connect \B 2'10
- connect \Y $280
+ connect \Y $331
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:118"
- cell $not $282
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83"
+ wire width 1 $333
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83"
+ cell $or $334
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A $331
+ connect \B \xer_in
+ connect \Y $333
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:179"
+ cell $not $335
parameter \A_SIGNED 0
parameter \A_WIDTH 6
parameter \Y_WIDTH 6
- connect \A { $280 $278 $276 \fast1_ok \spr1_ok \reg1_ok }
- connect \Y $275
+ connect \A { $333 $329 $325 \fast1_ok \spr1_ok \reg1_ok }
+ connect \Y $322
end
- process $group_85
- assign \fus_rdmaskn$151 6'000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- switch { \en_spr0 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- case 1'1
- assign \fus_rdmaskn$151 $275
+ process $group_87
+ assign \fus_rdmaskn$172 6'000000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ switch { \can_run }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+ switch \insn_type
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+ attribute \nmigen.decoding "OP_ATTN/5"
+ case 7'0000101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \nmigen.decoding "OP_NOP/1"
+ case 7'0000001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+ attribute \nmigen.decoding ""
+ case
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ switch { \fu_enable [5] }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ case 1'1
+ assign \fus_rdmaskn$172 $322
+ end
+ end
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:112"
- wire width 1 $283
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:112"
- wire width 11 $284
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:112"
- cell $and $285
- parameter \A_SIGNED 0
- parameter \A_WIDTH 11
- parameter \B_SIGNED 0
- parameter \B_WIDTH 4
- parameter \Y_WIDTH 11
- connect \A \fn_unit
- connect \B 4'1000
- connect \Y $284
+ process $group_88
+ assign \oper_i__insn_type$43 7'0000000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ switch { \can_run }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+ switch \insn_type
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+ attribute \nmigen.decoding "OP_ATTN/5"
+ case 7'0000101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \nmigen.decoding "OP_NOP/1"
+ case 7'0000001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+ attribute \nmigen.decoding ""
+ case
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ switch { \fu_enable [6] }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ case 1'1
+ assign \oper_i__insn_type$43 \insn_type
+ end
+ end
+ end
+ sync init
+ end
+ process $group_89
+ assign \oper_i__fn_unit$44 11'00000000000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ switch { \can_run }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+ switch \insn_type
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+ attribute \nmigen.decoding "OP_ATTN/5"
+ case 7'0000101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \nmigen.decoding "OP_NOP/1"
+ case 7'0000001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+ attribute \nmigen.decoding ""
+ case
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ switch { \fu_enable [6] }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ case 1'1
+ assign \oper_i__fn_unit$44 \fn_unit
+ end
+ end
+ end
+ sync init
+ end
+ process $group_90
+ assign \fus_oper_i__imm_data__imm$173 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \fus_oper_i__imm_data__imm_ok$174 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ switch { \can_run }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+ switch \insn_type
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+ attribute \nmigen.decoding "OP_ATTN/5"
+ case 7'0000101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \nmigen.decoding "OP_NOP/1"
+ case 7'0000001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+ attribute \nmigen.decoding ""
+ case
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ switch { \fu_enable [6] }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ case 1'1
+ assign { \fus_oper_i__imm_data__imm_ok$174 \fus_oper_i__imm_data__imm$173 } { \imm_ok \imm }
+ end
+ end
+ end
+ sync init
+ end
+ process $group_92
+ assign \fus_oper_i__rc__rc$175 1'0
+ assign \fus_oper_i__rc__rc_ok$176 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ switch { \can_run }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+ switch \insn_type
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+ attribute \nmigen.decoding "OP_ATTN/5"
+ case 7'0000101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \nmigen.decoding "OP_NOP/1"
+ case 7'0000001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+ attribute \nmigen.decoding ""
+ case
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ switch { \fu_enable [6] }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ case 1'1
+ assign { \fus_oper_i__rc__rc_ok$176 \fus_oper_i__rc__rc$175 } { \rc_ok \rc }
+ end
+ end
+ end
+ sync init
+ end
+ process $group_94
+ assign \fus_oper_i__oe__oe$177 1'0
+ assign \fus_oper_i__oe__oe_ok$178 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ switch { \can_run }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+ switch \insn_type
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+ attribute \nmigen.decoding "OP_ATTN/5"
+ case 7'0000101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \nmigen.decoding "OP_NOP/1"
+ case 7'0000001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+ attribute \nmigen.decoding ""
+ case
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ switch { \fu_enable [6] }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ case 1'1
+ assign { \fus_oper_i__oe__oe_ok$178 \fus_oper_i__oe__oe$177 } { \oe_ok \oe }
+ end
+ end
+ end
+ sync init
+ end
+ process $group_96
+ assign \oper_i__invert_a$45 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ switch { \can_run }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+ switch \insn_type
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+ attribute \nmigen.decoding "OP_ATTN/5"
+ case 7'0000101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \nmigen.decoding "OP_NOP/1"
+ case 7'0000001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+ attribute \nmigen.decoding ""
+ case
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ switch { \fu_enable [6] }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ case 1'1
+ assign \oper_i__invert_a$45 \invert_a
+ end
+ end
+ end
+ sync init
+ end
+ process $group_97
+ assign \oper_i__zero_a$46 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ switch { \can_run }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+ switch \insn_type
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+ attribute \nmigen.decoding "OP_ATTN/5"
+ case 7'0000101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \nmigen.decoding "OP_NOP/1"
+ case 7'0000001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+ attribute \nmigen.decoding ""
+ case
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ switch { \fu_enable [6] }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ case 1'1
+ assign \oper_i__zero_a$46 \zero_a
+ end
+ end
+ end
+ sync init
+ end
+ process $group_98
+ assign \oper_i__invert_out$47 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ switch { \can_run }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+ switch \insn_type
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+ attribute \nmigen.decoding "OP_ATTN/5"
+ case 7'0000101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \nmigen.decoding "OP_NOP/1"
+ case 7'0000001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+ attribute \nmigen.decoding ""
+ case
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ switch { \fu_enable [6] }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ case 1'1
+ assign \oper_i__invert_out$47 \invert_out
+ end
+ end
+ end
+ sync init
+ end
+ process $group_99
+ assign \oper_i__write_cr0$48 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ switch { \can_run }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+ switch \insn_type
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+ attribute \nmigen.decoding "OP_ATTN/5"
+ case 7'0000101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \nmigen.decoding "OP_NOP/1"
+ case 7'0000001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+ attribute \nmigen.decoding ""
+ case
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ switch { \fu_enable [6] }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ case 1'1
+ assign \oper_i__write_cr0$48 \write_cr0
+ end
+ end
+ end
+ sync init
+ end
+ process $group_100
+ assign \oper_i__is_32bit$49 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ switch { \can_run }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+ switch \insn_type
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+ attribute \nmigen.decoding "OP_ATTN/5"
+ case 7'0000101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \nmigen.decoding "OP_NOP/1"
+ case 7'0000001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+ attribute \nmigen.decoding ""
+ case
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ switch { \fu_enable [6] }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ case 1'1
+ assign \oper_i__is_32bit$49 \is_32bit
+ end
+ end
+ end
+ sync init
+ end
+ process $group_101
+ assign \oper_i__is_signed$50 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ switch { \can_run }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+ switch \insn_type
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+ attribute \nmigen.decoding "OP_ATTN/5"
+ case 7'0000101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \nmigen.decoding "OP_NOP/1"
+ case 7'0000001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+ attribute \nmigen.decoding ""
+ case
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ switch { \fu_enable [6] }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ case 1'1
+ assign \oper_i__is_signed$50 \is_signed
+ end
+ end
+ end
+ sync init
+ end
+ process $group_102
+ assign \oper_i__insn$51 32'00000000000000000000000000000000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ switch { \can_run }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+ switch \insn_type
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+ attribute \nmigen.decoding "OP_ATTN/5"
+ case 7'0000101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \nmigen.decoding "OP_NOP/1"
+ case 7'0000001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+ attribute \nmigen.decoding ""
+ case
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ switch { \fu_enable [6] }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ case 1'1
+ assign \oper_i__insn$51 \insn
+ end
+ end
+ end
+ sync init
+ end
+ process $group_103
+ assign \issue_i$52 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ switch { \can_run }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+ switch \insn_type
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+ attribute \nmigen.decoding "OP_ATTN/5"
+ case 7'0000101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \nmigen.decoding "OP_NOP/1"
+ case 7'0000001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+ attribute \nmigen.decoding ""
+ case
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ switch { \fu_enable [6] }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ case 1'1
+ assign \issue_i$52 \issue_i
+ end
+ end
+ end
+ sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:112"
- cell $reduce_bool $286
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:179"
+ wire width 3 $336
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79"
+ wire width 1 $337
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79"
+ cell $and $338
parameter \A_SIGNED 0
- parameter \A_WIDTH 11
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $284
- connect \Y $283
+ connect \A \oe
+ connect \B \oe_ok
+ connect \Y $337
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:112"
- wire width 1 $287
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:112"
- cell $and $288
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79"
+ wire width 1 $339
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79"
+ cell $or $340
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \valid
- connect \B $283
- connect \Y $287
+ connect \A $337
+ connect \B \xer_in
+ connect \Y $339
end
- process $group_86
- assign \en_shiftrot0 1'0
- assign \en_shiftrot0 $287
- sync init
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:179"
+ cell $not $341
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 3
+ parameter \Y_WIDTH 3
+ connect \A { $339 \reg2_ok \reg1_ok }
+ connect \Y $336
end
- process $group_87
- assign \oper_i__insn_type$37 7'0000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- switch { \en_shiftrot0 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- case 1'1
- assign \oper_i__insn_type$37 \insn_type
+ process $group_104
+ assign \fus_rdmaskn$179 3'000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ switch { \can_run }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+ switch \insn_type
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+ attribute \nmigen.decoding "OP_ATTN/5"
+ case 7'0000101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \nmigen.decoding "OP_NOP/1"
+ case 7'0000001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+ attribute \nmigen.decoding ""
+ case
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ switch { \fu_enable [6] }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ case 1'1
+ assign \fus_rdmaskn$179 $336
+ end
+ end
end
sync init
end
- process $group_88
- assign \fus_oper_i__fn_unit$152 11'00000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- switch { \en_shiftrot0 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- case 1'1
- assign \fus_oper_i__fn_unit$152 \fn_unit
+ process $group_105
+ assign \oper_i__insn_type$54 7'0000000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ switch { \can_run }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+ switch \insn_type
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+ attribute \nmigen.decoding "OP_ATTN/5"
+ case 7'0000101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \nmigen.decoding "OP_NOP/1"
+ case 7'0000001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+ attribute \nmigen.decoding ""
+ case
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ switch { \fu_enable [7] }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ case 1'1
+ assign \oper_i__insn_type$54 \insn_type
+ end
+ end
end
sync init
end
- process $group_89
- assign \fus_oper_i__imm_data__imm$153 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \fus_oper_i__imm_data__imm_ok$154 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- switch { \en_shiftrot0 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- case 1'1
- assign { \fus_oper_i__imm_data__imm_ok$154 \fus_oper_i__imm_data__imm$153 } { \imm_ok \imm }
+ process $group_106
+ assign \oper_i__fn_unit$55 11'00000000000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ switch { \can_run }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+ switch \insn_type
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+ attribute \nmigen.decoding "OP_ATTN/5"
+ case 7'0000101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \nmigen.decoding "OP_NOP/1"
+ case 7'0000001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+ attribute \nmigen.decoding ""
+ case
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ switch { \fu_enable [7] }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ case 1'1
+ assign \oper_i__fn_unit$55 \fn_unit
+ end
+ end
end
sync init
end
- process $group_91
- assign \fus_oper_i__rc__rc$155 1'0
- assign \fus_oper_i__rc__rc_ok$156 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- switch { \en_shiftrot0 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- case 1'1
- assign { \fus_oper_i__rc__rc_ok$156 \fus_oper_i__rc__rc$155 } { \rc_ok \rc }
+ process $group_107
+ assign \fus_oper_i__imm_data__imm$180 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \fus_oper_i__imm_data__imm_ok$181 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ switch { \can_run }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+ switch \insn_type
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+ attribute \nmigen.decoding "OP_ATTN/5"
+ case 7'0000101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \nmigen.decoding "OP_NOP/1"
+ case 7'0000001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+ attribute \nmigen.decoding ""
+ case
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ switch { \fu_enable [7] }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ case 1'1
+ assign { \fus_oper_i__imm_data__imm_ok$181 \fus_oper_i__imm_data__imm$180 } { \imm_ok \imm }
+ end
+ end
+ end
+ sync init
+ end
+ process $group_109
+ assign \fus_oper_i__rc__rc$182 1'0
+ assign \fus_oper_i__rc__rc_ok$183 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ switch { \can_run }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+ switch \insn_type
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+ attribute \nmigen.decoding "OP_ATTN/5"
+ case 7'0000101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \nmigen.decoding "OP_NOP/1"
+ case 7'0000001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+ attribute \nmigen.decoding ""
+ case
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ switch { \fu_enable [7] }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ case 1'1
+ assign { \fus_oper_i__rc__rc_ok$183 \fus_oper_i__rc__rc$182 } { \rc_ok \rc }
+ end
+ end
end
sync init
end
- process $group_93
- assign \fus_oper_i__oe__oe$157 1'0
- assign \fus_oper_i__oe__oe_ok$158 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- switch { \en_shiftrot0 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- case 1'1
- assign { \fus_oper_i__oe__oe_ok$158 \fus_oper_i__oe__oe$157 } { \oe_ok \oe }
+ process $group_111
+ assign \fus_oper_i__oe__oe$184 1'0
+ assign \fus_oper_i__oe__oe_ok$185 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ switch { \can_run }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+ switch \insn_type
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+ attribute \nmigen.decoding "OP_ATTN/5"
+ case 7'0000101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \nmigen.decoding "OP_NOP/1"
+ case 7'0000001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+ attribute \nmigen.decoding ""
+ case
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ switch { \fu_enable [7] }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ case 1'1
+ assign { \fus_oper_i__oe__oe_ok$185 \fus_oper_i__oe__oe$184 } { \oe_ok \oe }
+ end
+ end
end
sync init
end
- process $group_95
- assign \fus_oper_i__write_cr__data$159 3'000
- assign \fus_oper_i__write_cr__ok$160 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- switch { \en_shiftrot0 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- case 1'1
- assign { \fus_oper_i__write_cr__ok$160 \fus_oper_i__write_cr__data$159 } { \cr_out_ok \cr_out }
+ process $group_113
+ assign { } 0'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ switch { \can_run }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+ switch \insn_type
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+ attribute \nmigen.decoding "OP_ATTN/5"
+ case 7'0000101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \nmigen.decoding "OP_NOP/1"
+ case 7'0000001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+ attribute \nmigen.decoding ""
+ case
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ switch { \fu_enable [7] }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ case 1'1
+ assign { } {}
+ end
+ end
end
sync init
end
- process $group_97
- assign \oper_i__input_carry$38 2'00
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- switch { \en_shiftrot0 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- case 1'1
- assign \oper_i__input_carry$38 \input_carry
+ process $group_114
+ assign \oper_i__input_carry$56 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ switch { \can_run }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+ switch \insn_type
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+ attribute \nmigen.decoding "OP_ATTN/5"
+ case 7'0000101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \nmigen.decoding "OP_NOP/1"
+ case 7'0000001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+ attribute \nmigen.decoding ""
+ case
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ switch { \fu_enable [7] }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ case 1'1
+ assign \oper_i__input_carry$56 \input_carry
+ end
+ end
end
sync init
end
- process $group_98
- assign \oper_i__output_carry$39 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- switch { \en_shiftrot0 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- case 1'1
- assign \oper_i__output_carry$39 \output_carry
+ process $group_115
+ assign \oper_i__output_carry$57 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ switch { \can_run }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+ switch \insn_type
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+ attribute \nmigen.decoding "OP_ATTN/5"
+ case 7'0000101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \nmigen.decoding "OP_NOP/1"
+ case 7'0000001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+ attribute \nmigen.decoding ""
+ case
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ switch { \fu_enable [7] }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ case 1'1
+ assign \oper_i__output_carry$57 \output_carry
+ end
+ end
end
sync init
end
- process $group_99
- assign \oper_i__input_cr$40 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- switch { \en_shiftrot0 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- case 1'1
- assign \oper_i__input_cr$40 \input_cr
+ process $group_116
+ assign \oper_i__input_cr 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ switch { \can_run }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+ switch \insn_type
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+ attribute \nmigen.decoding "OP_ATTN/5"
+ case 7'0000101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \nmigen.decoding "OP_NOP/1"
+ case 7'0000001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+ attribute \nmigen.decoding ""
+ case
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ switch { \fu_enable [7] }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ case 1'1
+ assign \oper_i__input_cr \input_cr
+ end
+ end
end
sync init
end
- process $group_100
- assign \oper_i__output_cr$41 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- switch { \en_shiftrot0 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- case 1'1
- assign \oper_i__output_cr$41 \output_cr
+ process $group_117
+ assign \oper_i__output_cr 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ switch { \can_run }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+ switch \insn_type
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+ attribute \nmigen.decoding "OP_ATTN/5"
+ case 7'0000101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \nmigen.decoding "OP_NOP/1"
+ case 7'0000001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+ attribute \nmigen.decoding ""
+ case
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ switch { \fu_enable [7] }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ case 1'1
+ assign \oper_i__output_cr \output_cr
+ end
+ end
end
sync init
end
- process $group_101
- assign \oper_i__is_32bit$42 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- switch { \en_shiftrot0 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- case 1'1
- assign \oper_i__is_32bit$42 \is_32bit
+ process $group_118
+ assign \oper_i__is_32bit$58 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ switch { \can_run }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+ switch \insn_type
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+ attribute \nmigen.decoding "OP_ATTN/5"
+ case 7'0000101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \nmigen.decoding "OP_NOP/1"
+ case 7'0000001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+ attribute \nmigen.decoding ""
+ case
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ switch { \fu_enable [7] }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ case 1'1
+ assign \oper_i__is_32bit$58 \is_32bit
+ end
+ end
end
sync init
end
- process $group_102
- assign \oper_i__is_signed$43 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- switch { \en_shiftrot0 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- case 1'1
- assign \oper_i__is_signed$43 \is_signed
+ process $group_119
+ assign \oper_i__is_signed$59 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ switch { \can_run }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+ switch \insn_type
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+ attribute \nmigen.decoding "OP_ATTN/5"
+ case 7'0000101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \nmigen.decoding "OP_NOP/1"
+ case 7'0000001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+ attribute \nmigen.decoding ""
+ case
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ switch { \fu_enable [7] }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ case 1'1
+ assign \oper_i__is_signed$59 \is_signed
+ end
+ end
end
sync init
end
- process $group_103
- assign \fus_oper_i__insn$161 32'00000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- switch { \en_shiftrot0 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- case 1'1
- assign \fus_oper_i__insn$161 \insn
+ process $group_120
+ assign \oper_i__insn$60 32'00000000000000000000000000000000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ switch { \can_run }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+ switch \insn_type
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+ attribute \nmigen.decoding "OP_ATTN/5"
+ case 7'0000101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \nmigen.decoding "OP_NOP/1"
+ case 7'0000001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+ attribute \nmigen.decoding ""
+ case
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ switch { \fu_enable [7] }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ case 1'1
+ assign \oper_i__insn$60 \insn
+ end
+ end
end
sync init
end
- process $group_104
- assign \issue_i$44 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- switch { \en_shiftrot0 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- case 1'1
- assign \issue_i$44 \issue_i
+ process $group_121
+ assign \issue_i$61 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ switch { \can_run }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+ switch \insn_type
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+ attribute \nmigen.decoding "OP_ATTN/5"
+ case 7'0000101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \nmigen.decoding "OP_NOP/1"
+ case 7'0000001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+ attribute \nmigen.decoding ""
+ case
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ switch { \fu_enable [7] }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ case 1'1
+ assign \issue_i$61 \issue_i
+ end
+ end
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:118"
- wire width 4 $289
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:75"
- wire width 1 $290
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:75"
- cell $eq $291
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:179"
+ wire width 4 $342
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83"
+ wire width 1 $343
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83"
+ cell $eq $344
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \input_carry
connect \B 2'10
- connect \Y $290
+ connect \Y $343
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83"
+ wire width 1 $345
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83"
+ cell $or $346
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A $343
+ connect \B \xer_in
+ connect \Y $345
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:118"
- cell $not $292
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:179"
+ cell $not $347
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \Y_WIDTH 4
- connect \A { $290 \reg3_ok \reg2_ok \reg1_ok }
- connect \Y $289
+ connect \A { $345 \reg3_ok \reg2_ok \reg1_ok }
+ connect \Y $342
end
- process $group_105
- assign \fus_rdmaskn$162 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- switch { \en_shiftrot0 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- case 1'1
- assign \fus_rdmaskn$162 $289
+ process $group_122
+ assign \fus_rdmaskn$186 4'0000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ switch { \can_run }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+ switch \insn_type
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+ attribute \nmigen.decoding "OP_ATTN/5"
+ case 7'0000101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \nmigen.decoding "OP_NOP/1"
+ case 7'0000001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+ attribute \nmigen.decoding ""
+ case
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ switch { \fu_enable [7] }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ case 1'1
+ assign \fus_rdmaskn$186 $342
+ end
+ end
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:112"
- wire width 1 $293
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:112"
- wire width 11 $294
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:112"
- cell $and $295
- parameter \A_SIGNED 0
- parameter \A_WIDTH 11
- parameter \B_SIGNED 0
- parameter \B_WIDTH 3
- parameter \Y_WIDTH 11
- connect \A \fn_unit
- connect \B 3'100
- connect \Y $294
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:112"
- cell $reduce_bool $296
- parameter \A_SIGNED 0
- parameter \A_WIDTH 11
- parameter \Y_WIDTH 1
- connect \A $294
- connect \Y $293
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:112"
- wire width 1 $297
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:112"
- cell $and $298
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \valid
- connect \B $293
- connect \Y $297
+ process $group_123
+ assign \oper_i__insn_type$63 7'0000000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ switch { \can_run }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+ switch \insn_type
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+ attribute \nmigen.decoding "OP_ATTN/5"
+ case 7'0000101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \nmigen.decoding "OP_NOP/1"
+ case 7'0000001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+ attribute \nmigen.decoding ""
+ case
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ switch { \fu_enable [8] }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ case 1'1
+ assign \oper_i__insn_type$63 \insn_type
+ end
+ end
+ end
+ sync init
end
- process $group_106
- assign \en_ldst0 1'0
- assign \en_ldst0 $297
+ process $group_124
+ assign \fus_oper_i__imm_data__imm$187 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \fus_oper_i__imm_data__imm_ok$188 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ switch { \can_run }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+ switch \insn_type
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+ attribute \nmigen.decoding "OP_ATTN/5"
+ case 7'0000101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \nmigen.decoding "OP_NOP/1"
+ case 7'0000001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+ attribute \nmigen.decoding ""
+ case
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ switch { \fu_enable [8] }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ case 1'1
+ assign { \fus_oper_i__imm_data__imm_ok$188 \fus_oper_i__imm_data__imm$187 } { \imm_ok \imm }
+ end
+ end
+ end
sync init
end
- process $group_107
- assign \oper_i__insn_type$46 7'0000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- switch { \en_ldst0 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- case 1'1
- assign \oper_i__insn_type$46 \insn_type
+ process $group_126
+ assign \oper_i__zero_a$64 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ switch { \can_run }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+ switch \insn_type
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+ attribute \nmigen.decoding "OP_ATTN/5"
+ case 7'0000101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \nmigen.decoding "OP_NOP/1"
+ case 7'0000001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+ attribute \nmigen.decoding ""
+ case
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ switch { \fu_enable [8] }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ case 1'1
+ assign \oper_i__zero_a$64 \zero_a
+ end
+ end
end
sync init
end
- process $group_108
- assign \fus_oper_i__imm_data__imm$163 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \fus_oper_i__imm_data__imm_ok$164 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- switch { \en_ldst0 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- case 1'1
- assign { \fus_oper_i__imm_data__imm_ok$164 \fus_oper_i__imm_data__imm$163 } { \imm_ok \imm }
+ process $group_127
+ assign \fus_oper_i__rc__rc$189 1'0
+ assign \fus_oper_i__rc__rc_ok$190 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ switch { \can_run }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+ switch \insn_type
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+ attribute \nmigen.decoding "OP_ATTN/5"
+ case 7'0000101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \nmigen.decoding "OP_NOP/1"
+ case 7'0000001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+ attribute \nmigen.decoding ""
+ case
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ switch { \fu_enable [8] }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ case 1'1
+ assign { \fus_oper_i__rc__rc_ok$190 \fus_oper_i__rc__rc$189 } { \rc_ok \rc }
+ end
+ end
end
sync init
end
- process $group_110
- assign \oper_i__zero_a 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- switch { \en_ldst0 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- case 1'1
- assign \oper_i__zero_a \zero_a
+ process $group_129
+ assign \fus_oper_i__oe__oe$191 1'0
+ assign \fus_oper_i__oe__oe_ok$192 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ switch { \can_run }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+ switch \insn_type
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+ attribute \nmigen.decoding "OP_ATTN/5"
+ case 7'0000101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \nmigen.decoding "OP_NOP/1"
+ case 7'0000001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+ attribute \nmigen.decoding ""
+ case
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ switch { \fu_enable [8] }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ case 1'1
+ assign { \fus_oper_i__oe__oe_ok$192 \fus_oper_i__oe__oe$191 } { \oe_ok \oe }
+ end
+ end
end
sync init
end
- process $group_111
- assign \oper_i__is_32bit$47 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- switch { \en_ldst0 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- case 1'1
- assign \oper_i__is_32bit$47 \is_32bit
+ process $group_131
+ assign \oper_i__is_32bit$65 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ switch { \can_run }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+ switch \insn_type
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+ attribute \nmigen.decoding "OP_ATTN/5"
+ case 7'0000101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \nmigen.decoding "OP_NOP/1"
+ case 7'0000001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+ attribute \nmigen.decoding ""
+ case
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ switch { \fu_enable [8] }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ case 1'1
+ assign \oper_i__is_32bit$65 \is_32bit
+ end
+ end
end
sync init
end
- process $group_112
- assign \oper_i__is_signed$48 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- switch { \en_ldst0 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- case 1'1
- assign \oper_i__is_signed$48 \is_signed
+ process $group_132
+ assign \oper_i__is_signed$66 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ switch { \can_run }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+ switch \insn_type
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+ attribute \nmigen.decoding "OP_ATTN/5"
+ case 7'0000101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \nmigen.decoding "OP_NOP/1"
+ case 7'0000001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+ attribute \nmigen.decoding ""
+ case
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ switch { \fu_enable [8] }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ case 1'1
+ assign \oper_i__is_signed$66 \is_signed
+ end
+ end
end
sync init
end
- process $group_113
- assign \oper_i__data_len$49 4'0000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- switch { \en_ldst0 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- case 1'1
- assign \oper_i__data_len$49 \data_len
+ process $group_133
+ assign \oper_i__data_len$67 4'0000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ switch { \can_run }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+ switch \insn_type
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+ attribute \nmigen.decoding "OP_ATTN/5"
+ case 7'0000101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \nmigen.decoding "OP_NOP/1"
+ case 7'0000001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+ attribute \nmigen.decoding ""
+ case
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ switch { \fu_enable [8] }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ case 1'1
+ assign \oper_i__data_len$67 \data_len
+ end
+ end
end
sync init
end
- process $group_114
- assign \oper_i__byte_reverse$50 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- switch { \en_ldst0 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- case 1'1
- assign \oper_i__byte_reverse$50 \byte_reverse
+ process $group_134
+ assign \oper_i__byte_reverse 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ switch { \can_run }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+ switch \insn_type
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+ attribute \nmigen.decoding "OP_ATTN/5"
+ case 7'0000101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \nmigen.decoding "OP_NOP/1"
+ case 7'0000001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+ attribute \nmigen.decoding ""
+ case
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ switch { \fu_enable [8] }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ case 1'1
+ assign \oper_i__byte_reverse \byte_reverse
+ end
+ end
end
sync init
end
- process $group_115
- assign \oper_i__sign_extend$51 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- switch { \en_ldst0 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- case 1'1
- assign \oper_i__sign_extend$51 \sign_extend
+ process $group_135
+ assign \oper_i__sign_extend 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ switch { \can_run }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+ switch \insn_type
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+ attribute \nmigen.decoding "OP_ATTN/5"
+ case 7'0000101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \nmigen.decoding "OP_NOP/1"
+ case 7'0000001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+ attribute \nmigen.decoding ""
+ case
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ switch { \fu_enable [8] }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ case 1'1
+ assign \oper_i__sign_extend \sign_extend
+ end
+ end
end
sync init
end
- process $group_116
- assign \oper_i__update 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- switch { \en_ldst0 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- case 1'1
- assign \oper_i__update \update
+ process $group_136
+ assign \oper_i__ldst_mode 2'00
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ switch { \can_run }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+ switch \insn_type
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+ attribute \nmigen.decoding "OP_ATTN/5"
+ case 7'0000101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \nmigen.decoding "OP_NOP/1"
+ case 7'0000001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+ attribute \nmigen.decoding ""
+ case
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ switch { \fu_enable [8] }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ case 1'1
+ assign \oper_i__ldst_mode \ldst_mode
+ end
+ end
end
sync init
end
- process $group_117
- assign \issue_i$52 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- switch { \en_ldst0 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- case 1'1
- assign \issue_i$52 \issue_i
+ process $group_137
+ assign \issue_i$68 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ switch { \can_run }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+ switch \insn_type
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+ attribute \nmigen.decoding "OP_ATTN/5"
+ case 7'0000101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \nmigen.decoding "OP_NOP/1"
+ case 7'0000001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+ attribute \nmigen.decoding ""
+ case
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ switch { \fu_enable [8] }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ case 1'1
+ assign \issue_i$68 \issue_i
+ end
+ end
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:118"
- wire width 3 $299
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:118"
- cell $not $300
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:179"
+ wire width 3 $348
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:179"
+ cell $not $349
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \Y_WIDTH 3
connect \A { \reg3_ok \reg2_ok \reg1_ok }
- connect \Y $299
+ connect \Y $348
end
- process $group_118
- assign \fus_rdmaskn$165 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- switch { \en_ldst0 }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:113"
- case 1'1
- assign \fus_rdmaskn$165 $299
+ process $group_138
+ assign \fus_rdmaskn$193 3'000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ switch { \can_run }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:157"
+ case 1'1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+ switch \insn_type
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:160"
+ attribute \nmigen.decoding "OP_ATTN/5"
+ case 7'0000101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \nmigen.decoding "OP_NOP/1"
+ case 7'0000001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:167"
+ attribute \nmigen.decoding ""
+ case
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ switch { \fu_enable [8] }
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
+ case 1'1
+ assign \fus_rdmaskn$193 $348
+ end
+ end
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
wire width 1 \rdflag_INT_ra
- process $group_119
+ process $group_139
assign \rdflag_INT_ra 1'0
assign \rdflag_INT_ra \reg1_ok
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:47"
- wire width 32 $301
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:47"
- cell $sshl $302
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:51"
+ wire width 32 $350
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:51"
+ cell $sshl $351
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 32
connect \A 1'1
connect \B \reg1
- connect \Y $301
+ connect \Y $350
end
- process $group_120
+ process $group_140
assign \int_src1__ren 32'00000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223"
switch { \rdpick_INT_ra_en_o }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223"
case 1'1
- assign \int_src1__ren $301
+ assign \int_src1__ren $350
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- wire width 1 $303
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- cell $and $304
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ wire width 1 $352
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ cell $and $353
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \rd__rel [0]
connect \B \fu_enable [0]
- connect \Y $303
+ connect \Y $352
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- wire width 1 $305
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- cell $and $306
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ wire width 1 $354
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ cell $and $355
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $303
+ connect \A $352
connect \B \rdflag_INT_ra
- connect \Y $305
+ connect \Y $354
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- wire width 1 $307
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- cell $and $308
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ wire width 1 $356
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ cell $and $357
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \rd__rel$54 [0]
+ connect \A \rd__rel$70 [0]
connect \B \fu_enable [1]
- connect \Y $307
+ connect \Y $356
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- wire width 1 $309
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- cell $and $310
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ wire width 1 $358
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ cell $and $359
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $307
+ connect \A $356
connect \B \rdflag_INT_ra
- connect \Y $309
+ connect \Y $358
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- wire width 1 $311
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- cell $and $312
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ wire width 1 $360
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ cell $and $361
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \rd__rel$57 [0]
+ connect \A \rd__rel$73 [0]
connect \B \fu_enable [3]
- connect \Y $311
+ connect \Y $360
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- wire width 1 $313
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- cell $and $314
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ wire width 1 $362
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ cell $and $363
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $311
+ connect \A $360
connect \B \rdflag_INT_ra
- connect \Y $313
+ connect \Y $362
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- wire width 1 $315
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- cell $and $316
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ wire width 1 $364
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ cell $and $365
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \rd__rel$60 [0]
+ connect \A \rd__rel$76 [0]
connect \B \fu_enable [4]
- connect \Y $315
+ connect \Y $364
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- wire width 1 $317
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- cell $and $318
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ wire width 1 $366
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ cell $and $367
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $315
+ connect \A $364
connect \B \rdflag_INT_ra
- connect \Y $317
+ connect \Y $366
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- wire width 1 $319
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- cell $and $320
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ wire width 1 $368
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ cell $and $369
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \rd__rel$63 [0]
+ connect \A \rd__rel$79 [0]
connect \B \fu_enable [5]
- connect \Y $319
+ connect \Y $368
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- wire width 1 $321
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- cell $and $322
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ wire width 1 $370
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ cell $and $371
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $319
+ connect \A $368
connect \B \rdflag_INT_ra
- connect \Y $321
+ connect \Y $370
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- wire width 1 $323
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- cell $and $324
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ wire width 1 $372
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ cell $and $373
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \rd__rel$66 [0]
+ connect \A \rd__rel$82 [0]
connect \B \fu_enable [6]
- connect \Y $323
+ connect \Y $372
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- wire width 1 $325
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- cell $and $326
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ wire width 1 $374
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ cell $and $375
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $323
+ connect \A $372
connect \B \rdflag_INT_ra
- connect \Y $325
+ connect \Y $374
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- wire width 1 $327
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- cell $and $328
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ wire width 1 $376
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ cell $and $377
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \rd__rel$69 [0]
+ connect \A \rd__rel$85 [0]
connect \B \fu_enable [7]
- connect \Y $327
+ connect \Y $376
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- wire width 1 $329
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- cell $and $330
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ wire width 1 $378
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ cell $and $379
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $327
+ connect \A $376
connect \B \rdflag_INT_ra
- connect \Y $329
+ connect \Y $378
end
- process $group_121
- assign \rdpick_INT_ra_i 7'0000000
- assign \rdpick_INT_ra_i [0] $305
- assign \rdpick_INT_ra_i [1] $309
- assign \rdpick_INT_ra_i [2] $313
- assign \rdpick_INT_ra_i [3] $317
- assign \rdpick_INT_ra_i [4] $321
- assign \rdpick_INT_ra_i [5] $325
- assign \rdpick_INT_ra_i [6] $329
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ wire width 1 $380
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ cell $and $381
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \rd__rel$88 [0]
+ connect \B \fu_enable [8]
+ connect \Y $380
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ wire width 1 $382
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ cell $and $383
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A $380
+ connect \B \rdflag_INT_ra
+ connect \Y $382
+ end
+ process $group_141
+ assign \rdpick_INT_ra_i 8'00000000
+ assign \rdpick_INT_ra_i [0] $354
+ assign \rdpick_INT_ra_i [1] $358
+ assign \rdpick_INT_ra_i [2] $362
+ assign \rdpick_INT_ra_i [3] $366
+ assign \rdpick_INT_ra_i [4] $370
+ assign \rdpick_INT_ra_i [5] $374
+ assign \rdpick_INT_ra_i [6] $378
+ assign \rdpick_INT_ra_i [7] $382
sync init
end
- process $group_122
+ process $group_142
assign \rd__go 4'0000
assign \rd__go [0] \rdpick_INT_ra_o [0]
assign \rd__go [1] \rdpick_INT_rb_o [0]
assign \rd__go [3] \rdpick_XER_xer_ca_o [0]
sync init
end
- process $group_123
+ process $group_143
assign \src1_i 64'0000000000000000000000000000000000000000000000000000000000000000
assign \src1_i \int_src1__data_o
sync init
end
- process $group_124
- assign \rd__go$55 6'000000
- assign \rd__go$55 [0] \rdpick_INT_ra_o [1]
- assign \rd__go$55 [1] \rdpick_INT_rb_o [1]
- assign \rd__go$55 [2] \rdpick_CR_full_cr_o
- assign \rd__go$55 [3] \rdpick_CR_cr_a_o [0]
- assign \rd__go$55 [4] \rdpick_CR_cr_b_o
- assign \rd__go$55 [5] \rdpick_CR_cr_c_o
+ process $group_144
+ assign \rd__go$71 6'000000
+ assign \rd__go$71 [0] \rdpick_INT_ra_o [1]
+ assign \rd__go$71 [1] \rdpick_INT_rb_o [1]
+ assign \rd__go$71 [2] \rdpick_CR_full_cr_o
+ assign \rd__go$71 [3] \rdpick_CR_cr_a_o [0]
+ assign \rd__go$71 [4] \rdpick_CR_cr_b_o
+ assign \rd__go$71 [5] \rdpick_CR_cr_c_o
sync init
end
- process $group_125
- assign \src1_i$56 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \src1_i$56 \int_src1__data_o
+ process $group_145
+ assign \src1_i$72 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \src1_i$72 \int_src1__data_o
sync init
end
- process $group_126
- assign \rd__go$58 6'000000
- assign \rd__go$58 [0] \rdpick_INT_ra_o [2]
- assign \rd__go$58 [1] \rdpick_INT_rb_o [2]
- assign \rd__go$58 [2] \rdpick_FAST_fast1_o [1]
- assign \rd__go$58 [3] \rdpick_FAST_fast2_o [1]
- assign \rd__go$58 [4] \rdpick_FAST_cia_o [1]
- assign \rd__go$58 [5] \rdpick_FAST_msr_o
+ process $group_146
+ assign \rd__go$74 4'0000
+ assign \rd__go$74 [0] \rdpick_INT_ra_o [2]
+ assign \rd__go$74 [1] \rdpick_INT_rb_o [2]
+ assign \rd__go$74 [2] \rdpick_FAST_fast1_o [1]
+ assign \rd__go$74 [3] \rdpick_FAST_fast2_o [1]
sync init
end
- process $group_127
- assign \src1_i$59 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \src1_i$59 \int_src1__data_o
+ process $group_147
+ assign \src1_i$75 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \src1_i$75 \int_src1__data_o
sync init
end
- process $group_128
- assign \rd__go$61 2'00
- assign \rd__go$61 [0] \rdpick_INT_ra_o [3]
- assign \rd__go$61 [1] \rdpick_INT_rb_o [3]
+ process $group_148
+ assign \rd__go$77 2'00
+ assign \rd__go$77 [0] \rdpick_INT_ra_o [3]
+ assign \rd__go$77 [1] \rdpick_INT_rb_o [3]
sync init
end
- process $group_129
- assign \src1_i$62 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \src1_i$62 \int_src1__data_o
+ process $group_149
+ assign \src1_i$78 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \src1_i$78 \int_src1__data_o
sync init
end
- process $group_130
- assign \rd__go$64 6'000000
- assign \rd__go$64 [0] \rdpick_INT_ra_o [4]
- assign \rd__go$64 [3] \rdpick_XER_xer_so_o [1]
- assign \rd__go$64 [5] \rdpick_XER_xer_ca_o [1]
- assign \rd__go$64 [4] \rdpick_XER_xer_ov_o
- assign \rd__go$64 [2] \rdpick_FAST_fast1_o [2]
- assign \rd__go$64 [1] \rdpick_SPR_spr1_o
+ process $group_150
+ assign \rd__go$80 6'000000
+ assign \rd__go$80 [0] \rdpick_INT_ra_o [4]
+ assign \rd__go$80 [3] \rdpick_XER_xer_so_o [1]
+ assign \rd__go$80 [5] \rdpick_XER_xer_ca_o [1]
+ assign \rd__go$80 [4] \rdpick_XER_xer_ov_o
+ assign \rd__go$80 [2] \rdpick_FAST_fast1_o [2]
+ assign \rd__go$80 [1] \rdpick_SPR_spr1_o
sync init
end
- process $group_131
- assign \src1_i$65 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \src1_i$65 \int_src1__data_o
+ process $group_151
+ assign \src1_i$81 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \src1_i$81 \int_src1__data_o
sync init
end
- process $group_132
- assign \rd__go$67 4'0000
- assign \rd__go$67 [0] \rdpick_INT_ra_o [5]
- assign \rd__go$67 [1] \rdpick_INT_rb_o [4]
- assign \rd__go$67 [2] \rdpick_INT_rc_o [0]
- assign \rd__go$67 [3] \rdpick_XER_xer_ca_o [2]
+ process $group_152
+ assign \rd__go$83 3'000
+ assign \rd__go$83 [0] \rdpick_INT_ra_o [5]
+ assign \rd__go$83 [1] \rdpick_INT_rb_o [4]
+ assign \rd__go$83 [2] \rdpick_XER_xer_so_o [2]
sync init
end
- process $group_133
- assign \src1_i$68 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \src1_i$68 \int_src1__data_o
+ process $group_153
+ assign \src1_i$84 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \src1_i$84 \int_src1__data_o
sync init
end
- process $group_134
- assign \rd__go$70 3'000
- assign \rd__go$70 [0] \rdpick_INT_ra_o [6]
- assign \rd__go$70 [1] \rdpick_INT_rb_o [5]
- assign \rd__go$70 [2] \rdpick_INT_rc_o [1]
+ process $group_154
+ assign \rd__go$86 4'0000
+ assign \rd__go$86 [0] \rdpick_INT_ra_o [6]
+ assign \rd__go$86 [1] \rdpick_INT_rb_o [5]
+ assign \rd__go$86 [2] \rdpick_INT_rc_o [0]
+ assign \rd__go$86 [3] \rdpick_XER_xer_ca_o [2]
sync init
end
- process $group_135
- assign \src1_i$71 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \src1_i$71 \int_src1__data_o
+ process $group_155
+ assign \src1_i$87 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \src1_i$87 \int_src1__data_o
+ sync init
+ end
+ process $group_156
+ assign \rd__go$89 3'000
+ assign \rd__go$89 [0] \rdpick_INT_ra_o [7]
+ assign \rd__go$89 [1] \rdpick_INT_rb_o [6]
+ assign \rd__go$89 [2] \rdpick_INT_rc_o [1]
+ sync init
+ end
+ process $group_157
+ assign \src1_i$90 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \src1_i$90 \int_src1__data_o
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
wire width 1 \rdflag_INT_rb
- process $group_136
+ process $group_158
assign \rdflag_INT_rb 1'0
assign \rdflag_INT_rb \reg2_ok
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:49"
- wire width 32 $331
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:49"
- cell $sshl $332
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:53"
+ wire width 32 $384
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:53"
+ cell $sshl $385
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 32
connect \A 1'1
connect \B \reg2
- connect \Y $331
+ connect \Y $384
end
- process $group_137
+ process $group_159
assign \int_src2__ren 32'00000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223"
switch { \rdpick_INT_rb_en_o }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223"
case 1'1
- assign \int_src2__ren $331
+ assign \int_src2__ren $384
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- wire width 1 $333
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- cell $and $334
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ wire width 1 $386
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ cell $and $387
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \rd__rel [1]
connect \B \fu_enable [0]
- connect \Y $333
+ connect \Y $386
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- wire width 1 $335
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- cell $and $336
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ wire width 1 $388
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ cell $and $389
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $333
+ connect \A $386
connect \B \rdflag_INT_rb
- connect \Y $335
+ connect \Y $388
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- wire width 1 $337
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- cell $and $338
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ wire width 1 $390
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ cell $and $391
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \rd__rel$54 [1]
+ connect \A \rd__rel$70 [1]
connect \B \fu_enable [1]
- connect \Y $337
+ connect \Y $390
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- wire width 1 $339
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- cell $and $340
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ wire width 1 $392
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ cell $and $393
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $337
+ connect \A $390
connect \B \rdflag_INT_rb
- connect \Y $339
+ connect \Y $392
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- wire width 1 $341
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- cell $and $342
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ wire width 1 $394
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ cell $and $395
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \rd__rel$57 [1]
+ connect \A \rd__rel$73 [1]
connect \B \fu_enable [3]
- connect \Y $341
+ connect \Y $394
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- wire width 1 $343
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- cell $and $344
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ wire width 1 $396
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ cell $and $397
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $341
+ connect \A $394
connect \B \rdflag_INT_rb
- connect \Y $343
+ connect \Y $396
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- wire width 1 $345
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- cell $and $346
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ wire width 1 $398
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ cell $and $399
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \rd__rel$60 [1]
+ connect \A \rd__rel$76 [1]
connect \B \fu_enable [4]
- connect \Y $345
+ connect \Y $398
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- wire width 1 $347
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- cell $and $348
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ wire width 1 $400
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ cell $and $401
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $345
+ connect \A $398
connect \B \rdflag_INT_rb
- connect \Y $347
+ connect \Y $400
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- wire width 1 $349
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- cell $and $350
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ wire width 1 $402
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ cell $and $403
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \rd__rel$66 [1]
+ connect \A \rd__rel$82 [1]
connect \B \fu_enable [6]
- connect \Y $349
+ connect \Y $402
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- wire width 1 $351
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- cell $and $352
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ wire width 1 $404
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ cell $and $405
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $349
+ connect \A $402
connect \B \rdflag_INT_rb
- connect \Y $351
+ connect \Y $404
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- wire width 1 $353
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- cell $and $354
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ wire width 1 $406
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ cell $and $407
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \rd__rel$69 [1]
+ connect \A \rd__rel$85 [1]
connect \B \fu_enable [7]
- connect \Y $353
+ connect \Y $406
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- wire width 1 $355
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- cell $and $356
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ wire width 1 $408
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ cell $and $409
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $353
+ connect \A $406
connect \B \rdflag_INT_rb
- connect \Y $355
+ connect \Y $408
end
- process $group_138
- assign \rdpick_INT_rb_i 6'000000
- assign \rdpick_INT_rb_i [0] $335
- assign \rdpick_INT_rb_i [1] $339
- assign \rdpick_INT_rb_i [2] $343
- assign \rdpick_INT_rb_i [3] $347
- assign \rdpick_INT_rb_i [4] $351
- assign \rdpick_INT_rb_i [5] $355
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ wire width 1 $410
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ cell $and $411
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \rd__rel$88 [1]
+ connect \B \fu_enable [8]
+ connect \Y $410
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ wire width 1 $412
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ cell $and $413
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A $410
+ connect \B \rdflag_INT_rb
+ connect \Y $412
+ end
+ process $group_160
+ assign \rdpick_INT_rb_i 7'0000000
+ assign \rdpick_INT_rb_i [0] $388
+ assign \rdpick_INT_rb_i [1] $392
+ assign \rdpick_INT_rb_i [2] $396
+ assign \rdpick_INT_rb_i [3] $400
+ assign \rdpick_INT_rb_i [4] $404
+ assign \rdpick_INT_rb_i [5] $408
+ assign \rdpick_INT_rb_i [6] $412
sync init
end
- process $group_139
+ process $group_161
assign \src2_i 64'0000000000000000000000000000000000000000000000000000000000000000
assign \src2_i \int_src2__data_o
sync init
end
- process $group_140
- assign \src2_i$72 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \src2_i$72 \int_src2__data_o
+ process $group_162
+ assign \src2_i$91 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \src2_i$91 \int_src2__data_o
sync init
end
- process $group_141
- assign \src2_i$73 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \src2_i$73 \int_src2__data_o
+ process $group_163
+ assign \src2_i$92 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \src2_i$92 \int_src2__data_o
sync init
end
- process $group_142
- assign \src2_i$74 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \src2_i$74 \int_src2__data_o
+ process $group_164
+ assign \src2_i$93 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \src2_i$93 \int_src2__data_o
sync init
end
- process $group_143
- assign \src2_i$75 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \src2_i$75 \int_src2__data_o
+ process $group_165
+ assign \src2_i$94 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \src2_i$94 \int_src2__data_o
sync init
end
- process $group_144
- assign \src2_i$76 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \src2_i$76 \int_src2__data_o
+ process $group_166
+ assign \src2_i$95 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \src2_i$95 \int_src2__data_o
+ sync init
+ end
+ process $group_167
+ assign \src2_i$96 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \src2_i$96 \int_src2__data_o
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
wire width 1 \rdflag_INT_rc
- process $group_145
+ process $group_168
assign \rdflag_INT_rc 1'0
assign \rdflag_INT_rc \reg3_ok
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:51"
- wire width 32 $357
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:51"
- cell $sshl $358
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:55"
+ wire width 32 $414
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:55"
+ cell $sshl $415
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 32
connect \A 1'1
connect \B \reg3
- connect \Y $357
+ connect \Y $414
end
- process $group_146
+ process $group_169
assign \int_src3__ren 32'00000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223"
switch { \rdpick_INT_rc_en_o }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223"
case 1'1
- assign \int_src3__ren $357
+ assign \int_src3__ren $414
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- wire width 1 $359
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- cell $and $360
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ wire width 1 $416
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ cell $and $417
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \rd__rel$66 [2]
- connect \B \fu_enable [6]
- connect \Y $359
+ connect \A \rd__rel$85 [2]
+ connect \B \fu_enable [7]
+ connect \Y $416
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- wire width 1 $361
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- cell $and $362
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ wire width 1 $418
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ cell $and $419
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $359
+ connect \A $416
connect \B \rdflag_INT_rc
- connect \Y $361
+ connect \Y $418
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- wire width 1 $363
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- cell $and $364
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ wire width 1 $420
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ cell $and $421
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \rd__rel$69 [2]
- connect \B \fu_enable [7]
- connect \Y $363
+ connect \A \rd__rel$88 [2]
+ connect \B \fu_enable [8]
+ connect \Y $420
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- wire width 1 $365
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- cell $and $366
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ wire width 1 $422
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ cell $and $423
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $363
+ connect \A $420
connect \B \rdflag_INT_rc
- connect \Y $365
+ connect \Y $422
end
- process $group_147
+ process $group_170
assign \rdpick_INT_rc_i 2'00
- assign \rdpick_INT_rc_i [0] $361
- assign \rdpick_INT_rc_i [1] $365
+ assign \rdpick_INT_rc_i [0] $418
+ assign \rdpick_INT_rc_i [1] $422
sync init
end
- process $group_148
+ process $group_171
assign \fus_src3_i 64'0000000000000000000000000000000000000000000000000000000000000000
assign \fus_src3_i \int_src3__data_o
sync init
end
- process $group_149
+ process $group_172
assign \src3_i 64'0000000000000000000000000000000000000000000000000000000000000000
assign \src3_i \int_src3__data_o
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
wire width 1 \rdflag_XER_xer_so
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:71"
- wire width 1 $367
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:71"
- cell $and $368
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79"
+ wire width 1 $424
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79"
+ cell $and $425
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \oe
connect \B \oe_ok
- connect \Y $367
+ connect \Y $424
end
- process $group_150
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79"
+ wire width 1 $426
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79"
+ cell $or $427
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A $424
+ connect \B \xer_in
+ connect \Y $426
+ end
+ process $group_173
assign \rdflag_XER_xer_so 1'0
- assign \rdflag_XER_xer_so $367
+ assign \rdflag_XER_xer_so $426
sync init
end
- process $group_151
+ process $group_174
assign \xer_src1__ren 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223"
switch { \rdpick_XER_xer_so_en_o }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223"
case 1'1
assign \xer_src1__ren 3'001
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- wire width 1 $369
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- cell $and $370
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ wire width 1 $428
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ cell $and $429
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \rd__rel [2]
connect \B \fu_enable [0]
- connect \Y $369
+ connect \Y $428
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- wire width 1 $371
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- cell $and $372
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ wire width 1 $430
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ cell $and $431
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $369
+ connect \A $428
connect \B \rdflag_XER_xer_so
- connect \Y $371
+ connect \Y $430
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- wire width 1 $373
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- cell $and $374
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ wire width 1 $432
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ cell $and $433
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \rd__rel$63 [3]
+ connect \A \rd__rel$79 [3]
connect \B \fu_enable [5]
- connect \Y $373
+ connect \Y $432
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- wire width 1 $375
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- cell $and $376
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ wire width 1 $434
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ cell $and $435
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $373
+ connect \A $432
connect \B \rdflag_XER_xer_so
- connect \Y $375
+ connect \Y $434
end
- process $group_152
- assign \rdpick_XER_xer_so_i 2'00
- assign \rdpick_XER_xer_so_i [0] $371
- assign \rdpick_XER_xer_so_i [1] $375
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ wire width 1 $436
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ cell $and $437
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \rd__rel$82 [2]
+ connect \B \fu_enable [6]
+ connect \Y $436
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ wire width 1 $438
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ cell $and $439
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A $436
+ connect \B \rdflag_XER_xer_so
+ connect \Y $438
+ end
+ process $group_175
+ assign \rdpick_XER_xer_so_i 3'000
+ assign \rdpick_XER_xer_so_i [0] $430
+ assign \rdpick_XER_xer_so_i [1] $434
+ assign \rdpick_XER_xer_so_i [2] $438
sync init
end
- process $group_153
- assign \fus_src3_i$166 1'0
- assign \fus_src3_i$166 \xer_src1__data_o [0]
+ process $group_176
+ assign \fus_src3_i$194 1'0
+ assign \fus_src3_i$194 \xer_src1__data_o [0]
sync init
end
- process $group_154
+ process $group_177
assign \fus_src4_i 1'0
assign \fus_src4_i \xer_src1__data_o [0]
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+ process $group_178
+ assign \fus_src3_i$195 1'0
+ assign \fus_src3_i$195 \xer_src1__data_o [0]
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
wire width 1 \rdflag_XER_xer_ca
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:75"
- wire width 1 $377
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:75"
- cell $eq $378
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83"
+ wire width 1 $440
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83"
+ cell $eq $441
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \input_carry
connect \B 2'10
- connect \Y $377
+ connect \Y $440
end
- process $group_155
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83"
+ wire width 1 $442
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83"
+ cell $or $443
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A $440
+ connect \B \xer_in
+ connect \Y $442
+ end
+ process $group_179
assign \rdflag_XER_xer_ca 1'0
- assign \rdflag_XER_xer_ca $377
+ assign \rdflag_XER_xer_ca $442
sync init
end
- process $group_156
+ process $group_180
assign \xer_src2__ren 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223"
switch { \rdpick_XER_xer_ca_en_o }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223"
case 1'1
assign \xer_src2__ren 3'010
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- wire width 1 $379
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- cell $and $380
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ wire width 1 $444
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ cell $and $445
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \rd__rel [3]
connect \B \fu_enable [0]
- connect \Y $379
+ connect \Y $444
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- wire width 1 $381
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- cell $and $382
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ wire width 1 $446
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ cell $and $447
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $379
+ connect \A $444
connect \B \rdflag_XER_xer_ca
- connect \Y $381
+ connect \Y $446
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- wire width 1 $383
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- cell $and $384
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ wire width 1 $448
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ cell $and $449
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \rd__rel$63 [5]
+ connect \A \rd__rel$79 [5]
connect \B \fu_enable [5]
- connect \Y $383
+ connect \Y $448
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- wire width 1 $385
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- cell $and $386
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ wire width 1 $450
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ cell $and $451
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $383
+ connect \A $448
connect \B \rdflag_XER_xer_ca
- connect \Y $385
+ connect \Y $450
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- wire width 1 $387
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- cell $and $388
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ wire width 1 $452
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ cell $and $453
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \rd__rel$66 [3]
- connect \B \fu_enable [6]
- connect \Y $387
+ connect \A \rd__rel$85 [3]
+ connect \B \fu_enable [7]
+ connect \Y $452
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- wire width 1 $389
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- cell $and $390
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ wire width 1 $454
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ cell $and $455
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $387
+ connect \A $452
connect \B \rdflag_XER_xer_ca
- connect \Y $389
+ connect \Y $454
end
- process $group_157
+ process $group_181
assign \rdpick_XER_xer_ca_i 3'000
- assign \rdpick_XER_xer_ca_i [0] $381
- assign \rdpick_XER_xer_ca_i [1] $385
- assign \rdpick_XER_xer_ca_i [2] $389
+ assign \rdpick_XER_xer_ca_i [0] $446
+ assign \rdpick_XER_xer_ca_i [1] $450
+ assign \rdpick_XER_xer_ca_i [2] $454
sync init
end
- process $group_158
- assign \fus_src4_i$167 2'00
- assign \fus_src4_i$167 \xer_src2__data_o
+ process $group_182
+ assign \fus_src4_i$196 2'00
+ assign \fus_src4_i$196 \xer_src2__data_o
sync init
end
- process $group_159
+ process $group_183
assign \fus_src6_i 2'00
assign \fus_src6_i \xer_src2__data_o
sync init
end
- process $group_160
- assign \fus_src4_i$168 2'00
- assign \fus_src4_i$168 \xer_src2__data_o
+ process $group_184
+ assign \fus_src4_i$197 2'00
+ assign \fus_src4_i$197 \xer_src2__data_o
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
wire width 1 \rdflag_XER_xer_ov
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:73"
- wire width 1 $391
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:73"
- cell $and $392
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81"
+ wire width 1 $456
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81"
+ cell $and $457
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \oe
connect \B \oe_ok
- connect \Y $391
+ connect \Y $456
end
- process $group_161
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81"
+ wire width 1 $458
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81"
+ cell $or $459
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A $456
+ connect \B \xer_in
+ connect \Y $458
+ end
+ process $group_185
assign \rdflag_XER_xer_ov 1'0
- assign \rdflag_XER_xer_ov $391
+ assign \rdflag_XER_xer_ov $458
sync init
end
- process $group_162
+ process $group_186
assign \xer_src3__ren 3'000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223"
switch { \rdpick_XER_xer_ov_en_o }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223"
case 1'1
assign \xer_src3__ren 3'100
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- wire width 1 $393
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- cell $and $394
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ wire width 1 $460
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ cell $and $461
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \rd__rel$63 [4]
+ connect \A \rd__rel$79 [4]
connect \B \fu_enable [5]
- connect \Y $393
+ connect \Y $460
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- wire width 1 $395
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- cell $and $396
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ wire width 1 $462
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ cell $and $463
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $393
+ connect \A $460
connect \B \rdflag_XER_xer_ov
- connect \Y $395
+ connect \Y $462
end
- process $group_163
+ process $group_187
assign \rdpick_XER_xer_ov_i 1'0
- assign \rdpick_XER_xer_ov_i $395
+ assign \rdpick_XER_xer_ov_i $462
sync init
end
- process $group_164
+ process $group_188
assign \fus_src5_i 2'00
assign \fus_src5_i \xer_src3__data_o
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
wire width 1 \rdflag_CR_full_cr
- process $group_165
+ process $group_189
assign \rdflag_CR_full_cr 1'0
assign \rdflag_CR_full_cr \read_cr_whole
sync init
end
- process $group_166
+ process $group_190
assign \cr_full_rd__ren 8'00000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223"
switch { \rdpick_CR_full_cr_en_o }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223"
case 1'1
assign \cr_full_rd__ren 8'11111111
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- wire width 1 $397
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- cell $and $398
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ wire width 1 $464
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ cell $and $465
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \rd__rel$54 [2]
+ connect \A \rd__rel$70 [2]
connect \B \fu_enable [1]
- connect \Y $397
+ connect \Y $464
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- wire width 1 $399
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- cell $and $400
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ wire width 1 $466
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ cell $and $467
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $397
+ connect \A $464
connect \B \rdflag_CR_full_cr
- connect \Y $399
+ connect \Y $466
end
- process $group_167
+ process $group_191
assign \rdpick_CR_full_cr_i 1'0
- assign \rdpick_CR_full_cr_i $399
+ assign \rdpick_CR_full_cr_i $466
sync init
end
- process $group_168
- assign \fus_src3_i$169 32'00000000000000000000000000000000
- assign \fus_src3_i$169 \cr_full_rd__data_o
+ process $group_192
+ assign \fus_src3_i$198 32'00000000000000000000000000000000
+ assign \fus_src3_i$198 \cr_full_rd__data_o
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
wire width 1 \rdflag_CR_cr_a
- process $group_169
+ process $group_193
assign \rdflag_CR_cr_a 1'0
assign \rdflag_CR_cr_a \cr_in1_ok
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:59"
- wire width 16 $401
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:59"
- wire width 4 $402
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:59"
- cell $sub $403
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:65"
+ wire width 16 $468
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:65"
+ wire width 4 $469
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:65"
+ cell $sub $470
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A 3'111
connect \B \cr_in1
- connect \Y $402
+ connect \Y $469
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:59"
- wire width 16 $404
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:59"
- cell $sshl $405
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:65"
+ wire width 16 $471
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:65"
+ cell $sshl $472
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 16
connect \A 1'1
- connect \B $402
- connect \Y $404
+ connect \B $469
+ connect \Y $471
end
- connect $401 $404
- process $group_170
+ connect $468 $471
+ process $group_194
assign \cr_src1__ren 8'00000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223"
switch { \rdpick_CR_cr_a_en_o }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223"
case 1'1
- assign \cr_src1__ren $401 [7:0]
+ assign \cr_src1__ren $468 [7:0]
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- wire width 1 $406
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- cell $and $407
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ wire width 1 $473
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ cell $and $474
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \rd__rel$54 [3]
+ connect \A \rd__rel$70 [3]
connect \B \fu_enable [1]
- connect \Y $406
+ connect \Y $473
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- wire width 1 $408
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- cell $and $409
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ wire width 1 $475
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ cell $and $476
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $406
+ connect \A $473
connect \B \rdflag_CR_cr_a
- connect \Y $408
+ connect \Y $475
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- wire width 1 $410
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- cell $and $411
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ wire width 1 $477
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ cell $and $478
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \rd__rel$77 [2]
+ connect \A \rd__rel$97 [2]
connect \B \fu_enable [2]
- connect \Y $410
+ connect \Y $477
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- wire width 1 $412
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- cell $and $413
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ wire width 1 $479
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ cell $and $480
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $410
+ connect \A $477
connect \B \rdflag_CR_cr_a
- connect \Y $412
+ connect \Y $479
end
- process $group_171
+ process $group_195
assign \rdpick_CR_cr_a_i 2'00
- assign \rdpick_CR_cr_a_i [0] $408
- assign \rdpick_CR_cr_a_i [1] $412
+ assign \rdpick_CR_cr_a_i [0] $475
+ assign \rdpick_CR_cr_a_i [1] $479
sync init
end
- process $group_172
- assign \fus_src4_i$170 4'0000
- assign \fus_src4_i$170 \cr_src1__data_o
+ process $group_196
+ assign \fus_src4_i$199 4'0000
+ assign \fus_src4_i$199 \cr_src1__data_o
sync init
end
- process $group_173
- assign \rd__go$78 4'0000
- assign \rd__go$78 [2] \rdpick_CR_cr_a_o [1]
- assign \rd__go$78 [0] \rdpick_FAST_fast1_o [0]
- assign \rd__go$78 [1] \rdpick_FAST_fast2_o [0]
- assign \rd__go$78 [3] \rdpick_FAST_cia_o [0]
+ process $group_197
+ assign \rd__go$98 3'000
+ assign \rd__go$98 [2] \rdpick_CR_cr_a_o [1]
+ assign \rd__go$98 [0] \rdpick_FAST_fast1_o [0]
+ assign \rd__go$98 [1] \rdpick_FAST_fast2_o [0]
sync init
end
- process $group_174
- assign \fus_src3_i$171 4'0000
- assign \fus_src3_i$171 \cr_src1__data_o
+ process $group_198
+ assign \fus_src3_i$200 4'0000
+ assign \fus_src3_i$200 \cr_src1__data_o
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
wire width 1 \rdflag_CR_cr_b
- process $group_175
+ process $group_199
assign \rdflag_CR_cr_b 1'0
assign \rdflag_CR_cr_b \cr_in2_ok
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:61"
- wire width 16 $414
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:61"
- wire width 4 $415
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:61"
- cell $sub $416
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:67"
+ wire width 16 $481
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:67"
+ wire width 4 $482
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:67"
+ cell $sub $483
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A 3'111
connect \B \cr_in2
- connect \Y $415
+ connect \Y $482
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:61"
- wire width 16 $417
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:61"
- cell $sshl $418
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:67"
+ wire width 16 $484
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:67"
+ cell $sshl $485
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 16
connect \A 1'1
- connect \B $415
- connect \Y $417
+ connect \B $482
+ connect \Y $484
end
- connect $414 $417
- process $group_176
+ connect $481 $484
+ process $group_200
assign \cr_src2__ren 8'00000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223"
switch { \rdpick_CR_cr_b_en_o }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223"
case 1'1
- assign \cr_src2__ren $414 [7:0]
+ assign \cr_src2__ren $481 [7:0]
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- wire width 1 $419
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- cell $and $420
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ wire width 1 $486
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ cell $and $487
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \rd__rel$54 [4]
+ connect \A \rd__rel$70 [4]
connect \B \fu_enable [1]
- connect \Y $419
+ connect \Y $486
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- wire width 1 $421
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- cell $and $422
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ wire width 1 $488
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ cell $and $489
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $419
+ connect \A $486
connect \B \rdflag_CR_cr_b
- connect \Y $421
+ connect \Y $488
end
- process $group_177
+ process $group_201
assign \rdpick_CR_cr_b_i 1'0
- assign \rdpick_CR_cr_b_i $421
+ assign \rdpick_CR_cr_b_i $488
sync init
end
- process $group_178
- assign \fus_src5_i$172 4'0000
- assign \fus_src5_i$172 \cr_src2__data_o
+ process $group_202
+ assign \fus_src5_i$201 4'0000
+ assign \fus_src5_i$201 \cr_src2__data_o
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
wire width 1 \rdflag_CR_cr_c
- process $group_179
+ process $group_203
assign \rdflag_CR_cr_c 1'0
- assign \rdflag_CR_cr_c \cr_in2_ok$5
+ assign \rdflag_CR_cr_c \cr_in2_ok$7
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:63"
- wire width 16 $423
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:63"
- wire width 4 $424
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:63"
- cell $sub $425
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:69"
+ wire width 16 $490
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:69"
+ wire width 4 $491
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:69"
+ cell $sub $492
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \B_WIDTH 3
parameter \Y_WIDTH 4
connect \A 3'111
- connect \B \cr_in2$79
- connect \Y $424
+ connect \B \cr_in2$99
+ connect \Y $491
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:63"
- wire width 16 $426
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:63"
- cell $sshl $427
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:69"
+ wire width 16 $493
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:69"
+ cell $sshl $494
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 16
connect \A 1'1
- connect \B $424
- connect \Y $426
+ connect \B $491
+ connect \Y $493
end
- connect $423 $426
- process $group_180
+ connect $490 $493
+ process $group_204
assign \cr_src3__ren 8'00000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223"
switch { \rdpick_CR_cr_c_en_o }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223"
case 1'1
- assign \cr_src3__ren $423 [7:0]
+ assign \cr_src3__ren $490 [7:0]
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- wire width 1 $428
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- cell $and $429
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ wire width 1 $495
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ cell $and $496
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \rd__rel$54 [5]
+ connect \A \rd__rel$70 [5]
connect \B \fu_enable [1]
- connect \Y $428
+ connect \Y $495
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- wire width 1 $430
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- cell $and $431
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ wire width 1 $497
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ cell $and $498
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $428
+ connect \A $495
connect \B \rdflag_CR_cr_c
- connect \Y $430
+ connect \Y $497
end
- process $group_181
+ process $group_205
assign \rdpick_CR_cr_c_i 1'0
- assign \rdpick_CR_cr_c_i $430
+ assign \rdpick_CR_cr_c_i $497
sync init
end
- process $group_182
- assign \fus_src6_i$173 4'0000
- assign \fus_src6_i$173 \cr_src3__data_o
+ process $group_206
+ assign \fus_src6_i$202 4'0000
+ assign \fus_src6_i$202 \cr_src3__data_o
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
wire width 1 \rdflag_FAST_fast1
- process $group_183
+ process $group_207
assign \rdflag_FAST_fast1 1'0
assign \rdflag_FAST_fast1 \fast1_ok
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:92"
- wire width 8 $432
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:92"
- cell $sshl $433
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:102"
+ wire width 8 $499
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:102"
+ cell $sshl $500
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 8
connect \A 1'1
connect \B \fast1
- connect \Y $432
+ connect \Y $499
end
- process $group_184
- assign \fast_src3__ren 8'00000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ process $group_208
+ assign \fast_src1__ren 8'00000000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223"
switch { \rdpick_FAST_fast1_en_o }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223"
case 1'1
- assign \fast_src3__ren $432
+ assign \fast_src1__ren $499
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- wire width 1 $434
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- cell $and $435
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ wire width 1 $501
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ cell $and $502
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \rd__rel$77 [0]
+ connect \A \rd__rel$97 [0]
connect \B \fu_enable [2]
- connect \Y $434
+ connect \Y $501
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- wire width 1 $436
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- cell $and $437
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ wire width 1 $503
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ cell $and $504
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $434
+ connect \A $501
connect \B \rdflag_FAST_fast1
- connect \Y $436
+ connect \Y $503
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- wire width 1 $438
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- cell $and $439
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ wire width 1 $505
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ cell $and $506
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \rd__rel$57 [2]
+ connect \A \rd__rel$73 [2]
connect \B \fu_enable [3]
- connect \Y $438
+ connect \Y $505
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- wire width 1 $440
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- cell $and $441
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ wire width 1 $507
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ cell $and $508
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $438
+ connect \A $505
connect \B \rdflag_FAST_fast1
- connect \Y $440
+ connect \Y $507
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- wire width 1 $442
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- cell $and $443
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ wire width 1 $509
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ cell $and $510
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \rd__rel$63 [2]
+ connect \A \rd__rel$79 [2]
connect \B \fu_enable [5]
- connect \Y $442
+ connect \Y $509
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- wire width 1 $444
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- cell $and $445
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ wire width 1 $511
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ cell $and $512
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $442
+ connect \A $509
connect \B \rdflag_FAST_fast1
- connect \Y $444
+ connect \Y $511
end
- process $group_185
+ process $group_209
assign \rdpick_FAST_fast1_i 3'000
- assign \rdpick_FAST_fast1_i [0] $436
- assign \rdpick_FAST_fast1_i [1] $440
- assign \rdpick_FAST_fast1_i [2] $444
+ assign \rdpick_FAST_fast1_i [0] $503
+ assign \rdpick_FAST_fast1_i [1] $507
+ assign \rdpick_FAST_fast1_i [2] $511
sync init
end
- process $group_186
- assign \src1_i$80 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \src1_i$80 \fast_src3__data_o
+ process $group_210
+ assign \src1_i$100 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \src1_i$100 \fast_src1__data_o
sync init
end
- process $group_187
- assign \fus_src3_i$174 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \fus_src3_i$174 \fast_src3__data_o
+ process $group_211
+ assign \fus_src3_i$203 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \fus_src3_i$203 \fast_src1__data_o
sync init
end
- process $group_188
- assign \fus_src3_i$175 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \fus_src3_i$175 \fast_src3__data_o
+ process $group_212
+ assign \fus_src3_i$204 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \fus_src3_i$204 \fast_src1__data_o
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
wire width 1 \rdflag_FAST_fast2
- process $group_189
+ process $group_213
assign \rdflag_FAST_fast2 1'0
assign \rdflag_FAST_fast2 \fast2_ok
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:94"
- wire width 8 $446
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:94"
- cell $sshl $447
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:104"
+ wire width 8 $513
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:104"
+ cell $sshl $514
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 8
connect \A 1'1
connect \B \fast2
- connect \Y $446
+ connect \Y $513
end
- process $group_190
- assign \fast_src4__ren 8'00000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ process $group_214
+ assign \fast_src2__ren 8'00000000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223"
switch { \rdpick_FAST_fast2_en_o }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223"
case 1'1
- assign \fast_src4__ren $446
+ assign \fast_src2__ren $513
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- wire width 1 $448
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- cell $and $449
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ wire width 1 $515
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ cell $and $516
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \rd__rel$77 [1]
+ connect \A \rd__rel$97 [1]
connect \B \fu_enable [2]
- connect \Y $448
+ connect \Y $515
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- wire width 1 $450
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- cell $and $451
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ wire width 1 $517
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ cell $and $518
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $448
+ connect \A $515
connect \B \rdflag_FAST_fast2
- connect \Y $450
+ connect \Y $517
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- wire width 1 $452
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- cell $and $453
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ wire width 1 $519
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ cell $and $520
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \rd__rel$57 [3]
+ connect \A \rd__rel$73 [3]
connect \B \fu_enable [3]
- connect \Y $452
+ connect \Y $519
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- wire width 1 $454
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- cell $and $455
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ wire width 1 $521
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ cell $and $522
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $452
+ connect \A $519
connect \B \rdflag_FAST_fast2
- connect \Y $454
+ connect \Y $521
end
- process $group_191
+ process $group_215
assign \rdpick_FAST_fast2_i 2'00
- assign \rdpick_FAST_fast2_i [0] $450
- assign \rdpick_FAST_fast2_i [1] $454
- sync init
- end
- process $group_192
- assign \src2_i$81 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \src2_i$81 \fast_src4__data_o
- sync init
- end
- process $group_193
- assign \fus_src4_i$176 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \fus_src4_i$176 \fast_src4__data_o
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
- wire width 1 \rdflag_FAST_cia
- wire width 1 $verilog_initial_trigger
- process $group_194
- assign \rdflag_FAST_cia 1'0
- assign \rdflag_FAST_cia 1'1
- assign $verilog_initial_trigger $verilog_initial_trigger
- sync init
- update $verilog_initial_trigger 1'0
- end
- process $group_195
- assign \fast_src1__ren 8'00000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
- switch { \rdpick_FAST_cia_en_o }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
- case 1'1
- assign \fast_src1__ren 8'00000001
- end
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- wire width 1 $456
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- cell $and $457
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \rd__rel$77 [3]
- connect \B \fu_enable [2]
- connect \Y $456
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- wire width 1 $458
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- cell $and $459
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A $456
- connect \B \rdflag_FAST_cia
- connect \Y $458
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- wire width 1 $460
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- cell $and $461
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \rd__rel$57 [4]
- connect \B \fu_enable [3]
- connect \Y $460
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- wire width 1 $462
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- cell $and $463
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A $460
- connect \B \rdflag_FAST_cia
- connect \Y $462
- end
- process $group_196
- assign \rdpick_FAST_cia_i 2'00
- assign \rdpick_FAST_cia_i [0] $458
- assign \rdpick_FAST_cia_i [1] $462
- sync init
- end
- process $group_197
- assign \fus_src4_i$177 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \fus_src4_i$177 \fast_src1__data_o
- sync init
- end
- process $group_198
- assign \fus_src5_i$178 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \fus_src5_i$178 \fast_src1__data_o
- sync init
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
- wire width 1 \rdflag_FAST_msr
- process $group_199
- assign \rdflag_FAST_msr 1'0
- assign \rdflag_FAST_msr 1'1
- assign $verilog_initial_trigger $verilog_initial_trigger
- sync init
- end
- process $group_200
- assign \fast_src2__ren 8'00000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
- switch { \rdpick_FAST_msr_en_o }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
- case 1'1
- assign \fast_src2__ren 8'00000010
- end
+ assign \rdpick_FAST_fast2_i [0] $517
+ assign \rdpick_FAST_fast2_i [1] $521
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- wire width 1 $464
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- cell $and $465
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A \rd__rel$57 [5]
- connect \B \fu_enable [3]
- connect \Y $464
- end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- wire width 1 $466
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- cell $and $467
- parameter \A_SIGNED 0
- parameter \A_WIDTH 1
- parameter \B_SIGNED 0
- parameter \B_WIDTH 1
- parameter \Y_WIDTH 1
- connect \A $464
- connect \B \rdflag_FAST_msr
- connect \Y $466
- end
- process $group_201
- assign \rdpick_FAST_msr_i 1'0
- assign \rdpick_FAST_msr_i $466
+ process $group_216
+ assign \src2_i$101 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \src2_i$101 \fast_src2__data_o
sync init
end
- process $group_202
- assign \fus_src6_i$179 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \fus_src6_i$179 \fast_src2__data_o
+ process $group_217
+ assign \fus_src4_i$205 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \fus_src4_i$205 \fast_src2__data_o
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:211"
wire width 1 \rdflag_SPR_spr1
- process $group_203
+ process $group_218
assign \rdflag_SPR_spr1 1'0
assign \rdflag_SPR_spr1 \spr1_ok
sync init
end
- process $group_204
+ process $group_219
assign \spr_src__ren 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223"
switch { \rdpick_SPR_spr1_en_o }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:163"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223"
case 1'1
assign \spr_src__ren \spr1 [0]
end
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- wire width 1 $468
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- cell $and $469
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ wire width 1 $523
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ cell $and $524
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \rd__rel$63 [1]
+ connect \A \rd__rel$79 [1]
connect \B \fu_enable [5]
- connect \Y $468
+ connect \Y $523
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- wire width 1 $470
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:173"
- cell $and $471
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ wire width 1 $525
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:233"
+ cell $and $526
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A $468
+ connect \A $523
connect \B \rdflag_SPR_spr1
- connect \Y $470
+ connect \Y $525
end
- process $group_205
+ process $group_220
assign \rdpick_SPR_spr1_i 1'0
- assign \rdpick_SPR_spr1_i $470
+ assign \rdpick_SPR_spr1_i $525
sync init
end
- process $group_206
- assign \src2_i$82 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \src2_i$82 \spr_src__data_o
+ process $group_221
+ assign \src2_i$102 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \src2_i$102 \spr_src__data_o
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:111"
- wire width 32 $472
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:111"
- cell $sshl $473
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:125"
+ wire width 32 $527
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:125"
+ cell $sshl $528
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 32
connect \A 1'1
connect \B \rego
- connect \Y $472
+ connect \Y $527
end
- process $group_207
- assign \int_wen$next \int_wen
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223"
+ process $group_222
+ assign \int_wen 32'00000000000000000000000000000000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283"
switch { \wrpick_INT_o_en_o }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283"
case 1'1
- assign \int_wen$next $472
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
+ assign \int_wen $527
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285"
case
- assign \int_wen$next 32'00000000000000000000000000000000
- end
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
- switch \rst
- case 1'1
- assign \int_wen$next 32'00000000000000000000000000000000
+ assign \int_wen 32'00000000000000000000000000000000
end
sync init
- update \int_wen 32'00000000000000000000000000000000
- sync posedge \clk
- update \int_wen \int_wen$next
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:235"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296"
wire width 1 \wrflag_alu0_o_0
- process $group_208
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+ wire width 1 $529
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+ cell $and $530
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \fus_o_ok
+ connect \B \busy_o
+ connect \Y $529
+ end
+ process $group_223
assign \wrflag_alu0_o_0 1'0
- assign \wrflag_alu0_o_0 \fus_o_ok
+ assign \wrflag_alu0_o_0 $529
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
- wire width 1 $474
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
- cell $and $475
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
+ wire width 1 $531
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
+ cell $and $532
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wr__rel [0]
connect \B \fu_enable [0]
- connect \Y $474
+ connect \Y $531
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
- wire width 1 $476
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
- cell $and $477
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
+ wire width 1 $533
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
+ cell $and $534
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr__rel$83 [0]
+ connect \A \wr__rel$103 [0]
connect \B \fu_enable [1]
- connect \Y $476
+ connect \Y $533
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
- wire width 1 $478
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
- cell $and $479
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
+ wire width 1 $535
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
+ cell $and $536
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr__rel$85 [0]
+ connect \A \wr__rel$105 [0]
connect \B \fu_enable [3]
- connect \Y $478
+ connect \Y $535
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
- wire width 1 $480
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
- cell $and $481
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
+ wire width 1 $537
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
+ cell $and $538
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr__rel$87 [0]
+ connect \A \wr__rel$107 [0]
connect \B \fu_enable [4]
- connect \Y $480
+ connect \Y $537
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
- wire width 1 $482
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
- cell $and $483
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
+ wire width 1 $539
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
+ cell $and $540
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr__rel$89 [0]
+ connect \A \wr__rel$109 [0]
connect \B \fu_enable [5]
- connect \Y $482
+ connect \Y $539
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
- wire width 1 $484
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
- cell $and $485
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
+ wire width 1 $541
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
+ cell $and $542
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr__rel$91 [0]
+ connect \A \wr__rel$111 [0]
connect \B \fu_enable [6]
- connect \Y $484
+ connect \Y $541
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
- wire width 1 $486
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
- cell $and $487
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
+ wire width 1 $543
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
+ cell $and $544
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr__rel$93 [0]
+ connect \A \wr__rel$113 [0]
connect \B \fu_enable [7]
- connect \Y $486
+ connect \Y $543
end
- process $group_209
- assign \wrpick_INT_o_i 7'0000000
- assign \wrpick_INT_o_i [0] $474
- assign \wrpick_INT_o_i [1] $476
- assign \wrpick_INT_o_i [2] $478
- assign \wrpick_INT_o_i [3] $480
- assign \wrpick_INT_o_i [4] $482
- assign \wrpick_INT_o_i [5] $484
- assign \wrpick_INT_o_i [6] $486
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
+ wire width 1 $545
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
+ cell $and $546
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \wr__rel$115 [0]
+ connect \B \fu_enable [8]
+ connect \Y $545
+ end
+ process $group_224
+ assign \wrpick_INT_o_i 8'00000000
+ assign \wrpick_INT_o_i [0] $531
+ assign \wrpick_INT_o_i [1] $533
+ assign \wrpick_INT_o_i [2] $535
+ assign \wrpick_INT_o_i [3] $537
+ assign \wrpick_INT_o_i [4] $539
+ assign \wrpick_INT_o_i [5] $541
+ assign \wrpick_INT_o_i [6] $543
+ assign \wrpick_INT_o_i [7] $545
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:242"
- wire width 1 $488
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:242"
- cell $and $489
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+ wire width 1 $547
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+ cell $and $548
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wrpick_INT_o_o [0]
connect \B \wrpick_INT_o_en_o
- connect \Y $488
+ connect \Y $547
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:242"
- wire width 1 $490
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:242"
- cell $and $491
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+ wire width 1 $549
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+ cell $and $550
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wrpick_CR_cr_a_o [0]
connect \B \wrpick_CR_cr_a_en_o
- connect \Y $490
+ connect \Y $549
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:242"
- wire width 1 $492
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:242"
- cell $and $493
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+ wire width 1 $551
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+ cell $and $552
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wrpick_XER_xer_ca_o [0]
connect \B \wrpick_XER_xer_ca_en_o
- connect \Y $492
+ connect \Y $551
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:242"
- wire width 1 $494
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:242"
- cell $and $495
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+ wire width 1 $553
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+ cell $and $554
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wrpick_XER_xer_ov_o [0]
connect \B \wrpick_XER_xer_ov_en_o
- connect \Y $494
+ connect \Y $553
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:242"
- wire width 1 $496
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:242"
- cell $and $497
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+ wire width 1 $555
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+ cell $and $556
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wrpick_XER_xer_so_o [0]
connect \B \wrpick_XER_xer_so_en_o
- connect \Y $496
+ connect \Y $555
end
- process $group_210
- assign \wr__go$next \wr__go
- assign \wr__go$next [0] $488
- assign \wr__go$next [1] $490
- assign \wr__go$next [2] $492
- assign \wr__go$next [3] $494
- assign \wr__go$next [4] $496
- sync init
- update \wr__go 5'00000
- sync posedge \clk
- update \wr__go \wr__go$next
+ process $group_225
+ assign \wr__go 5'00000
+ assign \wr__go [0] $547
+ assign \wr__go [1] $549
+ assign \wr__go [2] $551
+ assign \wr__go [3] $553
+ assign \wr__go [4] $555
+ sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:235"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296"
wire width 1 \wrflag_cr0_o_0
- process $group_211
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+ wire width 1 $557
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+ cell $and $558
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \fus_o_ok$206
+ connect \B \busy_o$6
+ connect \Y $557
+ end
+ process $group_226
assign \wrflag_cr0_o_0 1'0
- assign \wrflag_cr0_o_0 \fus_o_ok$180
+ assign \wrflag_cr0_o_0 $557
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:242"
- wire width 1 $498
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:242"
- cell $and $499
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+ wire width 1 $559
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+ cell $and $560
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wrpick_INT_o_o [1]
connect \B \wrpick_INT_o_en_o
- connect \Y $498
+ connect \Y $559
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:242"
- wire width 1 $500
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:242"
- cell $and $501
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+ wire width 1 $561
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+ cell $and $562
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wrpick_CR_full_cr_o
connect \B \wrpick_CR_full_cr_en_o
- connect \Y $500
+ connect \Y $561
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:242"
- wire width 1 $502
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:242"
- cell $and $503
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+ wire width 1 $563
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+ cell $and $564
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wrpick_CR_cr_a_o [1]
connect \B \wrpick_CR_cr_a_en_o
- connect \Y $502
+ connect \Y $563
end
- process $group_212
- assign \wr__go$84$next \wr__go$84
- assign \wr__go$84$next [0] $498
- assign \wr__go$84$next [1] $500
- assign \wr__go$84$next [2] $502
+ process $group_227
+ assign \wr__go$104 3'000
+ assign \wr__go$104 [0] $559
+ assign \wr__go$104 [1] $561
+ assign \wr__go$104 [2] $563
sync init
- update \wr__go$84 3'000
- sync posedge \clk
- update \wr__go$84 \wr__go$84$next
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:235"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296"
wire width 1 \wrflag_trap0_o_0
- process $group_213
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+ wire width 1 $565
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+ cell $and $566
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \fus_o_ok$207
+ connect \B \busy_o$22
+ connect \Y $565
+ end
+ process $group_228
assign \wrflag_trap0_o_0 1'0
- assign \wrflag_trap0_o_0 \fus_o_ok$181
+ assign \wrflag_trap0_o_0 $565
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:242"
- wire width 1 $504
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:242"
- cell $and $505
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+ wire width 1 $567
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+ cell $and $568
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wrpick_INT_o_o [2]
connect \B \wrpick_INT_o_en_o
- connect \Y $504
+ connect \Y $567
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:242"
- wire width 1 $506
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:242"
- cell $and $507
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+ wire width 1 $569
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+ cell $and $570
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wrpick_FAST_fast1_o [1]
connect \B \wrpick_FAST_fast1_en_o
- connect \Y $506
+ connect \Y $569
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:242"
- wire width 1 $508
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:242"
- cell $and $509
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+ wire width 1 $571
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+ cell $and $572
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wrpick_FAST_fast2_o [1]
connect \B \wrpick_FAST_fast2_en_o
- connect \Y $508
+ connect \Y $571
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:242"
- wire width 1 $510
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:242"
- cell $and $511
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+ wire width 1 $573
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+ cell $and $574
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wrpick_FAST_nia_o [1]
connect \B \wrpick_FAST_nia_en_o
- connect \Y $510
+ connect \Y $573
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:242"
- wire width 1 $512
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:242"
- cell $and $513
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+ wire width 1 $575
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+ cell $and $576
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wrpick_FAST_msr_o
connect \B \wrpick_FAST_msr_en_o
- connect \Y $512
+ connect \Y $575
end
- process $group_214
- assign \wr__go$86$next \wr__go$86
- assign \wr__go$86$next [0] $504
- assign \wr__go$86$next [1] $506
- assign \wr__go$86$next [2] $508
- assign \wr__go$86$next [3] $510
- assign \wr__go$86$next [4] $512
- sync init
- update \wr__go$86 5'00000
- sync posedge \clk
- update \wr__go$86 \wr__go$86$next
+ process $group_229
+ assign \wr__go$106 5'00000
+ assign \wr__go$106 [0] $567
+ assign \wr__go$106 [1] $569
+ assign \wr__go$106 [2] $571
+ assign \wr__go$106 [3] $573
+ assign \wr__go$106 [4] $575
+ sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:235"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296"
wire width 1 \wrflag_logical0_o_0
- process $group_215
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+ wire width 1 $577
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+ cell $and $578
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \fus_o_ok$208
+ connect \B \busy_o$36
+ connect \Y $577
+ end
+ process $group_230
assign \wrflag_logical0_o_0 1'0
- assign \wrflag_logical0_o_0 \fus_o_ok$182
+ assign \wrflag_logical0_o_0 $577
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:242"
- wire width 1 $514
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:242"
- cell $and $515
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+ wire width 1 $579
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+ cell $and $580
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wrpick_INT_o_o [3]
connect \B \wrpick_INT_o_en_o
- connect \Y $514
+ connect \Y $579
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:242"
- wire width 1 $516
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:242"
- cell $and $517
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+ wire width 1 $581
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+ cell $and $582
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wrpick_CR_cr_a_o [2]
connect \B \wrpick_CR_cr_a_en_o
- connect \Y $516
+ connect \Y $581
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:242"
- wire width 1 $518
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:242"
- cell $and $519
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+ wire width 1 $583
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+ cell $and $584
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wrpick_XER_xer_ca_o [1]
connect \B \wrpick_XER_xer_ca_en_o
- connect \Y $518
+ connect \Y $583
end
- process $group_216
- assign \wr__go$88$next \wr__go$88
- assign \wr__go$88$next [0] $514
- assign \wr__go$88$next [1] $516
- assign \wr__go$88$next [2] $518
+ process $group_231
+ assign \wr__go$108 3'000
+ assign \wr__go$108 [0] $579
+ assign \wr__go$108 [1] $581
+ assign \wr__go$108 [2] $583
sync init
- update \wr__go$88 3'000
- sync posedge \clk
- update \wr__go$88 \wr__go$88$next
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:235"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296"
wire width 1 \wrflag_spr0_o_0
- process $group_217
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+ wire width 1 $585
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+ cell $and $586
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \fus_o_ok$209
+ connect \B \busy_o$42
+ connect \Y $585
+ end
+ process $group_232
assign \wrflag_spr0_o_0 1'0
- assign \wrflag_spr0_o_0 \fus_o_ok$183
+ assign \wrflag_spr0_o_0 $585
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:242"
- wire width 1 $520
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:242"
- cell $and $521
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+ wire width 1 $587
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+ cell $and $588
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wrpick_INT_o_o [4]
connect \B \wrpick_INT_o_en_o
- connect \Y $520
+ connect \Y $587
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:242"
- wire width 1 $522
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:242"
- cell $and $523
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+ wire width 1 $589
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+ cell $and $590
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wrpick_XER_xer_ca_o [2]
connect \B \wrpick_XER_xer_ca_en_o
- connect \Y $522
+ connect \Y $589
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:242"
- wire width 1 $524
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:242"
- cell $and $525
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+ wire width 1 $591
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+ cell $and $592
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wrpick_XER_xer_ov_o [1]
connect \B \wrpick_XER_xer_ov_en_o
- connect \Y $524
+ connect \Y $591
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:242"
- wire width 1 $526
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:242"
- cell $and $527
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+ wire width 1 $593
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+ cell $and $594
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wrpick_XER_xer_so_o [1]
connect \B \wrpick_XER_xer_so_en_o
- connect \Y $526
+ connect \Y $593
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:242"
- wire width 1 $528
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:242"
- cell $and $529
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+ wire width 1 $595
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+ cell $and $596
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wrpick_FAST_fast1_o [2]
connect \B \wrpick_FAST_fast1_en_o
- connect \Y $528
+ connect \Y $595
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:242"
- wire width 1 $530
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:242"
- cell $and $531
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+ wire width 1 $597
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+ cell $and $598
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wrpick_SPR_spr1_o
connect \B \wrpick_SPR_spr1_en_o
- connect \Y $530
+ connect \Y $597
end
- process $group_218
- assign \wr__go$90$next \wr__go$90
- assign \wr__go$90$next [0] $520
- assign \wr__go$90$next [5] $522
- assign \wr__go$90$next [4] $524
- assign \wr__go$90$next [3] $526
- assign \wr__go$90$next [2] $528
- assign \wr__go$90$next [1] $530
- sync init
- update \wr__go$90 6'000000
- sync posedge \clk
- update \wr__go$90 \wr__go$90$next
+ process $group_233
+ assign \wr__go$110 6'000000
+ assign \wr__go$110 [0] $587
+ assign \wr__go$110 [5] $589
+ assign \wr__go$110 [4] $591
+ assign \wr__go$110 [3] $593
+ assign \wr__go$110 [2] $595
+ assign \wr__go$110 [1] $597
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296"
+ wire width 1 \wrflag_mul0_o_0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+ wire width 1 $599
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+ cell $and $600
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \fus_o_ok$210
+ connect \B \busy_o$53
+ connect \Y $599
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:235"
- wire width 1 \wrflag_shiftrot0_o_0
- process $group_219
- assign \wrflag_shiftrot0_o_0 1'0
- assign \wrflag_shiftrot0_o_0 \fus_o_ok$184
+ process $group_234
+ assign \wrflag_mul0_o_0 1'0
+ assign \wrflag_mul0_o_0 $599
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:242"
- wire width 1 $532
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:242"
- cell $and $533
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+ wire width 1 $601
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+ cell $and $602
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wrpick_INT_o_o [5]
connect \B \wrpick_INT_o_en_o
- connect \Y $532
+ connect \Y $601
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:242"
- wire width 1 $534
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:242"
- cell $and $535
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+ wire width 1 $603
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+ cell $and $604
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wrpick_CR_cr_a_o [3]
connect \B \wrpick_CR_cr_a_en_o
- connect \Y $534
+ connect \Y $603
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+ wire width 1 $605
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+ cell $and $606
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \wrpick_XER_xer_ov_o [2]
+ connect \B \wrpick_XER_xer_ov_en_o
+ connect \Y $605
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+ wire width 1 $607
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+ cell $and $608
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \wrpick_XER_xer_so_o [2]
+ connect \B \wrpick_XER_xer_so_en_o
+ connect \Y $607
+ end
+ process $group_235
+ assign \wr__go$112 4'0000
+ assign \wr__go$112 [0] $601
+ assign \wr__go$112 [1] $603
+ assign \wr__go$112 [2] $605
+ assign \wr__go$112 [3] $607
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296"
+ wire width 1 \wrflag_shiftrot0_o_0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+ wire width 1 $609
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+ cell $and $610
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \fus_o_ok$211
+ connect \B \busy_o$62
+ connect \Y $609
+ end
+ process $group_236
+ assign \wrflag_shiftrot0_o_0 1'0
+ assign \wrflag_shiftrot0_o_0 $609
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+ wire width 1 $611
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+ cell $and $612
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \wrpick_INT_o_o [6]
+ connect \B \wrpick_INT_o_en_o
+ connect \Y $611
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+ wire width 1 $613
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+ cell $and $614
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \wrpick_CR_cr_a_o [4]
+ connect \B \wrpick_CR_cr_a_en_o
+ connect \Y $613
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:242"
- wire width 1 $536
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:242"
- cell $and $537
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+ wire width 1 $615
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+ cell $and $616
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wrpick_XER_xer_ca_o [3]
connect \B \wrpick_XER_xer_ca_en_o
- connect \Y $536
+ connect \Y $615
end
- process $group_220
- assign \wr__go$92$next \wr__go$92
- assign \wr__go$92$next [0] $532
- assign \wr__go$92$next [1] $534
- assign \wr__go$92$next [2] $536
+ process $group_237
+ assign \wr__go$114 3'000
+ assign \wr__go$114 [0] $611
+ assign \wr__go$114 [1] $613
+ assign \wr__go$114 [2] $615
sync init
- update \wr__go$92 3'000
- sync posedge \clk
- update \wr__go$92 \wr__go$92$next
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:235"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296"
wire width 1 \wrflag_ldst0_o_0
- process $group_221
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+ wire width 1 $617
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+ cell $and $618
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \o_ok
+ connect \B \busy_o$69
+ connect \Y $617
+ end
+ process $group_238
assign \wrflag_ldst0_o_0 1'0
- assign \wrflag_ldst0_o_0 \o_ok
+ assign \wrflag_ldst0_o_0 $617
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:242"
- wire width 1 $538
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:242"
- cell $and $539
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+ wire width 1 $619
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+ cell $and $620
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wrpick_INT_o_o [6]
+ connect \A \wrpick_INT_o_o [7]
connect \B \wrpick_INT_o_en_o
- connect \Y $538
+ connect \Y $619
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:242"
- wire width 1 $540
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:242"
- cell $and $541
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+ wire width 1 $621
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+ cell $and $622
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wrpick_INT_o1_o
connect \B \wrpick_INT_o1_en_o
- connect \Y $540
+ connect \Y $621
end
- process $group_222
- assign \wr__go$94$next \wr__go$94
- assign \wr__go$94$next [0] $538
- assign \wr__go$94$next [1] $540
+ process $group_239
+ assign \wr__go$116 2'00
+ assign \wr__go$116 [0] $619
+ assign \wr__go$116 [1] $621
sync init
- update \wr__go$94 2'00
- sync posedge \clk
- update \wr__go$94 \wr__go$94$next
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
- wire width 64 $542
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
- cell $or $543
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+ wire width 65 $623
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+ wire width 64 $624
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+ cell $or $625
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \B_WIDTH 64
parameter \Y_WIDTH 64
- connect \A \fus_o$185
- connect \B \fus_o$186
- connect \Y $542
+ connect \A \dest1_o
+ connect \B \dest1_o$117
+ connect \Y $624
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
- wire width 64 $544
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
- cell $or $545
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+ wire width 64 $626
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+ cell $or $627
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \B_WIDTH 64
parameter \Y_WIDTH 64
- connect \A \fus_o
- connect \B $542
- connect \Y $544
+ connect \A \dest1_o$118
+ connect \B \dest1_o$119
+ connect \Y $626
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
- wire width 64 $546
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
- cell $or $547
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+ wire width 64 $628
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+ cell $or $629
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \B_WIDTH 64
parameter \Y_WIDTH 64
- connect \A \fus_o$187
- connect \B \fus_o$188
- connect \Y $546
+ connect \A $624
+ connect \B $626
+ connect \Y $628
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
- wire width 64 $548
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
- cell $or $549
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+ wire width 64 $630
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+ cell $or $631
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \B_WIDTH 64
parameter \Y_WIDTH 64
- connect \A \fus_o$189
- connect \B \o
- connect \Y $548
+ connect \A \dest1_o$120
+ connect \B \dest1_o$121
+ connect \Y $630
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
- wire width 64 $550
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
- cell $or $551
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+ wire width 65 $632
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+ cell $or $633
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
- parameter \B_WIDTH 64
- parameter \Y_WIDTH 64
- connect \A $546
- connect \B $548
- connect \Y $550
+ parameter \B_WIDTH 65
+ parameter \Y_WIDTH 65
+ connect \A \dest1_o$122
+ connect \B { \o_ok \o }
+ connect \Y $632
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
- wire width 64 $552
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
- cell $or $553
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+ wire width 65 $634
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+ cell $or $635
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
- parameter \B_WIDTH 64
- parameter \Y_WIDTH 64
- connect \A $544
- connect \B $550
- connect \Y $552
+ parameter \B_WIDTH 65
+ parameter \Y_WIDTH 65
+ connect \A $630
+ connect \B $632
+ connect \Y $634
end
- process $group_223
- assign \int_data_i$next \int_data_i
- assign \int_data_i$next $552
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
- switch \rst
- case 1'1
- assign \int_data_i$next 64'0000000000000000000000000000000000000000000000000000000000000000
- end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+ wire width 65 $636
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+ cell $or $637
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 64
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 65
+ parameter \Y_WIDTH 65
+ connect \A $628
+ connect \B $634
+ connect \Y $636
+ end
+ connect $623 $636
+ process $group_240
+ assign \int_data_i 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \int_data_i $623 [63:0]
sync init
- update \int_data_i 64'0000000000000000000000000000000000000000000000000000000000000000
- sync posedge \clk
- update \int_data_i \int_data_i$next
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:113"
- wire width 32 $554
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:113"
- cell $sshl $555
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:127"
+ wire width 32 $638
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:127"
+ cell $sshl $639
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 32
connect \A 1'1
connect \B \ea
- connect \Y $554
+ connect \Y $638
end
- process $group_224
- assign \int_wen$214$next \int_wen$214
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223"
+ process $group_241
+ assign \int_wen$246 32'00000000000000000000000000000000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283"
switch { \wrpick_INT_o1_en_o }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283"
case 1'1
- assign \int_wen$214$next $554
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
+ assign \int_wen$246 $638
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285"
case
- assign \int_wen$214$next 32'00000000000000000000000000000000
- end
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
- switch \rst
- case 1'1
- assign \int_wen$214$next 32'00000000000000000000000000000000
+ assign \int_wen$246 32'00000000000000000000000000000000
end
sync init
- update \int_wen$214 32'00000000000000000000000000000000
- sync posedge \clk
- update \int_wen$214 \int_wen$214$next
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:235"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296"
wire width 1 \wrflag_ldst0_o1_1
- process $group_225
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+ wire width 1 $640
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+ cell $and $641
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \ea_ok
+ connect \B \busy_o$69
+ connect \Y $640
+ end
+ process $group_242
assign \wrflag_ldst0_o1_1 1'0
- assign \wrflag_ldst0_o1_1 \ea_ok
+ assign \wrflag_ldst0_o1_1 $640
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
- wire width 1 $556
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
- cell $and $557
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
+ wire width 1 $642
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
+ cell $and $643
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr__rel$93 [1]
- connect \B \fu_enable [7]
- connect \Y $556
+ connect \A \wr__rel$115 [1]
+ connect \B \fu_enable [8]
+ connect \Y $642
end
- process $group_226
+ process $group_243
assign \wrpick_INT_o1_i 1'0
- assign \wrpick_INT_o1_i $556
+ assign \wrpick_INT_o1_i $642
sync init
end
- process $group_227
- assign \int_data_i$215$next \int_data_i$215
- assign \int_data_i$215$next \ea$95
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
- switch \rst
- case 1'1
- assign \int_data_i$215$next 64'0000000000000000000000000000000000000000000000000000000000000000
- end
+ process $group_244
+ assign \int_data_i$247 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \int_data_i$247 { \ea_ok \ea$123 } [63:0]
sync init
- update \int_data_i$215 64'0000000000000000000000000000000000000000000000000000000000000000
- sync posedge \clk
- update \int_data_i$215 \int_data_i$215$next
- end
- process $group_228
- assign \cr_full_wr__wen$next \cr_full_wr__wen
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223"
+ end
+ process $group_245
+ assign \cr_full_wr__wen 8'00000000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283"
switch { \wrpick_CR_full_cr_en_o }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283"
case 1'1
- assign \cr_full_wr__wen$next 8'11111111
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
+ assign \cr_full_wr__wen 8'11111111
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285"
case
- assign \cr_full_wr__wen$next 8'00000000
- end
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
- switch \rst
- case 1'1
- assign \cr_full_wr__wen$next 8'00000000
+ assign \cr_full_wr__wen 8'00000000
end
sync init
- update \cr_full_wr__wen 8'00000000
- sync posedge \clk
- update \cr_full_wr__wen \cr_full_wr__wen$next
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:235"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296"
wire width 1 \wrflag_cr0_full_cr_1
- process $group_229
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+ wire width 1 $644
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+ cell $and $645
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \fus_full_cr_ok
+ connect \B \busy_o$6
+ connect \Y $644
+ end
+ process $group_246
assign \wrflag_cr0_full_cr_1 1'0
- assign \wrflag_cr0_full_cr_1 \fus_full_cr_ok
+ assign \wrflag_cr0_full_cr_1 $644
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
- wire width 1 $558
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
- cell $and $559
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
+ wire width 1 $646
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
+ cell $and $647
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr__rel$83 [1]
+ connect \A \wr__rel$103 [1]
connect \B \fu_enable [1]
- connect \Y $558
+ connect \Y $646
end
- process $group_230
+ process $group_247
assign \wrpick_CR_full_cr_i 1'0
- assign \wrpick_CR_full_cr_i $558
+ assign \wrpick_CR_full_cr_i $646
sync init
end
- process $group_231
- assign \cr_full_wr__data_i$next \cr_full_wr__data_i
- assign \cr_full_wr__data_i$next \fus_full_cr
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
- switch \rst
- case 1'1
- assign \cr_full_wr__data_i$next 32'00000000000000000000000000000000
- end
+ process $group_248
+ assign \cr_full_wr__data_i 32'00000000000000000000000000000000
+ assign \cr_full_wr__data_i \fus_dest2_o
sync init
- update \cr_full_wr__data_i 32'00000000000000000000000000000000
- sync posedge \clk
- update \cr_full_wr__data_i \cr_full_wr__data_i$next
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:121"
- wire width 16 $560
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:121"
- wire width 4 $561
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:121"
- cell $sub $562
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:137"
+ wire width 16 $648
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:137"
+ wire width 4 $649
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:137"
+ cell $sub $650
parameter \A_SIGNED 0
parameter \A_WIDTH 3
parameter \B_SIGNED 0
parameter \Y_WIDTH 4
connect \A 3'111
connect \B \cr_out
- connect \Y $561
+ connect \Y $649
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:121"
- wire width 16 $563
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:121"
- cell $sshl $564
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:137"
+ wire width 16 $651
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:137"
+ cell $sshl $652
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 16
connect \A 1'1
- connect \B $561
- connect \Y $563
+ connect \B $649
+ connect \Y $651
end
- connect $560 $563
- process $group_232
- assign \cr_wen$next \cr_wen
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223"
+ connect $648 $651
+ process $group_249
+ assign \cr_wen 8'00000000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283"
switch { \wrpick_CR_cr_a_en_o }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283"
case 1'1
- assign \cr_wen$next $560 [7:0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
+ assign \cr_wen $648 [7:0]
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285"
case
- assign \cr_wen$next 8'00000000
- end
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
- switch \rst
- case 1'1
- assign \cr_wen$next 8'00000000
+ assign \cr_wen 8'00000000
end
sync init
- update \cr_wen 8'00000000
- sync posedge \clk
- update \cr_wen \cr_wen$next
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:235"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296"
wire width 1 \wrflag_alu0_cr_a_1
- process $group_233
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+ wire width 1 $653
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+ cell $and $654
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \fus_cr_a_ok
+ connect \B \busy_o
+ connect \Y $653
+ end
+ process $group_250
assign \wrflag_alu0_cr_a_1 1'0
- assign \wrflag_alu0_cr_a_1 \fus_cr_a_ok
+ assign \wrflag_alu0_cr_a_1 $653
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
- wire width 1 $565
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
- cell $and $566
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
+ wire width 1 $655
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
+ cell $and $656
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wr__rel [1]
connect \B \fu_enable [0]
- connect \Y $565
+ connect \Y $655
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
- wire width 1 $567
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
- cell $and $568
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
+ wire width 1 $657
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
+ cell $and $658
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr__rel$83 [2]
+ connect \A \wr__rel$103 [2]
connect \B \fu_enable [1]
- connect \Y $567
+ connect \Y $657
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
- wire width 1 $569
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
- cell $and $570
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
+ wire width 1 $659
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
+ cell $and $660
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr__rel$87 [1]
+ connect \A \wr__rel$107 [1]
connect \B \fu_enable [4]
- connect \Y $569
+ connect \Y $659
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
- wire width 1 $571
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
- cell $and $572
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
+ wire width 1 $661
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
+ cell $and $662
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr__rel$91 [1]
+ connect \A \wr__rel$111 [1]
connect \B \fu_enable [6]
- connect \Y $571
+ connect \Y $661
end
- process $group_234
- assign \wrpick_CR_cr_a_i 4'0000
- assign \wrpick_CR_cr_a_i [0] $565
- assign \wrpick_CR_cr_a_i [1] $567
- assign \wrpick_CR_cr_a_i [2] $569
- assign \wrpick_CR_cr_a_i [3] $571
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
+ wire width 1 $663
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
+ cell $and $664
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \wr__rel$113 [1]
+ connect \B \fu_enable [7]
+ connect \Y $663
+ end
+ process $group_251
+ assign \wrpick_CR_cr_a_i 5'00000
+ assign \wrpick_CR_cr_a_i [0] $655
+ assign \wrpick_CR_cr_a_i [1] $657
+ assign \wrpick_CR_cr_a_i [2] $659
+ assign \wrpick_CR_cr_a_i [3] $661
+ assign \wrpick_CR_cr_a_i [4] $663
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:235"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296"
wire width 1 \wrflag_cr0_cr_a_2
- process $group_235
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+ wire width 1 $665
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+ cell $and $666
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \fus_cr_a_ok$212
+ connect \B \busy_o$6
+ connect \Y $665
+ end
+ process $group_252
assign \wrflag_cr0_cr_a_2 1'0
- assign \wrflag_cr0_cr_a_2 \fus_cr_a_ok$190
+ assign \wrflag_cr0_cr_a_2 $665
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:235"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296"
wire width 1 \wrflag_logical0_cr_a_1
- process $group_236
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+ wire width 1 $667
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+ cell $and $668
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \fus_cr_a_ok$213
+ connect \B \busy_o$36
+ connect \Y $667
+ end
+ process $group_253
assign \wrflag_logical0_cr_a_1 1'0
- assign \wrflag_logical0_cr_a_1 \fus_cr_a_ok$191
+ assign \wrflag_logical0_cr_a_1 $667
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296"
+ wire width 1 \wrflag_mul0_cr_a_1
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+ wire width 1 $669
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+ cell $and $670
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \fus_cr_a_ok$214
+ connect \B \busy_o$53
+ connect \Y $669
+ end
+ process $group_254
+ assign \wrflag_mul0_cr_a_1 1'0
+ assign \wrflag_mul0_cr_a_1 $669
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:235"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296"
wire width 1 \wrflag_shiftrot0_cr_a_1
- process $group_237
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+ wire width 1 $671
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+ cell $and $672
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \fus_cr_a_ok$215
+ connect \B \busy_o$62
+ connect \Y $671
+ end
+ process $group_255
assign \wrflag_shiftrot0_cr_a_1 1'0
- assign \wrflag_shiftrot0_cr_a_1 \fus_cr_a_ok$192
+ assign \wrflag_shiftrot0_cr_a_1 $671
sync init
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
- wire width 4 $573
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
- cell $or $574
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+ wire width 4 $673
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+ cell $or $674
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 4
- connect \A \fus_cr_a
- connect \B \fus_cr_a$193
- connect \Y $573
+ connect \A \fus_dest2_o$216
+ connect \B \fus_dest3_o
+ connect \Y $673
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
- wire width 4 $575
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
- cell $or $576
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+ wire width 4 $675
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+ cell $or $676
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 4
- connect \A \fus_cr_a$194
- connect \B \fus_cr_a$195
- connect \Y $575
+ connect \A \fus_dest2_o$218
+ connect \B \fus_dest2_o$219
+ connect \Y $675
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
- wire width 4 $577
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
- cell $or $578
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+ wire width 4 $677
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+ cell $or $678
parameter \A_SIGNED 0
parameter \A_WIDTH 4
parameter \B_SIGNED 0
parameter \B_WIDTH 4
parameter \Y_WIDTH 4
- connect \A $573
- connect \B $575
- connect \Y $577
+ connect \A \fus_dest2_o$217
+ connect \B $675
+ connect \Y $677
end
- process $group_238
- assign \cr_data_i$next \cr_data_i
- assign \cr_data_i$next $577
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
- switch \rst
- case 1'1
- assign \cr_data_i$next 4'0000
- end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+ wire width 4 $679
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+ cell $or $680
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 4
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 4
+ parameter \Y_WIDTH 4
+ connect \A $673
+ connect \B $677
+ connect \Y $679
+ end
+ process $group_256
+ assign \cr_data_i 4'0000
+ assign \cr_data_i $679
sync init
- update \cr_data_i 4'0000
- sync posedge \clk
- update \cr_data_i \cr_data_i$next
end
- process $group_239
- assign \xer_wen$next \xer_wen
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223"
+ process $group_257
+ assign \xer_wen 3'000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283"
switch { \wrpick_XER_xer_ca_en_o }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283"
case 1'1
- assign \xer_wen$next 3'010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
+ assign \xer_wen 3'010
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285"
case
- assign \xer_wen$next 3'000
- end
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
- switch \rst
- case 1'1
- assign \xer_wen$next 3'000
+ assign \xer_wen 3'000
end
sync init
- update \xer_wen 3'000
- sync posedge \clk
- update \xer_wen \xer_wen$next
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:235"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296"
wire width 1 \wrflag_alu0_xer_ca_2
- process $group_240
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+ wire width 1 $681
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+ cell $and $682
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \fus_xer_ca_ok
+ connect \B \busy_o
+ connect \Y $681
+ end
+ process $group_258
assign \wrflag_alu0_xer_ca_2 1'0
- assign \wrflag_alu0_xer_ca_2 \fus_xer_ca_ok
+ assign \wrflag_alu0_xer_ca_2 $681
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
- wire width 1 $579
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
- cell $and $580
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
+ wire width 1 $683
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
+ cell $and $684
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wr__rel [2]
connect \B \fu_enable [0]
- connect \Y $579
+ connect \Y $683
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
- wire width 1 $581
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
- cell $and $582
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
+ wire width 1 $685
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
+ cell $and $686
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr__rel$87 [2]
+ connect \A \wr__rel$107 [2]
connect \B \fu_enable [4]
- connect \Y $581
+ connect \Y $685
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
- wire width 1 $583
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
- cell $and $584
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
+ wire width 1 $687
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
+ cell $and $688
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr__rel$89 [5]
+ connect \A \wr__rel$109 [5]
connect \B \fu_enable [5]
- connect \Y $583
+ connect \Y $687
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
- wire width 1 $585
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
- cell $and $586
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
+ wire width 1 $689
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
+ cell $and $690
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr__rel$91 [2]
- connect \B \fu_enable [6]
- connect \Y $585
+ connect \A \wr__rel$113 [2]
+ connect \B \fu_enable [7]
+ connect \Y $689
end
- process $group_241
+ process $group_259
assign \wrpick_XER_xer_ca_i 4'0000
- assign \wrpick_XER_xer_ca_i [0] $579
- assign \wrpick_XER_xer_ca_i [1] $581
- assign \wrpick_XER_xer_ca_i [2] $583
- assign \wrpick_XER_xer_ca_i [3] $585
+ assign \wrpick_XER_xer_ca_i [0] $683
+ assign \wrpick_XER_xer_ca_i [1] $685
+ assign \wrpick_XER_xer_ca_i [2] $687
+ assign \wrpick_XER_xer_ca_i [3] $689
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:235"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296"
wire width 1 \wrflag_logical0_xer_ca_2
- process $group_242
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+ wire width 1 $691
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+ cell $and $692
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \fus_xer_ca_ok$220
+ connect \B \busy_o$36
+ connect \Y $691
+ end
+ process $group_260
assign \wrflag_logical0_xer_ca_2 1'0
- assign \wrflag_logical0_xer_ca_2 \fus_xer_ca_ok$196
+ assign \wrflag_logical0_xer_ca_2 $691
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:235"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296"
wire width 1 \wrflag_spr0_xer_ca_5
- process $group_243
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+ wire width 1 $693
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+ cell $and $694
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \fus_xer_ca_ok$221
+ connect \B \busy_o$42
+ connect \Y $693
+ end
+ process $group_261
assign \wrflag_spr0_xer_ca_5 1'0
- assign \wrflag_spr0_xer_ca_5 \fus_xer_ca_ok$197
+ assign \wrflag_spr0_xer_ca_5 $693
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:235"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296"
wire width 1 \wrflag_shiftrot0_xer_ca_2
- process $group_244
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+ wire width 1 $695
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+ cell $and $696
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \fus_xer_ca_ok$222
+ connect \B \busy_o$62
+ connect \Y $695
+ end
+ process $group_262
assign \wrflag_shiftrot0_xer_ca_2 1'0
- assign \wrflag_shiftrot0_xer_ca_2 \fus_xer_ca_ok$198
+ assign \wrflag_shiftrot0_xer_ca_2 $695
sync init
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
- wire width 2 $587
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
- cell $or $588
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+ wire width 2 $697
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+ cell $or $698
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \B_WIDTH 2
parameter \Y_WIDTH 2
- connect \A \fus_xer_ca
- connect \B \fus_xer_ca$199
- connect \Y $587
+ connect \A \fus_dest3_o$223
+ connect \B \fus_dest3_o$224
+ connect \Y $697
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
- wire width 2 $589
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
- cell $or $590
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+ wire width 2 $699
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+ cell $or $700
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \B_WIDTH 2
parameter \Y_WIDTH 2
- connect \A \fus_xer_ca$200
- connect \B \fus_xer_ca$201
- connect \Y $589
+ connect \A \fus_dest6_o
+ connect \B \fus_dest3_o$225
+ connect \Y $699
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
- wire width 2 $591
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
- cell $or $592
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+ wire width 2 $701
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+ cell $or $702
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \B_WIDTH 2
parameter \Y_WIDTH 2
- connect \A $587
- connect \B $589
- connect \Y $591
+ connect \A $697
+ connect \B $699
+ connect \Y $701
end
- process $group_245
- assign \xer_data_i$next \xer_data_i
- assign \xer_data_i$next $591
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
- switch \rst
- case 1'1
- assign \xer_data_i$next 2'00
- end
+ process $group_263
+ assign \xer_data_i 2'00
+ assign \xer_data_i $701
sync init
- update \xer_data_i 2'00
- sync posedge \clk
- update \xer_data_i \xer_data_i$next
end
- process $group_246
- assign \xer_wen$216$next \xer_wen$216
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223"
+ process $group_264
+ assign \xer_wen$248 3'000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283"
switch { \wrpick_XER_xer_ov_en_o }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283"
case 1'1
- assign \xer_wen$216$next 3'100
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
+ assign \xer_wen$248 3'100
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285"
case
- assign \xer_wen$216$next 3'000
- end
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
- switch \rst
- case 1'1
- assign \xer_wen$216$next 3'000
+ assign \xer_wen$248 3'000
end
sync init
- update \xer_wen$216 3'000
- sync posedge \clk
- update \xer_wen$216 \xer_wen$216$next
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:235"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296"
wire width 1 \wrflag_alu0_xer_ov_3
- process $group_247
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+ wire width 1 $703
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+ cell $and $704
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \fus_xer_ov_ok
+ connect \B \busy_o
+ connect \Y $703
+ end
+ process $group_265
assign \wrflag_alu0_xer_ov_3 1'0
- assign \wrflag_alu0_xer_ov_3 \fus_xer_ov_ok
+ assign \wrflag_alu0_xer_ov_3 $703
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
- wire width 1 $593
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
- cell $and $594
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
+ wire width 1 $705
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
+ cell $and $706
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wr__rel [3]
connect \B \fu_enable [0]
- connect \Y $593
+ connect \Y $705
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
- wire width 1 $595
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
- cell $and $596
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
+ wire width 1 $707
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
+ cell $and $708
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr__rel$89 [4]
+ connect \A \wr__rel$109 [4]
connect \B \fu_enable [5]
- connect \Y $595
+ connect \Y $707
end
- process $group_248
- assign \wrpick_XER_xer_ov_i 2'00
- assign \wrpick_XER_xer_ov_i [0] $593
- assign \wrpick_XER_xer_ov_i [1] $595
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
+ wire width 1 $709
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
+ cell $and $710
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \wr__rel$111 [2]
+ connect \B \fu_enable [6]
+ connect \Y $709
+ end
+ process $group_266
+ assign \wrpick_XER_xer_ov_i 3'000
+ assign \wrpick_XER_xer_ov_i [0] $705
+ assign \wrpick_XER_xer_ov_i [1] $707
+ assign \wrpick_XER_xer_ov_i [2] $709
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:235"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296"
wire width 1 \wrflag_spr0_xer_ov_4
- process $group_249
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+ wire width 1 $711
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+ cell $and $712
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \fus_xer_ov_ok$226
+ connect \B \busy_o$42
+ connect \Y $711
+ end
+ process $group_267
assign \wrflag_spr0_xer_ov_4 1'0
- assign \wrflag_spr0_xer_ov_4 \fus_xer_ov_ok$202
+ assign \wrflag_spr0_xer_ov_4 $711
sync init
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
- wire width 2 $597
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
- cell $or $598
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296"
+ wire width 1 \wrflag_mul0_xer_ov_2
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+ wire width 1 $713
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+ cell $and $714
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \fus_xer_ov_ok$227
+ connect \B \busy_o$53
+ connect \Y $713
+ end
+ process $group_268
+ assign \wrflag_mul0_xer_ov_2 1'0
+ assign \wrflag_mul0_xer_ov_2 $713
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+ wire width 2 $715
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+ cell $or $716
parameter \A_SIGNED 0
parameter \A_WIDTH 2
parameter \B_SIGNED 0
parameter \B_WIDTH 2
parameter \Y_WIDTH 2
- connect \A \fus_xer_ov
- connect \B \fus_xer_ov$203
- connect \Y $597
+ connect \A \fus_dest5_o
+ connect \B \fus_dest3_o$228
+ connect \Y $715
end
- process $group_250
- assign \xer_data_i$217$next \xer_data_i$217
- assign \xer_data_i$217$next $597
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
- switch \rst
- case 1'1
- assign \xer_data_i$217$next 2'00
- end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+ wire width 2 $717
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+ cell $or $718
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 2
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 2
+ parameter \Y_WIDTH 2
+ connect \A \fus_dest4_o
+ connect \B $715
+ connect \Y $717
+ end
+ process $group_269
+ assign \xer_data_i$249 2'00
+ assign \xer_data_i$249 $717
sync init
- update \xer_data_i$217 2'00
- sync posedge \clk
- update \xer_data_i$217 \xer_data_i$217$next
end
- process $group_251
- assign \xer_wen$218$next \xer_wen$218
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223"
+ process $group_270
+ assign \xer_wen$250 3'000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283"
switch { \wrpick_XER_xer_so_en_o }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283"
case 1'1
- assign \xer_wen$218$next 3'001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
+ assign \xer_wen$250 3'001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285"
case
- assign \xer_wen$218$next 3'000
- end
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
- switch \rst
- case 1'1
- assign \xer_wen$218$next 3'000
+ assign \xer_wen$250 3'000
end
sync init
- update \xer_wen$218 3'000
- sync posedge \clk
- update \xer_wen$218 \xer_wen$218$next
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:235"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296"
wire width 1 \wrflag_alu0_xer_so_4
- process $group_252
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+ wire width 1 $719
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+ cell $and $720
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \fus_xer_so_ok
+ connect \B \busy_o
+ connect \Y $719
+ end
+ process $group_271
assign \wrflag_alu0_xer_so_4 1'0
- assign \wrflag_alu0_xer_so_4 \fus_xer_so_ok
+ assign \wrflag_alu0_xer_so_4 $719
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
- wire width 1 $599
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
- cell $and $600
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
+ wire width 1 $721
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
+ cell $and $722
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wr__rel [4]
connect \B \fu_enable [0]
- connect \Y $599
+ connect \Y $721
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
- wire width 1 $601
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
- cell $and $602
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
+ wire width 1 $723
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
+ cell $and $724
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr__rel$89 [3]
+ connect \A \wr__rel$109 [3]
connect \B \fu_enable [5]
- connect \Y $601
+ connect \Y $723
end
- process $group_253
- assign \wrpick_XER_xer_so_i 2'00
- assign \wrpick_XER_xer_so_i [0] $599
- assign \wrpick_XER_xer_so_i [1] $601
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
+ wire width 1 $725
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
+ cell $and $726
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \wr__rel$111 [3]
+ connect \B \fu_enable [6]
+ connect \Y $725
+ end
+ process $group_272
+ assign \wrpick_XER_xer_so_i 3'000
+ assign \wrpick_XER_xer_so_i [0] $721
+ assign \wrpick_XER_xer_so_i [1] $723
+ assign \wrpick_XER_xer_so_i [2] $725
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:235"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296"
wire width 1 \wrflag_spr0_xer_so_3
- process $group_254
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+ wire width 1 $727
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+ cell $and $728
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \fus_xer_so_ok$229
+ connect \B \busy_o$42
+ connect \Y $727
+ end
+ process $group_273
assign \wrflag_spr0_xer_so_3 1'0
- assign \wrflag_spr0_xer_so_3 \fus_xer_so_ok$204
+ assign \wrflag_spr0_xer_so_3 $727
sync init
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
- wire width 2 $603
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
- wire width 1 $604
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
- cell $or $605
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296"
+ wire width 1 \wrflag_mul0_xer_so_3
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+ wire width 1 $729
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+ cell $and $730
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \fus_xer_so
- connect \B \fus_xer_so$205
- connect \Y $604
+ connect \A \fus_xer_so_ok$230
+ connect \B \busy_o$53
+ connect \Y $729
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
- cell $pos $606
+ process $group_274
+ assign \wrflag_mul0_xer_so_3 1'0
+ assign \wrflag_mul0_xer_so_3 $729
+ sync init
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+ wire width 2 $731
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+ wire width 1 $732
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+ cell $or $733
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \fus_dest4_o$232
+ connect \B \fus_dest4_o$233
+ connect \Y $732
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+ wire width 1 $734
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+ cell $or $735
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \fus_dest5_o$231
+ connect \B $732
+ connect \Y $734
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+ cell $pos $736
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 2
- connect \A $604
- connect \Y $603
+ connect \A $734
+ connect \Y $731
end
- process $group_255
- assign \xer_data_i$219$next \xer_data_i$219
- assign \xer_data_i$219$next $603
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
- switch \rst
- case 1'1
- assign \xer_data_i$219$next 2'00
- end
+ process $group_275
+ assign \xer_data_i$251 2'00
+ assign \xer_data_i$251 $731
sync init
- update \xer_data_i$219 2'00
- sync posedge \clk
- update \xer_data_i$219 \xer_data_i$219$next
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:150"
- wire width 8 $607
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:150"
- cell $sshl $608
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:170"
+ wire width 8 $737
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:170"
+ cell $sshl $738
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 8
connect \A 1'1
connect \B \fasto1
- connect \Y $607
+ connect \Y $737
end
- process $group_256
- assign \fast_wen$next \fast_wen
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223"
+ process $group_276
+ assign \fast_wen 8'00000000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283"
switch { \wrpick_FAST_fast1_en_o }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283"
case 1'1
- assign \fast_wen$next $607
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
+ assign \fast_wen $737
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285"
case
- assign \fast_wen$next 8'00000000
- end
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
- switch \rst
- case 1'1
- assign \fast_wen$next 8'00000000
+ assign \fast_wen 8'00000000
end
sync init
- update \fast_wen 8'00000000
- sync posedge \clk
- update \fast_wen \fast_wen$next
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:235"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296"
wire width 1 \wrflag_branch0_fast1_0
- process $group_257
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+ wire width 1 $739
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+ cell $and $740
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \fus_fast1_ok
+ connect \B \busy_o$14
+ connect \Y $739
+ end
+ process $group_277
assign \wrflag_branch0_fast1_0 1'0
- assign \wrflag_branch0_fast1_0 \fus_fast1_ok
+ assign \wrflag_branch0_fast1_0 $739
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
- wire width 1 $609
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
- cell $and $610
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
+ wire width 1 $741
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
+ cell $and $742
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr__rel$96 [0]
+ connect \A \wr__rel$124 [0]
connect \B \fu_enable [2]
- connect \Y $609
+ connect \Y $741
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
- wire width 1 $611
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
- cell $and $612
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
+ wire width 1 $743
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
+ cell $and $744
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr__rel$85 [1]
+ connect \A \wr__rel$105 [1]
connect \B \fu_enable [3]
- connect \Y $611
+ connect \Y $743
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
- wire width 1 $613
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
- cell $and $614
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
+ wire width 1 $745
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
+ cell $and $746
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr__rel$89 [2]
+ connect \A \wr__rel$109 [2]
connect \B \fu_enable [5]
- connect \Y $613
+ connect \Y $745
end
- process $group_258
+ process $group_278
assign \wrpick_FAST_fast1_i 3'000
- assign \wrpick_FAST_fast1_i [0] $609
- assign \wrpick_FAST_fast1_i [1] $611
- assign \wrpick_FAST_fast1_i [2] $613
+ assign \wrpick_FAST_fast1_i [0] $741
+ assign \wrpick_FAST_fast1_i [1] $743
+ assign \wrpick_FAST_fast1_i [2] $745
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:242"
- wire width 1 $615
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:242"
- cell $and $616
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+ wire width 1 $747
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+ cell $and $748
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wrpick_FAST_fast1_o [0]
connect \B \wrpick_FAST_fast1_en_o
- connect \Y $615
+ connect \Y $747
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:242"
- wire width 1 $617
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:242"
- cell $and $618
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+ wire width 1 $749
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+ cell $and $750
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wrpick_FAST_fast2_o [0]
connect \B \wrpick_FAST_fast2_en_o
- connect \Y $617
+ connect \Y $749
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:242"
- wire width 1 $619
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:242"
- cell $and $620
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+ wire width 1 $751
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
+ cell $and $752
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 1
connect \A \wrpick_FAST_nia_o [0]
connect \B \wrpick_FAST_nia_en_o
- connect \Y $619
+ connect \Y $751
end
- process $group_259
- assign \wr__go$97$next \wr__go$97
- assign \wr__go$97$next [0] $615
- assign \wr__go$97$next [1] $617
- assign \wr__go$97$next [2] $619
+ process $group_279
+ assign \wr__go$125 3'000
+ assign \wr__go$125 [0] $747
+ assign \wr__go$125 [1] $749
+ assign \wr__go$125 [2] $751
sync init
- update \wr__go$97 3'000
- sync posedge \clk
- update \wr__go$97 \wr__go$97$next
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:235"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296"
wire width 1 \wrflag_trap0_fast1_1
- process $group_260
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+ wire width 1 $753
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+ cell $and $754
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \fus_fast1_ok$234
+ connect \B \busy_o$22
+ connect \Y $753
+ end
+ process $group_280
assign \wrflag_trap0_fast1_1 1'0
- assign \wrflag_trap0_fast1_1 \fus_fast1_ok$206
+ assign \wrflag_trap0_fast1_1 $753
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:235"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296"
wire width 1 \wrflag_spr0_fast1_2
- process $group_261
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+ wire width 1 $755
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+ cell $and $756
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \fus_fast1_ok$235
+ connect \B \busy_o$42
+ connect \Y $755
+ end
+ process $group_281
assign \wrflag_spr0_fast1_2 1'0
- assign \wrflag_spr0_fast1_2 \fus_fast1_ok$207
+ assign \wrflag_spr0_fast1_2 $755
sync init
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
- wire width 64 $621
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
- cell $or $622
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+ wire width 64 $757
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+ cell $or $758
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \B_WIDTH 64
parameter \Y_WIDTH 64
- connect \A \fus_fast1$208
- connect \B \fus_fast1$209
- connect \Y $621
+ connect \A \fus_dest2_o$236
+ connect \B \fus_dest3_o$237
+ connect \Y $757
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
- wire width 64 $623
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:28"
- cell $or $624
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+ wire width 64 $759
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+ cell $or $760
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \B_WIDTH 64
parameter \Y_WIDTH 64
- connect \A \fus_fast1
- connect \B $621
- connect \Y $623
+ connect \A \dest1_o$126
+ connect \B $757
+ connect \Y $759
end
- process $group_262
- assign \fast_data_i$next \fast_data_i
- assign \fast_data_i$next $623
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
- switch \rst
- case 1'1
- assign \fast_data_i$next 64'0000000000000000000000000000000000000000000000000000000000000000
- end
+ process $group_282
+ assign \fast_data_i 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \fast_data_i $759
sync init
- update \fast_data_i 64'0000000000000000000000000000000000000000000000000000000000000000
- sync posedge \clk
- update \fast_data_i \fast_data_i$next
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:152"
- wire width 8 $625
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:152"
- cell $sshl $626
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:172"
+ wire width 8 $761
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:172"
+ cell $sshl $762
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \Y_WIDTH 8
connect \A 1'1
connect \B \fasto2
- connect \Y $625
+ connect \Y $761
end
- process $group_263
- assign \fast_wen$220$next \fast_wen$220
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223"
+ process $group_283
+ assign \fast_wen$252 8'00000000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283"
switch { \wrpick_FAST_fast2_en_o }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283"
case 1'1
- assign \fast_wen$220$next $625
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
+ assign \fast_wen$252 $761
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285"
case
- assign \fast_wen$220$next 8'00000000
- end
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
- switch \rst
- case 1'1
- assign \fast_wen$220$next 8'00000000
+ assign \fast_wen$252 8'00000000
end
sync init
- update \fast_wen$220 8'00000000
- sync posedge \clk
- update \fast_wen$220 \fast_wen$220$next
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:235"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296"
wire width 1 \wrflag_branch0_fast2_1
- process $group_264
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+ wire width 1 $763
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+ cell $and $764
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \fus_fast2_ok
+ connect \B \busy_o$14
+ connect \Y $763
+ end
+ process $group_284
assign \wrflag_branch0_fast2_1 1'0
- assign \wrflag_branch0_fast2_1 \fus_fast2_ok
+ assign \wrflag_branch0_fast2_1 $763
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
- wire width 1 $627
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
- cell $and $628
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
+ wire width 1 $765
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
+ cell $and $766
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr__rel$96 [1]
+ connect \A \wr__rel$124 [1]
connect \B \fu_enable [2]
- connect \Y $627
+ connect \Y $765
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
- wire width 1 $629
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
- cell $and $630
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
+ wire width 1 $767
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
+ cell $and $768
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr__rel$85 [2]
+ connect \A \wr__rel$105 [2]
connect \B \fu_enable [3]
- connect \Y $629
+ connect \Y $767
end
- process $group_265
+ process $group_285
assign \wrpick_FAST_fast2_i 2'00
- assign \wrpick_FAST_fast2_i [0] $627
- assign \wrpick_FAST_fast2_i [1] $629
+ assign \wrpick_FAST_fast2_i [0] $765
+ assign \wrpick_FAST_fast2_i [1] $767
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:235"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296"
wire width 1 \wrflag_trap0_fast2_2
- process $group_266
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+ wire width 1 $769
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+ cell $and $770
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \fus_fast2_ok$238
+ connect \B \busy_o$22
+ connect \Y $769
+ end
+ process $group_286
assign \wrflag_trap0_fast2_2 1'0
- assign \wrflag_trap0_fast2_2 \fus_fast2_ok$210
+ assign \wrflag_trap0_fast2_2 $769
sync init
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
- wire width 64 $631
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
- cell $or $632
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+ wire width 64 $771
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+ cell $or $772
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \B_WIDTH 64
parameter \Y_WIDTH 64
- connect \A \fus_fast2
- connect \B \fus_fast2$211
- connect \Y $631
+ connect \A \fus_dest2_o$239
+ connect \B \fus_dest3_o$240
+ connect \Y $771
end
- process $group_267
- assign \fast_data_i$221$next \fast_data_i$221
- assign \fast_data_i$221$next $631
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
- switch \rst
- case 1'1
- assign \fast_data_i$221$next 64'0000000000000000000000000000000000000000000000000000000000000000
- end
+ process $group_287
+ assign \fast_data_i$253 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \fast_data_i$253 $771
sync init
- update \fast_data_i$221 64'0000000000000000000000000000000000000000000000000000000000000000
- sync posedge \clk
- update \fast_data_i$221 \fast_data_i$221$next
end
- process $group_268
- assign \fast_nia_wen$next \fast_nia_wen
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223"
+ process $group_288
+ assign \fast_nia_wen 8'00000000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283"
switch { \wrpick_FAST_nia_en_o }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283"
case 1'1
- assign \fast_nia_wen$next 8'00000001
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
+ assign \fast_nia_wen 8'00000001
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285"
case
- assign \fast_nia_wen$next 8'00000000
- end
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
- switch \rst
- case 1'1
- assign \fast_nia_wen$next 8'00000000
+ assign \fast_nia_wen 8'00000000
end
sync init
- update \fast_nia_wen 8'00000000
- sync posedge \clk
- update \fast_nia_wen \fast_nia_wen$next
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:235"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296"
wire width 1 \wrflag_branch0_nia_2
- process $group_269
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+ wire width 1 $773
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+ cell $and $774
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \fus_nia_ok
+ connect \B \busy_o$14
+ connect \Y $773
+ end
+ process $group_289
assign \wrflag_branch0_nia_2 1'0
- assign \wrflag_branch0_nia_2 \fus_nia_ok
+ assign \wrflag_branch0_nia_2 $773
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
- wire width 1 $633
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
- cell $and $634
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
+ wire width 1 $775
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
+ cell $and $776
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr__rel$96 [2]
+ connect \A \wr__rel$124 [2]
connect \B \fu_enable [2]
- connect \Y $633
+ connect \Y $775
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
- wire width 1 $635
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
- cell $and $636
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
+ wire width 1 $777
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
+ cell $and $778
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr__rel$85 [3]
+ connect \A \wr__rel$105 [3]
connect \B \fu_enable [3]
- connect \Y $635
+ connect \Y $777
end
- process $group_270
+ process $group_290
assign \wrpick_FAST_nia_i 2'00
- assign \wrpick_FAST_nia_i [0] $633
- assign \wrpick_FAST_nia_i [1] $635
+ assign \wrpick_FAST_nia_i [0] $775
+ assign \wrpick_FAST_nia_i [1] $777
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:235"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296"
wire width 1 \wrflag_trap0_nia_3
- process $group_271
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+ wire width 1 $779
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+ cell $and $780
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \fus_nia_ok$241
+ connect \B \busy_o$22
+ connect \Y $779
+ end
+ process $group_291
assign \wrflag_trap0_nia_3 1'0
- assign \wrflag_trap0_nia_3 \fus_nia_ok$212
+ assign \wrflag_trap0_nia_3 $779
sync init
end
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
- wire width 64 $637
- attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:25"
- cell $or $638
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+ wire width 64 $781
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+ cell $or $782
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \B_WIDTH 64
parameter \Y_WIDTH 64
- connect \A \fus_nia
- connect \B \fus_nia$213
- connect \Y $637
+ connect \A \fus_dest3_o$242
+ connect \B \fus_dest4_o$243
+ connect \Y $781
end
- process $group_272
- assign \fast_data_i$222$next \fast_data_i$222
- assign \fast_data_i$222$next $637
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
- switch \rst
- case 1'1
- assign \fast_data_i$222$next 64'0000000000000000000000000000000000000000000000000000000000000000
- end
+ process $group_292
+ assign \fast_data_i$254 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \fast_data_i$254 $781
sync init
- update \fast_data_i$222 64'0000000000000000000000000000000000000000000000000000000000000000
- sync posedge \clk
- update \fast_data_i$222 \fast_data_i$222$next
end
- process $group_273
- assign \fast_wen$223$next \fast_wen$223
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223"
+ process $group_293
+ assign \fast_wen$255 8'00000000
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283"
switch { \wrpick_FAST_msr_en_o }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283"
case 1'1
- assign \fast_wen$223$next 8'00000010
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
+ assign \fast_wen$255 8'00000010
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285"
case
- assign \fast_wen$223$next 8'00000000
- end
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
- switch \rst
- case 1'1
- assign \fast_wen$223$next 8'00000000
+ assign \fast_wen$255 8'00000000
end
sync init
- update \fast_wen$223 8'00000000
- sync posedge \clk
- update \fast_wen$223 \fast_wen$223$next
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:235"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296"
wire width 1 \wrflag_trap0_msr_4
- process $group_274
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+ wire width 1 $783
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+ cell $and $784
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \fus_msr_ok
+ connect \B \busy_o$22
+ connect \Y $783
+ end
+ process $group_294
assign \wrflag_trap0_msr_4 1'0
- assign \wrflag_trap0_msr_4 \fus_msr_ok
+ assign \wrflag_trap0_msr_4 $783
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
- wire width 1 $639
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
- cell $and $640
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
+ wire width 1 $785
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
+ cell $and $786
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr__rel$85 [4]
+ connect \A \wr__rel$105 [4]
connect \B \fu_enable [3]
- connect \Y $639
+ connect \Y $785
end
- process $group_275
+ process $group_295
assign \wrpick_FAST_msr_i 1'0
- assign \wrpick_FAST_msr_i $639
+ assign \wrpick_FAST_msr_i $785
sync init
end
- process $group_276
- assign \fast_data_i$224$next \fast_data_i$224
- assign \fast_data_i$224$next \fus_msr
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
- switch \rst
- case 1'1
- assign \fast_data_i$224$next 64'0000000000000000000000000000000000000000000000000000000000000000
- end
+ process $group_296
+ assign \fast_data_i$256 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \fast_data_i$256 \fus_dest5_o$244
sync init
- update \fast_data_i$224 64'0000000000000000000000000000000000000000000000000000000000000000
- sync posedge \clk
- update \fast_data_i$224 \fast_data_i$224$next
end
- process $group_277
- assign \spr_dest__wen$next \spr_dest__wen
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223"
+ process $group_297
+ assign \spr_dest__wen 1'0
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283"
switch { \wrpick_SPR_spr1_en_o }
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:223"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:283"
case 1'1
- assign \spr_dest__wen$next \spro [0]
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:225"
+ assign \spr_dest__wen \spro [0]
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:285"
case
- assign \spr_dest__wen$next 1'0
- end
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
- switch \rst
- case 1'1
- assign \spr_dest__wen$next 1'0
+ assign \spr_dest__wen 1'0
end
sync init
- update \spr_dest__wen 1'0
- sync posedge \clk
- update \spr_dest__wen \spr_dest__wen$next
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:235"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:296"
wire width 1 \wrflag_spr0_spr1_1
- process $group_278
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+ wire width 1 $787
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+ cell $and $788
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \fus_spr1_ok
+ connect \B \busy_o$42
+ connect \Y $787
+ end
+ process $group_298
assign \wrflag_spr0_spr1_1 1'0
- assign \wrflag_spr0_spr1_1 \fus_spr1_ok
+ assign \wrflag_spr0_spr1_1 $787
sync init
end
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
- wire width 1 $641
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240"
- cell $and $642
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
+ wire width 1 $789
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:301"
+ cell $and $790
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 1
parameter \Y_WIDTH 1
- connect \A \wr__rel$89 [1]
+ connect \A \wr__rel$109 [1]
connect \B \fu_enable [5]
- connect \Y $641
+ connect \Y $789
end
- process $group_279
+ process $group_299
assign \wrpick_SPR_spr1_i 1'0
- assign \wrpick_SPR_spr1_i $641
+ assign \wrpick_SPR_spr1_i $789
sync init
end
- process $group_280
- assign \spr_dest__data_i$next \spr_dest__data_i
- assign \spr_dest__data_i$next \fus_spr1
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
- switch \rst
- case 1'1
- assign \spr_dest__data_i$next 64'0000000000000000000000000000000000000000000000000000000000000000
- end
+ process $group_300
+ assign \spr_dest__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \spr_dest__data_i \fus_dest2_o$245
sync init
- update \spr_dest__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
- sync posedge \clk
- update \spr_dest__data_i \spr_dest__data_i$next
end
end
attribute \generator "nMigen"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:81"
case 1'1
assign \f_busy_o 1'0
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:83"
case
assign \f_busy_o \ibus__cyc
end
switch { \f_fetch_err_o }
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:81"
case 1'1
- assign \f_instr_o 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:83"
case
assign \f_instr_o \ibus_rdata
end
attribute \nmigen.hierarchy "test_issuer"
module \test_issuer
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 input 0 \pc
+ wire width 64 input 0 \pc_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 input 1 \pc_ok
- attribute \src "simple/issuer.py:46"
+ wire width 1 input 1 \pc_i_ok
+ attribute \src "simple/issuer.py:49"
wire width 64 output 2 \pc_o
- attribute \src "simple/issuer.py:45"
+ attribute \src "simple/issuer.py:48"
wire width 1 input 3 \go_insn_i
- attribute \src "simple/issuer.py:49"
+ attribute \src "simple/issuer.py:56"
wire width 1 input 4 \memerr_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
wire width 4 output 5 \rd__go
wire width 1 input 8 \shadown_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96"
wire width 1 input 9 \go_die_i
- attribute \enum_base_type "InternalOp"
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 7 output 10 \oper_i__insn_type
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 output 11 \oper_i__lk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \enum_base_type "Function"
+ attribute \enum_value_00000000000 "NONE"
+ attribute \enum_value_00000000010 "ALU"
+ attribute \enum_value_00000000100 "LDST"
+ attribute \enum_value_00000001000 "SHIFT_ROT"
+ attribute \enum_value_00000010000 "LOGICAL"
+ attribute \enum_value_00000100000 "BRANCH"
+ attribute \enum_value_00001000000 "CR"
+ attribute \enum_value_00010000000 "TRAP"
+ attribute \enum_value_00100000000 "MUL"
+ attribute \enum_value_01000000000 "DIV"
+ attribute \enum_value_10000000000 "SPR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 11 output 11 \oper_i__fn_unit
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 output 12 \oper_i__invert_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 output 13 \oper_i__invert_out
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 13 \oper_i__zero_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 14 \oper_i__invert_out
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 15 \oper_i__write_cr0
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 2 output 14 \oper_i__input_carry
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 output 15 \oper_i__output_carry
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 output 16 \oper_i__input_cr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 output 17 \oper_i__output_cr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 2 output 16 \oper_i__input_carry
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 17 \oper_i__output_carry
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 output 18 \oper_i__is_32bit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 1 output 19 \oper_i__is_signed
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
wire width 4 output 20 \oper_i__data_len
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 output 21 \oper_i__byte_reverse
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/alu_input_record.py:35"
- wire width 1 output 22 \oper_i__sign_extend
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 output 21 \oper_i__insn
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
- wire width 64 output 23 \src1_i
+ wire width 64 output 22 \src1_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
- wire width 64 output 24 \src2_i
+ wire width 64 output 23 \src2_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
- wire width 1 output 25 \busy_o
+ wire width 1 output 24 \busy_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 4 output 26 \rd__rel
+ wire width 4 output 25 \rd__rel
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 5 output 27 \wr__rel
+ wire width 5 output 26 \wr__rel
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
- wire width 64 output 28 \dest1_o
+ wire width 64 output 27 \dest1_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 6 output 29 \rd__go$1
+ wire width 6 output 28 \rd__go$1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 3 output 30 \wr__go$2
+ wire width 3 output 29 \wr__go$2
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94"
- wire width 1 output 31 \issue_i$3
+ wire width 1 output 30 \issue_i$3
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
- wire width 1 input 32 \shadown_i$4
+ wire width 1 input 31 \shadown_i$4
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96"
- wire width 1 input 33 \go_die_i$5
- attribute \enum_base_type "InternalOp"
+ wire width 1 input 32 \go_die_i$5
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
- wire width 7 output 34 \oper_i__insn_type$6
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
- wire width 32 output 35 \oper_i__insn
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 7 output 33 \oper_i__insn_type$6
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00000000010 "ALU"
attribute \enum_value_00100000000 "MUL"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
- wire width 11 output 36 \oper_i__fn_unit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
- wire width 1 output 37 \oper_i__read_cr_whole
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/cr_input_record.py:21"
- wire width 1 output 38 \oper_i__write_cr_whole
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 11 output 34 \oper_i__fn_unit$7
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 output 35 \oper_i__insn$8
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 36 \oper_i__read_cr_whole
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 37 \oper_i__write_cr_whole
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
- wire width 64 output 39 \src1_i$7
+ wire width 64 output 38 \src1_i$9
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
- wire width 64 output 40 \src2_i$8
+ wire width 64 output 39 \src2_i$10
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
- wire width 1 output 41 \busy_o$9
+ wire width 1 output 40 \busy_o$11
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 6 output 42 \rd__rel$10
+ wire width 6 output 41 \rd__rel$12
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 3 output 43 \wr__rel$11
+ wire width 3 output 42 \wr__rel$13
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
- wire width 64 output 44 \dest1_o$12
+ wire width 64 output 43 \dest1_o$14
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 4 output 45 \rd__go$13
+ wire width 3 output 44 \rd__go$15
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 3 output 46 \wr__go$14
+ wire width 3 output 45 \wr__go$16
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94"
- wire width 1 output 47 \issue_i$15
+ wire width 1 output 46 \issue_i$17
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
- wire width 1 input 48 \shadown_i$16
+ wire width 1 input 47 \shadown_i$18
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96"
- wire width 1 input 49 \go_die_i$17
- attribute \enum_base_type "InternalOp"
+ wire width 1 input 48 \go_die_i$19
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 output 49 \oper_i__cia
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
- wire width 7 output 50 \oper_i__insn_type$18
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 7 output 50 \oper_i__insn_type$20
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00000000010 "ALU"
attribute \enum_value_00100000000 "MUL"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
- wire width 11 output 51 \oper_i__fn_unit$19
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
- wire width 1 output 52 \oper_i__lk$20
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
- wire width 1 output 53 \oper_i__is_32bit$21
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/br_input_record.py:26"
- wire width 32 output 54 \oper_i__insn$22
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 11 output 51 \oper_i__fn_unit$21
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 output 52 \oper_i__insn$22
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 53 \oper_i__lk
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 54 \oper_i__is_32bit$23
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
- wire width 64 output 55 \src1_i$23
+ wire width 64 output 55 \src1_i$24
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
- wire width 64 output 56 \src2_i$24
+ wire width 64 output 56 \src2_i$25
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
- wire width 1 output 57 \busy_o$25
+ wire width 1 output 57 \busy_o$26
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 4 output 58 \rd__rel$26
+ wire width 3 output 58 \rd__rel$27
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 3 output 59 \wr__rel$27
+ wire width 3 output 59 \wr__rel$28
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
- wire width 64 output 60 \dest1_o$28
+ wire width 64 output 60 \dest1_o$29
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 6 output 61 \rd__go$29
+ wire width 4 output 61 \rd__go$30
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 5 output 62 \wr__go$30
+ wire width 5 output 62 \wr__go$31
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94"
- wire width 1 output 63 \issue_i$31
+ wire width 1 output 63 \issue_i$32
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
- wire width 1 input 64 \shadown_i$32
+ wire width 1 input 64 \shadown_i$33
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96"
- wire width 1 input 65 \go_die_i$33
- attribute \enum_base_type "InternalOp"
+ wire width 1 input 65 \go_die_i$34
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
- wire width 7 output 66 \oper_i__insn_type$34
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
- wire width 32 output 67 \oper_i__insn$35
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 7 output 66 \oper_i__insn_type$35
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00000000010 "ALU"
attribute \enum_value_00100000000 "MUL"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
- wire width 11 output 68 \oper_i__fn_unit$36
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
- wire width 1 output 69 \oper_i__is_32bit$37
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
- wire width 5 output 70 \oper_i__traptype
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/trap_input_record.py:22"
- wire width 13 output 71 \oper_i__trapaddr
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 11 output 67 \oper_i__fn_unit$36
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 output 68 \oper_i__insn$37
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 output 69 \oper_i__msr
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 64 output 70 \oper_i__cia$38
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 71 \oper_i__is_32bit$39
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 5 output 72 \oper_i__traptype
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 13 output 73 \oper_i__trapaddr
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
- wire width 64 output 72 \src1_i$38
+ wire width 64 output 74 \src1_i$40
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
- wire width 64 output 73 \src2_i$39
+ wire width 64 output 75 \src2_i$41
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
- wire width 1 output 74 \busy_o$40
+ wire width 1 output 76 \busy_o$42
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 6 output 75 \rd__rel$41
+ wire width 4 output 77 \rd__rel$43
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 5 output 76 \wr__rel$42
+ wire width 5 output 78 \wr__rel$44
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
- wire width 64 output 77 \dest1_o$43
+ wire width 64 output 79 \dest1_o$45
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 2 output 78 \rd__go$44
+ wire width 2 output 80 \rd__go$46
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 3 output 79 \wr__go$45
+ wire width 3 output 81 \wr__go$47
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94"
- wire width 1 output 80 \issue_i$46
+ wire width 1 output 82 \issue_i$48
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
- wire width 1 input 81 \shadown_i$47
+ wire width 1 input 83 \shadown_i$49
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96"
- wire width 1 input 82 \go_die_i$48
- attribute \enum_base_type "InternalOp"
+ wire width 1 input 84 \go_die_i$50
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 7 output 83 \oper_i__insn_type$49
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 7 output 85 \oper_i__insn_type$51
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00000000010 "ALU"
attribute \enum_value_00100000000 "MUL"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 11 output 84 \oper_i__fn_unit$50
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 output 85 \oper_i__lk$51
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 output 86 \oper_i__invert_a$52
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 output 87 \oper_i__invert_out$53
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 11 output 86 \oper_i__fn_unit$52
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 87 \oper_i__invert_a$53
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 88 \oper_i__zero_a$54
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 2 output 88 \oper_i__input_carry$54
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 output 89 \oper_i__output_carry$55
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 output 90 \oper_i__is_32bit$56
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 1 output 91 \oper_i__is_signed$57
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/logical_input_record.py:32"
- wire width 4 output 92 \oper_i__data_len$58
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 2 output 89 \oper_i__input_carry$55
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 90 \oper_i__invert_out$56
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 91 \oper_i__write_cr0$57
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 92 \oper_i__output_carry$58
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 93 \oper_i__is_32bit$59
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 94 \oper_i__is_signed$60
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 4 output 95 \oper_i__data_len$61
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 output 96 \oper_i__insn$62
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
- wire width 64 output 93 \src1_i$59
+ wire width 64 output 97 \src1_i$63
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
- wire width 64 output 94 \src2_i$60
+ wire width 64 output 98 \src2_i$64
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
- wire width 1 output 95 \busy_o$61
+ wire width 1 output 99 \busy_o$65
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 2 output 96 \rd__rel$62
+ wire width 2 output 100 \rd__rel$66
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 3 output 97 \wr__rel$63
+ wire width 3 output 101 \wr__rel$67
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
- wire width 64 output 98 \dest1_o$64
+ wire width 64 output 102 \dest1_o$68
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 6 output 99 \rd__go$65
+ wire width 6 output 103 \rd__go$69
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 6 output 100 \wr__go$66
+ wire width 6 output 104 \wr__go$70
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94"
- wire width 1 output 101 \issue_i$67
+ wire width 1 output 105 \issue_i$71
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
- wire width 1 input 102 \shadown_i$68
+ wire width 1 input 106 \shadown_i$72
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96"
- wire width 1 input 103 \go_die_i$69
- attribute \enum_base_type "InternalOp"
+ wire width 1 input 107 \go_die_i$73
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20"
- wire width 7 output 104 \oper_i__insn_type$70
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20"
- wire width 32 output 105 \oper_i__insn$71
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 7 output 108 \oper_i__insn_type$74
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00000000010 "ALU"
attribute \enum_value_00100000000 "MUL"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20"
- wire width 11 output 106 \oper_i__fn_unit$72
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/spr_input_record.py:20"
- wire width 1 output 107 \oper_i__is_32bit$73
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 11 output 109 \oper_i__fn_unit$75
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 output 110 \oper_i__insn$76
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 111 \oper_i__is_32bit$77
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
- wire width 64 output 108 \src1_i$74
+ wire width 64 output 112 \src1_i$78
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
- wire width 64 output 109 \src2_i$75
+ wire width 64 output 113 \src2_i$79
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
- wire width 1 output 110 \busy_o$76
+ wire width 1 output 114 \busy_o$80
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 6 output 111 \rd__rel$77
+ wire width 6 output 115 \rd__rel$81
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 6 output 112 \wr__rel$78
+ wire width 6 output 116 \wr__rel$82
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
- wire width 64 output 113 \dest1_o$79
+ wire width 64 output 117 \dest1_o$83
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 4 output 114 \rd__go$80
+ wire width 3 output 118 \rd__go$84
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 3 output 115 \wr__go$81
+ wire width 4 output 119 \wr__go$85
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94"
- wire width 1 output 116 \issue_i$82
+ wire width 1 output 120 \issue_i$86
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
- wire width 1 input 117 \shadown_i$83
+ wire width 1 input 121 \shadown_i$87
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96"
- wire width 1 input 118 \go_die_i$84
- attribute \enum_base_type "InternalOp"
+ wire width 1 input 122 \go_die_i$88
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 7 output 119 \oper_i__insn_type$85
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 7 output 123 \oper_i__insn_type$89
+ attribute \enum_base_type "Function"
+ attribute \enum_value_00000000000 "NONE"
+ attribute \enum_value_00000000010 "ALU"
+ attribute \enum_value_00000000100 "LDST"
+ attribute \enum_value_00000001000 "SHIFT_ROT"
+ attribute \enum_value_00000010000 "LOGICAL"
+ attribute \enum_value_00000100000 "BRANCH"
+ attribute \enum_value_00001000000 "CR"
+ attribute \enum_value_00010000000 "TRAP"
+ attribute \enum_value_00100000000 "MUL"
+ attribute \enum_value_01000000000 "DIV"
+ attribute \enum_value_10000000000 "SPR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 11 output 124 \oper_i__fn_unit$90
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 125 \oper_i__invert_a$91
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 126 \oper_i__zero_a$92
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 127 \oper_i__invert_out$93
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 128 \oper_i__write_cr0$94
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 129 \oper_i__is_32bit$95
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 130 \oper_i__is_signed$96
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 output 131 \oper_i__insn$97
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
+ wire width 64 output 132 \src1_i$98
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
+ wire width 64 output 133 \src2_i$99
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
+ wire width 1 output 134 \busy_o$100
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+ wire width 3 output 135 \rd__rel$101
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+ wire width 4 output 136 \wr__rel$102
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
+ wire width 64 output 137 \dest1_o$103
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+ wire width 4 output 138 \rd__go$104
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+ wire width 3 output 139 \wr__go$105
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94"
+ wire width 1 output 140 \issue_i$106
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
+ wire width 1 input 141 \shadown_i$107
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96"
+ wire width 1 input 142 \go_die_i$108
+ attribute \enum_base_type "MicrOp"
+ attribute \enum_value_0000000 "OP_ILLEGAL"
+ attribute \enum_value_0000001 "OP_NOP"
+ attribute \enum_value_0000010 "OP_ADD"
+ attribute \enum_value_0000011 "OP_ADDPCIS"
+ attribute \enum_value_0000100 "OP_AND"
+ attribute \enum_value_0000101 "OP_ATTN"
+ attribute \enum_value_0000110 "OP_B"
+ attribute \enum_value_0000111 "OP_BC"
+ attribute \enum_value_0001000 "OP_BCREG"
+ attribute \enum_value_0001001 "OP_BPERM"
+ attribute \enum_value_0001010 "OP_CMP"
+ attribute \enum_value_0001011 "OP_CMPB"
+ attribute \enum_value_0001100 "OP_CMPEQB"
+ attribute \enum_value_0001101 "OP_CMPRB"
+ attribute \enum_value_0001110 "OP_CNTZ"
+ attribute \enum_value_0001111 "OP_CRAND"
+ attribute \enum_value_0010000 "OP_CRANDC"
+ attribute \enum_value_0010001 "OP_CREQV"
+ attribute \enum_value_0010010 "OP_CRNAND"
+ attribute \enum_value_0010011 "OP_CRNOR"
+ attribute \enum_value_0010100 "OP_CROR"
+ attribute \enum_value_0010101 "OP_CRORC"
+ attribute \enum_value_0010110 "OP_CRXOR"
+ attribute \enum_value_0010111 "OP_DARN"
+ attribute \enum_value_0011000 "OP_DCBF"
+ attribute \enum_value_0011001 "OP_DCBST"
+ attribute \enum_value_0011010 "OP_DCBT"
+ attribute \enum_value_0011011 "OP_DCBTST"
+ attribute \enum_value_0011100 "OP_DCBZ"
+ attribute \enum_value_0011101 "OP_DIV"
+ attribute \enum_value_0011110 "OP_DIVE"
+ attribute \enum_value_0011111 "OP_EXTS"
+ attribute \enum_value_0100000 "OP_EXTSWSLI"
+ attribute \enum_value_0100001 "OP_ICBI"
+ attribute \enum_value_0100010 "OP_ICBT"
+ attribute \enum_value_0100011 "OP_ISEL"
+ attribute \enum_value_0100100 "OP_ISYNC"
+ attribute \enum_value_0100101 "OP_LOAD"
+ attribute \enum_value_0100110 "OP_STORE"
+ attribute \enum_value_0100111 "OP_MADDHD"
+ attribute \enum_value_0101000 "OP_MADDHDU"
+ attribute \enum_value_0101001 "OP_MADDLD"
+ attribute \enum_value_0101010 "OP_MCRF"
+ attribute \enum_value_0101011 "OP_MCRXR"
+ attribute \enum_value_0101100 "OP_MCRXRX"
+ attribute \enum_value_0101101 "OP_MFCR"
+ attribute \enum_value_0101110 "OP_MFSPR"
+ attribute \enum_value_0101111 "OP_MOD"
+ attribute \enum_value_0110000 "OP_MTCRF"
+ attribute \enum_value_0110001 "OP_MTSPR"
+ attribute \enum_value_0110010 "OP_MUL_L64"
+ attribute \enum_value_0110011 "OP_MUL_H64"
+ attribute \enum_value_0110100 "OP_MUL_H32"
+ attribute \enum_value_0110101 "OP_OR"
+ attribute \enum_value_0110110 "OP_POPCNT"
+ attribute \enum_value_0110111 "OP_PRTY"
+ attribute \enum_value_0111000 "OP_RLC"
+ attribute \enum_value_0111001 "OP_RLCL"
+ attribute \enum_value_0111010 "OP_RLCR"
+ attribute \enum_value_0111011 "OP_SETB"
+ attribute \enum_value_0111100 "OP_SHL"
+ attribute \enum_value_0111101 "OP_SHR"
+ attribute \enum_value_0111110 "OP_SYNC"
+ attribute \enum_value_0111111 "OP_TRAP"
+ attribute \enum_value_1000011 "OP_XOR"
+ attribute \enum_value_1000100 "OP_SIM_CONFIG"
+ attribute \enum_value_1000101 "OP_CROP"
+ attribute \enum_value_1000110 "OP_RFID"
+ attribute \enum_value_1000111 "OP_MFMSR"
+ attribute \enum_value_1001000 "OP_MTMSRD"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 7 output 143 \oper_i__insn_type$109
+ attribute \enum_base_type "Function"
+ attribute \enum_value_00000000000 "NONE"
+ attribute \enum_value_00000000010 "ALU"
+ attribute \enum_value_00000000100 "LDST"
+ attribute \enum_value_00000001000 "SHIFT_ROT"
+ attribute \enum_value_00000010000 "LOGICAL"
+ attribute \enum_value_00000100000 "BRANCH"
+ attribute \enum_value_00001000000 "CR"
+ attribute \enum_value_00010000000 "TRAP"
+ attribute \enum_value_00100000000 "MUL"
+ attribute \enum_value_01000000000 "DIV"
+ attribute \enum_value_10000000000 "SPR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 11 output 144 \oper_i__fn_unit$110
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 2 output 120 \oper_i__input_carry$86
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 output 121 \oper_i__output_carry$87
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 output 122 \oper_i__input_cr$88
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 output 123 \oper_i__output_cr$89
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 output 124 \oper_i__is_32bit$90
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/sr_input_record.py:29"
- wire width 1 output 125 \oper_i__is_signed$91
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 2 output 146 \oper_i__input_carry$111
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 147 \oper_i__output_carry$112
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 148 \oper_i__input_cr
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 149 \oper_i__output_cr
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 150 \oper_i__is_32bit$113
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 151 \oper_i__is_signed$114
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 32 output 152 \oper_i__insn$115
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
- wire width 64 output 126 \src1_i$92
+ wire width 64 output 153 \src1_i$116
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
- wire width 64 output 127 \src2_i$93
+ wire width 64 output 154 \src2_i$117
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
- wire width 1 output 128 \busy_o$94
+ wire width 1 output 155 \busy_o$118
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 4 output 129 \rd__rel$95
+ wire width 4 output 156 \rd__rel$119
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 3 output 130 \wr__rel$96
+ wire width 3 output 157 \wr__rel$120
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:81"
- wire width 64 output 131 \dest1_o$97
+ wire width 64 output 158 \dest1_o$121
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 3 output 132 \rd__go$98
+ wire width 3 output 159 \rd__go$122
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 1 output 133 \ad__go
+ wire width 1 output 160 \ad__go
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 2 output 134 \wr__go$99
+ wire width 2 output 161 \wr__go$123
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 1 output 135 \st__go
+ wire width 1 output 162 \st__go
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:94"
- wire width 1 output 136 \issue_i$100
+ wire width 1 output 163 \issue_i$124
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
- wire width 1 input 137 \shadown_i$101
+ wire width 1 input 164 \shadown_i$125
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96"
- wire width 1 input 138 \go_die_i$102
- attribute \enum_base_type "InternalOp"
+ wire width 1 input 165 \go_die_i$126
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
- wire width 7 output 139 \oper_i__insn_type$103
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
- wire width 1 output 140 \oper_i__is_32bit$104
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
- wire width 1 output 141 \oper_i__zero_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
- wire width 1 output 142 \oper_i__is_signed$105
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
- wire width 4 output 143 \oper_i__data_len$106
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
- wire width 1 output 144 \oper_i__byte_reverse$107
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
- wire width 1 output 145 \oper_i__sign_extend$108
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/ldst/ldst_input_record.py:24"
- wire width 1 output 146 \oper_i__update
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 7 output 166 \oper_i__insn_type$127
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 167 \oper_i__zero_a$128
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 168 \oper_i__is_32bit$129
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 169 \oper_i__is_signed$130
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 4 output 170 \oper_i__data_len$131
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 171 \oper_i__byte_reverse
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 1 output 172 \oper_i__sign_extend
+ attribute \enum_base_type "LDSTMode"
+ attribute \enum_value_00 "NONE"
+ attribute \enum_value_01 "update"
+ attribute \enum_value_10 "cix"
+ attribute \enum_value_11 "cx"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:12"
+ wire width 2 output 173 \oper_i__ldst_mode
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
- wire width 64 output 147 \src1_i$109
+ wire width 64 output 174 \src1_i$132
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
- wire width 64 output 148 \src2_i$110
+ wire width 64 output 175 \src2_i$133
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:69"
- wire width 64 output 149 \src3_i
+ wire width 64 output 176 \src3_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
- wire width 1 output 150 \busy_o$111
+ wire width 1 output 177 \busy_o$134
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 3 output 151 \rd__rel$112
+ wire width 3 output 178 \rd__rel$135
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 1 output 152 \ad__rel
+ wire width 1 output 179 \ad__rel
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 1 output 153 \st__rel
+ wire width 1 output 180 \st__rel
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
- wire width 2 output 154 \wr__rel$113
+ wire width 2 output 181 \wr__rel$136
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 output 155 \o
+ wire width 64 output 182 \o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 input 156 \o_ok
+ wire width 1 input 183 \o_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 output 157 \ea
+ wire width 64 output 184 \ea
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 input 158 \ea_ok
+ wire width 1 input 185 \ea_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:112"
- wire width 1 output 159 \load_mem_o
+ wire width 1 output 186 \load_mem_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:113"
- wire width 1 output 160 \stwd_mem_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:318"
- wire width 32 output 161 \raw_opcode_in
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:319"
- wire width 1 output 162 \bigendian
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:219"
- wire width 32 output 163 \opcode_in
+ wire width 1 output 187 \stwd_mem_o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:328"
+ wire width 32 output 188 \raw_opcode_in
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:329"
+ wire width 1 input 189 \bigendian
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:229"
+ wire width 32 output 190 \opcode_in
attribute \enum_base_type "Function"
attribute \enum_value_00000000000 "NONE"
attribute \enum_value_00000000010 "ALU"
attribute \enum_value_01000000000 "DIV"
attribute \enum_value_10000000000 "SPR"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:119"
- wire width 11 output 164 \function_unit
+ wire width 11 output 191 \function_unit
attribute \enum_base_type "In1Sel"
attribute \enum_value_000 "NONE"
attribute \enum_value_001 "RA"
attribute \enum_value_011 "SPR"
attribute \enum_value_100 "RS"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:124"
- wire width 3 output 165 \in1_sel
+ wire width 3 output 192 \in1_sel
attribute \enum_base_type "In2Sel"
attribute \enum_value_0000 "NONE"
attribute \enum_value_0001 "RB"
attribute \enum_value_1100 "SPR"
attribute \enum_value_1101 "RS"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:125"
- wire width 4 output 166 \in2_sel
+ wire width 4 output 193 \in2_sel
attribute \enum_base_type "In3Sel"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "RS"
attribute \enum_value_10 "RB"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:126"
- wire width 2 output 167 \in3_sel
+ wire width 2 output 194 \in3_sel
attribute \enum_base_type "OutSel"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "RT"
attribute \enum_value_10 "RA"
attribute \enum_value_11 "SPR"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:127"
- wire width 2 output 168 \out_sel
+ wire width 2 output 195 \out_sel
attribute \enum_base_type "CRInSel"
attribute \enum_value_000 "NONE"
attribute \enum_value_001 "CR0"
attribute \enum_value_101 "BC"
attribute \enum_value_110 "WHOLE_REG"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:128"
- wire width 3 output 169 \cr_in
+ wire width 3 output 196 \cr_in
attribute \enum_base_type "CROutSel"
attribute \enum_value_000 "NONE"
attribute \enum_value_001 "CR0"
attribute \enum_value_011 "BT"
attribute \enum_value_100 "WHOLE_REG"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:129"
- wire width 3 output 170 \cr_out
+ wire width 3 output 197 \cr_out
attribute \enum_base_type "LdstLen"
attribute \enum_value_0000 "NONE"
attribute \enum_value_0001 "is1B"
attribute \enum_value_0100 "is4B"
attribute \enum_value_1000 "is8B"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:130"
- wire width 4 output 171 \ldst_len
+ wire width 4 output 198 \ldst_len
attribute \enum_base_type "RC"
attribute \enum_value_00 "NONE"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "RC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:131"
- wire width 2 output 172 \rc_sel
- attribute \enum_base_type "InternalOp"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:132"
+ wire width 2 output 199 \rc_sel
+ attribute \enum_base_type "MicrOp"
attribute \enum_value_0000000 "OP_ILLEGAL"
attribute \enum_value_0000001 "OP_NOP"
attribute \enum_value_0000010 "OP_ADD"
attribute \enum_value_1000111 "OP_MFMSR"
attribute \enum_value_1001000 "OP_MTMSRD"
attribute \enum_value_1001001 "OP_SC"
+ attribute \enum_value_1001010 "OP_MTMSR"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:120"
- wire width 7 output 173 \internal_op
+ wire width 7 output 200 \internal_op
attribute \enum_base_type "Form"
attribute \enum_value_00000 "NONE"
attribute \enum_value_00001 "I"
attribute \enum_value_11011 "Z22"
attribute \enum_value_11100 "Z23"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:121"
- wire width 5 output 174 \form
+ wire width 5 output 201 \form
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:123"
- wire width 8 output 175 \asmcode
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 176 \inv_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 177 \inv_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 178 \cry_out
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 179 \br
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 180 \sgn_ext
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 181 \upd
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 182 \rsrv
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 183 \is_32b
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 184 \sgn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 185 \lk
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:135"
- wire width 1 output 186 \sgl_pipe
- attribute \enum_base_type "InternalOp"
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- attribute \enum_value_0000010 "OP_ADD"
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- attribute \enum_value_0000100 "OP_AND"
- attribute \enum_value_0000101 "OP_ATTN"
- attribute \enum_value_0000110 "OP_B"
- attribute \enum_value_0000111 "OP_BC"
- attribute \enum_value_0001000 "OP_BCREG"
- attribute \enum_value_0001001 "OP_BPERM"
- attribute \enum_value_0001010 "OP_CMP"
- attribute \enum_value_0001011 "OP_CMPB"
- attribute \enum_value_0001100 "OP_CMPEQB"
- attribute \enum_value_0001101 "OP_CMPRB"
- attribute \enum_value_0001110 "OP_CNTZ"
- attribute \enum_value_0001111 "OP_CRAND"
- attribute \enum_value_0010000 "OP_CRANDC"
- attribute \enum_value_0010001 "OP_CREQV"
- attribute \enum_value_0010010 "OP_CRNAND"
- attribute \enum_value_0010011 "OP_CRNOR"
- attribute \enum_value_0010100 "OP_CROR"
- attribute \enum_value_0010101 "OP_CRORC"
- attribute \enum_value_0010110 "OP_CRXOR"
- attribute \enum_value_0010111 "OP_DARN"
- attribute \enum_value_0011000 "OP_DCBF"
- attribute \enum_value_0011001 "OP_DCBST"
- attribute \enum_value_0011010 "OP_DCBT"
- attribute \enum_value_0011011 "OP_DCBTST"
- attribute \enum_value_0011100 "OP_DCBZ"
- attribute \enum_value_0011101 "OP_DIV"
- attribute \enum_value_0011110 "OP_DIVE"
- attribute \enum_value_0011111 "OP_EXTS"
- attribute \enum_value_0100000 "OP_EXTSWSLI"
- attribute \enum_value_0100001 "OP_ICBI"
- attribute \enum_value_0100010 "OP_ICBT"
- attribute \enum_value_0100011 "OP_ISEL"
- attribute \enum_value_0100100 "OP_ISYNC"
- attribute \enum_value_0100101 "OP_LOAD"
- attribute \enum_value_0100110 "OP_STORE"
- attribute \enum_value_0100111 "OP_MADDHD"
- attribute \enum_value_0101000 "OP_MADDHDU"
- attribute \enum_value_0101001 "OP_MADDLD"
- attribute \enum_value_0101010 "OP_MCRF"
- attribute \enum_value_0101011 "OP_MCRXR"
- attribute \enum_value_0101100 "OP_MCRXRX"
- attribute \enum_value_0101101 "OP_MFCR"
- attribute \enum_value_0101110 "OP_MFSPR"
- attribute \enum_value_0101111 "OP_MOD"
- attribute \enum_value_0110000 "OP_MTCRF"
- attribute \enum_value_0110001 "OP_MTSPR"
- attribute \enum_value_0110010 "OP_MUL_L64"
- attribute \enum_value_0110011 "OP_MUL_H64"
- attribute \enum_value_0110100 "OP_MUL_H32"
- attribute \enum_value_0110101 "OP_OR"
- attribute \enum_value_0110110 "OP_POPCNT"
- attribute \enum_value_0110111 "OP_PRTY"
- attribute \enum_value_0111000 "OP_RLC"
- attribute \enum_value_0111001 "OP_RLCL"
- attribute \enum_value_0111010 "OP_RLCR"
- attribute \enum_value_0111011 "OP_SETB"
- attribute \enum_value_0111100 "OP_SHL"
- attribute \enum_value_0111101 "OP_SHR"
- attribute \enum_value_0111110 "OP_SYNC"
- attribute \enum_value_0111111 "OP_TRAP"
- attribute \enum_value_1000011 "OP_XOR"
- attribute \enum_value_1000100 "OP_SIM_CONFIG"
- attribute \enum_value_1000101 "OP_CROP"
- attribute \enum_value_1000110 "OP_RFID"
- attribute \enum_value_1000111 "OP_MFMSR"
- attribute \enum_value_1001000 "OP_MTMSRD"
- attribute \enum_value_1001001 "OP_SC"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:32"
- wire width 7 output 187 \insn_type
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- attribute \enum_value_00000000010 "ALU"
- attribute \enum_value_00000000100 "LDST"
- attribute \enum_value_00000001000 "SHIFT_ROT"
- attribute \enum_value_00000010000 "LOGICAL"
- attribute \enum_value_00000100000 "BRANCH"
- attribute \enum_value_00001000000 "CR"
- attribute \enum_value_00010000000 "TRAP"
- attribute \enum_value_00100000000 "MUL"
- attribute \enum_value_01000000000 "DIV"
- attribute \enum_value_10000000000 "SPR"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:33"
- wire width 11 output 188 \fn_unit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:35"
- wire width 8 output 189 \asmcode$114
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:36"
- wire width 64 output 190 \nia
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 5 output 191 \rego
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 192 \rego_ok
+ wire width 8 output 202 \asmcode
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 203 \inv_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 204 \inv_out
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 205 \cry_out
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 206 \br
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 207 \sgn_ext
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 208 \rsrv
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 209 \is_32b
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 210 \sgn
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 211 \lk
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:136"
+ wire width 1 output 212 \sgl_pipe
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:71"
+ wire width 8 output 213 \asmcode$137
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 5 output 193 \ea$115
+ wire width 5 output 214 \rego
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 194 \ea_ok$116
+ wire width 1 output 215 \rego_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 5 output 195 \reg1
+ wire width 5 output 216 \ea$138
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 196 \reg1_ok
+ wire width 1 output 217 \ea_ok$139
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 5 output 197 \reg2
+ wire width 5 output 218 \reg1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 198 \reg2_ok
+ wire width 1 output 219 \reg1_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 5 output 199 \reg3
+ wire width 5 output 220 \reg2
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 200 \reg3_ok
+ wire width 1 output 221 \reg2_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 output 201 \imm
+ wire width 5 output 222 \reg3
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 202 \imm_ok
+ wire width 1 output 223 \reg3_ok
attribute \enum_base_type "SPR"
attribute \enum_value_0000000001 "XER"
attribute \enum_value_0000000011 "DSCR"
attribute \enum_value_1110000010 "PPR32"
attribute \enum_value_1111111111 "PIR"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 10 output 203 \spro
+ wire width 10 output 224 \spro
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 204 \spro_ok
+ wire width 1 output 225 \spro_ok
attribute \enum_base_type "SPR"
attribute \enum_value_0000000001 "XER"
attribute \enum_value_0000000011 "DSCR"
attribute \enum_value_1110000010 "PPR32"
attribute \enum_value_1111111111 "PIR"
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 10 output 205 \spr1
+ wire width 10 output 226 \spr1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 206 \spr1_ok
+ wire width 1 output 227 \spr1_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:81"
+ wire width 1 output 228 \xer_in
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:82"
+ wire width 1 output 229 \xer_out
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 3 output 207 \fast1
+ wire width 3 output 230 \fast1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 208 \fast1_ok
+ wire width 1 output 231 \fast1_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 3 output 209 \fast2
+ wire width 3 output 232 \fast2
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 210 \fast2_ok
+ wire width 1 output 233 \fast2_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 3 output 211 \fasto1
+ wire width 3 output 234 \fasto1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 212 \fasto1_ok
+ wire width 1 output 235 \fasto1_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 3 output 213 \fasto2
+ wire width 3 output 236 \fasto2
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 214 \fasto2_ok
+ wire width 1 output 237 \fasto2_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 3 output 215 \cr_in1
+ wire width 3 output 238 \cr_in1
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 216 \cr_in1_ok
+ wire width 1 output 239 \cr_in1_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 3 output 217 \cr_in2
+ wire width 3 output 240 \cr_in2
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 218 \cr_in2_ok
+ wire width 1 output 241 \cr_in2_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 3 output 219 \cr_in2$117
+ wire width 3 output 242 \cr_in2$140
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 220 \cr_in2_ok$118
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:55"
- wire width 1 output 221 \read_cr_whole
+ wire width 1 output 243 \cr_in2_ok$141
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 3 output 244 \cr_out$142
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
+ wire width 1 output 245 \cr_out_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:33"
+ wire width 64 output 246 \msr
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:34"
+ wire width 64 output 247 \cia
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:37"
+ wire width 32 output 248 \insn
+ attribute \enum_base_type "MicrOp"
+ attribute \enum_value_0000000 "OP_ILLEGAL"
+ attribute \enum_value_0000001 "OP_NOP"
+ attribute \enum_value_0000010 "OP_ADD"
+ attribute \enum_value_0000011 "OP_ADDPCIS"
+ attribute \enum_value_0000100 "OP_AND"
+ attribute \enum_value_0000101 "OP_ATTN"
+ attribute \enum_value_0000110 "OP_B"
+ attribute \enum_value_0000111 "OP_BC"
+ attribute \enum_value_0001000 "OP_BCREG"
+ attribute \enum_value_0001001 "OP_BPERM"
+ attribute \enum_value_0001010 "OP_CMP"
+ attribute \enum_value_0001011 "OP_CMPB"
+ attribute \enum_value_0001100 "OP_CMPEQB"
+ attribute \enum_value_0001101 "OP_CMPRB"
+ attribute \enum_value_0001110 "OP_CNTZ"
+ attribute \enum_value_0001111 "OP_CRAND"
+ attribute \enum_value_0010000 "OP_CRANDC"
+ attribute \enum_value_0010001 "OP_CREQV"
+ attribute \enum_value_0010010 "OP_CRNAND"
+ attribute \enum_value_0010011 "OP_CRNOR"
+ attribute \enum_value_0010100 "OP_CROR"
+ attribute \enum_value_0010101 "OP_CRORC"
+ attribute \enum_value_0010110 "OP_CRXOR"
+ attribute \enum_value_0010111 "OP_DARN"
+ attribute \enum_value_0011000 "OP_DCBF"
+ attribute \enum_value_0011001 "OP_DCBST"
+ attribute \enum_value_0011010 "OP_DCBT"
+ attribute \enum_value_0011011 "OP_DCBTST"
+ attribute \enum_value_0011100 "OP_DCBZ"
+ attribute \enum_value_0011101 "OP_DIV"
+ attribute \enum_value_0011110 "OP_DIVE"
+ attribute \enum_value_0011111 "OP_EXTS"
+ attribute \enum_value_0100000 "OP_EXTSWSLI"
+ attribute \enum_value_0100001 "OP_ICBI"
+ attribute \enum_value_0100010 "OP_ICBT"
+ attribute \enum_value_0100011 "OP_ISEL"
+ attribute \enum_value_0100100 "OP_ISYNC"
+ attribute \enum_value_0100101 "OP_LOAD"
+ attribute \enum_value_0100110 "OP_STORE"
+ attribute \enum_value_0100111 "OP_MADDHD"
+ attribute \enum_value_0101000 "OP_MADDHDU"
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+ attribute \enum_value_0101010 "OP_MCRF"
+ attribute \enum_value_0101011 "OP_MCRXR"
+ attribute \enum_value_0101100 "OP_MCRXRX"
+ attribute \enum_value_0101101 "OP_MFCR"
+ attribute \enum_value_0101110 "OP_MFSPR"
+ attribute \enum_value_0101111 "OP_MOD"
+ attribute \enum_value_0110000 "OP_MTCRF"
+ attribute \enum_value_0110001 "OP_MTSPR"
+ attribute \enum_value_0110010 "OP_MUL_L64"
+ attribute \enum_value_0110011 "OP_MUL_H64"
+ attribute \enum_value_0110100 "OP_MUL_H32"
+ attribute \enum_value_0110101 "OP_OR"
+ attribute \enum_value_0110110 "OP_POPCNT"
+ attribute \enum_value_0110111 "OP_PRTY"
+ attribute \enum_value_0111000 "OP_RLC"
+ attribute \enum_value_0111001 "OP_RLCL"
+ attribute \enum_value_0111010 "OP_RLCR"
+ attribute \enum_value_0111011 "OP_SETB"
+ attribute \enum_value_0111100 "OP_SHL"
+ attribute \enum_value_0111101 "OP_SHR"
+ attribute \enum_value_0111110 "OP_SYNC"
+ attribute \enum_value_0111111 "OP_TRAP"
+ attribute \enum_value_1000011 "OP_XOR"
+ attribute \enum_value_1000100 "OP_SIM_CONFIG"
+ attribute \enum_value_1000101 "OP_CROP"
+ attribute \enum_value_1000110 "OP_RFID"
+ attribute \enum_value_1000111 "OP_MFMSR"
+ attribute \enum_value_1001000 "OP_MTMSRD"
+ attribute \enum_value_1001001 "OP_SC"
+ attribute \enum_value_1001010 "OP_MTMSR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:38"
+ wire width 7 output 249 \insn_type
+ attribute \enum_base_type "Function"
+ attribute \enum_value_00000000000 "NONE"
+ attribute \enum_value_00000000010 "ALU"
+ attribute \enum_value_00000000100 "LDST"
+ attribute \enum_value_00000001000 "SHIFT_ROT"
+ attribute \enum_value_00000010000 "LOGICAL"
+ attribute \enum_value_00000100000 "BRANCH"
+ attribute \enum_value_00001000000 "CR"
+ attribute \enum_value_00010000000 "TRAP"
+ attribute \enum_value_00100000000 "MUL"
+ attribute \enum_value_01000000000 "DIV"
+ attribute \enum_value_10000000000 "SPR"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:39"
+ wire width 11 output 250 \fn_unit
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 3 output 222 \cr_out$119
+ wire width 64 output 251 \imm
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 223 \cr_out_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:57"
- wire width 1 output 224 \write_cr_whole
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:58"
- wire width 1 output 225 \lk$120
+ wire width 1 output 252 \imm_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:41"
+ wire width 1 output 253 \lk$143
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 226 \rc
+ wire width 1 output 254 \rc
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 227 \rc_ok
+ wire width 1 output 255 \rc_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 228 \oe
+ wire width 1 output 256 \oe
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 229 \oe_ok
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:61"
- wire width 1 output 230 \invert_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:62"
- wire width 1 output 231 \zero_a
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:63"
- wire width 1 output 232 \invert_out
+ wire width 1 output 257 \oe_ok
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:44"
+ wire width 1 output 258 \invert_a
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:45"
+ wire width 1 output 259 \zero_a
attribute \enum_base_type "CryIn"
attribute \enum_value_00 "ZERO"
attribute \enum_value_01 "ONE"
attribute \enum_value_10 "CA"
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:64"
- wire width 2 output 233 \input_carry
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:65"
- wire width 1 output 234 \output_carry
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:66"
- wire width 1 output 235 \input_cr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:67"
- wire width 1 output 236 \output_cr
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:68"
- wire width 1 output 237 \is_32bit
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:69"
- wire width 1 output 238 \is_signed
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:70"
- wire width 32 output 239 \insn
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:71"
- wire width 4 output 240 \data_len
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:72"
- wire width 1 output 241 \byte_reverse
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:73"
- wire width 1 output 242 \sign_extend
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:74"
- wire width 1 output 243 \update
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:75"
- wire width 5 output 244 \traptype
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:76"
- wire width 13 output 245 \trapaddr
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:46"
+ wire width 2 output 260 \input_carry
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47"
+ wire width 1 output 261 \output_carry
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48"
+ wire width 1 output 262 \input_cr
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:49"
+ wire width 1 output 263 \output_cr
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:50"
+ wire width 1 output 264 \invert_out
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:51"
+ wire width 1 output 265 \is_32bit
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:52"
+ wire width 1 output 266 \is_signed
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53"
+ wire width 4 output 267 \data_len
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:54"
+ wire width 1 output 268 \byte_reverse
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:55"
+ wire width 1 output 269 \sign_extend
+ attribute \enum_base_type "LDSTMode"
+ attribute \enum_value_00 "NONE"
+ attribute \enum_value_01 "update"
+ attribute \enum_value_10 "cix"
+ attribute \enum_value_11 "cx"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:56"
+ wire width 2 output 270 \ldst_mode
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:57"
+ wire width 5 output 271 \traptype
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:58"
+ wire width 13 output 272 \trapaddr
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:59"
+ wire width 1 output 273 \read_cr_whole
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:60"
+ wire width 1 output 274 \write_cr_whole
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:61"
+ wire width 1 output 275 \write_cr0
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:95"
- wire width 1 output 246 \ldst_port0_is_ld_i
+ wire width 1 output 276 \ldst_port0_is_ld_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:96"
- wire width 1 output 247 \ldst_port0_is_st_i
+ wire width 1 output 277 \ldst_port0_is_st_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99"
- wire width 4 output 248 \ldst_port0_data_len
+ wire width 4 output 278 \ldst_port0_data_len
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102"
- wire width 1 output 249 \ldst_port0_busy_o
+ wire width 1 output 279 \ldst_port0_busy_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:103"
- wire width 1 output 250 \ldst_port0_go_die_i
+ wire width 1 output 280 \ldst_port0_go_die_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 48 output 251 \ldst_port0_addr_i
+ wire width 48 output 281 \ldst_port0_addr_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 252 \ldst_port0_addr_i_ok
+ wire width 1 output 282 \ldst_port0_addr_i_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:106"
- wire width 1 output 253 \ldst_port0_addr_ok_o
+ wire width 1 output 283 \ldst_port0_addr_ok_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:107"
- wire width 1 input 254 \ldst_port0_addr_exc_o
+ wire width 1 input 284 \ldst_port0_addr_exc_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 output 255 \ldst_port0_ld_data_o
+ wire width 64 output 285 \ldst_port0_ld_data_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 256 \ldst_port0_ld_data_o_ok
+ wire width 1 output 286 \ldst_port0_ld_data_o_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 output 257 \ldst_port0_st_data_i
+ wire width 64 output 287 \ldst_port0_st_data_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 258 \ldst_port0_st_data_i_ok
+ wire width 1 output 288 \ldst_port0_st_data_i_ok
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:26"
- wire width 48 output 259 \x_addr_i
+ wire width 48 output 289 \x_addr_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:27"
- wire width 8 output 260 \x_mask_i
+ wire width 8 output 290 \x_mask_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:28"
- wire width 1 output 261 \x_ld_i
+ wire width 1 output 291 \x_ld_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:29"
- wire width 1 output 262 \x_st_i
+ wire width 1 output 292 \x_st_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:30"
- wire width 64 output 263 \x_st_data_i
+ wire width 64 output 293 \x_st_data_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32"
- wire width 1 input 264 \x_stall_i
+ wire width 1 input 294 \x_stall_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:33"
- wire width 1 output 265 \x_valid_i
+ wire width 1 output 295 \x_valid_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:36"
- wire width 1 input 266 \m_stall_i
+ wire width 1 input 296 \m_stall_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:37"
- wire width 1 output 267 \m_valid_i
+ wire width 1 output 297 \m_valid_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:42"
- wire width 1 output 268 \x_busy_o
+ wire width 1 output 298 \x_busy_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:43"
- wire width 1 output 269 \m_busy_o
+ wire width 1 output 299 \m_busy_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:45"
- wire width 64 output 270 \m_ld_data_o
+ wire width 64 output 300 \m_ld_data_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:50"
- wire width 1 output 271 \m_load_err_o
+ wire width 1 output 301 \m_load_err_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:51"
- wire width 1 output 272 \m_store_err_o
+ wire width 1 output 302 \m_store_err_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:52"
- wire width 45 output 273 \m_badaddr_o
+ wire width 45 output 303 \m_badaddr_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
- wire width 45 output 274 \dbus__adr
+ wire width 45 output 304 \dbus__adr
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
- wire width 64 output 275 \dbus__dat_w
+ wire width 64 output 305 \dbus__dat_w
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
- wire width 64 input 276 \dbus__dat_r
+ wire width 64 input 306 \dbus__dat_r
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
- wire width 8 output 277 \dbus__sel
+ wire width 8 output 307 \dbus__sel
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
- wire width 1 output 278 \dbus__cyc
+ wire width 1 output 308 \dbus__cyc
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
- wire width 1 output 279 \dbus__stb
+ wire width 1 output 309 \dbus__stb
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
- wire width 1 input 280 \dbus__ack
+ wire width 1 input 310 \dbus__ack
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
- wire width 1 output 281 \dbus__we
+ wire width 1 output 311 \dbus__we
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
- wire width 3 input 282 \dbus__cti
+ wire width 3 input 312 \dbus__cti
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
- wire width 2 input 283 \dbus__bte
+ wire width 2 input 313 \dbus__bte
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
- wire width 1 input 284 \dbus__err
+ wire width 1 input 314 \dbus__err
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:95"
- wire width 1 output 285 \ldst_port0_is_ld_i$121
+ wire width 1 output 315 \ldst_port0_is_ld_i$144
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:96"
- wire width 1 output 286 \ldst_port0_is_st_i$122
+ wire width 1 output 316 \ldst_port0_is_st_i$145
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99"
- wire width 4 output 287 \ldst_port0_data_len$123
+ wire width 4 output 317 \ldst_port0_data_len$146
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102"
- wire width 1 output 288 \ldst_port0_busy_o$124
+ wire width 1 output 318 \ldst_port0_busy_o$147
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:103"
- wire width 1 input 289 \ldst_port0_go_die_i$125
+ wire width 1 input 319 \ldst_port0_go_die_i$148
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 96 output 290 \ldst_port0_addr_i$126
+ wire width 96 output 320 \ldst_port0_addr_i$149
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 291 \ldst_port0_addr_i_ok$127
+ wire width 1 output 321 \ldst_port0_addr_i_ok$150
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:106"
- wire width 1 output 292 \ldst_port0_addr_ok_o$128
+ wire width 1 output 322 \ldst_port0_addr_ok_o$151
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:107"
- wire width 1 output 293 \ldst_port0_addr_exc_o$129
+ wire width 1 output 323 \ldst_port0_addr_exc_o$152
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 output 294 \ldst_port0_ld_data_o$130
+ wire width 64 output 324 \ldst_port0_ld_data_o$153
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 295 \ldst_port0_ld_data_o_ok$131
+ wire width 1 output 325 \ldst_port0_ld_data_o_ok$154
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 64 output 296 \ldst_port0_st_data_i$132
+ wire width 64 output 326 \ldst_port0_st_data_i$155
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:16"
- wire width 1 output 297 \ldst_port0_st_data_i_ok$133
+ wire width 1 output 327 \ldst_port0_st_data_i_ok$156
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:21"
- wire width 48 output 298 \a_pc_i
+ wire width 48 output 328 \a_pc_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:22"
- wire width 1 input 299 \a_stall_i
+ wire width 1 input 329 \a_stall_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:23"
- wire width 1 output 300 \a_valid_i
+ wire width 1 output 330 \a_valid_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:24"
- wire width 1 input 301 \f_stall_i
+ wire width 1 input 331 \f_stall_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:25"
- wire width 1 output 302 \f_valid_i
+ wire width 1 output 332 \f_valid_i
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:28"
- wire width 1 output 303 \a_busy_o
+ wire width 1 output 333 \a_busy_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:29"
- wire width 1 output 304 \f_busy_o
+ wire width 1 output 334 \f_busy_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:30"
- wire width 64 output 305 \f_instr_o
+ wire width 64 output 335 \f_instr_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:31"
- wire width 1 output 306 \f_fetch_err_o
+ wire width 1 output 336 \f_fetch_err_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:32"
- wire width 45 output 307 \f_badaddr_o
+ wire width 45 output 337 \f_badaddr_o
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:17"
- wire width 45 output 308 \ibus__adr
+ wire width 45 output 338 \ibus__adr
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:17"
- wire width 64 input 309 \ibus__dat_w
+ wire width 64 input 339 \ibus__dat_w
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:17"
- wire width 64 input 310 \ibus__dat_r
+ wire width 64 input 340 \ibus__dat_r
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:17"
- wire width 8 input 311 \ibus__sel
+ wire width 8 input 341 \ibus__sel
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:17"
- wire width 1 output 312 \ibus__cyc
+ wire width 1 output 342 \ibus__cyc
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:17"
- wire width 1 output 313 \ibus__stb
+ wire width 1 output 343 \ibus__stb
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:17"
- wire width 1 input 314 \ibus__ack
+ wire width 1 input 344 \ibus__ack
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:17"
- wire width 1 input 315 \ibus__we
+ wire width 1 input 345 \ibus__we
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:17"
- wire width 3 input 316 \ibus__cti
+ wire width 3 input 346 \ibus__cti
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:17"
- wire width 2 input 317 \ibus__bte
+ wire width 2 input 347 \ibus__bte
attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:17"
- wire width 1 input 318 \ibus__err
+ wire width 1 input 348 \ibus__err
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
- wire width 1 input 319 \clk
+ wire width 1 input 349 \clk
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
- wire width 1 input 320 \rst
+ wire width 1 input 350 \rst
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:79"
+ wire width 1 \core_corebusy_o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:88"
+ wire width 1 \core_core_terminated_o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:86"
+ wire width 1 \core_core_start_i
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:87"
+ wire width 1 \core_core_stop_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 8 \core_d_rd1__ren
+ wire width 8 \core_cia__ren
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
- wire width 64 \core_d_rd1__data_o
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:546"
+ wire width 64 \core_cia__data_o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:562"
wire width 1 \core_valid
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:74"
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:78"
wire width 1 \core_issue_i
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+ wire width 8 \core_msr__ren
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+ wire width 64 \core_msr__data_o
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:565"
+ wire width 64 \core_msr
+ attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566"
+ wire width 64 \core_cia
+ attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 8 \core_fast_nia_wen
- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:75"
- wire width 1 \core_corebusy_o
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 8 \core_wen
attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
wire width 64 \core_data_i
cell \core \core
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connect \raw_opcode_in \raw_opcode_in
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connect \data_i \core_data_i
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connect \clk \clk
connect \fn_unit \fn_unit
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connect \oe \oe
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connect \invert_a \invert_a
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connect \zero_a \zero_a
connect \oper_i__invert_out \oper_i__invert_out
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connect \oper_i__input_carry \oper_i__input_carry
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connect \oper_i__is_32bit \oper_i__is_32bit
connect \is_32bit \is_32bit
connect \oper_i__is_signed \oper_i__is_signed
connect \is_signed \is_signed
connect \oper_i__data_len \oper_i__data_len
connect \data_len \data_len
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connect \insn \insn
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connect \issue_i$1 \issue_i
connect \busy_o \busy_o
connect \reg1_ok \reg1_ok
connect \reg2_ok \reg2_ok
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connect \oper_i__read_cr_whole \oper_i__read_cr_whole
connect \read_cr_whole \read_cr_whole
connect \oper_i__write_cr_whole \oper_i__write_cr_whole
connect \write_cr_whole \write_cr_whole
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connect \cr_in1_ok \cr_in1_ok
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connect \fast1_ok \fast1_ok
connect \fast2_ok \fast2_ok
- connect \oper_i__insn_type$13 \oper_i__insn_type$34
- connect \oper_i__fn_unit$14 \oper_i__fn_unit$36
- connect \oper_i__insn$15 \oper_i__insn$35
- connect \oper_i__is_32bit$16 \oper_i__is_32bit$37
+ connect \oper_i__insn_type$15 \oper_i__insn_type$35
+ connect \oper_i__fn_unit$16 \oper_i__fn_unit$36
+ connect \oper_i__insn$17 \oper_i__insn$37
+ connect \oper_i__msr \oper_i__msr
+ connect \msr$18 \msr
+ connect \oper_i__cia$19 \oper_i__cia$38
+ connect \oper_i__is_32bit$20 \oper_i__is_32bit$39
connect \oper_i__traptype \oper_i__traptype
connect \traptype \traptype
connect \oper_i__trapaddr \oper_i__trapaddr
connect \trapaddr \trapaddr
- connect \issue_i$17 \issue_i$31
- connect \busy_o$18 \busy_o$40
- connect \oper_i__insn_type$19 \oper_i__insn_type$49
- connect \oper_i__fn_unit$20 \oper_i__fn_unit$50
- connect \oper_i__lk$21 \oper_i__lk$51
- connect \oper_i__invert_a$22 \oper_i__invert_a$52
- connect \oper_i__input_carry$23 \oper_i__input_carry$54
- connect \oper_i__invert_out$24 \oper_i__invert_out$53
- connect \oper_i__output_carry$25 \oper_i__output_carry$55
- connect \oper_i__is_32bit$26 \oper_i__is_32bit$56
- connect \oper_i__is_signed$27 \oper_i__is_signed$57
- connect \oper_i__data_len$28 \oper_i__data_len$58
- connect \issue_i$29 \issue_i$46
- connect \busy_o$30 \busy_o$61
- connect \oper_i__insn_type$31 \oper_i__insn_type$70
- connect \oper_i__fn_unit$32 \oper_i__fn_unit$72
- connect \oper_i__insn$33 \oper_i__insn$71
- connect \oper_i__is_32bit$34 \oper_i__is_32bit$73
- connect \issue_i$35 \issue_i$67
- connect \busy_o$36 \busy_o$76
+ connect \issue_i$21 \issue_i$32
+ connect \busy_o$22 \busy_o$42
+ connect \oper_i__insn_type$23 \oper_i__insn_type$51
+ connect \oper_i__fn_unit$24 \oper_i__fn_unit$52
+ connect \oper_i__invert_a$25 \oper_i__invert_a$53
+ connect \oper_i__zero_a$26 \oper_i__zero_a$54
+ connect \oper_i__input_carry$27 \oper_i__input_carry$55
+ connect \oper_i__invert_out$28 \oper_i__invert_out$56
+ connect \oper_i__write_cr0$29 \oper_i__write_cr0$57
+ connect \oper_i__output_carry$30 \oper_i__output_carry$58
+ connect \oper_i__is_32bit$31 \oper_i__is_32bit$59
+ connect \oper_i__is_signed$32 \oper_i__is_signed$60
+ connect \oper_i__data_len$33 \oper_i__data_len$61
+ connect \oper_i__insn$34 \oper_i__insn$62
+ connect \issue_i$35 \issue_i$48
+ connect \busy_o$36 \busy_o$65
+ connect \oper_i__insn_type$37 \oper_i__insn_type$74
+ connect \oper_i__fn_unit$38 \oper_i__fn_unit$75
+ connect \oper_i__insn$39 \oper_i__insn$76
+ connect \oper_i__is_32bit$40 \oper_i__is_32bit$77
+ connect \issue_i$41 \issue_i$71
+ connect \busy_o$42 \busy_o$80
connect \spr1_ok \spr1_ok
- connect \oper_i__insn_type$37 \oper_i__insn_type$85
- connect \oper_i__input_carry$38 \oper_i__input_carry$86
- connect \oper_i__output_carry$39 \oper_i__output_carry$87
- connect \oper_i__input_cr$40 \oper_i__input_cr$88
- connect \oper_i__output_cr$41 \oper_i__output_cr$89
- connect \oper_i__is_32bit$42 \oper_i__is_32bit$90
- connect \oper_i__is_signed$43 \oper_i__is_signed$91
- connect \issue_i$44 \issue_i$82
- connect \busy_o$45 \busy_o$94
+ connect \oper_i__insn_type$43 \oper_i__insn_type$89
+ connect \oper_i__fn_unit$44 \oper_i__fn_unit$90
+ connect \oper_i__invert_a$45 \oper_i__invert_a$91
+ connect \oper_i__zero_a$46 \oper_i__zero_a$92
+ connect \oper_i__invert_out$47 \oper_i__invert_out$93
+ connect \oper_i__write_cr0$48 \oper_i__write_cr0$94
+ connect \oper_i__is_32bit$49 \oper_i__is_32bit$95
+ connect \oper_i__is_signed$50 \oper_i__is_signed$96
+ connect \oper_i__insn$51 \oper_i__insn$97
+ connect \issue_i$52 \issue_i$86
+ connect \busy_o$53 \busy_o$100
+ connect \oper_i__insn_type$54 \oper_i__insn_type$109
+ connect \oper_i__fn_unit$55 \oper_i__fn_unit$110
+ connect \oper_i__input_carry$56 \oper_i__input_carry$111
+ connect \oper_i__output_carry$57 \oper_i__output_carry$112
+ connect \oper_i__input_cr \oper_i__input_cr
+ connect \input_cr \input_cr
+ connect \oper_i__output_cr \oper_i__output_cr
+ connect \output_cr \output_cr
+ connect \oper_i__is_32bit$58 \oper_i__is_32bit$113
+ connect \oper_i__is_signed$59 \oper_i__is_signed$114
+ connect \oper_i__insn$60 \oper_i__insn$115
+ connect \issue_i$61 \issue_i$106
+ connect \busy_o$62 \busy_o$118
connect \reg3_ok \reg3_ok
- connect \oper_i__insn_type$46 \oper_i__insn_type$103
- connect \oper_i__zero_a \oper_i__zero_a
- connect \oper_i__is_32bit$47 \oper_i__is_32bit$104
- connect \oper_i__is_signed$48 \oper_i__is_signed$105
- connect \oper_i__data_len$49 \oper_i__data_len$106
- connect \oper_i__byte_reverse$50 \oper_i__byte_reverse$107
- connect \oper_i__sign_extend$51 \oper_i__sign_extend$108
- connect \oper_i__update \oper_i__update
- connect \update \update
- connect \issue_i$52 \issue_i$100
- connect \busy_o$53 \busy_o$111
+ connect \oper_i__insn_type$63 \oper_i__insn_type$127
+ connect \oper_i__zero_a$64 \oper_i__zero_a$128
+ connect \oper_i__is_32bit$65 \oper_i__is_32bit$129
+ connect \oper_i__is_signed$66 \oper_i__is_signed$130
+ connect \oper_i__data_len$67 \oper_i__data_len$131
+ connect \oper_i__byte_reverse \oper_i__byte_reverse
+ connect \byte_reverse \byte_reverse
+ connect \oper_i__sign_extend \oper_i__sign_extend
+ connect \sign_extend \sign_extend
+ connect \oper_i__ldst_mode \oper_i__ldst_mode
+ connect \ldst_mode \ldst_mode
+ connect \issue_i$68 \issue_i$124
+ connect \busy_o$69 \busy_o$134
connect \reg1 \reg1
connect \rd__rel \rd__rel
connect \rd__go \rd__go
connect \src1_i \src1_i
- connect \rd__rel$54 \rd__rel$10
- connect \rd__go$55 \rd__go$1
- connect \src1_i$56 \src1_i$7
- connect \rd__rel$57 \rd__rel$41
- connect \rd__go$58 \rd__go$29
- connect \src1_i$59 \src1_i$38
- connect \rd__rel$60 \rd__rel$62
- connect \rd__go$61 \rd__go$44
- connect \src1_i$62 \src1_i$59
- connect \rd__rel$63 \rd__rel$77
- connect \rd__go$64 \rd__go$65
- connect \src1_i$65 \src1_i$74
- connect \rd__rel$66 \rd__rel$95
- connect \rd__go$67 \rd__go$80
- connect \src1_i$68 \src1_i$92
- connect \rd__rel$69 \rd__rel$112
- connect \rd__go$70 \rd__go$98
- connect \src1_i$71 \src1_i$109
+ connect \rd__rel$70 \rd__rel$12
+ connect \rd__go$71 \rd__go$1
+ connect \src1_i$72 \src1_i$9
+ connect \rd__rel$73 \rd__rel$43
+ connect \rd__go$74 \rd__go$30
+ connect \src1_i$75 \src1_i$40
+ connect \rd__rel$76 \rd__rel$66
+ connect \rd__go$77 \rd__go$46
+ connect \src1_i$78 \src1_i$63
+ connect \rd__rel$79 \rd__rel$81
+ connect \rd__go$80 \rd__go$69
+ connect \src1_i$81 \src1_i$78
+ connect \rd__rel$82 \rd__rel$101
+ connect \rd__go$83 \rd__go$84
+ connect \src1_i$84 \src1_i$98
+ connect \rd__rel$85 \rd__rel$119
+ connect \rd__go$86 \rd__go$104
+ connect \src1_i$87 \src1_i$116
+ connect \rd__rel$88 \rd__rel$135
+ connect \rd__go$89 \rd__go$122
+ connect \src1_i$90 \src1_i$132
connect \reg2 \reg2
connect \src2_i \src2_i
- connect \src2_i$72 \src2_i$8
- connect \src2_i$73 \src2_i$39
- connect \src2_i$74 \src2_i$60
- connect \src2_i$75 \src2_i$93
- connect \src2_i$76 \src2_i$110
+ connect \src2_i$91 \src2_i$10
+ connect \src2_i$92 \src2_i$41
+ connect \src2_i$93 \src2_i$64
+ connect \src2_i$94 \src2_i$99
+ connect \src2_i$95 \src2_i$117
+ connect \src2_i$96 \src2_i$133
connect \reg3 \reg3
connect \src3_i \src3_i
connect \cr_in1 \cr_in1
- connect \rd__rel$77 \rd__rel$26
- connect \rd__go$78 \rd__go$13
+ connect \rd__rel$97 \rd__rel$27
+ connect \rd__go$98 \rd__go$15
connect \cr_in2 \cr_in2
- connect \cr_in2$79 \cr_in2$117
+ connect \cr_in2$99 \cr_in2$140
connect \fast1 \fast1
- connect \src1_i$80 \src1_i$23
+ connect \src1_i$100 \src1_i$24
connect \fast2 \fast2
- connect \src2_i$81 \src2_i$24
+ connect \src2_i$101 \src2_i$25
connect \spr1 \spr1
- connect \src2_i$82 \src2_i$75
+ connect \src2_i$102 \src2_i$79
connect \rego \rego
connect \wr__rel \wr__rel
connect \wr__go \wr__go
- connect \wr__rel$83 \wr__rel$11
- connect \wr__go$84 \wr__go$2
- connect \wr__rel$85 \wr__rel$42
- connect \wr__go$86 \wr__go$30
- connect \wr__rel$87 \wr__rel$63
- connect \wr__go$88 \wr__go$45
- connect \wr__rel$89 \wr__rel$78
- connect \wr__go$90 \wr__go$66
- connect \wr__rel$91 \wr__rel$96
- connect \wr__go$92 \wr__go$81
+ connect \wr__rel$103 \wr__rel$13
+ connect \wr__go$104 \wr__go$2
+ connect \wr__rel$105 \wr__rel$44
+ connect \wr__go$106 \wr__go$31
+ connect \wr__rel$107 \wr__rel$67
+ connect \wr__go$108 \wr__go$47
+ connect \wr__rel$109 \wr__rel$82
+ connect \wr__go$110 \wr__go$70
+ connect \wr__rel$111 \wr__rel$102
+ connect \wr__go$112 \wr__go$85
+ connect \wr__rel$113 \wr__rel$120
+ connect \wr__go$114 \wr__go$105
connect \o_ok \o_ok
- connect \wr__rel$93 \wr__rel$113
- connect \wr__go$94 \wr__go$99
+ connect \wr__rel$115 \wr__rel$136
+ connect \wr__go$116 \wr__go$123
+ connect \dest1_o \dest1_o
+ connect \dest1_o$117 \dest1_o$14
+ connect \dest1_o$118 \dest1_o$45
+ connect \dest1_o$119 \dest1_o$68
+ connect \dest1_o$120 \dest1_o$83
+ connect \dest1_o$121 \dest1_o$103
+ connect \dest1_o$122 \dest1_o$121
connect \o \o
- connect \ea \ea$115
+ connect \ea \ea$138
connect \ea_ok \ea_ok
- connect \ea$95 \ea
+ connect \ea$123 \ea
+ connect \cr_out \cr_out$142
connect \fasto1 \fasto1
- connect \wr__rel$96 \wr__rel$27
- connect \wr__go$97 \wr__go$14
+ connect \wr__rel$124 \wr__rel$28
+ connect \wr__go$125 \wr__go$16
+ connect \dest1_o$126 \dest1_o$29
connect \fasto2 \fasto2
connect \spro \spro
connect \opcode_in \opcode_in
connect \out_sel \out_sel
connect \rc_sel \rc_sel
connect \cr_in \cr_in
- connect \cr_out$98 \cr_out
- connect \nia \nia
- connect \function_unit \function_unit
+ connect \cr_out$127 \cr_out
connect \internal_op \internal_op
+ connect \function_unit \function_unit
connect \rego_ok \rego_ok
- connect \ea_ok$99 \ea_ok$116
+ connect \ea_ok$128 \ea_ok$139
connect \spro_ok \spro_ok
connect \fasto1_ok \fasto1_ok
connect \fasto2_ok \fasto2_ok
+ connect \cr_out_ok \cr_out_ok
connect \ldst_len \ldst_len
connect \inv_a \inv_a
connect \inv_out \inv_out
connect \cry_out \cry_out
connect \is_32b \is_32b
connect \sgn \sgn
- connect \lk$100 \lk
+ connect \lk$129 \lk
connect \br \br
connect \sgn_ext \sgn_ext
- connect \upd \upd
- connect \asmcode \asmcode$114
+ connect \xer_out \xer_out
+ connect \asmcode \asmcode$137
connect \form \form
connect \rsrv \rsrv
connect \sgl_pipe \sgl_pipe
- connect \asmcode$101 \asmcode
+ connect \asmcode$130 \asmcode
connect \go_die_i \go_die_i
connect \shadown_i \shadown_i
- connect \dest1_o \dest1_o
- connect \go_die_i$102 \go_die_i$5
- connect \shadown_i$103 \shadown_i$4
- connect \dest1_o$104 \dest1_o$12
- connect \go_die_i$105 \go_die_i$17
- connect \shadown_i$106 \shadown_i$16
- connect \dest1_o$107 \dest1_o$28
- connect \go_die_i$108 \go_die_i$33
- connect \shadown_i$109 \shadown_i$32
- connect \dest1_o$110 \dest1_o$43
- connect \go_die_i$111 \go_die_i$48
- connect \shadown_i$112 \shadown_i$47
- connect \dest1_o$113 \dest1_o$64
- connect \go_die_i$114 \go_die_i$69
- connect \shadown_i$115 \shadown_i$68
- connect \dest1_o$116 \dest1_o$79
- connect \go_die_i$117 \go_die_i$84
- connect \shadown_i$118 \shadown_i$83
- connect \dest1_o$119 \dest1_o$97
- connect \go_die_i$120 \go_die_i$102
+ connect \go_die_i$131 \go_die_i$5
+ connect \shadown_i$132 \shadown_i$4
+ connect \go_die_i$133 \go_die_i$19
+ connect \shadown_i$134 \shadown_i$18
+ connect \go_die_i$135 \go_die_i$34
+ connect \shadown_i$136 \shadown_i$33
+ connect \go_die_i$137 \go_die_i$50
+ connect \shadown_i$138 \shadown_i$49
+ connect \go_die_i$139 \go_die_i$73
+ connect \shadown_i$140 \shadown_i$72
+ connect \go_die_i$141 \go_die_i$88
+ connect \shadown_i$142 \shadown_i$87
+ connect \go_die_i$143 \go_die_i$108
+ connect \shadown_i$144 \shadown_i$107
+ connect \go_die_i$145 \go_die_i$126
connect \load_mem_o \load_mem_o
connect \stwd_mem_o \stwd_mem_o
- connect \shadown_i$121 \shadown_i$101
- connect \ldst_port0_is_ld_i \ldst_port0_is_ld_i$121
- connect \ldst_port0_is_st_i \ldst_port0_is_st_i$122
- connect \ldst_port0_data_len \ldst_port0_data_len$123
- connect \ldst_port0_addr_i \ldst_port0_addr_i$126
- connect \ldst_port0_addr_i_ok \ldst_port0_addr_i_ok$127
- connect \ldst_port0_addr_exc_o \ldst_port0_addr_exc_o$129
- connect \ldst_port0_addr_ok_o \ldst_port0_addr_ok_o$128
- connect \ldst_port0_ld_data_o \ldst_port0_ld_data_o$130
- connect \ldst_port0_ld_data_o_ok \ldst_port0_ld_data_o_ok$131
- connect \ldst_port0_st_data_i \ldst_port0_st_data_i$132
- connect \ldst_port0_st_data_i_ok \ldst_port0_st_data_i_ok$133
- connect \ldst_port0_is_ld_i$122 \ldst_port0_is_ld_i
+ connect \shadown_i$146 \shadown_i$125
+ connect \ldst_port0_is_ld_i \ldst_port0_is_ld_i$144
+ connect \ldst_port0_is_st_i \ldst_port0_is_st_i$145
+ connect \ldst_port0_data_len \ldst_port0_data_len$146
+ connect \ldst_port0_addr_i \ldst_port0_addr_i$149
+ connect \ldst_port0_addr_i_ok \ldst_port0_addr_i_ok$150
+ connect \ldst_port0_addr_exc_o \ldst_port0_addr_exc_o$152
+ connect \ldst_port0_addr_ok_o \ldst_port0_addr_ok_o$151
+ connect \ldst_port0_ld_data_o \ldst_port0_ld_data_o$153
+ connect \ldst_port0_ld_data_o_ok \ldst_port0_ld_data_o_ok$154
+ connect \ldst_port0_st_data_i \ldst_port0_st_data_i$155
+ connect \ldst_port0_st_data_i_ok \ldst_port0_st_data_i_ok$156
+ connect \ldst_port0_is_ld_i$147 \ldst_port0_is_ld_i
connect \ldst_port0_busy_o \ldst_port0_busy_o
- connect \ldst_port0_is_st_i$123 \ldst_port0_is_st_i
- connect \ldst_port0_data_len$124 \ldst_port0_data_len
- connect \ldst_port0_addr_i$125 \ldst_port0_addr_i
- connect \ldst_port0_addr_i_ok$126 \ldst_port0_addr_i_ok
+ connect \ldst_port0_is_st_i$148 \ldst_port0_is_st_i
+ connect \ldst_port0_data_len$149 \ldst_port0_data_len
+ connect \ldst_port0_addr_i$150 \ldst_port0_addr_i
+ connect \ldst_port0_addr_i_ok$151 \ldst_port0_addr_i_ok
connect \x_mask_i \x_mask_i
connect \x_addr_i \x_addr_i
- connect \ldst_port0_addr_ok_o$127 \ldst_port0_addr_ok_o
+ connect \ldst_port0_addr_ok_o$152 \ldst_port0_addr_ok_o
connect \m_ld_data_o \m_ld_data_o
- connect \ldst_port0_ld_data_o$128 \ldst_port0_ld_data_o
- connect \ldst_port0_ld_data_o_ok$129 \ldst_port0_ld_data_o_ok
+ connect \ldst_port0_ld_data_o$153 \ldst_port0_ld_data_o
+ connect \ldst_port0_ld_data_o_ok$154 \ldst_port0_ld_data_o_ok
connect \x_busy_o \x_busy_o
- connect \ldst_port0_st_data_i_ok$130 \ldst_port0_st_data_i_ok
- connect \ldst_port0_st_data_i$131 \ldst_port0_st_data_i
+ connect \ldst_port0_st_data_i_ok$155 \ldst_port0_st_data_i_ok
+ connect \ldst_port0_st_data_i$156 \ldst_port0_st_data_i
connect \x_st_data_i \x_st_data_i
- connect \ldst_port0_addr_exc_o$132 \ldst_port0_addr_exc_o
+ connect \ldst_port0_addr_exc_o$157 \ldst_port0_addr_exc_o
connect \x_ld_i \x_ld_i
connect \x_st_i \x_st_i
connect \m_valid_i \m_valid_i
connect \x_valid_i \x_valid_i
connect \ldst_port0_go_die_i \ldst_port0_go_die_i
- connect \ldst_port0_go_die_i$133 \ldst_port0_go_die_i$125
- connect \ldst_port0_busy_o$134 \ldst_port0_busy_o$124
+ connect \ldst_port0_go_die_i$158 \ldst_port0_go_die_i$148
+ connect \ldst_port0_busy_o$159 \ldst_port0_busy_o$147
connect \dbus__cyc \dbus__cyc
connect \x_stall_i \x_stall_i
connect \dbus__ack \dbus__ack
connect \f_badaddr_o \f_badaddr_o
connect \a_busy_o \a_busy_o
end
+ attribute \src "simple/issuer.py:54"
+ wire width 1 \busy_o$157
process $group_0
+ assign \busy_o$157 1'0
+ assign \busy_o$157 \core_corebusy_o
+ sync init
+ end
+ attribute \src "simple/issuer.py:55"
+ wire width 1 \halted_o
+ process $group_1
+ assign \halted_o 1'0
+ assign \halted_o \core_core_terminated_o
+ sync init
+ end
+ attribute \src "simple/issuer.py:51"
+ wire width 1 \core_start_i
+ process $group_2
+ assign \core_start_i 1'0
+ assign \core_start_i \core_core_start_i
+ sync init
+ end
+ attribute \src "simple/issuer.py:52"
+ wire width 1 \core_stop_i
+ process $group_3
+ assign \core_stop_i 1'0
+ assign \core_stop_i \core_core_stop_i
+ sync init
+ end
+ attribute \src "simple/issuer.py:53"
+ wire width 1 \core_bigendian_i
+ process $group_4
+ assign \core_bigendian_i 1'0
+ assign \core_bigendian_i \bigendian
+ sync init
+ end
+ process $group_5
assign \ad__go 1'0
assign \ad__go \ad__rel
sync init
end
- process $group_1
+ process $group_6
assign \st__go 1'0
assign \st__go \st__rel
sync init
end
- attribute \src "simple/issuer.py:73"
- wire width 64 \current_pc
- attribute \src "simple/issuer.py:73"
- wire width 64 \current_pc$next
- process $group_2
+ attribute \src "simple/issuer.py:89"
+ wire width 64 \cur_pc
+ attribute \src "simple/issuer.py:89"
+ wire width 64 \cur_pc$next
+ process $group_7
assign \pc_o 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \pc_o \current_pc
+ assign \pc_o \cur_pc
sync init
end
- attribute \src "simple/issuer.py:79"
- wire width 64 \nia$134
- attribute \src "simple/issuer.py:80"
- wire width 65 $135
- attribute \src "simple/issuer.py:80"
- wire width 65 $136
- attribute \src "simple/issuer.py:80"
- cell $add $137
+ attribute \src "simple/issuer.py:99"
+ wire width 64 \nia
+ attribute \src "simple/issuer.py:100"
+ wire width 65 $158
+ attribute \src "simple/issuer.py:100"
+ wire width 65 $159
+ attribute \src "simple/issuer.py:100"
+ cell $add $160
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \B_WIDTH 3
parameter \Y_WIDTH 65
- connect \A \current_pc
+ connect \A \cur_pc
connect \B 3'100
- connect \Y $136
+ connect \Y $159
end
- connect $135 $136
- process $group_3
- assign \nia$134 64'0000000000000000000000000000000000000000000000000000000000000000
- assign \nia$134 $135 [63:0]
+ connect $158 $159
+ process $group_8
+ assign \nia 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \nia $158 [63:0]
sync init
end
- attribute \src "simple/issuer.py:74"
+ attribute \src "simple/issuer.py:90"
wire width 1 \pc_changed
- attribute \src "simple/issuer.py:74"
- wire width 1 \pc_changed$next
attribute \src "simple/issuer.py:90"
+ wire width 1 \pc_changed$next
+ attribute \src "simple/issuer.py:114"
+ wire width 1 $161
+ attribute \src "simple/issuer.py:114"
+ cell $not $162
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \core_core_terminated_o
+ connect \Y $161
+ end
+ attribute \src "simple/issuer.py:121"
wire width 2 \fsm_state
- attribute \src "simple/issuer.py:90"
+ attribute \src "simple/issuer.py:121"
wire width 2 \fsm_state$next
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
- wire width 1 $138
- attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:439"
- cell $reduce_bool $139
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
+ wire width 1 $163
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
+ cell $reduce_bool $164
parameter \A_SIGNED 0
parameter \A_WIDTH 8
parameter \Y_WIDTH 1
connect \A \core_fast_nia_wen
- connect \Y $138
+ connect \Y $163
end
- process $group_4
+ process $group_9
assign \pc_changed$next \pc_changed
- attribute \src "simple/issuer.py:90"
- switch \fsm_state
- attribute \src "simple/issuer.py:93"
- attribute \nmigen.decoding "IDLE/0"
- case 2'00
- assign \pc_changed$next 1'0
- attribute \src "simple/issuer.py:115"
- attribute \nmigen.decoding "INSN_READ/1"
- case 2'01
- attribute \src "simple/issuer.py:132"
- attribute \nmigen.decoding "INSN_ACTIVE/2"
- case 2'10
- attribute \src "simple/issuer.py:136"
- switch { $138 }
- attribute \src "simple/issuer.py:136"
- case 1'1
- assign \pc_changed$next 1'1
+ attribute \src "simple/issuer.py:114"
+ switch { $161 }
+ attribute \src "simple/issuer.py:114"
+ case 1'1
+ attribute \src "simple/issuer.py:121"
+ switch \fsm_state
+ attribute \src "simple/issuer.py:124"
+ attribute \nmigen.decoding "IDLE/0"
+ case 2'00
+ assign \pc_changed$next 1'0
+ attribute \src "simple/issuer.py:146"
+ attribute \nmigen.decoding "INSN_READ/1"
+ case 2'01
+ attribute \src "simple/issuer.py:172"
+ attribute \nmigen.decoding "INSN_ACTIVE/2"
+ case 2'10
+ attribute \src "simple/issuer.py:173"
+ switch { \core_core_terminated_o }
+ attribute \src "simple/issuer.py:173"
+ case 1'1
+ attribute \src "simple/issuer.py:175"
+ case
+ attribute \src "simple/issuer.py:181"
+ switch { $163 }
+ attribute \src "simple/issuer.py:181"
+ case 1'1
+ assign \pc_changed$next 1'1
+ end
+ end
end
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
sync posedge \clk
update \pc_changed \pc_changed$next
end
- attribute \src "simple/issuer.py:97"
- wire width 64 \pc$140
- process $group_5
- assign \pc$140 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "simple/issuer.py:90"
- switch \fsm_state
- attribute \src "simple/issuer.py:93"
- attribute \nmigen.decoding "IDLE/0"
- case 2'00
- attribute \src "simple/issuer.py:95"
- switch { \go_insn_i }
- attribute \src "simple/issuer.py:95"
- case 1'1
- attribute \src "simple/issuer.py:98"
- switch { \pc_ok }
- attribute \src "simple/issuer.py:98"
+ attribute \src "simple/issuer.py:128"
+ wire width 64 \pc
+ attribute \src "simple/issuer.py:114"
+ wire width 1 $165
+ attribute \src "simple/issuer.py:114"
+ cell $not $166
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \core_core_terminated_o
+ connect \Y $165
+ end
+ process $group_10
+ assign \pc 64'0000000000000000000000000000000000000000000000000000000000000000
+ attribute \src "simple/issuer.py:114"
+ switch { $165 }
+ attribute \src "simple/issuer.py:114"
+ case 1'1
+ attribute \src "simple/issuer.py:121"
+ switch \fsm_state
+ attribute \src "simple/issuer.py:124"
+ attribute \nmigen.decoding "IDLE/0"
+ case 2'00
+ attribute \src "simple/issuer.py:126"
+ switch { \go_insn_i }
+ attribute \src "simple/issuer.py:126"
case 1'1
- assign \pc$140 \pc
- attribute \src "simple/issuer.py:101"
- case
- assign \pc$140 \core_d_rd1__data_o
+ attribute \src "simple/issuer.py:129"
+ switch { \pc_i_ok }
+ attribute \src "simple/issuer.py:129"
+ case 1'1
+ assign \pc \pc_i
+ attribute \src "simple/issuer.py:132"
+ case
+ assign \pc \core_cia__data_o
+ end
end
+ attribute \src "simple/issuer.py:146"
+ attribute \nmigen.decoding "INSN_READ/1"
+ case 2'01
+ attribute \src "simple/issuer.py:172"
+ attribute \nmigen.decoding "INSN_ACTIVE/2"
+ case 2'10
end
- attribute \src "simple/issuer.py:115"
- attribute \nmigen.decoding "INSN_READ/1"
- case 2'01
- attribute \src "simple/issuer.py:132"
- attribute \nmigen.decoding "INSN_ACTIVE/2"
- case 2'10
end
sync init
end
- process $group_6
- assign \core_d_rd1__ren 8'00000000
- attribute \src "simple/issuer.py:90"
- switch \fsm_state
- attribute \src "simple/issuer.py:93"
- attribute \nmigen.decoding "IDLE/0"
- case 2'00
- attribute \src "simple/issuer.py:95"
- switch { \go_insn_i }
- attribute \src "simple/issuer.py:95"
- case 1'1
- attribute \src "simple/issuer.py:98"
- switch { \pc_ok }
- attribute \src "simple/issuer.py:98"
+ attribute \src "simple/issuer.py:114"
+ wire width 1 $167
+ attribute \src "simple/issuer.py:114"
+ cell $not $168
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \core_core_terminated_o
+ connect \Y $167
+ end
+ process $group_11
+ assign \core_cia__ren 8'00000000
+ attribute \src "simple/issuer.py:114"
+ switch { $167 }
+ attribute \src "simple/issuer.py:114"
+ case 1'1
+ attribute \src "simple/issuer.py:121"
+ switch \fsm_state
+ attribute \src "simple/issuer.py:124"
+ attribute \nmigen.decoding "IDLE/0"
+ case 2'00
+ attribute \src "simple/issuer.py:126"
+ switch { \go_insn_i }
+ attribute \src "simple/issuer.py:126"
case 1'1
- attribute \src "simple/issuer.py:101"
- case
- assign \core_d_rd1__ren 8'00000001
+ attribute \src "simple/issuer.py:129"
+ switch { \pc_i_ok }
+ attribute \src "simple/issuer.py:129"
+ case 1'1
+ attribute \src "simple/issuer.py:132"
+ case
+ assign \core_cia__ren 8'00000001
+ end
end
+ attribute \src "simple/issuer.py:146"
+ attribute \nmigen.decoding "INSN_READ/1"
+ case 2'01
+ attribute \src "simple/issuer.py:172"
+ attribute \nmigen.decoding "INSN_ACTIVE/2"
+ case 2'10
end
- attribute \src "simple/issuer.py:115"
- attribute \nmigen.decoding "INSN_READ/1"
- case 2'01
- attribute \src "simple/issuer.py:132"
- attribute \nmigen.decoding "INSN_ACTIVE/2"
- case 2'10
end
sync init
end
- process $group_7
+ attribute \src "simple/issuer.py:114"
+ wire width 1 $169
+ attribute \src "simple/issuer.py:114"
+ cell $not $170
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \core_core_terminated_o
+ connect \Y $169
+ end
+ process $group_12
assign \a_pc_i 48'000000000000000000000000000000000000000000000000
- attribute \src "simple/issuer.py:90"
- switch \fsm_state
- attribute \src "simple/issuer.py:93"
- attribute \nmigen.decoding "IDLE/0"
- case 2'00
- attribute \src "simple/issuer.py:95"
- switch { \go_insn_i }
- attribute \src "simple/issuer.py:95"
- case 1'1
- assign \a_pc_i \pc$140 [47:0]
+ attribute \src "simple/issuer.py:114"
+ switch { $169 }
+ attribute \src "simple/issuer.py:114"
+ case 1'1
+ attribute \src "simple/issuer.py:121"
+ switch \fsm_state
+ attribute \src "simple/issuer.py:124"
+ attribute \nmigen.decoding "IDLE/0"
+ case 2'00
+ attribute \src "simple/issuer.py:126"
+ switch { \go_insn_i }
+ attribute \src "simple/issuer.py:126"
+ case 1'1
+ assign \a_pc_i \pc [47:0]
+ end
+ attribute \src "simple/issuer.py:146"
+ attribute \nmigen.decoding "INSN_READ/1"
+ case 2'01
+ attribute \src "simple/issuer.py:172"
+ attribute \nmigen.decoding "INSN_ACTIVE/2"
+ case 2'10
end
- attribute \src "simple/issuer.py:115"
- attribute \nmigen.decoding "INSN_READ/1"
- case 2'01
- attribute \src "simple/issuer.py:132"
- attribute \nmigen.decoding "INSN_ACTIVE/2"
- case 2'10
end
sync init
end
- process $group_8
+ attribute \src "simple/issuer.py:114"
+ wire width 1 $171
+ attribute \src "simple/issuer.py:114"
+ cell $not $172
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \core_core_terminated_o
+ connect \Y $171
+ end
+ process $group_13
assign \a_valid_i 1'0
- attribute \src "simple/issuer.py:90"
- switch \fsm_state
- attribute \src "simple/issuer.py:93"
- attribute \nmigen.decoding "IDLE/0"
- case 2'00
- attribute \src "simple/issuer.py:95"
- switch { \go_insn_i }
- attribute \src "simple/issuer.py:95"
- case 1'1
- assign \a_valid_i 1'1
- end
- attribute \src "simple/issuer.py:115"
- attribute \nmigen.decoding "INSN_READ/1"
- case 2'01
- attribute \src "simple/issuer.py:116"
- switch { \f_busy_o }
- attribute \src "simple/issuer.py:116"
- case 1'1
- assign \a_valid_i 1'1
- attribute \src "simple/issuer.py:120"
- case
+ attribute \src "simple/issuer.py:114"
+ switch { $171 }
+ attribute \src "simple/issuer.py:114"
+ case 1'1
+ attribute \src "simple/issuer.py:121"
+ switch \fsm_state
+ attribute \src "simple/issuer.py:124"
+ attribute \nmigen.decoding "IDLE/0"
+ case 2'00
+ attribute \src "simple/issuer.py:126"
+ switch { \go_insn_i }
+ attribute \src "simple/issuer.py:126"
+ case 1'1
+ assign \a_valid_i 1'1
+ end
+ attribute \src "simple/issuer.py:146"
+ attribute \nmigen.decoding "INSN_READ/1"
+ case 2'01
+ attribute \src "simple/issuer.py:147"
+ switch { \f_busy_o }
+ attribute \src "simple/issuer.py:147"
+ case 1'1
+ assign \a_valid_i 1'1
+ attribute \src "simple/issuer.py:151"
+ case
+ end
+ attribute \src "simple/issuer.py:172"
+ attribute \nmigen.decoding "INSN_ACTIVE/2"
+ case 2'10
end
- attribute \src "simple/issuer.py:132"
- attribute \nmigen.decoding "INSN_ACTIVE/2"
- case 2'10
end
sync init
end
- process $group_9
+ attribute \src "simple/issuer.py:114"
+ wire width 1 $173
+ attribute \src "simple/issuer.py:114"
+ cell $not $174
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \core_core_terminated_o
+ connect \Y $173
+ end
+ process $group_14
assign \f_valid_i 1'0
- attribute \src "simple/issuer.py:90"
- switch \fsm_state
- attribute \src "simple/issuer.py:93"
- attribute \nmigen.decoding "IDLE/0"
- case 2'00
- attribute \src "simple/issuer.py:95"
- switch { \go_insn_i }
- attribute \src "simple/issuer.py:95"
- case 1'1
- assign \f_valid_i 1'1
- end
- attribute \src "simple/issuer.py:115"
- attribute \nmigen.decoding "INSN_READ/1"
- case 2'01
- attribute \src "simple/issuer.py:116"
- switch { \f_busy_o }
- attribute \src "simple/issuer.py:116"
- case 1'1
- assign \f_valid_i 1'1
- attribute \src "simple/issuer.py:120"
- case
+ attribute \src "simple/issuer.py:114"
+ switch { $173 }
+ attribute \src "simple/issuer.py:114"
+ case 1'1
+ attribute \src "simple/issuer.py:121"
+ switch \fsm_state
+ attribute \src "simple/issuer.py:124"
+ attribute \nmigen.decoding "IDLE/0"
+ case 2'00
+ attribute \src "simple/issuer.py:126"
+ switch { \go_insn_i }
+ attribute \src "simple/issuer.py:126"
+ case 1'1
+ assign \f_valid_i 1'1
+ end
+ attribute \src "simple/issuer.py:146"
+ attribute \nmigen.decoding "INSN_READ/1"
+ case 2'01
+ attribute \src "simple/issuer.py:147"
+ switch { \f_busy_o }
+ attribute \src "simple/issuer.py:147"
+ case 1'1
+ assign \f_valid_i 1'1
+ attribute \src "simple/issuer.py:151"
+ case
+ end
+ attribute \src "simple/issuer.py:172"
+ attribute \nmigen.decoding "INSN_ACTIVE/2"
+ case 2'10
end
- attribute \src "simple/issuer.py:132"
- attribute \nmigen.decoding "INSN_ACTIVE/2"
- case 2'10
end
sync init
end
- process $group_10
- assign \current_pc$next \current_pc
- attribute \src "simple/issuer.py:90"
- switch \fsm_state
- attribute \src "simple/issuer.py:93"
- attribute \nmigen.decoding "IDLE/0"
- case 2'00
- attribute \src "simple/issuer.py:95"
- switch { \go_insn_i }
- attribute \src "simple/issuer.py:95"
- case 1'1
- assign \current_pc$next \pc$140
+ attribute \src "simple/issuer.py:114"
+ wire width 1 $175
+ attribute \src "simple/issuer.py:114"
+ cell $not $176
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \core_core_terminated_o
+ connect \Y $175
+ end
+ process $group_15
+ assign \cur_pc$next \cur_pc
+ attribute \src "simple/issuer.py:114"
+ switch { $175 }
+ attribute \src "simple/issuer.py:114"
+ case 1'1
+ attribute \src "simple/issuer.py:121"
+ switch \fsm_state
+ attribute \src "simple/issuer.py:124"
+ attribute \nmigen.decoding "IDLE/0"
+ case 2'00
+ attribute \src "simple/issuer.py:126"
+ switch { \go_insn_i }
+ attribute \src "simple/issuer.py:126"
+ case 1'1
+ assign \cur_pc$next \pc
+ end
+ attribute \src "simple/issuer.py:146"
+ attribute \nmigen.decoding "INSN_READ/1"
+ case 2'01
+ attribute \src "simple/issuer.py:172"
+ attribute \nmigen.decoding "INSN_ACTIVE/2"
+ case 2'10
end
- attribute \src "simple/issuer.py:115"
- attribute \nmigen.decoding "INSN_READ/1"
- case 2'01
- attribute \src "simple/issuer.py:132"
- attribute \nmigen.decoding "INSN_ACTIVE/2"
- case 2'10
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
case 1'1
- assign \current_pc$next 64'0000000000000000000000000000000000000000000000000000000000000000
+ assign \cur_pc$next 64'0000000000000000000000000000000000000000000000000000000000000000
end
sync init
- update \current_pc 64'0000000000000000000000000000000000000000000000000000000000000000
+ update \cur_pc 64'0000000000000000000000000000000000000000000000000000000000000000
sync posedge \clk
- update \current_pc \current_pc$next
+ update \cur_pc \cur_pc$next
end
- attribute \src "simple/issuer.py:138"
- wire width 1 $141
- attribute \src "simple/issuer.py:138"
- cell $not $142
+ attribute \src "simple/issuer.py:114"
+ wire width 1 $177
+ attribute \src "simple/issuer.py:114"
+ cell $not $178
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \core_core_terminated_o
+ connect \Y $177
+ end
+ attribute \src "simple/issuer.py:183"
+ wire width 1 $179
+ attribute \src "simple/issuer.py:183"
+ cell $not $180
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \core_corebusy_o
- connect \Y $141
+ connect \Y $179
end
- process $group_11
+ process $group_16
assign \fsm_state$next \fsm_state
- attribute \src "simple/issuer.py:90"
- switch \fsm_state
- attribute \src "simple/issuer.py:93"
- attribute \nmigen.decoding "IDLE/0"
- case 2'00
- attribute \src "simple/issuer.py:95"
- switch { \go_insn_i }
- attribute \src "simple/issuer.py:95"
- case 1'1
- assign \fsm_state$next 2'01
- end
- attribute \src "simple/issuer.py:115"
- attribute \nmigen.decoding "INSN_READ/1"
- case 2'01
- attribute \src "simple/issuer.py:116"
- switch { \f_busy_o }
- attribute \src "simple/issuer.py:116"
- case 1'1
- attribute \src "simple/issuer.py:120"
- case
- assign \fsm_state$next 2'10
- end
- attribute \src "simple/issuer.py:132"
- attribute \nmigen.decoding "INSN_ACTIVE/2"
- case 2'10
- attribute \src "simple/issuer.py:138"
- switch { $141 }
- attribute \src "simple/issuer.py:138"
- case 1'1
- assign \fsm_state$next 2'00
+ attribute \src "simple/issuer.py:114"
+ switch { $177 }
+ attribute \src "simple/issuer.py:114"
+ case 1'1
+ attribute \src "simple/issuer.py:121"
+ switch \fsm_state
+ attribute \src "simple/issuer.py:124"
+ attribute \nmigen.decoding "IDLE/0"
+ case 2'00
+ attribute \src "simple/issuer.py:126"
+ switch { \go_insn_i }
+ attribute \src "simple/issuer.py:126"
+ case 1'1
+ assign \fsm_state$next 2'01
+ end
+ attribute \src "simple/issuer.py:146"
+ attribute \nmigen.decoding "INSN_READ/1"
+ case 2'01
+ attribute \src "simple/issuer.py:147"
+ switch { \f_busy_o }
+ attribute \src "simple/issuer.py:147"
+ case 1'1
+ attribute \src "simple/issuer.py:151"
+ case
+ assign \fsm_state$next 2'10
+ end
+ attribute \src "simple/issuer.py:172"
+ attribute \nmigen.decoding "INSN_ACTIVE/2"
+ case 2'10
+ attribute \src "simple/issuer.py:173"
+ switch { \core_core_terminated_o }
+ attribute \src "simple/issuer.py:173"
+ case 1'1
+ assign \fsm_state$next 2'00
+ attribute \src "simple/issuer.py:175"
+ case
+ attribute \src "simple/issuer.py:183"
+ switch { $179 }
+ attribute \src "simple/issuer.py:183"
+ case 1'1
+ assign \fsm_state$next 2'00
+ end
+ end
end
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
sync posedge \clk
update \fsm_state \fsm_state$next
end
- attribute \src "simple/issuer.py:72"
+ attribute \src "simple/issuer.py:88"
wire width 32 \current_insn
- attribute \src "simple/issuer.py:122"
- wire width 32 $143
+ attribute \src "simple/issuer.py:114"
+ wire width 1 $181
+ attribute \src "simple/issuer.py:114"
+ cell $not $182
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \core_core_terminated_o
+ connect \Y $181
+ end
+ attribute \src "simple/issuer.py:153"
+ wire width 32 $183
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609"
- wire width 7 $144
+ wire width 7 $184
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609"
- cell $mul $145
+ cell $mul $185
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \B_SIGNED 0
parameter \B_WIDTH 6
parameter \Y_WIDTH 7
- connect \A \current_pc [2]
+ connect \A \cur_pc [2]
connect \B 6'100000
- connect \Y $144
+ connect \Y $184
end
- attribute \src "simple/issuer.py:122"
- cell $shift $146
+ attribute \src "simple/issuer.py:153"
+ cell $shift $186
parameter \A_SIGNED 0
parameter \A_WIDTH 64
parameter \B_SIGNED 0
parameter \B_WIDTH 7
parameter \Y_WIDTH 32
connect \A \f_instr_o
- connect \B $144
- connect \Y $143
+ connect \B $184
+ connect \Y $183
end
- process $group_12
+ process $group_17
assign \current_insn 32'00000000000000000000000000000000
- attribute \src "simple/issuer.py:90"
- switch \fsm_state
- attribute \src "simple/issuer.py:93"
- attribute \nmigen.decoding "IDLE/0"
- case 2'00
- attribute \src "simple/issuer.py:115"
- attribute \nmigen.decoding "INSN_READ/1"
- case 2'01
- attribute \src "simple/issuer.py:116"
- switch { \f_busy_o }
- attribute \src "simple/issuer.py:116"
- case 1'1
- attribute \src "simple/issuer.py:120"
- case
- assign \current_insn $143
+ attribute \src "simple/issuer.py:114"
+ switch { $181 }
+ attribute \src "simple/issuer.py:114"
+ case 1'1
+ attribute \src "simple/issuer.py:121"
+ switch \fsm_state
+ attribute \src "simple/issuer.py:124"
+ attribute \nmigen.decoding "IDLE/0"
+ case 2'00
+ attribute \src "simple/issuer.py:146"
+ attribute \nmigen.decoding "INSN_READ/1"
+ case 2'01
+ attribute \src "simple/issuer.py:147"
+ switch { \f_busy_o }
+ attribute \src "simple/issuer.py:147"
+ case 1'1
+ attribute \src "simple/issuer.py:151"
+ case
+ assign \current_insn $183
+ end
+ attribute \src "simple/issuer.py:172"
+ attribute \nmigen.decoding "INSN_ACTIVE/2"
+ case 2'10
end
- attribute \src "simple/issuer.py:132"
- attribute \nmigen.decoding "INSN_ACTIVE/2"
- case 2'10
end
sync init
end
- process $group_13
+ attribute \src "simple/issuer.py:114"
+ wire width 1 $187
+ attribute \src "simple/issuer.py:114"
+ cell $not $188
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \core_core_terminated_o
+ connect \Y $187
+ end
+ attribute \src "simple/issuer.py:176"
+ wire width 1 $189
+ attribute \src "simple/issuer.py:176"
+ cell $ne $190
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 7
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 7
+ parameter \Y_WIDTH 1
+ connect \A \insn_type
+ connect \B 7'0000001
+ connect \Y $189
+ end
+ process $group_18
assign \core_valid 1'0
- attribute \src "simple/issuer.py:90"
- switch \fsm_state
- attribute \src "simple/issuer.py:93"
- attribute \nmigen.decoding "IDLE/0"
- case 2'00
- attribute \src "simple/issuer.py:115"
- attribute \nmigen.decoding "INSN_READ/1"
- case 2'01
- attribute \src "simple/issuer.py:116"
- switch { \f_busy_o }
- attribute \src "simple/issuer.py:116"
- case 1'1
- attribute \src "simple/issuer.py:120"
- case
- assign \core_valid 1'1
+ attribute \src "simple/issuer.py:114"
+ switch { $187 }
+ attribute \src "simple/issuer.py:114"
+ case 1'1
+ attribute \src "simple/issuer.py:121"
+ switch \fsm_state
+ attribute \src "simple/issuer.py:124"
+ attribute \nmigen.decoding "IDLE/0"
+ case 2'00
+ attribute \src "simple/issuer.py:146"
+ attribute \nmigen.decoding "INSN_READ/1"
+ case 2'01
+ attribute \src "simple/issuer.py:147"
+ switch { \f_busy_o }
+ attribute \src "simple/issuer.py:147"
+ case 1'1
+ attribute \src "simple/issuer.py:151"
+ case
+ assign \core_valid 1'1
+ end
+ attribute \src "simple/issuer.py:172"
+ attribute \nmigen.decoding "INSN_ACTIVE/2"
+ case 2'10
+ attribute \src "simple/issuer.py:173"
+ switch { \core_core_terminated_o }
+ attribute \src "simple/issuer.py:173"
+ case 1'1
+ attribute \src "simple/issuer.py:175"
+ case
+ attribute \src "simple/issuer.py:176"
+ switch { $189 }
+ attribute \src "simple/issuer.py:176"
+ case 1'1
+ assign \core_valid 1'1
+ end
+ end
end
- attribute \src "simple/issuer.py:132"
- attribute \nmigen.decoding "INSN_ACTIVE/2"
- case 2'10
- assign \core_valid 1'1
end
sync init
end
- process $group_14
+ attribute \src "simple/issuer.py:114"
+ wire width 1 $191
+ attribute \src "simple/issuer.py:114"
+ cell $not $192
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \core_core_terminated_o
+ connect \Y $191
+ end
+ process $group_19
assign \core_issue_i 1'0
- attribute \src "simple/issuer.py:90"
- switch \fsm_state
- attribute \src "simple/issuer.py:93"
- attribute \nmigen.decoding "IDLE/0"
- case 2'00
- attribute \src "simple/issuer.py:115"
- attribute \nmigen.decoding "INSN_READ/1"
- case 2'01
- attribute \src "simple/issuer.py:116"
- switch { \f_busy_o }
- attribute \src "simple/issuer.py:116"
- case 1'1
- attribute \src "simple/issuer.py:120"
- case
- assign \core_issue_i 1'1
+ attribute \src "simple/issuer.py:114"
+ switch { $191 }
+ attribute \src "simple/issuer.py:114"
+ case 1'1
+ attribute \src "simple/issuer.py:121"
+ switch \fsm_state
+ attribute \src "simple/issuer.py:124"
+ attribute \nmigen.decoding "IDLE/0"
+ case 2'00
+ attribute \src "simple/issuer.py:146"
+ attribute \nmigen.decoding "INSN_READ/1"
+ case 2'01
+ attribute \src "simple/issuer.py:147"
+ switch { \f_busy_o }
+ attribute \src "simple/issuer.py:147"
+ case 1'1
+ attribute \src "simple/issuer.py:151"
+ case
+ assign \core_issue_i 1'1
+ end
+ attribute \src "simple/issuer.py:172"
+ attribute \nmigen.decoding "INSN_ACTIVE/2"
+ case 2'10
end
- attribute \src "simple/issuer.py:132"
- attribute \nmigen.decoding "INSN_ACTIVE/2"
- case 2'10
end
sync init
end
- process $group_15
- assign \bigendian 1'0
- attribute \src "simple/issuer.py:90"
- switch \fsm_state
- attribute \src "simple/issuer.py:93"
- attribute \nmigen.decoding "IDLE/0"
- case 2'00
- attribute \src "simple/issuer.py:115"
- attribute \nmigen.decoding "INSN_READ/1"
- case 2'01
- attribute \src "simple/issuer.py:116"
- switch { \f_busy_o }
- attribute \src "simple/issuer.py:116"
- case 1'1
- attribute \src "simple/issuer.py:120"
- case
- assign \bigendian 1'0
- end
- attribute \src "simple/issuer.py:132"
- attribute \nmigen.decoding "INSN_ACTIVE/2"
- case 2'10
- end
- sync init
+ attribute \src "simple/issuer.py:114"
+ wire width 1 $193
+ attribute \src "simple/issuer.py:114"
+ cell $not $194
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \core_core_terminated_o
+ connect \Y $193
end
- attribute \src "simple/issuer.py:76"
+ attribute \src "simple/issuer.py:92"
wire width 32 \ilatch
- attribute \src "simple/issuer.py:76"
+ attribute \src "simple/issuer.py:92"
wire width 32 \ilatch$next
- process $group_16
+ process $group_20
assign \raw_opcode_in 32'00000000000000000000000000000000
- attribute \src "simple/issuer.py:90"
- switch \fsm_state
- attribute \src "simple/issuer.py:93"
- attribute \nmigen.decoding "IDLE/0"
- case 2'00
- attribute \src "simple/issuer.py:115"
- attribute \nmigen.decoding "INSN_READ/1"
- case 2'01
- attribute \src "simple/issuer.py:116"
- switch { \f_busy_o }
- attribute \src "simple/issuer.py:116"
- case 1'1
- attribute \src "simple/issuer.py:120"
- case
- assign \raw_opcode_in \current_insn
+ attribute \src "simple/issuer.py:114"
+ switch { $193 }
+ attribute \src "simple/issuer.py:114"
+ case 1'1
+ attribute \src "simple/issuer.py:121"
+ switch \fsm_state
+ attribute \src "simple/issuer.py:124"
+ attribute \nmigen.decoding "IDLE/0"
+ case 2'00
+ attribute \src "simple/issuer.py:146"
+ attribute \nmigen.decoding "INSN_READ/1"
+ case 2'01
+ attribute \src "simple/issuer.py:147"
+ switch { \f_busy_o }
+ attribute \src "simple/issuer.py:147"
+ case 1'1
+ attribute \src "simple/issuer.py:151"
+ case
+ assign \raw_opcode_in \current_insn
+ end
+ attribute \src "simple/issuer.py:172"
+ attribute \nmigen.decoding "INSN_ACTIVE/2"
+ case 2'10
+ attribute \src "simple/issuer.py:173"
+ switch { \core_core_terminated_o }
+ attribute \src "simple/issuer.py:173"
+ case 1'1
+ attribute \src "simple/issuer.py:175"
+ case
+ assign \raw_opcode_in \ilatch
+ end
end
- attribute \src "simple/issuer.py:132"
- attribute \nmigen.decoding "INSN_ACTIVE/2"
- case 2'10
- assign \raw_opcode_in \ilatch
end
sync init
end
- process $group_17
+ attribute \src "simple/issuer.py:114"
+ wire width 1 $195
+ attribute \src "simple/issuer.py:114"
+ cell $not $196
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \core_core_terminated_o
+ connect \Y $195
+ end
+ process $group_21
assign \ilatch$next \ilatch
- attribute \src "simple/issuer.py:90"
- switch \fsm_state
- attribute \src "simple/issuer.py:93"
- attribute \nmigen.decoding "IDLE/0"
- case 2'00
- attribute \src "simple/issuer.py:115"
- attribute \nmigen.decoding "INSN_READ/1"
- case 2'01
- attribute \src "simple/issuer.py:116"
- switch { \f_busy_o }
- attribute \src "simple/issuer.py:116"
- case 1'1
- attribute \src "simple/issuer.py:120"
- case
- assign \ilatch$next \current_insn
+ attribute \src "simple/issuer.py:114"
+ switch { $195 }
+ attribute \src "simple/issuer.py:114"
+ case 1'1
+ attribute \src "simple/issuer.py:121"
+ switch \fsm_state
+ attribute \src "simple/issuer.py:124"
+ attribute \nmigen.decoding "IDLE/0"
+ case 2'00
+ attribute \src "simple/issuer.py:146"
+ attribute \nmigen.decoding "INSN_READ/1"
+ case 2'01
+ attribute \src "simple/issuer.py:147"
+ switch { \f_busy_o }
+ attribute \src "simple/issuer.py:147"
+ case 1'1
+ attribute \src "simple/issuer.py:151"
+ case
+ assign \ilatch$next \current_insn
+ end
+ attribute \src "simple/issuer.py:172"
+ attribute \nmigen.decoding "INSN_ACTIVE/2"
+ case 2'10
end
- attribute \src "simple/issuer.py:132"
- attribute \nmigen.decoding "INSN_ACTIVE/2"
- case 2'10
end
attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
switch \rst
sync posedge \clk
update \ilatch \ilatch$next
end
- attribute \src "simple/issuer.py:138"
- wire width 1 $147
- attribute \src "simple/issuer.py:138"
- cell $not $148
+ attribute \src "simple/issuer.py:114"
+ wire width 1 $197
+ attribute \src "simple/issuer.py:114"
+ cell $not $198
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \core_core_terminated_o
+ connect \Y $197
+ end
+ process $group_22
+ assign \core_msr__ren 8'00000000
+ attribute \src "simple/issuer.py:114"
+ switch { $197 }
+ attribute \src "simple/issuer.py:114"
+ case 1'1
+ attribute \src "simple/issuer.py:121"
+ switch \fsm_state
+ attribute \src "simple/issuer.py:124"
+ attribute \nmigen.decoding "IDLE/0"
+ case 2'00
+ attribute \src "simple/issuer.py:146"
+ attribute \nmigen.decoding "INSN_READ/1"
+ case 2'01
+ attribute \src "simple/issuer.py:147"
+ switch { \f_busy_o }
+ attribute \src "simple/issuer.py:147"
+ case 1'1
+ attribute \src "simple/issuer.py:151"
+ case
+ assign \core_msr__ren 8'00000010
+ end
+ attribute \src "simple/issuer.py:172"
+ attribute \nmigen.decoding "INSN_ACTIVE/2"
+ case 2'10
+ end
+ end
+ sync init
+ end
+ attribute \src "simple/issuer.py:96"
+ wire width 64 \msr$199
+ attribute \src "simple/issuer.py:114"
+ wire width 1 $200
+ attribute \src "simple/issuer.py:114"
+ cell $not $201
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \core_core_terminated_o
+ connect \Y $200
+ end
+ process $group_23
+ assign \msr$199 64'0000000000000000000000000000000000000000000000000000000000000000
+ attribute \src "simple/issuer.py:114"
+ switch { $200 }
+ attribute \src "simple/issuer.py:114"
+ case 1'1
+ attribute \src "simple/issuer.py:121"
+ switch \fsm_state
+ attribute \src "simple/issuer.py:124"
+ attribute \nmigen.decoding "IDLE/0"
+ case 2'00
+ attribute \src "simple/issuer.py:146"
+ attribute \nmigen.decoding "INSN_READ/1"
+ case 2'01
+ attribute \src "simple/issuer.py:147"
+ switch { \f_busy_o }
+ attribute \src "simple/issuer.py:147"
+ case 1'1
+ attribute \src "simple/issuer.py:151"
+ case
+ assign \msr$199 \core_msr__data_o
+ end
+ attribute \src "simple/issuer.py:172"
+ attribute \nmigen.decoding "INSN_ACTIVE/2"
+ case 2'10
+ end
+ end
+ sync init
+ end
+ attribute \src "simple/issuer.py:114"
+ wire width 1 $202
+ attribute \src "simple/issuer.py:114"
+ cell $not $203
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \core_core_terminated_o
+ connect \Y $202
+ end
+ attribute \src "simple/issuer.py:95"
+ wire width 64 \cur_msr
+ attribute \src "simple/issuer.py:95"
+ wire width 64 \cur_msr$next
+ process $group_24
+ assign \core_msr 64'0000000000000000000000000000000000000000000000000000000000000000
+ attribute \src "simple/issuer.py:114"
+ switch { $202 }
+ attribute \src "simple/issuer.py:114"
+ case 1'1
+ attribute \src "simple/issuer.py:121"
+ switch \fsm_state
+ attribute \src "simple/issuer.py:124"
+ attribute \nmigen.decoding "IDLE/0"
+ case 2'00
+ attribute \src "simple/issuer.py:146"
+ attribute \nmigen.decoding "INSN_READ/1"
+ case 2'01
+ attribute \src "simple/issuer.py:147"
+ switch { \f_busy_o }
+ attribute \src "simple/issuer.py:147"
+ case 1'1
+ attribute \src "simple/issuer.py:151"
+ case
+ assign \core_msr \msr$199
+ end
+ attribute \src "simple/issuer.py:172"
+ attribute \nmigen.decoding "INSN_ACTIVE/2"
+ case 2'10
+ attribute \src "simple/issuer.py:173"
+ switch { \core_core_terminated_o }
+ attribute \src "simple/issuer.py:173"
+ case 1'1
+ attribute \src "simple/issuer.py:175"
+ case
+ assign \core_msr \cur_msr
+ end
+ end
+ end
+ sync init
+ end
+ attribute \src "simple/issuer.py:114"
+ wire width 1 $204
+ attribute \src "simple/issuer.py:114"
+ cell $not $205
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \core_core_terminated_o
+ connect \Y $204
+ end
+ process $group_25
+ assign \cur_msr$next \cur_msr
+ attribute \src "simple/issuer.py:114"
+ switch { $204 }
+ attribute \src "simple/issuer.py:114"
+ case 1'1
+ attribute \src "simple/issuer.py:121"
+ switch \fsm_state
+ attribute \src "simple/issuer.py:124"
+ attribute \nmigen.decoding "IDLE/0"
+ case 2'00
+ attribute \src "simple/issuer.py:146"
+ attribute \nmigen.decoding "INSN_READ/1"
+ case 2'01
+ attribute \src "simple/issuer.py:147"
+ switch { \f_busy_o }
+ attribute \src "simple/issuer.py:147"
+ case 1'1
+ attribute \src "simple/issuer.py:151"
+ case
+ assign \cur_msr$next \msr$199
+ end
+ attribute \src "simple/issuer.py:172"
+ attribute \nmigen.decoding "INSN_ACTIVE/2"
+ case 2'10
+ end
+ end
+ attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+ switch \rst
+ case 1'1
+ assign \cur_msr$next 64'0000000000000000000000000000000000000000000000000000000000000000
+ end
+ sync init
+ update \cur_msr 64'0000000000000000000000000000000000000000000000000000000000000000
+ sync posedge \clk
+ update \cur_msr \cur_msr$next
+ end
+ attribute \src "simple/issuer.py:114"
+ wire width 1 $206
+ attribute \src "simple/issuer.py:114"
+ cell $not $207
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \core_core_terminated_o
+ connect \Y $206
+ end
+ process $group_26
+ assign \core_cia 64'0000000000000000000000000000000000000000000000000000000000000000
+ attribute \src "simple/issuer.py:114"
+ switch { $206 }
+ attribute \src "simple/issuer.py:114"
+ case 1'1
+ attribute \src "simple/issuer.py:121"
+ switch \fsm_state
+ attribute \src "simple/issuer.py:124"
+ attribute \nmigen.decoding "IDLE/0"
+ case 2'00
+ attribute \src "simple/issuer.py:146"
+ attribute \nmigen.decoding "INSN_READ/1"
+ case 2'01
+ attribute \src "simple/issuer.py:147"
+ switch { \f_busy_o }
+ attribute \src "simple/issuer.py:147"
+ case 1'1
+ attribute \src "simple/issuer.py:151"
+ case
+ assign \core_cia \cur_pc
+ end
+ attribute \src "simple/issuer.py:172"
+ attribute \nmigen.decoding "INSN_ACTIVE/2"
+ case 2'10
+ attribute \src "simple/issuer.py:173"
+ switch { \core_core_terminated_o }
+ attribute \src "simple/issuer.py:173"
+ case 1'1
+ attribute \src "simple/issuer.py:175"
+ case
+ assign \core_cia \cur_pc
+ end
+ end
+ end
+ sync init
+ end
+ attribute \src "simple/issuer.py:114"
+ wire width 1 $208
+ attribute \src "simple/issuer.py:114"
+ cell $not $209
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \core_core_terminated_o
+ connect \Y $208
+ end
+ attribute \src "simple/issuer.py:183"
+ wire width 1 $210
+ attribute \src "simple/issuer.py:183"
+ cell $not $211
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \core_corebusy_o
- connect \Y $147
+ connect \Y $210
end
- attribute \src "simple/issuer.py:144"
- wire width 1 $149
- attribute \src "simple/issuer.py:144"
- cell $not $150
+ attribute \src "simple/issuer.py:187"
+ wire width 1 $212
+ attribute \src "simple/issuer.py:187"
+ cell $not $213
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \pc_changed
- connect \Y $149
+ connect \Y $212
end
- process $group_18
+ process $group_27
assign \core_wen 8'00000000
- attribute \src "simple/issuer.py:90"
- switch \fsm_state
- attribute \src "simple/issuer.py:93"
- attribute \nmigen.decoding "IDLE/0"
- case 2'00
- attribute \src "simple/issuer.py:115"
- attribute \nmigen.decoding "INSN_READ/1"
- case 2'01
- attribute \src "simple/issuer.py:132"
- attribute \nmigen.decoding "INSN_ACTIVE/2"
- case 2'10
- attribute \src "simple/issuer.py:138"
- switch { $147 }
- attribute \src "simple/issuer.py:138"
- case 1'1
- attribute \src "simple/issuer.py:144"
- switch { $149 }
- attribute \src "simple/issuer.py:144"
+ attribute \src "simple/issuer.py:114"
+ switch { $208 }
+ attribute \src "simple/issuer.py:114"
+ case 1'1
+ attribute \src "simple/issuer.py:121"
+ switch \fsm_state
+ attribute \src "simple/issuer.py:124"
+ attribute \nmigen.decoding "IDLE/0"
+ case 2'00
+ attribute \src "simple/issuer.py:146"
+ attribute \nmigen.decoding "INSN_READ/1"
+ case 2'01
+ attribute \src "simple/issuer.py:172"
+ attribute \nmigen.decoding "INSN_ACTIVE/2"
+ case 2'10
+ attribute \src "simple/issuer.py:173"
+ switch { \core_core_terminated_o }
+ attribute \src "simple/issuer.py:173"
case 1'1
- assign \core_wen 8'00000001
+ attribute \src "simple/issuer.py:175"
+ case
+ attribute \src "simple/issuer.py:183"
+ switch { $210 }
+ attribute \src "simple/issuer.py:183"
+ case 1'1
+ attribute \src "simple/issuer.py:187"
+ switch { $212 }
+ attribute \src "simple/issuer.py:187"
+ case 1'1
+ assign \core_wen 8'00000001
+ end
+ end
end
end
end
sync init
end
- attribute \src "simple/issuer.py:138"
- wire width 1 $151
- attribute \src "simple/issuer.py:138"
- cell $not $152
+ attribute \src "simple/issuer.py:114"
+ wire width 1 $214
+ attribute \src "simple/issuer.py:114"
+ cell $not $215
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A \core_core_terminated_o
+ connect \Y $214
+ end
+ attribute \src "simple/issuer.py:183"
+ wire width 1 $216
+ attribute \src "simple/issuer.py:183"
+ cell $not $217
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \core_corebusy_o
- connect \Y $151
+ connect \Y $216
end
- attribute \src "simple/issuer.py:144"
- wire width 1 $153
- attribute \src "simple/issuer.py:144"
- cell $not $154
+ attribute \src "simple/issuer.py:187"
+ wire width 1 $218
+ attribute \src "simple/issuer.py:187"
+ cell $not $219
parameter \A_SIGNED 0
parameter \A_WIDTH 1
parameter \Y_WIDTH 1
connect \A \pc_changed
- connect \Y $153
+ connect \Y $218
end
- process $group_19
+ process $group_28
assign \core_data_i 64'0000000000000000000000000000000000000000000000000000000000000000
- attribute \src "simple/issuer.py:90"
- switch \fsm_state
- attribute \src "simple/issuer.py:93"
- attribute \nmigen.decoding "IDLE/0"
- case 2'00
- attribute \src "simple/issuer.py:115"
- attribute \nmigen.decoding "INSN_READ/1"
- case 2'01
- attribute \src "simple/issuer.py:132"
- attribute \nmigen.decoding "INSN_ACTIVE/2"
- case 2'10
- attribute \src "simple/issuer.py:138"
- switch { $151 }
- attribute \src "simple/issuer.py:138"
- case 1'1
- attribute \src "simple/issuer.py:144"
- switch { $153 }
- attribute \src "simple/issuer.py:144"
+ attribute \src "simple/issuer.py:114"
+ switch { $214 }
+ attribute \src "simple/issuer.py:114"
+ case 1'1
+ attribute \src "simple/issuer.py:121"
+ switch \fsm_state
+ attribute \src "simple/issuer.py:124"
+ attribute \nmigen.decoding "IDLE/0"
+ case 2'00
+ attribute \src "simple/issuer.py:146"
+ attribute \nmigen.decoding "INSN_READ/1"
+ case 2'01
+ attribute \src "simple/issuer.py:172"
+ attribute \nmigen.decoding "INSN_ACTIVE/2"
+ case 2'10
+ attribute \src "simple/issuer.py:173"
+ switch { \core_core_terminated_o }
+ attribute \src "simple/issuer.py:173"
case 1'1
- assign \core_data_i \nia$134
+ attribute \src "simple/issuer.py:175"
+ case
+ attribute \src "simple/issuer.py:183"
+ switch { $216 }
+ attribute \src "simple/issuer.py:183"
+ case 1'1
+ attribute \src "simple/issuer.py:187"
+ switch { $218 }
+ attribute \src "simple/issuer.py:187"
+ case 1'1
+ assign \core_data_i \nia
+ end
+ end
end
end
end
sync init
end
+ connect \core_core_start_i 1'0
+ connect \core_core_stop_i 1'0
end
projects / soclayout.git / commitdiff