projects / soc-cocotb-sim.git / commitdiff
? search:
summary | shortlog | log | commit | commitdiff | tree
raw | patch | inline | side by side (parent: 5208414)
disallow adding verilog files
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sat, 5 Jun 2021 18:07:40 +0000 (19:07 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sat, 5 Jun 2021 18:07:40 +0000 (19:07 +0100)
.gitignore patch | blob | history

diff --git a/.gitignore b/.gitignore
index 3a8cbad6cbf74cf7a28603724255c90a1bb4a944..ff14265ba4ba023fd82e2a19b691e66895a3b3cf 100644 (file)
--- a/.gitignore
+++ b/.gitignore
@@ -2,3 +2,4 @@
 __pycache__/
 sim_build_*/
 results_*.xml
+*.v