list of hyperrams not just one

diff --git a/src/ls2.py b/src/ls2.py
index 283eb410e7c16bb924001255f8618f15cba6f205..993186f3ee55afa643b55961c06c0db2a475a082 100644 (file)
--- a/src/ls2.py
+++ b/src/ls2.py
@@ -795,8 +795,8 @@ class DDR3SoC(SoC, Elaboratable):
         # and at the moment that's just UART tx/rx.
         ports = []
         ports += [self.uart.tx_o, self.uart.rx_i]
-        if hasattr(self, "hyperram"):
-            ports += list(self.hyperram.ports())
+        for hr in self.hyperramL
+            ports += list(hr.ports())
         if hasattr(self, "ddrphy"):
             if hasattr(self.ddrphy, "pads"): # real PHY
                 ports += list(self.ddrphy.pads.fields.values())