swap over SPR1/2 to fit with microwatt SPR conventions

diff --git a/src/soc/fu/branch/formal/proof_main_stage.py b/src/soc/fu/branch/formal/proof_main_stage.py
index 2ff11b68ff945cd5915dd8ff5b6664e7266507aa..32a29651dd378ed5162fce3ae9124d56804eb165 100644 (file)
--- a/src/soc/fu/branch/formal/proof_main_stage.py
+++ b/src/soc/fu/branch/formal/proof_main_stage.py
@@ -57,10 +57,11 @@ class Driver(Elaboratable):
         cr_arr = Array([cr[(7-i)*4:(7-i)*4+4] for i in range(8)])
         cr_bit_arr = Array([cr[31-i] for i in range(32)])
 
-        cia, cr_in, spr1, ctr = dut.i.cia, dut.i.cr, dut.i.spr1, dut.i.spr2
+        cia, cr_in, spr1, spr2 = dut.i.cia, dut.i.cr, dut.i.spr1, dut.i.spr2
+        ctr = spr1
         lr_o, nia_o = dut.o.lr, dut.o.nia
 
-        comb += [spr1.eq(AnyConst(64)),
+        comb += [spr2.eq(AnyConst(64)),
                  ctr.eq(AnyConst(64)),
                  cia.eq(AnyConst(64))]
 

diff --git a/src/soc/fu/branch/pipe_data.py b/src/soc/fu/branch/pipe_data.py
index b5aa4c0ff07d56a7a744c46257c30af04f930eb0..f32872b1d4d49b4f8227ccecdc6088eb454b4067 100644 (file)
--- a/src/soc/fu/branch/pipe_data.py
+++ b/src/soc/fu/branch/pipe_data.py
@@ -5,7 +5,7 @@
     * CR is Condition Register (not an SPR)
     * SPR1 and SPR2 are all from the SPR regfile.  2 ports are needed
 
-    insn       CR  SPR1  SPR2
+    insn       CR  SPR2  SPR1
     ----       --  ----  ----
     op_b       xx  xx     xx
     op_ba      xx  xx     xx
@@ -47,8 +47,8 @@ class BranchInputData(IntegerData):
         self.cia = Signal(64, reset_less=True)  # Current Instruction Address
 
         # convenience variables.  not all of these are used at once
-        self.ctr = self.srr0 = self.hsrr0 = self.spr2
-        self.lr = self.tar = self.srr1 = self.hsrr1 = self.spr1
+        self.ctr = self.srr0 = self.hsrr0 = self.spr1
+        self.lr = self.tar = self.srr1 = self.hsrr1 = self.spr2
 
     def __iter__(self):
         yield from super().__iter__()

diff --git a/src/soc/fu/branch/test/test_pipe_caller.py b/src/soc/fu/branch/test/test_pipe_caller.py
index 541b56dd1e4b3912ca7f9023d4b1e8789e527ac6..c9e059b403399afa0a3253f0dd73add1d6b6851c 100644 (file)
--- a/src/soc/fu/branch/test/test_pipe_caller.py
+++ b/src/soc/fu/branch/test/test_pipe_caller.py
@@ -153,11 +153,11 @@ class TestRunner(FHDLTestCase):
                     yield branch.p.data_i.cia.eq(simulator.pc.CIA.value)
                     # note, here, the op will need further decoding in order
                     # to set the correct SPRs on SPR1/2/3.  op_bc* require
-                    # spr2 to be set to CTR, op_bctar require spr1 to be
-                    # set to TAR, op_bclr* require spr1 to be set to LR.
+                    # spr1 to be set to CTR, op_bctar require spr2 to be
+                    # set to TAR, op_bclr* require spr2 to be set to LR.
                     # if op_sc*, op_rf* and op_hrfid are to be added here
                     # then additional op-decoding is required, accordingly
-                    yield branch.p.data_i.spr2.eq(simulator.spr['CTR'].value)
+                    yield branch.p.data_i.spr1.eq(simulator.spr['CTR'].value)
                     print(f"cr0: {simulator.crl[0].get_range()}")
                     yield Settle()