Remove VectorAssembler files

diff --git a/TLB/src/VectorAssembler.py b/TLB/src/VectorAssembler.py
deleted file mode 100644 (file)
index ac757e9..0000000
--- a/TLB/src/VectorAssembler.py
+++ /dev/null
@@ -1,32 +0,0 @@
-from nmigen import Array, Module, Signal
-from nmigen.cli import main 
-
-class VectorAssembler():
-    """ Vector Assembler
-
-        The purpose of this module is to take a generic number of inputs
-        and cleanly combine them into one vector. While this is very much
-        possible through raw code it may result in a very unfortunate sight
-        in a yosys graph. Thus this class was born! No more will ugly loops
-        exist in my graphs! Get outta here ya goddam Lochness Monster.
-    """
-    def __init__(self, width):
-        """ Arguments:
-            * width: (bit count) The desired size of the output vector
-
-        """
-        # Internal
-        self.width = width
-
-        # Input
-        self.i = Array(Signal(1) for index in range(width))
-
-        # Output
-        self.o = Signal(width)
-
-    def elaborate(self, platform=None):
-        m = Module()
-        for index in range(self.width):
-            m.d.comb += self.o[index].eq(self.i[index])
-
-        return m

diff --git a/TLB/test/test_vector_assembler.py b/TLB/test/test_vector_assembler.py
deleted file mode 100644 (file)
index 9e9192a..0000000
--- a/TLB/test/test_vector_assembler.py
+++ /dev/null
@@ -1,53 +0,0 @@
-import sys
-sys.path.append("../src")
-sys.path.append("../../TestUtil")
-
-from nmigen.compat.sim import run_simulation
-
-from test_helper import assert_eq, assert_ne, assert_op
-from VectorAssembler import VectorAssembler
-
-# Constant that defines size of output 
-# Dont change this unless you change the input vectors to match!
-assembler_size = 4
-
-# This function allows for the easy setting of values to the VectorAssembler
-# Arguments:
-#   dut: The CamEntry being tested
-#   input: The array of single bits to be written
-def set_assembler(dut, i):
-    assert len(i) == assembler_size
-    for index in range(assembler_size):
-        # Make sure we start from the beginning of the array
-        # at least the side that makes sense from a human standpoint
-        # of reading bits
-        input_index = assembler_size - index - 1
-        yield dut.i[index].eq(i[input_index])
-    yield
-
-# Checks the output of the VectorAssembler
-# Arguments:
-#   dut: The VectorAssembler
-#   o (Output): The expected output
-#   op (Operation): (0 => ==), (1 => !=)
-def check_output(dut, o, op):
-    out_o = yield dut.o
-    assert_op("Output", out_o, o, op)
-
-def testbench(dut):
-    # Input should but bit readable from left to right
-    # with Little Endian notation
-    i = [1, 1, 0, 0]
-    output = 12
-    yield from set_assembler(dut, i)
-    yield from check_output(dut, output, 0)
-
-    i = [1, 1, 0, 1]
-    output = 13
-    yield from set_assembler(dut, i)
-    yield from check_output(dut, output, 0)
-
-if __name__ == "__main__":
-    dut = VectorAssembler(assembler_size)
-    run_simulation(dut, testbench(dut), vcd_name="Waveforms/test_vector_assembler.vcd")
-    print("VectorAssembler Unit Test Success")