append actual bit, see if coriolis issue goes away

diff --git a/src/ieee754/part_shift/part_shift_dynamic.py b/src/ieee754/part_shift/part_shift_dynamic.py
index daa1ec07a3d0df02f21b8af174fc14c98a2a007f..04a6bec09c38aee6d3ac7e9459add759aaad5f58 100644 (file)
--- a/src/ieee754/part_shift/part_shift_dynamic.py
+++ b/src/ieee754/part_shift/part_shift_dynamic.py
@@ -37,10 +37,12 @@ class ShifterMask(Elaboratable):
         bits = Signal(self.pwid, reset_less=True)
         bl = []
         for j in range(self.pwid):
+            bit = Signal(self.pwid, name="bit%d" % j, reset_less=True)
             if j != 0:
-                bl.append((~self.gates[j]) & bits[j-1])
+                comb += bit.eq((~self.gates[j]) & bl[j-1])
             else:
-                bl.append(~self.gates[j])
+                comb += bit.eq(~self.gates[j])
+            bl.append(bit)
         # XXX ARGH, really annoying: simulation bug, can't use Cat(*bl).
         for j in range(bits.shape()[0]):
             comb += bits[j].eq(bl[j])