core hazard bitvector regfiles need to be readable

immediately (combinatorial) not via sync.  allow synced option to
pass through from VirtualRegPort to RegFileArray

diff --git a/src/soc/regfile/regfiles.py b/src/soc/regfile/regfiles.py
index fc87bee924fff5cb75af431e9033a988ccef2259..234c06e7c3817d4627a28f8add1fa5d6aa88eb10 100644 (file)
--- a/src/soc/regfile/regfiles.py
+++ b/src/soc/regfile/regfiles.py
@@ -285,9 +285,9 @@ class RegFiles:
 
     def make_hazard_vec(self, rf, name):
         if isinstance(rf, VirtualRegPort):
-            vec = VirtualRegPort(rf.nregs, rf.nregs, wr2=True)
+            vec = VirtualRegPort(rf.nregs, rf.nregs, wr2=True, synced=False)
         else:
-            vec = VirtualRegPort(rf.depth, rf.depth, wr2=True)
+            vec = VirtualRegPort(rf.depth, rf.depth, wr2=True, synced=False)
         # get read/write port specs and create bitvector ports with same names
         wr_spec, rd_spec = rf.get_port_specs()
         # ok, this is complicated/fun.

diff --git a/src/soc/regfile/virtual_port.py b/src/soc/regfile/virtual_port.py
index dc5c57d6ad3f8d2f5d68384a4c005efd848b8da8..78a6124020641edca4ceae3dd89a76b6b40fb683 100644 (file)
--- a/src/soc/regfile/virtual_port.py
+++ b/src/soc/regfile/virtual_port.py
@@ -18,13 +18,13 @@ from soc.regfile.regfile import RegFileArray
 
 
 class VirtualRegPort(RegFileArray):
-    def __init__(self, bitwidth, n_regs, rd2=False, wr2=False):
+    def __init__(self, bitwidth, n_regs, rd2=False, wr2=False, synced=True):
         self.bitwidth = bitwidth
         self.nregs = n_regs
         self.rd2 = rd2 # eurgh hack
         self.wr2 = wr2 # eurgh hack
         self.regwidth = regwidth = bitwidth // n_regs
-        super().__init__(self.regwidth, n_regs)
+        super().__init__(self.regwidth, n_regs, synced=synced)
 
         # "full" depth variant of the "external" port
         self.full_wr = RecordObject([("wen", n_regs),