corrections to mantissa length, FP16/32/64 DIV work (preliminary)

diff --git a/src/ieee754/fpdiv/div0.py b/src/ieee754/fpdiv/div0.py
index 1174d01b9618c9a8a27c7b8d696c121c51cdb938..80ffc68996ff3faa6a3fcdd38596b29f1ce61012 100644 (file)
--- a/src/ieee754/fpdiv/div0.py
+++ b/src/ieee754/fpdiv/div0.py
@@ -54,6 +54,12 @@ class FPDivStage0Mod(Elaboratable):
             # do conversion here, of both self.i.a and self.i.b,
             # into DivPipeInputData dividend and divisor.
 
+            if self.pspec.width == 16:
+                extra = 3
+            elif self.pspec.width == 32:
+                extra = 4
+            elif self.pspec.width == 64:
+                extra = 3
             # the mantissas, having been de-normalised (and containing
             # a "1" in the MSB) represent numbers in the range 0.5 to
             # 0.9999999-recurring.  the min and max range of the
@@ -73,7 +79,7 @@ class FPDivStage0Mod(Elaboratable):
 
             m.d.comb += [self.o.z.e.eq(self.i.a.e - self.i.b.e + 1),
                          self.o.z.s.eq(self.i.a.s ^ self.i.b.s),
-                         self.o.dividend[len(self.i.a.m)+3:].eq(am0), # TODO: check
+                         self.o.dividend[len(self.i.a.m)+extra:].eq(am0), # TODO: check
                          self.o.divisor_radicand.eq(bm0), # TODO: check
                          self.o.operation.eq(Const(0)) # TODO check: DIV
                 ]

diff --git a/src/ieee754/fpdiv/pipeline.py b/src/ieee754/fpdiv/pipeline.py
index f9ad69e35dbe0431c8d1f8a171b7063f2356f26a..c11dbf1a938ed72d3d5e2b18951d03d216a498b3 100644 (file)
--- a/src/ieee754/fpdiv/pipeline.py
+++ b/src/ieee754/fpdiv/pipeline.py
@@ -163,7 +163,13 @@ class FPDIVMuxInOut(ReservationStations):
         # ...5 extra bits on the mantissa: MSB is zero, MSB-1 is 1
         # then there is guard, round and sticky at the LSB end.
         # also: round up to nearest radix
-        fmt.m_width = roundup(fmt.m_width + 5, log2_radix)
+        if width == 16:
+            extra = 5
+        elif width == 32:
+            extra = 6
+        elif width == 64:
+            extra = 5
+        fmt.m_width = roundup(fmt.m_width + extra, log2_radix)
         print ("width", fmt.m_width)
 
         cfg = DivPipeCoreConfig(fmt.m_width, fmt.fraction_width, log2_radix)