use a slightly different yosys initialisation sequence for memory

diff --git a/simsoc.ys b/simsoc.ys
index be21ccbb467cac02112fb8c4a07a66812b1c684e..4bf15309728a120187f6cee41f2e5b25351d9096 100644 (file)
--- a/simsoc.ys
+++ b/simsoc.ys
@@ -14,8 +14,6 @@ read_verilog  ../uart16550/rtl/verilog/uart_wb.v
 read_verilog  ./external_core_top.v
 
 delete w:$verilog_initial_trigger
-proc
-memory
 proc_prune
 proc_clean
 proc_rmdead
@@ -25,13 +23,15 @@ proc_dlatch
 proc_dff
 proc_mux
 proc_rmdead
+proc_memwr
 proc_clean
+opt_expr -keepdc
+memory_collect
 pmuxtree
 #opt_mem
 #opt_mem_priority
 #opt_mem_feedback
 #opt_clean
-#memory_collect
 extract_fa
 clean
 opt