m.d.comb += Assert((z1.v == 0) | (z1.v == 1))
- with m.Switch(opc):
- with m.Case(0b10):
- m.d.comb += Assert(z1.v == (a1.v == b1.v))
+ with m.If(a1.is_nan | b1.is_nan):
+ m.d.comb += Assert(z1.v == 0)
+ with m.Else():
+ with m.Switch(opc):
+ with m.Case(0b10):
+ m.d.comb += Assert(z1.v == (a1.v == b1.v))
class FPCMPTestCase(FHDLTestCase):
- def test_max(self):
+ def test_fpcmp(self):
for bits in [16, 32, 64]:
module = FPCMPDriver(PipelineSpec(bits, 2, 2))
self.assertFormal(module, mode="bmc", depth=4)
ab_equal = Signal()
m.d.comb += ab_equal.eq(a1.v == b1.v)
+ contains_nan = Signal()
+ m.d.comb += contains_nan.eq(a1.is_nan | b1.is_nan)
- with m.Switch(opcode):
- with m.Case(0b10):
- comb += z1.eq(ab_equal)
+ with m.If(contains_nan):
+ m.d.comb += z1.eq(0)
+ with m.Else():
+ with m.Switch(opcode):
+ with m.Case(0b10):
+ comb += z1.eq(ab_equal)
# copy the context (muxid, operator)
comb += self.o.ctx.eq(self.i.ctx)