fix LD/ST pimem issue with rising_edge detection

diff --git a/src/soc/experiment/compldst_multi.py b/src/soc/experiment/compldst_multi.py
index 5ec522685bea7d1ed473978e3e2d91d4e4b42277..7606ade59ef80bf8c9447ac569554e048cf77a01 100644 (file)
--- a/src/soc/experiment/compldst_multi.py
+++ b/src/soc/experiment/compldst_multi.py
@@ -362,6 +362,8 @@ class LDSTCompUnit(RegSpecAPI, Elaboratable):
         oper_r = CompLDSTOpSubset(name="oper_r")  # Dest register
         with m.If(self.issue_i):
             sync += oper_r.eq(self.oper_i)
+        with m.If(self.done_o):
+            sync += oper_r.eq(0)
 
         # and for LD
         ldd_r = Signal(self.data_wid, reset_less=True)  # Dest register

diff --git a/src/soc/experiment/pimem.py b/src/soc/experiment/pimem.py
index 279e8971f44a9b626ed28114332ad457b2581577..492b7c2e5125912f6ed4829437e46f9b653b5bdd 100644 (file)
--- a/src/soc/experiment/pimem.py
+++ b/src/soc/experiment/pimem.py
@@ -22,6 +22,7 @@ from nmutil.iocontrol import RecordObject
 from nmigen.utils import log2_int
 
 from nmutil.latch import SRLatch, latchregister
+from nmutil.util import rising_edge
 from soc.decoder.power_decoder2 import Data
 from soc.scoreboard.addr_match import LenExpand
 
@@ -193,8 +194,8 @@ class PortInterfaceBase(Elaboratable):
         comb += busy_edge.eq(pi.busy_o & ~busy_delay)
 
         # activate mode: only on "edge"
-        comb += ld_active.s.eq(lds & busy_edge)  # activate LD mode
-        comb += st_active.s.eq(sts & busy_edge)  # activate ST mode
+        comb += ld_active.s.eq(rising_edge(m, lds))  # activate LD mode
+        comb += st_active.s.eq(rising_edge(m, sts))  # activate ST mode
 
         # LD/ST requested activates "busy" (only if not already busy)
         with m.If(self.pi.is_ld_i | self.pi.is_st_i):