update comments

diff --git a/src/soc/decoder/isa/caller.py b/src/soc/decoder/isa/caller.py
index 83f07be0ae231b3dba2b58ca0a425f9e5fb995c0..3f94019e257c2d3203df7770122a5e05035f407b 100644 (file)
--- a/src/soc/decoder/isa/caller.py
+++ b/src/soc/decoder/isa/caller.py
@@ -235,8 +235,8 @@ class ISACaller:
 
     def TRAP(self, trap_addr=0x700):
         print ("TRAP: TODO")
-        # store PC in SRR0, set PC to 0x700
-        # store MSR in SRR1, set MSR to um errr something
+        # store CIA(+4?) in SRR0, set NIA to 0x700
+        # store MSR in SRR1, set MSR to um errr something, have to check spec
 
     def memassign(self, ea, sz, val):
         self.mem.memassign(ea, sz, val)