yield dut.int_store_i.eq(0)
- for i in range(1):
+ for i in range(100):
# set random values in the registers
for i in range(1, dut.n_regs):
# create some instructions (some random, some regression tests)
instrs = []
- if False:
- for i in range(10):
+ if True:
+ for i in range(20):
src1 = randint(1, dut.n_regs-1)
src2 = randint(1, dut.n_regs-1)
while True:
instrs.append((1, 1, 1, 1))
instrs.append((1, 5, 3, 0))
- if True:
- instrs.append( (7, 1, 2, 0) )
- instrs.append( (1, 1, 4, 2) )
- instrs.append( (2, 3, 2, 2) )
- instrs.append( (5, 3, 1, 0) )
- instrs.append( (7, 3, 5, 2) )
- instrs.append( (1, 2, 6, 2) )
+ if False:
+ # very weird failure
instrs.append( (5, 2, 5, 2) )
- instrs.append( (2, 2, 3, 0) )
+ instrs.append( (2, 6, 3, 0) )
instrs.append( (4, 2, 2, 1) )
- instrs.append( (2, 4, 6, 1) )
# issue instruction(s), wait for issue to be free before proceeding
for i, (src1, src2, dest, op) in enumerate(instrs):
# connect up hazard checks: read-after-write and write-after-read
m.d.comb += dest_c.hazard_i.eq(self.rd_pend_i) # read-after-write
- with m.If(~selfhazard):
- m.d.comb += src1_c.hazard_i.eq(self.wr_pend_i) # write-after-read
- m.d.comb += src2_c.hazard_i.eq(self.wr_pend_i) # write-after-read
+ m.d.comb += src1_c.hazard_i.eq(self.wr_pend_i) # write-after-read
+ m.d.comb += src2_c.hazard_i.eq(self.wr_pend_i) # write-after-read
# connect fwd / reg-sel outputs
for c, fwd, rsel in [(dest_c, self.dest_fwd_o, self.dest_rsel_o),
from nmigen.compat.sim import run_simulation
from nmigen.cli import verilog, rtlil
-from nmigen import Module, Signal, Elaboratable, Array, Cat
+from nmigen import Module, Signal, Elaboratable, Array, Cat, Const
#from nmutil.latch import SRLatch
from .fu_dep_cell import FUDependenceCell
rd_pend_i = []
wr_pend_i = []
for x in range(self.n_fu_col):
+ if x == y: # ignore hazards on the diagonal: self-against-self
+ dummyrd = Signal(reset_less=True)
+ dummywr = Signal(reset_less=True)
+ rd_pend_i.append(dummyrd)
+ wr_pend_i.append(dummywr)
+ continue
dc = dm[x][y]
# accumulate cell rd_pend/wr_pend/go_rd/go_wr
rd_pend_i.append(dc.rd_pend_i)