do not need FAST regs in MMU

diff --git a/src/soc/fu/mmu/pipe_data.py b/src/soc/fu/mmu/pipe_data.py
index 2c2a45ca7b3e7814e76cd1d77699cad56529d3f2..1b7066d4dfabfff72640f1c31e23246db4efa28d 100644 (file)
--- a/src/soc/fu/mmu/pipe_data.py
+++ b/src/soc/fu/mmu/pipe_data.py
@@ -19,7 +19,6 @@ class MMUInputData(IntegerData):
     regspec = [('INT', 'ra', '0:63'),        # RA
                ('INT', 'rb', '0:63'),        # RB
                ('SPR', 'spr1', '0:63'),      # MMU (slow)
-               ('FAST', 'fast1', '0:63'),    # MMU (fast: LR, CTR etc)
                ]   
     def __init__(self, pspec):
         super().__init__(pspec, False)
@@ -31,7 +30,6 @@ class MMUInputData(IntegerData):
 class MMUOutputData(IntegerData):
     regspec = [('INT', 'o', '0:63'),        # RT
                ('SPR', 'spr1', '0:63'),     # MMU (slow)
-               ('FAST', 'fast1', '0:63'),   # MMU (fast: LR, CTR etc)
                ]
     def __init__(self, pspec):
         super().__init__(pspec, True)