add stubs
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Mon, 25 May 2020 15:24:10 +0000 (16:24 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Mon, 25 May 2020 15:24:10 +0000 (16:24 +0100)
src/soc/experiment/compalu_multi.py

index 2aac8246c99287aa87b5b4a82bbb622fd878d79b..7c9b8b07d0ae9ca325af4ac20425653f019bf87f 100644 (file)
@@ -412,6 +412,13 @@ class CompUnitParallelTest:
             print("    Monitor: busy_o =", busy_o)
             yield
 
+    def rd(self, rd_idx):
+        # monitor self.dut.rd.req[rd_idx] and sets dut.rd.go[idx] for one cycle
+        pass
+
+    def wr(self, wr_idx):
+        # monitor self.dut.wr.req[rd_idx] and sets dut.wr.go[idx] for one cycle
+        pass
 
 def test_compunit_regspec1():
     from alu_hier import ALU
@@ -438,7 +445,10 @@ def test_compunit_regspec1():
 
     test = CompUnitParallelTest(dut)
     run_simulation(dut, [test.driver(),
-                         test.monitor()
+                         test.monitor(),
+                         test.rd(0), # one read port (a)
+                         test.rd(1), # one read port (b)
+                         test.wr(0)  # one write port (o)
                         ],
                    vcd_name="test_compunit_parallel.vcd")