fix imports

diff --git a/src/ieee754/div_rem_sqrt_rsqrt/div_pipe.py b/src/ieee754/div_rem_sqrt_rsqrt/div_pipe.py
index 28eacbd665d0b929fe07cb03bdd19f5b99825c91..353ccc4fc7594f91cfbf90000cfc8ad3ced04f59 100644 (file)
--- a/src/ieee754/div_rem_sqrt_rsqrt/div_pipe.py
+++ b/src/ieee754/div_rem_sqrt_rsqrt/div_pipe.py
@@ -2,8 +2,14 @@
 # See Notices.txt for copyright information
 """ div/rem/sqrt/rsqrt pipeline. """
 
-from .core import (DivPipeCoreConfig, DivPipeCoreInputData,
-                   DivPipeCoreInterstageData, DivPipeCoreOutputData)
+from ieee754.div_rem_sqrt_rsqrt.core import (DivPipeCoreConfig,
+                                             DivPipeCoreInputData,
+                                             DivPipeCoreInterstageData,
+                                             DivPipeCoreOutputData,
+                                             DivPipeCoreSetupStage,
+                                             DivPipeCoreCalculateStage,
+                                             DivPipeCoreFinalStage,
+                                            )
 from ieee754.fpcommon.getop import FPPipeContext
 from ieee754.fpcommon.fpbase import FPFormat, FPNumBaseRecord
 
@@ -61,7 +67,7 @@ class DivPipeBaseData:
 
     def eq(self, rhs):
         """ Assign member signals. """
-        return [self.z.eq(rhz.z, self.out_do_z.eq(i.out_do_z), self.oz.eq(i.oz),
+        return [self.z.eq(rhs.z), self.out_do_z.eq(i.out_do_z), self.oz.eq(i.oz),
                 self.ctx.eq(i.ctx)]
 
 

diff --git a/src/ieee754/fpcommon/fpbase.py b/src/ieee754/fpcommon/fpbase.py
index 860d02dcb89501c509f085289dbc60c7b1b41844..5f7df717e374719c0b8b1ec1c2eee13feda427f0 100644 (file)
--- a/src/ieee754/fpcommon/fpbase.py
+++ b/src/ieee754/fpcommon/fpbase.py
@@ -51,8 +51,6 @@ class FPFormat:
         :param width: bit-width of requested format.
         :returns: the requested ``FPFormat`` instance.
         """
-        if not instanceof(width, int):
-            raise TypeError()
         if width == 16:
             return FPFormat(5, 10)
         if width == 32:

diff --git a/src/ieee754/fpdiv/div0.py b/src/ieee754/fpdiv/div0.py
index 5f30d632b69f144104d0234fea60fbc9334815e1..35cc41aaef42e1e1607d632eb9f71fd25b0b2a34 100644 (file)
--- a/src/ieee754/fpdiv/div0.py
+++ b/src/ieee754/fpdiv/div0.py
@@ -92,7 +92,7 @@ class FPDivStage0Mod(Elaboratable):
                         ]
 
             m.d.comb += [self.o.z.e.eq(self.i.a.e - self.i.b.e + 1),
-                         self.o.z.s.eq(self.i.a.s ^ self.i.b.s)
+                         self.o.z.s.eq(self.i.a.s ^ self.i.b.s),
                          self.o.dividend.eq(am0), # TODO: check
                          self.o.divisor_radicand.eq(bm0), # TODO: check
                          self.o.operation.eq(Const(0)) # TODO check: DIV

diff --git a/src/ieee754/fpdiv/divstages.py b/src/ieee754/fpdiv/divstages.py
index e3b31d0df17848f3fa63d5edca435f5411d1891f..6a65f0050b6f587f6d29b80feefbe83e8ce9f9ca 100644 (file)
--- a/src/ieee754/fpdiv/divstages.py
+++ b/src/ieee754/fpdiv/divstages.py
@@ -74,7 +74,7 @@ class FPDivStagesSetup(FPState, SimpleHandshake):
         m.next = "normalise_1"
 
 
-class FPDivStagesIntermediary(FPState, SimpleHandshake):
+class FPDivStagesIntermediate(FPState, SimpleHandshake):
 
     def __init__(self, pspec, n_stages, stage_offs):
         FPState.__init__(self, "divintermediate")

diff --git a/src/ieee754/fpdiv/pipeline.py b/src/ieee754/fpdiv/pipeline.py
index 5bdbaf5f93350b762349421aff01e0044bf1be82..4e4836333b5e39a084144a4fbc0fd3d056c873b6 100644 (file)
--- a/src/ieee754/fpdiv/pipeline.py
+++ b/src/ieee754/fpdiv/pipeline.py
@@ -64,6 +64,7 @@ from nmutil.concurrentunit import ReservationStations, num_bits
 
 from ieee754.fpcommon.getop import FPADDBaseData
 from ieee754.fpcommon.denorm import FPSCData
+from ieee754.fpcommon.fpbase import FPFormat
 from ieee754.fpcommon.pack import FPPackData
 from ieee754.fpcommon.normtopack import FPNormToPack
 from ieee754.fpdiv.specialcases import FPDIVSpecialCasesDeNorm