m = Module()
r_data = self.stage.ispec() # input type
- result = self.stage.ospec() # output data
if hasattr(self.stage, "setup"):
self.stage.setup(m, r_data)
p_i_valid = Signal(reset_less=True)
m.d.comb += p_i_valid.eq(self.p.i_valid_logic())
- m.d.comb += eq(result, self.stage.process(r_data))
m.d.comb += self.n.o_valid.eq(self._data_valid)
m.d.comb += self.p.o_ready.eq(~self._data_valid | self.n.i_ready)
m.d.sync += self._data_valid.eq(p_i_valid | \
(~self.n.i_ready & self._data_valid))
with m.If(self.p.i_valid & self.p.o_ready):
m.d.sync += eq(r_data, self.p.i_data)
- m.d.comb += eq(self.n.o_data, result)
+ m.d.comb += eq(self.n.o_data, self.stage.process(r_data))
return m