add comments and start of elaborate

diff --git a/src/soc/experiment/l0_cache.py b/src/soc/experiment/l0_cache.py
index 1e85beae4b1f2af3a70c98620960c0b80708f99b..09d0e5f18343f1186040da259cde94e5f03fa558 100644 (file)
--- a/src/soc/experiment/l0_cache.py
+++ b/src/soc/experiment/l0_cache.py
@@ -128,6 +128,14 @@ class DualPortSplitter(Elaboratable):
 
     once that is done each pair of ports may be wired directly
     to the dual ports of L0CacheBuffer
+
+    The split is carried out so that, regardless of alignment or
+    mis-alignment, outgoing PortInterface[0] takes bit 4 == 0
+    of the address, whilst outgoing PortInterface[1] takes
+    bit 4 == 1.
+
+    PortInterface *may* need to be changed so that the length is
+    a binary number (accepting values 1-16).
     """
     def __init__(self):
         self.outp = []
@@ -135,6 +143,9 @@ class DualPortSplitter(Elaboratable):
         self.outp[1] = PortInterface(name="outp_1")
         self.inp     = PortInterface(name="inp")
 
+    def elaborate(self, platform):
+        splitter = LDSTSplitter(64, 48, 4)
+
 
 class DataMergerRecord(Record):
     """