store CR lut result in temporary

diff --git a/src/soc/fu/cr/main_stage.py b/src/soc/fu/cr/main_stage.py
index 00417651c8fa9c08221224223d651db7a1e6e4c2..2ec877e5e8e02c33cde39f033f236163c258c02c 100644 (file)
--- a/src/soc/fu/cr/main_stage.py
+++ b/src/soc/fu/cr/main_stage.py
@@ -108,8 +108,10 @@ class CRMainStage(PipeModBase):
 
                 # Use the two input bits to look up the result in the LUT
                 idx = Signal(2, reset_less=True)
+                lv = Signal(1, reset_less=True)
                 comb += idx.eq(Cat(cr_arr[bb], cr_arr[ba]))
-                comb += cr_out_arr[bt].eq(lut[idx])
+                comb += lv.eq(lut[idx])
+                comb += cr_out_arr[bt].eq(lv)
 
             ##### mtcrf #####
             with m.Case(InternalOp.OP_MTCRF):