print("oe:", oe, oe_ok)
+def teststate_check_regs(dut, states, test, code):
+ """teststate_check_regs: compares a set of Power ISA objects
+ to check if they have the same "state" (registers only, at the moment)
+ """
+ slist = []
+ for stype, totest in states.items():
+ state = yield from TestState(stype, totest, dut, code)
+ slist.append(state)
+ for i in range(len(slist)-1):
+ state, against = slist[i], slist[i+1]
+ state.compare(against)
+
+
def check_regs(dut, sim, core, test, code):
# create the two states and compare
testdic = {'sim': sim, 'hdl': core}
- simstate = yield from TestState('sim', testdic, dut, code)
- corestate = yield from TestState('hdl', testdic, dut, code)
- simstate.compare(corestate)
+ yield from teststate_check_regs(dut, testdic, test, code)
def wait_for_busy_hi(cu):
print("class hdl pc", hex(self.pc))
-def TestState(state_type, state_dic, dut, code):
- state_factory = {'sim': SimState, 'hdl': HDLState}
+global state_factory
+state_factory = {'sim': SimState, 'hdl': HDLState}
+
+
+def TestState(state_type, to_test, dut, code):
state_class = state_factory[state_type]
- state = state_class(state_dic[state_type])
+ state = state_class(to_test)
+ state.to_test = to_test
state.dut = dut
state.state_type = state_type
state.code = code