icache.py add missing comb signal assignments per https://bugs.libre-soc.org/show_bug...

diff --git a/src/soc/experiment/icache.py b/src/soc/experiment/icache.py
index 46ba5d0cddb409c4362041578255bc532a9a7e5d..75361d9bdc8781969e52e1e8c7a1ec29987ae941 100644 (file)
--- a/src/soc/experiment/icache.py
+++ b/src/soc/experiment/icache.py
@@ -761,6 +761,12 @@ class ICache(Elaboratable):
             comb += req_is_hit.eq(is_hit)
             comb += req_is_miss.eq(~is_hit)
 
+        with m.Else():
+            comb += req_is_hit.eq(0)
+            comb += req_is_miss.eq(0)
+
+        comb += req_hit_way.eq(hit_way)
+
         # The way to replace on a miss
         with m.If(r.state == State.CLR_TAG):
             comb += replace_way.eq(plru_victim[r.store_index])