# ========= Interface declarations ================ #
-mux_interface=MuxInterface('cell',
+mux_interface = MuxInterface('cell',
[{'name': 'mux', 'ready': False, 'enabled': False,
'bitspec': '{1}', 'action': True}])
-io_interface=IOInterface(
+io_interface = IOInterface(
'io',
[{'name': 'cell_out', 'enabled': True, },
{'name': 'cell_outen', 'enabled': True, 'outenmode': True, },
# basic test
if __name__ == '__main__':
- uartinterface_decl=Interface('uart',
+ uartinterface_decl = Interface('uart',
[{'name': 'rx'},
{'name': 'tx', 'action': True},
])
- twiinterface_decl=Interface('twi',
+ twiinterface_decl = Interface('twi',
[{'name': 'sda', 'outen': True},
{'name': 'scl', 'outen': True},
])
return "%(name)s%(ifacenum)dEnd" % locals()
def axi_reg_def(self, start, name, ifacenum):
- name=name.upper()
- offs=self.num_axi_regs32() * 4 * 16
- end=start + offs - 1
- bname=self.axibase(name, ifacenum)
- bend=self.axiend(name, ifacenum)
+ name = name.upper()
+ offs = self.num_axi_regs32() * 4 * 16
+ end = start + offs - 1
+ bname = self.axibase(name, ifacenum)
+ bend = self.axiend(name, ifacenum)
comment = "%d 32-bit regs" % self.num_axi_regs32()
return (" `define%(bname)s 'h%(start)08X\n"
" `define%(bend)s 'h%(end)08X // %(comment)s" % locals(),