update comments, link/setup of peripherals

(all done manually at the moment, TODO a dev-env-setup)

diff --git a/src/ls2.py b/src/ls2.py
index 64c5126035dee2a938d8c34acae903c799dea98a..98fe67b79e8c75a9abef67605348ee21e6441d99 100644 (file)
--- a/src/ls2.py
+++ b/src/ls2.py
@@ -519,7 +519,8 @@ class DDR3SoC(SoC, Elaboratable):
 
         # add uart16550 verilog source. assumes a directory
         # structure where ls2 has been checked out in a common
-        # subdirectory as https://github.com/freecores/uart16550
+        # subdirectory as:
+        # git clone https://github.com/freecores/uart16550
         opencores_16550 = "../../uart16550/rtl/verilog"
         pth = os.path.split(__file__)[0]
         pth = os.path.join(pth, opencores_16550)
@@ -528,10 +529,10 @@ class DDR3SoC(SoC, Elaboratable):
         self.uart.add_verilog_source(fname, platform)
 
         if hasattr(self, "spi0"):
-            # add Tercel verilog source. assumes a directory
-            # structure where microwatt has been checked out in a common
-            # subdirectory as https://git.libre-soc.org/git/microwatt.git
-            raptor_tercel = "../../microwatt/tercel"
+            # add Tercel verilog source. assumes a directory structure where
+            # microwatt has been checked out in a common subdirectory with:
+            # git clone https://git.libre-soc.org/git/microwatt.git tercel-qspi
+            raptor_tercel = "../../tercel-qspi/tercel"
             pth = os.path.split(__file__)[0]
             pth = os.path.join(pth, raptor_tercel)
             fname = os.path.abspath(pth)
@@ -541,7 +542,8 @@ class DDR3SoC(SoC, Elaboratable):
         if hasattr(self, "eth0"):
             # add EthMAC verilog source. assumes a directory
             # structure where the opencores ethmac has been checked out
-            # in a common subdirectory as https://github.com/freecores/ethmac
+            # in a common subdirectory as:
+            # git clone https://github.com/freecores/ethmac
             opencores_ethmac = "../../ethmac/rtl/verilog"
             pth = os.path.split(__file__)[0]
             pth = os.path.join(pth, opencores_ethmac)