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change name to not clash with cell name add1
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 20 Feb 2020 20:34:28 +0000 (20:34 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 20 Feb 2020 20:34:28 +0000 (20:34 +0000)
src/ieee754/part/partsig.py patch | blob | history

diff --git a/src/ieee754/part/partsig.py b/src/ieee754/part/partsig.py
index bf0e85bc06bd2c4b2b1a49b7c748243c26d96d9f..75417cfdb06c121613c0883a709779bd205131bd 100644 (file)
--- a/src/ieee754/part/partsig.py
+++ b/src/ieee754/part/partsig.py
@@ -51,7 +51,7 @@ class PartitionedSignal:
 
     def get_modname(self, category):
         self.modnames[category] += 1
-        return "%s%d" % (category, self.modnames[category])
+        return "%s_%d" % (category, self.modnames[category])
 
     def eq(self, val):
         return self.sig.eq(getsig(val))