move coresync clock synchronisation into HDLRunner

diff --git a/src/soc/simple/test/test_runner.py b/src/soc/simple/test/test_runner.py
index 223d947864b350767e2d112dae46736b6844d0e9..130462e0aff9a460c89696c732cd05bfd0a725c7 100644 (file)
--- a/src/soc/simple/test/test_runner.py
+++ b/src/soc/simple/test/test_runner.py
@@ -198,6 +198,10 @@ class HDLRunner(StateRunner):
         comb += self.issuer.pc_i.data.eq(self.pc_i)
         comb += self.issuer.svstate_i.data.eq(self.svstate_i)
 
+        # run core clock at same rate as test clock
+        intclk = ClockSignal("coresync")
+        comb += intclk.eq(ClockSignal())
+
     def prepare_for_test(self, test):
         self.test = test
 
@@ -377,10 +381,6 @@ class TestRunner(FHDLTestCase):
         if self.run_sim:
             simrun = SimRunner(self, m, pspec)
 
-        # run core clock at same rate as test clock
-        intclk = ClockSignal("coresync")
-        comb += intclk.eq(ClockSignal())
-
         # nmigen Simulation - everything runs around this, so it
         # still has to be created.
         sim = Simulator(m)