fix partsig gt test, add ge test

diff --git a/src/ieee754/part/test/test_partsig.py b/src/ieee754/part/test/test_partsig.py
index 1ec0cab40ec6b47ffca21f23645a8e1fd091e74d..908a3e91b04b98bcf71d474958c6c2fadcd86f57 100644 (file)
--- a/src/ieee754/part/test/test_partsig.py
+++ b/src/ieee754/part/test/test_partsig.py
@@ -30,6 +30,7 @@ class TestAddMod(Elaboratable):
         self.add_output = Signal(width)
         self.eq_output = Signal(len(partpoints)+1)
         self.gt_output = Signal(len(partpoints)+1)
+        self.ge_output = Signal(len(partpoints)+1)
 
     def elaborate(self, platform):
         m = Module()
@@ -37,6 +38,7 @@ class TestAddMod(Elaboratable):
         self.b.set_module(m)
         m.d.comb += self.gt_output.eq(self.a > self.b)
         m.d.comb += self.eq_output.eq(self.a == self.b)
+        m.d.comb += self.ge_output.eq(self.a >= self.b)
         m.d.comb += self.add_output.eq(self.a + self.b)
 
         return m
@@ -145,17 +147,55 @@ class TestPartitionPoints(unittest.TestCase):
                             # OR y with the lowest set bit in the mask
                             y |= (maskbit_list[i] & ~(maskbit_list[i]-1))
                     # check the result
-                    outval = (yield module.eq_output)
+                    outval = (yield module.gt_output)
                     msg = f"{msg_prefix}: 0x{a:X} == 0x{b:X}" + \
                         f" => 0x{y:X} != 0x{outval:X}, masklist %s"
                     #print ((msg % str(maskbit_list)).format(locals()))
                     self.assertEqual(y, outval, msg % str(maskbit_list))
             yield part_mask.eq(0)
-            yield from test_eq("16-bit", 0b1111)
+            yield from test_gt("16-bit", 0b1111)
             yield part_mask.eq(0b10)
-            yield from test_eq("8-bit", 0b1100, 0b0011)
+            yield from test_gt("8-bit", 0b1100, 0b0011)
             yield part_mask.eq(0b1111)
-            yield from test_eq("4-bit", 0b1000, 0b0100, 0b0010, 0b0001)
+            yield from test_gt("4-bit", 0b1000, 0b0100, 0b0010, 0b0001)
+
+            def test_ge(msg_prefix, *maskbit_list):
+                for a, b in [(0x0000, 0x0000),
+                             (0x1234, 0x1234),
+                             (0xABCD, 0xABCD),
+                             (0xFFFF, 0x0000),
+                             (0x0000, 0x0000),
+                             (0xFFFF, 0xFFFF),
+                             (0x0000, 0xFFFF)]:
+                    yield module.a.eq(a)
+                    yield module.b.eq(b)
+                    yield Delay(0.1e-6)
+                    # convert to mask_list
+                    mask_list = []
+                    for mb in maskbit_list:
+                        v = 0
+                        for i in range(4):
+                            if mb & (1<<i):
+                                v |= 0xf << (i*4)
+                        mask_list.append(v)
+                    y = 0
+                    # do the partitioned tests
+                    for i, mask in enumerate(mask_list):
+                        if (a & mask) >= (b & mask):
+                            # OR y with the lowest set bit in the mask
+                            y |= (maskbit_list[i] & ~(maskbit_list[i]-1))
+                    # check the result
+                    outval = (yield module.ge_output)
+                    msg = f"{msg_prefix}: 0x{a:X} == 0x{b:X}" + \
+                        f" => 0x{y:X} != 0x{outval:X}, masklist %s"
+                    #print ((msg % str(maskbit_list)).format(locals()))
+                    self.assertEqual(y, outval, msg % str(maskbit_list))
+            yield part_mask.eq(0)
+            yield from test_ge("16-bit", 0b1111)
+            yield part_mask.eq(0b10)
+            yield from test_ge("8-bit", 0b1100, 0b0011)
+            yield part_mask.eq(0b1111)
+            yield from test_ge("4-bit", 0b1000, 0b0100, 0b0010, 0b0001)
 
         sim.add_process(async_process)
         sim.run()