convert branch pipeline to use msr/cia as immediates

diff --git a/src/soc/decoder/isa/caller.py b/src/soc/decoder/isa/caller.py
index 85b8aa5caa0532c7faf9850fc3eb5e9876c9007f..fce89a441f08a2deda15e2d4a24385a1e4ac1c6c 100644 (file)
--- a/src/soc/decoder/isa/caller.py
+++ b/src/soc/decoder/isa/caller.py
@@ -500,6 +500,8 @@ class ISACaller:
 
         yield self.dec2.dec.raw_opcode_in.eq(ins & 0xffffffff)
         yield self.dec2.dec.bigendian.eq(self.bigendian)
+        yield self.dec2.msr.eq(self.msr.value)
+        yield self.dec2.cia.eq(pc)
 
     def execute_one(self):
         """execute one instruction

diff --git a/src/soc/fu/branch/br_input_record.py b/src/soc/fu/branch/br_input_record.py
index 697b8fb42876e56b9b9307596e0c6e90a796637a..2e0a1e1e0141770877f93f4b6fde7eb0a4396717 100644 (file)
--- a/src/soc/fu/branch/br_input_record.py
+++ b/src/soc/fu/branch/br_input_record.py
@@ -12,7 +12,8 @@ class CompBROpSubset(CompOpSubsetBase):
     grab subsets.
     """
     def __init__(self, name=None):
-        layout = (('insn_type', MicrOp),
+        layout = (('cia', 64), # PC "state"
+                  ('insn_type', MicrOp),
                   ('fn_unit', Function),
                   ('insn', 32),
                   ('imm_data', Layout((("imm", 64), ("imm_ok", 1)))),

diff --git a/src/soc/fu/branch/main_stage.py b/src/soc/fu/branch/main_stage.py
index d6425f031ad152a976fa8a0735fdf8019e0c3bdd..39631afdca281c1b280765281cbae5cb000b35b3 100644 (file)
--- a/src/soc/fu/branch/main_stage.py
+++ b/src/soc/fu/branch/main_stage.py
@@ -72,7 +72,7 @@ class BranchMainStage(PipeModBase):
         comb = m.d.comb
         op = self.i.ctx.op
         lk = op.lk # see PowerDecode2 as to why this is done
-        cr, cia, ctr, fast1 = self.i.cr, self.i.cia, self.i.ctr, self.i.fast1
+        cr, cia, ctr, fast1 = self.i.cr, op.cia, self.i.ctr, self.i.fast1
         fast2 = self.i.fast2
         nia_o, lr_o, ctr_o = self.o.nia, self.o.lr, self.o.ctr
 

diff --git a/src/soc/fu/branch/pipe_data.py b/src/soc/fu/branch/pipe_data.py
index fb01775d65eb7c0ce56e162b42800e72f8eaeb17..9bbe0552243c7035076eb11d001ff96519ab7f10 100644 (file)
--- a/src/soc/fu/branch/pipe_data.py
+++ b/src/soc/fu/branch/pipe_data.py
@@ -34,7 +34,7 @@ class BranchInputData(IntegerData):
     regspec = [('FAST', 'fast1', '0:63'), # see table above, SPR1
                ('FAST', 'fast2', '0:63'), # see table above, SPR2
                ('CR', 'cr_a', '0:3'),    # Condition Register(s) CR0-7
-               ('FAST', 'cia', '0:63')]  # Current Instruction Address
+               ]
     def __init__(self, pspec):
         super().__init__(pspec, False)
 

diff --git a/src/soc/fu/branch/test/test_pipe_caller.py b/src/soc/fu/branch/test/test_pipe_caller.py
index 70796198d75fcaedd8c450ab186279eca371a3f3..b29d8a45a99eca8d0f40798f0818a0669e44f2c0 100644 (file)
--- a/src/soc/fu/branch/test/test_pipe_caller.py
+++ b/src/soc/fu/branch/test/test_pipe_caller.py
@@ -55,7 +55,7 @@ def get_cu_inputs(dec2, sim):
     res = {}
 
     # CIA (PC)
-    res['cia'] = sim.pc.CIA.value
+    #res['cia'] = sim.pc.CIA.value
 
     yield from ALUHelpers.get_sim_fast_spr1(res, sim, dec2)
     yield from ALUHelpers.get_sim_fast_spr2(res, sim, dec2)
@@ -77,6 +77,13 @@ class BranchTestCase(FHDLTestCase):
                       initial_regs, initial_sprs, initial_cr)
         self.test_data.append(tc)
 
+    def test_0_regression_unconditional(self):
+        for i in range(2):
+            imm = random.randrange(-1<<23, (1<<23)-1) * 4
+            lst = [f"bl {imm}"]
+            initial_regs = [0] * 32
+            self.run_tst_program(Program(lst, bigendian), initial_regs)
+
     def test_unconditional(self):
         choices = ["b", "ba", "bl", "bla"]
         for i in range(20):
@@ -174,7 +181,9 @@ class TestRunner(FHDLTestCase):
                 gen = program.generate_instructions()
                 instructions = list(zip(gen, program.assembly.splitlines()))
 
-                index = (simulator.pc.CIA.value - initial_cia)//4
+                pc = simulator.pc.CIA.value
+                msr = simulator.msr.value
+                index = (pc - initial_cia)//4
                 while index < len(instructions) and index >= 0:
                     print(index)
                     ins, code = instructions[index]
@@ -184,6 +193,8 @@ class TestRunner(FHDLTestCase):
 
                     # ask the decoder to decode this binary data (endian'd)
                     yield pdecode2.dec.bigendian.eq(bigendian)  # little / big?
+                    yield pdecode2.msr.eq(msr) # set MSR in pdecode2
+                    yield pdecode2.cia.eq(pc) # set PC in pdecode2
                     yield instruction.eq(ins)          # raw binary instr.
                     # note, here, the op will need further decoding in order
                     # to set the correct SPRs on SPR1/2/3.  op_bc* require
@@ -192,6 +203,8 @@ class TestRunner(FHDLTestCase):
                     # if op_sc*, op_rf* and op_hrfid are to be added here
                     # then additional op-decoding is required, accordingly
                     yield Settle()
+                    lk = yield pdecode2.e.do.lk
+                    print ("lk:", lk)
                     yield from self.set_inputs(branch, pdecode2, simulator)
                     fn_unit = yield pdecode2.e.do.fn_unit
                     self.assertEqual(fn_unit, Function.BRANCH.value, code)
@@ -200,14 +213,15 @@ class TestRunner(FHDLTestCase):
                     opname = code.split(' ')[0]
                     prev_nia = simulator.pc.NIA.value
                     yield from simulator.call(opname)
-                    index = (simulator.pc.CIA.value - initial_cia)//4
+                    pc = simulator.pc.CIA.value
+                    msr = simulator.msr.value
+                    index = (pc - initial_cia)//4
 
                     yield from self.assert_outputs(branch, pdecode2,
                                                    simulator, prev_nia, code)
 
         sim.add_sync_process(process)
-        with sim.write_vcd("simulator.vcd", "simulator.gtkw",
-                            traces=[]):
+        with sim.write_vcd("branch_simulator.vcd"):
             sim.run()
 
     def assert_outputs(self, branch, dec2, sim, prev_nia, code):
@@ -234,7 +248,6 @@ class TestRunner(FHDLTestCase):
 
         inp = yield from get_cu_inputs(dec2, sim)
 
-        yield from ALUHelpers.set_cia(branch, dec2, inp)
         yield from ALUHelpers.set_fast_spr1(branch, dec2, inp)
         yield from ALUHelpers.set_fast_spr2(branch, dec2, inp)
         yield from ALUHelpers.set_cr_a(branch, dec2, inp)

diff --git a/src/soc/fu/spr/test/test_pipe_caller.py b/src/soc/fu/spr/test/test_pipe_caller.py
index 3ba1ac3dff97afa9ce637a599e5337f27363a174..e20c55e0ff5a4d00b1b967be588b6d0070f6a8f5 100644 (file)
--- a/src/soc/fu/spr/test/test_pipe_caller.py
+++ b/src/soc/fu/spr/test/test_pipe_caller.py
@@ -210,6 +210,7 @@ class TestRunner(FHDLTestCase):
                     # ask the decoder to decode this binary data (endian'd)
                     yield pdecode2.dec.bigendian.eq(bigendian)  # little / big?
                     yield pdecode2.msr.eq(msr) # set MSR in pdecode2
+                    yield pdecode2.cia.eq(pc) # set PC in pdecode2
                     yield instruction.eq(ins)          # raw binary instr.
                     yield Settle()