add convenience name to branch main stage and branch output data

diff --git a/src/soc/branch/main_stage.py b/src/soc/branch/main_stage.py
index 7fde08b04c43afff00fd6e51800cd34c307e17df..d1dfbbda278686db3615a2409b2f09f16055e68c 100644 (file)
--- a/src/soc/branch/main_stage.py
+++ b/src/soc/branch/main_stage.py
@@ -71,8 +71,8 @@ class BranchMainStage(PipeModBase):
             # Yes, the CTR only counts 32 bits
             ctr = Signal(64, reset_less=True)
             comb += ctr.eq(self.i.ctr - 1)
-            comb += self.o.spr.data.eq(ctr)
-            comb += self.o.spr.ok.eq(1)
+            comb += self.o.ctr.data.eq(ctr)
+            comb += self.o.ctr.ok.eq(1)
             ctr_zero_bo1 = Signal(reset_less=True) # BO[1] == (ctr==0)
             comb += ctr_zero_bo1.eq(BO[1] ^ ctr.any())
             with m.If(BO[3:5] == 0b00):

diff --git a/src/soc/branch/pipe_data.py b/src/soc/branch/pipe_data.py
index 7cd250dd137c556bbbf61f1db7b4d43451d20886..2ca8a8476241eaf541b18b14e5914b52c1ff4be8 100644 (file)
--- a/src/soc/branch/pipe_data.py
+++ b/src/soc/branch/pipe_data.py
@@ -75,6 +75,9 @@ class BranchOutputData(IntegerData):
         self.spr = Data(64, name="spr")
         self.nia_out = Data(64, name="nia_out")
 
+        # convenience variables.
+        self.ctr = self.spr
+
     def __iter__(self):
         yield from super().__iter__()
         yield from self.lr