add div and mul to test_issuer

diff --git a/experiments9/cells.lst b/experiments9/cells.lst
index 499bb7bce9798a355829660fe6131325b100c1d6..1e8f149c344caf1eb147938c0a98dabd6e24020c 100644 (file)
--- a/experiments9/cells.lst
+++ b/experiments9/cells.lst
@@ -58,6 +58,7 @@ dec_sub4
 dec_sub8
 dec_sub9
 dec
+div0
 fast
 fus
 idx_l
@@ -78,6 +79,7 @@ main_38
 main_54
 main_9
 main
+mul0
 mem
 opc_l_11
 opc_l_25

diff --git a/experiments9/non_generated/test_issuer.il b/experiments9/non_generated/test_issuer.il
index 4bfeab1516cb073c9505d582dbb3c7b4459d652a..b03420b8d5a2d33308662e5607793c94f42f15dd 100644 (file)
--- a/experiments9/non_generated/test_issuer.il
+++ b/experiments9/non_generated/test_issuer.il
@@ -37785,7 +37785,7 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.pdecode2.dec_a.sprmap"
 module \sprmap
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:55"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:56"
   wire width 10 input 0 \spr_i
   attribute \enum_base_type "SPR"
   attribute \enum_value_0000000001 "XER"
@@ -37898,340 +37898,340 @@ module \sprmap
   attribute \enum_value_1110000000 "PPR"
   attribute \enum_value_1110000010 "PPR32"
   attribute \enum_value_1111111111 "PIR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:56"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:57"
   wire width 10 output 1 \spr_o
   process $group_0
     assign \spr_o 10'0000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:60"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
     switch \spr_i
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'0000000001
         assign \spr_o 10'0000000000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'0000000011
         assign \spr_o 10'0000000001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'0000001000
         assign \spr_o 10'0000000010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'0000001001
         assign \spr_o 10'0000000011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'0000001101
         assign \spr_o 10'0000000100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'0000010001
         assign \spr_o 10'0000000101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'0000010010
         assign \spr_o 10'0000000110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'0000010011
         assign \spr_o 10'0000000111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'0000010110
         assign \spr_o 10'0000001000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'0000011010
         assign \spr_o 10'0000001001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'0000011011
         assign \spr_o 10'0000001010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'0000011100
         assign \spr_o 10'0000001011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'0000011101
         assign \spr_o 10'0000001100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'0000110000
         assign \spr_o 10'0000001101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'0000111101
         assign \spr_o 10'0000001110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'0010000000
         assign \spr_o 10'0000001111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'0010000001
         assign \spr_o 10'0000010000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'0010000010
         assign \spr_o 10'0000010001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'0010000011
         assign \spr_o 10'0000010010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'0010001000
         assign \spr_o 10'0000010011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'0010010000
         assign \spr_o 10'0000010100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'0010011000
         assign \spr_o 10'0000010101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'0010011001
         assign \spr_o 10'0000010110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'0010011101
         assign \spr_o 10'0000010111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'0010011110
         assign \spr_o 10'0000011000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'0010011111
         assign \spr_o 10'0000011001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'0010110000
         assign \spr_o 10'0000011010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'0010110100
         assign \spr_o 10'0000011011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'0010111010
         assign \spr_o 10'0000011100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'0010111011
         assign \spr_o 10'0000011101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'0010111100
         assign \spr_o 10'0000011110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'0010111110
         assign \spr_o 10'0000011111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'0100000000
         assign \spr_o 10'0000100000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'0100000011
         assign \spr_o 10'0000100001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'0100001100
         assign \spr_o 10'0000100010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'0100001101
         assign \spr_o 10'0000100011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'0100010000
         assign \spr_o 10'0000100100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'0100010001
         assign \spr_o 10'0000100101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'0100010010
         assign \spr_o 10'0000100110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'0100010011
         assign \spr_o 10'0000100111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'0100011011
         assign \spr_o 10'0000101000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'0100011100
         assign \spr_o 10'0000101001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'0100011101
         assign \spr_o 10'0000101010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'0100011110
         assign \spr_o 10'0000101011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'0100011111
         assign \spr_o 10'0000101100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'0100110000
         assign \spr_o 10'0000101101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'0100110001
         assign \spr_o 10'0000101110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'0100110010
         assign \spr_o 10'0000101111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'0100110011
         assign \spr_o 10'0000110000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'0100110100
         assign \spr_o 10'0000110001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'0100110101
         assign \spr_o 10'0000110010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'0100110110
         assign \spr_o 10'0000110011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'0100111001
         assign \spr_o 10'0000110100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'0100111010
         assign \spr_o 10'0000110101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'0100111011
         assign \spr_o 10'0000110110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'0100111110
         assign \spr_o 10'0000110111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'0100111111
         assign \spr_o 10'0000111000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'0101010000
         assign \spr_o 10'0000111001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'0101010001
         assign \spr_o 10'0000111010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'0101010010
         assign \spr_o 10'0000111011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'0101010011
         assign \spr_o 10'0000111100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'0101011101
         assign \spr_o 10'0000111101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'0110111110
         assign \spr_o 10'0000111110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'0111010000
         assign \spr_o 10'0000111111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'1100000000
         assign \spr_o 10'0001000000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'1100000001
         assign \spr_o 10'0001000001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'1100000010
         assign \spr_o 10'0001000010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'1100000011
         assign \spr_o 10'0001000011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'1100000100
         assign \spr_o 10'0001000100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'1100000101
         assign \spr_o 10'0001000101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'1100000110
         assign \spr_o 10'0001000110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'1100000111
         assign \spr_o 10'0001000111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'1100001000
         assign \spr_o 10'0001001000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'1100001011
         assign \spr_o 10'0001001001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'1100001100
         assign \spr_o 10'0001001010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'1100001101
         assign \spr_o 10'0001001011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'1100001110
         assign \spr_o 10'0001001100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'1100010000
         assign \spr_o 10'0001001101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'1100010001
         assign \spr_o 10'0001001110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'1100010010
         assign \spr_o 10'0001001111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'1100010011
         assign \spr_o 10'0001010000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'1100010100
         assign \spr_o 10'0001010001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'1100010101
         assign \spr_o 10'0001010010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'1100010110
         assign \spr_o 10'0001010011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'1100010111
         assign \spr_o 10'0001010100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'1100011000
         assign \spr_o 10'0001010101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'1100011011
         assign \spr_o 10'0001010110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'1100011100
         assign \spr_o 10'0001010111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'1100011101
         assign \spr_o 10'0001011000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'1100011110
         assign \spr_o 10'0001011001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'1100100000
         assign \spr_o 10'0001011010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'1100100001
         assign \spr_o 10'0001011011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'1100100010
         assign \spr_o 10'0001011100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'1100100011
         assign \spr_o 10'0001011101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'1100100100
         assign \spr_o 10'0001011110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'1100100101
         assign \spr_o 10'0001011111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'1100100110
         assign \spr_o 10'0001100000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'1100101000
         assign \spr_o 10'0001100001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'1100101001
         assign \spr_o 10'0001100010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'1100101010
         assign \spr_o 10'0001100011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'1100101011
         assign \spr_o 10'0001100100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'1100101111
         assign \spr_o 10'0001100101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'1100110000
         assign \spr_o 10'0001100110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'1100110111
         assign \spr_o 10'0001100111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'1101010000
         assign \spr_o 10'0001101000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'1101010001
         assign \spr_o 10'0001101001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'1101010111
         assign \spr_o 10'0001101010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'1110000000
         assign \spr_o 10'0001101011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'1110000010
         assign \spr_o 10'0001101100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'1111111111
         assign \spr_o 10'0001101101
     end
@@ -38247,7 +38247,7 @@ module \dec_a
   attribute \enum_value_010 "RA_OR_ZERO"
   attribute \enum_value_011 "SPR"
   attribute \enum_value_100 "RS"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:76"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:77"
   wire width 3 input 0 \sel_in
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -38328,7 +38328,7 @@ module \dec_a
   wire width 5 output 2 \reg_a
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 3 \reg_a_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:79"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:80"
   wire width 1 output 4 \immz_out
   attribute \enum_base_type "SPR"
   attribute \enum_value_0000000001 "XER"
@@ -38459,7 +38459,7 @@ module \dec_a
   wire width 10 input 12 \SPR
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 10 input 13 \XL_XO
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:55"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:56"
   wire width 10 \sprmap_spr_i
   attribute \enum_base_type "SPR"
   attribute \enum_value_0000000001 "XER"
@@ -38572,22 +38572,22 @@ module \dec_a
   attribute \enum_value_1110000000 "PPR"
   attribute \enum_value_1110000010 "PPR32"
   attribute \enum_value_1111111111 "PIR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:56"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:57"
   wire width 10 \sprmap_spr_o
   cell \sprmap \sprmap
     connect \spr_i \sprmap_spr_i
     connect \spr_o \sprmap_spr_o
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:89"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:90"
   wire width 5 \ra
   process $group_0
     assign \ra 5'00000
     assign \ra \RA
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:91"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92"
   wire width 1 $1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:91"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92"
   cell $eq $2
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
@@ -38598,9 +38598,9 @@ module \dec_a
     connect \B 3'001
     connect \Y $1
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:93"
   wire width 1 $3
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:93"
   cell $eq $4
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
@@ -38611,9 +38611,9 @@ module \dec_a
     connect \B 3'010
     connect \Y $3
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:93"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:94"
   wire width 1 $5
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:93"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:94"
   cell $ne $6
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
@@ -38624,9 +38624,9 @@ module \dec_a
     connect \B 5'00000
     connect \Y $5
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:93"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:94"
   wire width 1 $7
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:93"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:94"
   cell $and $8
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -38637,9 +38637,9 @@ module \dec_a
     connect \B $5
     connect \Y $7
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:93"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:94"
   wire width 1 $9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:93"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:94"
   cell $or $10
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -38650,9 +38650,9 @@ module \dec_a
     connect \B $7
     connect \Y $9
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:103"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:104"
   wire width 1 $11
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:103"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:104"
   cell $eq $12
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
@@ -38665,23 +38665,23 @@ module \dec_a
   end
   process $group_1
     assign \reg_a 5'00000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:93"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:94"
     switch { $9 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:93"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:94"
       case 1'1
         assign \reg_a \ra
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:103"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:104"
     switch { $11 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:103"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:104"
       case 1'1
         assign \reg_a \RS
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:91"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92"
   wire width 1 $13
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:91"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92"
   cell $eq $14
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
@@ -38692,9 +38692,9 @@ module \dec_a
     connect \B 3'001
     connect \Y $13
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:93"
   wire width 1 $15
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:92"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:93"
   cell $eq $16
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
@@ -38705,9 +38705,9 @@ module \dec_a
     connect \B 3'010
     connect \Y $15
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:93"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:94"
   wire width 1 $17
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:93"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:94"
   cell $ne $18
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
@@ -38718,9 +38718,9 @@ module \dec_a
     connect \B 5'00000
     connect \Y $17
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:93"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:94"
   wire width 1 $19
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:93"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:94"
   cell $and $20
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -38731,9 +38731,9 @@ module \dec_a
     connect \B $17
     connect \Y $19
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:93"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:94"
   wire width 1 $21
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:93"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:94"
   cell $or $22
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -38744,9 +38744,9 @@ module \dec_a
     connect \B $19
     connect \Y $21
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:103"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:104"
   wire width 1 $23
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:103"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:104"
   cell $eq $24
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
@@ -38759,23 +38759,23 @@ module \dec_a
   end
   process $group_2
     assign \reg_a_ok 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:93"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:94"
     switch { $21 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:93"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:94"
       case 1'1
         assign \reg_a_ok 1'1
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:103"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:104"
     switch { $23 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:103"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:104"
       case 1'1
         assign \reg_a_ok 1'1
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:98"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:99"
   wire width 1 $25
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:98"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:99"
   cell $eq $26
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
@@ -38786,9 +38786,9 @@ module \dec_a
     connect \B 3'010
     connect \Y $25
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:99"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:100"
   wire width 1 $27
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:99"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:100"
   cell $eq $28
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
@@ -38799,9 +38799,9 @@ module \dec_a
     connect \B 5'00000
     connect \Y $27
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:99"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:100"
   wire width 1 $29
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:99"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:100"
   cell $and $30
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -38814,17 +38814,17 @@ module \dec_a
   end
   process $group_3
     assign \immz_out 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:99"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:100"
     switch { $29 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:99"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:100"
       case 1'1
         assign \immz_out 1'1
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:113"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114"
   wire width 1 $31
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:113"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114"
   cell $not $32
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -38832,9 +38832,9 @@ module \dec_a
     connect \A \BO [2]
     connect \Y $31
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:120"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:121"
   wire width 1 $33
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:120"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:121"
   cell $not $34
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -38842,9 +38842,9 @@ module \dec_a
     connect \A \XL_XO [5]
     connect \Y $33
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:120"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:121"
   wire width 1 $35
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:120"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:121"
   cell $and $36
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -38855,61 +38855,61 @@ module \dec_a
     connect \B $33
     connect \Y $35
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:127"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:128"
   wire width 10 \spr
   process $group_4
     assign \fast_a 3'000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:109"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:110"
     switch \internal_op
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:113"
       attribute \nmigen.decoding "OP_BC/7"
       case 7'0000111
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:113"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114"
         switch { $31 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:113"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114"
           case 1'1
             assign \fast_a 3'010
         end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:117"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:118"
       attribute \nmigen.decoding "OP_BCREG/8"
       case 7'0001000
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:120"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:121"
         switch { $35 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:120"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:121"
           case 1'1
             assign \fast_a 3'010
         end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:126"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:127"
       attribute \nmigen.decoding "OP_MFSPR/46"
       case 7'0101110
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:129"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130"
         switch \spr
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:131"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:132"
           case 10'0000001001
             assign \fast_a 3'010
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:134"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:135"
           case 10'0000001000
             assign \fast_a 3'011
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:137"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:138"
           case 10'1100101111
             assign \fast_a 3'100
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:140"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:141"
           case 10'0000011010
             assign \fast_a 3'101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:143"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:144"
           case 10'0000011011
             assign \fast_a 3'110
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:146"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:147"
           case 10'0000000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:150"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:151"
           case
         end
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:113"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114"
   wire width 1 $37
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:113"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114"
   cell $not $38
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -38917,9 +38917,9 @@ module \dec_a
     connect \A \BO [2]
     connect \Y $37
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:120"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:121"
   wire width 1 $39
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:120"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:121"
   cell $not $40
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -38927,9 +38927,9 @@ module \dec_a
     connect \A \XL_XO [5]
     connect \Y $39
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:120"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:121"
   wire width 1 $41
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:120"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:121"
   cell $and $42
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -38942,49 +38942,49 @@ module \dec_a
   end
   process $group_5
     assign \fast_a_ok 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:109"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:110"
     switch \internal_op
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:113"
       attribute \nmigen.decoding "OP_BC/7"
       case 7'0000111
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:113"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114"
         switch { $37 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:113"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:114"
           case 1'1
             assign \fast_a_ok 1'1
         end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:117"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:118"
       attribute \nmigen.decoding "OP_BCREG/8"
       case 7'0001000
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:120"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:121"
         switch { $41 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:120"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:121"
           case 1'1
             assign \fast_a_ok 1'1
         end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:126"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:127"
       attribute \nmigen.decoding "OP_MFSPR/46"
       case 7'0101110
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:129"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130"
         switch \spr
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:131"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:132"
           case 10'0000001001
             assign \fast_a_ok 1'1
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:134"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:135"
           case 10'0000001000
             assign \fast_a_ok 1'1
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:137"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:138"
           case 10'1100101111
             assign \fast_a_ok 1'1
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:140"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:141"
           case 10'0000011010
             assign \fast_a_ok 1'1
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:143"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:144"
           case 10'0000011011
             assign \fast_a_ok 1'1
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:146"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:147"
           case 10'0000000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:150"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:151"
           case
         end
     end
@@ -38992,15 +38992,15 @@ module \dec_a
   end
   process $group_6
     assign \spr 10'0000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:109"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:110"
     switch \internal_op
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:113"
       attribute \nmigen.decoding "OP_BC/7"
       case 7'0000111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:117"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:118"
       attribute \nmigen.decoding "OP_BCREG/8"
       case 7'0001000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:126"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:127"
       attribute \nmigen.decoding "OP_MFSPR/46"
       case 7'0101110
         assign \spr { \SPR [4:0] \SPR [9:5] }
@@ -39009,32 +39009,32 @@ module \dec_a
   end
   process $group_7
     assign \sprmap_spr_i 10'0000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:109"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:110"
     switch \internal_op
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:113"
       attribute \nmigen.decoding "OP_BC/7"
       case 7'0000111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:117"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:118"
       attribute \nmigen.decoding "OP_BCREG/8"
       case 7'0001000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:126"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:127"
       attribute \nmigen.decoding "OP_MFSPR/46"
       case 7'0101110
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:129"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130"
         switch \spr
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:131"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:132"
           case 10'0000001001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:134"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:135"
           case 10'0000001000
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:137"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:138"
           case 10'1100101111
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:140"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:141"
           case 10'0000011010
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:143"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:144"
           case 10'0000011011
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:146"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:147"
           case 10'0000000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:150"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:151"
           case
             assign \sprmap_spr_i \spr
         end
@@ -39043,32 +39043,32 @@ module \dec_a
   end
   process $group_8
     assign \spr_a 10'0000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:109"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:110"
     switch \internal_op
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:113"
       attribute \nmigen.decoding "OP_BC/7"
       case 7'0000111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:117"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:118"
       attribute \nmigen.decoding "OP_BCREG/8"
       case 7'0001000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:126"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:127"
       attribute \nmigen.decoding "OP_MFSPR/46"
       case 7'0101110
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:129"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130"
         switch \spr
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:131"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:132"
           case 10'0000001001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:134"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:135"
           case 10'0000001000
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:137"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:138"
           case 10'1100101111
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:140"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:141"
           case 10'0000011010
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:143"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:144"
           case 10'0000011011
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:146"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:147"
           case 10'0000000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:150"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:151"
           case
             assign \spr_a \sprmap_spr_o
         end
@@ -39077,32 +39077,32 @@ module \dec_a
   end
   process $group_9
     assign \spr_a_ok 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:109"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:110"
     switch \internal_op
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:113"
       attribute \nmigen.decoding "OP_BC/7"
       case 7'0000111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:117"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:118"
       attribute \nmigen.decoding "OP_BCREG/8"
       case 7'0001000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:126"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:127"
       attribute \nmigen.decoding "OP_MFSPR/46"
       case 7'0101110
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:129"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130"
         switch \spr
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:131"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:132"
           case 10'0000001001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:134"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:135"
           case 10'0000001000
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:137"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:138"
           case 10'1100101111
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:140"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:141"
           case 10'0000011010
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:143"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:144"
           case 10'0000011011
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:146"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:147"
           case 10'0000000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:150"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:151"
           case
             assign \spr_a_ok 1'1
         end
@@ -39128,7 +39128,7 @@ module \dec_b
   attribute \enum_value_1011 "CONST_SH32"
   attribute \enum_value_1100 "SPR"
   attribute \enum_value_1101 "RS"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:169"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:170"
   wire width 4 input 0 \sel_in
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -39239,44 +39239,44 @@ module \dec_b
   wire width 10 input 17 \XL_XO
   process $group_0
     assign \reg_b 5'00000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:180"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:181"
     switch \sel_in
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:181"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:182"
       attribute \nmigen.decoding "RB/1"
       case 4'0001
         assign \reg_b \RB
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:184"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:185"
       attribute \nmigen.decoding "RS/13"
       case 4'1101
         assign \reg_b \RS
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:188"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:189"
       attribute \nmigen.decoding "CONST_UI/2"
       case 4'0010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192"
       attribute \nmigen.decoding "CONST_SI/3"
       case 4'0011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:195"
-      attribute \nmigen.decoding "CONST_UI_HI/4"
-      case 4'0100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:198"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:197"
       attribute \nmigen.decoding "CONST_SI_HI/5"
       case 4'0101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:203"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:202"
+      attribute \nmigen.decoding "CONST_UI_HI/4"
+      case 4'0100
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:207"
       attribute \nmigen.decoding "CONST_LI/6"
       case 4'0110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:206"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:212"
       attribute \nmigen.decoding "CONST_BD/7"
       case 4'0111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:209"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:217"
       attribute \nmigen.decoding "CONST_DS/8"
       case 4'1000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:212"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:222"
       attribute \nmigen.decoding "CONST_M1/9"
       case 4'1001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:215"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225"
       attribute \nmigen.decoding "CONST_SH/10"
       case 4'1010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:218"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228"
       attribute \nmigen.decoding "CONST_SH32/11"
       case 4'1011
     end
@@ -39284,44 +39284,44 @@ module \dec_b
   end
   process $group_1
     assign \reg_b_ok 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:180"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:181"
     switch \sel_in
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:181"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:182"
       attribute \nmigen.decoding "RB/1"
       case 4'0001
         assign \reg_b_ok 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:184"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:185"
       attribute \nmigen.decoding "RS/13"
       case 4'1101
         assign \reg_b_ok 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:188"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:189"
       attribute \nmigen.decoding "CONST_UI/2"
       case 4'0010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192"
       attribute \nmigen.decoding "CONST_SI/3"
       case 4'0011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:195"
-      attribute \nmigen.decoding "CONST_UI_HI/4"
-      case 4'0100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:198"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:197"
       attribute \nmigen.decoding "CONST_SI_HI/5"
       case 4'0101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:203"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:202"
+      attribute \nmigen.decoding "CONST_UI_HI/4"
+      case 4'0100
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:207"
       attribute \nmigen.decoding "CONST_LI/6"
       case 4'0110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:206"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:212"
       attribute \nmigen.decoding "CONST_BD/7"
       case 4'0111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:209"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:217"
       attribute \nmigen.decoding "CONST_DS/8"
       case 4'1000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:212"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:222"
       attribute \nmigen.decoding "CONST_M1/9"
       case 4'1001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:215"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225"
       attribute \nmigen.decoding "CONST_SH/10"
       case 4'1010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:218"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228"
       attribute \nmigen.decoding "CONST_SH32/11"
       case 4'1011
     end
@@ -39337,22 +39337,28 @@ module \dec_b
     connect \A \UI
     connect \Y $1
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:196"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:193"
+  wire width 16 \si
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:198"
+  wire width 32 \si_hi
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:205"
   wire width 64 $3
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:196"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:203"
+  wire width 16 \ui
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:205"
   wire width 47 $4
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:196"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:205"
   cell $sshl $5
     parameter \A_SIGNED 0
     parameter \A_WIDTH 16
     parameter \B_SIGNED 0
     parameter \B_WIDTH 5
     parameter \Y_WIDTH 47
-    connect \A \UI
+    connect \A \ui
     connect \B 5'10000
     connect \Y $4
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:196"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:205"
   cell $pos $6
     parameter \A_SIGNED 0
     parameter \A_WIDTH 47
@@ -39360,808 +39366,480 @@ module \dec_b
     connect \A $4
     connect \Y $3
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:199"
-  wire width 64 $7
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:199"
-  wire width 47 $8
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:199"
-  cell $sshl $9
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 16
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 5
-    parameter \Y_WIDTH 47
-    connect \A \SI
-    connect \B 5'10000
-    connect \Y $8
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:199"
-  cell $pos $10
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 47
-    parameter \Y_WIDTH 64
-    connect \A $8
-    connect \Y $7
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
-  wire width 47 $11
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
-  wire width 47 $12
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
-  cell $sshl $13
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 16
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 5
-    parameter \Y_WIDTH 47
-    connect \A \SI
-    connect \B 5'10000
-    connect \Y $12
-  end
-  connect $11 $12
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
-  wire width 47 $14
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
-  wire width 47 $15
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
-  cell $sshl $16
-    parameter \A_SIGNED 0
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-    parameter \B_WIDTH 5
-    parameter \Y_WIDTH 47
-    connect \A \SI
-    connect \B 5'10000
-    connect \Y $15
-  end
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-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
-  wire width 47 $17
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
-  wire width 47 $18
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
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-    parameter \B_WIDTH 5
-    parameter \Y_WIDTH 47
-    connect \A \SI
-    connect \B 5'10000
-    connect \Y $18
-  end
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-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
-  wire width 47 $20
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
-  wire width 47 $21
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
-  cell $sshl $22
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-    parameter \B_WIDTH 5
-    parameter \Y_WIDTH 47
-    connect \A \SI
-    connect \B 5'10000
-    connect \Y $21
-  end
-  connect $20 $21
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
-  wire width 47 $23
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
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-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
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-    parameter \B_WIDTH 5
-    parameter \Y_WIDTH 47
-    connect \A \SI
-    connect \B 5'10000
-    connect \Y $24
-  end
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-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
-  wire width 47 $26
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
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-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
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-    connect \A \SI
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-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
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-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
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-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
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-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
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-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
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-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
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-    connect \A \SI
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-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
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-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
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-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
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-    connect \A \SI
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-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
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-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
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-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
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-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
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-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
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-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
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-    connect \A \SI
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-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
-  wire width 47 $44
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
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-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
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-    connect \A \SI
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-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
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-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
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-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
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-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
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-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
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-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
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-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
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-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
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-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
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-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
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-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
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-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
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-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
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-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
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-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
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-    connect \A \SI
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-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
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-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
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-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
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-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
-  wire width 47 $71
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
-  wire width 47 $72
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
-  cell $sshl $73
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 16
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 5
-    parameter \Y_WIDTH 47
-    connect \A \SI
-    connect \B 5'10000
-    connect \Y $72
-  end
-  connect $71 $72
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
-  wire width 47 $74
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
-  wire width 47 $75
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
-  cell $sshl $76
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 16
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 5
-    parameter \Y_WIDTH 47
-    connect \A \SI
-    connect \B 5'10000
-    connect \Y $75
-  end
-  connect $74 $75
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
-  wire width 47 $77
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
-  wire width 47 $78
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
-  cell $sshl $79
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 16
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 5
-    parameter \Y_WIDTH 47
-    connect \A \SI
-    connect \B 5'10000
-    connect \Y $78
-  end
-  connect $77 $78
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
-  wire width 47 $80
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
-  wire width 47 $81
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
-  cell $sshl $82
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 16
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 5
-    parameter \Y_WIDTH 47
-    connect \A \SI
-    connect \B 5'10000
-    connect \Y $81
-  end
-  connect $80 $81
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
-  wire width 47 $83
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
-  wire width 47 $84
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
-  cell $sshl $85
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 16
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 5
-    parameter \Y_WIDTH 47
-    connect \A \SI
-    connect \B 5'10000
-    connect \Y $84
-  end
-  connect $83 $84
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
-  wire width 47 $86
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
-  wire width 47 $87
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
-  cell $sshl $88
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 16
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 5
-    parameter \Y_WIDTH 47
-    connect \A \SI
-    connect \B 5'10000
-    connect \Y $87
-  end
-  connect $86 $87
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
-  wire width 47 $89
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
-  wire width 47 $90
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
-  cell $sshl $91
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 16
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 5
-    parameter \Y_WIDTH 47
-    connect \A \SI
-    connect \B 5'10000
-    connect \Y $90
-  end
-  connect $89 $90
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
-  wire width 47 $92
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
-  wire width 47 $93
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
-  cell $sshl $94
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 16
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 5
-    parameter \Y_WIDTH 47
-    connect \A \SI
-    connect \B 5'10000
-    connect \Y $93
-  end
-  connect $92 $93
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
-  wire width 47 $95
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
-  wire width 47 $96
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
-  cell $sshl $97
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 16
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 5
-    parameter \Y_WIDTH 47
-    connect \A \SI
-    connect \B 5'10000
-    connect \Y $96
-  end
-  connect $95 $96
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
-  wire width 47 $98
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
-  wire width 47 $99
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
-  cell $sshl $100
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 16
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 5
-    parameter \Y_WIDTH 47
-    connect \A \SI
-    connect \B 5'10000
-    connect \Y $99
-  end
-  connect $98 $99
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
-  wire width 47 $101
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
-  wire width 47 $102
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
-  cell $sshl $103
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 16
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 5
-    parameter \Y_WIDTH 47
-    connect \A \SI
-    connect \B 5'10000
-    connect \Y $102
-  end
-  connect $101 $102
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
-  wire width 47 $104
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
-  wire width 47 $105
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
-  cell $sshl $106
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 16
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 5
-    parameter \Y_WIDTH 47
-    connect \A \SI
-    connect \B 5'10000
-    connect \Y $105
-  end
-  connect $104 $105
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
-  wire width 47 $107
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
-  wire width 47 $108
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201"
-  cell $sshl $109
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 16
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 5
-    parameter \Y_WIDTH 47
-    connect \A \SI
-    connect \B 5'10000
-    connect \Y $108
-  end
-  connect $107 $108
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:204"
-  wire width 64 $110
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:204"
-  wire width 27 $111
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:204"
-  cell $sshl $112
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 24
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 2
-    parameter \Y_WIDTH 27
-    connect \A \LI
-    connect \B 2'10
-    connect \Y $111
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:204"
-  cell $pos $113
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 27
-    parameter \Y_WIDTH 64
-    connect \A $111
-    connect \Y $110
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:207"
-  wire width 64 $114
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:207"
-  wire width 17 $115
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:207"
-  cell $sshl $116
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 14
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 2
-    parameter \Y_WIDTH 17
-    connect \A \BD
-    connect \B 2'10
-    connect \Y $115
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:207"
-  cell $pos $117
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 17
-    parameter \Y_WIDTH 64
-    connect \A $115
-    connect \Y $114
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:210"
-  wire width 64 $118
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:210"
-  wire width 17 $119
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:210"
-  cell $sshl $120
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 14
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 2
-    parameter \Y_WIDTH 17
-    connect \A \DS
-    connect \B 2'10
-    connect \Y $119
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:210"
-  cell $pos $121
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 17
-    parameter \Y_WIDTH 64
-    connect \A $119
-    connect \Y $118
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:213"
-  wire width 64 $122
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:208"
+  wire width 26 \li
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:213"
-  cell $not $123
+  wire width 16 \bd
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:218"
+  wire width 16 \ds
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:223"
+  wire width 64 $7
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:223"
+  cell $not $8
     parameter \A_SIGNED 0
     parameter \A_WIDTH 64
     parameter \Y_WIDTH 64
     connect \A 64'0000000000000000000000000000000000000000000000000000000000000000
-    connect \Y $122
+    connect \Y $7
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
-  wire width 64 $124
+  wire width 64 $9
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
-  cell $pos $125
+  cell $pos $10
     parameter \A_SIGNED 0
     parameter \A_WIDTH 6
     parameter \Y_WIDTH 64
     connect \A \sh
-    connect \Y $124
+    connect \Y $9
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
-  wire width 64 $126
+  wire width 64 $11
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
-  cell $pos $127
+  cell $pos $12
     parameter \A_SIGNED 0
     parameter \A_WIDTH 5
     parameter \Y_WIDTH 64
     connect \A \SH32
-    connect \Y $126
+    connect \Y $11
   end
   process $group_2
     assign \imm_b 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:180"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:181"
     switch \sel_in
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:181"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:182"
       attribute \nmigen.decoding "RB/1"
       case 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:184"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:185"
       attribute \nmigen.decoding "RS/13"
       case 4'1101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:188"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:189"
       attribute \nmigen.decoding "CONST_UI/2"
       case 4'0010
         assign \imm_b $1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192"
       attribute \nmigen.decoding "CONST_SI/3"
       case 4'0011
-        assign \imm_b { { \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] \SI [15] } \SI }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:195"
+        assign \imm_b { { \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] } \si }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:197"
+      attribute \nmigen.decoding "CONST_SI_HI/5"
+      case 4'0101
+        assign \imm_b { { \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] } \si_hi }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:202"
       attribute \nmigen.decoding "CONST_UI_HI/4"
       case 4'0100
         assign \imm_b $3
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:198"
-      attribute \nmigen.decoding "CONST_SI_HI/5"
-      case 4'0101
-        assign \imm_b $7
-        assign \imm_b { { $14 [31:0] [31] $17 [31:0] [31] $20 [31:0] [31] $23 [31:0] [31] $26 [31:0] [31] $29 [31:0] [31] $32 [31:0] [31] $35 [31:0] [31] $38 [31:0] [31] $41 [31:0] [31] $44 [31:0] [31] $47 [31:0] [31] $50 [31:0] [31] $53 [31:0] [31] $56 [31:0] [31] $59 [31:0] [31] $62 [31:0] [31] $65 [31:0] [31] $68 [31:0] [31] $71 [31:0] [31] $74 [31:0] [31] $77 [31:0] [31] $80 [31:0] [31] $83 [31:0] [31] $86 [31:0] [31] $89 [31:0] [31] $92 [31:0] [31] $95 [31:0] [31] $98 [31:0] [31] $101 [31:0] [31] $104 [31:0] [31] $107 [31:0] [31] } $11 [31:0] }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:203"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:207"
       attribute \nmigen.decoding "CONST_LI/6"
       case 4'0110
-        assign \imm_b $110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:206"
+        assign \imm_b { { \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] } \li }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:212"
       attribute \nmigen.decoding "CONST_BD/7"
       case 4'0111
-        assign \imm_b $114
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:209"
+        assign \imm_b { { \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] } \bd }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:217"
       attribute \nmigen.decoding "CONST_DS/8"
       case 4'1000
-        assign \imm_b $118
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:212"
+        assign \imm_b { { \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] } \ds }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:222"
       attribute \nmigen.decoding "CONST_M1/9"
       case 4'1001
-        assign \imm_b $122
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:215"
+        assign \imm_b $7
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225"
       attribute \nmigen.decoding "CONST_SH/10"
       case 4'1010
-        assign \imm_b $124
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:218"
+        assign \imm_b $9
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228"
       attribute \nmigen.decoding "CONST_SH32/11"
       case 4'1011
-        assign \imm_b $126
+        assign \imm_b $11
     end
     sync init
   end
   process $group_3
     assign \imm_b_ok 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:180"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:181"
     switch \sel_in
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:181"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:182"
       attribute \nmigen.decoding "RB/1"
       case 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:184"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:185"
       attribute \nmigen.decoding "RS/13"
       case 4'1101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:188"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:189"
       attribute \nmigen.decoding "CONST_UI/2"
       case 4'0010
         assign \imm_b_ok 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:191"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192"
       attribute \nmigen.decoding "CONST_SI/3"
       case 4'0011
         assign \imm_b_ok 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:195"
-      attribute \nmigen.decoding "CONST_UI_HI/4"
-      case 4'0100
-        assign \imm_b_ok 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:198"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:197"
       attribute \nmigen.decoding "CONST_SI_HI/5"
       case 4'0101
         assign \imm_b_ok 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:203"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:202"
+      attribute \nmigen.decoding "CONST_UI_HI/4"
+      case 4'0100
+        assign \imm_b_ok 1'1
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:207"
       attribute \nmigen.decoding "CONST_LI/6"
       case 4'0110
         assign \imm_b_ok 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:206"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:212"
       attribute \nmigen.decoding "CONST_BD/7"
       case 4'0111
         assign \imm_b_ok 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:209"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:217"
       attribute \nmigen.decoding "CONST_DS/8"
       case 4'1000
         assign \imm_b_ok 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:212"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:222"
       attribute \nmigen.decoding "CONST_M1/9"
       case 4'1001
         assign \imm_b_ok 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:215"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225"
       attribute \nmigen.decoding "CONST_SH/10"
       case 4'1010
         assign \imm_b_ok 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:218"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228"
       attribute \nmigen.decoding "CONST_SH32/11"
       case 4'1011
         assign \imm_b_ok 1'1
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:226"
-  wire width 1 $128
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:226"
-  cell $eq $129
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 7
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 7
-    parameter \Y_WIDTH 1
-    connect \A \internal_op
-    connect \B 7'0001000
-    connect \Y $128
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:229"
-  wire width 1 $130
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:229"
-  cell $not $131
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \XL_XO [9]
-    connect \Y $130
-  end
   process $group_4
-    assign \fast_b 3'000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:226"
-    switch { $128 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:226"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:229"
-        switch { \XL_XO [5] $130 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:229"
-          case 2'-1
-            assign \fast_b 3'011
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:232"
-          case 2'1-
-            assign \fast_b 3'100
-        end
+    assign \si 16'0000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:181"
+    switch \sel_in
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:182"
+      attribute \nmigen.decoding "RB/1"
+      case 4'0001
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:185"
+      attribute \nmigen.decoding "RS/13"
+      case 4'1101
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:189"
+      attribute \nmigen.decoding "CONST_UI/2"
+      case 4'0010
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192"
+      attribute \nmigen.decoding "CONST_SI/3"
+      case 4'0011
+        assign \si \SI
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:197"
+      attribute \nmigen.decoding "CONST_SI_HI/5"
+      case 4'0101
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:202"
+      attribute \nmigen.decoding "CONST_UI_HI/4"
+      case 4'0100
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:207"
+      attribute \nmigen.decoding "CONST_LI/6"
+      case 4'0110
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:212"
+      attribute \nmigen.decoding "CONST_BD/7"
+      case 4'0111
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:217"
+      attribute \nmigen.decoding "CONST_DS/8"
+      case 4'1000
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:222"
+      attribute \nmigen.decoding "CONST_M1/9"
+      case 4'1001
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225"
+      attribute \nmigen.decoding "CONST_SH/10"
+      case 4'1010
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228"
+      attribute \nmigen.decoding "CONST_SH32/11"
+      case 4'1011
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:226"
-  wire width 1 $132
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:226"
-  cell $eq $133
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:199"
+  wire width 47 $13
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:199"
+  wire width 47 $14
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:199"
+  cell $sshl $15
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 16
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 5
+    parameter \Y_WIDTH 47
+    connect \A \SI
+    connect \B 5'10000
+    connect \Y $14
+  end
+  connect $13 $14
+  process $group_5
+    assign \si_hi 32'00000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:181"
+    switch \sel_in
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:182"
+      attribute \nmigen.decoding "RB/1"
+      case 4'0001
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:185"
+      attribute \nmigen.decoding "RS/13"
+      case 4'1101
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:189"
+      attribute \nmigen.decoding "CONST_UI/2"
+      case 4'0010
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192"
+      attribute \nmigen.decoding "CONST_SI/3"
+      case 4'0011
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:197"
+      attribute \nmigen.decoding "CONST_SI_HI/5"
+      case 4'0101
+        assign \si_hi $13 [31:0]
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:202"
+      attribute \nmigen.decoding "CONST_UI_HI/4"
+      case 4'0100
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:207"
+      attribute \nmigen.decoding "CONST_LI/6"
+      case 4'0110
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:212"
+      attribute \nmigen.decoding "CONST_BD/7"
+      case 4'0111
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:217"
+      attribute \nmigen.decoding "CONST_DS/8"
+      case 4'1000
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:222"
+      attribute \nmigen.decoding "CONST_M1/9"
+      case 4'1001
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225"
+      attribute \nmigen.decoding "CONST_SH/10"
+      case 4'1010
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228"
+      attribute \nmigen.decoding "CONST_SH32/11"
+      case 4'1011
+    end
+    sync init
+  end
+  process $group_6
+    assign \ui 16'0000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:181"
+    switch \sel_in
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:182"
+      attribute \nmigen.decoding "RB/1"
+      case 4'0001
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:185"
+      attribute \nmigen.decoding "RS/13"
+      case 4'1101
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:189"
+      attribute \nmigen.decoding "CONST_UI/2"
+      case 4'0010
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192"
+      attribute \nmigen.decoding "CONST_SI/3"
+      case 4'0011
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:197"
+      attribute \nmigen.decoding "CONST_SI_HI/5"
+      case 4'0101
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:202"
+      attribute \nmigen.decoding "CONST_UI_HI/4"
+      case 4'0100
+        assign \ui \UI
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:207"
+      attribute \nmigen.decoding "CONST_LI/6"
+      case 4'0110
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:212"
+      attribute \nmigen.decoding "CONST_BD/7"
+      case 4'0111
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:217"
+      attribute \nmigen.decoding "CONST_DS/8"
+      case 4'1000
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:222"
+      attribute \nmigen.decoding "CONST_M1/9"
+      case 4'1001
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225"
+      attribute \nmigen.decoding "CONST_SH/10"
+      case 4'1010
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228"
+      attribute \nmigen.decoding "CONST_SH32/11"
+      case 4'1011
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:209"
+  wire width 27 $16
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:209"
+  wire width 27 $17
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:209"
+  cell $sshl $18
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 24
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 2
+    parameter \Y_WIDTH 27
+    connect \A \LI
+    connect \B 2'10
+    connect \Y $17
+  end
+  connect $16 $17
+  process $group_7
+    assign \li 26'00000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:181"
+    switch \sel_in
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:182"
+      attribute \nmigen.decoding "RB/1"
+      case 4'0001
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:185"
+      attribute \nmigen.decoding "RS/13"
+      case 4'1101
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:189"
+      attribute \nmigen.decoding "CONST_UI/2"
+      case 4'0010
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192"
+      attribute \nmigen.decoding "CONST_SI/3"
+      case 4'0011
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:197"
+      attribute \nmigen.decoding "CONST_SI_HI/5"
+      case 4'0101
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:202"
+      attribute \nmigen.decoding "CONST_UI_HI/4"
+      case 4'0100
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:207"
+      attribute \nmigen.decoding "CONST_LI/6"
+      case 4'0110
+        assign \li $16 [25:0]
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:212"
+      attribute \nmigen.decoding "CONST_BD/7"
+      case 4'0111
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:217"
+      attribute \nmigen.decoding "CONST_DS/8"
+      case 4'1000
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:222"
+      attribute \nmigen.decoding "CONST_M1/9"
+      case 4'1001
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225"
+      attribute \nmigen.decoding "CONST_SH/10"
+      case 4'1010
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228"
+      attribute \nmigen.decoding "CONST_SH32/11"
+      case 4'1011
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:214"
+  wire width 17 $19
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:214"
+  wire width 17 $20
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:214"
+  cell $sshl $21
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 14
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 2
+    parameter \Y_WIDTH 17
+    connect \A \BD
+    connect \B 2'10
+    connect \Y $20
+  end
+  connect $19 $20
+  process $group_8
+    assign \bd 16'0000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:181"
+    switch \sel_in
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:182"
+      attribute \nmigen.decoding "RB/1"
+      case 4'0001
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:185"
+      attribute \nmigen.decoding "RS/13"
+      case 4'1101
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:189"
+      attribute \nmigen.decoding "CONST_UI/2"
+      case 4'0010
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192"
+      attribute \nmigen.decoding "CONST_SI/3"
+      case 4'0011
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:197"
+      attribute \nmigen.decoding "CONST_SI_HI/5"
+      case 4'0101
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:202"
+      attribute \nmigen.decoding "CONST_UI_HI/4"
+      case 4'0100
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:207"
+      attribute \nmigen.decoding "CONST_LI/6"
+      case 4'0110
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:212"
+      attribute \nmigen.decoding "CONST_BD/7"
+      case 4'0111
+        assign \bd $19 [15:0]
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:217"
+      attribute \nmigen.decoding "CONST_DS/8"
+      case 4'1000
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:222"
+      attribute \nmigen.decoding "CONST_M1/9"
+      case 4'1001
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225"
+      attribute \nmigen.decoding "CONST_SH/10"
+      case 4'1010
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228"
+      attribute \nmigen.decoding "CONST_SH32/11"
+      case 4'1011
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:219"
+  wire width 17 $22
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:219"
+  wire width 17 $23
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:219"
+  cell $sshl $24
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 14
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 2
+    parameter \Y_WIDTH 17
+    connect \A \DS
+    connect \B 2'10
+    connect \Y $23
+  end
+  connect $22 $23
+  process $group_9
+    assign \ds 16'0000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:181"
+    switch \sel_in
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:182"
+      attribute \nmigen.decoding "RB/1"
+      case 4'0001
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:185"
+      attribute \nmigen.decoding "RS/13"
+      case 4'1101
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:189"
+      attribute \nmigen.decoding "CONST_UI/2"
+      case 4'0010
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:192"
+      attribute \nmigen.decoding "CONST_SI/3"
+      case 4'0011
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:197"
+      attribute \nmigen.decoding "CONST_SI_HI/5"
+      case 4'0101
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:202"
+      attribute \nmigen.decoding "CONST_UI_HI/4"
+      case 4'0100
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:207"
+      attribute \nmigen.decoding "CONST_LI/6"
+      case 4'0110
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:212"
+      attribute \nmigen.decoding "CONST_BD/7"
+      case 4'0111
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:217"
+      attribute \nmigen.decoding "CONST_DS/8"
+      case 4'1000
+        assign \ds $22 [15:0]
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:222"
+      attribute \nmigen.decoding "CONST_M1/9"
+      case 4'1001
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225"
+      attribute \nmigen.decoding "CONST_SH/10"
+      case 4'1010
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228"
+      attribute \nmigen.decoding "CONST_SH32/11"
+      case 4'1011
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:236"
+  wire width 1 $25
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:236"
+  cell $eq $26
     parameter \A_SIGNED 0
     parameter \A_WIDTH 7
     parameter \B_SIGNED 0
@@ -40169,30 +39847,71 @@ module \dec_b
     parameter \Y_WIDTH 1
     connect \A \internal_op
     connect \B 7'0001000
-    connect \Y $132
+    connect \Y $25
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:229"
-  wire width 1 $134
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:229"
-  cell $not $135
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239"
+  wire width 1 $27
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239"
+  cell $not $28
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \XL_XO [9]
-    connect \Y $134
+    connect \Y $27
   end
-  process $group_5
+  process $group_10
+    assign \fast_b 3'000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:236"
+    switch { $25 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:236"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239"
+        switch { \XL_XO [5] $27 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239"
+          case 2'-1
+            assign \fast_b 3'011
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:242"
+          case 2'1-
+            assign \fast_b 3'100
+        end
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:236"
+  wire width 1 $29
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:236"
+  cell $eq $30
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 7
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 7
+    parameter \Y_WIDTH 1
+    connect \A \internal_op
+    connect \B 7'0001000
+    connect \Y $29
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239"
+  wire width 1 $31
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239"
+  cell $not $32
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \XL_XO [9]
+    connect \Y $31
+  end
+  process $group_11
     assign \fast_b_ok 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:226"
-    switch { $132 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:226"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:236"
+    switch { $29 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:236"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:229"
-        switch { \XL_XO [5] $134 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:229"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239"
+        switch { \XL_XO [5] $31 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239"
           case 2'-1
             assign \fast_b_ok 1'1
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:232"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:242"
           case 2'1-
             assign \fast_b_ok 1'1
         end
@@ -40207,7 +39926,7 @@ module \dec_c
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "RS"
   attribute \enum_value_10 "RB"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:247"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:257"
   wire width 2 input 0 \sel_in
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 5 output 1 \reg_c
@@ -40219,13 +39938,13 @@ module \dec_c
   wire width 5 input 4 \RB
   process $group_0
     assign \reg_c 5'00000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:256"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:266"
     switch \sel_in
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:257"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:267"
       attribute \nmigen.decoding "RB/2"
       case 2'10
         assign \reg_c \RB
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271"
       attribute \nmigen.decoding "RS/1"
       case 2'01
         assign \reg_c \RS
@@ -40234,13 +39953,13 @@ module \dec_c
   end
   process $group_1
     assign \reg_c_ok 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:256"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:266"
     switch \sel_in
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:257"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:267"
       attribute \nmigen.decoding "RB/2"
       case 2'10
         assign \reg_c_ok 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:271"
       attribute \nmigen.decoding "RS/1"
       case 2'01
         assign \reg_c_ok 1'1
@@ -40251,7 +39970,7 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.pdecode2.dec_o.sprmap"
 module \sprmap$1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:55"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:56"
   wire width 10 input 0 \spr_i
   attribute \enum_base_type "SPR"
   attribute \enum_value_0000000001 "XER"
@@ -40364,340 +40083,340 @@ module \sprmap$1
   attribute \enum_value_1110000000 "PPR"
   attribute \enum_value_1110000010 "PPR32"
   attribute \enum_value_1111111111 "PIR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:56"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:57"
   wire width 10 output 1 \spr_o
   process $group_0
     assign \spr_o 10'0000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:60"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:61"
     switch \spr_i
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'0000000001
         assign \spr_o 10'0000000000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'0000000011
         assign \spr_o 10'0000000001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'0000001000
         assign \spr_o 10'0000000010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'0000001001
         assign \spr_o 10'0000000011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'0000001101
         assign \spr_o 10'0000000100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'0000010001
         assign \spr_o 10'0000000101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'0000010010
         assign \spr_o 10'0000000110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'0000010011
         assign \spr_o 10'0000000111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'0000010110
         assign \spr_o 10'0000001000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'0000011010
         assign \spr_o 10'0000001001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'0000011011
         assign \spr_o 10'0000001010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'0000011100
         assign \spr_o 10'0000001011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'0000011101
         assign \spr_o 10'0000001100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'0000110000
         assign \spr_o 10'0000001101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'0000111101
         assign \spr_o 10'0000001110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'0010000000
         assign \spr_o 10'0000001111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'0010000001
         assign \spr_o 10'0000010000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'0010000010
         assign \spr_o 10'0000010001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'0010000011
         assign \spr_o 10'0000010010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'0010001000
         assign \spr_o 10'0000010011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'0010010000
         assign \spr_o 10'0000010100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'0010011000
         assign \spr_o 10'0000010101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'0010011001
         assign \spr_o 10'0000010110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'0010011101
         assign \spr_o 10'0000010111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'0010011110
         assign \spr_o 10'0000011000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'0010011111
         assign \spr_o 10'0000011001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'0010110000
         assign \spr_o 10'0000011010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'0010110100
         assign \spr_o 10'0000011011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'0010111010
         assign \spr_o 10'0000011100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'0010111011
         assign \spr_o 10'0000011101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'0010111100
         assign \spr_o 10'0000011110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'0010111110
         assign \spr_o 10'0000011111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'0100000000
         assign \spr_o 10'0000100000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'0100000011
         assign \spr_o 10'0000100001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'0100001100
         assign \spr_o 10'0000100010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'0100001101
         assign \spr_o 10'0000100011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'0100010000
         assign \spr_o 10'0000100100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'0100010001
         assign \spr_o 10'0000100101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'0100010010
         assign \spr_o 10'0000100110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'0100010011
         assign \spr_o 10'0000100111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'0100011011
         assign \spr_o 10'0000101000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'0100011100
         assign \spr_o 10'0000101001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'0100011101
         assign \spr_o 10'0000101010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'0100011110
         assign \spr_o 10'0000101011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'0100011111
         assign \spr_o 10'0000101100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'0100110000
         assign \spr_o 10'0000101101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'0100110001
         assign \spr_o 10'0000101110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'0100110010
         assign \spr_o 10'0000101111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'0100110011
         assign \spr_o 10'0000110000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'0100110100
         assign \spr_o 10'0000110001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'0100110101
         assign \spr_o 10'0000110010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'0100110110
         assign \spr_o 10'0000110011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'0100111001
         assign \spr_o 10'0000110100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'0100111010
         assign \spr_o 10'0000110101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'0100111011
         assign \spr_o 10'0000110110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'0100111110
         assign \spr_o 10'0000110111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'0100111111
         assign \spr_o 10'0000111000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'0101010000
         assign \spr_o 10'0000111001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'0101010001
         assign \spr_o 10'0000111010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'0101010010
         assign \spr_o 10'0000111011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'0101010011
         assign \spr_o 10'0000111100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'0101011101
         assign \spr_o 10'0000111101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'0110111110
         assign \spr_o 10'0000111110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'0111010000
         assign \spr_o 10'0000111111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'1100000000
         assign \spr_o 10'0001000000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'1100000001
         assign \spr_o 10'0001000001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'1100000010
         assign \spr_o 10'0001000010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'1100000011
         assign \spr_o 10'0001000011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'1100000100
         assign \spr_o 10'0001000100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'1100000101
         assign \spr_o 10'0001000101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'1100000110
         assign \spr_o 10'0001000110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'1100000111
         assign \spr_o 10'0001000111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'1100001000
         assign \spr_o 10'0001001000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'1100001011
         assign \spr_o 10'0001001001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'1100001100
         assign \spr_o 10'0001001010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'1100001101
         assign \spr_o 10'0001001011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'1100001110
         assign \spr_o 10'0001001100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'1100010000
         assign \spr_o 10'0001001101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'1100010001
         assign \spr_o 10'0001001110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'1100010010
         assign \spr_o 10'0001001111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'1100010011
         assign \spr_o 10'0001010000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'1100010100
         assign \spr_o 10'0001010001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'1100010101
         assign \spr_o 10'0001010010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'1100010110
         assign \spr_o 10'0001010011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'1100010111
         assign \spr_o 10'0001010100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'1100011000
         assign \spr_o 10'0001010101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'1100011011
         assign \spr_o 10'0001010110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'1100011100
         assign \spr_o 10'0001010111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'1100011101
         assign \spr_o 10'0001011000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'1100011110
         assign \spr_o 10'0001011001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'1100100000
         assign \spr_o 10'0001011010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'1100100001
         assign \spr_o 10'0001011011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'1100100010
         assign \spr_o 10'0001011100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'1100100011
         assign \spr_o 10'0001011101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'1100100100
         assign \spr_o 10'0001011110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'1100100101
         assign \spr_o 10'0001011111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'1100100110
         assign \spr_o 10'0001100000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'1100101000
         assign \spr_o 10'0001100001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'1100101001
         assign \spr_o 10'0001100010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'1100101010
         assign \spr_o 10'0001100011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'1100101011
         assign \spr_o 10'0001100100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'1100101111
         assign \spr_o 10'0001100101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'1100110000
         assign \spr_o 10'0001100110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'1100110111
         assign \spr_o 10'0001100111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'1101010000
         assign \spr_o 10'0001101000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'1101010001
         assign \spr_o 10'0001101001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'1101010111
         assign \spr_o 10'0001101010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'1110000000
         assign \spr_o 10'0001101011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'1110000010
         assign \spr_o 10'0001101100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:62"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:63"
       case 10'1111111111
         assign \spr_o 10'0001101101
     end
@@ -40712,7 +40431,7 @@ module \dec_o
   attribute \enum_value_01 "RT"
   attribute \enum_value_10 "RA"
   attribute \enum_value_11 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:276"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286"
   wire width 2 input 0 \sel_in
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -40920,7 +40639,7 @@ module \dec_o
   wire width 5 input 10 \BO
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
   wire width 10 input 11 \SPR
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:55"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:56"
   wire width 10 \sprmap_spr_i
   attribute \enum_base_type "SPR"
   attribute \enum_value_0000000001 "XER"
@@ -41033,7 +40752,7 @@ module \dec_o
   attribute \enum_value_1110000000 "PPR"
   attribute \enum_value_1110000010 "PPR32"
   attribute \enum_value_1111111111 "PIR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:56"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:57"
   wire width 10 \sprmap_spr_o
   cell \sprmap$1 \sprmap
     connect \spr_i \sprmap_spr_i
@@ -41041,17 +40760,17 @@ module \dec_o
   end
   process $group_0
     assign \reg_o 5'00000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:299"
     switch \sel_in
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:290"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:300"
       attribute \nmigen.decoding "RT/1"
       case 2'01
         assign \reg_o \RT
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:293"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:303"
       attribute \nmigen.decoding "RA/2"
       case 2'10
         assign \reg_o \RA
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:296"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:306"
       attribute \nmigen.decoding "SPR/3"
       case 2'11
     end
@@ -41059,44 +40778,44 @@ module \dec_o
   end
   process $group_1
     assign \reg_o_ok 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:299"
     switch \sel_in
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:290"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:300"
       attribute \nmigen.decoding "RT/1"
       case 2'01
         assign \reg_o_ok 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:293"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:303"
       attribute \nmigen.decoding "RA/2"
       case 2'10
         assign \reg_o_ok 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:296"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:306"
       attribute \nmigen.decoding "SPR/3"
       case 2'11
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:297"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:307"
   wire width 10 \spr
   process $group_2
     assign \spr 10'0000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:299"
     switch \sel_in
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:290"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:300"
       attribute \nmigen.decoding "RT/1"
       case 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:293"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:303"
       attribute \nmigen.decoding "RA/2"
       case 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:296"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:306"
       attribute \nmigen.decoding "SPR/3"
       case 2'11
         assign \spr { \SPR [4:0] \SPR [9:5] }
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:300"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:310"
   wire width 1 $1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:300"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:310"
   cell $eq $2
     parameter \A_SIGNED 0
     parameter \A_WIDTH 7
@@ -41107,9 +40826,9 @@ module \dec_o
     connect \B 7'0110001
     connect \Y $1
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:331"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:341"
   wire width 1 $3
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:331"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:341"
   cell $not $4
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -41119,66 +40838,66 @@ module \dec_o
   end
   process $group_3
     assign \fast_o 3'000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:299"
     switch \sel_in
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:290"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:300"
       attribute \nmigen.decoding "RT/1"
       case 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:293"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:303"
       attribute \nmigen.decoding "RA/2"
       case 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:296"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:306"
       attribute \nmigen.decoding "SPR/3"
       case 2'11
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:300"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:310"
         switch { $1 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:300"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:310"
           case 1'1
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:301"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:311"
             switch \spr
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:303"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:313"
               case 10'0000001001
                 assign \fast_o 3'010
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:306"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:316"
               case 10'0000001000
                 assign \fast_o 3'011
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:309"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:319"
               case 10'1100101111
                 assign \fast_o 3'100
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:312"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:322"
               case 10'0000011010
                 assign \fast_o 3'101
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:315"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:325"
               case 10'0000011011
                 assign \fast_o 3'110
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:318"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:328"
               case 10'0000000001
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:322"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:332"
               case
             end
         end
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:327"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:337"
     switch \internal_op
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:330"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:340"
       attribute \nmigen.decoding "OP_BC/7|OP_BCREG/8"
       case 7'0000111, 7'0001000
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:331"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:341"
         switch { $3 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:331"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:341"
           case 1'1
             assign \fast_o 3'010
         end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:337"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:347"
       attribute \nmigen.decoding "OP_RFID/70"
       case 7'1000110
         assign \fast_o 3'101
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:300"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:310"
   wire width 1 $5
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:300"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:310"
   cell $eq $6
     parameter \A_SIGNED 0
     parameter \A_WIDTH 7
@@ -41189,9 +40908,9 @@ module \dec_o
     connect \B 7'0110001
     connect \Y $5
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:331"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:341"
   wire width 1 $7
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:331"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:341"
   cell $not $8
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
@@ -41201,66 +40920,66 @@ module \dec_o
   end
   process $group_4
     assign \fast_o_ok 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:299"
     switch \sel_in
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:290"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:300"
       attribute \nmigen.decoding "RT/1"
       case 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:293"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:303"
       attribute \nmigen.decoding "RA/2"
       case 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:296"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:306"
       attribute \nmigen.decoding "SPR/3"
       case 2'11
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:300"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:310"
         switch { $5 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:300"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:310"
           case 1'1
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:301"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:311"
             switch \spr
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:303"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:313"
               case 10'0000001001
                 assign \fast_o_ok 1'1
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:306"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:316"
               case 10'0000001000
                 assign \fast_o_ok 1'1
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:309"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:319"
               case 10'1100101111
                 assign \fast_o_ok 1'1
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:312"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:322"
               case 10'0000011010
                 assign \fast_o_ok 1'1
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:315"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:325"
               case 10'0000011011
                 assign \fast_o_ok 1'1
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:318"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:328"
               case 10'0000000001
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:322"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:332"
               case
             end
         end
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:327"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:337"
     switch \internal_op
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:330"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:340"
       attribute \nmigen.decoding "OP_BC/7|OP_BCREG/8"
       case 7'0000111, 7'0001000
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:331"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:341"
         switch { $7 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:331"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:341"
           case 1'1
             assign \fast_o_ok 1'1
         end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:337"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:347"
       attribute \nmigen.decoding "OP_RFID/70"
       case 7'1000110
         assign \fast_o_ok 1'1
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:300"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:310"
   wire width 1 $9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:300"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:310"
   cell $eq $10
     parameter \A_SIGNED 0
     parameter \A_WIDTH 7
@@ -41273,36 +40992,36 @@ module \dec_o
   end
   process $group_5
     assign \sprmap_spr_i 10'0000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:299"
     switch \sel_in
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:290"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:300"
       attribute \nmigen.decoding "RT/1"
       case 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:293"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:303"
       attribute \nmigen.decoding "RA/2"
       case 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:296"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:306"
       attribute \nmigen.decoding "SPR/3"
       case 2'11
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:300"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:310"
         switch { $9 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:300"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:310"
           case 1'1
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:301"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:311"
             switch \spr
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:303"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:313"
               case 10'0000001001
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:306"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:316"
               case 10'0000001000
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:309"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:319"
               case 10'1100101111
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:312"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:322"
               case 10'0000011010
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:315"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:325"
               case 10'0000011011
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:318"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:328"
               case 10'0000000001
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:322"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:332"
               case
                 assign \sprmap_spr_i \spr
             end
@@ -41310,9 +41029,9 @@ module \dec_o
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:300"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:310"
   wire width 1 $11
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:300"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:310"
   cell $eq $12
     parameter \A_SIGNED 0
     parameter \A_WIDTH 7
@@ -41325,36 +41044,36 @@ module \dec_o
   end
   process $group_6
     assign \spr_o 10'0000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:299"
     switch \sel_in
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:290"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:300"
       attribute \nmigen.decoding "RT/1"
       case 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:293"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:303"
       attribute \nmigen.decoding "RA/2"
       case 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:296"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:306"
       attribute \nmigen.decoding "SPR/3"
       case 2'11
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:300"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:310"
         switch { $11 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:300"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:310"
           case 1'1
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:301"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:311"
             switch \spr
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:303"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:313"
               case 10'0000001001
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:306"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:316"
               case 10'0000001000
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:309"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:319"
               case 10'1100101111
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:312"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:322"
               case 10'0000011010
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:315"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:325"
               case 10'0000011011
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:318"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:328"
               case 10'0000000001
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:322"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:332"
               case
                 assign \spr_o \sprmap_spr_o
             end
@@ -41362,9 +41081,9 @@ module \dec_o
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:300"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:310"
   wire width 1 $13
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:300"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:310"
   cell $eq $14
     parameter \A_SIGNED 0
     parameter \A_WIDTH 7
@@ -41377,36 +41096,36 @@ module \dec_o
   end
   process $group_7
     assign \spr_o_ok 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:289"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:299"
     switch \sel_in
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:290"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:300"
       attribute \nmigen.decoding "RT/1"
       case 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:293"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:303"
       attribute \nmigen.decoding "RA/2"
       case 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:296"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:306"
       attribute \nmigen.decoding "SPR/3"
       case 2'11
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:300"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:310"
         switch { $13 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:300"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:310"
           case 1'1
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:301"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:311"
             switch \spr
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:303"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:313"
               case 10'0000001001
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:306"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:316"
               case 10'0000001000
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:309"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:319"
               case 10'1100101111
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:312"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:322"
               case 10'0000011010
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:315"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:325"
               case 10'0000011011
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:318"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:328"
               case 10'0000000001
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:322"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:332"
               case
                 assign \spr_o_ok 1'1
             end
@@ -41418,7 +41137,7 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.pdecode2.dec_o2"
 module \dec_o2
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:353"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:363"
   wire width 1 input 0 \lk
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -41512,9 +41231,9 @@ module \dec_o2
   wire width 2 input 6 \upd
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
   wire width 5 input 7 \RA
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:363"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373"
   wire width 1 $1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:363"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373"
   cell $eq $2
     parameter \A_SIGNED 0
     parameter \A_WIDTH 2
@@ -41538,9 +41257,9 @@ module \dec_o2
   process $group_0
     assign \reg_o 5'00000
     assign \reg_o_ok 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:363"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373"
     switch { $1 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:363"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373"
       case 1'1
         assign { \reg_o_ok \reg_o } $3
         assign \reg_o_ok 1'1
@@ -41549,18 +41268,18 @@ module \dec_o2
   end
   process $group_2
     assign \fast_o 3'000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:370"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:380"
     switch \internal_op
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:383"
       attribute \nmigen.decoding "OP_BC/7|OP_B/6|OP_BCREG/8"
       case 7'0000111, 7'0000110, 7'0001000
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:374"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:384"
         switch { \lk }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:374"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:384"
           case 1'1
             assign \fast_o 3'011
         end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:379"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:389"
       attribute \nmigen.decoding "OP_RFID/70"
       case 7'1000110
         assign \fast_o 3'110
@@ -41569,18 +41288,18 @@ module \dec_o2
   end
   process $group_3
     assign \fast_o_ok 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:370"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:380"
     switch \internal_op
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:383"
       attribute \nmigen.decoding "OP_BC/7|OP_B/6|OP_BCREG/8"
       case 7'0000111, 7'0000110, 7'0001000
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:374"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:384"
         switch { \lk }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:374"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:384"
           case 1'1
             assign \fast_o_ok 1'1
         end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:379"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:389"
       attribute \nmigen.decoding "OP_RFID/70"
       case 7'1000110
         assign \fast_o_ok 1'1
@@ -41595,7 +41314,7 @@ module \dec_rc
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "RC"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:394"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404"
   wire width 2 input 0 \sel_in
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 1 \rc
@@ -41605,17 +41324,17 @@ module \dec_rc
   wire width 1 input 3 \Rc
   process $group_0
     assign \rc 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:403"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:413"
     switch \sel_in
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:414"
       attribute \nmigen.decoding "RC/2"
       case 2'10
         assign \rc \Rc
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:407"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417"
       attribute \nmigen.decoding "ONE/1"
       case 2'01
         assign \rc 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:410"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:420"
       attribute \nmigen.decoding "NONE/0"
       case 2'00
         assign \rc 1'0
@@ -41624,17 +41343,17 @@ module \dec_rc
   end
   process $group_1
     assign \rc_ok 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:403"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:413"
     switch \sel_in
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:414"
       attribute \nmigen.decoding "RC/2"
       case 2'10
         assign \rc_ok 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:407"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417"
       attribute \nmigen.decoding "ONE/1"
       case 2'01
         assign \rc_ok 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:410"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:420"
       attribute \nmigen.decoding "NONE/0"
       case 2'00
         assign \rc_ok 1'1
@@ -41649,7 +41368,7 @@ module \dec_oe
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "RC"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:431"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441"
   wire width 2 input 0 \sel_in
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
@@ -41734,17 +41453,17 @@ module \dec_oe
   wire width 1 input 4 \OE
   process $group_0
     assign \oe 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:440"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450"
     switch \internal_op
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:443"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:453"
       attribute \nmigen.decoding "OP_MUL_H64/51|OP_MUL_H32/52"
       case 7'0110011, 7'0110100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:447"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:457"
       attribute \nmigen.decoding ""
       case
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:449"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:459"
         switch \sel_in
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:460"
           attribute \nmigen.decoding "RC/2"
           case 2'10
             assign \oe \OE
@@ -41754,17 +41473,17 @@ module \dec_oe
   end
   process $group_1
     assign \oe_ok 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:440"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450"
     switch \internal_op
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:443"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:453"
       attribute \nmigen.decoding "OP_MUL_H64/51|OP_MUL_H32/52"
       case 7'0110011, 7'0110100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:447"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:457"
       attribute \nmigen.decoding ""
       case
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:449"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:459"
         switch \sel_in
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:460"
           attribute \nmigen.decoding "RC/2"
           case 2'10
             assign \oe_ok 1'1
@@ -41784,7 +41503,7 @@ module \dec_cr_in
   attribute \enum_value_100 "BA_BB"
   attribute \enum_value_101 "BC"
   attribute \enum_value_110 "WHOLE_REG"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:466"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:476"
   wire width 3 input 0 \sel_in
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 3 output 1 \cr_bitfield
@@ -41798,7 +41517,7 @@ module \dec_cr_in
   wire width 3 output 5 \cr_bitfield_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 6 \cr_bitfield_o_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:481"
   wire width 1 output 7 \whole_reg
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:335"
   wire width 5 input 8 \BB
@@ -41815,32 +41534,32 @@ module \dec_cr_in
   process $group_0
     assign \cr_bitfield_ok 1'0
     assign \cr_bitfield_ok 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:480"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:490"
     switch \sel_in
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:481"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:491"
       attribute \nmigen.decoding "NONE/0"
       case 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:483"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:493"
       attribute \nmigen.decoding "CR0/1"
       case 3'001
         assign \cr_bitfield_ok 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:496"
       attribute \nmigen.decoding "BI/2"
       case 3'010
         assign \cr_bitfield_ok 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:489"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499"
       attribute \nmigen.decoding "BFA/3"
       case 3'011
         assign \cr_bitfield_ok 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:492"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502"
       attribute \nmigen.decoding "BA_BB/4"
       case 3'100
         assign \cr_bitfield_ok 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:509"
       attribute \nmigen.decoding "BC/5"
       case 3'101
         assign \cr_bitfield_ok 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:512"
       attribute \nmigen.decoding "WHOLE_REG/6"
       case 3'110
     end
@@ -41849,28 +41568,28 @@ module \dec_cr_in
   process $group_1
     assign \cr_bitfield_b_ok 1'0
     assign \cr_bitfield_b_ok 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:480"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:490"
     switch \sel_in
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:481"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:491"
       attribute \nmigen.decoding "NONE/0"
       case 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:483"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:493"
       attribute \nmigen.decoding "CR0/1"
       case 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:496"
       attribute \nmigen.decoding "BI/2"
       case 3'010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:489"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499"
       attribute \nmigen.decoding "BFA/3"
       case 3'011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:492"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502"
       attribute \nmigen.decoding "BA_BB/4"
       case 3'100
         assign \cr_bitfield_b_ok 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:509"
       attribute \nmigen.decoding "BC/5"
       case 3'101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:512"
       attribute \nmigen.decoding "WHOLE_REG/6"
       case 3'110
     end
@@ -41879,27 +41598,27 @@ module \dec_cr_in
   process $group_2
     assign \whole_reg 1'0
     assign \whole_reg 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:480"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:490"
     switch \sel_in
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:481"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:491"
       attribute \nmigen.decoding "NONE/0"
       case 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:483"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:493"
       attribute \nmigen.decoding "CR0/1"
       case 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:496"
       attribute \nmigen.decoding "BI/2"
       case 3'010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:489"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499"
       attribute \nmigen.decoding "BFA/3"
       case 3'011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:492"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502"
       attribute \nmigen.decoding "BA_BB/4"
       case 3'100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:509"
       attribute \nmigen.decoding "BC/5"
       case 3'101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:512"
       attribute \nmigen.decoding "WHOLE_REG/6"
       case 3'110
         assign \whole_reg 1'1
@@ -41908,32 +41627,32 @@ module \dec_cr_in
   end
   process $group_3
     assign \cr_bitfield 3'000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:480"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:490"
     switch \sel_in
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:481"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:491"
       attribute \nmigen.decoding "NONE/0"
       case 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:483"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:493"
       attribute \nmigen.decoding "CR0/1"
       case 3'001
         assign \cr_bitfield 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:496"
       attribute \nmigen.decoding "BI/2"
       case 3'010
         assign \cr_bitfield \BI [4:2]
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:489"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499"
       attribute \nmigen.decoding "BFA/3"
       case 3'011
         assign \cr_bitfield \X_BFA
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:492"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502"
       attribute \nmigen.decoding "BA_BB/4"
       case 3'100
         assign \cr_bitfield \BA [4:2]
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:509"
       attribute \nmigen.decoding "BC/5"
       case 3'101
         assign \cr_bitfield \BC [4:2]
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:512"
       attribute \nmigen.decoding "WHOLE_REG/6"
       case 3'110
     end
@@ -41941,28 +41660,28 @@ module \dec_cr_in
   end
   process $group_4
     assign \cr_bitfield_b 3'000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:480"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:490"
     switch \sel_in
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:481"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:491"
       attribute \nmigen.decoding "NONE/0"
       case 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:483"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:493"
       attribute \nmigen.decoding "CR0/1"
       case 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:496"
       attribute \nmigen.decoding "BI/2"
       case 3'010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:489"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499"
       attribute \nmigen.decoding "BFA/3"
       case 3'011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:492"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502"
       attribute \nmigen.decoding "BA_BB/4"
       case 3'100
         assign \cr_bitfield_b \BB [4:2]
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:509"
       attribute \nmigen.decoding "BC/5"
       case 3'101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:512"
       attribute \nmigen.decoding "WHOLE_REG/6"
       case 3'110
     end
@@ -41970,28 +41689,28 @@ module \dec_cr_in
   end
   process $group_5
     assign \cr_bitfield_o 3'000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:480"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:490"
     switch \sel_in
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:481"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:491"
       attribute \nmigen.decoding "NONE/0"
       case 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:483"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:493"
       attribute \nmigen.decoding "CR0/1"
       case 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:496"
       attribute \nmigen.decoding "BI/2"
       case 3'010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:489"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499"
       attribute \nmigen.decoding "BFA/3"
       case 3'011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:492"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502"
       attribute \nmigen.decoding "BA_BB/4"
       case 3'100
         assign \cr_bitfield_o \BT [4:2]
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:509"
       attribute \nmigen.decoding "BC/5"
       case 3'101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:512"
       attribute \nmigen.decoding "WHOLE_REG/6"
       case 3'110
     end
@@ -41999,28 +41718,28 @@ module \dec_cr_in
   end
   process $group_6
     assign \cr_bitfield_o_ok 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:480"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:490"
     switch \sel_in
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:481"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:491"
       attribute \nmigen.decoding "NONE/0"
       case 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:483"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:493"
       attribute \nmigen.decoding "CR0/1"
       case 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:486"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:496"
       attribute \nmigen.decoding "BI/2"
       case 3'010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:489"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499"
       attribute \nmigen.decoding "BFA/3"
       case 3'011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:492"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502"
       attribute \nmigen.decoding "BA_BB/4"
       case 3'100
         assign \cr_bitfield_o_ok 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:499"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:509"
       attribute \nmigen.decoding "BC/5"
       case 3'101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:512"
       attribute \nmigen.decoding "WHOLE_REG/6"
       case 3'110
     end
@@ -42036,15 +41755,15 @@ module \dec_cr_out
   attribute \enum_value_010 "BF"
   attribute \enum_value_011 "BT"
   attribute \enum_value_100 "WHOLE_REG"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:518"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528"
   wire width 3 input 0 \sel_in
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:517"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:527"
   wire width 1 input 1 \rc_in
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 3 output 2 \cr_bitfield
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 3 \cr_bitfield_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:531"
   wire width 1 output 4 \whole_reg
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:348"
   wire width 3 input 5 \X_BF
@@ -42053,24 +41772,24 @@ module \dec_cr_out
   process $group_0
     assign \cr_bitfield_ok 1'0
     assign \cr_bitfield_ok 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:539"
     switch \sel_in
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:530"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:540"
       attribute \nmigen.decoding "NONE/0"
       case 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:542"
       attribute \nmigen.decoding "CR0/1"
       case 3'001
         assign \cr_bitfield_ok \rc_in
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:535"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:545"
       attribute \nmigen.decoding "BF/2"
       case 3'010
         assign \cr_bitfield_ok 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:538"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:548"
       attribute \nmigen.decoding "BT/3"
       case 3'011
         assign \cr_bitfield_ok 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:541"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:551"
       attribute \nmigen.decoding "WHOLE_REG/4"
       case 3'100
     end
@@ -42079,21 +41798,21 @@ module \dec_cr_out
   process $group_1
     assign \whole_reg 1'0
     assign \whole_reg 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:539"
     switch \sel_in
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:530"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:540"
       attribute \nmigen.decoding "NONE/0"
       case 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:542"
       attribute \nmigen.decoding "CR0/1"
       case 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:535"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:545"
       attribute \nmigen.decoding "BF/2"
       case 3'010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:538"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:548"
       attribute \nmigen.decoding "BT/3"
       case 3'011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:541"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:551"
       attribute \nmigen.decoding "WHOLE_REG/4"
       case 3'100
         assign \whole_reg 1'1
@@ -42102,24 +41821,24 @@ module \dec_cr_out
   end
   process $group_2
     assign \cr_bitfield 3'000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:539"
     switch \sel_in
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:530"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:540"
       attribute \nmigen.decoding "NONE/0"
       case 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:542"
       attribute \nmigen.decoding "CR0/1"
       case 3'001
         assign \cr_bitfield 3'000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:535"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:545"
       attribute \nmigen.decoding "BF/2"
       case 3'010
         assign \cr_bitfield \X_BF
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:538"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:548"
       attribute \nmigen.decoding "BT/3"
       case 3'011
         assign \cr_bitfield \XL_BT [4:2]
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:541"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:551"
       attribute \nmigen.decoding "WHOLE_REG/4"
       case 3'100
     end
@@ -42133,10 +41852,10 @@ module \pdecode2
   wire width 1 input 0 \bigendian
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:331"
   wire width 32 input 1 \raw_opcode_in
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:574"
-  wire width 64 input 2 \msr
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575"
-  wire width 64 input 3 \cia
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:9"
+  wire width 64 input 2 \dec2_msr
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:8"
+  wire width 64 input 3 \dec2_pc
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
   attribute \enum_value_0000001 "OP_NOP"
@@ -42279,7 +41998,7 @@ module \pdecode2
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 29 \cr_in2_ok$1
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:35"
-  wire width 64 output 30 \cia$2
+  wire width 64 output 30 \cia
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:42"
   wire width 1 output 31 \lk
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
@@ -42287,7 +42006,7 @@ module \pdecode2
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 output 33 \fast2_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:34"
-  wire width 64 output 34 \msr$3
+  wire width 64 output 34 \msr
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:58"
   wire width 5 output 35 \traptype
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:59"
@@ -42322,7 +42041,7 @@ module \pdecode2
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 3 output 48 \cr_in2
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 3 output 49 \cr_in2$4
+  wire width 3 output 49 \cr_in2$2
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 3 output 50 \fast1
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
@@ -42859,13 +42578,13 @@ module \pdecode2
   attribute \enum_value_010 "RA_OR_ZERO"
   attribute \enum_value_011 "SPR"
   attribute \enum_value_100 "RS"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:76"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:77"
   wire width 3 \dec_a_sel_in
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 5 \dec_a_reg_a
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \dec_a_reg_a_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:79"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:80"
   wire width 1 \dec_a_immz_out
   attribute \enum_base_type "SPR"
   attribute \enum_value_0000000001 "XER"
@@ -43017,7 +42736,7 @@ module \pdecode2
   attribute \enum_value_1011 "CONST_SH32"
   attribute \enum_value_1100 "SPR"
   attribute \enum_value_1101 "RS"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:169"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:170"
   wire width 4 \dec_b_sel_in
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 5 \dec_b_reg_b
@@ -43055,7 +42774,7 @@ module \pdecode2
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "RS"
   attribute \enum_value_10 "RB"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:247"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:257"
   wire width 2 \dec_c_sel_in
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 5 \dec_c_reg_c
@@ -43073,7 +42792,7 @@ module \pdecode2
   attribute \enum_value_01 "RT"
   attribute \enum_value_10 "RA"
   attribute \enum_value_11 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:276"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:286"
   wire width 2 \dec_o_sel_in
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 5 \dec_o_reg_o
@@ -43212,7 +42931,7 @@ module \pdecode2
     connect \BO \dec_BO
     connect \SPR \dec_SPR
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:353"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:363"
   wire width 1 \dec_o2_lk
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 5 \dec_o2_reg_o
@@ -43236,7 +42955,7 @@ module \pdecode2
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "RC"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:394"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404"
   wire width 2 \dec_rc_sel_in
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \dec_rc_rc
@@ -43252,7 +42971,7 @@ module \pdecode2
   attribute \enum_value_00 "NONE"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "RC"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:431"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441"
   wire width 2 \dec_oe_sel_in
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \dec_oe_oe
@@ -43273,7 +42992,7 @@ module \pdecode2
   attribute \enum_value_100 "BA_BB"
   attribute \enum_value_101 "BC"
   attribute \enum_value_110 "WHOLE_REG"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:466"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:476"
   wire width 3 \dec_cr_in_sel_in
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 3 \dec_cr_in_cr_bitfield
@@ -43287,9 +43006,9 @@ module \pdecode2
   wire width 3 \dec_cr_in_cr_bitfield_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \dec_cr_in_cr_bitfield_o_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:471"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:481"
   wire width 1 \dec_cr_in_whole_reg
-  cell \dec_cr_in \dec_cr_in$5
+  cell \dec_cr_in \dec_cr_in$3
     connect \sel_in \dec_cr_in_sel_in
     connect \cr_bitfield \dec_cr_in_cr_bitfield
     connect \cr_bitfield_ok \dec_cr_in_cr_bitfield_ok
@@ -43311,17 +43030,17 @@ module \pdecode2
   attribute \enum_value_010 "BF"
   attribute \enum_value_011 "BT"
   attribute \enum_value_100 "WHOLE_REG"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:518"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528"
   wire width 3 \dec_cr_out_sel_in
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:517"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:527"
   wire width 1 \dec_cr_out_rc_in
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 3 \dec_cr_out_cr_bitfield
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \dec_cr_out_cr_bitfield_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:531"
   wire width 1 \dec_cr_out_whole_reg
-  cell \dec_cr_out \dec_cr_out$6
+  cell \dec_cr_out \dec_cr_out$4
     connect \sel_in \dec_cr_out_sel_in
     connect \rc_in \dec_cr_out_rc_in
     connect \cr_bitfield \dec_cr_out_cr_bitfield
@@ -43346,10 +43065,10 @@ module \pdecode2
   wire width 1 \xer_out
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:72"
   wire width 8 \asmcode
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:680"
-  wire width 1 $7
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:680"
-  cell $eq $8
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:690"
+  wire width 1 $5
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:690"
+  cell $eq $6
     parameter \A_SIGNED 0
     parameter \A_WIDTH 7
     parameter \B_SIGNED 0
@@ -43357,12 +43076,12 @@ module \pdecode2
     parameter \Y_WIDTH 1
     connect \A \dec_internal_op
     connect \B 7'0101110
-    connect \Y $7
+    connect \Y $5
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:682"
-  wire width 1 $9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:682"
-  cell $eq $10
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:692"
+  wire width 1 $7
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:692"
+  cell $eq $8
     parameter \A_SIGNED 0
     parameter \A_WIDTH 7
     parameter \B_SIGNED 0
@@ -43370,12 +43089,12 @@ module \pdecode2
     parameter \Y_WIDTH 1
     connect \A \dec_internal_op
     connect \B 7'0110001
-    connect \Y $9
+    connect \Y $7
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:686"
-  wire width 1 $11
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:686"
-  cell $eq $12
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:696"
+  wire width 1 $9
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:696"
+  cell $eq $10
     parameter \A_SIGNED 0
     parameter \A_WIDTH 7
     parameter \B_SIGNED 0
@@ -43383,27 +43102,27 @@ module \pdecode2
     parameter \Y_WIDTH 1
     connect \A \dec_internal_op
     connect \B 7'0111111
-    connect \Y $11
+    connect \Y $9
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:37"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:38"
   wire width 1 \is_priv_insn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:692"
-  wire width 1 $13
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:692"
-  cell $and $14
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:702"
+  wire width 1 $11
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:702"
+  cell $and $12
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \is_priv_insn
-    connect \B \msr [14]
-    connect \Y $13
+    connect \B \dec2_msr [14]
+    connect \Y $11
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:700"
-  wire width 1 $15
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:700"
-  cell $eq $16
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:710"
+  wire width 1 $13
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:710"
+  cell $eq $14
     parameter \A_SIGNED 0
     parameter \A_WIDTH 7
     parameter \B_SIGNED 0
@@ -43411,12 +43130,12 @@ module \pdecode2
     parameter \Y_WIDTH 1
     connect \A \dec_internal_op
     connect \B 7'0000000
-    connect \Y $15
+    connect \Y $13
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:706"
-  wire width 1 $17
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:706"
-  cell $eq $18
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:716"
+  wire width 1 $15
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:716"
+  cell $eq $16
     parameter \A_SIGNED 0
     parameter \A_WIDTH 7
     parameter \B_SIGNED 0
@@ -43424,12 +43143,12 @@ module \pdecode2
     parameter \Y_WIDTH 1
     connect \A \insn_type
     connect \B 7'0111111
-    connect \Y $17
+    connect \Y $15
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:707"
-  wire width 1 $19
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:707"
-  cell $eq $20
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:717"
+  wire width 1 $17
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:717"
+  cell $eq $18
     parameter \A_SIGNED 0
     parameter \A_WIDTH 7
     parameter \B_SIGNED 0
@@ -43437,25 +43156,25 @@ module \pdecode2
     parameter \Y_WIDTH 1
     connect \A \insn_type
     connect \B 7'1001001
-    connect \Y $19
+    connect \Y $17
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:707"
-  wire width 1 $21
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:707"
-  cell $or $22
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:717"
+  wire width 1 $19
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:717"
+  cell $or $20
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $17
-    connect \B $19
-    connect \Y $21
+    connect \A $15
+    connect \B $17
+    connect \Y $19
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:716"
-  wire width 1 $23
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:716"
-  cell $eq $24
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:726"
+  wire width 1 $21
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:726"
+  cell $eq $22
     parameter \A_SIGNED 0
     parameter \A_WIDTH 7
     parameter \B_SIGNED 0
@@ -43463,12 +43182,12 @@ module \pdecode2
     parameter \Y_WIDTH 1
     connect \A \insn_type
     connect \B 7'1000110
-    connect \Y $23
+    connect \Y $21
   end
   process $group_82
     assign \insn 32'00000000000000000000000000000000
-    assign \msr$3 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \cia$2 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \msr 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \cia 64'0000000000000000000000000000000000000000000000000000000000000000
     assign \insn_type 7'0000000
     assign \fn_unit 11'00000000000
     assign \reg1 5'00000
@@ -43504,7 +43223,7 @@ module \pdecode2
     assign \cr_in1_ok 1'0
     assign \cr_in2 3'000
     assign \cr_in2_ok 1'0
-    assign \cr_in2$4 3'000
+    assign \cr_in2$2 3'000
     assign \cr_in2_ok$1 1'0
     assign \cr_out 3'000
     assign \cr_out_ok 1'0
@@ -43530,8 +43249,8 @@ module \pdecode2
     assign \asmcode 8'00000000
     assign \traptype 5'00000
     assign \insn \dec_opcode_in
-    assign \msr$3 \msr
-    assign \cia$2 \cia
+    assign \msr \dec2_msr
+    assign \cia \dec2_pc
     assign \insn_type \dec_internal_op
     assign \fn_unit \dec_function_unit
     assign { \reg1_ok \reg1 } { \dec_a_reg_a_ok \dec_a_reg_a }
@@ -43551,7 +43270,7 @@ module \pdecode2
     assign { \fasto2_ok \fasto2 } { \dec_o2_fast_o_ok \dec_o2_fast_o }
     assign { \cr_in1_ok \cr_in1 } { \dec_cr_in_cr_bitfield_ok \dec_cr_in_cr_bitfield }
     assign { \cr_in2_ok \cr_in2 } { \dec_cr_in_cr_bitfield_b_ok \dec_cr_in_cr_bitfield_b }
-    assign { \cr_in2_ok$1 \cr_in2$4 } { \dec_cr_in_cr_bitfield_o_ok \dec_cr_in_cr_bitfield_o }
+    assign { \cr_in2_ok$1 \cr_in2$2 } { \dec_cr_in_cr_bitfield_o_ok \dec_cr_in_cr_bitfield_o }
     assign { \cr_out_ok \cr_out } { \dec_cr_out_cr_bitfield_ok \dec_cr_out_cr_bitfield }
     assign \read_cr_whole \dec_cr_in_whole_reg
     assign \write_cr_whole \dec_cr_out_whole_reg
@@ -43563,9 +43282,9 @@ module \pdecode2
     assign \output_carry \dec_cry_out
     assign \is_32bit \dec_is_32b
     assign \is_signed \dec_sgn
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:666"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:676"
     switch { \dec_lk }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:666"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:676"
       case 1'1
         assign \lk \dec_LK
     end
@@ -43589,59 +43308,59 @@ module \pdecode2
       case
         assign \output_cr \dec_cr_out [0]
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:680"
-    switch { $7 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:680"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:690"
+    switch { $5 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:690"
       case 1'1
         assign \xer_in 1'1
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:682"
-    switch { $9 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:682"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:692"
+    switch { $7 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:692"
       case 1'1
         assign \xer_out 1'1
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:686"
-    switch { $11 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:686"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:696"
+    switch { $9 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:696"
       case 1'1
         assign \trapaddr 13'0000001110000
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:692"
-    switch { $15 $13 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:692"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:702"
+    switch { $13 $11 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:702"
       case 2'-1
-        assign { \write_cr0 \write_cr_whole \read_cr_whole \trapaddr \traptype \ldst_mode \sign_extend \byte_reverse \data_len \is_signed \is_32bit \invert_out \output_cr \input_cr \output_carry \input_carry \zero_a \invert_a \oe_ok \oe \rc_ok \rc \lk \imm_ok \imm \fn_unit \insn_type \insn \cia$2 \msr$3 { \cr_out_ok \cr_out } { \cr_in2_ok$1 \cr_in2$4 } { \cr_in2_ok \cr_in2 } { \cr_in1_ok \cr_in1 } { \fasto2_ok \fasto2 } { \fasto1_ok \fasto1 } { \fast2_ok \fast2 } { \fast1_ok \fast1 } \xer_out \xer_in { \spr1_ok \spr1 } { \spro_ok \spro } { \reg3_ok \reg3 } { \reg2_ok \reg2 } { \reg1_ok \reg1 } { \ea_ok \ea } { \rego_ok \rego } \asmcode } 381'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
+        assign { \write_cr0 \write_cr_whole \read_cr_whole \trapaddr \traptype \ldst_mode \sign_extend \byte_reverse \data_len \is_signed \is_32bit \invert_out \output_cr \input_cr \output_carry \input_carry \zero_a \invert_a \oe_ok \oe \rc_ok \rc \lk \imm_ok \imm \fn_unit \insn_type \insn \cia \msr { \cr_out_ok \cr_out } { \cr_in2_ok$1 \cr_in2$2 } { \cr_in2_ok \cr_in2 } { \cr_in1_ok \cr_in1 } { \fasto2_ok \fasto2 } { \fasto1_ok \fasto1 } { \fast2_ok \fast2 } { \fast1_ok \fast1 } \xer_out \xer_in { \spr1_ok \spr1 } { \spro_ok \spro } { \reg3_ok \reg3 } { \reg2_ok \reg2 } { \reg1_ok \reg1 } { \ea_ok \ea } { \rego_ok \rego } \asmcode } 381'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
         assign \insn \dec_opcode_in
         assign \insn_type 7'0111111
         assign \fn_unit 11'00010000000
         assign \trapaddr 13'0000001110000
         assign \traptype 5'00010
-        assign \msr$3 \msr
-        assign \cia$2 \cia
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:700"
+        assign \msr \dec2_msr
+        assign \cia \dec2_pc
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:710"
       case 2'1-
-        assign { \write_cr0 \write_cr_whole \read_cr_whole \trapaddr \traptype \ldst_mode \sign_extend \byte_reverse \data_len \is_signed \is_32bit \invert_out \output_cr \input_cr \output_carry \input_carry \zero_a \invert_a \oe_ok \oe \rc_ok \rc \lk \imm_ok \imm \fn_unit \insn_type \insn \cia$2 \msr$3 { \cr_out_ok \cr_out } { \cr_in2_ok$1 \cr_in2$4 } { \cr_in2_ok \cr_in2 } { \cr_in1_ok \cr_in1 } { \fasto2_ok \fasto2 } { \fasto1_ok \fasto1 } { \fast2_ok \fast2 } { \fast1_ok \fast1 } \xer_out \xer_in { \spr1_ok \spr1 } { \spro_ok \spro } { \reg3_ok \reg3 } { \reg2_ok \reg2 } { \reg1_ok \reg1 } { \ea_ok \ea } { \rego_ok \rego } \asmcode } 381'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
+        assign { \write_cr0 \write_cr_whole \read_cr_whole \trapaddr \traptype \ldst_mode \sign_extend \byte_reverse \data_len \is_signed \is_32bit \invert_out \output_cr \input_cr \output_carry \input_carry \zero_a \invert_a \oe_ok \oe \rc_ok \rc \lk \imm_ok \imm \fn_unit \insn_type \insn \cia \msr { \cr_out_ok \cr_out } { \cr_in2_ok$1 \cr_in2$2 } { \cr_in2_ok \cr_in2 } { \cr_in1_ok \cr_in1 } { \fasto2_ok \fasto2 } { \fasto1_ok \fasto1 } { \fast2_ok \fast2 } { \fast1_ok \fast1 } \xer_out \xer_in { \spr1_ok \spr1 } { \spro_ok \spro } { \reg3_ok \reg3 } { \reg2_ok \reg2 } { \reg1_ok \reg1 } { \ea_ok \ea } { \rego_ok \rego } \asmcode } 381'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
         assign \insn \dec_opcode_in
         assign \insn_type 7'0111111
         assign \fn_unit 11'00010000000
         assign \trapaddr 13'0000001110000
         assign \traptype 5'10000
-        assign \msr$3 \msr
-        assign \cia$2 \cia
+        assign \msr \dec2_msr
+        assign \cia \dec2_pc
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:707"
-    switch { $21 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:707"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:717"
+    switch { $19 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:717"
       case 1'1
         assign \fasto1 3'101
         assign \fasto1_ok 1'1
         assign \fasto2 3'110
         assign \fasto2_ok 1'1
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:716"
-    switch { $23 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:716"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:726"
+    switch { $21 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:726"
       case 1'1
         assign \fast1 3'101
         assign \fast1_ok 1'1
@@ -43650,69 +43369,69 @@ module \pdecode2
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:77"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:78"
   wire width 32 \insn_in
   process $group_1
     assign \insn_in 32'00000000000000000000000000000000
     assign \insn_in \dec_opcode_in
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:170"
-  wire width 32 \insn_in$25
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:171"
+  wire width 32 \insn_in$23
   process $group_2
+    assign \insn_in$23 32'00000000000000000000000000000000
+    assign \insn_in$23 \dec_opcode_in
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258"
+  wire width 32 \insn_in$24
+  process $group_3
+    assign \insn_in$24 32'00000000000000000000000000000000
+    assign \insn_in$24 \dec_opcode_in
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:287"
+  wire width 32 \insn_in$25
+  process $group_4
     assign \insn_in$25 32'00000000000000000000000000000000
     assign \insn_in$25 \dec_opcode_in
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:364"
   wire width 32 \insn_in$26
-  process $group_3
+  process $group_5
     assign \insn_in$26 32'00000000000000000000000000000000
     assign \insn_in$26 \dec_opcode_in
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:277"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:405"
   wire width 32 \insn_in$27
-  process $group_4
+  process $group_6
     assign \insn_in$27 32'00000000000000000000000000000000
     assign \insn_in$27 \dec_opcode_in
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:354"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442"
   wire width 32 \insn_in$28
-  process $group_5
+  process $group_7
     assign \insn_in$28 32'00000000000000000000000000000000
     assign \insn_in$28 \dec_opcode_in
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:395"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:477"
   wire width 32 \insn_in$29
-  process $group_6
+  process $group_8
     assign \insn_in$29 32'00000000000000000000000000000000
     assign \insn_in$29 \dec_opcode_in
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:432"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:529"
   wire width 32 \insn_in$30
-  process $group_7
+  process $group_9
     assign \insn_in$30 32'00000000000000000000000000000000
     assign \insn_in$30 \dec_opcode_in
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:467"
-  wire width 32 \insn_in$31
-  process $group_8
-    assign \insn_in$31 32'00000000000000000000000000000000
-    assign \insn_in$31 \dec_opcode_in
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:519"
-  wire width 32 \insn_in$32
-  process $group_9
-    assign \insn_in$32 32'00000000000000000000000000000000
-    assign \insn_in$32 \dec_opcode_in
-    sync init
-  end
   process $group_10
     assign \dec_a_sel_in 3'000
     assign \dec_a_sel_in \dec_in1_sel
@@ -43738,7 +43457,7 @@ module \pdecode2
   attribute \enum_value_01 "RT"
   attribute \enum_value_10 "RA"
   attribute \enum_value_11 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:352"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:362"
   wire width 2 \sel_in
   process $group_14
     assign \sel_in 2'00
@@ -43777,18 +43496,18 @@ module \pdecode2
   end
   process $group_81
     assign \is_priv_insn 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:38"
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:39"
     switch \dec_internal_op
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:40"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:41"
       attribute \nmigen.decoding "OP_ATTN/5|OP_MFMSR/71|OP_MTMSRD/72|OP_MTMSR/74|OP_RFID/70"
       case 7'0000101, 7'1000111, 7'1001000, 7'1001010, 7'1000110
         assign \is_priv_insn 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:44"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:45"
       attribute \nmigen.decoding "OP_MFSPR/46|OP_MTSPR/49"
       case 7'0101110, 7'0110001
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:45"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:46"
         switch { \insn [20] }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:45"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:46"
           case 1'1
             assign \is_priv_insn 1'1
         end
@@ -46001,10 +45720,10 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu_alu0.pipe"
 module \pipe
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153"
   wire width 1 input 2 \p_valid_i
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154"
@@ -47769,13 +47488,13 @@ module \pipe
         assign \r_busy$next 1'0
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \r_busy$next 1'0
     end
     sync init
       update \r_busy 1'0
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \r_busy \r_busy$next
   end
   process $group_108
@@ -47791,7 +47510,7 @@ module \pipe
     end
     sync init
       update \muxid$1 2'00
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \muxid$1 \muxid$1$next
   end
   process $group_109
@@ -47823,7 +47542,7 @@ module \pipe
         assign { \alu_op__insn$19$next \alu_op__data_len$18$next \alu_op__is_signed$17$next \alu_op__is_32bit$16$next \alu_op__output_carry$15$next \alu_op__input_carry$14$next \alu_op__write_cr0$13$next \alu_op__invert_out$12$next \alu_op__zero_a$11$next \alu_op__invert_a$10$next { \alu_op__oe__oe_ok$9$next \alu_op__oe__oe$8$next } { \alu_op__rc__rc_ok$7$next \alu_op__rc__rc$6$next } { \alu_op__imm_data__imm_ok$5$next \alu_op__imm_data__imm$4$next } \alu_op__fn_unit$3$next \alu_op__insn_type$2$next } { \alu_op__insn$117 \alu_op__data_len$116 \alu_op__is_signed$115 \alu_op__is_32bit$114 \alu_op__output_carry$113 \alu_op__input_carry$112 \alu_op__write_cr0$111 \alu_op__invert_out$110 \alu_op__zero_a$109 \alu_op__invert_a$108 { \alu_op__oe__oe_ok$107 \alu_op__oe__oe$106 } { \alu_op__rc__rc_ok$105 \alu_op__rc__rc$104 } { \alu_op__imm_data__imm_ok$103 \alu_op__imm_data__imm$102 } \alu_op__fn_unit$101 \alu_op__insn_type$100 }
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \alu_op__imm_data__imm$4$next 64'0000000000000000000000000000000000000000000000000000000000000000
         assign \alu_op__imm_data__imm_ok$5$next 1'0
@@ -47851,7 +47570,7 @@ module \pipe
       update \alu_op__is_signed$17 1'0
       update \alu_op__data_len$18 4'0000
       update \alu_op__insn$19 32'00000000000000000000000000000000
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \alu_op__insn_type$2 \alu_op__insn_type$2$next
       update \alu_op__fn_unit$3 \alu_op__fn_unit$3$next
       update \alu_op__imm_data__imm$4 \alu_op__imm_data__imm$4$next
@@ -47884,14 +47603,14 @@ module \pipe
         assign { \o_ok$next \o$next } { \o_ok$119 \o$118 }
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \o_ok$next 1'0
     end
     sync init
       update \o 64'0000000000000000000000000000000000000000000000000000000000000000
       update \o_ok 1'0
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \o \o$next
       update \o_ok \o_ok$next
   end
@@ -47908,14 +47627,14 @@ module \pipe
         assign { \cr_a_ok$next \cr_a$next } { \cr_a_ok$121 \cr_a$120 }
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \cr_a_ok$next 1'0
     end
     sync init
       update \cr_a 4'0000
       update \cr_a_ok 1'0
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \cr_a \cr_a$next
       update \cr_a_ok \cr_a_ok$next
   end
@@ -47932,14 +47651,14 @@ module \pipe
         assign { \xer_ca_ok$next \xer_ca$20$next } { \xer_ca_ok$123 \xer_ca$122 }
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \xer_ca_ok$next 1'0
     end
     sync init
       update \xer_ca$20 2'00
       update \xer_ca_ok 1'0
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \xer_ca$20 \xer_ca$20$next
       update \xer_ca_ok \xer_ca_ok$next
   end
@@ -47956,14 +47675,14 @@ module \pipe
         assign { \xer_ov_ok$next \xer_ov$next } { \xer_ov_ok$125 \xer_ov$124 }
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \xer_ov_ok$next 1'0
     end
     sync init
       update \xer_ov 2'00
       update \xer_ov_ok 1'0
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \xer_ov \xer_ov$next
       update \xer_ov_ok \xer_ov_ok$next
   end
@@ -47980,14 +47699,14 @@ module \pipe
         assign { \xer_so_ok$next \xer_so$21$next } { \xer_so_ok$127 \xer_so$126 }
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \xer_so_ok$next 1'0
     end
     sync init
       update \xer_so$21 1'0
       update \xer_so_ok 1'0
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \xer_so$21 \xer_so$21$next
       update \xer_so_ok \xer_so_ok$next
   end
@@ -48006,20 +47725,20 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu_alu0"
 module \alu_alu0
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 2 \o_ok
+  wire width 1 output 1 \o_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 3 \cr_a_ok
+  wire width 1 output 2 \cr_a_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 4 \xer_ca_ok
+  wire width 1 output 3 \xer_ca_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 5 \xer_ov_ok
+  wire width 1 output 4 \xer_ov_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 6 \xer_so_ok
+  wire width 1 output 5 \xer_so_ok
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 6 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
   wire width 1 output 7 \n_valid_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
@@ -48470,8 +48189,8 @@ module \alu_alu0
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \pipe_xer_so_ok
   cell \pipe \pipe
-    connect \rst \rst
-    connect \clk \clk
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
     connect \p_valid_i \pipe_p_valid_i
     connect \p_ready_o \pipe_p_ready_o
     connect \muxid \pipe_muxid
@@ -48787,10 +48506,10 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.src_l"
 module \src_l
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
   wire width 4 input 2 \s_src
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
@@ -48841,13 +48560,13 @@ module \src_l
     assign \q_int$next \q_int
     assign \q_int$next $5
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \q_int$next 4'0000
     end
     sync init
       update \q_int 4'0000
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \q_int \q_int$next
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
@@ -48932,10 +48651,10 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.opc_l"
 module \opc_l
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
   wire width 1 input 2 \s_opc
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
@@ -48986,13 +48705,13 @@ module \opc_l
     assign \q_int$next \q_int
     assign \q_int$next $5
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \q_int$next 1'0
     end
     sync init
       update \q_int 1'0
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \q_int \q_int$next
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
@@ -49077,10 +48796,10 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.req_l"
 module \req_l
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
   wire width 5 output 2 \q_req
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
@@ -49131,13 +48850,13 @@ module \req_l
     assign \q_int$next \q_int
     assign \q_int$next $5
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \q_int$next 5'00000
     end
     sync init
       update \q_int 5'00000
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \q_int \q_int$next
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
@@ -49222,10 +48941,10 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.rst_l"
 module \rst_l
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
   wire width 1 input 2 \s_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
@@ -49274,13 +48993,13 @@ module \rst_l
     assign \q_int$next \q_int
     assign \q_int$next $5
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \q_int$next 1'0
     end
     sync init
       update \q_int 1'0
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \q_int \q_int$next
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
@@ -49367,10 +49086,10 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.rok_l"
 module \rok_l
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
   wire width 1 output 2 \q_rdok
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
@@ -49421,13 +49140,13 @@ module \rok_l
     assign \q_int$next \q_int
     assign \q_int$next $5
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \q_int$next 1'0
     end
     sync init
       update \q_int 1'0
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \q_int \q_int$next
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
@@ -49512,10 +49231,10 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alui_l"
 module \alui_l
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
   wire width 1 output 2 \q_alui
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
@@ -49566,13 +49285,13 @@ module \alui_l
     assign \q_int$next \q_int
     assign \q_int$next $5
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \q_int$next 1'0
     end
     sync init
       update \q_int 1'0
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \q_int \q_int$next
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
@@ -49657,10 +49376,10 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu_l"
 module \alu_l
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
   wire width 1 output 2 \q_alu
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
@@ -49711,13 +49430,13 @@ module \alu_l
     assign \q_int$next \q_int
     assign \q_int$next $5
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \q_int$next 1'0
     end
     sync init
       update \q_int 1'0
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \q_int \q_int$next
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
@@ -49802,10 +49521,8 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.alu0"
 module \alu0
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
   attribute \enum_value_0000001 "OP_NOP"
@@ -49880,7 +49597,7 @@ module \alu0
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 7 input 2 \oper_i_alu_alu0__insn_type
+  wire width 7 input 1 \oper_i_alu_alu0__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -49894,85 +49611,87 @@ module \alu0
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 11 input 3 \oper_i_alu_alu0__fn_unit
+  wire width 11 input 2 \oper_i_alu_alu0__fn_unit
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 64 input 4 \oper_i_alu_alu0__imm_data__imm
+  wire width 64 input 3 \oper_i_alu_alu0__imm_data__imm
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 5 \oper_i_alu_alu0__imm_data__imm_ok
+  wire width 1 input 4 \oper_i_alu_alu0__imm_data__imm_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 6 \oper_i_alu_alu0__rc__rc
+  wire width 1 input 5 \oper_i_alu_alu0__rc__rc
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 7 \oper_i_alu_alu0__rc__rc_ok
+  wire width 1 input 6 \oper_i_alu_alu0__rc__rc_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 8 \oper_i_alu_alu0__oe__oe
+  wire width 1 input 7 \oper_i_alu_alu0__oe__oe
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 9 \oper_i_alu_alu0__oe__oe_ok
+  wire width 1 input 8 \oper_i_alu_alu0__oe__oe_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 10 \oper_i_alu_alu0__invert_a
+  wire width 1 input 9 \oper_i_alu_alu0__invert_a
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 11 \oper_i_alu_alu0__zero_a
+  wire width 1 input 10 \oper_i_alu_alu0__zero_a
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 12 \oper_i_alu_alu0__invert_out
+  wire width 1 input 11 \oper_i_alu_alu0__invert_out
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 13 \oper_i_alu_alu0__write_cr0
+  wire width 1 input 12 \oper_i_alu_alu0__write_cr0
   attribute \enum_base_type "CryIn"
   attribute \enum_value_00 "ZERO"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "CA"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 2 input 14 \oper_i_alu_alu0__input_carry
+  wire width 2 input 13 \oper_i_alu_alu0__input_carry
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 15 \oper_i_alu_alu0__output_carry
+  wire width 1 input 14 \oper_i_alu_alu0__output_carry
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 16 \oper_i_alu_alu0__is_32bit
+  wire width 1 input 15 \oper_i_alu_alu0__is_32bit
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 17 \oper_i_alu_alu0__is_signed
+  wire width 1 input 16 \oper_i_alu_alu0__is_signed
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 4 input 18 \oper_i_alu_alu0__data_len
+  wire width 4 input 17 \oper_i_alu_alu0__data_len
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 32 input 19 \oper_i_alu_alu0__insn
+  wire width 32 input 18 \oper_i_alu_alu0__insn
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
-  wire width 1 input 20 \cu_issue_i
+  wire width 1 input 19 \cu_issue_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:106"
-  wire width 1 output 21 \cu_busy_o
+  wire width 1 output 20 \cu_busy_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
-  wire width 4 input 22 \cu_rdmaskn_i
+  wire width 4 input 21 \cu_rdmaskn_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 4 output 23 \cu_rd__rel_o
+  wire width 4 output 22 \cu_rd__rel_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 4 input 24 \cu_rd__go_i
+  wire width 4 input 23 \cu_rd__go_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
-  wire width 64 input 25 \src1_i
+  wire width 64 input 24 \src1_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
-  wire width 64 input 26 \src2_i
+  wire width 64 input 25 \src2_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
-  wire width 1 input 27 \src3_i
+  wire width 1 input 26 \src3_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
-  wire width 2 input 28 \src4_i
+  wire width 2 input 27 \src4_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 29 \o_ok
+  wire width 1 output 28 \o_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 5 output 30 \cu_wr__rel_o
+  wire width 5 output 29 \cu_wr__rel_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 5 input 31 \cu_wr__go_i
+  wire width 5 input 30 \cu_wr__go_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
-  wire width 64 output 32 \dest1_o
+  wire width 64 output 31 \dest1_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 33 \cr_a_ok
+  wire width 1 output 32 \cr_a_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
-  wire width 4 output 34 \dest2_o
+  wire width 4 output 33 \dest2_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 35 \xer_ca_ok
+  wire width 1 output 34 \xer_ca_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
-  wire width 2 output 36 \dest3_o
+  wire width 2 output 35 \dest3_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 37 \xer_ov_ok
+  wire width 1 output 36 \xer_ov_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
-  wire width 2 output 38 \dest4_o
+  wire width 2 output 37 \dest4_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 39 \xer_so_ok
+  wire width 1 output 38 \xer_so_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
-  wire width 1 output 40 \dest5_o
+  wire width 1 output 39 \dest5_o
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 40 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
   wire width 1 \alu_alu0_n_valid_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
@@ -50125,13 +49844,13 @@ module \alu0
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154"
   wire width 1 \alu_alu0_p_ready_o
   cell \alu_alu0 \alu_alu0
-    connect \rst \rst
-    connect \clk \clk
+    connect \coresync_clk \coresync_clk
     connect \o_ok \o_ok
     connect \cr_a_ok \cr_a_ok
     connect \xer_ca_ok \xer_ca_ok
     connect \xer_ov_ok \xer_ov_ok
     connect \xer_so_ok \xer_so_ok
+    connect \coresync_rst \coresync_rst
     connect \n_valid_o \alu_alu0_n_valid_o
     connect \n_ready_i \alu_alu0_n_ready_i
     connect \o \alu_alu0_o
@@ -50175,8 +49894,8 @@ module \alu0
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
   wire width 4 \src_l_q_src
   cell \src_l \src_l
-    connect \rst \rst
-    connect \clk \clk
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
     connect \s_src \src_l_s_src
     connect \r_src \src_l_r_src
     connect \q_src \src_l_q_src
@@ -50192,8 +49911,8 @@ module \alu0
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
   wire width 1 \opc_l_q_opc
   cell \opc_l \opc_l
-    connect \rst \rst
-    connect \clk \clk
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
     connect \s_opc \opc_l_s_opc
     connect \r_opc \opc_l_r_opc
     connect \q_opc \opc_l_q_opc
@@ -50205,8 +49924,8 @@ module \alu0
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
   wire width 5 \req_l_r_req
   cell \req_l \req_l
-    connect \rst \rst
-    connect \clk \clk
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
     connect \q_req \req_l_q_req
     connect \s_req \req_l_s_req
     connect \r_req \req_l_r_req
@@ -50216,8 +49935,8 @@ module \alu0
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
   wire width 1 \rst_l_r_rst
   cell \rst_l \rst_l
-    connect \rst \rst
-    connect \clk \clk
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
     connect \s_rst \rst_l_s_rst
     connect \r_rst \rst_l_r_rst
   end
@@ -50230,8 +49949,8 @@ module \alu0
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
   wire width 1 \rok_l_r_rdok$next
   cell \rok_l \rok_l
-    connect \rst \rst
-    connect \clk \clk
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
     connect \q_rdok \rok_l_q_rdok
     connect \s_rdok \rok_l_s_rdok
     connect \r_rdok \rok_l_r_rdok
@@ -50245,8 +49964,8 @@ module \alu0
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
   wire width 1 \alui_l_s_alui
   cell \alui_l \alui_l
-    connect \rst \rst
-    connect \clk \clk
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
     connect \q_alui \alui_l_q_alui
     connect \r_alui \alui_l_r_alui
     connect \s_alui \alui_l_s_alui
@@ -50260,8 +49979,8 @@ module \alu0
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
   wire width 1 \alu_l_s_alu
   cell \alu_l \alu_l
-    connect \rst \rst
-    connect \clk \clk
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
     connect \q_alu \alu_l_q_alu
     connect \r_alu \alu_l_r_alu
     connect \s_alu \alu_l_s_alu
@@ -50341,7 +50060,7 @@ module \alu0
     assign \all_rd_dly$next \all_rd
     sync init
       update \all_rd_dly 1'0
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \all_rd_dly \all_rd_dly$next
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:192"
@@ -50390,7 +50109,7 @@ module \alu0
     assign \alu_done_dly$next \alu_done
     sync init
       update \alu_done_dly 1'0
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \alu_done_dly \alu_done_dly$next
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:199"
@@ -50451,13 +50170,13 @@ module \alu0
     assign \prev_wr_go$next \prev_wr_go
     assign \prev_wr_go$next $21
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \prev_wr_go$next 5'00000
     end
     sync init
       update \prev_wr_go 5'00000
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \prev_wr_go \prev_wr_go$next
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107"
@@ -50796,13 +50515,13 @@ module \alu0
     assign \rok_l_r_rdok$next \rok_l_r_rdok
     assign \rok_l_r_rdok$next $65
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \rok_l_r_rdok$next 1'1
     end
     sync init
       update \rok_l_r_rdok 1'1
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \rok_l_r_rdok \rok_l_r_rdok$next
   end
   process $group_17
@@ -50819,52 +50538,52 @@ module \alu0
     assign \opc_l_s_opc$next \opc_l_s_opc
     assign \opc_l_s_opc$next \cu_issue_i
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \opc_l_s_opc$next 1'0
     end
     sync init
       update \opc_l_s_opc 1'0
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \opc_l_s_opc \opc_l_s_opc$next
   end
   process $group_20
     assign \opc_l_r_opc$next \opc_l_r_opc
     assign \opc_l_r_opc$next \req_done
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \opc_l_r_opc$next 1'1
     end
     sync init
       update \opc_l_r_opc 1'1
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \opc_l_r_opc \opc_l_r_opc$next
   end
   process $group_21
     assign \src_l_s_src$next \src_l_s_src
     assign \src_l_s_src$next { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i }
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \src_l_s_src$next 4'0000
     end
     sync init
       update \src_l_s_src 4'0000
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \src_l_s_src \src_l_s_src$next
   end
   process $group_22
     assign \src_l_r_src$next \src_l_r_src
     assign \src_l_r_src$next \reset_r
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \src_l_r_src$next 4'1111
     end
     sync init
       update \src_l_r_src 4'1111
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \src_l_r_src \src_l_r_src$next
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:255"
@@ -51158,7 +50877,7 @@ module \alu0
         assign { \oper_l__insn$next \oper_l__data_len$next \oper_l__is_signed$next \oper_l__is_32bit$next \oper_l__output_carry$next \oper_l__input_carry$next \oper_l__write_cr0$next \oper_l__invert_out$next \oper_l__zero_a$next \oper_l__invert_a$next { \oper_l__oe__oe_ok$next \oper_l__oe__oe$next } { \oper_l__rc__rc_ok$next \oper_l__rc__rc$next } { \oper_l__imm_data__imm_ok$next \oper_l__imm_data__imm$next } \oper_l__fn_unit$next \oper_l__insn_type$next } { \oper_i_alu_alu0__insn \oper_i_alu_alu0__data_len \oper_i_alu_alu0__is_signed \oper_i_alu_alu0__is_32bit \oper_i_alu_alu0__output_carry \oper_i_alu_alu0__input_carry \oper_i_alu_alu0__write_cr0 \oper_i_alu_alu0__invert_out \oper_i_alu_alu0__zero_a \oper_i_alu_alu0__invert_a { \oper_i_alu_alu0__oe__oe_ok \oper_i_alu_alu0__oe__oe } { \oper_i_alu_alu0__rc__rc_ok \oper_i_alu_alu0__rc__rc } { \oper_i_alu_alu0__imm_data__imm_ok \oper_i_alu_alu0__imm_data__imm } \oper_i_alu_alu0__fn_unit \oper_i_alu_alu0__insn_type }
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \oper_l__imm_data__imm$next 64'0000000000000000000000000000000000000000000000000000000000000000
         assign \oper_l__imm_data__imm_ok$next 1'0
@@ -51186,7 +50905,7 @@ module \alu0
       update \oper_l__is_signed 1'0
       update \oper_l__data_len 4'0000
       update \oper_l__insn 32'00000000000000000000000000000000
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \oper_l__insn_type \oper_l__insn_type$next
       update \oper_l__fn_unit \oper_l__fn_unit$next
       update \oper_l__imm_data__imm \oper_l__imm_data__imm$next
@@ -51264,14 +50983,14 @@ module \alu0
         assign { \data_r0_l__o_ok$next \data_r0_l__o$next } { \o_ok \alu_alu0_o }
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \data_r0_l__o_ok$next 1'0
     end
     sync init
       update \data_r0_l__o 64'0000000000000000000000000000000000000000000000000000000000000000
       update \data_r0_l__o_ok 1'0
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \data_r0_l__o \data_r0_l__o$next
       update \data_r0_l__o_ok \data_r0_l__o_ok$next
   end
@@ -51333,14 +51052,14 @@ module \alu0
         assign { \data_r1_l__cr_a_ok$next \data_r1_l__cr_a$next } { \cr_a_ok \alu_alu0_cr_a }
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \data_r1_l__cr_a_ok$next 1'0
     end
     sync init
       update \data_r1_l__cr_a 4'0000
       update \data_r1_l__cr_a_ok 1'0
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \data_r1_l__cr_a \data_r1_l__cr_a$next
       update \data_r1_l__cr_a_ok \data_r1_l__cr_a_ok$next
   end
@@ -51402,14 +51121,14 @@ module \alu0
         assign { \data_r2_l__xer_ca_ok$next \data_r2_l__xer_ca$next } { \xer_ca_ok \alu_alu0_xer_ca }
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \data_r2_l__xer_ca_ok$next 1'0
     end
     sync init
       update \data_r2_l__xer_ca 2'00
       update \data_r2_l__xer_ca_ok 1'0
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \data_r2_l__xer_ca \data_r2_l__xer_ca$next
       update \data_r2_l__xer_ca_ok \data_r2_l__xer_ca_ok$next
   end
@@ -51471,14 +51190,14 @@ module \alu0
         assign { \data_r3_l__xer_ov_ok$next \data_r3_l__xer_ov$next } { \xer_ov_ok \alu_alu0_xer_ov }
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \data_r3_l__xer_ov_ok$next 1'0
     end
     sync init
       update \data_r3_l__xer_ov 2'00
       update \data_r3_l__xer_ov_ok 1'0
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \data_r3_l__xer_ov \data_r3_l__xer_ov$next
       update \data_r3_l__xer_ov_ok \data_r3_l__xer_ov_ok$next
   end
@@ -51540,14 +51259,14 @@ module \alu0
         assign { \data_r4_l__xer_so_ok$next \data_r4_l__xer_so$next } { \xer_so_ok \alu_alu0_xer_so }
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \data_r4_l__xer_so_ok$next 1'0
     end
     sync init
       update \data_r4_l__xer_so 1'0
       update \data_r4_l__xer_so_ok 1'0
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \data_r4_l__xer_so \data_r4_l__xer_so$next
       update \data_r4_l__xer_so_ok \data_r4_l__xer_so_ok$next
   end
@@ -51740,7 +51459,7 @@ module \alu0
     end
     sync init
       update \src_r0 64'0000000000000000000000000000000000000000000000000000000000000000
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \src_r0 \src_r0$next
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
@@ -51772,7 +51491,7 @@ module \alu0
     end
     sync init
       update \src_r1 64'0000000000000000000000000000000000000000000000000000000000000000
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \src_r1 \src_r1$next
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
@@ -51804,7 +51523,7 @@ module \alu0
     end
     sync init
       update \src_r2 1'0
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \src_r2 \src_r2$next
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
@@ -51836,7 +51555,7 @@ module \alu0
     end
     sync init
       update \src_r3 2'00
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \src_r3 \src_r3$next
   end
   process $group_112
@@ -51861,13 +51580,13 @@ module \alu0
     assign \alui_l_r_alui$next \alui_l_r_alui
     assign \alui_l_r_alui$next $131
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \alui_l_r_alui$next 1'1
     end
     sync init
       update \alui_l_r_alui 1'1
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \alui_l_r_alui \alui_l_r_alui$next
   end
   process $group_114
@@ -51897,13 +51616,13 @@ module \alu0
     assign \alu_l_r_alu$next \alu_l_r_alu
     assign \alu_l_r_alu$next $133
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \alu_l_r_alu$next 1'1
     end
     sync init
       update \alu_l_r_alu 1'1
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \alu_l_r_alu \alu_l_r_alu$next
   end
   process $group_117
@@ -53189,10 +52908,10 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.alu_cr0.pipe"
 module \pipe$6
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153"
   wire width 1 input 2 \p_valid_i
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154"
@@ -53930,13 +53649,13 @@ module \pipe$6
         assign \r_busy$next 1'0
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \r_busy$next 1'0
     end
     sync init
       update \r_busy 1'0
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \r_busy \r_busy$next
   end
   process $group_28
@@ -53952,7 +53671,7 @@ module \pipe$6
     end
     sync init
       update \muxid$1 2'00
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \muxid$1 \muxid$1$next
   end
   process $group_29
@@ -53976,7 +53695,7 @@ module \pipe$6
       update \cr_op__insn$4 32'00000000000000000000000000000000
       update \cr_op__read_cr_whole$5 1'0
       update \cr_op__write_cr_whole$6 1'0
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \cr_op__insn_type$2 \cr_op__insn_type$2$next
       update \cr_op__fn_unit$3 \cr_op__fn_unit$3$next
       update \cr_op__insn$4 \cr_op__insn$4$next
@@ -53996,14 +53715,14 @@ module \pipe$6
         assign { \o_ok$next \o$next } { \o_ok$27 \o$26 }
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \o_ok$next 1'0
     end
     sync init
       update \o 64'0000000000000000000000000000000000000000000000000000000000000000
       update \o_ok 1'0
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \o \o$next
       update \o_ok \o_ok$next
   end
@@ -54020,14 +53739,14 @@ module \pipe$6
         assign { \full_cr_ok$next \full_cr$7$next } { \full_cr_ok$29 \full_cr$28 }
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \full_cr_ok$next 1'0
     end
     sync init
       update \full_cr$7 32'00000000000000000000000000000000
       update \full_cr_ok 1'0
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \full_cr$7 \full_cr$7$next
       update \full_cr_ok \full_cr_ok$next
   end
@@ -54044,14 +53763,14 @@ module \pipe$6
         assign { \cr_a_ok$next \cr_a$8$next } { \cr_a_ok$31 \cr_a$30 }
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \cr_a_ok$next 1'0
     end
     sync init
       update \cr_a$8 4'0000
       update \cr_a_ok 1'0
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \cr_a$8 \cr_a$8$next
       update \cr_a_ok \cr_a_ok$next
   end
@@ -54069,16 +53788,16 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.alu_cr0"
 module \alu_cr0
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 2 \o_ok
+  wire width 1 output 1 \o_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 3 \full_cr_ok
+  wire width 1 output 2 \full_cr_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 4 \cr_a_ok
+  wire width 1 output 3 \cr_a_ok
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 4 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
   wire width 1 output 5 \n_valid_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
@@ -54435,8 +54154,8 @@ module \alu_cr0
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \pipe_cr_a_ok
   cell \pipe$6 \pipe
-    connect \rst \rst
-    connect \clk \clk
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
     connect \p_valid_i \pipe_p_valid_i
     connect \p_ready_o \pipe_p_ready_o
     connect \muxid \pipe_muxid
@@ -54666,10 +54385,10 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.src_l"
 module \src_l$10
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
   wire width 6 input 2 \s_src
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
@@ -54720,13 +54439,13 @@ module \src_l$10
     assign \q_int$next \q_int
     assign \q_int$next $5
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \q_int$next 6'000000
     end
     sync init
       update \q_int 6'000000
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \q_int \q_int$next
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
@@ -54811,10 +54530,10 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.opc_l"
 module \opc_l$11
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
   wire width 1 input 2 \s_opc
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
@@ -54865,13 +54584,13 @@ module \opc_l$11
     assign \q_int$next \q_int
     assign \q_int$next $5
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \q_int$next 1'0
     end
     sync init
       update \q_int 1'0
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \q_int \q_int$next
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
@@ -54956,10 +54675,10 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.req_l"
 module \req_l$12
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
   wire width 3 output 2 \q_req
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
@@ -55010,13 +54729,13 @@ module \req_l$12
     assign \q_int$next \q_int
     assign \q_int$next $5
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \q_int$next 3'000
     end
     sync init
       update \q_int 3'000
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \q_int \q_int$next
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
@@ -55101,10 +54820,10 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.rst_l"
 module \rst_l$13
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
   wire width 1 input 2 \s_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
@@ -55153,13 +54872,13 @@ module \rst_l$13
     assign \q_int$next \q_int
     assign \q_int$next $5
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \q_int$next 1'0
     end
     sync init
       update \q_int 1'0
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \q_int \q_int$next
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
@@ -55246,10 +54965,10 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.rok_l"
 module \rok_l$14
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
   wire width 1 output 2 \q_rdok
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
@@ -55300,13 +55019,13 @@ module \rok_l$14
     assign \q_int$next \q_int
     assign \q_int$next $5
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \q_int$next 1'0
     end
     sync init
       update \q_int 1'0
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \q_int \q_int$next
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
@@ -55391,10 +55110,10 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.alui_l"
 module \alui_l$15
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
   wire width 1 output 2 \q_alui
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
@@ -55445,13 +55164,13 @@ module \alui_l$15
     assign \q_int$next \q_int
     assign \q_int$next $5
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \q_int$next 1'0
     end
     sync init
       update \q_int 1'0
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \q_int \q_int$next
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
@@ -55536,10 +55255,10 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.alu_l"
 module \alu_l$16
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
   wire width 1 output 2 \q_alu
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
@@ -55590,13 +55309,13 @@ module \alu_l$16
     assign \q_int$next \q_int
     assign \q_int$next $5
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \q_int$next 1'0
     end
     sync init
       update \q_int 1'0
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \q_int \q_int$next
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
@@ -55681,10 +55400,8 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.cr0"
 module \cr0
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
   attribute \enum_value_0000001 "OP_NOP"
@@ -55759,7 +55476,7 @@ module \cr0
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 7 input 2 \oper_i_alu_cr0__insn_type
+  wire width 7 input 1 \oper_i_alu_cr0__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -55773,51 +55490,53 @@ module \cr0
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 11 input 3 \oper_i_alu_cr0__fn_unit
+  wire width 11 input 2 \oper_i_alu_cr0__fn_unit
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 32 input 4 \oper_i_alu_cr0__insn
+  wire width 32 input 3 \oper_i_alu_cr0__insn
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 5 \oper_i_alu_cr0__read_cr_whole
+  wire width 1 input 4 \oper_i_alu_cr0__read_cr_whole
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 6 \oper_i_alu_cr0__write_cr_whole
+  wire width 1 input 5 \oper_i_alu_cr0__write_cr_whole
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
-  wire width 1 input 7 \cu_issue_i
+  wire width 1 input 6 \cu_issue_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:106"
-  wire width 1 output 8 \cu_busy_o
+  wire width 1 output 7 \cu_busy_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
-  wire width 6 input 9 \cu_rdmaskn_i
+  wire width 6 input 8 \cu_rdmaskn_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 6 output 10 \cu_rd__rel_o
+  wire width 6 output 9 \cu_rd__rel_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 6 input 11 \cu_rd__go_i
+  wire width 6 input 10 \cu_rd__go_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
-  wire width 64 input 12 \src1_i
+  wire width 64 input 11 \src1_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
-  wire width 64 input 13 \src2_i
+  wire width 64 input 12 \src2_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
-  wire width 32 input 14 \src3_i
+  wire width 32 input 13 \src3_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
-  wire width 4 input 15 \src4_i
+  wire width 4 input 14 \src4_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
-  wire width 4 input 16 \src5_i
+  wire width 4 input 15 \src5_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
-  wire width 4 input 17 \src6_i
+  wire width 4 input 16 \src6_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 18 \o_ok
+  wire width 1 output 17 \o_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 3 output 19 \cu_wr__rel_o
+  wire width 3 output 18 \cu_wr__rel_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 3 input 20 \cu_wr__go_i
+  wire width 3 input 19 \cu_wr__go_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
-  wire width 64 output 21 \dest1_o
+  wire width 64 output 20 \dest1_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 22 \full_cr_ok
+  wire width 1 output 21 \full_cr_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
-  wire width 32 output 23 \dest2_o
+  wire width 32 output 22 \dest2_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 24 \cr_a_ok
+  wire width 1 output 23 \cr_a_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
-  wire width 4 output 25 \dest3_o
+  wire width 4 output 24 \dest3_o
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 25 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
   wire width 1 \alu_cr0_n_valid_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
@@ -55940,11 +55659,11 @@ module \cr0
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154"
   wire width 1 \alu_cr0_p_ready_o
   cell \alu_cr0 \alu_cr0
-    connect \rst \rst
-    connect \clk \clk
+    connect \coresync_clk \coresync_clk
     connect \o_ok \o_ok
     connect \full_cr_ok \full_cr_ok
     connect \cr_a_ok \cr_a_ok
+    connect \coresync_rst \coresync_rst
     connect \n_valid_o \alu_cr0_n_valid_o
     connect \n_ready_i \alu_cr0_n_ready_i
     connect \o \alu_cr0_o
@@ -55975,8 +55694,8 @@ module \cr0
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
   wire width 6 \src_l_q_src
   cell \src_l$10 \src_l
-    connect \rst \rst
-    connect \clk \clk
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
     connect \s_src \src_l_s_src
     connect \r_src \src_l_r_src
     connect \q_src \src_l_q_src
@@ -55992,8 +55711,8 @@ module \cr0
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
   wire width 1 \opc_l_q_opc
   cell \opc_l$11 \opc_l
-    connect \rst \rst
-    connect \clk \clk
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
     connect \s_opc \opc_l_s_opc
     connect \r_opc \opc_l_r_opc
     connect \q_opc \opc_l_q_opc
@@ -56005,8 +55724,8 @@ module \cr0
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
   wire width 3 \req_l_r_req
   cell \req_l$12 \req_l
-    connect \rst \rst
-    connect \clk \clk
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
     connect \q_req \req_l_q_req
     connect \s_req \req_l_s_req
     connect \r_req \req_l_r_req
@@ -56016,8 +55735,8 @@ module \cr0
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
   wire width 1 \rst_l_r_rst
   cell \rst_l$13 \rst_l
-    connect \rst \rst
-    connect \clk \clk
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
     connect \s_rst \rst_l_s_rst
     connect \r_rst \rst_l_r_rst
   end
@@ -56030,8 +55749,8 @@ module \cr0
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
   wire width 1 \rok_l_r_rdok$next
   cell \rok_l$14 \rok_l
-    connect \rst \rst
-    connect \clk \clk
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
     connect \q_rdok \rok_l_q_rdok
     connect \s_rdok \rok_l_s_rdok
     connect \r_rdok \rok_l_r_rdok
@@ -56045,8 +55764,8 @@ module \cr0
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
   wire width 1 \alui_l_s_alui
   cell \alui_l$15 \alui_l
-    connect \rst \rst
-    connect \clk \clk
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
     connect \q_alui \alui_l_q_alui
     connect \r_alui \alui_l_r_alui
     connect \s_alui \alui_l_s_alui
@@ -56060,8 +55779,8 @@ module \cr0
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
   wire width 1 \alu_l_s_alu
   cell \alu_l$16 \alu_l
-    connect \rst \rst
-    connect \clk \clk
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
     connect \q_alu \alu_l_q_alu
     connect \r_alu \alu_l_r_alu
     connect \s_alu \alu_l_s_alu
@@ -56141,7 +55860,7 @@ module \cr0
     assign \all_rd_dly$next \all_rd
     sync init
       update \all_rd_dly 1'0
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \all_rd_dly \all_rd_dly$next
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:192"
@@ -56190,7 +55909,7 @@ module \cr0
     assign \alu_done_dly$next \alu_done
     sync init
       update \alu_done_dly 1'0
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \alu_done_dly \alu_done_dly$next
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:199"
@@ -56251,13 +55970,13 @@ module \cr0
     assign \prev_wr_go$next \prev_wr_go
     assign \prev_wr_go$next $21
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \prev_wr_go$next 3'000
     end
     sync init
       update \prev_wr_go 3'000
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \prev_wr_go \prev_wr_go$next
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107"
@@ -56596,13 +56315,13 @@ module \cr0
     assign \rok_l_r_rdok$next \rok_l_r_rdok
     assign \rok_l_r_rdok$next $65
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \rok_l_r_rdok$next 1'1
     end
     sync init
       update \rok_l_r_rdok 1'1
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \rok_l_r_rdok \rok_l_r_rdok$next
   end
   process $group_17
@@ -56619,52 +56338,52 @@ module \cr0
     assign \opc_l_s_opc$next \opc_l_s_opc
     assign \opc_l_s_opc$next \cu_issue_i
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \opc_l_s_opc$next 1'0
     end
     sync init
       update \opc_l_s_opc 1'0
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \opc_l_s_opc \opc_l_s_opc$next
   end
   process $group_20
     assign \opc_l_r_opc$next \opc_l_r_opc
     assign \opc_l_r_opc$next \req_done
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \opc_l_r_opc$next 1'1
     end
     sync init
       update \opc_l_r_opc 1'1
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \opc_l_r_opc \opc_l_r_opc$next
   end
   process $group_21
     assign \src_l_s_src$next \src_l_s_src
     assign \src_l_s_src$next { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i }
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \src_l_s_src$next 6'000000
     end
     sync init
       update \src_l_s_src 6'000000
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \src_l_s_src \src_l_s_src$next
   end
   process $group_22
     assign \src_l_r_src$next \src_l_r_src
     assign \src_l_r_src$next \reset_r
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \src_l_r_src$next 6'111111
     end
     sync init
       update \src_l_r_src 6'111111
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \src_l_r_src \src_l_r_src$next
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:255"
@@ -56855,7 +56574,7 @@ module \cr0
       update \oper_l__insn 32'00000000000000000000000000000000
       update \oper_l__read_cr_whole 1'0
       update \oper_l__write_cr_whole 1'0
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \oper_l__insn_type \oper_l__insn_type$next
       update \oper_l__fn_unit \oper_l__fn_unit$next
       update \oper_l__insn \oper_l__insn$next
@@ -56920,14 +56639,14 @@ module \cr0
         assign { \data_r0_l__o_ok$next \data_r0_l__o$next } { \o_ok \alu_cr0_o }
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \data_r0_l__o_ok$next 1'0
     end
     sync init
       update \data_r0_l__o 64'0000000000000000000000000000000000000000000000000000000000000000
       update \data_r0_l__o_ok 1'0
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \data_r0_l__o \data_r0_l__o$next
       update \data_r0_l__o_ok \data_r0_l__o_ok$next
   end
@@ -56989,14 +56708,14 @@ module \cr0
         assign { \data_r1_l__full_cr_ok$next \data_r1_l__full_cr$next } { \full_cr_ok \alu_cr0_full_cr }
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \data_r1_l__full_cr_ok$next 1'0
     end
     sync init
       update \data_r1_l__full_cr 32'00000000000000000000000000000000
       update \data_r1_l__full_cr_ok 1'0
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \data_r1_l__full_cr \data_r1_l__full_cr$next
       update \data_r1_l__full_cr_ok \data_r1_l__full_cr_ok$next
   end
@@ -57058,14 +56777,14 @@ module \cr0
         assign { \data_r2_l__cr_a_ok$next \data_r2_l__cr_a$next } { \cr_a_ok \alu_cr0_cr_a }
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \data_r2_l__cr_a_ok$next 1'0
     end
     sync init
       update \data_r2_l__cr_a 4'0000
       update \data_r2_l__cr_a_ok 1'0
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \data_r2_l__cr_a \data_r2_l__cr_a$next
       update \data_r2_l__cr_a_ok \data_r2_l__cr_a_ok$next
   end
@@ -57151,7 +56870,7 @@ module \cr0
     end
     sync init
       update \src_r0 64'0000000000000000000000000000000000000000000000000000000000000000
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \src_r0 \src_r0$next
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
@@ -57183,7 +56902,7 @@ module \cr0
     end
     sync init
       update \src_r1 64'0000000000000000000000000000000000000000000000000000000000000000
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \src_r1 \src_r1$next
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
@@ -57215,7 +56934,7 @@ module \cr0
     end
     sync init
       update \src_r2 32'00000000000000000000000000000000
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \src_r2 \src_r2$next
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
@@ -57247,7 +56966,7 @@ module \cr0
     end
     sync init
       update \src_r3 4'0000
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \src_r3 \src_r3$next
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
@@ -57279,7 +56998,7 @@ module \cr0
     end
     sync init
       update \src_r4 4'0000
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \src_r4 \src_r4$next
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
@@ -57311,7 +57030,7 @@ module \cr0
     end
     sync init
       update \src_r5 4'0000
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \src_r5 \src_r5$next
   end
   process $group_65
@@ -57336,13 +57055,13 @@ module \cr0
     assign \alui_l_r_alui$next \alui_l_r_alui
     assign \alui_l_r_alui$next $109
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \alui_l_r_alui$next 1'1
     end
     sync init
       update \alui_l_r_alui 1'1
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \alui_l_r_alui \alui_l_r_alui$next
   end
   process $group_67
@@ -57372,13 +57091,13 @@ module \cr0
     assign \alu_l_r_alu$next \alu_l_r_alu
     assign \alu_l_r_alu$next $111
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \alu_l_r_alu$next 1'1
     end
     sync init
       update \alu_l_r_alu 1'1
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \alu_l_r_alu \alu_l_r_alu$next
   end
   process $group_70
@@ -58420,10 +58139,10 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.alu_branch0.pipe"
 module \pipe$19
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153"
   wire width 1 input 2 \p_valid_i
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154"
@@ -59179,13 +58898,13 @@ module \pipe$19
         assign \r_busy$next 1'0
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \r_busy$next 1'0
     end
     sync init
       update \r_busy 1'0
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \r_busy \r_busy$next
   end
   process $group_31
@@ -59201,7 +58920,7 @@ module \pipe$19
     end
     sync init
       update \muxid$1 2'00
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \muxid$1 \muxid$1$next
   end
   process $group_32
@@ -59223,7 +58942,7 @@ module \pipe$19
         assign { \br_op__is_32bit$9$next \br_op__lk$8$next { \br_op__imm_data__imm_ok$7$next \br_op__imm_data__imm$6$next } \br_op__insn$5$next \br_op__fn_unit$4$next \br_op__insn_type$3$next \br_op__cia$2$next } { \br_op__is_32bit$34 \br_op__lk$33 { \br_op__imm_data__imm_ok$32 \br_op__imm_data__imm$31 } \br_op__insn$30 \br_op__fn_unit$29 \br_op__insn_type$28 \br_op__cia$27 }
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \br_op__imm_data__imm$6$next 64'0000000000000000000000000000000000000000000000000000000000000000
         assign \br_op__imm_data__imm_ok$7$next 1'0
@@ -59237,7 +58956,7 @@ module \pipe$19
       update \br_op__imm_data__imm_ok$7 1'0
       update \br_op__lk$8 1'0
       update \br_op__is_32bit$9 1'0
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \br_op__cia$2 \br_op__cia$2$next
       update \br_op__insn_type$3 \br_op__insn_type$3$next
       update \br_op__fn_unit$4 \br_op__fn_unit$4$next
@@ -59260,14 +58979,14 @@ module \pipe$19
         assign { \fast1_ok$next \fast1$10$next } { \fast1_ok$36 \fast1$35 }
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \fast1_ok$next 1'0
     end
     sync init
       update \fast1$10 64'0000000000000000000000000000000000000000000000000000000000000000
       update \fast1_ok 1'0
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \fast1$10 \fast1$10$next
       update \fast1_ok \fast1_ok$next
   end
@@ -59284,14 +59003,14 @@ module \pipe$19
         assign { \fast2_ok$next \fast2$11$next } { \fast2_ok$38 \fast2$37 }
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \fast2_ok$next 1'0
     end
     sync init
       update \fast2$11 64'0000000000000000000000000000000000000000000000000000000000000000
       update \fast2_ok 1'0
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \fast2$11 \fast2$11$next
       update \fast2_ok \fast2_ok$next
   end
@@ -59308,14 +59027,14 @@ module \pipe$19
         assign { \nia_ok$next \nia$next } { \nia_ok$40 \nia$39 }
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \nia_ok$next 1'0
     end
     sync init
       update \nia 64'0000000000000000000000000000000000000000000000000000000000000000
       update \nia_ok 1'0
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \nia \nia$next
       update \nia_ok \nia_ok$next
   end
@@ -59333,16 +59052,16 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.alu_branch0"
 module \alu_branch0
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 2 \fast1_ok
+  wire width 1 output 1 \fast1_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 3 \fast2_ok
+  wire width 1 output 2 \fast2_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 4 \nia_ok
+  wire width 1 output 3 \nia_ok
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 4 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
   wire width 1 output 5 \n_valid_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
@@ -59705,8 +59424,8 @@ module \alu_branch0
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \pipe_nia_ok
   cell \pipe$19 \pipe
-    connect \rst \rst
-    connect \clk \clk
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
     connect \p_valid_i \pipe_p_valid_i
     connect \p_ready_o \pipe_p_ready_o
     connect \muxid \pipe_muxid
@@ -59936,10 +59655,10 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.src_l"
 module \src_l$23
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
   wire width 3 input 2 \s_src
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
@@ -59990,13 +59709,13 @@ module \src_l$23
     assign \q_int$next \q_int
     assign \q_int$next $5
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \q_int$next 3'000
     end
     sync init
       update \q_int 3'000
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \q_int \q_int$next
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
@@ -60081,10 +59800,10 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.opc_l"
 module \opc_l$24
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
   wire width 1 input 2 \s_opc
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
@@ -60135,13 +59854,13 @@ module \opc_l$24
     assign \q_int$next \q_int
     assign \q_int$next $5
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \q_int$next 1'0
     end
     sync init
       update \q_int 1'0
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \q_int \q_int$next
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
@@ -60226,10 +59945,10 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.req_l"
 module \req_l$25
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
   wire width 3 output 2 \q_req
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
@@ -60280,13 +59999,13 @@ module \req_l$25
     assign \q_int$next \q_int
     assign \q_int$next $5
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \q_int$next 3'000
     end
     sync init
       update \q_int 3'000
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \q_int \q_int$next
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
@@ -60371,10 +60090,10 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.rst_l"
 module \rst_l$26
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
   wire width 1 input 2 \s_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
@@ -60423,13 +60142,13 @@ module \rst_l$26
     assign \q_int$next \q_int
     assign \q_int$next $5
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \q_int$next 1'0
     end
     sync init
       update \q_int 1'0
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \q_int \q_int$next
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
@@ -60516,10 +60235,10 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.rok_l"
 module \rok_l$27
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
   wire width 1 output 2 \q_rdok
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
@@ -60570,13 +60289,13 @@ module \rok_l$27
     assign \q_int$next \q_int
     assign \q_int$next $5
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \q_int$next 1'0
     end
     sync init
       update \q_int 1'0
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \q_int \q_int$next
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
@@ -60661,10 +60380,10 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.alui_l"
 module \alui_l$28
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
   wire width 1 output 2 \q_alui
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
@@ -60715,13 +60434,13 @@ module \alui_l$28
     assign \q_int$next \q_int
     assign \q_int$next $5
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \q_int$next 1'0
     end
     sync init
       update \q_int 1'0
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \q_int \q_int$next
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
@@ -60806,10 +60525,10 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.alu_l"
 module \alu_l$29
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
   wire width 1 output 2 \q_alu
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
@@ -60860,13 +60579,13 @@ module \alu_l$29
     assign \q_int$next \q_int
     assign \q_int$next $5
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \q_int$next 1'0
     end
     sync init
       update \q_int 1'0
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \q_int \q_int$next
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
@@ -60951,12 +60670,10 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.branch0"
 module \branch0
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 64 input 2 \oper_i_alu_branch0__cia
+  wire width 64 input 1 \oper_i_alu_branch0__cia
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
   attribute \enum_value_0000001 "OP_NOP"
@@ -61031,7 +60748,7 @@ module \branch0
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 7 input 3 \oper_i_alu_branch0__insn_type
+  wire width 7 input 2 \oper_i_alu_branch0__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -61045,49 +60762,51 @@ module \branch0
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 11 input 4 \oper_i_alu_branch0__fn_unit
+  wire width 11 input 3 \oper_i_alu_branch0__fn_unit
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 32 input 5 \oper_i_alu_branch0__insn
+  wire width 32 input 4 \oper_i_alu_branch0__insn
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 64 input 6 \oper_i_alu_branch0__imm_data__imm
+  wire width 64 input 5 \oper_i_alu_branch0__imm_data__imm
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 7 \oper_i_alu_branch0__imm_data__imm_ok
+  wire width 1 input 6 \oper_i_alu_branch0__imm_data__imm_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 8 \oper_i_alu_branch0__lk
+  wire width 1 input 7 \oper_i_alu_branch0__lk
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 9 \oper_i_alu_branch0__is_32bit
+  wire width 1 input 8 \oper_i_alu_branch0__is_32bit
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
-  wire width 1 input 10 \cu_issue_i
+  wire width 1 input 9 \cu_issue_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:106"
-  wire width 1 output 11 \cu_busy_o
+  wire width 1 output 10 \cu_busy_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
-  wire width 3 input 12 \cu_rdmaskn_i
+  wire width 3 input 11 \cu_rdmaskn_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 3 output 13 \cu_rd__rel_o
+  wire width 3 output 12 \cu_rd__rel_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 3 input 14 \cu_rd__go_i
+  wire width 3 input 13 \cu_rd__go_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
-  wire width 4 input 15 \src3_i
+  wire width 4 input 14 \src3_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
-  wire width 64 input 16 \src1_i
+  wire width 64 input 15 \src1_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
-  wire width 64 input 17 \src2_i
+  wire width 64 input 16 \src2_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 18 \fast1_ok
+  wire width 1 output 17 \fast1_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 3 output 19 \cu_wr__rel_o
+  wire width 3 output 18 \cu_wr__rel_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 3 input 20 \cu_wr__go_i
+  wire width 3 input 19 \cu_wr__go_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
-  wire width 64 output 21 \dest1_o
+  wire width 64 output 20 \dest1_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 22 \fast2_ok
+  wire width 1 output 21 \fast2_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
-  wire width 64 output 23 \dest2_o
+  wire width 64 output 22 \dest2_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 24 \nia_ok
+  wire width 1 output 23 \nia_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
-  wire width 64 output 25 \dest3_o
+  wire width 64 output 24 \dest3_o
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 25 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
   wire width 1 \alu_branch0_n_valid_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
@@ -61210,11 +60929,11 @@ module \branch0
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154"
   wire width 1 \alu_branch0_p_ready_o
   cell \alu_branch0 \alu_branch0
-    connect \rst \rst
-    connect \clk \clk
+    connect \coresync_clk \coresync_clk
     connect \fast1_ok \fast1_ok
     connect \fast2_ok \fast2_ok
     connect \nia_ok \nia_ok
+    connect \coresync_rst \coresync_rst
     connect \n_valid_o \alu_branch0_n_valid_o
     connect \n_ready_i \alu_branch0_n_ready_i
     connect \fast1 \alu_branch0_fast1
@@ -61245,8 +60964,8 @@ module \branch0
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
   wire width 3 \src_l_q_src
   cell \src_l$23 \src_l
-    connect \rst \rst
-    connect \clk \clk
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
     connect \s_src \src_l_s_src
     connect \r_src \src_l_r_src
     connect \q_src \src_l_q_src
@@ -61262,8 +60981,8 @@ module \branch0
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
   wire width 1 \opc_l_q_opc
   cell \opc_l$24 \opc_l
-    connect \rst \rst
-    connect \clk \clk
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
     connect \s_opc \opc_l_s_opc
     connect \r_opc \opc_l_r_opc
     connect \q_opc \opc_l_q_opc
@@ -61275,8 +60994,8 @@ module \branch0
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
   wire width 3 \req_l_r_req
   cell \req_l$25 \req_l
-    connect \rst \rst
-    connect \clk \clk
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
     connect \q_req \req_l_q_req
     connect \s_req \req_l_s_req
     connect \r_req \req_l_r_req
@@ -61286,8 +61005,8 @@ module \branch0
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
   wire width 1 \rst_l_r_rst
   cell \rst_l$26 \rst_l
-    connect \rst \rst
-    connect \clk \clk
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
     connect \s_rst \rst_l_s_rst
     connect \r_rst \rst_l_r_rst
   end
@@ -61300,8 +61019,8 @@ module \branch0
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
   wire width 1 \rok_l_r_rdok$next
   cell \rok_l$27 \rok_l
-    connect \rst \rst
-    connect \clk \clk
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
     connect \q_rdok \rok_l_q_rdok
     connect \s_rdok \rok_l_s_rdok
     connect \r_rdok \rok_l_r_rdok
@@ -61315,8 +61034,8 @@ module \branch0
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
   wire width 1 \alui_l_s_alui
   cell \alui_l$28 \alui_l
-    connect \rst \rst
-    connect \clk \clk
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
     connect \q_alui \alui_l_q_alui
     connect \r_alui \alui_l_r_alui
     connect \s_alui \alui_l_s_alui
@@ -61330,8 +61049,8 @@ module \branch0
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
   wire width 1 \alu_l_s_alu
   cell \alu_l$29 \alu_l
-    connect \rst \rst
-    connect \clk \clk
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
     connect \q_alu \alu_l_q_alu
     connect \r_alu \alu_l_r_alu
     connect \s_alu \alu_l_s_alu
@@ -61411,7 +61130,7 @@ module \branch0
     assign \all_rd_dly$next \all_rd
     sync init
       update \all_rd_dly 1'0
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \all_rd_dly \all_rd_dly$next
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:192"
@@ -61460,7 +61179,7 @@ module \branch0
     assign \alu_done_dly$next \alu_done
     sync init
       update \alu_done_dly 1'0
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \alu_done_dly \alu_done_dly$next
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:199"
@@ -61521,13 +61240,13 @@ module \branch0
     assign \prev_wr_go$next \prev_wr_go
     assign \prev_wr_go$next $21
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \prev_wr_go$next 3'000
     end
     sync init
       update \prev_wr_go 3'000
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \prev_wr_go \prev_wr_go$next
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107"
@@ -61866,13 +61585,13 @@ module \branch0
     assign \rok_l_r_rdok$next \rok_l_r_rdok
     assign \rok_l_r_rdok$next $65
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \rok_l_r_rdok$next 1'1
     end
     sync init
       update \rok_l_r_rdok 1'1
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \rok_l_r_rdok \rok_l_r_rdok$next
   end
   process $group_17
@@ -61889,52 +61608,52 @@ module \branch0
     assign \opc_l_s_opc$next \opc_l_s_opc
     assign \opc_l_s_opc$next \cu_issue_i
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \opc_l_s_opc$next 1'0
     end
     sync init
       update \opc_l_s_opc 1'0
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \opc_l_s_opc \opc_l_s_opc$next
   end
   process $group_20
     assign \opc_l_r_opc$next \opc_l_r_opc
     assign \opc_l_r_opc$next \req_done
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \opc_l_r_opc$next 1'1
     end
     sync init
       update \opc_l_r_opc 1'1
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \opc_l_r_opc \opc_l_r_opc$next
   end
   process $group_21
     assign \src_l_s_src$next \src_l_s_src
     assign \src_l_s_src$next { \cu_issue_i \cu_issue_i \cu_issue_i }
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \src_l_s_src$next 3'000
     end
     sync init
       update \src_l_s_src 3'000
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \src_l_s_src \src_l_s_src$next
   end
   process $group_22
     assign \src_l_r_src$next \src_l_r_src
     assign \src_l_r_src$next \reset_r
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \src_l_r_src$next 3'111
     end
     sync init
       update \src_l_r_src 3'111
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \src_l_r_src \src_l_r_src$next
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:255"
@@ -62144,7 +61863,7 @@ module \branch0
         assign { \oper_l__is_32bit$next \oper_l__lk$next { \oper_l__imm_data__imm_ok$next \oper_l__imm_data__imm$next } \oper_l__insn$next \oper_l__fn_unit$next \oper_l__insn_type$next \oper_l__cia$next } { \oper_i_alu_branch0__is_32bit \oper_i_alu_branch0__lk { \oper_i_alu_branch0__imm_data__imm_ok \oper_i_alu_branch0__imm_data__imm } \oper_i_alu_branch0__insn \oper_i_alu_branch0__fn_unit \oper_i_alu_branch0__insn_type \oper_i_alu_branch0__cia }
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \oper_l__imm_data__imm$next 64'0000000000000000000000000000000000000000000000000000000000000000
         assign \oper_l__imm_data__imm_ok$next 1'0
@@ -62158,7 +61877,7 @@ module \branch0
       update \oper_l__imm_data__imm_ok 1'0
       update \oper_l__lk 1'0
       update \oper_l__is_32bit 1'0
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \oper_l__cia \oper_l__cia$next
       update \oper_l__insn_type \oper_l__insn_type$next
       update \oper_l__fn_unit \oper_l__fn_unit$next
@@ -62226,14 +61945,14 @@ module \branch0
         assign { \data_r0_l__fast1_ok$next \data_r0_l__fast1$next } { \fast1_ok \alu_branch0_fast1 }
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \data_r0_l__fast1_ok$next 1'0
     end
     sync init
       update \data_r0_l__fast1 64'0000000000000000000000000000000000000000000000000000000000000000
       update \data_r0_l__fast1_ok 1'0
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \data_r0_l__fast1 \data_r0_l__fast1$next
       update \data_r0_l__fast1_ok \data_r0_l__fast1_ok$next
   end
@@ -62295,14 +62014,14 @@ module \branch0
         assign { \data_r1_l__fast2_ok$next \data_r1_l__fast2$next } { \fast2_ok \alu_branch0_fast2 }
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \data_r1_l__fast2_ok$next 1'0
     end
     sync init
       update \data_r1_l__fast2 64'0000000000000000000000000000000000000000000000000000000000000000
       update \data_r1_l__fast2_ok 1'0
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \data_r1_l__fast2 \data_r1_l__fast2$next
       update \data_r1_l__fast2_ok \data_r1_l__fast2_ok$next
   end
@@ -62364,14 +62083,14 @@ module \branch0
         assign { \data_r2_l__nia_ok$next \data_r2_l__nia$next } { \nia_ok \alu_branch0_nia }
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \data_r2_l__nia_ok$next 1'0
     end
     sync init
       update \data_r2_l__nia 64'0000000000000000000000000000000000000000000000000000000000000000
       update \data_r2_l__nia_ok 1'0
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \data_r2_l__nia \data_r2_l__nia$next
       update \data_r2_l__nia_ok \data_r2_l__nia_ok$next
   end
@@ -62494,7 +62213,7 @@ module \branch0
     end
     sync init
       update \src_r0 64'0000000000000000000000000000000000000000000000000000000000000000
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \src_r0 \src_r0$next
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
@@ -62526,7 +62245,7 @@ module \branch0
     end
     sync init
       update \src_r1 64'0000000000000000000000000000000000000000000000000000000000000000
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \src_r1 \src_r1$next
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
@@ -62558,7 +62277,7 @@ module \branch0
     end
     sync init
       update \src_r2 4'0000
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \src_r2 \src_r2$next
   end
   process $group_70
@@ -62583,13 +62302,13 @@ module \branch0
     assign \alui_l_r_alui$next \alui_l_r_alui
     assign \alui_l_r_alui$next $107
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \alui_l_r_alui$next 1'1
     end
     sync init
       update \alui_l_r_alui 1'1
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \alui_l_r_alui \alui_l_r_alui$next
   end
   process $group_72
@@ -62619,13 +62338,13 @@ module \branch0
     assign \alu_l_r_alu$next \alu_l_r_alu
     assign \alu_l_r_alu$next $109
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \alu_l_r_alu$next 1'1
     end
     sync init
       update \alu_l_r_alu 1'1
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \alu_l_r_alu \alu_l_r_alu$next
   end
   process $group_75
@@ -64130,10 +63849,10 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.alu_trap0.pipe"
 module \pipe$32
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153"
   wire width 1 input 2 \p_valid_i
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154"
@@ -64947,13 +64666,13 @@ module \pipe$32
         assign \r_busy$next 1'0
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \r_busy$next 1'0
     end
     sync init
       update \r_busy 1'0
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \r_busy \r_busy$next
   end
   process $group_36
@@ -64969,7 +64688,7 @@ module \pipe$32
     end
     sync init
       update \muxid$1 2'00
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \muxid$1 \muxid$1$next
   end
   process $group_37
@@ -64999,7 +64718,7 @@ module \pipe$32
       update \trap_op__is_32bit$7 1'0
       update \trap_op__traptype$8 5'00000
       update \trap_op__trapaddr$9 13'0000000000000
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \trap_op__insn_type$2 \trap_op__insn_type$2$next
       update \trap_op__fn_unit$3 \trap_op__fn_unit$3$next
       update \trap_op__insn$4 \trap_op__insn$4$next
@@ -65022,14 +64741,14 @@ module \pipe$32
         assign { \o_ok$next \o$next } { \o_ok$36 \o$35 }
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \o_ok$next 1'0
     end
     sync init
       update \o 64'0000000000000000000000000000000000000000000000000000000000000000
       update \o_ok 1'0
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \o \o$next
       update \o_ok \o_ok$next
   end
@@ -65046,14 +64765,14 @@ module \pipe$32
         assign { \fast1_ok$next \fast1$10$next } { \fast1_ok$38 \fast1$37 }
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \fast1_ok$next 1'0
     end
     sync init
       update \fast1$10 64'0000000000000000000000000000000000000000000000000000000000000000
       update \fast1_ok 1'0
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \fast1$10 \fast1$10$next
       update \fast1_ok \fast1_ok$next
   end
@@ -65070,14 +64789,14 @@ module \pipe$32
         assign { \fast2_ok$next \fast2$11$next } { \fast2_ok$40 \fast2$39 }
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \fast2_ok$next 1'0
     end
     sync init
       update \fast2$11 64'0000000000000000000000000000000000000000000000000000000000000000
       update \fast2_ok 1'0
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \fast2$11 \fast2$11$next
       update \fast2_ok \fast2_ok$next
   end
@@ -65094,14 +64813,14 @@ module \pipe$32
         assign { \nia_ok$next \nia$next } { \nia_ok$42 \nia$41 }
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \nia_ok$next 1'0
     end
     sync init
       update \nia 64'0000000000000000000000000000000000000000000000000000000000000000
       update \nia_ok 1'0
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \nia \nia$next
       update \nia_ok \nia_ok$next
   end
@@ -65118,14 +64837,14 @@ module \pipe$32
         assign { \msr_ok$next \msr$next } { \msr_ok$44 \msr$43 }
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \msr_ok$next 1'0
     end
     sync init
       update \msr 64'0000000000000000000000000000000000000000000000000000000000000000
       update \msr_ok 1'0
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \msr \msr$next
       update \msr_ok \msr_ok$next
   end
@@ -65143,20 +64862,20 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.alu_trap0"
 module \alu_trap0
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 2 \o_ok
+  wire width 1 output 1 \o_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 3 \fast1_ok
+  wire width 1 output 2 \fast1_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 4 \fast2_ok
+  wire width 1 output 3 \fast2_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 5 \nia_ok
+  wire width 1 output 4 \nia_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 6 \msr_ok
+  wire width 1 output 5 \msr_ok
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 6 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
   wire width 1 output 7 \n_valid_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
@@ -65535,8 +65254,8 @@ module \alu_trap0
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \pipe_msr_ok
   cell \pipe$32 \pipe
-    connect \rst \rst
-    connect \clk \clk
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
     connect \p_valid_i \pipe_p_valid_i
     connect \p_ready_o \pipe_p_ready_o
     connect \muxid \pipe_muxid
@@ -65788,10 +65507,10 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.src_l"
 module \src_l$36
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
   wire width 4 input 2 \s_src
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
@@ -65842,13 +65561,13 @@ module \src_l$36
     assign \q_int$next \q_int
     assign \q_int$next $5
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \q_int$next 4'0000
     end
     sync init
       update \q_int 4'0000
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \q_int \q_int$next
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
@@ -65933,10 +65652,10 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.opc_l"
 module \opc_l$37
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
   wire width 1 input 2 \s_opc
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
@@ -65987,13 +65706,13 @@ module \opc_l$37
     assign \q_int$next \q_int
     assign \q_int$next $5
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \q_int$next 1'0
     end
     sync init
       update \q_int 1'0
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \q_int \q_int$next
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
@@ -66078,10 +65797,10 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.req_l"
 module \req_l$38
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
   wire width 5 output 2 \q_req
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
@@ -66132,13 +65851,13 @@ module \req_l$38
     assign \q_int$next \q_int
     assign \q_int$next $5
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \q_int$next 5'00000
     end
     sync init
       update \q_int 5'00000
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \q_int \q_int$next
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
@@ -66223,10 +65942,10 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.rst_l"
 module \rst_l$39
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
   wire width 1 input 2 \s_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
@@ -66275,13 +65994,13 @@ module \rst_l$39
     assign \q_int$next \q_int
     assign \q_int$next $5
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \q_int$next 1'0
     end
     sync init
       update \q_int 1'0
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \q_int \q_int$next
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
@@ -66368,10 +66087,10 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.rok_l"
 module \rok_l$40
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
   wire width 1 output 2 \q_rdok
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
@@ -66422,13 +66141,13 @@ module \rok_l$40
     assign \q_int$next \q_int
     assign \q_int$next $5
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \q_int$next 1'0
     end
     sync init
       update \q_int 1'0
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \q_int \q_int$next
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
@@ -66513,10 +66232,10 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.alui_l"
 module \alui_l$41
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
   wire width 1 output 2 \q_alui
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
@@ -66567,13 +66286,13 @@ module \alui_l$41
     assign \q_int$next \q_int
     assign \q_int$next $5
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \q_int$next 1'0
     end
     sync init
       update \q_int 1'0
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \q_int \q_int$next
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
@@ -66658,10 +66377,10 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.alu_l"
 module \alu_l$42
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
   wire width 1 output 2 \q_alu
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
@@ -66712,13 +66431,13 @@ module \alu_l$42
     assign \q_int$next \q_int
     assign \q_int$next $5
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \q_int$next 1'0
     end
     sync init
       update \q_int 1'0
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \q_int \q_int$next
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
@@ -66803,10 +66522,8 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.trap0"
 module \trap0
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
   attribute \enum_value_0000001 "OP_NOP"
@@ -66881,7 +66598,7 @@ module \trap0
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 7 input 2 \oper_i_alu_trap0__insn_type
+  wire width 7 input 1 \oper_i_alu_trap0__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -66895,61 +66612,63 @@ module \trap0
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 11 input 3 \oper_i_alu_trap0__fn_unit
+  wire width 11 input 2 \oper_i_alu_trap0__fn_unit
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 32 input 4 \oper_i_alu_trap0__insn
+  wire width 32 input 3 \oper_i_alu_trap0__insn
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 64 input 5 \oper_i_alu_trap0__msr
+  wire width 64 input 4 \oper_i_alu_trap0__msr
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 64 input 6 \oper_i_alu_trap0__cia
+  wire width 64 input 5 \oper_i_alu_trap0__cia
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 7 \oper_i_alu_trap0__is_32bit
+  wire width 1 input 6 \oper_i_alu_trap0__is_32bit
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 5 input 8 \oper_i_alu_trap0__traptype
+  wire width 5 input 7 \oper_i_alu_trap0__traptype
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 13 input 9 \oper_i_alu_trap0__trapaddr
+  wire width 13 input 8 \oper_i_alu_trap0__trapaddr
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
-  wire width 1 input 10 \cu_issue_i
+  wire width 1 input 9 \cu_issue_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:106"
-  wire width 1 output 11 \cu_busy_o
+  wire width 1 output 10 \cu_busy_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
-  wire width 4 input 12 \cu_rdmaskn_i
+  wire width 4 input 11 \cu_rdmaskn_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 4 output 13 \cu_rd__rel_o
+  wire width 4 output 12 \cu_rd__rel_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 4 input 14 \cu_rd__go_i
+  wire width 4 input 13 \cu_rd__go_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
-  wire width 64 input 15 \src1_i
+  wire width 64 input 14 \src1_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
-  wire width 64 input 16 \src2_i
+  wire width 64 input 15 \src2_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
-  wire width 64 input 17 \src3_i
+  wire width 64 input 16 \src3_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
-  wire width 64 input 18 \src4_i
+  wire width 64 input 17 \src4_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 19 \o_ok
+  wire width 1 output 18 \o_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 5 output 20 \cu_wr__rel_o
+  wire width 5 output 19 \cu_wr__rel_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 5 input 21 \cu_wr__go_i
+  wire width 5 input 20 \cu_wr__go_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
-  wire width 64 output 22 \dest1_o
+  wire width 64 output 21 \dest1_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 23 \fast1_ok
+  wire width 1 output 22 \fast1_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
-  wire width 64 output 24 \dest2_o
+  wire width 64 output 23 \dest2_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 25 \fast2_ok
+  wire width 1 output 24 \fast2_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
-  wire width 64 output 26 \dest3_o
+  wire width 64 output 25 \dest3_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 27 \nia_ok
+  wire width 1 output 26 \nia_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
-  wire width 64 output 28 \dest4_o
+  wire width 64 output 27 \dest4_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 29 \msr_ok
+  wire width 1 output 28 \msr_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
-  wire width 64 output 30 \dest5_o
+  wire width 64 output 29 \dest5_o
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 30 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
   wire width 1 \alu_trap0_n_valid_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
@@ -67078,13 +66797,13 @@ module \trap0
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154"
   wire width 1 \alu_trap0_p_ready_o
   cell \alu_trap0 \alu_trap0
-    connect \rst \rst
-    connect \clk \clk
+    connect \coresync_clk \coresync_clk
     connect \o_ok \o_ok
     connect \fast1_ok \fast1_ok
     connect \fast2_ok \fast2_ok
     connect \nia_ok \nia_ok
     connect \msr_ok \msr_ok
+    connect \coresync_rst \coresync_rst
     connect \n_valid_o \alu_trap0_n_valid_o
     connect \n_ready_i \alu_trap0_n_ready_i
     connect \o \alu_trap0_o
@@ -67118,8 +66837,8 @@ module \trap0
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
   wire width 4 \src_l_q_src
   cell \src_l$36 \src_l
-    connect \rst \rst
-    connect \clk \clk
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
     connect \s_src \src_l_s_src
     connect \r_src \src_l_r_src
     connect \q_src \src_l_q_src
@@ -67135,8 +66854,8 @@ module \trap0
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
   wire width 1 \opc_l_q_opc
   cell \opc_l$37 \opc_l
-    connect \rst \rst
-    connect \clk \clk
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
     connect \s_opc \opc_l_s_opc
     connect \r_opc \opc_l_r_opc
     connect \q_opc \opc_l_q_opc
@@ -67148,8 +66867,8 @@ module \trap0
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
   wire width 5 \req_l_r_req
   cell \req_l$38 \req_l
-    connect \rst \rst
-    connect \clk \clk
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
     connect \q_req \req_l_q_req
     connect \s_req \req_l_s_req
     connect \r_req \req_l_r_req
@@ -67159,8 +66878,8 @@ module \trap0
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
   wire width 1 \rst_l_r_rst
   cell \rst_l$39 \rst_l
-    connect \rst \rst
-    connect \clk \clk
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
     connect \s_rst \rst_l_s_rst
     connect \r_rst \rst_l_r_rst
   end
@@ -67173,8 +66892,8 @@ module \trap0
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
   wire width 1 \rok_l_r_rdok$next
   cell \rok_l$40 \rok_l
-    connect \rst \rst
-    connect \clk \clk
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
     connect \q_rdok \rok_l_q_rdok
     connect \s_rdok \rok_l_s_rdok
     connect \r_rdok \rok_l_r_rdok
@@ -67188,8 +66907,8 @@ module \trap0
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
   wire width 1 \alui_l_s_alui
   cell \alui_l$41 \alui_l
-    connect \rst \rst
-    connect \clk \clk
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
     connect \q_alui \alui_l_q_alui
     connect \r_alui \alui_l_r_alui
     connect \s_alui \alui_l_s_alui
@@ -67203,8 +66922,8 @@ module \trap0
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
   wire width 1 \alu_l_s_alu
   cell \alu_l$42 \alu_l
-    connect \rst \rst
-    connect \clk \clk
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
     connect \q_alu \alu_l_q_alu
     connect \r_alu \alu_l_r_alu
     connect \s_alu \alu_l_s_alu
@@ -67284,7 +67003,7 @@ module \trap0
     assign \all_rd_dly$next \all_rd
     sync init
       update \all_rd_dly 1'0
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \all_rd_dly \all_rd_dly$next
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:192"
@@ -67333,7 +67052,7 @@ module \trap0
     assign \alu_done_dly$next \alu_done
     sync init
       update \alu_done_dly 1'0
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \alu_done_dly \alu_done_dly$next
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:199"
@@ -67394,13 +67113,13 @@ module \trap0
     assign \prev_wr_go$next \prev_wr_go
     assign \prev_wr_go$next $21
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \prev_wr_go$next 5'00000
     end
     sync init
       update \prev_wr_go 5'00000
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \prev_wr_go \prev_wr_go$next
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107"
@@ -67739,13 +67458,13 @@ module \trap0
     assign \rok_l_r_rdok$next \rok_l_r_rdok
     assign \rok_l_r_rdok$next $65
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \rok_l_r_rdok$next 1'1
     end
     sync init
       update \rok_l_r_rdok 1'1
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \rok_l_r_rdok \rok_l_r_rdok$next
   end
   process $group_17
@@ -67762,52 +67481,52 @@ module \trap0
     assign \opc_l_s_opc$next \opc_l_s_opc
     assign \opc_l_s_opc$next \cu_issue_i
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \opc_l_s_opc$next 1'0
     end
     sync init
       update \opc_l_s_opc 1'0
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \opc_l_s_opc \opc_l_s_opc$next
   end
   process $group_20
     assign \opc_l_r_opc$next \opc_l_r_opc
     assign \opc_l_r_opc$next \req_done
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \opc_l_r_opc$next 1'1
     end
     sync init
       update \opc_l_r_opc 1'1
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \opc_l_r_opc \opc_l_r_opc$next
   end
   process $group_21
     assign \src_l_s_src$next \src_l_s_src
     assign \src_l_s_src$next { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i }
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \src_l_s_src$next 4'0000
     end
     sync init
       update \src_l_s_src 4'0000
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \src_l_s_src \src_l_s_src$next
   end
   process $group_22
     assign \src_l_r_src$next \src_l_r_src
     assign \src_l_r_src$next \reset_r
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \src_l_r_src$next 4'1111
     end
     sync init
       update \src_l_r_src 4'1111
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \src_l_r_src \src_l_r_src$next
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:255"
@@ -68025,7 +67744,7 @@ module \trap0
       update \oper_l__is_32bit 1'0
       update \oper_l__traptype 5'00000
       update \oper_l__trapaddr 13'0000000000000
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \oper_l__insn_type \oper_l__insn_type$next
       update \oper_l__fn_unit \oper_l__fn_unit$next
       update \oper_l__insn \oper_l__insn$next
@@ -68093,14 +67812,14 @@ module \trap0
         assign { \data_r0_l__o_ok$next \data_r0_l__o$next } { \o_ok \alu_trap0_o }
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \data_r0_l__o_ok$next 1'0
     end
     sync init
       update \data_r0_l__o 64'0000000000000000000000000000000000000000000000000000000000000000
       update \data_r0_l__o_ok 1'0
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \data_r0_l__o \data_r0_l__o$next
       update \data_r0_l__o_ok \data_r0_l__o_ok$next
   end
@@ -68162,14 +67881,14 @@ module \trap0
         assign { \data_r1_l__fast1_ok$next \data_r1_l__fast1$next } { \fast1_ok \alu_trap0_fast1 }
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \data_r1_l__fast1_ok$next 1'0
     end
     sync init
       update \data_r1_l__fast1 64'0000000000000000000000000000000000000000000000000000000000000000
       update \data_r1_l__fast1_ok 1'0
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \data_r1_l__fast1 \data_r1_l__fast1$next
       update \data_r1_l__fast1_ok \data_r1_l__fast1_ok$next
   end
@@ -68231,14 +67950,14 @@ module \trap0
         assign { \data_r2_l__fast2_ok$next \data_r2_l__fast2$next } { \fast2_ok \alu_trap0_fast2 }
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \data_r2_l__fast2_ok$next 1'0
     end
     sync init
       update \data_r2_l__fast2 64'0000000000000000000000000000000000000000000000000000000000000000
       update \data_r2_l__fast2_ok 1'0
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \data_r2_l__fast2 \data_r2_l__fast2$next
       update \data_r2_l__fast2_ok \data_r2_l__fast2_ok$next
   end
@@ -68300,14 +68019,14 @@ module \trap0
         assign { \data_r3_l__nia_ok$next \data_r3_l__nia$next } { \nia_ok \alu_trap0_nia }
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \data_r3_l__nia_ok$next 1'0
     end
     sync init
       update \data_r3_l__nia 64'0000000000000000000000000000000000000000000000000000000000000000
       update \data_r3_l__nia_ok 1'0
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \data_r3_l__nia \data_r3_l__nia$next
       update \data_r3_l__nia_ok \data_r3_l__nia_ok$next
   end
@@ -68369,14 +68088,14 @@ module \trap0
         assign { \data_r4_l__msr_ok$next \data_r4_l__msr$next } { \msr_ok \alu_trap0_msr }
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \data_r4_l__msr_ok$next 1'0
     end
     sync init
       update \data_r4_l__msr 64'0000000000000000000000000000000000000000000000000000000000000000
       update \data_r4_l__msr_ok 1'0
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \data_r4_l__msr \data_r4_l__msr$next
       update \data_r4_l__msr_ok \data_r4_l__msr_ok$next
   end
@@ -68491,7 +68210,7 @@ module \trap0
     end
     sync init
       update \src_r0 64'0000000000000000000000000000000000000000000000000000000000000000
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \src_r0 \src_r0$next
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
@@ -68523,7 +68242,7 @@ module \trap0
     end
     sync init
       update \src_r1 64'0000000000000000000000000000000000000000000000000000000000000000
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \src_r1 \src_r1$next
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
@@ -68555,7 +68274,7 @@ module \trap0
     end
     sync init
       update \src_r2 64'0000000000000000000000000000000000000000000000000000000000000000
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \src_r2 \src_r2$next
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
@@ -68587,7 +68306,7 @@ module \trap0
     end
     sync init
       update \src_r3 64'0000000000000000000000000000000000000000000000000000000000000000
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \src_r3 \src_r3$next
   end
   process $group_78
@@ -68612,13 +68331,13 @@ module \trap0
     assign \alui_l_r_alui$next \alui_l_r_alui
     assign \alui_l_r_alui$next $121
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \alui_l_r_alui$next 1'1
     end
     sync init
       update \alui_l_r_alui 1'1
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \alui_l_r_alui \alui_l_r_alui$next
   end
   process $group_80
@@ -68648,13 +68367,13 @@ module \trap0
     assign \alu_l_r_alu$next \alu_l_r_alu
     assign \alu_l_r_alu$next $123
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \alu_l_r_alu$next 1'1
     end
     sync init
       update \alu_l_r_alu 1'1
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \alu_l_r_alu \alu_l_r_alu$next
   end
   process $group_83
@@ -77702,10 +77421,10 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_logical0.pipe"
 module \pipe$45
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153"
   wire width 1 input 2 \p_valid_i
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154"
@@ -79343,13 +79062,13 @@ module \pipe$45
         assign \r_busy$next 1'0
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \r_busy$next 1'0
     end
     sync init
       update \r_busy 1'0
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \r_busy \r_busy$next
   end
   process $group_96
@@ -79365,7 +79084,7 @@ module \pipe$45
     end
     sync init
       update \muxid$1 2'00
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \muxid$1 \muxid$1$next
   end
   process $group_97
@@ -79397,7 +79116,7 @@ module \pipe$45
         assign { \logical_op__insn$19$next \logical_op__data_len$18$next \logical_op__is_signed$17$next \logical_op__is_32bit$16$next \logical_op__output_carry$15$next \logical_op__write_cr0$14$next \logical_op__invert_out$13$next \logical_op__input_carry$12$next \logical_op__zero_a$11$next \logical_op__invert_a$10$next { \logical_op__oe__oe_ok$9$next \logical_op__oe__oe$8$next } { \logical_op__rc__rc_ok$7$next \logical_op__rc__rc$6$next } { \logical_op__imm_data__imm_ok$5$next \logical_op__imm_data__imm$4$next } \logical_op__fn_unit$3$next \logical_op__insn_type$2$next } { \logical_op__insn$110 \logical_op__data_len$109 \logical_op__is_signed$108 \logical_op__is_32bit$107 \logical_op__output_carry$106 \logical_op__write_cr0$105 \logical_op__invert_out$104 \logical_op__input_carry$103 \logical_op__zero_a$102 \logical_op__invert_a$101 { \logical_op__oe__oe_ok$100 \logical_op__oe__oe$99 } { \logical_op__rc__rc_ok$98 \logical_op__rc__rc$97 } { \logical_op__imm_data__imm_ok$96 \logical_op__imm_data__imm$95 } \logical_op__fn_unit$94 \logical_op__insn_type$93 }
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \logical_op__imm_data__imm$4$next 64'0000000000000000000000000000000000000000000000000000000000000000
         assign \logical_op__imm_data__imm_ok$5$next 1'0
@@ -79425,7 +79144,7 @@ module \pipe$45
       update \logical_op__is_signed$17 1'0
       update \logical_op__data_len$18 4'0000
       update \logical_op__insn$19 32'00000000000000000000000000000000
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \logical_op__insn_type$2 \logical_op__insn_type$2$next
       update \logical_op__fn_unit$3 \logical_op__fn_unit$3$next
       update \logical_op__imm_data__imm$4 \logical_op__imm_data__imm$4$next
@@ -79458,14 +79177,14 @@ module \pipe$45
         assign { \o_ok$next \o$next } { \o_ok$112 \o$111 }
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \o_ok$next 1'0
     end
     sync init
       update \o 64'0000000000000000000000000000000000000000000000000000000000000000
       update \o_ok 1'0
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \o \o$next
       update \o_ok \o_ok$next
   end
@@ -79482,14 +79201,14 @@ module \pipe$45
         assign { \cr_a_ok$next \cr_a$next } { \cr_a_ok$114 \cr_a$113 }
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \cr_a_ok$next 1'0
     end
     sync init
       update \cr_a 4'0000
       update \cr_a_ok 1'0
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \cr_a \cr_a$next
       update \cr_a_ok \cr_a_ok$next
   end
@@ -79506,14 +79225,14 @@ module \pipe$45
         assign { \xer_ca_ok$next \xer_ca$next } { \xer_ca_ok$116 \xer_ca$115 }
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \xer_ca_ok$next 1'0
     end
     sync init
       update \xer_ca 2'00
       update \xer_ca_ok 1'0
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \xer_ca \xer_ca$next
       update \xer_ca_ok \xer_ca_ok$next
   end
@@ -79535,16 +79254,16 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_logical0"
 module \alu_logical0
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 2 \o_ok
+  wire width 1 output 1 \o_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 3 \cr_a_ok
+  wire width 1 output 2 \cr_a_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 4 \xer_ca_ok
+  wire width 1 output 3 \xer_ca_ok
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 4 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
   wire width 1 output 5 \n_valid_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
@@ -79975,8 +79694,8 @@ module \alu_logical0
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \pipe_xer_ca_ok
   cell \pipe$45 \pipe
-    connect \rst \rst
-    connect \clk \clk
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
     connect \p_valid_i \pipe_p_valid_i
     connect \p_ready_o \pipe_p_ready_o
     connect \muxid \pipe_muxid
@@ -80264,10 +79983,10 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.src_l"
 module \src_l$51
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
   wire width 2 input 2 \s_src
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
@@ -80318,13 +80037,13 @@ module \src_l$51
     assign \q_int$next \q_int
     assign \q_int$next $5
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \q_int$next 2'00
     end
     sync init
       update \q_int 2'00
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \q_int \q_int$next
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
@@ -80409,10 +80128,10 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.opc_l"
 module \opc_l$52
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
   wire width 1 input 2 \s_opc
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
@@ -80463,13 +80182,13 @@ module \opc_l$52
     assign \q_int$next \q_int
     assign \q_int$next $5
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \q_int$next 1'0
     end
     sync init
       update \q_int 1'0
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \q_int \q_int$next
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
@@ -80554,10 +80273,10 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.req_l"
 module \req_l$53
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
   wire width 3 output 2 \q_req
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
@@ -80608,13 +80327,13 @@ module \req_l$53
     assign \q_int$next \q_int
     assign \q_int$next $5
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \q_int$next 3'000
     end
     sync init
       update \q_int 3'000
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \q_int \q_int$next
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
@@ -80699,10 +80418,10 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.rst_l"
 module \rst_l$54
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
   wire width 1 input 2 \s_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
@@ -80751,13 +80470,13 @@ module \rst_l$54
     assign \q_int$next \q_int
     assign \q_int$next $5
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \q_int$next 1'0
     end
     sync init
       update \q_int 1'0
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \q_int \q_int$next
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
@@ -80844,10 +80563,10 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.rok_l"
 module \rok_l$55
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
   wire width 1 output 2 \q_rdok
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
@@ -80898,13 +80617,13 @@ module \rok_l$55
     assign \q_int$next \q_int
     assign \q_int$next $5
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \q_int$next 1'0
     end
     sync init
       update \q_int 1'0
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \q_int \q_int$next
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
@@ -80989,10 +80708,10 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alui_l"
 module \alui_l$56
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
   wire width 1 output 2 \q_alui
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
@@ -81043,13 +80762,13 @@ module \alui_l$56
     assign \q_int$next \q_int
     assign \q_int$next $5
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \q_int$next 1'0
     end
     sync init
       update \q_int 1'0
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \q_int \q_int$next
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
@@ -81134,10 +80853,10 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_l"
 module \alu_l$57
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
   wire width 1 output 2 \q_alu
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
@@ -81188,13 +80907,13 @@ module \alu_l$57
     assign \q_int$next \q_int
     assign \q_int$next $5
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \q_int$next 1'0
     end
     sync init
       update \q_int 1'0
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \q_int \q_int$next
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
@@ -81279,10 +80998,8 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.logical0"
 module \logical0
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
   attribute \enum_value_0000001 "OP_NOP"
@@ -81357,7 +81074,7 @@ module \logical0
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 7 input 2 \oper_i_alu_logical0__insn_type
+  wire width 7 input 1 \oper_i_alu_logical0__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -81371,73 +81088,75 @@ module \logical0
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 11 input 3 \oper_i_alu_logical0__fn_unit
+  wire width 11 input 2 \oper_i_alu_logical0__fn_unit
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 64 input 4 \oper_i_alu_logical0__imm_data__imm
+  wire width 64 input 3 \oper_i_alu_logical0__imm_data__imm
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 5 \oper_i_alu_logical0__imm_data__imm_ok
+  wire width 1 input 4 \oper_i_alu_logical0__imm_data__imm_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 6 \oper_i_alu_logical0__rc__rc
+  wire width 1 input 5 \oper_i_alu_logical0__rc__rc
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 7 \oper_i_alu_logical0__rc__rc_ok
+  wire width 1 input 6 \oper_i_alu_logical0__rc__rc_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 8 \oper_i_alu_logical0__oe__oe
+  wire width 1 input 7 \oper_i_alu_logical0__oe__oe
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 9 \oper_i_alu_logical0__oe__oe_ok
+  wire width 1 input 8 \oper_i_alu_logical0__oe__oe_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 10 \oper_i_alu_logical0__invert_a
+  wire width 1 input 9 \oper_i_alu_logical0__invert_a
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 11 \oper_i_alu_logical0__zero_a
+  wire width 1 input 10 \oper_i_alu_logical0__zero_a
   attribute \enum_base_type "CryIn"
   attribute \enum_value_00 "ZERO"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "CA"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 2 input 12 \oper_i_alu_logical0__input_carry
+  wire width 2 input 11 \oper_i_alu_logical0__input_carry
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 13 \oper_i_alu_logical0__invert_out
+  wire width 1 input 12 \oper_i_alu_logical0__invert_out
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 14 \oper_i_alu_logical0__write_cr0
+  wire width 1 input 13 \oper_i_alu_logical0__write_cr0
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 15 \oper_i_alu_logical0__output_carry
+  wire width 1 input 14 \oper_i_alu_logical0__output_carry
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 16 \oper_i_alu_logical0__is_32bit
+  wire width 1 input 15 \oper_i_alu_logical0__is_32bit
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 17 \oper_i_alu_logical0__is_signed
+  wire width 1 input 16 \oper_i_alu_logical0__is_signed
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 4 input 18 \oper_i_alu_logical0__data_len
+  wire width 4 input 17 \oper_i_alu_logical0__data_len
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 32 input 19 \oper_i_alu_logical0__insn
+  wire width 32 input 18 \oper_i_alu_logical0__insn
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
-  wire width 1 input 20 \cu_issue_i
+  wire width 1 input 19 \cu_issue_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:106"
-  wire width 1 output 21 \cu_busy_o
+  wire width 1 output 20 \cu_busy_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
-  wire width 2 input 22 \cu_rdmaskn_i
+  wire width 2 input 21 \cu_rdmaskn_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 2 output 23 \cu_rd__rel_o
+  wire width 2 output 22 \cu_rd__rel_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 2 input 24 \cu_rd__go_i
+  wire width 2 input 23 \cu_rd__go_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
-  wire width 64 input 25 \src1_i
+  wire width 64 input 24 \src1_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
-  wire width 64 input 26 \src2_i
+  wire width 64 input 25 \src2_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 27 \o_ok
+  wire width 1 output 26 \o_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 3 output 28 \cu_wr__rel_o
+  wire width 3 output 27 \cu_wr__rel_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 3 input 29 \cu_wr__go_i
+  wire width 3 input 28 \cu_wr__go_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
-  wire width 64 output 30 \dest1_o
+  wire width 64 output 29 \dest1_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 31 \cr_a_ok
+  wire width 1 output 30 \cr_a_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
-  wire width 4 output 32 \dest2_o
+  wire width 4 output 31 \dest2_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 33 \xer_ca_ok
+  wire width 1 output 32 \xer_ca_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
-  wire width 2 output 34 \dest3_o
+  wire width 2 output 33 \dest3_o
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 34 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
   wire width 1 \alu_logical0_n_valid_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
@@ -81582,11 +81301,11 @@ module \logical0
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154"
   wire width 1 \alu_logical0_p_ready_o
   cell \alu_logical0 \alu_logical0
-    connect \rst \rst
-    connect \clk \clk
+    connect \coresync_clk \coresync_clk
     connect \o_ok \o_ok
     connect \cr_a_ok \cr_a_ok
     connect \xer_ca_ok \xer_ca_ok
+    connect \coresync_rst \coresync_rst
     connect \n_valid_o \alu_logical0_n_valid_o
     connect \n_ready_i \alu_logical0_n_ready_i
     connect \o \alu_logical0_o
@@ -81626,8 +81345,8 @@ module \logical0
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
   wire width 2 \src_l_q_src
   cell \src_l$51 \src_l
-    connect \rst \rst
-    connect \clk \clk
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
     connect \s_src \src_l_s_src
     connect \r_src \src_l_r_src
     connect \q_src \src_l_q_src
@@ -81643,8 +81362,8 @@ module \logical0
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
   wire width 1 \opc_l_q_opc
   cell \opc_l$52 \opc_l
-    connect \rst \rst
-    connect \clk \clk
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
     connect \s_opc \opc_l_s_opc
     connect \r_opc \opc_l_r_opc
     connect \q_opc \opc_l_q_opc
@@ -81656,8 +81375,8 @@ module \logical0
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
   wire width 3 \req_l_r_req
   cell \req_l$53 \req_l
-    connect \rst \rst
-    connect \clk \clk
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
     connect \q_req \req_l_q_req
     connect \s_req \req_l_s_req
     connect \r_req \req_l_r_req
@@ -81667,8 +81386,8 @@ module \logical0
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
   wire width 1 \rst_l_r_rst
   cell \rst_l$54 \rst_l
-    connect \rst \rst
-    connect \clk \clk
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
     connect \s_rst \rst_l_s_rst
     connect \r_rst \rst_l_r_rst
   end
@@ -81681,8 +81400,8 @@ module \logical0
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
   wire width 1 \rok_l_r_rdok$next
   cell \rok_l$55 \rok_l
-    connect \rst \rst
-    connect \clk \clk
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
     connect \q_rdok \rok_l_q_rdok
     connect \s_rdok \rok_l_s_rdok
     connect \r_rdok \rok_l_r_rdok
@@ -81696,8 +81415,8 @@ module \logical0
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
   wire width 1 \alui_l_s_alui
   cell \alui_l$56 \alui_l
-    connect \rst \rst
-    connect \clk \clk
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
     connect \q_alui \alui_l_q_alui
     connect \r_alui \alui_l_r_alui
     connect \s_alui \alui_l_s_alui
@@ -81711,8 +81430,8 @@ module \logical0
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
   wire width 1 \alu_l_s_alu
   cell \alu_l$57 \alu_l
-    connect \rst \rst
-    connect \clk \clk
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
     connect \q_alu \alu_l_q_alu
     connect \r_alu \alu_l_r_alu
     connect \s_alu \alu_l_s_alu
@@ -81792,7 +81511,7 @@ module \logical0
     assign \all_rd_dly$next \all_rd
     sync init
       update \all_rd_dly 1'0
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \all_rd_dly \all_rd_dly$next
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:192"
@@ -81841,7 +81560,7 @@ module \logical0
     assign \alu_done_dly$next \alu_done
     sync init
       update \alu_done_dly 1'0
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \alu_done_dly \alu_done_dly$next
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:199"
@@ -81902,13 +81621,13 @@ module \logical0
     assign \prev_wr_go$next \prev_wr_go
     assign \prev_wr_go$next $19
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \prev_wr_go$next 3'000
     end
     sync init
       update \prev_wr_go 3'000
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \prev_wr_go \prev_wr_go$next
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107"
@@ -82247,13 +81966,13 @@ module \logical0
     assign \rok_l_r_rdok$next \rok_l_r_rdok
     assign \rok_l_r_rdok$next $63
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \rok_l_r_rdok$next 1'1
     end
     sync init
       update \rok_l_r_rdok 1'1
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \rok_l_r_rdok \rok_l_r_rdok$next
   end
   process $group_17
@@ -82270,52 +81989,52 @@ module \logical0
     assign \opc_l_s_opc$next \opc_l_s_opc
     assign \opc_l_s_opc$next \cu_issue_i
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \opc_l_s_opc$next 1'0
     end
     sync init
       update \opc_l_s_opc 1'0
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \opc_l_s_opc \opc_l_s_opc$next
   end
   process $group_20
     assign \opc_l_r_opc$next \opc_l_r_opc
     assign \opc_l_r_opc$next \req_done
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \opc_l_r_opc$next 1'1
     end
     sync init
       update \opc_l_r_opc 1'1
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \opc_l_r_opc \opc_l_r_opc$next
   end
   process $group_21
     assign \src_l_s_src$next \src_l_s_src
     assign \src_l_s_src$next { \cu_issue_i \cu_issue_i }
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \src_l_s_src$next 2'00
     end
     sync init
       update \src_l_s_src 2'00
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \src_l_s_src \src_l_s_src$next
   end
   process $group_22
     assign \src_l_r_src$next \src_l_r_src
     assign \src_l_r_src$next \reset_r
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \src_l_r_src$next 2'11
     end
     sync init
       update \src_l_r_src 2'11
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \src_l_r_src \src_l_r_src$next
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:255"
@@ -82609,7 +82328,7 @@ module \logical0
         assign { \oper_l__insn$next \oper_l__data_len$next \oper_l__is_signed$next \oper_l__is_32bit$next \oper_l__output_carry$next \oper_l__write_cr0$next \oper_l__invert_out$next \oper_l__input_carry$next \oper_l__zero_a$next \oper_l__invert_a$next { \oper_l__oe__oe_ok$next \oper_l__oe__oe$next } { \oper_l__rc__rc_ok$next \oper_l__rc__rc$next } { \oper_l__imm_data__imm_ok$next \oper_l__imm_data__imm$next } \oper_l__fn_unit$next \oper_l__insn_type$next } { \oper_i_alu_logical0__insn \oper_i_alu_logical0__data_len \oper_i_alu_logical0__is_signed \oper_i_alu_logical0__is_32bit \oper_i_alu_logical0__output_carry \oper_i_alu_logical0__write_cr0 \oper_i_alu_logical0__invert_out \oper_i_alu_logical0__input_carry \oper_i_alu_logical0__zero_a \oper_i_alu_logical0__invert_a { \oper_i_alu_logical0__oe__oe_ok \oper_i_alu_logical0__oe__oe } { \oper_i_alu_logical0__rc__rc_ok \oper_i_alu_logical0__rc__rc } { \oper_i_alu_logical0__imm_data__imm_ok \oper_i_alu_logical0__imm_data__imm } \oper_i_alu_logical0__fn_unit \oper_i_alu_logical0__insn_type }
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \oper_l__imm_data__imm$next 64'0000000000000000000000000000000000000000000000000000000000000000
         assign \oper_l__imm_data__imm_ok$next 1'0
@@ -82637,7 +82356,7 @@ module \logical0
       update \oper_l__is_signed 1'0
       update \oper_l__data_len 4'0000
       update \oper_l__insn 32'00000000000000000000000000000000
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \oper_l__insn_type \oper_l__insn_type$next
       update \oper_l__fn_unit \oper_l__fn_unit$next
       update \oper_l__imm_data__imm \oper_l__imm_data__imm$next
@@ -82715,14 +82434,14 @@ module \logical0
         assign { \data_r0_l__o_ok$next \data_r0_l__o$next } { \o_ok \alu_logical0_o }
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \data_r0_l__o_ok$next 1'0
     end
     sync init
       update \data_r0_l__o 64'0000000000000000000000000000000000000000000000000000000000000000
       update \data_r0_l__o_ok 1'0
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \data_r0_l__o \data_r0_l__o$next
       update \data_r0_l__o_ok \data_r0_l__o_ok$next
   end
@@ -82784,14 +82503,14 @@ module \logical0
         assign { \data_r1_l__cr_a_ok$next \data_r1_l__cr_a$next } { \cr_a_ok \alu_logical0_cr_a }
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \data_r1_l__cr_a_ok$next 1'0
     end
     sync init
       update \data_r1_l__cr_a 4'0000
       update \data_r1_l__cr_a_ok 1'0
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \data_r1_l__cr_a \data_r1_l__cr_a$next
       update \data_r1_l__cr_a_ok \data_r1_l__cr_a_ok$next
   end
@@ -82853,14 +82572,14 @@ module \logical0
         assign { \data_r2_l__xer_ca_ok$next \data_r2_l__xer_ca$next } { \xer_ca_ok \alu_logical0_xer_ca }
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \data_r2_l__xer_ca_ok$next 1'0
     end
     sync init
       update \data_r2_l__xer_ca 2'00
       update \data_r2_l__xer_ca_ok 1'0
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \data_r2_l__xer_ca \data_r2_l__xer_ca$next
       update \data_r2_l__xer_ca_ok \data_r2_l__xer_ca_ok$next
   end
@@ -83027,7 +82746,7 @@ module \logical0
     end
     sync init
       update \src_r0 64'0000000000000000000000000000000000000000000000000000000000000000
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \src_r0 \src_r0$next
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
@@ -83059,7 +82778,7 @@ module \logical0
     end
     sync init
       update \src_r1 64'0000000000000000000000000000000000000000000000000000000000000000
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \src_r1 \src_r1$next
   end
   process $group_100
@@ -83084,13 +82803,13 @@ module \logical0
     assign \alui_l_r_alui$next \alui_l_r_alui
     assign \alui_l_r_alui$next $109
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \alui_l_r_alui$next 1'1
     end
     sync init
       update \alui_l_r_alui 1'1
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \alui_l_r_alui \alui_l_r_alui$next
   end
   process $group_102
@@ -83120,13 +82839,13 @@ module \logical0
     assign \alu_l_r_alu$next \alu_l_r_alu
     assign \alu_l_r_alu$next $111
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \alu_l_r_alu$next 1'1
     end
     sync init
       update \alu_l_r_alu 1'1
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \alu_l_r_alu \alu_l_r_alu$next
   end
   process $group_105
@@ -83914,10 +83633,10 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.alu_spr0.pipe"
 module \pipe$60
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153"
   wire width 1 input 2 \p_valid_i
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154"
@@ -84708,13 +84427,13 @@ module \pipe$60
         assign \r_busy$next 1'0
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \r_busy$next 1'0
     end
     sync init
       update \r_busy 1'0
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \r_busy \r_busy$next
   end
   process $group_32
@@ -84730,7 +84449,7 @@ module \pipe$60
     end
     sync init
       update \muxid$1 2'00
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \muxid$1 \muxid$1$next
   end
   process $group_33
@@ -84752,7 +84471,7 @@ module \pipe$60
       update \spr_op__fn_unit$3 11'00000000000
       update \spr_op__insn$4 32'00000000000000000000000000000000
       update \spr_op__is_32bit$5 1'0
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \spr_op__insn_type$2 \spr_op__insn_type$2$next
       update \spr_op__fn_unit$3 \spr_op__fn_unit$3$next
       update \spr_op__insn$4 \spr_op__insn$4$next
@@ -84771,14 +84490,14 @@ module \pipe$60
         assign { \o_ok$next \o$next } { \o_ok$30 \o$29 }
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \o_ok$next 1'0
     end
     sync init
       update \o 64'0000000000000000000000000000000000000000000000000000000000000000
       update \o_ok 1'0
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \o \o$next
       update \o_ok \o_ok$next
   end
@@ -84795,14 +84514,14 @@ module \pipe$60
         assign { \spr1_ok$next \spr1$6$next } { \spr1_ok$32 \spr1$31 }
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \spr1_ok$next 1'0
     end
     sync init
       update \spr1$6 64'0000000000000000000000000000000000000000000000000000000000000000
       update \spr1_ok 1'0
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \spr1$6 \spr1$6$next
       update \spr1_ok \spr1_ok$next
   end
@@ -84819,14 +84538,14 @@ module \pipe$60
         assign { \fast1_ok$next \fast1$7$next } { \fast1_ok$36 \fast1$35 }
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \fast1_ok$next 1'0
     end
     sync init
       update \fast1$7 64'0000000000000000000000000000000000000000000000000000000000000000
       update \fast1_ok 1'0
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \fast1$7 \fast1$7$next
       update \fast1_ok \fast1_ok$next
   end
@@ -84843,14 +84562,14 @@ module \pipe$60
         assign { \xer_so_ok$next \xer_so$8$next } { \xer_so_ok$38 \xer_so$37 }
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \xer_so_ok$next 1'0
     end
     sync init
       update \xer_so$8 1'0
       update \xer_so_ok 1'0
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \xer_so$8 \xer_so$8$next
       update \xer_so_ok \xer_so_ok$next
   end
@@ -84867,14 +84586,14 @@ module \pipe$60
         assign { \xer_ov_ok$next \xer_ov$9$next } { \xer_ov_ok$40 \xer_ov$39 }
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \xer_ov_ok$next 1'0
     end
     sync init
       update \xer_ov$9 2'00
       update \xer_ov_ok 1'0
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \xer_ov$9 \xer_ov$9$next
       update \xer_ov_ok \xer_ov_ok$next
   end
@@ -84891,14 +84610,14 @@ module \pipe$60
         assign { \xer_ca_ok$next \xer_ca$10$next } { \xer_ca_ok$42 \xer_ca$41 }
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \xer_ca_ok$next 1'0
     end
     sync init
       update \xer_ca$10 2'00
       update \xer_ca_ok 1'0
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \xer_ca$10 \xer_ca$10$next
       update \xer_ca_ok \xer_ca_ok$next
   end
@@ -84918,22 +84637,22 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.alu_spr0"
 module \alu_spr0
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 2 \o_ok
+  wire width 1 output 1 \o_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 3 \xer_ca_ok
+  wire width 1 output 2 \xer_ca_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 4 \xer_ov_ok
+  wire width 1 output 3 \xer_ov_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 5 \xer_so_ok
+  wire width 1 output 4 \xer_so_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 6 \fast1_ok
+  wire width 1 output 5 \fast1_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 7 \spr1_ok
+  wire width 1 output 6 \spr1_ok
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 7 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
   wire width 1 output 8 \n_valid_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
@@ -85302,8 +85021,8 @@ module \alu_spr0
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \pipe_xer_ca_ok
   cell \pipe$60 \pipe
-    connect \rst \rst
-    connect \clk \clk
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
     connect \p_valid_i \pipe_p_valid_i
     connect \p_ready_o \pipe_p_ready_o
     connect \muxid \pipe_muxid
@@ -85551,10 +85270,10 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.src_l"
 module \src_l$63
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
   wire width 6 input 2 \s_src
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
@@ -85605,13 +85324,13 @@ module \src_l$63
     assign \q_int$next \q_int
     assign \q_int$next $5
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \q_int$next 6'000000
     end
     sync init
       update \q_int 6'000000
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \q_int \q_int$next
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
@@ -85696,10 +85415,10 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.opc_l"
 module \opc_l$64
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
   wire width 1 input 2 \s_opc
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
@@ -85750,13 +85469,13 @@ module \opc_l$64
     assign \q_int$next \q_int
     assign \q_int$next $5
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \q_int$next 1'0
     end
     sync init
       update \q_int 1'0
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \q_int \q_int$next
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
@@ -85841,10 +85560,10 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.req_l"
 module \req_l$65
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
   wire width 6 output 2 \q_req
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
@@ -85895,13 +85614,13 @@ module \req_l$65
     assign \q_int$next \q_int
     assign \q_int$next $5
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \q_int$next 6'000000
     end
     sync init
       update \q_int 6'000000
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \q_int \q_int$next
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
@@ -85986,10 +85705,10 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.rst_l"
 module \rst_l$66
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
   wire width 1 input 2 \s_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
@@ -86038,13 +85757,13 @@ module \rst_l$66
     assign \q_int$next \q_int
     assign \q_int$next $5
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \q_int$next 1'0
     end
     sync init
       update \q_int 1'0
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \q_int \q_int$next
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
@@ -86131,10 +85850,10 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.rok_l"
 module \rok_l$67
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
   wire width 1 output 2 \q_rdok
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
@@ -86185,13 +85904,13 @@ module \rok_l$67
     assign \q_int$next \q_int
     assign \q_int$next $5
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \q_int$next 1'0
     end
     sync init
       update \q_int 1'0
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \q_int \q_int$next
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
@@ -86276,10 +85995,10 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.alui_l"
 module \alui_l$68
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
   wire width 1 output 2 \q_alui
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
@@ -86330,13 +86049,13 @@ module \alui_l$68
     assign \q_int$next \q_int
     assign \q_int$next $5
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \q_int$next 1'0
     end
     sync init
       update \q_int 1'0
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \q_int \q_int$next
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
@@ -86421,10 +86140,10 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.alu_l"
 module \alu_l$69
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
   wire width 1 output 2 \q_alu
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
@@ -86475,13 +86194,13 @@ module \alu_l$69
     assign \q_int$next \q_int
     assign \q_int$next $5
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \q_int$next 1'0
     end
     sync init
       update \q_int 1'0
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \q_int \q_int$next
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
@@ -86566,10 +86285,8 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fus.spr0"
 module \spr0
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
   attribute \enum_value_0000001 "OP_NOP"
@@ -86644,7 +86361,7 @@ module \spr0
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 7 input 2 \oper_i_alu_spr0__insn_type
+  wire width 7 input 1 \oper_i_alu_spr0__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -86658,61 +86375,63 @@ module \spr0
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 11 input 3 \oper_i_alu_spr0__fn_unit
+  wire width 11 input 2 \oper_i_alu_spr0__fn_unit
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 32 input 4 \oper_i_alu_spr0__insn
+  wire width 32 input 3 \oper_i_alu_spr0__insn
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 5 \oper_i_alu_spr0__is_32bit
+  wire width 1 input 4 \oper_i_alu_spr0__is_32bit
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
-  wire width 1 input 6 \cu_issue_i
+  wire width 1 input 5 \cu_issue_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:106"
-  wire width 1 output 7 \cu_busy_o
+  wire width 1 output 6 \cu_busy_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
-  wire width 6 input 8 \cu_rdmaskn_i
+  wire width 6 input 7 \cu_rdmaskn_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 6 output 9 \cu_rd__rel_o
+  wire width 6 output 8 \cu_rd__rel_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 6 input 10 \cu_rd__go_i
+  wire width 6 input 9 \cu_rd__go_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
-  wire width 64 input 11 \src1_i
+  wire width 64 input 10 \src1_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
-  wire width 1 input 12 \src4_i
+  wire width 1 input 11 \src4_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
-  wire width 2 input 13 \src6_i
+  wire width 2 input 12 \src6_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
-  wire width 2 input 14 \src5_i
+  wire width 2 input 13 \src5_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
-  wire width 64 input 15 \src3_i
+  wire width 64 input 14 \src3_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
-  wire width 64 input 16 \src2_i
+  wire width 64 input 15 \src2_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 17 \o_ok
+  wire width 1 output 16 \o_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 6 output 18 \cu_wr__rel_o
+  wire width 6 output 17 \cu_wr__rel_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 6 input 19 \cu_wr__go_i
+  wire width 6 input 18 \cu_wr__go_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
-  wire width 64 output 20 \dest1_o
+  wire width 64 output 19 \dest1_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 21 \xer_ca_ok
+  wire width 1 output 20 \xer_ca_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
-  wire width 2 output 22 \dest6_o
+  wire width 2 output 21 \dest6_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 23 \xer_ov_ok
+  wire width 1 output 22 \xer_ov_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
-  wire width 2 output 24 \dest5_o
+  wire width 2 output 23 \dest5_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 25 \xer_so_ok
+  wire width 1 output 24 \xer_so_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
-  wire width 1 output 26 \dest4_o
+  wire width 1 output 25 \dest4_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 27 \fast1_ok
+  wire width 1 output 26 \fast1_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
-  wire width 64 output 28 \dest3_o
+  wire width 64 output 27 \dest3_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 29 \spr1_ok
+  wire width 1 output 28 \spr1_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
-  wire width 64 output 30 \dest2_o
+  wire width 64 output 29 \dest2_o
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 30 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
   wire width 1 \alu_spr0_n_valid_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
@@ -86839,14 +86558,14 @@ module \spr0
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154"
   wire width 1 \alu_spr0_p_ready_o
   cell \alu_spr0 \alu_spr0
-    connect \rst \rst
-    connect \clk \clk
+    connect \coresync_clk \coresync_clk
     connect \o_ok \o_ok
     connect \xer_ca_ok \xer_ca_ok
     connect \xer_ov_ok \xer_ov_ok
     connect \xer_so_ok \xer_so_ok
     connect \fast1_ok \fast1_ok
     connect \spr1_ok \spr1_ok
+    connect \coresync_rst \coresync_rst
     connect \n_valid_o \alu_spr0_n_valid_o
     connect \n_ready_i \alu_spr0_n_ready_i
     connect \o \alu_spr0_o
@@ -86879,8 +86598,8 @@ module \spr0
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
   wire width 6 \src_l_q_src
   cell \src_l$63 \src_l
-    connect \rst \rst
-    connect \clk \clk
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
     connect \s_src \src_l_s_src
     connect \r_src \src_l_r_src
     connect \q_src \src_l_q_src
@@ -86896,8 +86615,8 @@ module \spr0
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
   wire width 1 \opc_l_q_opc
   cell \opc_l$64 \opc_l
-    connect \rst \rst
-    connect \clk \clk
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
     connect \s_opc \opc_l_s_opc
     connect \r_opc \opc_l_r_opc
     connect \q_opc \opc_l_q_opc
@@ -86909,8 +86628,8 @@ module \spr0
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
   wire width 6 \req_l_r_req
   cell \req_l$65 \req_l
-    connect \rst \rst
-    connect \clk \clk
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
     connect \q_req \req_l_q_req
     connect \s_req \req_l_s_req
     connect \r_req \req_l_r_req
@@ -86920,8 +86639,8 @@ module \spr0
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
   wire width 1 \rst_l_r_rst
   cell \rst_l$66 \rst_l
-    connect \rst \rst
-    connect \clk \clk
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
     connect \s_rst \rst_l_s_rst
     connect \r_rst \rst_l_r_rst
   end
@@ -86934,8 +86653,8 @@ module \spr0
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
   wire width 1 \rok_l_r_rdok$next
   cell \rok_l$67 \rok_l
-    connect \rst \rst
-    connect \clk \clk
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
     connect \q_rdok \rok_l_q_rdok
     connect \s_rdok \rok_l_s_rdok
     connect \r_rdok \rok_l_r_rdok
@@ -86949,8 +86668,8 @@ module \spr0
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
   wire width 1 \alui_l_s_alui
   cell \alui_l$68 \alui_l
-    connect \rst \rst
-    connect \clk \clk
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
     connect \q_alui \alui_l_q_alui
     connect \r_alui \alui_l_r_alui
     connect \s_alui \alui_l_s_alui
@@ -86964,8 +86683,8 @@ module \spr0
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
   wire width 1 \alu_l_s_alu
   cell \alu_l$69 \alu_l
-    connect \rst \rst
-    connect \clk \clk
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
     connect \q_alu \alu_l_q_alu
     connect \r_alu \alu_l_r_alu
     connect \s_alu \alu_l_s_alu
@@ -87045,7 +86764,7 @@ module \spr0
     assign \all_rd_dly$next \all_rd
     sync init
       update \all_rd_dly 1'0
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \all_rd_dly \all_rd_dly$next
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:192"
@@ -87094,7 +86813,7 @@ module \spr0
     assign \alu_done_dly$next \alu_done
     sync init
       update \alu_done_dly 1'0
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \alu_done_dly \alu_done_dly$next
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:199"
@@ -87155,13 +86874,13 @@ module \spr0
     assign \prev_wr_go$next \prev_wr_go
     assign \prev_wr_go$next $24
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \prev_wr_go$next 6'000000
     end
     sync init
       update \prev_wr_go 6'000000
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \prev_wr_go \prev_wr_go$next
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107"
@@ -87500,13 +87219,13 @@ module \spr0
     assign \rok_l_r_rdok$next \rok_l_r_rdok
     assign \rok_l_r_rdok$next $68
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \rok_l_r_rdok$next 1'1
     end
     sync init
       update \rok_l_r_rdok 1'1
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \rok_l_r_rdok \rok_l_r_rdok$next
   end
   process $group_17
@@ -87523,52 +87242,52 @@ module \spr0
     assign \opc_l_s_opc$next \opc_l_s_opc
     assign \opc_l_s_opc$next \cu_issue_i
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \opc_l_s_opc$next 1'0
     end
     sync init
       update \opc_l_s_opc 1'0
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \opc_l_s_opc \opc_l_s_opc$next
   end
   process $group_20
     assign \opc_l_r_opc$next \opc_l_r_opc
     assign \opc_l_r_opc$next \req_done
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \opc_l_r_opc$next 1'1
     end
     sync init
       update \opc_l_r_opc 1'1
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \opc_l_r_opc \opc_l_r_opc$next
   end
   process $group_21
     assign \src_l_s_src$next \src_l_s_src
     assign \src_l_s_src$next { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i }
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \src_l_s_src$next 6'000000
     end
     sync init
       update \src_l_s_src 6'000000
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \src_l_s_src \src_l_s_src$next
   end
   process $group_22
     assign \src_l_r_src$next \src_l_r_src
     assign \src_l_r_src$next \reset_r
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \src_l_r_src$next 6'111111
     end
     sync init
       update \src_l_r_src 6'111111
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \src_l_r_src \src_l_r_src$next
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:255"
@@ -87750,7 +87469,7 @@ module \spr0
       update \oper_l__fn_unit 11'00000000000
       update \oper_l__insn 32'00000000000000000000000000000000
       update \oper_l__is_32bit 1'0
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \oper_l__insn_type \oper_l__insn_type$next
       update \oper_l__fn_unit \oper_l__fn_unit$next
       update \oper_l__insn \oper_l__insn$next
@@ -87814,14 +87533,14 @@ module \spr0
         assign { \data_r0_l__o_ok$next \data_r0_l__o$next } { \o_ok \alu_spr0_o }
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \data_r0_l__o_ok$next 1'0
     end
     sync init
       update \data_r0_l__o 64'0000000000000000000000000000000000000000000000000000000000000000
       update \data_r0_l__o_ok 1'0
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \data_r0_l__o \data_r0_l__o$next
       update \data_r0_l__o_ok \data_r0_l__o_ok$next
   end
@@ -87883,14 +87602,14 @@ module \spr0
         assign { \data_r1_l__spr1_ok$next \data_r1_l__spr1$next } { \spr1_ok \alu_spr0_spr1 }
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \data_r1_l__spr1_ok$next 1'0
     end
     sync init
       update \data_r1_l__spr1 64'0000000000000000000000000000000000000000000000000000000000000000
       update \data_r1_l__spr1_ok 1'0
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \data_r1_l__spr1 \data_r1_l__spr1$next
       update \data_r1_l__spr1_ok \data_r1_l__spr1_ok$next
   end
@@ -87952,14 +87671,14 @@ module \spr0
         assign { \data_r2_l__fast1_ok$next \data_r2_l__fast1$next } { \fast1_ok \alu_spr0_fast1 }
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \data_r2_l__fast1_ok$next 1'0
     end
     sync init
       update \data_r2_l__fast1 64'0000000000000000000000000000000000000000000000000000000000000000
       update \data_r2_l__fast1_ok 1'0
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \data_r2_l__fast1 \data_r2_l__fast1$next
       update \data_r2_l__fast1_ok \data_r2_l__fast1_ok$next
   end
@@ -88021,14 +87740,14 @@ module \spr0
         assign { \data_r3_l__xer_so_ok$next \data_r3_l__xer_so$next } { \xer_so_ok \alu_spr0_xer_so }
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \data_r3_l__xer_so_ok$next 1'0
     end
     sync init
       update \data_r3_l__xer_so 1'0
       update \data_r3_l__xer_so_ok 1'0
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \data_r3_l__xer_so \data_r3_l__xer_so$next
       update \data_r3_l__xer_so_ok \data_r3_l__xer_so_ok$next
   end
@@ -88090,14 +87809,14 @@ module \spr0
         assign { \data_r4_l__xer_ov_ok$next \data_r4_l__xer_ov$next } { \xer_ov_ok \alu_spr0_xer_ov }
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \data_r4_l__xer_ov_ok$next 1'0
     end
     sync init
       update \data_r4_l__xer_ov 2'00
       update \data_r4_l__xer_ov_ok 1'0
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \data_r4_l__xer_ov \data_r4_l__xer_ov$next
       update \data_r4_l__xer_ov_ok \data_r4_l__xer_ov_ok$next
   end
@@ -88159,14 +87878,14 @@ module \spr0
         assign { \data_r5_l__xer_ca_ok$next \data_r5_l__xer_ca$next } { \xer_ca_ok \alu_spr0_xer_ca }
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \data_r5_l__xer_ca_ok$next 1'0
     end
     sync init
       update \data_r5_l__xer_ca 2'00
       update \data_r5_l__xer_ca_ok 1'0
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \data_r5_l__xer_ca \data_r5_l__xer_ca$next
       update \data_r5_l__xer_ca_ok \data_r5_l__xer_ca_ok$next
   end
@@ -88290,7 +88009,7 @@ module \spr0
     end
     sync init
       update \src_r0 64'0000000000000000000000000000000000000000000000000000000000000000
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \src_r0 \src_r0$next
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
@@ -88322,7 +88041,7 @@ module \spr0
     end
     sync init
       update \src_r1 64'0000000000000000000000000000000000000000000000000000000000000000
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \src_r1 \src_r1$next
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
@@ -88354,7 +88073,7 @@ module \spr0
     end
     sync init
       update \src_r2 64'0000000000000000000000000000000000000000000000000000000000000000
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \src_r2 \src_r2$next
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
@@ -88386,7 +88105,7 @@ module \spr0
     end
     sync init
       update \src_r3 1'0
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \src_r3 \src_r3$next
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
@@ -88418,7 +88137,7 @@ module \spr0
     end
     sync init
       update \src_r4 2'00
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \src_r4 \src_r4$next
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
@@ -88450,7 +88169,7 @@ module \spr0
     end
     sync init
       update \src_r5 2'00
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \src_r5 \src_r5$next
   end
   process $group_74
@@ -88475,13 +88194,13 @@ module \spr0
     assign \alui_l_r_alui$next \alui_l_r_alui
     assign \alui_l_r_alui$next $136
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \alui_l_r_alui$next 1'1
     end
     sync init
       update \alui_l_r_alui 1'1
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \alui_l_r_alui \alui_l_r_alui$next
   end
   process $group_76
@@ -88511,13 +88230,13 @@ module \spr0
     assign \alu_l_r_alu$next \alu_l_r_alu
     assign \alu_l_r_alu$next $138
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \alu_l_r_alu$next 1'1
     end
     sync init
       update \alu_l_r_alu 1'1
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \alu_l_r_alu \alu_l_r_alu$next
   end
   process $group_79
@@ -88837,7 +88556,7 @@ module \spr0
   connect \cu_shadown_i 1'1
 end
 attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.p"
+attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.p"
 module \p$70
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153"
   wire width 1 input 0 \p_valid_i
@@ -88865,7 +88584,7 @@ module \p$70
   end
 end
 attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.n"
+attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.n"
 module \n$71
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
   wire width 1 input 0 \n_valid_o
@@ -88893,7 +88612,7 @@ module \n$71
   end
 end
 attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe1.p"
+attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_start.p"
 module \p$72
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153"
   wire width 1 input 0 \p_valid_i
@@ -88921,7 +88640,7 @@ module \p$72
   end
 end
 attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe1.n"
+attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_start.n"
 module \n$73
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
   wire width 1 input 0 \n_valid_o
@@ -88949,7 +88668,7 @@ module \n$73
   end
 end
 attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe1.input"
+attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_start.input"
 module \input$74
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 input 0 \muxid
@@ -89027,7 +88746,7 @@ module \input$74
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 7 input 1 \mul_op__insn_type
+  wire width 7 input 1 \logical_op__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -89041,41 +88760,51 @@ module \input$74
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 11 input 2 \mul_op__fn_unit
+  wire width 11 input 2 \logical_op__fn_unit
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 64 input 3 \mul_op__imm_data__imm
+  wire width 64 input 3 \logical_op__imm_data__imm
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 4 \mul_op__imm_data__imm_ok
+  wire width 1 input 4 \logical_op__imm_data__imm_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 5 \mul_op__rc__rc
+  wire width 1 input 5 \logical_op__rc__rc
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 6 \mul_op__rc__rc_ok
+  wire width 1 input 6 \logical_op__rc__rc_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 7 \mul_op__oe__oe
+  wire width 1 input 7 \logical_op__oe__oe
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 8 \mul_op__oe__oe_ok
+  wire width 1 input 8 \logical_op__oe__oe_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 9 \mul_op__invert_a
+  wire width 1 input 9 \logical_op__invert_a
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 10 \mul_op__zero_a
+  wire width 1 input 10 \logical_op__zero_a
+  attribute \enum_base_type "CryIn"
+  attribute \enum_value_00 "ZERO"
+  attribute \enum_value_01 "ONE"
+  attribute \enum_value_10 "CA"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 11 \mul_op__invert_out
+  wire width 2 input 11 \logical_op__input_carry
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 12 \mul_op__write_cr0
+  wire width 1 input 12 \logical_op__invert_out
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 13 \mul_op__is_32bit
+  wire width 1 input 13 \logical_op__write_cr0
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 14 \mul_op__is_signed
+  wire width 1 input 14 \logical_op__output_carry
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 32 input 15 \mul_op__insn
+  wire width 1 input 15 \logical_op__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 16 \logical_op__is_signed
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 4 input 17 \logical_op__data_len
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 input 18 \logical_op__insn
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
-  wire width 64 input 16 \ra
+  wire width 64 input 19 \ra
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
-  wire width 64 input 17 \rb
+  wire width 64 input 20 \rb
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
-  wire width 1 input 18 \xer_so
+  wire width 1 input 21 \xer_so
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
-  wire width 2 output 19 \muxid$1
+  wire width 2 output 22 \muxid$1
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
   attribute \enum_value_0000001 "OP_NOP"
@@ -89150,7 +88879,7 @@ module \input$74
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 7 output 20 \mul_op__insn_type$2
+  wire width 7 output 23 \logical_op__insn_type$2
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -89164,58 +88893,68 @@ module \input$74
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 11 output 21 \mul_op__fn_unit$3
+  wire width 11 output 24 \logical_op__fn_unit$3
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 64 output 22 \mul_op__imm_data__imm$4
+  wire width 64 output 25 \logical_op__imm_data__imm$4
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 23 \mul_op__imm_data__imm_ok$5
+  wire width 1 output 26 \logical_op__imm_data__imm_ok$5
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 24 \mul_op__rc__rc$6
+  wire width 1 output 27 \logical_op__rc__rc$6
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 25 \mul_op__rc__rc_ok$7
+  wire width 1 output 28 \logical_op__rc__rc_ok$7
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 26 \mul_op__oe__oe$8
+  wire width 1 output 29 \logical_op__oe__oe$8
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 27 \mul_op__oe__oe_ok$9
+  wire width 1 output 30 \logical_op__oe__oe_ok$9
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 28 \mul_op__invert_a$10
+  wire width 1 output 31 \logical_op__invert_a$10
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 29 \mul_op__zero_a$11
+  wire width 1 output 32 \logical_op__zero_a$11
+  attribute \enum_base_type "CryIn"
+  attribute \enum_value_00 "ZERO"
+  attribute \enum_value_01 "ONE"
+  attribute \enum_value_10 "CA"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 30 \mul_op__invert_out$12
+  wire width 2 output 33 \logical_op__input_carry$12
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 31 \mul_op__write_cr0$13
+  wire width 1 output 34 \logical_op__invert_out$13
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 32 \mul_op__is_32bit$14
+  wire width 1 output 35 \logical_op__write_cr0$14
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 33 \mul_op__is_signed$15
+  wire width 1 output 36 \logical_op__output_carry$15
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 32 output 34 \mul_op__insn$16
+  wire width 1 output 37 \logical_op__is_32bit$16
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 38 \logical_op__is_signed$17
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 4 output 39 \logical_op__data_len$18
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 output 40 \logical_op__insn$19
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
-  wire width 64 output 35 \ra$17
+  wire width 64 output 41 \ra$20
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
-  wire width 64 output 36 \rb$18
+  wire width 64 output 42 \rb$21
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
-  wire width 1 output 37 \xer_so$19
+  wire width 1 output 43 \xer_so$22
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20"
   wire width 64 \a
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:24"
-  wire width 64 $20
+  wire width 64 $23
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:24"
-  cell $not $21
+  cell $not $24
     parameter \A_SIGNED 0
     parameter \A_WIDTH 64
     parameter \Y_WIDTH 64
     connect \A \ra
-    connect \Y $20
+    connect \Y $23
   end
   process $group_0
     assign \a 64'0000000000000000000000000000000000000000000000000000000000000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:23"
-    switch { \mul_op__invert_a }
+    switch { \logical_op__invert_a }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:23"
       case 1'1
-        assign \a $20
+        assign \a $23
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:25"
       case
         assign \a \ra
@@ -89223,17 +88962,17 @@ module \input$74
     sync init
   end
   process $group_1
-    assign \ra$17 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \ra$17 \a
+    assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \ra$20 \a
     sync init
   end
   process $group_2
-    assign \xer_so$19 1'0
+    assign \xer_so$22 1'0
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:47"
-    switch { \mul_op__oe__oe_ok }
+    switch { \logical_op__oe__oe_ok }
       attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:47"
       case 1'1
-        assign \xer_so$19 \xer_so
+        assign \xer_so$22 \xer_so
     end
     sync init
   end
@@ -89243,33 +88982,36 @@ module \input$74
     sync init
   end
   process $group_4
-    assign \mul_op__insn_type$2 7'0000000
-    assign \mul_op__fn_unit$3 11'00000000000
-    assign \mul_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \mul_op__imm_data__imm_ok$5 1'0
-    assign \mul_op__rc__rc$6 1'0
-    assign \mul_op__rc__rc_ok$7 1'0
-    assign \mul_op__oe__oe$8 1'0
-    assign \mul_op__oe__oe_ok$9 1'0
-    assign \mul_op__invert_a$10 1'0
-    assign \mul_op__zero_a$11 1'0
-    assign \mul_op__invert_out$12 1'0
-    assign \mul_op__write_cr0$13 1'0
-    assign \mul_op__is_32bit$14 1'0
-    assign \mul_op__is_signed$15 1'0
-    assign \mul_op__insn$16 32'00000000000000000000000000000000
-    assign { \mul_op__insn$16 \mul_op__is_signed$15 \mul_op__is_32bit$14 \mul_op__write_cr0$13 \mul_op__invert_out$12 \mul_op__zero_a$11 \mul_op__invert_a$10 { \mul_op__oe__oe_ok$9 \mul_op__oe__oe$8 } { \mul_op__rc__rc_ok$7 \mul_op__rc__rc$6 } { \mul_op__imm_data__imm_ok$5 \mul_op__imm_data__imm$4 } \mul_op__fn_unit$3 \mul_op__insn_type$2 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__invert_out \mul_op__zero_a \mul_op__invert_a { \mul_op__oe__oe_ok \mul_op__oe__oe } { \mul_op__rc__rc_ok \mul_op__rc__rc } { \mul_op__imm_data__imm_ok \mul_op__imm_data__imm } \mul_op__fn_unit \mul_op__insn_type }
+    assign \logical_op__insn_type$2 7'0000000
+    assign \logical_op__fn_unit$3 11'00000000000
+    assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \logical_op__imm_data__imm_ok$5 1'0
+    assign \logical_op__rc__rc$6 1'0
+    assign \logical_op__rc__rc_ok$7 1'0
+    assign \logical_op__oe__oe$8 1'0
+    assign \logical_op__oe__oe_ok$9 1'0
+    assign \logical_op__invert_a$10 1'0
+    assign \logical_op__zero_a$11 1'0
+    assign \logical_op__input_carry$12 2'00
+    assign \logical_op__invert_out$13 1'0
+    assign \logical_op__write_cr0$14 1'0
+    assign \logical_op__output_carry$15 1'0
+    assign \logical_op__is_32bit$16 1'0
+    assign \logical_op__is_signed$17 1'0
+    assign \logical_op__data_len$18 4'0000
+    assign \logical_op__insn$19 32'00000000000000000000000000000000
+    assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_a$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_a { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type }
     sync init
   end
-  process $group_19
-    assign \rb$18 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \rb$18 \rb
+  process $group_22
+    assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \rb$21 \rb
     sync init
   end
 end
 attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe1.mul1"
-module \mul1
+attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_start.setup_stage"
+module \setup_stage
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 input 0 \muxid
   attribute \enum_base_type "MicrOp"
@@ -89346,7 +89088,7 @@ module \mul1
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 7 input 1 \mul_op__insn_type
+  wire width 7 input 1 \logical_op__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -89360,41 +89102,51 @@ module \mul1
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 11 input 2 \mul_op__fn_unit
+  wire width 11 input 2 \logical_op__fn_unit
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 64 input 3 \mul_op__imm_data__imm
+  wire width 64 input 3 \logical_op__imm_data__imm
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 4 \mul_op__imm_data__imm_ok
+  wire width 1 input 4 \logical_op__imm_data__imm_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 5 \mul_op__rc__rc
+  wire width 1 input 5 \logical_op__rc__rc
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 6 \mul_op__rc__rc_ok
+  wire width 1 input 6 \logical_op__rc__rc_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 7 \mul_op__oe__oe
+  wire width 1 input 7 \logical_op__oe__oe
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 8 \mul_op__oe__oe_ok
+  wire width 1 input 8 \logical_op__oe__oe_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 9 \mul_op__invert_a
+  wire width 1 input 9 \logical_op__invert_a
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 10 \mul_op__zero_a
+  wire width 1 input 10 \logical_op__zero_a
+  attribute \enum_base_type "CryIn"
+  attribute \enum_value_00 "ZERO"
+  attribute \enum_value_01 "ONE"
+  attribute \enum_value_10 "CA"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 11 \mul_op__invert_out
+  wire width 2 input 11 \logical_op__input_carry
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 12 \mul_op__write_cr0
+  wire width 1 input 12 \logical_op__invert_out
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 13 \mul_op__is_32bit
+  wire width 1 input 13 \logical_op__write_cr0
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 14 \mul_op__is_signed
+  wire width 1 input 14 \logical_op__output_carry
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 32 input 15 \mul_op__insn
+  wire width 1 input 15 \logical_op__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 16 \logical_op__is_signed
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 4 input 17 \logical_op__data_len
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 input 18 \logical_op__insn
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
-  wire width 64 input 16 \ra
+  wire width 64 input 19 \ra
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
-  wire width 64 input 17 \rb
+  wire width 64 input 20 \rb
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
-  wire width 1 input 18 \xer_so
+  wire width 1 input 21 \xer_so
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
-  wire width 2 output 19 \muxid$1
+  wire width 2 output 22 \muxid$1
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
   attribute \enum_value_0000001 "OP_NOP"
@@ -89469,7 +89221,7 @@ module \mul1
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 7 output 20 \mul_op__insn_type$2
+  wire width 7 output 23 \logical_op__insn_type$2
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -89483,193 +89235,172 @@ module \mul1
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 11 output 21 \mul_op__fn_unit$3
+  wire width 11 output 24 \logical_op__fn_unit$3
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 64 output 22 \mul_op__imm_data__imm$4
+  wire width 64 output 25 \logical_op__imm_data__imm$4
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 23 \mul_op__imm_data__imm_ok$5
+  wire width 1 output 26 \logical_op__imm_data__imm_ok$5
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 24 \mul_op__rc__rc$6
+  wire width 1 output 27 \logical_op__rc__rc$6
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 25 \mul_op__rc__rc_ok$7
+  wire width 1 output 28 \logical_op__rc__rc_ok$7
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 26 \mul_op__oe__oe$8
+  wire width 1 output 29 \logical_op__oe__oe$8
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 27 \mul_op__oe__oe_ok$9
+  wire width 1 output 30 \logical_op__oe__oe_ok$9
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 28 \mul_op__invert_a$10
+  wire width 1 output 31 \logical_op__invert_a$10
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 29 \mul_op__zero_a$11
+  wire width 1 output 32 \logical_op__zero_a$11
+  attribute \enum_base_type "CryIn"
+  attribute \enum_value_00 "ZERO"
+  attribute \enum_value_01 "ONE"
+  attribute \enum_value_10 "CA"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 30 \mul_op__invert_out$12
+  wire width 2 output 33 \logical_op__input_carry$12
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 31 \mul_op__write_cr0$13
+  wire width 1 output 34 \logical_op__invert_out$13
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 32 \mul_op__is_32bit$14
+  wire width 1 output 35 \logical_op__write_cr0$14
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 33 \mul_op__is_signed$15
+  wire width 1 output 36 \logical_op__output_carry$15
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 32 output 34 \mul_op__insn$16
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
-  wire width 64 output 35 \ra$17
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
-  wire width 64 output 36 \rb$18
+  wire width 1 output 37 \logical_op__is_32bit$16
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 38 \logical_op__is_signed$17
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 4 output 39 \logical_op__data_len$18
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 output 40 \logical_op__insn$19
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
-  wire width 1 output 37 \xer_so$19
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11"
-  wire width 1 output 38 \neg_res
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12"
-  wire width 1 output 39 \neg_res32
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:30"
-  wire width 1 \is_32bit
+  wire width 1 output 41 \xer_so$20
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160"
+  wire width 1 output 42 \divisor_neg
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161"
+  wire width 1 output 43 \dividend_neg
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167"
+  wire width 1 output 44 \dive_abs_ov32
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168"
+  wire width 1 output 45 \dive_abs_ov64
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162"
+  wire width 1 output 46 \div_by_zero
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18"
+  wire width 128 output 47 \dividend
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19"
+  wire width 64 output 48 \divisor_radicand
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21"
+  wire width 2 output 49 \operation
+  wire width 1 $verilog_initial_trigger
   process $group_0
-    assign \is_32bit 1'0
-    assign \is_32bit \mul_op__is_32bit
+    assign \operation 2'00
+    assign \operation 2'01
+    assign $verilog_initial_trigger $verilog_initial_trigger
     sync init
+      update $verilog_initial_trigger 1'0
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:31"
-  wire width 1 \sign_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:38"
-  wire width 1 $20
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:38"
-  cell $mux $21
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:45"
+  wire width 1 $21
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:45"
+  cell $mux $22
     parameter \WIDTH 1
     connect \A \ra [63]
     connect \B \ra [31]
-    connect \S \mul_op__is_32bit
-    connect \Y $20
+    connect \S \logical_op__is_32bit
+    connect \Y $21
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:38"
-  wire width 1 $22
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:38"
-  cell $and $23
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:45"
+  wire width 1 $23
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:45"
+  cell $and $24
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $20
-    connect \B \mul_op__is_signed
-    connect \Y $22
+    connect \A $21
+    connect \B \logical_op__is_signed
+    connect \Y $23
   end
   process $group_1
-    assign \sign_a 1'0
-    assign \sign_a $22
+    assign \dividend_neg 1'0
+    assign \dividend_neg $23
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:32"
-  wire width 1 \sign_b
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:39"
-  wire width 1 $24
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:39"
-  cell $mux $25
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:46"
+  wire width 1 $25
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:46"
+  cell $mux $26
     parameter \WIDTH 1
     connect \A \rb [63]
     connect \B \rb [31]
-    connect \S \mul_op__is_32bit
-    connect \Y $24
+    connect \S \logical_op__is_32bit
+    connect \Y $25
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:39"
-  wire width 1 $26
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:39"
-  cell $and $27
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:46"
+  wire width 1 $27
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:46"
+  cell $and $28
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $24
-    connect \B \mul_op__is_signed
-    connect \Y $26
+    connect \A $25
+    connect \B \logical_op__is_signed
+    connect \Y $27
   end
   process $group_2
-    assign \sign_b 1'0
-    assign \sign_b $26
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:33"
-  wire width 1 \sign32_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:40"
-  wire width 1 $28
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:40"
-  cell $and $29
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \ra [31]
-    connect \B \mul_op__is_signed
-    connect \Y $28
-  end
-  process $group_3
-    assign \sign32_a 1'0
-    assign \sign32_a $28
+    assign \divisor_neg 1'0
+    assign \divisor_neg $27
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:34"
-  wire width 1 \sign32_b
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:41"
-  wire width 1 $30
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:41"
-  cell $and $31
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:51"
+  wire width 64 \abs_dor
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:53"
+  wire width 65 $29
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:53"
+  wire width 65 $30
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:53"
+  cell $neg $31
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \rb [31]
-    connect \B \mul_op__is_signed
+    parameter \A_WIDTH 64
+    parameter \Y_WIDTH 65
+    connect \A \rb
     connect \Y $30
   end
-  process $group_4
-    assign \sign32_b 1'0
-    assign \sign32_b $30
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:44"
-  wire width 1 $32
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:44"
-  cell $xor $33
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
+  wire width 65 $32
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
+  cell $pos $33
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \sign_a
-    connect \B \sign_b
+    parameter \A_WIDTH 64
+    parameter \Y_WIDTH 65
+    connect \A \rb
     connect \Y $32
   end
-  process $group_5
-    assign \neg_res 1'0
-    assign \neg_res $32
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:45"
-  wire width 1 $34
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:45"
-  cell $xor $35
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \sign32_a
-    connect \B \sign32_b
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:53"
+  wire width 65 $34
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:53"
+  cell $mux $35
+    parameter \WIDTH 65
+    connect \A $32
+    connect \B $30
+    connect \S \divisor_neg
     connect \Y $34
   end
-  process $group_6
-    assign \neg_res32 1'0
-    assign \neg_res32 $34
+  connect $29 $34
+  process $group_3
+    assign \abs_dor 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \abs_dor $29 [63:0]
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:50"
-  wire width 64 \abs_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:52"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:52"
+  wire width 64 \abs_dend
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:54"
   wire width 65 $36
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:52"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:54"
   wire width 65 $37
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:52"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:54"
   cell $neg $38
     parameter \A_SIGNED 0
     parameter \A_WIDTH 64
@@ -89687,131 +89418,257 @@ module \mul1
     connect \A \ra
     connect \Y $39
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:52"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:54"
   wire width 65 $41
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:52"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:54"
   cell $mux $42
     parameter \WIDTH 65
     connect \A $39
     connect \B $37
-    connect \S \sign_a
+    connect \S \dividend_neg
     connect \Y $41
   end
   connect $36 $41
-  process $group_7
-    assign \abs_a 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \abs_a $36 [63:0]
+  process $group_4
+    assign \abs_dend 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \abs_dend $36 [63:0]
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:51"
-  wire width 64 \abs_b
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:53"
-  wire width 65 $43
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:53"
-  wire width 65 $44
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:53"
-  cell $neg $45
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:57"
+  wire width 1 $43
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:57"
+  cell $ge $44
     parameter \A_SIGNED 0
     parameter \A_WIDTH 64
-    parameter \Y_WIDTH 65
-    connect \A \rb
-    connect \Y $44
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 64
+    parameter \Y_WIDTH 1
+    connect \A \abs_dend
+    connect \B \abs_dor
+    connect \Y $43
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
-  wire width 65 $46
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
-  cell $pos $47
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:58"
+  wire width 1 $45
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:58"
+  cell $eq $46
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 64
-    parameter \Y_WIDTH 65
-    connect \A \rb
-    connect \Y $46
+    parameter \A_WIDTH 7
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 7
+    parameter \Y_WIDTH 1
+    connect \A \logical_op__insn_type
+    connect \B 7'0011110
+    connect \Y $45
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:53"
-  wire width 65 $48
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:53"
-  cell $mux $49
-    parameter \WIDTH 65
-    connect \A $46
-    connect \B $44
-    connect \S \sign_b
-    connect \Y $48
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:58"
+  wire width 1 $47
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:58"
+  cell $and $48
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $43
+    connect \B $45
+    connect \Y $47
   end
-  connect $43 $48
-  process $group_8
-    assign \abs_b 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \abs_b $43 [63:0]
+  process $group_5
+    assign \dive_abs_ov64 1'0
+    assign \dive_abs_ov64 $47
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:60"
+  wire width 1 $49
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:60"
+  cell $ge $50
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 32
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 32
+    parameter \Y_WIDTH 1
+    connect \A \abs_dend [31:0]
+    connect \B \abs_dor [31:0]
+    connect \Y $49
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:61"
+  wire width 1 $51
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:61"
+  cell $eq $52
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 7
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 7
+    parameter \Y_WIDTH 1
+    connect \A \logical_op__insn_type
+    connect \B 7'0011110
+    connect \Y $51
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:61"
+  wire width 1 $53
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:61"
+  cell $and $54
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $49
+    connect \B $51
+    connect \Y $53
+  end
+  process $group_6
+    assign \dive_abs_ov32 1'0
+    assign \dive_abs_ov32 $53
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:34"
-  wire width 32 $50
+  wire width 32 $55
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:34"
-  cell $mux $51
+  cell $mux $56
     parameter \WIDTH 32
-    connect \A \abs_a [63:32]
+    connect \A \abs_dor [63:32]
     connect \B 32'00000000000000000000000000000000
-    connect \S \is_32bit
-    connect \Y $50
+    connect \S \logical_op__is_32bit
+    connect \Y $55
   end
-  process $group_9
-    assign \ra$17 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \ra$17 [31:0] \abs_a [31:0]
-    assign \ra$17 [63:32] $50
+  process $group_7
+    assign \divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \divisor_radicand [31:0] \abs_dor [31:0]
+    assign \divisor_radicand [63:32] $55
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:67"
+  wire width 1 $57
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:67"
+  cell $eq $58
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 64
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \divisor_radicand
+    connect \B 1'0
+    connect \Y $57
+  end
+  process $group_8
+    assign \div_by_zero 1'0
+    assign \div_by_zero $57
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:34"
-  wire width 32 $52
+  wire width 32 $59
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:34"
-  cell $mux $53
+  cell $mux $60
     parameter \WIDTH 32
-    connect \A \abs_b [63:32]
+    connect \A \abs_dend [63:32]
     connect \B 32'00000000000000000000000000000000
-    connect \S \is_32bit
-    connect \Y $52
+    connect \S \logical_op__is_32bit
+    connect \Y $59
   end
-  process $group_10
-    assign \rb$18 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \rb$18 [31:0] \abs_b [31:0]
-    assign \rb$18 [63:32] $52
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:79"
+  wire width 128 $61
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:79"
+  wire width 95 $62
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:79"
+  cell $sshl $63
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 32
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 6
+    parameter \Y_WIDTH 95
+    connect \A \abs_dend [31:0]
+    connect \B 6'100000
+    connect \Y $62
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:79"
+  cell $pos $64
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 95
+    parameter \Y_WIDTH 128
+    connect \A $62
+    connect \Y $61
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:81"
+  wire width 191 $65
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:81"
+  wire width 191 $66
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:81"
+  cell $sshl $67
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 64
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 7
+    parameter \Y_WIDTH 191
+    connect \A \abs_dend
+    connect \B 7'1000000
+    connect \Y $66
+  end
+  connect $65 $66
+  process $group_9
+    assign \dividend 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:72"
+    switch \logical_op__insn_type
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:74"
+      attribute \nmigen.decoding "OP_DIV/29|OP_MOD/47"
+      case 7'0011101, 7'0101111
+        assign \dividend [31:0] \abs_dend [31:0]
+        assign \dividend [63:32] $59
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:77"
+      attribute \nmigen.decoding "OP_DIVE/30"
+      case 7'0011110
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:78"
+        switch { \logical_op__is_32bit }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:78"
+          case 1'1
+            assign \dividend $61
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:80"
+          case
+            assign \dividend $65 [127:0]
+        end
+    end
     sync init
   end
-  process $group_11
-    assign \xer_so$19 1'0
-    assign \xer_so$19 \xer_so
+  process $group_10
+    assign \xer_so$20 1'0
+    assign \xer_so$20 \xer_so
     sync init
   end
-  process $group_12
+  process $group_11
     assign \muxid$1 2'00
     assign \muxid$1 \muxid
     sync init
   end
-  process $group_13
-    assign \mul_op__insn_type$2 7'0000000
-    assign \mul_op__fn_unit$3 11'00000000000
-    assign \mul_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \mul_op__imm_data__imm_ok$5 1'0
-    assign \mul_op__rc__rc$6 1'0
-    assign \mul_op__rc__rc_ok$7 1'0
-    assign \mul_op__oe__oe$8 1'0
-    assign \mul_op__oe__oe_ok$9 1'0
-    assign \mul_op__invert_a$10 1'0
-    assign \mul_op__zero_a$11 1'0
-    assign \mul_op__invert_out$12 1'0
-    assign \mul_op__write_cr0$13 1'0
-    assign \mul_op__is_32bit$14 1'0
-    assign \mul_op__is_signed$15 1'0
-    assign \mul_op__insn$16 32'00000000000000000000000000000000
-    assign { \mul_op__insn$16 \mul_op__is_signed$15 \mul_op__is_32bit$14 \mul_op__write_cr0$13 \mul_op__invert_out$12 \mul_op__zero_a$11 \mul_op__invert_a$10 { \mul_op__oe__oe_ok$9 \mul_op__oe__oe$8 } { \mul_op__rc__rc_ok$7 \mul_op__rc__rc$6 } { \mul_op__imm_data__imm_ok$5 \mul_op__imm_data__imm$4 } \mul_op__fn_unit$3 \mul_op__insn_type$2 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__invert_out \mul_op__zero_a \mul_op__invert_a { \mul_op__oe__oe_ok \mul_op__oe__oe } { \mul_op__rc__rc_ok \mul_op__rc__rc } { \mul_op__imm_data__imm_ok \mul_op__imm_data__imm } \mul_op__fn_unit \mul_op__insn_type }
+  process $group_12
+    assign \logical_op__insn_type$2 7'0000000
+    assign \logical_op__fn_unit$3 11'00000000000
+    assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \logical_op__imm_data__imm_ok$5 1'0
+    assign \logical_op__rc__rc$6 1'0
+    assign \logical_op__rc__rc_ok$7 1'0
+    assign \logical_op__oe__oe$8 1'0
+    assign \logical_op__oe__oe_ok$9 1'0
+    assign \logical_op__invert_a$10 1'0
+    assign \logical_op__zero_a$11 1'0
+    assign \logical_op__input_carry$12 2'00
+    assign \logical_op__invert_out$13 1'0
+    assign \logical_op__write_cr0$14 1'0
+    assign \logical_op__output_carry$15 1'0
+    assign \logical_op__is_32bit$16 1'0
+    assign \logical_op__is_signed$17 1'0
+    assign \logical_op__data_len$18 4'0000
+    assign \logical_op__insn$19 32'00000000000000000000000000000000
+    assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_a$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_a { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type }
     sync init
   end
 end
 attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe1"
-module \mul_pipe1
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
+attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_start"
+module \pipe_start
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
   wire width 1 output 2 \n_valid_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
@@ -89894,9 +89751,9 @@ module \mul_pipe1
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 7 output 5 \mul_op__insn_type
+  wire width 7 output 5 \logical_op__insn_type
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 7 \mul_op__insn_type$next
+  wire width 7 \logical_op__insn_type$next
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -89910,87 +89767,127 @@ module \mul_pipe1
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 11 output 6 \mul_op__fn_unit
+  wire width 11 output 6 \logical_op__fn_unit
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 11 \mul_op__fn_unit$next
+  wire width 11 \logical_op__fn_unit$next
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 64 output 7 \mul_op__imm_data__imm
+  wire width 64 output 7 \logical_op__imm_data__imm
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 64 \mul_op__imm_data__imm$next
+  wire width 64 \logical_op__imm_data__imm$next
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 8 \mul_op__imm_data__imm_ok
+  wire width 1 output 8 \logical_op__imm_data__imm_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_op__imm_data__imm_ok$next
+  wire width 1 \logical_op__imm_data__imm_ok$next
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 9 \mul_op__rc__rc
+  wire width 1 output 9 \logical_op__rc__rc
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_op__rc__rc$next
+  wire width 1 \logical_op__rc__rc$next
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 10 \mul_op__rc__rc_ok
+  wire width 1 output 10 \logical_op__rc__rc_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_op__rc__rc_ok$next
+  wire width 1 \logical_op__rc__rc_ok$next
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 11 \mul_op__oe__oe
+  wire width 1 output 11 \logical_op__oe__oe
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_op__oe__oe$next
+  wire width 1 \logical_op__oe__oe$next
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 12 \mul_op__oe__oe_ok
+  wire width 1 output 12 \logical_op__oe__oe_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_op__oe__oe_ok$next
+  wire width 1 \logical_op__oe__oe_ok$next
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 13 \mul_op__invert_a
+  wire width 1 output 13 \logical_op__invert_a
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_op__invert_a$next
+  wire width 1 \logical_op__invert_a$next
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 14 \mul_op__zero_a
+  wire width 1 output 14 \logical_op__zero_a
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_op__zero_a$next
+  wire width 1 \logical_op__zero_a$next
+  attribute \enum_base_type "CryIn"
+  attribute \enum_value_00 "ZERO"
+  attribute \enum_value_01 "ONE"
+  attribute \enum_value_10 "CA"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 15 \mul_op__invert_out
+  wire width 2 output 15 \logical_op__input_carry
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_op__invert_out$next
+  wire width 2 \logical_op__input_carry$next
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 16 \mul_op__write_cr0
+  wire width 1 output 16 \logical_op__invert_out
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_op__write_cr0$next
+  wire width 1 \logical_op__invert_out$next
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 17 \mul_op__is_32bit
+  wire width 1 output 17 \logical_op__write_cr0
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_op__is_32bit$next
+  wire width 1 \logical_op__write_cr0$next
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 18 \mul_op__is_signed
+  wire width 1 output 18 \logical_op__output_carry
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_op__is_signed$next
+  wire width 1 \logical_op__output_carry$next
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 32 output 19 \mul_op__insn
+  wire width 1 output 19 \logical_op__is_32bit
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 32 \mul_op__insn$next
+  wire width 1 \logical_op__is_32bit$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 20 \logical_op__is_signed
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \logical_op__is_signed$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 4 output 21 \logical_op__data_len
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 4 \logical_op__data_len$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 output 22 \logical_op__insn
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \logical_op__insn$next
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
-  wire width 64 output 20 \ra
+  wire width 64 output 23 \ra
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 \ra$next
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
-  wire width 64 output 21 \rb
+  wire width 64 output 24 \rb
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 \rb$next
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
-  wire width 1 output 22 \xer_so
+  wire width 1 output 25 \xer_so
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 1 \xer_so$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11"
-  wire width 1 output 23 \neg_res
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11"
-  wire width 1 \neg_res$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12"
-  wire width 1 output 24 \neg_res32
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12"
-  wire width 1 \neg_res32$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160"
+  wire width 1 output 26 \divisor_neg
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160"
+  wire width 1 \divisor_neg$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161"
+  wire width 1 output 27 \dividend_neg
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161"
+  wire width 1 \dividend_neg$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167"
+  wire width 1 output 28 \dive_abs_ov32
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167"
+  wire width 1 \dive_abs_ov32$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168"
+  wire width 1 output 29 \dive_abs_ov64
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168"
+  wire width 1 \dive_abs_ov64$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162"
+  wire width 1 output 30 \div_by_zero
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162"
+  wire width 1 \div_by_zero$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18"
+  wire width 128 output 31 \dividend
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18"
+  wire width 128 \dividend$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19"
+  wire width 64 output 32 \divisor_radicand
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19"
+  wire width 64 \divisor_radicand$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21"
+  wire width 2 output 33 \operation
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21"
+  wire width 2 \operation$next
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153"
-  wire width 1 input 25 \p_valid_i
+  wire width 1 input 34 \p_valid_i
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154"
-  wire width 1 output 26 \p_ready_o
+  wire width 1 output 35 \p_ready_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
-  wire width 2 input 27 \muxid$1
+  wire width 2 input 36 \muxid$1
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
   attribute \enum_value_0000001 "OP_NOP"
@@ -90065,7 +89962,7 @@ module \mul_pipe1
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 7 input 28 \mul_op__insn_type$2
+  wire width 7 input 37 \logical_op__insn_type$2
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -90079,39 +89976,49 @@ module \mul_pipe1
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 11 input 29 \mul_op__fn_unit$3
+  wire width 11 input 38 \logical_op__fn_unit$3
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 64 input 30 \mul_op__imm_data__imm$4
+  wire width 64 input 39 \logical_op__imm_data__imm$4
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 31 \mul_op__imm_data__imm_ok$5
+  wire width 1 input 40 \logical_op__imm_data__imm_ok$5
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 32 \mul_op__rc__rc$6
+  wire width 1 input 41 \logical_op__rc__rc$6
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 33 \mul_op__rc__rc_ok$7
+  wire width 1 input 42 \logical_op__rc__rc_ok$7
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 34 \mul_op__oe__oe$8
+  wire width 1 input 43 \logical_op__oe__oe$8
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 35 \mul_op__oe__oe_ok$9
+  wire width 1 input 44 \logical_op__oe__oe_ok$9
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 36 \mul_op__invert_a$10
+  wire width 1 input 45 \logical_op__invert_a$10
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 37 \mul_op__zero_a$11
+  wire width 1 input 46 \logical_op__zero_a$11
+  attribute \enum_base_type "CryIn"
+  attribute \enum_value_00 "ZERO"
+  attribute \enum_value_01 "ONE"
+  attribute \enum_value_10 "CA"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 38 \mul_op__invert_out$12
+  wire width 2 input 47 \logical_op__input_carry$12
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 39 \mul_op__write_cr0$13
+  wire width 1 input 48 \logical_op__invert_out$13
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 40 \mul_op__is_32bit$14
+  wire width 1 input 49 \logical_op__write_cr0$14
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 41 \mul_op__is_signed$15
+  wire width 1 input 50 \logical_op__output_carry$15
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 32 input 42 \mul_op__insn$16
+  wire width 1 input 51 \logical_op__is_32bit$16
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 52 \logical_op__is_signed$17
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 4 input 53 \logical_op__data_len$18
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 input 54 \logical_op__insn$19
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
-  wire width 64 input 43 \ra$17
+  wire width 64 input 55 \ra$20
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
-  wire width 64 input 44 \rb$18
+  wire width 64 input 56 \rb$21
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
-  wire width 1 input 45 \xer_so$19
+  wire width 1 input 57 \xer_so$22
   cell \p$72 \p
     connect \p_valid_i \p_valid_i
     connect \p_ready_o \p_ready_o
@@ -90196,7 +90103,7 @@ module \mul_pipe1
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 7 \input_mul_op__insn_type
+  wire width 7 \input_logical_op__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -90210,33 +90117,43 @@ module \mul_pipe1
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 11 \input_mul_op__fn_unit
+  wire width 11 \input_logical_op__fn_unit
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 64 \input_mul_op__imm_data__imm
+  wire width 64 \input_logical_op__imm_data__imm
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \input_mul_op__imm_data__imm_ok
+  wire width 1 \input_logical_op__imm_data__imm_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \input_mul_op__rc__rc
+  wire width 1 \input_logical_op__rc__rc
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \input_mul_op__rc__rc_ok
+  wire width 1 \input_logical_op__rc__rc_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \input_mul_op__oe__oe
+  wire width 1 \input_logical_op__oe__oe
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \input_mul_op__oe__oe_ok
+  wire width 1 \input_logical_op__oe__oe_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \input_mul_op__invert_a
+  wire width 1 \input_logical_op__invert_a
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \input_mul_op__zero_a
+  wire width 1 \input_logical_op__zero_a
+  attribute \enum_base_type "CryIn"
+  attribute \enum_value_00 "ZERO"
+  attribute \enum_value_01 "ONE"
+  attribute \enum_value_10 "CA"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \input_mul_op__invert_out
+  wire width 2 \input_logical_op__input_carry
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \input_mul_op__write_cr0
+  wire width 1 \input_logical_op__invert_out
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \input_mul_op__is_32bit
+  wire width 1 \input_logical_op__write_cr0
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \input_mul_op__is_signed
+  wire width 1 \input_logical_op__output_carry
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 32 \input_mul_op__insn
+  wire width 1 \input_logical_op__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \input_logical_op__is_signed
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 4 \input_logical_op__data_len
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \input_logical_op__insn
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 64 \input_ra
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
@@ -90244,7 +90161,7 @@ module \mul_pipe1
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
   wire width 1 \input_xer_so
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
-  wire width 2 \input_muxid$20
+  wire width 2 \input_muxid$23
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
   attribute \enum_value_0000001 "OP_NOP"
@@ -90319,7 +90236,7 @@ module \mul_pipe1
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 7 \input_mul_op__insn_type$21
+  wire width 7 \input_logical_op__insn_type$24
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -90333,81 +90250,97 @@ module \mul_pipe1
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 11 \input_mul_op__fn_unit$22
+  wire width 11 \input_logical_op__fn_unit$25
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 64 \input_mul_op__imm_data__imm$23
+  wire width 64 \input_logical_op__imm_data__imm$26
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \input_mul_op__imm_data__imm_ok$24
+  wire width 1 \input_logical_op__imm_data__imm_ok$27
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \input_mul_op__rc__rc$25
+  wire width 1 \input_logical_op__rc__rc$28
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \input_mul_op__rc__rc_ok$26
+  wire width 1 \input_logical_op__rc__rc_ok$29
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \input_mul_op__oe__oe$27
+  wire width 1 \input_logical_op__oe__oe$30
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \input_mul_op__oe__oe_ok$28
+  wire width 1 \input_logical_op__oe__oe_ok$31
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \input_mul_op__invert_a$29
+  wire width 1 \input_logical_op__invert_a$32
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \input_mul_op__zero_a$30
+  wire width 1 \input_logical_op__zero_a$33
+  attribute \enum_base_type "CryIn"
+  attribute \enum_value_00 "ZERO"
+  attribute \enum_value_01 "ONE"
+  attribute \enum_value_10 "CA"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \input_mul_op__invert_out$31
+  wire width 2 \input_logical_op__input_carry$34
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \input_mul_op__write_cr0$32
+  wire width 1 \input_logical_op__invert_out$35
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \input_mul_op__is_32bit$33
+  wire width 1 \input_logical_op__write_cr0$36
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \input_mul_op__is_signed$34
+  wire width 1 \input_logical_op__output_carry$37
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 32 \input_mul_op__insn$35
+  wire width 1 \input_logical_op__is_32bit$38
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \input_logical_op__is_signed$39
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 4 \input_logical_op__data_len$40
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \input_logical_op__insn$41
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
-  wire width 64 \input_ra$36
+  wire width 64 \input_ra$42
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
-  wire width 64 \input_rb$37
+  wire width 64 \input_rb$43
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
-  wire width 1 \input_xer_so$38
+  wire width 1 \input_xer_so$44
   cell \input$74 \input
     connect \muxid \input_muxid
-    connect \mul_op__insn_type \input_mul_op__insn_type
-    connect \mul_op__fn_unit \input_mul_op__fn_unit
-    connect \mul_op__imm_data__imm \input_mul_op__imm_data__imm
-    connect \mul_op__imm_data__imm_ok \input_mul_op__imm_data__imm_ok
-    connect \mul_op__rc__rc \input_mul_op__rc__rc
-    connect \mul_op__rc__rc_ok \input_mul_op__rc__rc_ok
-    connect \mul_op__oe__oe \input_mul_op__oe__oe
-    connect \mul_op__oe__oe_ok \input_mul_op__oe__oe_ok
-    connect \mul_op__invert_a \input_mul_op__invert_a
-    connect \mul_op__zero_a \input_mul_op__zero_a
-    connect \mul_op__invert_out \input_mul_op__invert_out
-    connect \mul_op__write_cr0 \input_mul_op__write_cr0
-    connect \mul_op__is_32bit \input_mul_op__is_32bit
-    connect \mul_op__is_signed \input_mul_op__is_signed
-    connect \mul_op__insn \input_mul_op__insn
+    connect \logical_op__insn_type \input_logical_op__insn_type
+    connect \logical_op__fn_unit \input_logical_op__fn_unit
+    connect \logical_op__imm_data__imm \input_logical_op__imm_data__imm
+    connect \logical_op__imm_data__imm_ok \input_logical_op__imm_data__imm_ok
+    connect \logical_op__rc__rc \input_logical_op__rc__rc
+    connect \logical_op__rc__rc_ok \input_logical_op__rc__rc_ok
+    connect \logical_op__oe__oe \input_logical_op__oe__oe
+    connect \logical_op__oe__oe_ok \input_logical_op__oe__oe_ok
+    connect \logical_op__invert_a \input_logical_op__invert_a
+    connect \logical_op__zero_a \input_logical_op__zero_a
+    connect \logical_op__input_carry \input_logical_op__input_carry
+    connect \logical_op__invert_out \input_logical_op__invert_out
+    connect \logical_op__write_cr0 \input_logical_op__write_cr0
+    connect \logical_op__output_carry \input_logical_op__output_carry
+    connect \logical_op__is_32bit \input_logical_op__is_32bit
+    connect \logical_op__is_signed \input_logical_op__is_signed
+    connect \logical_op__data_len \input_logical_op__data_len
+    connect \logical_op__insn \input_logical_op__insn
     connect \ra \input_ra
     connect \rb \input_rb
     connect \xer_so \input_xer_so
-    connect \muxid$1 \input_muxid$20
-    connect \mul_op__insn_type$2 \input_mul_op__insn_type$21
-    connect \mul_op__fn_unit$3 \input_mul_op__fn_unit$22
-    connect \mul_op__imm_data__imm$4 \input_mul_op__imm_data__imm$23
-    connect \mul_op__imm_data__imm_ok$5 \input_mul_op__imm_data__imm_ok$24
-    connect \mul_op__rc__rc$6 \input_mul_op__rc__rc$25
-    connect \mul_op__rc__rc_ok$7 \input_mul_op__rc__rc_ok$26
-    connect \mul_op__oe__oe$8 \input_mul_op__oe__oe$27
-    connect \mul_op__oe__oe_ok$9 \input_mul_op__oe__oe_ok$28
-    connect \mul_op__invert_a$10 \input_mul_op__invert_a$29
-    connect \mul_op__zero_a$11 \input_mul_op__zero_a$30
-    connect \mul_op__invert_out$12 \input_mul_op__invert_out$31
-    connect \mul_op__write_cr0$13 \input_mul_op__write_cr0$32
-    connect \mul_op__is_32bit$14 \input_mul_op__is_32bit$33
-    connect \mul_op__is_signed$15 \input_mul_op__is_signed$34
-    connect \mul_op__insn$16 \input_mul_op__insn$35
-    connect \ra$17 \input_ra$36
-    connect \rb$18 \input_rb$37
-    connect \xer_so$19 \input_xer_so$38
+    connect \muxid$1 \input_muxid$23
+    connect \logical_op__insn_type$2 \input_logical_op__insn_type$24
+    connect \logical_op__fn_unit$3 \input_logical_op__fn_unit$25
+    connect \logical_op__imm_data__imm$4 \input_logical_op__imm_data__imm$26
+    connect \logical_op__imm_data__imm_ok$5 \input_logical_op__imm_data__imm_ok$27
+    connect \logical_op__rc__rc$6 \input_logical_op__rc__rc$28
+    connect \logical_op__rc__rc_ok$7 \input_logical_op__rc__rc_ok$29
+    connect \logical_op__oe__oe$8 \input_logical_op__oe__oe$30
+    connect \logical_op__oe__oe_ok$9 \input_logical_op__oe__oe_ok$31
+    connect \logical_op__invert_a$10 \input_logical_op__invert_a$32
+    connect \logical_op__zero_a$11 \input_logical_op__zero_a$33
+    connect \logical_op__input_carry$12 \input_logical_op__input_carry$34
+    connect \logical_op__invert_out$13 \input_logical_op__invert_out$35
+    connect \logical_op__write_cr0$14 \input_logical_op__write_cr0$36
+    connect \logical_op__output_carry$15 \input_logical_op__output_carry$37
+    connect \logical_op__is_32bit$16 \input_logical_op__is_32bit$38
+    connect \logical_op__is_signed$17 \input_logical_op__is_signed$39
+    connect \logical_op__data_len$18 \input_logical_op__data_len$40
+    connect \logical_op__insn$19 \input_logical_op__insn$41
+    connect \ra$20 \input_ra$42
+    connect \rb$21 \input_rb$43
+    connect \xer_so$22 \input_xer_so$44
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
-  wire width 2 \mul1_muxid
+  wire width 2 \setup_stage_muxid
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
   attribute \enum_value_0000001 "OP_NOP"
@@ -90482,7 +90415,7 @@ module \mul_pipe1
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 7 \mul1_mul_op__insn_type
+  wire width 7 \setup_stage_logical_op__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -90496,41 +90429,51 @@ module \mul_pipe1
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 11 \mul1_mul_op__fn_unit
+  wire width 11 \setup_stage_logical_op__fn_unit
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 64 \mul1_mul_op__imm_data__imm
+  wire width 64 \setup_stage_logical_op__imm_data__imm
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul1_mul_op__imm_data__imm_ok
+  wire width 1 \setup_stage_logical_op__imm_data__imm_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul1_mul_op__rc__rc
+  wire width 1 \setup_stage_logical_op__rc__rc
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul1_mul_op__rc__rc_ok
+  wire width 1 \setup_stage_logical_op__rc__rc_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul1_mul_op__oe__oe
+  wire width 1 \setup_stage_logical_op__oe__oe
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul1_mul_op__oe__oe_ok
+  wire width 1 \setup_stage_logical_op__oe__oe_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul1_mul_op__invert_a
+  wire width 1 \setup_stage_logical_op__invert_a
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul1_mul_op__zero_a
+  wire width 1 \setup_stage_logical_op__zero_a
+  attribute \enum_base_type "CryIn"
+  attribute \enum_value_00 "ZERO"
+  attribute \enum_value_01 "ONE"
+  attribute \enum_value_10 "CA"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul1_mul_op__invert_out
+  wire width 2 \setup_stage_logical_op__input_carry
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul1_mul_op__write_cr0
+  wire width 1 \setup_stage_logical_op__invert_out
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul1_mul_op__is_32bit
+  wire width 1 \setup_stage_logical_op__write_cr0
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul1_mul_op__is_signed
+  wire width 1 \setup_stage_logical_op__output_carry
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 32 \mul1_mul_op__insn
+  wire width 1 \setup_stage_logical_op__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \setup_stage_logical_op__is_signed
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 4 \setup_stage_logical_op__data_len
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \setup_stage_logical_op__insn
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
-  wire width 64 \mul1_ra
+  wire width 64 \setup_stage_ra
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
-  wire width 64 \mul1_rb
+  wire width 64 \setup_stage_rb
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
-  wire width 1 \mul1_xer_so
+  wire width 1 \setup_stage_xer_so
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
-  wire width 2 \mul1_muxid$39
+  wire width 2 \setup_stage_muxid$45
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
   attribute \enum_value_0000001 "OP_NOP"
@@ -90605,7 +90548,7 @@ module \mul_pipe1
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 7 \mul1_mul_op__insn_type$40
+  wire width 7 \setup_stage_logical_op__insn_type$46
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -90619,84 +90562,112 @@ module \mul_pipe1
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 11 \mul1_mul_op__fn_unit$41
+  wire width 11 \setup_stage_logical_op__fn_unit$47
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 64 \mul1_mul_op__imm_data__imm$42
+  wire width 64 \setup_stage_logical_op__imm_data__imm$48
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul1_mul_op__imm_data__imm_ok$43
+  wire width 1 \setup_stage_logical_op__imm_data__imm_ok$49
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul1_mul_op__rc__rc$44
+  wire width 1 \setup_stage_logical_op__rc__rc$50
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul1_mul_op__rc__rc_ok$45
+  wire width 1 \setup_stage_logical_op__rc__rc_ok$51
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul1_mul_op__oe__oe$46
+  wire width 1 \setup_stage_logical_op__oe__oe$52
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul1_mul_op__oe__oe_ok$47
+  wire width 1 \setup_stage_logical_op__oe__oe_ok$53
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul1_mul_op__invert_a$48
+  wire width 1 \setup_stage_logical_op__invert_a$54
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul1_mul_op__zero_a$49
+  wire width 1 \setup_stage_logical_op__zero_a$55
+  attribute \enum_base_type "CryIn"
+  attribute \enum_value_00 "ZERO"
+  attribute \enum_value_01 "ONE"
+  attribute \enum_value_10 "CA"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul1_mul_op__invert_out$50
+  wire width 2 \setup_stage_logical_op__input_carry$56
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul1_mul_op__write_cr0$51
+  wire width 1 \setup_stage_logical_op__invert_out$57
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul1_mul_op__is_32bit$52
+  wire width 1 \setup_stage_logical_op__write_cr0$58
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul1_mul_op__is_signed$53
+  wire width 1 \setup_stage_logical_op__output_carry$59
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 32 \mul1_mul_op__insn$54
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
-  wire width 64 \mul1_ra$55
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
-  wire width 64 \mul1_rb$56
+  wire width 1 \setup_stage_logical_op__is_32bit$60
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \setup_stage_logical_op__is_signed$61
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 4 \setup_stage_logical_op__data_len$62
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \setup_stage_logical_op__insn$63
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
-  wire width 1 \mul1_xer_so$57
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11"
-  wire width 1 \mul1_neg_res
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12"
-  wire width 1 \mul1_neg_res32
-  cell \mul1 \mul1
-    connect \muxid \mul1_muxid
-    connect \mul_op__insn_type \mul1_mul_op__insn_type
-    connect \mul_op__fn_unit \mul1_mul_op__fn_unit
-    connect \mul_op__imm_data__imm \mul1_mul_op__imm_data__imm
-    connect \mul_op__imm_data__imm_ok \mul1_mul_op__imm_data__imm_ok
-    connect \mul_op__rc__rc \mul1_mul_op__rc__rc
-    connect \mul_op__rc__rc_ok \mul1_mul_op__rc__rc_ok
-    connect \mul_op__oe__oe \mul1_mul_op__oe__oe
-    connect \mul_op__oe__oe_ok \mul1_mul_op__oe__oe_ok
-    connect \mul_op__invert_a \mul1_mul_op__invert_a
-    connect \mul_op__zero_a \mul1_mul_op__zero_a
-    connect \mul_op__invert_out \mul1_mul_op__invert_out
-    connect \mul_op__write_cr0 \mul1_mul_op__write_cr0
-    connect \mul_op__is_32bit \mul1_mul_op__is_32bit
-    connect \mul_op__is_signed \mul1_mul_op__is_signed
-    connect \mul_op__insn \mul1_mul_op__insn
-    connect \ra \mul1_ra
-    connect \rb \mul1_rb
-    connect \xer_so \mul1_xer_so
-    connect \muxid$1 \mul1_muxid$39
-    connect \mul_op__insn_type$2 \mul1_mul_op__insn_type$40
-    connect \mul_op__fn_unit$3 \mul1_mul_op__fn_unit$41
-    connect \mul_op__imm_data__imm$4 \mul1_mul_op__imm_data__imm$42
-    connect \mul_op__imm_data__imm_ok$5 \mul1_mul_op__imm_data__imm_ok$43
-    connect \mul_op__rc__rc$6 \mul1_mul_op__rc__rc$44
-    connect \mul_op__rc__rc_ok$7 \mul1_mul_op__rc__rc_ok$45
-    connect \mul_op__oe__oe$8 \mul1_mul_op__oe__oe$46
-    connect \mul_op__oe__oe_ok$9 \mul1_mul_op__oe__oe_ok$47
-    connect \mul_op__invert_a$10 \mul1_mul_op__invert_a$48
-    connect \mul_op__zero_a$11 \mul1_mul_op__zero_a$49
-    connect \mul_op__invert_out$12 \mul1_mul_op__invert_out$50
-    connect \mul_op__write_cr0$13 \mul1_mul_op__write_cr0$51
-    connect \mul_op__is_32bit$14 \mul1_mul_op__is_32bit$52
-    connect \mul_op__is_signed$15 \mul1_mul_op__is_signed$53
-    connect \mul_op__insn$16 \mul1_mul_op__insn$54
-    connect \ra$17 \mul1_ra$55
-    connect \rb$18 \mul1_rb$56
-    connect \xer_so$19 \mul1_xer_so$57
-    connect \neg_res \mul1_neg_res
-    connect \neg_res32 \mul1_neg_res32
+  wire width 1 \setup_stage_xer_so$64
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160"
+  wire width 1 \setup_stage_divisor_neg
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161"
+  wire width 1 \setup_stage_dividend_neg
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167"
+  wire width 1 \setup_stage_dive_abs_ov32
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168"
+  wire width 1 \setup_stage_dive_abs_ov64
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162"
+  wire width 1 \setup_stage_div_by_zero
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18"
+  wire width 128 \setup_stage_dividend
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19"
+  wire width 64 \setup_stage_divisor_radicand
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21"
+  wire width 2 \setup_stage_operation
+  cell \setup_stage \setup_stage
+    connect \muxid \setup_stage_muxid
+    connect \logical_op__insn_type \setup_stage_logical_op__insn_type
+    connect \logical_op__fn_unit \setup_stage_logical_op__fn_unit
+    connect \logical_op__imm_data__imm \setup_stage_logical_op__imm_data__imm
+    connect \logical_op__imm_data__imm_ok \setup_stage_logical_op__imm_data__imm_ok
+    connect \logical_op__rc__rc \setup_stage_logical_op__rc__rc
+    connect \logical_op__rc__rc_ok \setup_stage_logical_op__rc__rc_ok
+    connect \logical_op__oe__oe \setup_stage_logical_op__oe__oe
+    connect \logical_op__oe__oe_ok \setup_stage_logical_op__oe__oe_ok
+    connect \logical_op__invert_a \setup_stage_logical_op__invert_a
+    connect \logical_op__zero_a \setup_stage_logical_op__zero_a
+    connect \logical_op__input_carry \setup_stage_logical_op__input_carry
+    connect \logical_op__invert_out \setup_stage_logical_op__invert_out
+    connect \logical_op__write_cr0 \setup_stage_logical_op__write_cr0
+    connect \logical_op__output_carry \setup_stage_logical_op__output_carry
+    connect \logical_op__is_32bit \setup_stage_logical_op__is_32bit
+    connect \logical_op__is_signed \setup_stage_logical_op__is_signed
+    connect \logical_op__data_len \setup_stage_logical_op__data_len
+    connect \logical_op__insn \setup_stage_logical_op__insn
+    connect \ra \setup_stage_ra
+    connect \rb \setup_stage_rb
+    connect \xer_so \setup_stage_xer_so
+    connect \muxid$1 \setup_stage_muxid$45
+    connect \logical_op__insn_type$2 \setup_stage_logical_op__insn_type$46
+    connect \logical_op__fn_unit$3 \setup_stage_logical_op__fn_unit$47
+    connect \logical_op__imm_data__imm$4 \setup_stage_logical_op__imm_data__imm$48
+    connect \logical_op__imm_data__imm_ok$5 \setup_stage_logical_op__imm_data__imm_ok$49
+    connect \logical_op__rc__rc$6 \setup_stage_logical_op__rc__rc$50
+    connect \logical_op__rc__rc_ok$7 \setup_stage_logical_op__rc__rc_ok$51
+    connect \logical_op__oe__oe$8 \setup_stage_logical_op__oe__oe$52
+    connect \logical_op__oe__oe_ok$9 \setup_stage_logical_op__oe__oe_ok$53
+    connect \logical_op__invert_a$10 \setup_stage_logical_op__invert_a$54
+    connect \logical_op__zero_a$11 \setup_stage_logical_op__zero_a$55
+    connect \logical_op__input_carry$12 \setup_stage_logical_op__input_carry$56
+    connect \logical_op__invert_out$13 \setup_stage_logical_op__invert_out$57
+    connect \logical_op__write_cr0$14 \setup_stage_logical_op__write_cr0$58
+    connect \logical_op__output_carry$15 \setup_stage_logical_op__output_carry$59
+    connect \logical_op__is_32bit$16 \setup_stage_logical_op__is_32bit$60
+    connect \logical_op__is_signed$17 \setup_stage_logical_op__is_signed$61
+    connect \logical_op__data_len$18 \setup_stage_logical_op__data_len$62
+    connect \logical_op__insn$19 \setup_stage_logical_op__insn$63
+    connect \xer_so$20 \setup_stage_xer_so$64
+    connect \divisor_neg \setup_stage_divisor_neg
+    connect \dividend_neg \setup_stage_dividend_neg
+    connect \dive_abs_ov32 \setup_stage_dive_abs_ov32
+    connect \dive_abs_ov64 \setup_stage_dive_abs_ov64
+    connect \div_by_zero \setup_stage_div_by_zero
+    connect \dividend \setup_stage_dividend
+    connect \divisor_radicand \setup_stage_divisor_radicand
+    connect \operation \setup_stage_operation
   end
   process $group_0
     assign \input_muxid 2'00
@@ -90704,88 +90675,94 @@ module \mul_pipe1
     sync init
   end
   process $group_1
-    assign \input_mul_op__insn_type 7'0000000
-    assign \input_mul_op__fn_unit 11'00000000000
-    assign \input_mul_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \input_mul_op__imm_data__imm_ok 1'0
-    assign \input_mul_op__rc__rc 1'0
-    assign \input_mul_op__rc__rc_ok 1'0
-    assign \input_mul_op__oe__oe 1'0
-    assign \input_mul_op__oe__oe_ok 1'0
-    assign \input_mul_op__invert_a 1'0
-    assign \input_mul_op__zero_a 1'0
-    assign \input_mul_op__invert_out 1'0
-    assign \input_mul_op__write_cr0 1'0
-    assign \input_mul_op__is_32bit 1'0
-    assign \input_mul_op__is_signed 1'0
-    assign \input_mul_op__insn 32'00000000000000000000000000000000
-    assign { \input_mul_op__insn \input_mul_op__is_signed \input_mul_op__is_32bit \input_mul_op__write_cr0 \input_mul_op__invert_out \input_mul_op__zero_a \input_mul_op__invert_a { \input_mul_op__oe__oe_ok \input_mul_op__oe__oe } { \input_mul_op__rc__rc_ok \input_mul_op__rc__rc } { \input_mul_op__imm_data__imm_ok \input_mul_op__imm_data__imm } \input_mul_op__fn_unit \input_mul_op__insn_type } { \mul_op__insn$16 \mul_op__is_signed$15 \mul_op__is_32bit$14 \mul_op__write_cr0$13 \mul_op__invert_out$12 \mul_op__zero_a$11 \mul_op__invert_a$10 { \mul_op__oe__oe_ok$9 \mul_op__oe__oe$8 } { \mul_op__rc__rc_ok$7 \mul_op__rc__rc$6 } { \mul_op__imm_data__imm_ok$5 \mul_op__imm_data__imm$4 } \mul_op__fn_unit$3 \mul_op__insn_type$2 }
+    assign \input_logical_op__insn_type 7'0000000
+    assign \input_logical_op__fn_unit 11'00000000000
+    assign \input_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \input_logical_op__imm_data__imm_ok 1'0
+    assign \input_logical_op__rc__rc 1'0
+    assign \input_logical_op__rc__rc_ok 1'0
+    assign \input_logical_op__oe__oe 1'0
+    assign \input_logical_op__oe__oe_ok 1'0
+    assign \input_logical_op__invert_a 1'0
+    assign \input_logical_op__zero_a 1'0
+    assign \input_logical_op__input_carry 2'00
+    assign \input_logical_op__invert_out 1'0
+    assign \input_logical_op__write_cr0 1'0
+    assign \input_logical_op__output_carry 1'0
+    assign \input_logical_op__is_32bit 1'0
+    assign \input_logical_op__is_signed 1'0
+    assign \input_logical_op__data_len 4'0000
+    assign \input_logical_op__insn 32'00000000000000000000000000000000
+    assign { \input_logical_op__insn \input_logical_op__data_len \input_logical_op__is_signed \input_logical_op__is_32bit \input_logical_op__output_carry \input_logical_op__write_cr0 \input_logical_op__invert_out \input_logical_op__input_carry \input_logical_op__zero_a \input_logical_op__invert_a { \input_logical_op__oe__oe_ok \input_logical_op__oe__oe } { \input_logical_op__rc__rc_ok \input_logical_op__rc__rc } { \input_logical_op__imm_data__imm_ok \input_logical_op__imm_data__imm } \input_logical_op__fn_unit \input_logical_op__insn_type } { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_a$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 }
     sync init
   end
-  process $group_16
+  process $group_19
     assign \input_ra 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \input_ra \ra$17
+    assign \input_ra \ra$20
     sync init
   end
-  process $group_17
+  process $group_20
     assign \input_rb 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \input_rb \rb$18
+    assign \input_rb \rb$21
     sync init
   end
-  process $group_18
+  process $group_21
     assign \input_xer_so 1'0
-    assign \input_xer_so \xer_so$19
+    assign \input_xer_so \xer_so$22
     sync init
   end
-  process $group_19
-    assign \mul1_muxid 2'00
-    assign \mul1_muxid \input_muxid$20
+  process $group_22
+    assign \setup_stage_muxid 2'00
+    assign \setup_stage_muxid \input_muxid$23
     sync init
   end
-  process $group_20
-    assign \mul1_mul_op__insn_type 7'0000000
-    assign \mul1_mul_op__fn_unit 11'00000000000
-    assign \mul1_mul_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \mul1_mul_op__imm_data__imm_ok 1'0
-    assign \mul1_mul_op__rc__rc 1'0
-    assign \mul1_mul_op__rc__rc_ok 1'0
-    assign \mul1_mul_op__oe__oe 1'0
-    assign \mul1_mul_op__oe__oe_ok 1'0
-    assign \mul1_mul_op__invert_a 1'0
-    assign \mul1_mul_op__zero_a 1'0
-    assign \mul1_mul_op__invert_out 1'0
-    assign \mul1_mul_op__write_cr0 1'0
-    assign \mul1_mul_op__is_32bit 1'0
-    assign \mul1_mul_op__is_signed 1'0
-    assign \mul1_mul_op__insn 32'00000000000000000000000000000000
-    assign { \mul1_mul_op__insn \mul1_mul_op__is_signed \mul1_mul_op__is_32bit \mul1_mul_op__write_cr0 \mul1_mul_op__invert_out \mul1_mul_op__zero_a \mul1_mul_op__invert_a { \mul1_mul_op__oe__oe_ok \mul1_mul_op__oe__oe } { \mul1_mul_op__rc__rc_ok \mul1_mul_op__rc__rc } { \mul1_mul_op__imm_data__imm_ok \mul1_mul_op__imm_data__imm } \mul1_mul_op__fn_unit \mul1_mul_op__insn_type } { \input_mul_op__insn$35 \input_mul_op__is_signed$34 \input_mul_op__is_32bit$33 \input_mul_op__write_cr0$32 \input_mul_op__invert_out$31 \input_mul_op__zero_a$30 \input_mul_op__invert_a$29 { \input_mul_op__oe__oe_ok$28 \input_mul_op__oe__oe$27 } { \input_mul_op__rc__rc_ok$26 \input_mul_op__rc__rc$25 } { \input_mul_op__imm_data__imm_ok$24 \input_mul_op__imm_data__imm$23 } \input_mul_op__fn_unit$22 \input_mul_op__insn_type$21 }
+  process $group_23
+    assign \setup_stage_logical_op__insn_type 7'0000000
+    assign \setup_stage_logical_op__fn_unit 11'00000000000
+    assign \setup_stage_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \setup_stage_logical_op__imm_data__imm_ok 1'0
+    assign \setup_stage_logical_op__rc__rc 1'0
+    assign \setup_stage_logical_op__rc__rc_ok 1'0
+    assign \setup_stage_logical_op__oe__oe 1'0
+    assign \setup_stage_logical_op__oe__oe_ok 1'0
+    assign \setup_stage_logical_op__invert_a 1'0
+    assign \setup_stage_logical_op__zero_a 1'0
+    assign \setup_stage_logical_op__input_carry 2'00
+    assign \setup_stage_logical_op__invert_out 1'0
+    assign \setup_stage_logical_op__write_cr0 1'0
+    assign \setup_stage_logical_op__output_carry 1'0
+    assign \setup_stage_logical_op__is_32bit 1'0
+    assign \setup_stage_logical_op__is_signed 1'0
+    assign \setup_stage_logical_op__data_len 4'0000
+    assign \setup_stage_logical_op__insn 32'00000000000000000000000000000000
+    assign { \setup_stage_logical_op__insn \setup_stage_logical_op__data_len \setup_stage_logical_op__is_signed \setup_stage_logical_op__is_32bit \setup_stage_logical_op__output_carry \setup_stage_logical_op__write_cr0 \setup_stage_logical_op__invert_out \setup_stage_logical_op__input_carry \setup_stage_logical_op__zero_a \setup_stage_logical_op__invert_a { \setup_stage_logical_op__oe__oe_ok \setup_stage_logical_op__oe__oe } { \setup_stage_logical_op__rc__rc_ok \setup_stage_logical_op__rc__rc } { \setup_stage_logical_op__imm_data__imm_ok \setup_stage_logical_op__imm_data__imm } \setup_stage_logical_op__fn_unit \setup_stage_logical_op__insn_type } { \input_logical_op__insn$41 \input_logical_op__data_len$40 \input_logical_op__is_signed$39 \input_logical_op__is_32bit$38 \input_logical_op__output_carry$37 \input_logical_op__write_cr0$36 \input_logical_op__invert_out$35 \input_logical_op__input_carry$34 \input_logical_op__zero_a$33 \input_logical_op__invert_a$32 { \input_logical_op__oe__oe_ok$31 \input_logical_op__oe__oe$30 } { \input_logical_op__rc__rc_ok$29 \input_logical_op__rc__rc$28 } { \input_logical_op__imm_data__imm_ok$27 \input_logical_op__imm_data__imm$26 } \input_logical_op__fn_unit$25 \input_logical_op__insn_type$24 }
     sync init
   end
-  process $group_35
-    assign \mul1_ra 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \mul1_ra \input_ra$36
+  process $group_41
+    assign \setup_stage_ra 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \setup_stage_ra \input_ra$42
     sync init
   end
-  process $group_36
-    assign \mul1_rb 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \mul1_rb \input_rb$37
+  process $group_42
+    assign \setup_stage_rb 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \setup_stage_rb \input_rb$43
     sync init
   end
-  process $group_37
-    assign \mul1_xer_so 1'0
-    assign \mul1_xer_so \input_xer_so$38
+  process $group_43
+    assign \setup_stage_xer_so 1'0
+    assign \setup_stage_xer_so \input_xer_so$44
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621"
-  wire width 1 \p_valid_i$58
-  process $group_38
-    assign \p_valid_i$58 1'0
-    assign \p_valid_i$58 \p_valid_i
+  wire width 1 \p_valid_i$65
+  process $group_44
+    assign \p_valid_i$65 1'0
+    assign \p_valid_i$65 \p_valid_i
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619"
   wire width 1 \n_i_rdy_data
-  process $group_39
+  process $group_45
     assign \n_i_rdy_data 1'0
     assign \n_i_rdy_data \n_ready_i
     sync init
@@ -90793,28 +90770,28 @@ module \mul_pipe1
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620"
   wire width 1 \p_valid_i_p_ready_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624"
-  wire width 1 $59
+  wire width 1 $66
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624"
-  cell $and $60
+  cell $and $67
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \p_valid_i$58
+    connect \A \p_valid_i$65
     connect \B \p_ready_o
-    connect \Y $59
+    connect \Y $66
   end
-  process $group_40
+  process $group_46
     assign \p_valid_i_p_ready_o 1'0
-    assign \p_valid_i_p_ready_o $59
+    assign \p_valid_i_p_ready_o $66
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
-  wire width 2 \muxid$61
-  process $group_41
-    assign \muxid$61 2'00
-    assign \muxid$61 \mul1_muxid$39
+  wire width 2 \muxid$68
+  process $group_47
+    assign \muxid$68 2'00
+    assign \muxid$68 \setup_stage_muxid$45
     sync init
   end
   attribute \enum_base_type "MicrOp"
@@ -90891,7 +90868,7 @@ module \mul_pipe1
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 7 \mul_op__insn_type$62
+  wire width 7 \logical_op__insn_type$69
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -90905,92 +90882,151 @@ module \mul_pipe1
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 11 \mul_op__fn_unit$63
+  wire width 11 \logical_op__fn_unit$70
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 64 \mul_op__imm_data__imm$64
+  wire width 64 \logical_op__imm_data__imm$71
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_op__imm_data__imm_ok$65
+  wire width 1 \logical_op__imm_data__imm_ok$72
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_op__rc__rc$66
+  wire width 1 \logical_op__rc__rc$73
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_op__rc__rc_ok$67
+  wire width 1 \logical_op__rc__rc_ok$74
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_op__oe__oe$68
+  wire width 1 \logical_op__oe__oe$75
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_op__oe__oe_ok$69
+  wire width 1 \logical_op__oe__oe_ok$76
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_op__invert_a$70
+  wire width 1 \logical_op__invert_a$77
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_op__zero_a$71
+  wire width 1 \logical_op__zero_a$78
+  attribute \enum_base_type "CryIn"
+  attribute \enum_value_00 "ZERO"
+  attribute \enum_value_01 "ONE"
+  attribute \enum_value_10 "CA"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_op__invert_out$72
+  wire width 2 \logical_op__input_carry$79
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_op__write_cr0$73
+  wire width 1 \logical_op__invert_out$80
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_op__is_32bit$74
+  wire width 1 \logical_op__write_cr0$81
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_op__is_signed$75
+  wire width 1 \logical_op__output_carry$82
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 32 \mul_op__insn$76
-  process $group_42
-    assign \mul_op__insn_type$62 7'0000000
-    assign \mul_op__fn_unit$63 11'00000000000
-    assign \mul_op__imm_data__imm$64 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \mul_op__imm_data__imm_ok$65 1'0
-    assign \mul_op__rc__rc$66 1'0
-    assign \mul_op__rc__rc_ok$67 1'0
-    assign \mul_op__oe__oe$68 1'0
-    assign \mul_op__oe__oe_ok$69 1'0
-    assign \mul_op__invert_a$70 1'0
-    assign \mul_op__zero_a$71 1'0
-    assign \mul_op__invert_out$72 1'0
-    assign \mul_op__write_cr0$73 1'0
-    assign \mul_op__is_32bit$74 1'0
-    assign \mul_op__is_signed$75 1'0
-    assign \mul_op__insn$76 32'00000000000000000000000000000000
-    assign { \mul_op__insn$76 \mul_op__is_signed$75 \mul_op__is_32bit$74 \mul_op__write_cr0$73 \mul_op__invert_out$72 \mul_op__zero_a$71 \mul_op__invert_a$70 { \mul_op__oe__oe_ok$69 \mul_op__oe__oe$68 } { \mul_op__rc__rc_ok$67 \mul_op__rc__rc$66 } { \mul_op__imm_data__imm_ok$65 \mul_op__imm_data__imm$64 } \mul_op__fn_unit$63 \mul_op__insn_type$62 } { \mul1_mul_op__insn$54 \mul1_mul_op__is_signed$53 \mul1_mul_op__is_32bit$52 \mul1_mul_op__write_cr0$51 \mul1_mul_op__invert_out$50 \mul1_mul_op__zero_a$49 \mul1_mul_op__invert_a$48 { \mul1_mul_op__oe__oe_ok$47 \mul1_mul_op__oe__oe$46 } { \mul1_mul_op__rc__rc_ok$45 \mul1_mul_op__rc__rc$44 } { \mul1_mul_op__imm_data__imm_ok$43 \mul1_mul_op__imm_data__imm$42 } \mul1_mul_op__fn_unit$41 \mul1_mul_op__insn_type$40 }
+  wire width 1 \logical_op__is_32bit$83
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \logical_op__is_signed$84
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 4 \logical_op__data_len$85
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \logical_op__insn$86
+  process $group_48
+    assign \logical_op__insn_type$69 7'0000000
+    assign \logical_op__fn_unit$70 11'00000000000
+    assign \logical_op__imm_data__imm$71 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \logical_op__imm_data__imm_ok$72 1'0
+    assign \logical_op__rc__rc$73 1'0
+    assign \logical_op__rc__rc_ok$74 1'0
+    assign \logical_op__oe__oe$75 1'0
+    assign \logical_op__oe__oe_ok$76 1'0
+    assign \logical_op__invert_a$77 1'0
+    assign \logical_op__zero_a$78 1'0
+    assign \logical_op__input_carry$79 2'00
+    assign \logical_op__invert_out$80 1'0
+    assign \logical_op__write_cr0$81 1'0
+    assign \logical_op__output_carry$82 1'0
+    assign \logical_op__is_32bit$83 1'0
+    assign \logical_op__is_signed$84 1'0
+    assign \logical_op__data_len$85 4'0000
+    assign \logical_op__insn$86 32'00000000000000000000000000000000
+    assign { \logical_op__insn$86 \logical_op__data_len$85 \logical_op__is_signed$84 \logical_op__is_32bit$83 \logical_op__output_carry$82 \logical_op__write_cr0$81 \logical_op__invert_out$80 \logical_op__input_carry$79 \logical_op__zero_a$78 \logical_op__invert_a$77 { \logical_op__oe__oe_ok$76 \logical_op__oe__oe$75 } { \logical_op__rc__rc_ok$74 \logical_op__rc__rc$73 } { \logical_op__imm_data__imm_ok$72 \logical_op__imm_data__imm$71 } \logical_op__fn_unit$70 \logical_op__insn_type$69 } { \setup_stage_logical_op__insn$63 \setup_stage_logical_op__data_len$62 \setup_stage_logical_op__is_signed$61 \setup_stage_logical_op__is_32bit$60 \setup_stage_logical_op__output_carry$59 \setup_stage_logical_op__write_cr0$58 \setup_stage_logical_op__invert_out$57 \setup_stage_logical_op__input_carry$56 \setup_stage_logical_op__zero_a$55 \setup_stage_logical_op__invert_a$54 { \setup_stage_logical_op__oe__oe_ok$53 \setup_stage_logical_op__oe__oe$52 } { \setup_stage_logical_op__rc__rc_ok$51 \setup_stage_logical_op__rc__rc$50 } { \setup_stage_logical_op__imm_data__imm_ok$49 \setup_stage_logical_op__imm_data__imm$48 } \setup_stage_logical_op__fn_unit$47 \setup_stage_logical_op__insn_type$46 }
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
-  wire width 64 \ra$77
-  process $group_57
-    assign \ra$77 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \ra$77 \mul1_ra$55
+  wire width 64 \ra$87
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
+  wire width 64 \ra$88
+  process $group_66
+    assign \ra$87 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \ra$87 \ra$88
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
-  wire width 64 \rb$78
-  process $group_58
-    assign \rb$78 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \rb$78 \mul1_rb$56
+  wire width 64 \rb$89
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
+  wire width 64 \rb$90
+  process $group_67
+    assign \rb$89 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \rb$89 \rb$90
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
-  wire width 1 \xer_so$79
-  process $group_59
-    assign \xer_so$79 1'0
-    assign \xer_so$79 \mul1_xer_so$57
+  wire width 1 \xer_so$91
+  process $group_68
+    assign \xer_so$91 1'0
+    assign \xer_so$91 \setup_stage_xer_so$64
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11"
-  wire width 1 \neg_res$80
-  process $group_60
-    assign \neg_res$80 1'0
-    assign \neg_res$80 \mul1_neg_res
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160"
+  wire width 1 \divisor_neg$92
+  process $group_69
+    assign \divisor_neg$92 1'0
+    assign \divisor_neg$92 \setup_stage_divisor_neg
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12"
-  wire width 1 \neg_res32$81
-  process $group_61
-    assign \neg_res32$81 1'0
-    assign \neg_res32$81 \mul1_neg_res32
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161"
+  wire width 1 \dividend_neg$93
+  process $group_70
+    assign \dividend_neg$93 1'0
+    assign \dividend_neg$93 \setup_stage_dividend_neg
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167"
+  wire width 1 \dive_abs_ov32$94
+  process $group_71
+    assign \dive_abs_ov32$94 1'0
+    assign \dive_abs_ov32$94 \setup_stage_dive_abs_ov32
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168"
+  wire width 1 \dive_abs_ov64$95
+  process $group_72
+    assign \dive_abs_ov64$95 1'0
+    assign \dive_abs_ov64$95 \setup_stage_dive_abs_ov64
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162"
+  wire width 1 \div_by_zero$96
+  process $group_73
+    assign \div_by_zero$96 1'0
+    assign \div_by_zero$96 \setup_stage_div_by_zero
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18"
+  wire width 128 \dividend$97
+  process $group_74
+    assign \dividend$97 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
+    assign \dividend$97 \setup_stage_dividend
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19"
+  wire width 64 \divisor_radicand$98
+  process $group_75
+    assign \divisor_radicand$98 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \divisor_radicand$98 \setup_stage_divisor_radicand
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21"
+  wire width 2 \operation$99
+  process $group_76
+    assign \operation$99 2'00
+    assign \operation$99 \setup_stage_operation
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615"
   wire width 1 \r_busy
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615"
   wire width 1 \r_busy$next
-  process $group_62
+  process $group_77
     assign \r_busy$next \r_busy
     attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
     switch { \n_i_rdy_data \p_valid_i_p_ready_o }
@@ -91002,222 +91038,329 @@ module \mul_pipe1
         assign \r_busy$next 1'0
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \r_busy$next 1'0
     end
     sync init
       update \r_busy 1'0
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \r_busy \r_busy$next
   end
-  process $group_63
+  process $group_78
     assign \muxid$next \muxid
     attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
     switch { \n_i_rdy_data \p_valid_i_p_ready_o }
       attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
       case 2'-1
-        assign \muxid$next \muxid$61
+        assign \muxid$next \muxid$68
       attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
       case 2'1-
-        assign \muxid$next \muxid$61
+        assign \muxid$next \muxid$68
     end
     sync init
       update \muxid 2'00
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \muxid \muxid$next
   end
-  process $group_64
-    assign \mul_op__insn_type$next \mul_op__insn_type
-    assign \mul_op__fn_unit$next \mul_op__fn_unit
-    assign \mul_op__imm_data__imm$next \mul_op__imm_data__imm
-    assign \mul_op__imm_data__imm_ok$next \mul_op__imm_data__imm_ok
-    assign \mul_op__rc__rc$next \mul_op__rc__rc
-    assign \mul_op__rc__rc_ok$next \mul_op__rc__rc_ok
-    assign \mul_op__oe__oe$next \mul_op__oe__oe
-    assign \mul_op__oe__oe_ok$next \mul_op__oe__oe_ok
-    assign \mul_op__invert_a$next \mul_op__invert_a
-    assign \mul_op__zero_a$next \mul_op__zero_a
-    assign \mul_op__invert_out$next \mul_op__invert_out
-    assign \mul_op__write_cr0$next \mul_op__write_cr0
-    assign \mul_op__is_32bit$next \mul_op__is_32bit
-    assign \mul_op__is_signed$next \mul_op__is_signed
-    assign \mul_op__insn$next \mul_op__insn
+  process $group_79
+    assign \logical_op__insn_type$next \logical_op__insn_type
+    assign \logical_op__fn_unit$next \logical_op__fn_unit
+    assign \logical_op__imm_data__imm$next \logical_op__imm_data__imm
+    assign \logical_op__imm_data__imm_ok$next \logical_op__imm_data__imm_ok
+    assign \logical_op__rc__rc$next \logical_op__rc__rc
+    assign \logical_op__rc__rc_ok$next \logical_op__rc__rc_ok
+    assign \logical_op__oe__oe$next \logical_op__oe__oe
+    assign \logical_op__oe__oe_ok$next \logical_op__oe__oe_ok
+    assign \logical_op__invert_a$next \logical_op__invert_a
+    assign \logical_op__zero_a$next \logical_op__zero_a
+    assign \logical_op__input_carry$next \logical_op__input_carry
+    assign \logical_op__invert_out$next \logical_op__invert_out
+    assign \logical_op__write_cr0$next \logical_op__write_cr0
+    assign \logical_op__output_carry$next \logical_op__output_carry
+    assign \logical_op__is_32bit$next \logical_op__is_32bit
+    assign \logical_op__is_signed$next \logical_op__is_signed
+    assign \logical_op__data_len$next \logical_op__data_len
+    assign \logical_op__insn$next \logical_op__insn
     attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
     switch { \n_i_rdy_data \p_valid_i_p_ready_o }
       attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
       case 2'-1
-        assign { \mul_op__insn$next \mul_op__is_signed$next \mul_op__is_32bit$next \mul_op__write_cr0$next \mul_op__invert_out$next \mul_op__zero_a$next \mul_op__invert_a$next { \mul_op__oe__oe_ok$next \mul_op__oe__oe$next } { \mul_op__rc__rc_ok$next \mul_op__rc__rc$next } { \mul_op__imm_data__imm_ok$next \mul_op__imm_data__imm$next } \mul_op__fn_unit$next \mul_op__insn_type$next } { \mul_op__insn$76 \mul_op__is_signed$75 \mul_op__is_32bit$74 \mul_op__write_cr0$73 \mul_op__invert_out$72 \mul_op__zero_a$71 \mul_op__invert_a$70 { \mul_op__oe__oe_ok$69 \mul_op__oe__oe$68 } { \mul_op__rc__rc_ok$67 \mul_op__rc__rc$66 } { \mul_op__imm_data__imm_ok$65 \mul_op__imm_data__imm$64 } \mul_op__fn_unit$63 \mul_op__insn_type$62 }
+        assign { \logical_op__insn$next \logical_op__data_len$next \logical_op__is_signed$next \logical_op__is_32bit$next \logical_op__output_carry$next \logical_op__write_cr0$next \logical_op__invert_out$next \logical_op__input_carry$next \logical_op__zero_a$next \logical_op__invert_a$next { \logical_op__oe__oe_ok$next \logical_op__oe__oe$next } { \logical_op__rc__rc_ok$next \logical_op__rc__rc$next } { \logical_op__imm_data__imm_ok$next \logical_op__imm_data__imm$next } \logical_op__fn_unit$next \logical_op__insn_type$next } { \logical_op__insn$86 \logical_op__data_len$85 \logical_op__is_signed$84 \logical_op__is_32bit$83 \logical_op__output_carry$82 \logical_op__write_cr0$81 \logical_op__invert_out$80 \logical_op__input_carry$79 \logical_op__zero_a$78 \logical_op__invert_a$77 { \logical_op__oe__oe_ok$76 \logical_op__oe__oe$75 } { \logical_op__rc__rc_ok$74 \logical_op__rc__rc$73 } { \logical_op__imm_data__imm_ok$72 \logical_op__imm_data__imm$71 } \logical_op__fn_unit$70 \logical_op__insn_type$69 }
       attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
       case 2'1-
-        assign { \mul_op__insn$next \mul_op__is_signed$next \mul_op__is_32bit$next \mul_op__write_cr0$next \mul_op__invert_out$next \mul_op__zero_a$next \mul_op__invert_a$next { \mul_op__oe__oe_ok$next \mul_op__oe__oe$next } { \mul_op__rc__rc_ok$next \mul_op__rc__rc$next } { \mul_op__imm_data__imm_ok$next \mul_op__imm_data__imm$next } \mul_op__fn_unit$next \mul_op__insn_type$next } { \mul_op__insn$76 \mul_op__is_signed$75 \mul_op__is_32bit$74 \mul_op__write_cr0$73 \mul_op__invert_out$72 \mul_op__zero_a$71 \mul_op__invert_a$70 { \mul_op__oe__oe_ok$69 \mul_op__oe__oe$68 } { \mul_op__rc__rc_ok$67 \mul_op__rc__rc$66 } { \mul_op__imm_data__imm_ok$65 \mul_op__imm_data__imm$64 } \mul_op__fn_unit$63 \mul_op__insn_type$62 }
+        assign { \logical_op__insn$next \logical_op__data_len$next \logical_op__is_signed$next \logical_op__is_32bit$next \logical_op__output_carry$next \logical_op__write_cr0$next \logical_op__invert_out$next \logical_op__input_carry$next \logical_op__zero_a$next \logical_op__invert_a$next { \logical_op__oe__oe_ok$next \logical_op__oe__oe$next } { \logical_op__rc__rc_ok$next \logical_op__rc__rc$next } { \logical_op__imm_data__imm_ok$next \logical_op__imm_data__imm$next } \logical_op__fn_unit$next \logical_op__insn_type$next } { \logical_op__insn$86 \logical_op__data_len$85 \logical_op__is_signed$84 \logical_op__is_32bit$83 \logical_op__output_carry$82 \logical_op__write_cr0$81 \logical_op__invert_out$80 \logical_op__input_carry$79 \logical_op__zero_a$78 \logical_op__invert_a$77 { \logical_op__oe__oe_ok$76 \logical_op__oe__oe$75 } { \logical_op__rc__rc_ok$74 \logical_op__rc__rc$73 } { \logical_op__imm_data__imm_ok$72 \logical_op__imm_data__imm$71 } \logical_op__fn_unit$70 \logical_op__insn_type$69 }
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
-      case 1'1
-        assign \mul_op__imm_data__imm$next 64'0000000000000000000000000000000000000000000000000000000000000000
-        assign \mul_op__imm_data__imm_ok$next 1'0
-        assign \mul_op__rc__rc$next 1'0
-        assign \mul_op__rc__rc_ok$next 1'0
-        assign \mul_op__oe__oe$next 1'0
-        assign \mul_op__oe__oe_ok$next 1'0
-    end
-    sync init
-      update \mul_op__insn_type 7'0000000
-      update \mul_op__fn_unit 11'00000000000
-      update \mul_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
-      update \mul_op__imm_data__imm_ok 1'0
-      update \mul_op__rc__rc 1'0
-      update \mul_op__rc__rc_ok 1'0
-      update \mul_op__oe__oe 1'0
-      update \mul_op__oe__oe_ok 1'0
-      update \mul_op__invert_a 1'0
-      update \mul_op__zero_a 1'0
-      update \mul_op__invert_out 1'0
-      update \mul_op__write_cr0 1'0
-      update \mul_op__is_32bit 1'0
-      update \mul_op__is_signed 1'0
-      update \mul_op__insn 32'00000000000000000000000000000000
-    sync posedge \clk
-      update \mul_op__insn_type \mul_op__insn_type$next
-      update \mul_op__fn_unit \mul_op__fn_unit$next
-      update \mul_op__imm_data__imm \mul_op__imm_data__imm$next
-      update \mul_op__imm_data__imm_ok \mul_op__imm_data__imm_ok$next
-      update \mul_op__rc__rc \mul_op__rc__rc$next
-      update \mul_op__rc__rc_ok \mul_op__rc__rc_ok$next
-      update \mul_op__oe__oe \mul_op__oe__oe$next
-      update \mul_op__oe__oe_ok \mul_op__oe__oe_ok$next
-      update \mul_op__invert_a \mul_op__invert_a$next
-      update \mul_op__zero_a \mul_op__zero_a$next
-      update \mul_op__invert_out \mul_op__invert_out$next
-      update \mul_op__write_cr0 \mul_op__write_cr0$next
-      update \mul_op__is_32bit \mul_op__is_32bit$next
-      update \mul_op__is_signed \mul_op__is_signed$next
-      update \mul_op__insn \mul_op__insn$next
+    switch \coresync_rst
+      case 1'1
+        assign \logical_op__imm_data__imm$next 64'0000000000000000000000000000000000000000000000000000000000000000
+        assign \logical_op__imm_data__imm_ok$next 1'0
+        assign \logical_op__rc__rc$next 1'0
+        assign \logical_op__rc__rc_ok$next 1'0
+        assign \logical_op__oe__oe$next 1'0
+        assign \logical_op__oe__oe_ok$next 1'0
+    end
+    sync init
+      update \logical_op__insn_type 7'0000000
+      update \logical_op__fn_unit 11'00000000000
+      update \logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
+      update \logical_op__imm_data__imm_ok 1'0
+      update \logical_op__rc__rc 1'0
+      update \logical_op__rc__rc_ok 1'0
+      update \logical_op__oe__oe 1'0
+      update \logical_op__oe__oe_ok 1'0
+      update \logical_op__invert_a 1'0
+      update \logical_op__zero_a 1'0
+      update \logical_op__input_carry 2'00
+      update \logical_op__invert_out 1'0
+      update \logical_op__write_cr0 1'0
+      update \logical_op__output_carry 1'0
+      update \logical_op__is_32bit 1'0
+      update \logical_op__is_signed 1'0
+      update \logical_op__data_len 4'0000
+      update \logical_op__insn 32'00000000000000000000000000000000
+    sync posedge \coresync_clk
+      update \logical_op__insn_type \logical_op__insn_type$next
+      update \logical_op__fn_unit \logical_op__fn_unit$next
+      update \logical_op__imm_data__imm \logical_op__imm_data__imm$next
+      update \logical_op__imm_data__imm_ok \logical_op__imm_data__imm_ok$next
+      update \logical_op__rc__rc \logical_op__rc__rc$next
+      update \logical_op__rc__rc_ok \logical_op__rc__rc_ok$next
+      update \logical_op__oe__oe \logical_op__oe__oe$next
+      update \logical_op__oe__oe_ok \logical_op__oe__oe_ok$next
+      update \logical_op__invert_a \logical_op__invert_a$next
+      update \logical_op__zero_a \logical_op__zero_a$next
+      update \logical_op__input_carry \logical_op__input_carry$next
+      update \logical_op__invert_out \logical_op__invert_out$next
+      update \logical_op__write_cr0 \logical_op__write_cr0$next
+      update \logical_op__output_carry \logical_op__output_carry$next
+      update \logical_op__is_32bit \logical_op__is_32bit$next
+      update \logical_op__is_signed \logical_op__is_signed$next
+      update \logical_op__data_len \logical_op__data_len$next
+      update \logical_op__insn \logical_op__insn$next
   end
-  process $group_79
+  process $group_97
     assign \ra$next \ra
     attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
     switch { \n_i_rdy_data \p_valid_i_p_ready_o }
       attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
       case 2'-1
-        assign \ra$next \ra$77
+        assign \ra$next \ra$87
       attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
       case 2'1-
-        assign \ra$next \ra$77
+        assign \ra$next \ra$87
     end
     sync init
       update \ra 64'0000000000000000000000000000000000000000000000000000000000000000
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \ra \ra$next
   end
-  process $group_80
+  process $group_98
     assign \rb$next \rb
     attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
     switch { \n_i_rdy_data \p_valid_i_p_ready_o }
       attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
       case 2'-1
-        assign \rb$next \rb$78
+        assign \rb$next \rb$89
       attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
       case 2'1-
-        assign \rb$next \rb$78
+        assign \rb$next \rb$89
     end
     sync init
       update \rb 64'0000000000000000000000000000000000000000000000000000000000000000
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \rb \rb$next
   end
-  process $group_81
+  process $group_99
     assign \xer_so$next \xer_so
     attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
     switch { \n_i_rdy_data \p_valid_i_p_ready_o }
       attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
       case 2'-1
-        assign \xer_so$next \xer_so$79
+        assign \xer_so$next \xer_so$91
       attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
       case 2'1-
-        assign \xer_so$next \xer_so$79
+        assign \xer_so$next \xer_so$91
     end
     sync init
       update \xer_so 1'0
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \xer_so \xer_so$next
   end
-  process $group_82
-    assign \neg_res$next \neg_res
+  process $group_100
+    assign \divisor_neg$next \divisor_neg
     attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
     switch { \n_i_rdy_data \p_valid_i_p_ready_o }
       attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
       case 2'-1
-        assign \neg_res$next \neg_res$80
+        assign \divisor_neg$next \divisor_neg$92
       attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
       case 2'1-
-        assign \neg_res$next \neg_res$80
+        assign \divisor_neg$next \divisor_neg$92
     end
     sync init
-      update \neg_res 1'0
-    sync posedge \clk
-      update \neg_res \neg_res$next
+      update \divisor_neg 1'0
+    sync posedge \coresync_clk
+      update \divisor_neg \divisor_neg$next
   end
-  process $group_83
-    assign \neg_res32$next \neg_res32
+  process $group_101
+    assign \dividend_neg$next \dividend_neg
     attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
     switch { \n_i_rdy_data \p_valid_i_p_ready_o }
       attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
       case 2'-1
-        assign \neg_res32$next \neg_res32$81
+        assign \dividend_neg$next \dividend_neg$93
       attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
       case 2'1-
-        assign \neg_res32$next \neg_res32$81
+        assign \dividend_neg$next \dividend_neg$93
     end
     sync init
-      update \neg_res32 1'0
-    sync posedge \clk
-      update \neg_res32 \neg_res32$next
+      update \dividend_neg 1'0
+    sync posedge \coresync_clk
+      update \dividend_neg \dividend_neg$next
   end
-  process $group_84
-    assign \n_valid_o 1'0
-    assign \n_valid_o \r_busy
+  process $group_102
+    assign \dive_abs_ov32$next \dive_abs_ov32
+    attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+    switch { \n_i_rdy_data \p_valid_i_p_ready_o }
+      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+      case 2'-1
+        assign \dive_abs_ov32$next \dive_abs_ov32$94
+      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
+      case 2'1-
+        assign \dive_abs_ov32$next \dive_abs_ov32$94
+    end
     sync init
+      update \dive_abs_ov32 1'0
+    sync posedge \coresync_clk
+      update \dive_abs_ov32 \dive_abs_ov32$next
   end
-  process $group_85
-    assign \p_ready_o 1'0
-    assign \p_ready_o \n_i_rdy_data
+  process $group_103
+    assign \dive_abs_ov64$next \dive_abs_ov64
+    attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+    switch { \n_i_rdy_data \p_valid_i_p_ready_o }
+      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+      case 2'-1
+        assign \dive_abs_ov64$next \dive_abs_ov64$95
+      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
+      case 2'1-
+        assign \dive_abs_ov64$next \dive_abs_ov64$95
+    end
     sync init
+      update \dive_abs_ov64 1'0
+    sync posedge \coresync_clk
+      update \dive_abs_ov64 \dive_abs_ov64$next
   end
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe2.p"
-module \p$75
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153"
-  wire width 1 input 0 \p_valid_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154"
-  wire width 1 input 1 \p_ready_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158"
-  wire width 1 \trigger
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205"
-  wire width 1 $1
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205"
-  cell $and $2
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \p_valid_i
-    connect \B \p_ready_o
-    connect \Y $1
-  end
-  process $group_0
-    assign \trigger 1'0
-    assign \trigger $1
+  process $group_104
+    assign \div_by_zero$next \div_by_zero
+    attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+    switch { \n_i_rdy_data \p_valid_i_p_ready_o }
+      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+      case 2'-1
+        assign \div_by_zero$next \div_by_zero$96
+      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
+      case 2'1-
+        assign \div_by_zero$next \div_by_zero$96
+    end
     sync init
+      update \div_by_zero 1'0
+    sync posedge \coresync_clk
+      update \div_by_zero \div_by_zero$next
   end
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe2.n"
-module \n$76
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
+  process $group_105
+    assign \dividend$next \dividend
+    attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+    switch { \n_i_rdy_data \p_valid_i_p_ready_o }
+      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+      case 2'-1
+        assign \dividend$next \dividend$97
+      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
+      case 2'1-
+        assign \dividend$next \dividend$97
+    end
+    sync init
+      update \dividend 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
+    sync posedge \coresync_clk
+      update \dividend \dividend$next
+  end
+  process $group_106
+    assign \divisor_radicand$next \divisor_radicand
+    attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+    switch { \n_i_rdy_data \p_valid_i_p_ready_o }
+      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+      case 2'-1
+        assign \divisor_radicand$next \divisor_radicand$98
+      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
+      case 2'1-
+        assign \divisor_radicand$next \divisor_radicand$98
+    end
+    sync init
+      update \divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000
+    sync posedge \coresync_clk
+      update \divisor_radicand \divisor_radicand$next
+  end
+  process $group_107
+    assign \operation$next \operation
+    attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+    switch { \n_i_rdy_data \p_valid_i_p_ready_o }
+      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+      case 2'-1
+        assign \operation$next \operation$99
+      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
+      case 2'1-
+        assign \operation$next \operation$99
+    end
+    sync init
+      update \operation 2'00
+    sync posedge \coresync_clk
+      update \operation \operation$next
+  end
+  process $group_108
+    assign \n_valid_o 1'0
+    assign \n_valid_o \r_busy
+    sync init
+  end
+  process $group_109
+    assign \p_ready_o 1'0
+    assign \p_ready_o \n_i_rdy_data
+    sync init
+  end
+  connect \ra$88 64'0000000000000000000000000000000000000000000000000000000000000000
+  connect \rb$90 64'0000000000000000000000000000000000000000000000000000000000000000
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_0.p"
+module \p$75
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153"
+  wire width 1 input 0 \p_valid_i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154"
+  wire width 1 input 1 \p_ready_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158"
+  wire width 1 \trigger
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205"
+  wire width 1 $1
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205"
+  cell $and $2
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \p_valid_i
+    connect \B \p_ready_o
+    connect \Y $1
+  end
+  process $group_0
+    assign \trigger 1'0
+    assign \trigger $1
+    sync init
+  end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_0.n"
+module \n$76
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
   wire width 1 input 0 \n_valid_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
   wire width 1 input 1 \n_ready_i
@@ -91243,10 +91386,191 @@ module \n$76
   end
 end
 attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe2.mul2"
-module \mul2
+attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_0.div_state_next"
+module \div_state_next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:123"
+  wire width 128 output 0 \o_dividend_quotient
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:121"
+  wire width 7 output 1 \o_q_bits_known
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:121"
+  wire width 7 input 2 \i_q_bits_known
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:123"
+  wire width 128 input 3 \i_dividend_quotient
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:77"
+  wire width 64 input 4 \divisor
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:82"
+  wire width 128 \difference
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:85"
+  wire width 129 $1
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:85"
+  wire width 127 $2
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:85"
+  cell $sshl $3
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 64
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 6
+    parameter \Y_WIDTH 127
+    connect \A \divisor
+    connect \B 6'111111
+    connect \Y $2
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:85"
+  wire width 129 $4
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:85"
+  cell $sub $5
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 128
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 127
+    parameter \Y_WIDTH 129
+    connect \A \i_dividend_quotient
+    connect \B $2
+    connect \Y $4
+  end
+  connect $1 $4
+  process $group_0
+    assign \difference 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
+    assign \difference $1 [127:0]
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:86"
+  wire width 1 \next_quotient_bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:88"
+  wire width 1 $6
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:88"
+  cell $not $7
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \difference [127]
+    connect \Y $6
+  end
+  process $group_1
+    assign \next_quotient_bit 1'0
+    assign \next_quotient_bit $6
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:89"
+  wire width 128 \value
+  process $group_2
+    assign \value 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:90"
+    switch { \next_quotient_bit }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:90"
+      case 1'1
+        assign \value \difference
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:92"
+      case
+        assign \value \i_dividend_quotient
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:127"
+  wire width 1 $8
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:127"
+  cell $eq $9
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 7
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 7
+    parameter \Y_WIDTH 1
+    connect \A \i_q_bits_known
+    connect \B 7'1000000
+    connect \Y $8
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:99"
+  wire width 8 $10
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:99"
+  wire width 8 $11
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:99"
+  cell $add $12
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 7
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 8
+    connect \A \i_q_bits_known
+    connect \B 1'1
+    connect \Y $11
+  end
+  connect $10 $11
+  process $group_3
+    assign \o_q_bits_known 7'0000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:95"
+    switch { $8 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:95"
+      case 1'1
+        assign \o_q_bits_known \i_q_bits_known
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:97"
+      case
+        assign \o_q_bits_known $10 [6:0]
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:127"
+  wire width 1 $13
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:127"
+  cell $eq $14
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 7
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 7
+    parameter \Y_WIDTH 1
+    connect \A \i_q_bits_known
+    connect \B 7'1000000
+    connect \Y $13
+  end
+  process $group_4
+    assign \o_dividend_quotient 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:95"
+    switch { $13 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:95"
+      case 1'1
+        assign \o_dividend_quotient \i_dividend_quotient
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:97"
+      case
+        assign \o_dividend_quotient { \value \next_quotient_bit } [127:0]
+    end
+    sync init
+  end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_0.div_state_init"
+module \div_state_init
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:107"
+  wire width 128 input 0 \dividend
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:121"
+  wire width 7 output 1 \o_q_bits_known
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:123"
+  wire width 128 output 2 \o_dividend_quotient
+  wire width 1 $verilog_initial_trigger
+  process $group_0
+    assign \o_q_bits_known 7'0000000
+    assign \o_q_bits_known 7'0000000
+    assign $verilog_initial_trigger $verilog_initial_trigger
+    sync init
+      update $verilog_initial_trigger 1'0
+  end
+  process $group_1
+    assign \o_dividend_quotient 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
+    assign \o_dividend_quotient \dividend
+    sync init
+  end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_0"
+module \pipe_middle_0
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153"
+  wire width 1 input 2 \p_valid_i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154"
+  wire width 1 output 3 \p_ready_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
-  wire width 2 input 0 \muxid
+  wire width 2 input 4 \muxid
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
   attribute \enum_value_0000001 "OP_NOP"
@@ -91321,7 +91645,7 @@ module \mul2
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 7 input 1 \mul_op__insn_type
+  wire width 7 input 5 \logical_op__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -91335,45 +91659,71 @@ module \mul2
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 11 input 2 \mul_op__fn_unit
+  wire width 11 input 6 \logical_op__fn_unit
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 64 input 3 \mul_op__imm_data__imm
+  wire width 64 input 7 \logical_op__imm_data__imm
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 4 \mul_op__imm_data__imm_ok
+  wire width 1 input 8 \logical_op__imm_data__imm_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 5 \mul_op__rc__rc
+  wire width 1 input 9 \logical_op__rc__rc
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 6 \mul_op__rc__rc_ok
+  wire width 1 input 10 \logical_op__rc__rc_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 7 \mul_op__oe__oe
+  wire width 1 input 11 \logical_op__oe__oe
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 8 \mul_op__oe__oe_ok
+  wire width 1 input 12 \logical_op__oe__oe_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 9 \mul_op__invert_a
+  wire width 1 input 13 \logical_op__invert_a
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 10 \mul_op__zero_a
+  wire width 1 input 14 \logical_op__zero_a
+  attribute \enum_base_type "CryIn"
+  attribute \enum_value_00 "ZERO"
+  attribute \enum_value_01 "ONE"
+  attribute \enum_value_10 "CA"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 11 \mul_op__invert_out
+  wire width 2 input 15 \logical_op__input_carry
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 12 \mul_op__write_cr0
+  wire width 1 input 16 \logical_op__invert_out
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 13 \mul_op__is_32bit
+  wire width 1 input 17 \logical_op__write_cr0
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 14 \mul_op__is_signed
+  wire width 1 input 18 \logical_op__output_carry
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 32 input 15 \mul_op__insn
+  wire width 1 input 19 \logical_op__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 20 \logical_op__is_signed
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 4 input 21 \logical_op__data_len
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 input 22 \logical_op__insn
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
-  wire width 64 input 16 \ra
+  wire width 64 input 23 \ra
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
-  wire width 64 input 17 \rb
+  wire width 64 input 24 \rb
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
-  wire width 1 input 18 \xer_so
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11"
-  wire width 1 input 19 \neg_res
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12"
-  wire width 1 input 20 \neg_res32
+  wire width 1 input 25 \xer_so
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160"
+  wire width 1 input 26 \divisor_neg
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161"
+  wire width 1 input 27 \dividend_neg
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167"
+  wire width 1 input 28 \dive_abs_ov32
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168"
+  wire width 1 input 29 \dive_abs_ov64
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162"
+  wire width 1 input 30 \div_by_zero
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18"
+  wire width 128 input 31 \dividend
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19"
+  wire width 64 input 32 \divisor_radicand
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21"
+  wire width 2 input 33 \operation
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
+  wire width 1 output 34 \n_valid_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
+  wire width 1 input 35 \n_ready_i
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
-  wire width 2 output 21 \muxid$1
+  wire width 2 output 36 \muxid$1
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
   attribute \enum_value_0000001 "OP_NOP"
@@ -91448,7 +91798,7 @@ module \mul2
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 7 output 22 \mul_op__insn_type$2
+  wire width 7 output 37 \logical_op__insn_type$2
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -91462,122 +91812,113 @@ module \mul2
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 11 output 23 \mul_op__fn_unit$3
+  wire width 11 output 38 \logical_op__fn_unit$3
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 64 output 24 \mul_op__imm_data__imm$4
+  wire width 64 output 39 \logical_op__imm_data__imm$4
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 25 \mul_op__imm_data__imm_ok$5
+  wire width 1 output 40 \logical_op__imm_data__imm_ok$5
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 26 \mul_op__rc__rc$6
+  wire width 1 output 41 \logical_op__rc__rc$6
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 27 \mul_op__rc__rc_ok$7
+  wire width 1 output 42 \logical_op__rc__rc_ok$7
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 28 \mul_op__oe__oe$8
+  wire width 1 output 43 \logical_op__oe__oe$8
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 29 \mul_op__oe__oe_ok$9
+  wire width 1 output 44 \logical_op__oe__oe_ok$9
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 30 \mul_op__invert_a$10
+  wire width 1 output 45 \logical_op__invert_a$10
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 31 \mul_op__zero_a$11
+  wire width 1 output 46 \logical_op__zero_a$11
+  attribute \enum_base_type "CryIn"
+  attribute \enum_value_00 "ZERO"
+  attribute \enum_value_01 "ONE"
+  attribute \enum_value_10 "CA"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 32 \mul_op__invert_out$12
+  wire width 2 output 47 \logical_op__input_carry$12
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 33 \mul_op__write_cr0$13
+  wire width 1 output 48 \logical_op__invert_out$13
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 34 \mul_op__is_32bit$14
+  wire width 1 output 49 \logical_op__write_cr0$14
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 35 \mul_op__is_signed$15
+  wire width 1 output 50 \logical_op__output_carry$15
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 32 output 36 \mul_op__insn$16
+  wire width 1 output 51 \logical_op__is_32bit$16
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 52 \logical_op__is_signed$17
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 4 output 53 \logical_op__data_len$18
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 output 54 \logical_op__insn$19
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
-  wire width 129 output 37 \o
+  wire width 64 output 55 \ra$20
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
-  wire width 1 output 38 \xer_so$17
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23"
-  wire width 1 output 39 \neg_res$18
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24"
-  wire width 1 output 40 \neg_res32$19
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28"
-  wire width 129 $20
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28"
-  wire width 128 $21
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28"
-  cell $mul $22
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 64
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 64
-    parameter \Y_WIDTH 128
-    connect \A \ra
-    connect \B \rb
-    connect \Y $21
+  wire width 64 output 56 \rb$21
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
+  wire width 1 output 57 \xer_so$22
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160"
+  wire width 1 output 58 \divisor_neg$23
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161"
+  wire width 1 output 59 \dividend_neg$24
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167"
+  wire width 1 output 60 \dive_abs_ov32$25
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168"
+  wire width 1 output 61 \dive_abs_ov64$26
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162"
+  wire width 1 output 62 \div_by_zero$27
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40"
+  wire width 64 output 63 \quotient_root
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:41"
+  wire width 192 output 64 \remainder
+  cell \p$75 \p
+    connect \p_valid_i \p_valid_i
+    connect \p_ready_o \p_ready_o
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28"
-  cell $pos $23
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 128
-    parameter \Y_WIDTH 129
-    connect \A $21
-    connect \Y $20
+  cell \n$76 \n
+    connect \n_valid_o \n_valid_o
+    connect \n_ready_i \n_ready_i
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:123"
+  wire width 128 \div_state_next_o_dividend_quotient
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:121"
+  wire width 7 \div_state_next_o_q_bits_known
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:121"
+  wire width 7 \div_state_next_i_q_bits_known
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:123"
+  wire width 128 \div_state_next_i_dividend_quotient
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:77"
+  wire width 64 \div_state_next_divisor
+  cell \div_state_next \div_state_next
+    connect \o_dividend_quotient \div_state_next_o_dividend_quotient
+    connect \o_q_bits_known \div_state_next_o_q_bits_known
+    connect \i_q_bits_known \div_state_next_i_q_bits_known
+    connect \i_dividend_quotient \div_state_next_i_dividend_quotient
+    connect \divisor \div_state_next_divisor
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:107"
+  wire width 128 \div_state_init_dividend
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:121"
+  wire width 7 \div_state_init_o_q_bits_known
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:123"
+  wire width 128 \div_state_init_o_dividend_quotient
+  cell \div_state_init \div_state_init
+    connect \dividend \div_state_init_dividend
+    connect \o_q_bits_known \div_state_init_o_q_bits_known
+    connect \o_dividend_quotient \div_state_init_o_dividend_quotient
   end
   process $group_0
-    assign \o 129'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
-    assign \o $20
+    assign \div_state_init_dividend 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
+    assign \div_state_init_dividend \dividend
     sync init
   end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
+  wire width 2 \muxid$28
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
+  wire width 2 \muxid$28$next
   process $group_1
-    assign \neg_res$18 1'0
-    assign \neg_res$18 \neg_res
-    sync init
-  end
-  process $group_2
-    assign \neg_res32$19 1'0
-    assign \neg_res32$19 \neg_res32
-    sync init
-  end
-  process $group_3
-    assign \xer_so$17 1'0
-    assign \xer_so$17 \xer_so
-    sync init
-  end
-  process $group_4
     assign \muxid$1 2'00
-    assign \muxid$1 \muxid
-    sync init
-  end
-  process $group_5
-    assign \mul_op__insn_type$2 7'0000000
-    assign \mul_op__fn_unit$3 11'00000000000
-    assign \mul_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \mul_op__imm_data__imm_ok$5 1'0
-    assign \mul_op__rc__rc$6 1'0
-    assign \mul_op__rc__rc_ok$7 1'0
-    assign \mul_op__oe__oe$8 1'0
-    assign \mul_op__oe__oe_ok$9 1'0
-    assign \mul_op__invert_a$10 1'0
-    assign \mul_op__zero_a$11 1'0
-    assign \mul_op__invert_out$12 1'0
-    assign \mul_op__write_cr0$13 1'0
-    assign \mul_op__is_32bit$14 1'0
-    assign \mul_op__is_signed$15 1'0
-    assign \mul_op__insn$16 32'00000000000000000000000000000000
-    assign { \mul_op__insn$16 \mul_op__is_signed$15 \mul_op__is_32bit$14 \mul_op__write_cr0$13 \mul_op__invert_out$12 \mul_op__zero_a$11 \mul_op__invert_a$10 { \mul_op__oe__oe_ok$9 \mul_op__oe__oe$8 } { \mul_op__rc__rc_ok$7 \mul_op__rc__rc$6 } { \mul_op__imm_data__imm_ok$5 \mul_op__imm_data__imm$4 } \mul_op__fn_unit$3 \mul_op__insn_type$2 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__invert_out \mul_op__zero_a \mul_op__invert_a { \mul_op__oe__oe_ok \mul_op__oe__oe } { \mul_op__rc__rc_ok \mul_op__rc__rc } { \mul_op__imm_data__imm_ok \mul_op__imm_data__imm } \mul_op__fn_unit \mul_op__insn_type }
+    assign \muxid$1 \muxid$28
     sync init
   end
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe2"
-module \mul_pipe2
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153"
-  wire width 1 input 2 \p_valid_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154"
-  wire width 1 output 3 \p_ready_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
-  wire width 2 input 4 \muxid
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
   attribute \enum_value_0000001 "OP_NOP"
@@ -91652,7 +91993,9 @@ module \mul_pipe2
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 7 input 5 \mul_op__insn_type
+  wire width 7 \logical_op__insn_type$29
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 \logical_op__insn_type$29$next
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -91666,222 +92009,753 @@ module \mul_pipe2
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 11 input 6 \mul_op__fn_unit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 64 input 7 \mul_op__imm_data__imm
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 8 \mul_op__imm_data__imm_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 9 \mul_op__rc__rc
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 10 \mul_op__rc__rc_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 11 \mul_op__oe__oe
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 12 \mul_op__oe__oe_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 13 \mul_op__invert_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 14 \mul_op__zero_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 15 \mul_op__invert_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 16 \mul_op__write_cr0
+  wire width 11 \logical_op__fn_unit$30
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 17 \mul_op__is_32bit
+  wire width 11 \logical_op__fn_unit$30$next
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 18 \mul_op__is_signed
+  wire width 64 \logical_op__imm_data__imm$31
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 32 input 19 \mul_op__insn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
-  wire width 64 input 20 \ra
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
-  wire width 64 input 21 \rb
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
-  wire width 1 input 22 \xer_so
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11"
-  wire width 1 input 23 \neg_res
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12"
-  wire width 1 input 24 \neg_res32
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
-  wire width 1 output 25 \n_valid_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
-  wire width 1 input 26 \n_ready_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
-  wire width 2 output 27 \muxid$1
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
-  wire width 2 \muxid$1$next
-  attribute \enum_base_type "MicrOp"
-  attribute \enum_value_0000000 "OP_ILLEGAL"
-  attribute \enum_value_0000001 "OP_NOP"
-  attribute \enum_value_0000010 "OP_ADD"
-  attribute \enum_value_0000011 "OP_ADDPCIS"
-  attribute \enum_value_0000100 "OP_AND"
-  attribute \enum_value_0000101 "OP_ATTN"
-  attribute \enum_value_0000110 "OP_B"
-  attribute \enum_value_0000111 "OP_BC"
-  attribute \enum_value_0001000 "OP_BCREG"
-  attribute \enum_value_0001001 "OP_BPERM"
-  attribute \enum_value_0001010 "OP_CMP"
-  attribute \enum_value_0001011 "OP_CMPB"
-  attribute \enum_value_0001100 "OP_CMPEQB"
-  attribute \enum_value_0001101 "OP_CMPRB"
-  attribute \enum_value_0001110 "OP_CNTZ"
-  attribute \enum_value_0001111 "OP_CRAND"
-  attribute \enum_value_0010000 "OP_CRANDC"
-  attribute \enum_value_0010001 "OP_CREQV"
-  attribute \enum_value_0010010 "OP_CRNAND"
-  attribute \enum_value_0010011 "OP_CRNOR"
-  attribute \enum_value_0010100 "OP_CROR"
-  attribute \enum_value_0010101 "OP_CRORC"
-  attribute \enum_value_0010110 "OP_CRXOR"
-  attribute \enum_value_0010111 "OP_DARN"
-  attribute \enum_value_0011000 "OP_DCBF"
-  attribute \enum_value_0011001 "OP_DCBST"
-  attribute \enum_value_0011010 "OP_DCBT"
-  attribute \enum_value_0011011 "OP_DCBTST"
-  attribute \enum_value_0011100 "OP_DCBZ"
-  attribute \enum_value_0011101 "OP_DIV"
-  attribute \enum_value_0011110 "OP_DIVE"
-  attribute \enum_value_0011111 "OP_EXTS"
-  attribute \enum_value_0100000 "OP_EXTSWSLI"
-  attribute \enum_value_0100001 "OP_ICBI"
-  attribute \enum_value_0100010 "OP_ICBT"
-  attribute \enum_value_0100011 "OP_ISEL"
-  attribute \enum_value_0100100 "OP_ISYNC"
-  attribute \enum_value_0100101 "OP_LOAD"
-  attribute \enum_value_0100110 "OP_STORE"
-  attribute \enum_value_0100111 "OP_MADDHD"
-  attribute \enum_value_0101000 "OP_MADDHDU"
-  attribute \enum_value_0101001 "OP_MADDLD"
-  attribute \enum_value_0101010 "OP_MCRF"
-  attribute \enum_value_0101011 "OP_MCRXR"
-  attribute \enum_value_0101100 "OP_MCRXRX"
-  attribute \enum_value_0101101 "OP_MFCR"
-  attribute \enum_value_0101110 "OP_MFSPR"
-  attribute \enum_value_0101111 "OP_MOD"
-  attribute \enum_value_0110000 "OP_MTCRF"
-  attribute \enum_value_0110001 "OP_MTSPR"
-  attribute \enum_value_0110010 "OP_MUL_L64"
-  attribute \enum_value_0110011 "OP_MUL_H64"
-  attribute \enum_value_0110100 "OP_MUL_H32"
-  attribute \enum_value_0110101 "OP_OR"
-  attribute \enum_value_0110110 "OP_POPCNT"
-  attribute \enum_value_0110111 "OP_PRTY"
-  attribute \enum_value_0111000 "OP_RLC"
-  attribute \enum_value_0111001 "OP_RLCL"
-  attribute \enum_value_0111010 "OP_RLCR"
-  attribute \enum_value_0111011 "OP_SETB"
-  attribute \enum_value_0111100 "OP_SHL"
-  attribute \enum_value_0111101 "OP_SHR"
-  attribute \enum_value_0111110 "OP_SYNC"
-  attribute \enum_value_0111111 "OP_TRAP"
-  attribute \enum_value_1000011 "OP_XOR"
-  attribute \enum_value_1000100 "OP_SIM_CONFIG"
-  attribute \enum_value_1000101 "OP_CROP"
-  attribute \enum_value_1000110 "OP_RFID"
-  attribute \enum_value_1000111 "OP_MFMSR"
-  attribute \enum_value_1001000 "OP_MTMSRD"
-  attribute \enum_value_1001001 "OP_SC"
-  attribute \enum_value_1001010 "OP_MTMSR"
+  wire width 64 \logical_op__imm_data__imm$31$next
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 7 output 28 \mul_op__insn_type$2
+  wire width 1 \logical_op__imm_data__imm_ok$32
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 7 \mul_op__insn_type$2$next
-  attribute \enum_base_type "Function"
-  attribute \enum_value_00000000000 "NONE"
-  attribute \enum_value_00000000010 "ALU"
-  attribute \enum_value_00000000100 "LDST"
-  attribute \enum_value_00000001000 "SHIFT_ROT"
-  attribute \enum_value_00000010000 "LOGICAL"
-  attribute \enum_value_00000100000 "BRANCH"
-  attribute \enum_value_00001000000 "CR"
-  attribute \enum_value_00010000000 "TRAP"
-  attribute \enum_value_00100000000 "MUL"
-  attribute \enum_value_01000000000 "DIV"
-  attribute \enum_value_10000000000 "SPR"
+  wire width 1 \logical_op__imm_data__imm_ok$32$next
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 11 output 29 \mul_op__fn_unit$3
+  wire width 1 \logical_op__rc__rc$33
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 11 \mul_op__fn_unit$3$next
+  wire width 1 \logical_op__rc__rc$33$next
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 64 output 30 \mul_op__imm_data__imm$4
+  wire width 1 \logical_op__rc__rc_ok$34
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 64 \mul_op__imm_data__imm$4$next
+  wire width 1 \logical_op__rc__rc_ok$34$next
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 31 \mul_op__imm_data__imm_ok$5
+  wire width 1 \logical_op__oe__oe$35
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_op__imm_data__imm_ok$5$next
+  wire width 1 \logical_op__oe__oe$35$next
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 32 \mul_op__rc__rc$6
+  wire width 1 \logical_op__oe__oe_ok$36
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_op__rc__rc$6$next
+  wire width 1 \logical_op__oe__oe_ok$36$next
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 33 \mul_op__rc__rc_ok$7
+  wire width 1 \logical_op__invert_a$37
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_op__rc__rc_ok$7$next
+  wire width 1 \logical_op__invert_a$37$next
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 34 \mul_op__oe__oe$8
+  wire width 1 \logical_op__zero_a$38
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_op__oe__oe$8$next
+  wire width 1 \logical_op__zero_a$38$next
+  attribute \enum_base_type "CryIn"
+  attribute \enum_value_00 "ZERO"
+  attribute \enum_value_01 "ONE"
+  attribute \enum_value_10 "CA"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 35 \mul_op__oe__oe_ok$9
+  wire width 2 \logical_op__input_carry$39
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_op__oe__oe_ok$9$next
+  wire width 2 \logical_op__input_carry$39$next
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 36 \mul_op__invert_a$10
+  wire width 1 \logical_op__invert_out$40
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_op__invert_a$10$next
+  wire width 1 \logical_op__invert_out$40$next
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 37 \mul_op__zero_a$11
+  wire width 1 \logical_op__write_cr0$41
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_op__zero_a$11$next
+  wire width 1 \logical_op__write_cr0$41$next
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 38 \mul_op__invert_out$12
+  wire width 1 \logical_op__output_carry$42
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_op__invert_out$12$next
+  wire width 1 \logical_op__output_carry$42$next
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 39 \mul_op__write_cr0$13
+  wire width 1 \logical_op__is_32bit$43
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_op__write_cr0$13$next
+  wire width 1 \logical_op__is_32bit$43$next
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 40 \mul_op__is_32bit$14
+  wire width 1 \logical_op__is_signed$44
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_op__is_32bit$14$next
+  wire width 1 \logical_op__is_signed$44$next
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 41 \mul_op__is_signed$15
+  wire width 4 \logical_op__data_len$45
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_op__is_signed$15$next
+  wire width 4 \logical_op__data_len$45$next
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 32 output 42 \mul_op__insn$16
+  wire width 32 \logical_op__insn$46
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 32 \mul_op__insn$16$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
-  wire width 129 output 43 \o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
-  wire width 129 \o$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
-  wire width 1 output 44 \xer_so$17
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
-  wire width 1 \xer_so$17$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23"
-  wire width 1 output 45 \neg_res$18
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23"
-  wire width 1 \neg_res$18$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24"
-  wire width 1 output 46 \neg_res32$19
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24"
-  wire width 1 \neg_res32$19$next
-  cell \p$75 \p
-    connect \p_valid_i \p_valid_i
-    connect \p_ready_o \p_ready_o
+  wire width 32 \logical_op__insn$46$next
+  process $group_2
+    assign \logical_op__insn_type$2 7'0000000
+    assign \logical_op__fn_unit$3 11'00000000000
+    assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \logical_op__imm_data__imm_ok$5 1'0
+    assign \logical_op__rc__rc$6 1'0
+    assign \logical_op__rc__rc_ok$7 1'0
+    assign \logical_op__oe__oe$8 1'0
+    assign \logical_op__oe__oe_ok$9 1'0
+    assign \logical_op__invert_a$10 1'0
+    assign \logical_op__zero_a$11 1'0
+    assign \logical_op__input_carry$12 2'00
+    assign \logical_op__invert_out$13 1'0
+    assign \logical_op__write_cr0$14 1'0
+    assign \logical_op__output_carry$15 1'0
+    assign \logical_op__is_32bit$16 1'0
+    assign \logical_op__is_signed$17 1'0
+    assign \logical_op__data_len$18 4'0000
+    assign \logical_op__insn$19 32'00000000000000000000000000000000
+    assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_a$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn$46 \logical_op__data_len$45 \logical_op__is_signed$44 \logical_op__is_32bit$43 \logical_op__output_carry$42 \logical_op__write_cr0$41 \logical_op__invert_out$40 \logical_op__input_carry$39 \logical_op__zero_a$38 \logical_op__invert_a$37 { \logical_op__oe__oe_ok$36 \logical_op__oe__oe$35 } { \logical_op__rc__rc_ok$34 \logical_op__rc__rc$33 } { \logical_op__imm_data__imm_ok$32 \logical_op__imm_data__imm$31 } \logical_op__fn_unit$30 \logical_op__insn_type$29 }
+    sync init
   end
-  cell \n$76 \n
-    connect \n_valid_o \n_valid_o
-    connect \n_ready_i \n_ready_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
+  wire width 64 \ra$47
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
+  wire width 64 \ra$47$next
+  process $group_20
+    assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \ra$20 \ra$47
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
+  wire width 64 \rb$48
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
+  wire width 64 \rb$48$next
+  process $group_21
+    assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \rb$21 \rb$48
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
+  wire width 1 \xer_so$49
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
+  wire width 1 \xer_so$49$next
+  process $group_22
+    assign \xer_so$22 1'0
+    assign \xer_so$22 \xer_so$49
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160"
+  wire width 1 \divisor_neg$50
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160"
+  wire width 1 \divisor_neg$50$next
+  process $group_23
+    assign \divisor_neg$23 1'0
+    assign \divisor_neg$23 \divisor_neg$50
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161"
+  wire width 1 \dividend_neg$51
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161"
+  wire width 1 \dividend_neg$51$next
+  process $group_24
+    assign \dividend_neg$24 1'0
+    assign \dividend_neg$24 \dividend_neg$51
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167"
+  wire width 1 \dive_abs_ov32$52
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167"
+  wire width 1 \dive_abs_ov32$52$next
+  process $group_25
+    assign \dive_abs_ov32$25 1'0
+    assign \dive_abs_ov32$25 \dive_abs_ov32$52
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168"
+  wire width 1 \dive_abs_ov64$53
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168"
+  wire width 1 \dive_abs_ov64$53$next
+  process $group_26
+    assign \dive_abs_ov64$26 1'0
+    assign \dive_abs_ov64$26 \dive_abs_ov64$53
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162"
+  wire width 1 \div_by_zero$54
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162"
+  wire width 1 \div_by_zero$54$next
+  process $group_27
+    assign \div_by_zero$27 1'0
+    assign \div_by_zero$27 \div_by_zero$54
+    sync init
+  end
+  process $group_28
+    assign \quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \quotient_root \div_state_next_o_dividend_quotient [63:0]
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265"
+  wire width 192 $55
+  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265"
+  cell $pos $56
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 64
+    parameter \Y_WIDTH 192
+    connect \A \div_state_next_o_dividend_quotient [127:64]
+    connect \Y $55
+  end
+  process $group_29
+    assign \remainder 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
+    assign \remainder $55
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175"
+  wire width 1 $57
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:152"
+  wire width 1 \empty
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:152"
+  wire width 1 \empty$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175"
+  cell $not $58
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \empty
+    connect \Y $57
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:127"
+  wire width 1 $59
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:127"
+  cell $eq $60
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 7
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 7
+    parameter \Y_WIDTH 1
+    connect \A \div_state_next_o_q_bits_known
+    connect \B 7'1000000
+    connect \Y $59
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175"
+  wire width 1 $61
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:175"
+  cell $and $62
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $57
+    connect \B $59
+    connect \Y $61
+  end
+  process $group_30
+    assign \n_valid_o 1'0
+    assign \n_valid_o $61
+    sync init
+  end
+  process $group_31
+    assign \p_ready_o 1'0
+    assign \p_ready_o \empty
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:121"
+  wire width 7 \saved_state_q_bits_known
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:121"
+  wire width 7 \saved_state_q_bits_known$next
+  process $group_32
+    assign \saved_state_q_bits_known$next \saved_state_q_bits_known
+    assign \saved_state_q_bits_known$next \div_state_next_o_q_bits_known
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
+      case 1'1
+        assign \saved_state_q_bits_known$next 7'0000000
+    end
+    sync init
+      update \saved_state_q_bits_known 7'0000000
+    sync posedge \coresync_clk
+      update \saved_state_q_bits_known \saved_state_q_bits_known$next
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:123"
+  wire width 128 \saved_state_dividend_quotient
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:123"
+  wire width 128 \saved_state_dividend_quotient$next
+  process $group_33
+    assign \saved_state_dividend_quotient$next \saved_state_dividend_quotient
+    assign \saved_state_dividend_quotient$next \div_state_next_o_dividend_quotient
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
+      case 1'1
+        assign \saved_state_dividend_quotient$next 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+      update \saved_state_dividend_quotient 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
+    sync posedge \coresync_clk
+      update \saved_state_dividend_quotient \saved_state_dividend_quotient$next
+  end
+  process $group_34
+    assign \div_state_next_i_q_bits_known 7'0000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179"
+    switch { \empty }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179"
+      case 1'1
+        assign \div_state_next_i_q_bits_known \div_state_init_o_q_bits_known
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185"
+      case
+        assign \div_state_next_i_q_bits_known \saved_state_q_bits_known
+    end
+    sync init
+  end
+  process $group_35
+    assign \div_state_next_i_dividend_quotient 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179"
+    switch { \empty }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179"
+      case 1'1
+        assign \div_state_next_i_dividend_quotient \div_state_init_o_dividend_quotient
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185"
+      case
+        assign \div_state_next_i_dividend_quotient \saved_state_dividend_quotient
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19"
+  wire width 64 \divisor_radicand$63
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19"
+  wire width 64 \divisor_radicand$63$next
+  process $group_36
+    assign \div_state_next_divisor 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179"
+    switch { \empty }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179"
+      case 1'1
+        assign \div_state_next_divisor \divisor_radicand
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185"
+      case
+        assign \div_state_next_divisor \divisor_radicand$63
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:189"
+  wire width 1 $64
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:189"
+  cell $and $65
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \n_ready_i
+    connect \B \n_valid_o
+    connect \Y $64
+  end
+  process $group_37
+    assign \empty$next \empty
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179"
+    switch { \empty }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:182"
+        switch { \p_valid_i }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:182"
+          case 1'1
+            assign \empty$next 1'0
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185"
+      case
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:189"
+        switch { $64 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:189"
+          case 1'1
+            assign \empty$next 1'1
+        end
+    end
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
+      case 1'1
+        assign \empty$next 1'1
+    end
+    sync init
+      update \empty 1'1
+    sync posedge \coresync_clk
+      update \empty \empty$next
+  end
+  process $group_38
+    assign \muxid$28$next \muxid$28
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179"
+    switch { \empty }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:182"
+        switch { \p_valid_i }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:182"
+          case 1'1
+            assign \muxid$28$next \muxid
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185"
+      case
+    end
+    sync init
+      update \muxid$28 2'00
+    sync posedge \coresync_clk
+      update \muxid$28 \muxid$28$next
+  end
+  process $group_39
+    assign \logical_op__insn_type$29$next \logical_op__insn_type$29
+    assign \logical_op__fn_unit$30$next \logical_op__fn_unit$30
+    assign \logical_op__imm_data__imm$31$next \logical_op__imm_data__imm$31
+    assign \logical_op__imm_data__imm_ok$32$next \logical_op__imm_data__imm_ok$32
+    assign \logical_op__rc__rc$33$next \logical_op__rc__rc$33
+    assign \logical_op__rc__rc_ok$34$next \logical_op__rc__rc_ok$34
+    assign \logical_op__oe__oe$35$next \logical_op__oe__oe$35
+    assign \logical_op__oe__oe_ok$36$next \logical_op__oe__oe_ok$36
+    assign \logical_op__invert_a$37$next \logical_op__invert_a$37
+    assign \logical_op__zero_a$38$next \logical_op__zero_a$38
+    assign \logical_op__input_carry$39$next \logical_op__input_carry$39
+    assign \logical_op__invert_out$40$next \logical_op__invert_out$40
+    assign \logical_op__write_cr0$41$next \logical_op__write_cr0$41
+    assign \logical_op__output_carry$42$next \logical_op__output_carry$42
+    assign \logical_op__is_32bit$43$next \logical_op__is_32bit$43
+    assign \logical_op__is_signed$44$next \logical_op__is_signed$44
+    assign \logical_op__data_len$45$next \logical_op__data_len$45
+    assign \logical_op__insn$46$next \logical_op__insn$46
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179"
+    switch { \empty }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:182"
+        switch { \p_valid_i }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:182"
+          case 1'1
+            assign { \logical_op__insn$46$next \logical_op__data_len$45$next \logical_op__is_signed$44$next \logical_op__is_32bit$43$next \logical_op__output_carry$42$next \logical_op__write_cr0$41$next \logical_op__invert_out$40$next \logical_op__input_carry$39$next \logical_op__zero_a$38$next \logical_op__invert_a$37$next { \logical_op__oe__oe_ok$36$next \logical_op__oe__oe$35$next } { \logical_op__rc__rc_ok$34$next \logical_op__rc__rc$33$next } { \logical_op__imm_data__imm_ok$32$next \logical_op__imm_data__imm$31$next } \logical_op__fn_unit$30$next \logical_op__insn_type$29$next } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_a { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type }
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185"
+      case
+    end
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
+      case 1'1
+        assign \logical_op__imm_data__imm$31$next 64'0000000000000000000000000000000000000000000000000000000000000000
+        assign \logical_op__imm_data__imm_ok$32$next 1'0
+        assign \logical_op__rc__rc$33$next 1'0
+        assign \logical_op__rc__rc_ok$34$next 1'0
+        assign \logical_op__oe__oe$35$next 1'0
+        assign \logical_op__oe__oe_ok$36$next 1'0
+    end
+    sync init
+      update \logical_op__insn_type$29 7'0000000
+      update \logical_op__fn_unit$30 11'00000000000
+      update \logical_op__imm_data__imm$31 64'0000000000000000000000000000000000000000000000000000000000000000
+      update \logical_op__imm_data__imm_ok$32 1'0
+      update \logical_op__rc__rc$33 1'0
+      update \logical_op__rc__rc_ok$34 1'0
+      update \logical_op__oe__oe$35 1'0
+      update \logical_op__oe__oe_ok$36 1'0
+      update \logical_op__invert_a$37 1'0
+      update \logical_op__zero_a$38 1'0
+      update \logical_op__input_carry$39 2'00
+      update \logical_op__invert_out$40 1'0
+      update \logical_op__write_cr0$41 1'0
+      update \logical_op__output_carry$42 1'0
+      update \logical_op__is_32bit$43 1'0
+      update \logical_op__is_signed$44 1'0
+      update \logical_op__data_len$45 4'0000
+      update \logical_op__insn$46 32'00000000000000000000000000000000
+    sync posedge \coresync_clk
+      update \logical_op__insn_type$29 \logical_op__insn_type$29$next
+      update \logical_op__fn_unit$30 \logical_op__fn_unit$30$next
+      update \logical_op__imm_data__imm$31 \logical_op__imm_data__imm$31$next
+      update \logical_op__imm_data__imm_ok$32 \logical_op__imm_data__imm_ok$32$next
+      update \logical_op__rc__rc$33 \logical_op__rc__rc$33$next
+      update \logical_op__rc__rc_ok$34 \logical_op__rc__rc_ok$34$next
+      update \logical_op__oe__oe$35 \logical_op__oe__oe$35$next
+      update \logical_op__oe__oe_ok$36 \logical_op__oe__oe_ok$36$next
+      update \logical_op__invert_a$37 \logical_op__invert_a$37$next
+      update \logical_op__zero_a$38 \logical_op__zero_a$38$next
+      update \logical_op__input_carry$39 \logical_op__input_carry$39$next
+      update \logical_op__invert_out$40 \logical_op__invert_out$40$next
+      update \logical_op__write_cr0$41 \logical_op__write_cr0$41$next
+      update \logical_op__output_carry$42 \logical_op__output_carry$42$next
+      update \logical_op__is_32bit$43 \logical_op__is_32bit$43$next
+      update \logical_op__is_signed$44 \logical_op__is_signed$44$next
+      update \logical_op__data_len$45 \logical_op__data_len$45$next
+      update \logical_op__insn$46 \logical_op__insn$46$next
+  end
+  process $group_57
+    assign \ra$47$next \ra$47
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179"
+    switch { \empty }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:182"
+        switch { \p_valid_i }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:182"
+          case 1'1
+            assign \ra$47$next \ra
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185"
+      case
+    end
+    sync init
+      update \ra$47 64'0000000000000000000000000000000000000000000000000000000000000000
+    sync posedge \coresync_clk
+      update \ra$47 \ra$47$next
+  end
+  process $group_58
+    assign \rb$48$next \rb$48
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179"
+    switch { \empty }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:182"
+        switch { \p_valid_i }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:182"
+          case 1'1
+            assign \rb$48$next \rb
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185"
+      case
+    end
+    sync init
+      update \rb$48 64'0000000000000000000000000000000000000000000000000000000000000000
+    sync posedge \coresync_clk
+      update \rb$48 \rb$48$next
+  end
+  process $group_59
+    assign \xer_so$49$next \xer_so$49
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179"
+    switch { \empty }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:182"
+        switch { \p_valid_i }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:182"
+          case 1'1
+            assign \xer_so$49$next \xer_so
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185"
+      case
+    end
+    sync init
+      update \xer_so$49 1'0
+    sync posedge \coresync_clk
+      update \xer_so$49 \xer_so$49$next
+  end
+  process $group_60
+    assign \divisor_neg$50$next \divisor_neg$50
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179"
+    switch { \empty }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:182"
+        switch { \p_valid_i }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:182"
+          case 1'1
+            assign \divisor_neg$50$next \divisor_neg
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185"
+      case
+    end
+    sync init
+      update \divisor_neg$50 1'0
+    sync posedge \coresync_clk
+      update \divisor_neg$50 \divisor_neg$50$next
+  end
+  process $group_61
+    assign \dividend_neg$51$next \dividend_neg$51
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179"
+    switch { \empty }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:182"
+        switch { \p_valid_i }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:182"
+          case 1'1
+            assign \dividend_neg$51$next \dividend_neg
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185"
+      case
+    end
+    sync init
+      update \dividend_neg$51 1'0
+    sync posedge \coresync_clk
+      update \dividend_neg$51 \dividend_neg$51$next
+  end
+  process $group_62
+    assign \dive_abs_ov32$52$next \dive_abs_ov32$52
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179"
+    switch { \empty }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:182"
+        switch { \p_valid_i }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:182"
+          case 1'1
+            assign \dive_abs_ov32$52$next \dive_abs_ov32
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185"
+      case
+    end
+    sync init
+      update \dive_abs_ov32$52 1'0
+    sync posedge \coresync_clk
+      update \dive_abs_ov32$52 \dive_abs_ov32$52$next
+  end
+  process $group_63
+    assign \dive_abs_ov64$53$next \dive_abs_ov64$53
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179"
+    switch { \empty }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:182"
+        switch { \p_valid_i }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:182"
+          case 1'1
+            assign \dive_abs_ov64$53$next \dive_abs_ov64
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185"
+      case
+    end
+    sync init
+      update \dive_abs_ov64$53 1'0
+    sync posedge \coresync_clk
+      update \dive_abs_ov64$53 \dive_abs_ov64$53$next
+  end
+  process $group_64
+    assign \div_by_zero$54$next \div_by_zero$54
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179"
+    switch { \empty }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:182"
+        switch { \p_valid_i }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:182"
+          case 1'1
+            assign \div_by_zero$54$next \div_by_zero
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185"
+      case
+    end
+    sync init
+      update \div_by_zero$54 1'0
+    sync posedge \coresync_clk
+      update \div_by_zero$54 \div_by_zero$54$next
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18"
+  wire width 128 \dividend$66
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18"
+  wire width 128 \dividend$66$next
+  process $group_65
+    assign \dividend$66$next \dividend$66
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179"
+    switch { \empty }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:182"
+        switch { \p_valid_i }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:182"
+          case 1'1
+            assign \dividend$66$next \dividend
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185"
+      case
+    end
+    sync init
+      update \dividend$66 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
+    sync posedge \coresync_clk
+      update \dividend$66 \dividend$66$next
+  end
+  process $group_66
+    assign \divisor_radicand$63$next \divisor_radicand$63
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179"
+    switch { \empty }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:182"
+        switch { \p_valid_i }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:182"
+          case 1'1
+            assign \divisor_radicand$63$next \divisor_radicand
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185"
+      case
+    end
+    sync init
+      update \divisor_radicand$63 64'0000000000000000000000000000000000000000000000000000000000000000
+    sync posedge \coresync_clk
+      update \divisor_radicand$63 \divisor_radicand$63$next
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21"
+  wire width 2 \operation$67
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21"
+  wire width 2 \operation$67$next
+  process $group_67
+    assign \operation$67$next \operation$67
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179"
+    switch { \empty }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:179"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:182"
+        switch { \p_valid_i }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:182"
+          case 1'1
+            assign \operation$67$next \operation
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185"
+      case
+    end
+    sync init
+      update \operation$67 2'00
+    sync posedge \coresync_clk
+      update \operation$67 \operation$67$next
   end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_end.p"
+module \p$77
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153"
+  wire width 1 input 0 \p_valid_i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154"
+  wire width 1 input 1 \p_ready_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158"
+  wire width 1 \trigger
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205"
+  wire width 1 $1
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205"
+  cell $and $2
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \p_valid_i
+    connect \B \p_ready_o
+    connect \Y $1
+  end
+  process $group_0
+    assign \trigger 1'0
+    assign \trigger $1
+    sync init
+  end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_end.n"
+module \n$78
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
+  wire width 1 input 0 \n_valid_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
+  wire width 1 input 1 \n_ready_i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251"
+  wire width 1 \trigger
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298"
+  wire width 1 $1
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298"
+  cell $and $2
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \n_ready_i
+    connect \B \n_valid_o
+    connect \Y $1
+  end
+  process $group_0
+    assign \trigger 1'0
+    assign \trigger $1
+    sync init
+  end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_end.output_stage"
+module \output_stage
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
-  wire width 2 \mul2_muxid
+  wire width 2 input 0 \muxid
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
   attribute \enum_value_0000001 "OP_NOP"
@@ -91956,7 +92830,7 @@ module \mul_pipe2
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 7 \mul2_mul_op__insn_type
+  wire width 7 input 1 \logical_op__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -91970,45 +92844,61 @@ module \mul_pipe2
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 11 \mul2_mul_op__fn_unit
+  wire width 11 input 2 \logical_op__fn_unit
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 64 \mul2_mul_op__imm_data__imm
+  wire width 64 input 3 \logical_op__imm_data__imm
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul2_mul_op__imm_data__imm_ok
+  wire width 1 input 4 \logical_op__imm_data__imm_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul2_mul_op__rc__rc
+  wire width 1 input 5 \logical_op__rc__rc
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul2_mul_op__rc__rc_ok
+  wire width 1 input 6 \logical_op__rc__rc_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul2_mul_op__oe__oe
+  wire width 1 input 7 \logical_op__oe__oe
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul2_mul_op__oe__oe_ok
+  wire width 1 input 8 \logical_op__oe__oe_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul2_mul_op__invert_a
+  wire width 1 input 9 \logical_op__invert_a
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul2_mul_op__zero_a
+  wire width 1 input 10 \logical_op__zero_a
+  attribute \enum_base_type "CryIn"
+  attribute \enum_value_00 "ZERO"
+  attribute \enum_value_01 "ONE"
+  attribute \enum_value_10 "CA"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul2_mul_op__invert_out
+  wire width 2 input 11 \logical_op__input_carry
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul2_mul_op__write_cr0
+  wire width 1 input 12 \logical_op__invert_out
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul2_mul_op__is_32bit
+  wire width 1 input 13 \logical_op__write_cr0
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul2_mul_op__is_signed
+  wire width 1 input 14 \logical_op__output_carry
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 32 \mul2_mul_op__insn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
-  wire width 64 \mul2_ra
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
-  wire width 64 \mul2_rb
+  wire width 1 input 15 \logical_op__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 16 \logical_op__is_signed
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 4 input 17 \logical_op__data_len
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 input 18 \logical_op__insn
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
-  wire width 1 \mul2_xer_so
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11"
-  wire width 1 \mul2_neg_res
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12"
-  wire width 1 \mul2_neg_res32
+  wire width 1 input 19 \xer_so
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160"
+  wire width 1 input 20 \divisor_neg
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161"
+  wire width 1 input 21 \dividend_neg
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167"
+  wire width 1 input 22 \dive_abs_ov32
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168"
+  wire width 1 input 23 \dive_abs_ov64
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162"
+  wire width 1 input 24 \div_by_zero
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40"
+  wire width 64 input 25 \quotient_root
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:41"
+  wire width 192 input 26 \remainder
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
-  wire width 2 \mul2_muxid$20
+  wire width 2 output 27 \muxid$1
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
   attribute \enum_value_0000001 "OP_NOP"
@@ -92083,7 +92973,7 @@ module \mul_pipe2
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 7 \mul2_mul_op__insn_type$21
+  wire width 7 output 28 \logical_op__insn_type$2
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -92097,174 +92987,438 @@ module \mul_pipe2
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 11 \mul2_mul_op__fn_unit$22
+  wire width 11 output 29 \logical_op__fn_unit$3
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 64 \mul2_mul_op__imm_data__imm$23
+  wire width 64 output 30 \logical_op__imm_data__imm$4
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul2_mul_op__imm_data__imm_ok$24
+  wire width 1 output 31 \logical_op__imm_data__imm_ok$5
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul2_mul_op__rc__rc$25
+  wire width 1 output 32 \logical_op__rc__rc$6
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul2_mul_op__rc__rc_ok$26
+  wire width 1 output 33 \logical_op__rc__rc_ok$7
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul2_mul_op__oe__oe$27
+  wire width 1 output 34 \logical_op__oe__oe$8
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul2_mul_op__oe__oe_ok$28
+  wire width 1 output 35 \logical_op__oe__oe_ok$9
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul2_mul_op__invert_a$29
+  wire width 1 output 36 \logical_op__invert_a$10
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul2_mul_op__zero_a$30
+  wire width 1 output 37 \logical_op__zero_a$11
+  attribute \enum_base_type "CryIn"
+  attribute \enum_value_00 "ZERO"
+  attribute \enum_value_01 "ONE"
+  attribute \enum_value_10 "CA"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul2_mul_op__invert_out$31
+  wire width 2 output 38 \logical_op__input_carry$12
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul2_mul_op__write_cr0$32
+  wire width 1 output 39 \logical_op__invert_out$13
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul2_mul_op__is_32bit$33
+  wire width 1 output 40 \logical_op__write_cr0$14
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul2_mul_op__is_signed$34
+  wire width 1 output 41 \logical_op__output_carry$15
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 32 \mul2_mul_op__insn$35
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
-  wire width 129 \mul2_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
-  wire width 1 \mul2_xer_so$36
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23"
-  wire width 1 \mul2_neg_res$37
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24"
-  wire width 1 \mul2_neg_res32$38
-  cell \mul2 \mul2
-    connect \muxid \mul2_muxid
-    connect \mul_op__insn_type \mul2_mul_op__insn_type
-    connect \mul_op__fn_unit \mul2_mul_op__fn_unit
-    connect \mul_op__imm_data__imm \mul2_mul_op__imm_data__imm
-    connect \mul_op__imm_data__imm_ok \mul2_mul_op__imm_data__imm_ok
-    connect \mul_op__rc__rc \mul2_mul_op__rc__rc
-    connect \mul_op__rc__rc_ok \mul2_mul_op__rc__rc_ok
-    connect \mul_op__oe__oe \mul2_mul_op__oe__oe
-    connect \mul_op__oe__oe_ok \mul2_mul_op__oe__oe_ok
-    connect \mul_op__invert_a \mul2_mul_op__invert_a
-    connect \mul_op__zero_a \mul2_mul_op__zero_a
-    connect \mul_op__invert_out \mul2_mul_op__invert_out
-    connect \mul_op__write_cr0 \mul2_mul_op__write_cr0
-    connect \mul_op__is_32bit \mul2_mul_op__is_32bit
-    connect \mul_op__is_signed \mul2_mul_op__is_signed
-    connect \mul_op__insn \mul2_mul_op__insn
-    connect \ra \mul2_ra
-    connect \rb \mul2_rb
-    connect \xer_so \mul2_xer_so
-    connect \neg_res \mul2_neg_res
-    connect \neg_res32 \mul2_neg_res32
-    connect \muxid$1 \mul2_muxid$20
-    connect \mul_op__insn_type$2 \mul2_mul_op__insn_type$21
-    connect \mul_op__fn_unit$3 \mul2_mul_op__fn_unit$22
-    connect \mul_op__imm_data__imm$4 \mul2_mul_op__imm_data__imm$23
-    connect \mul_op__imm_data__imm_ok$5 \mul2_mul_op__imm_data__imm_ok$24
-    connect \mul_op__rc__rc$6 \mul2_mul_op__rc__rc$25
-    connect \mul_op__rc__rc_ok$7 \mul2_mul_op__rc__rc_ok$26
-    connect \mul_op__oe__oe$8 \mul2_mul_op__oe__oe$27
-    connect \mul_op__oe__oe_ok$9 \mul2_mul_op__oe__oe_ok$28
-    connect \mul_op__invert_a$10 \mul2_mul_op__invert_a$29
-    connect \mul_op__zero_a$11 \mul2_mul_op__zero_a$30
-    connect \mul_op__invert_out$12 \mul2_mul_op__invert_out$31
-    connect \mul_op__write_cr0$13 \mul2_mul_op__write_cr0$32
-    connect \mul_op__is_32bit$14 \mul2_mul_op__is_32bit$33
-    connect \mul_op__is_signed$15 \mul2_mul_op__is_signed$34
-    connect \mul_op__insn$16 \mul2_mul_op__insn$35
-    connect \o \mul2_o
-    connect \xer_so$17 \mul2_xer_so$36
-    connect \neg_res$18 \mul2_neg_res$37
-    connect \neg_res32$19 \mul2_neg_res32$38
+  wire width 1 output 42 \logical_op__is_32bit$16
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 43 \logical_op__is_signed$17
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 4 output 44 \logical_op__data_len$18
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 output 45 \logical_op__insn$19
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 64 output 46 \o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 output 47 \o_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 2 output 48 \xer_ov
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 output 49 \xer_ov_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 output 50 \xer_so$20
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:24"
+  wire width 1 \quotient_neg
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:55"
+  wire width 1 $21
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:55"
+  cell $xor $22
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \dividend_neg
+    connect \B \divisor_neg
+    connect \Y $21
   end
   process $group_0
-    assign \mul2_muxid 2'00
-    assign \mul2_muxid \muxid
+    assign \quotient_neg 1'0
+    assign \quotient_neg $21
     sync init
   end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:25"
+  wire width 1 \remainder_neg
   process $group_1
-    assign \mul2_mul_op__insn_type 7'0000000
-    assign \mul2_mul_op__fn_unit 11'00000000000
-    assign \mul2_mul_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \mul2_mul_op__imm_data__imm_ok 1'0
-    assign \mul2_mul_op__rc__rc 1'0
-    assign \mul2_mul_op__rc__rc_ok 1'0
-    assign \mul2_mul_op__oe__oe 1'0
-    assign \mul2_mul_op__oe__oe_ok 1'0
-    assign \mul2_mul_op__invert_a 1'0
-    assign \mul2_mul_op__zero_a 1'0
-    assign \mul2_mul_op__invert_out 1'0
-    assign \mul2_mul_op__write_cr0 1'0
-    assign \mul2_mul_op__is_32bit 1'0
-    assign \mul2_mul_op__is_signed 1'0
-    assign \mul2_mul_op__insn 32'00000000000000000000000000000000
-    assign { \mul2_mul_op__insn \mul2_mul_op__is_signed \mul2_mul_op__is_32bit \mul2_mul_op__write_cr0 \mul2_mul_op__invert_out \mul2_mul_op__zero_a \mul2_mul_op__invert_a { \mul2_mul_op__oe__oe_ok \mul2_mul_op__oe__oe } { \mul2_mul_op__rc__rc_ok \mul2_mul_op__rc__rc } { \mul2_mul_op__imm_data__imm_ok \mul2_mul_op__imm_data__imm } \mul2_mul_op__fn_unit \mul2_mul_op__insn_type } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__invert_out \mul_op__zero_a \mul_op__invert_a { \mul_op__oe__oe_ok \mul_op__oe__oe } { \mul_op__rc__rc_ok \mul_op__rc__rc } { \mul_op__imm_data__imm_ok \mul_op__imm_data__imm } \mul_op__fn_unit \mul_op__insn_type }
+    assign \remainder_neg 1'0
+    assign \remainder_neg \dividend_neg
     sync init
   end
-  process $group_16
-    assign \mul2_ra 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \mul2_ra \ra
-    sync init
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:26"
+  wire width 65 \quotient_65
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:65"
+  wire width 65 $23
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:65"
+  cell $neg $24
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 64
+    parameter \Y_WIDTH 65
+    connect \A \quotient_root
+    connect \Y $23
   end
-  process $group_17
-    assign \mul2_rb 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \mul2_rb \rb
-    sync init
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40"
+  wire width 65 $25
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40"
+  cell $pos $26
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 64
+    parameter \Y_WIDTH 65
+    connect \A \quotient_root
+    connect \Y $25
   end
-  process $group_18
-    assign \mul2_xer_so 1'0
-    assign \mul2_xer_so \xer_so
-    sync init
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:65"
+  wire width 65 $27
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:65"
+  cell $mux $28
+    parameter \WIDTH 65
+    connect \A $25
+    connect \B $23
+    connect \S \quotient_neg
+    connect \Y $27
   end
-  process $group_19
-    assign \mul2_neg_res 1'0
-    assign \mul2_neg_res \neg_res
+  process $group_2
+    assign \quotient_65 65'00000000000000000000000000000000000000000000000000000000000000000
+    assign \quotient_65 $27
     sync init
   end
-  process $group_20
-    assign \mul2_neg_res32 1'0
-    assign \mul2_neg_res32 \neg_res32
-    sync init
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:27"
+  wire width 64 \remainder_64
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67"
+  wire width 65 $29
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67"
+  wire width 65 $30
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67"
+  cell $neg $31
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 64
+    parameter \Y_WIDTH 65
+    connect \A \remainder [127:64]
+    connect \Y $30
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621"
-  wire width 1 \p_valid_i$39
-  process $group_21
-    assign \p_valid_i$39 1'0
-    assign \p_valid_i$39 \p_valid_i
+  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265"
+  wire width 65 $32
+  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265"
+  cell $pos $33
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 64
+    parameter \Y_WIDTH 65
+    connect \A \remainder [127:64]
+    connect \Y $32
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67"
+  wire width 65 $34
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67"
+  cell $mux $35
+    parameter \WIDTH 65
+    connect \A $32
+    connect \B $30
+    connect \S \remainder_neg
+    connect \Y $34
+  end
+  connect $29 $34
+  process $group_3
+    assign \remainder_64 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \remainder_64 $29 [63:0]
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619"
-  wire width 1 \n_i_rdy_data
-  process $group_22
-    assign \n_i_rdy_data 1'0
-    assign \n_i_rdy_data \n_ready_i
+  wire width 1 $verilog_initial_trigger
+  process $group_4
+    assign \xer_ov_ok 1'0
+    assign \xer_ov_ok 1'1
+    assign $verilog_initial_trigger $verilog_initial_trigger
     sync init
+      update $verilog_initial_trigger 1'0
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620"
-  wire width 1 \p_valid_i_p_ready_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:75"
+  wire width 1 \ov
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:78"
+  wire width 1 $36
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:78"
+  cell $not $37
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \logical_op__is_32bit
+    connect \Y $36
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:80"
+  wire width 1 $38
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:80"
+  cell $xor $39
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \quotient_65 [64]
+    connect \B \quotient_65 [63]
+    connect \Y $38
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:80"
   wire width 1 $40
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:80"
   cell $and $41
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \p_valid_i$39
-    connect \B \p_ready_o
+    connect \A \logical_op__is_signed
+    connect \B $38
     connect \Y $40
   end
-  process $group_23
-    assign \p_valid_i_p_ready_o 1'0
-    assign \p_valid_i_p_ready_o $40
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:84"
+  wire width 1 $42
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:84"
+  cell $ne $43
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \quotient_65 [32]
+    connect \B \quotient_65 [31]
+    connect \Y $42
+  end
+  process $group_5
+    assign \ov 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:76"
+    switch { \logical_op__is_signed $36 \div_by_zero }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:76"
+      case 3'--1
+        assign \ov 1'1
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:78"
+      case 3'-1-
+        assign \ov \dive_abs_ov64
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:80"
+        switch { $40 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:80"
+          case 1'1
+            assign \ov 1'1
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:82"
+      case 3'1--
+        assign \ov \dive_abs_ov32
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:84"
+        switch { $42 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:84"
+          case 1'1
+            assign \ov 1'1
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:86"
+      case
+        assign \ov \dive_abs_ov32
+    end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
-  wire width 2 \muxid$42
-  process $group_24
-    assign \muxid$42 2'00
-    assign \muxid$42 \mul2_muxid$20
+  process $group_6
+    assign \xer_ov 2'00
+    assign \xer_ov { \ov \ov }
+    sync init
+  end
+  process $group_7
+    assign \o_ok 1'0
+    assign \o_ok 1'1
+    assign $verilog_initial_trigger $verilog_initial_trigger
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:96"
+  wire width 1 $44
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:96"
+  cell $not $45
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \ov
+    connect \Y $44
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:102"
+  wire width 64 $46
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:102"
+  cell $pos $47
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 32
+    parameter \Y_WIDTH 64
+    connect \A \quotient_65 [31:0]
+    connect \Y $46
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:104"
+  wire width 64 $48
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:104"
+  cell $pos $49
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 32
+    parameter \Y_WIDTH 64
+    connect \A \quotient_65 [31:0]
+    connect \Y $48
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:111"
+  wire width 64 $50
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:111"
+  cell $pos $51
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 32
+    parameter \Y_WIDTH 64
+    connect \A \quotient_65 [31:0]
+    connect \Y $50
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:113"
+  wire width 64 $52
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:113"
+  cell $pos $53
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 32
+    parameter \Y_WIDTH 64
+    connect \A \quotient_65 [31:0]
+    connect \Y $52
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:120"
+  wire width 64 $54
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:120"
+  cell $pos $55
+    parameter \A_SIGNED 1
+    parameter \A_WIDTH 32
+    parameter \Y_WIDTH 64
+    connect \A \remainder_64 [31:0]
+    connect \Y $54
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:122"
+  wire width 64 $56
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:122"
+  cell $pos $57
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 32
+    parameter \Y_WIDTH 64
+    connect \A \remainder_64 [31:0]
+    connect \Y $56
+  end
+  process $group_8
+    assign \o 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:96"
+    switch { $44 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:96"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:97"
+        switch \logical_op__insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:98"
+          attribute \nmigen.decoding "OP_DIVE/30"
+          case 7'0011110
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:99"
+            switch { \logical_op__is_32bit }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:99"
+              case 1'1
+                attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:100"
+                switch { \logical_op__is_signed }
+                  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:100"
+                  case 1'1
+                    assign \o $46
+                  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:103"
+                  case
+                    assign \o $48
+                end
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:105"
+              case
+                assign \o \quotient_65 [63:0]
+            end
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:107"
+          attribute \nmigen.decoding "OP_DIV/29"
+          case 7'0011101
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:108"
+            switch { \logical_op__is_32bit }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:108"
+              case 1'1
+                attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:109"
+                switch { \logical_op__is_signed }
+                  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:109"
+                  case 1'1
+                    assign \o $50
+                  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:112"
+                  case
+                    assign \o $52
+                end
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:114"
+              case
+                assign \o \quotient_65 [63:0]
+            end
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:116"
+          attribute \nmigen.decoding "OP_MOD/47"
+          case 7'0101111
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:117"
+            switch { \logical_op__is_32bit }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:117"
+              case 1'1
+                attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:118"
+                switch { \logical_op__is_signed }
+                  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:118"
+                  case 1'1
+                    assign \o $54
+                  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:121"
+                  case
+                    assign \o $56
+                end
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:123"
+              case
+                assign \o \remainder_64
+            end
+        end
+    end
+    sync init
+  end
+  process $group_9
+    assign \xer_so$20 1'0
+    assign \xer_so$20 \xer_so
+    sync init
+  end
+  process $group_10
+    assign \muxid$1 2'00
+    assign \muxid$1 \muxid
+    sync init
+  end
+  process $group_11
+    assign \logical_op__insn_type$2 7'0000000
+    assign \logical_op__fn_unit$3 11'00000000000
+    assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \logical_op__imm_data__imm_ok$5 1'0
+    assign \logical_op__rc__rc$6 1'0
+    assign \logical_op__rc__rc_ok$7 1'0
+    assign \logical_op__oe__oe$8 1'0
+    assign \logical_op__oe__oe_ok$9 1'0
+    assign \logical_op__invert_a$10 1'0
+    assign \logical_op__zero_a$11 1'0
+    assign \logical_op__input_carry$12 2'00
+    assign \logical_op__invert_out$13 1'0
+    assign \logical_op__write_cr0$14 1'0
+    assign \logical_op__output_carry$15 1'0
+    assign \logical_op__is_32bit$16 1'0
+    assign \logical_op__is_signed$17 1'0
+    assign \logical_op__data_len$18 4'0000
+    assign \logical_op__insn$19 32'00000000000000000000000000000000
+    assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_a$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_a { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type }
     sync init
   end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_end.output"
+module \output$79
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
+  wire width 2 input 0 \muxid
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
   attribute \enum_value_0000001 "OP_NOP"
@@ -92339,7 +93493,7 @@ module \mul_pipe2
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 7 \mul_op__insn_type$43
+  wire width 7 input 1 \logical_op__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -92353,325 +93507,559 @@ module \mul_pipe2
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 11 \mul_op__fn_unit$44
+  wire width 11 input 2 \logical_op__fn_unit
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 64 \mul_op__imm_data__imm$45
+  wire width 64 input 3 \logical_op__imm_data__imm
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_op__imm_data__imm_ok$46
+  wire width 1 input 4 \logical_op__imm_data__imm_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_op__rc__rc$47
+  wire width 1 input 5 \logical_op__rc__rc
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_op__rc__rc_ok$48
+  wire width 1 input 6 \logical_op__rc__rc_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_op__oe__oe$49
+  wire width 1 input 7 \logical_op__oe__oe
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_op__oe__oe_ok$50
+  wire width 1 input 8 \logical_op__oe__oe_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_op__invert_a$51
+  wire width 1 input 9 \logical_op__invert_a
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_op__zero_a$52
+  wire width 1 input 10 \logical_op__zero_a
+  attribute \enum_base_type "CryIn"
+  attribute \enum_value_00 "ZERO"
+  attribute \enum_value_01 "ONE"
+  attribute \enum_value_10 "CA"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_op__invert_out$53
+  wire width 2 input 11 \logical_op__input_carry
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_op__write_cr0$54
+  wire width 1 input 12 \logical_op__invert_out
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_op__is_32bit$55
+  wire width 1 input 13 \logical_op__write_cr0
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_op__is_signed$56
+  wire width 1 input 14 \logical_op__output_carry
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 32 \mul_op__insn$57
-  process $group_25
-    assign \mul_op__insn_type$43 7'0000000
-    assign \mul_op__fn_unit$44 11'00000000000
-    assign \mul_op__imm_data__imm$45 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \mul_op__imm_data__imm_ok$46 1'0
-    assign \mul_op__rc__rc$47 1'0
-    assign \mul_op__rc__rc_ok$48 1'0
-    assign \mul_op__oe__oe$49 1'0
-    assign \mul_op__oe__oe_ok$50 1'0
-    assign \mul_op__invert_a$51 1'0
-    assign \mul_op__zero_a$52 1'0
-    assign \mul_op__invert_out$53 1'0
-    assign \mul_op__write_cr0$54 1'0
-    assign \mul_op__is_32bit$55 1'0
-    assign \mul_op__is_signed$56 1'0
-    assign \mul_op__insn$57 32'00000000000000000000000000000000
-    assign { \mul_op__insn$57 \mul_op__is_signed$56 \mul_op__is_32bit$55 \mul_op__write_cr0$54 \mul_op__invert_out$53 \mul_op__zero_a$52 \mul_op__invert_a$51 { \mul_op__oe__oe_ok$50 \mul_op__oe__oe$49 } { \mul_op__rc__rc_ok$48 \mul_op__rc__rc$47 } { \mul_op__imm_data__imm_ok$46 \mul_op__imm_data__imm$45 } \mul_op__fn_unit$44 \mul_op__insn_type$43 } { \mul2_mul_op__insn$35 \mul2_mul_op__is_signed$34 \mul2_mul_op__is_32bit$33 \mul2_mul_op__write_cr0$32 \mul2_mul_op__invert_out$31 \mul2_mul_op__zero_a$30 \mul2_mul_op__invert_a$29 { \mul2_mul_op__oe__oe_ok$28 \mul2_mul_op__oe__oe$27 } { \mul2_mul_op__rc__rc_ok$26 \mul2_mul_op__rc__rc$25 } { \mul2_mul_op__imm_data__imm_ok$24 \mul2_mul_op__imm_data__imm$23 } \mul2_mul_op__fn_unit$22 \mul2_mul_op__insn_type$21 }
-    sync init
+  wire width 1 input 15 \logical_op__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 16 \logical_op__is_signed
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 4 input 17 \logical_op__data_len
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 input 18 \logical_op__insn
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 64 input 19 \o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 input 20 \o_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 4 input 21 \cr_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 2 input 22 \xer_ov
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 input 23 \xer_so
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
+  wire width 2 output 24 \muxid$1
+  attribute \enum_base_type "MicrOp"
+  attribute \enum_value_0000000 "OP_ILLEGAL"
+  attribute \enum_value_0000001 "OP_NOP"
+  attribute \enum_value_0000010 "OP_ADD"
+  attribute \enum_value_0000011 "OP_ADDPCIS"
+  attribute \enum_value_0000100 "OP_AND"
+  attribute \enum_value_0000101 "OP_ATTN"
+  attribute \enum_value_0000110 "OP_B"
+  attribute \enum_value_0000111 "OP_BC"
+  attribute \enum_value_0001000 "OP_BCREG"
+  attribute \enum_value_0001001 "OP_BPERM"
+  attribute \enum_value_0001010 "OP_CMP"
+  attribute \enum_value_0001011 "OP_CMPB"
+  attribute \enum_value_0001100 "OP_CMPEQB"
+  attribute \enum_value_0001101 "OP_CMPRB"
+  attribute \enum_value_0001110 "OP_CNTZ"
+  attribute \enum_value_0001111 "OP_CRAND"
+  attribute \enum_value_0010000 "OP_CRANDC"
+  attribute \enum_value_0010001 "OP_CREQV"
+  attribute \enum_value_0010010 "OP_CRNAND"
+  attribute \enum_value_0010011 "OP_CRNOR"
+  attribute \enum_value_0010100 "OP_CROR"
+  attribute \enum_value_0010101 "OP_CRORC"
+  attribute \enum_value_0010110 "OP_CRXOR"
+  attribute \enum_value_0010111 "OP_DARN"
+  attribute \enum_value_0011000 "OP_DCBF"
+  attribute \enum_value_0011001 "OP_DCBST"
+  attribute \enum_value_0011010 "OP_DCBT"
+  attribute \enum_value_0011011 "OP_DCBTST"
+  attribute \enum_value_0011100 "OP_DCBZ"
+  attribute \enum_value_0011101 "OP_DIV"
+  attribute \enum_value_0011110 "OP_DIVE"
+  attribute \enum_value_0011111 "OP_EXTS"
+  attribute \enum_value_0100000 "OP_EXTSWSLI"
+  attribute \enum_value_0100001 "OP_ICBI"
+  attribute \enum_value_0100010 "OP_ICBT"
+  attribute \enum_value_0100011 "OP_ISEL"
+  attribute \enum_value_0100100 "OP_ISYNC"
+  attribute \enum_value_0100101 "OP_LOAD"
+  attribute \enum_value_0100110 "OP_STORE"
+  attribute \enum_value_0100111 "OP_MADDHD"
+  attribute \enum_value_0101000 "OP_MADDHDU"
+  attribute \enum_value_0101001 "OP_MADDLD"
+  attribute \enum_value_0101010 "OP_MCRF"
+  attribute \enum_value_0101011 "OP_MCRXR"
+  attribute \enum_value_0101100 "OP_MCRXRX"
+  attribute \enum_value_0101101 "OP_MFCR"
+  attribute \enum_value_0101110 "OP_MFSPR"
+  attribute \enum_value_0101111 "OP_MOD"
+  attribute \enum_value_0110000 "OP_MTCRF"
+  attribute \enum_value_0110001 "OP_MTSPR"
+  attribute \enum_value_0110010 "OP_MUL_L64"
+  attribute \enum_value_0110011 "OP_MUL_H64"
+  attribute \enum_value_0110100 "OP_MUL_H32"
+  attribute \enum_value_0110101 "OP_OR"
+  attribute \enum_value_0110110 "OP_POPCNT"
+  attribute \enum_value_0110111 "OP_PRTY"
+  attribute \enum_value_0111000 "OP_RLC"
+  attribute \enum_value_0111001 "OP_RLCL"
+  attribute \enum_value_0111010 "OP_RLCR"
+  attribute \enum_value_0111011 "OP_SETB"
+  attribute \enum_value_0111100 "OP_SHL"
+  attribute \enum_value_0111101 "OP_SHR"
+  attribute \enum_value_0111110 "OP_SYNC"
+  attribute \enum_value_0111111 "OP_TRAP"
+  attribute \enum_value_1000011 "OP_XOR"
+  attribute \enum_value_1000100 "OP_SIM_CONFIG"
+  attribute \enum_value_1000101 "OP_CROP"
+  attribute \enum_value_1000110 "OP_RFID"
+  attribute \enum_value_1000111 "OP_MFMSR"
+  attribute \enum_value_1001000 "OP_MTMSRD"
+  attribute \enum_value_1001001 "OP_SC"
+  attribute \enum_value_1001010 "OP_MTMSR"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 output 25 \logical_op__insn_type$2
+  attribute \enum_base_type "Function"
+  attribute \enum_value_00000000000 "NONE"
+  attribute \enum_value_00000000010 "ALU"
+  attribute \enum_value_00000000100 "LDST"
+  attribute \enum_value_00000001000 "SHIFT_ROT"
+  attribute \enum_value_00000010000 "LOGICAL"
+  attribute \enum_value_00000100000 "BRANCH"
+  attribute \enum_value_00001000000 "CR"
+  attribute \enum_value_00010000000 "TRAP"
+  attribute \enum_value_00100000000 "MUL"
+  attribute \enum_value_01000000000 "DIV"
+  attribute \enum_value_10000000000 "SPR"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 output 26 \logical_op__fn_unit$3
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 output 27 \logical_op__imm_data__imm$4
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 28 \logical_op__imm_data__imm_ok$5
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 29 \logical_op__rc__rc$6
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 30 \logical_op__rc__rc_ok$7
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 31 \logical_op__oe__oe$8
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 32 \logical_op__oe__oe_ok$9
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 33 \logical_op__invert_a$10
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 34 \logical_op__zero_a$11
+  attribute \enum_base_type "CryIn"
+  attribute \enum_value_00 "ZERO"
+  attribute \enum_value_01 "ONE"
+  attribute \enum_value_10 "CA"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 2 output 35 \logical_op__input_carry$12
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 36 \logical_op__invert_out$13
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 37 \logical_op__write_cr0$14
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 38 \logical_op__output_carry$15
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 39 \logical_op__is_32bit$16
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 40 \logical_op__is_signed$17
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 4 output 41 \logical_op__data_len$18
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 output 42 \logical_op__insn$19
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 64 output 43 \o$20
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 output 44 \o_ok$21
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 4 output 45 \cr_a$22
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 output 46 \cr_a_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 2 output 47 \xer_ov$23
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 output 48 \xer_ov_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 output 49 \xer_so$24
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 output 50 \xer_so_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:23"
+  wire width 65 \o$25
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:26"
+  wire width 65 $26
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:26"
+  wire width 64 $27
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:26"
+  cell $not $28
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 64
+    parameter \Y_WIDTH 64
+    connect \A \o
+    connect \Y $27
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
-  wire width 129 \o$58
-  process $group_40
-    assign \o$58 129'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
-    assign \o$58 \mul2_o
-    sync init
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:26"
+  cell $pos $29
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 64
+    parameter \Y_WIDTH 65
+    connect \A $27
+    connect \Y $26
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
-  wire width 1 \xer_so$59
-  process $group_41
-    assign \xer_so$59 1'0
-    assign \xer_so$59 \mul2_xer_so$36
-    sync init
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 65 $30
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  cell $pos $31
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 64
+    parameter \Y_WIDTH 65
+    connect \A \o
+    connect \Y $30
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23"
-  wire width 1 \neg_res$60
-  process $group_42
-    assign \neg_res$60 1'0
-    assign \neg_res$60 \mul2_neg_res$37
+  process $group_0
+    assign \o$25 65'00000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:25"
+    switch { \logical_op__invert_out }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:25"
+      case 1'1
+        assign \o$25 $26
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:27"
+      case
+        assign \o$25 $30
+    end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24"
-  wire width 1 \neg_res32$61
-  process $group_43
-    assign \neg_res32$61 1'0
-    assign \neg_res32$61 \mul2_neg_res32$38
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:35"
+  wire width 64 \target
+  process $group_1
+    assign \target 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \target \o$25 [63:0]
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615"
-  wire width 1 \r_busy
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615"
-  wire width 1 \r_busy$next
-  process $group_44
-    assign \r_busy$next \r_busy
-    attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
-    switch { \n_i_rdy_data \p_valid_i_p_ready_o }
-      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
-      case 2'-1
-        assign \r_busy$next 1'1
-      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
-      case 2'1-
-        assign \r_busy$next 1'0
-    end
-    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
-      case 1'1
-        assign \r_busy$next 1'0
-    end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:54"
+  wire width 1 \is_cmp
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:63"
+  wire width 1 $32
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:63"
+  cell $eq $33
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 7
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 7
+    parameter \Y_WIDTH 1
+    connect \A \logical_op__insn_type
+    connect \B 7'0001010
+    connect \Y $32
+  end
+  process $group_2
+    assign \is_cmp 1'0
+    assign \is_cmp $32
     sync init
-      update \r_busy 1'0
-    sync posedge \clk
-      update \r_busy \r_busy$next
   end
-  process $group_45
-    assign \muxid$1$next \muxid$1
-    attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
-    switch { \n_i_rdy_data \p_valid_i_p_ready_o }
-      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
-      case 2'-1
-        assign \muxid$1$next \muxid$42
-      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
-      case 2'1-
-        assign \muxid$1$next \muxid$42
-    end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:55"
+  wire width 1 \is_cmpeqb
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:64"
+  wire width 1 $34
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:64"
+  cell $eq $35
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 7
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 7
+    parameter \Y_WIDTH 1
+    connect \A \logical_op__insn_type
+    connect \B 7'0001100
+    connect \Y $34
+  end
+  process $group_3
+    assign \is_cmpeqb 1'0
+    assign \is_cmpeqb $34
     sync init
-      update \muxid$1 2'00
-    sync posedge \clk
-      update \muxid$1 \muxid$1$next
   end
-  process $group_46
-    assign \mul_op__insn_type$2$next \mul_op__insn_type$2
-    assign \mul_op__fn_unit$3$next \mul_op__fn_unit$3
-    assign \mul_op__imm_data__imm$4$next \mul_op__imm_data__imm$4
-    assign \mul_op__imm_data__imm_ok$5$next \mul_op__imm_data__imm_ok$5
-    assign \mul_op__rc__rc$6$next \mul_op__rc__rc$6
-    assign \mul_op__rc__rc_ok$7$next \mul_op__rc__rc_ok$7
-    assign \mul_op__oe__oe$8$next \mul_op__oe__oe$8
-    assign \mul_op__oe__oe_ok$9$next \mul_op__oe__oe_ok$9
-    assign \mul_op__invert_a$10$next \mul_op__invert_a$10
-    assign \mul_op__zero_a$11$next \mul_op__zero_a$11
-    assign \mul_op__invert_out$12$next \mul_op__invert_out$12
-    assign \mul_op__write_cr0$13$next \mul_op__write_cr0$13
-    assign \mul_op__is_32bit$14$next \mul_op__is_32bit$14
-    assign \mul_op__is_signed$15$next \mul_op__is_signed$15
-    assign \mul_op__insn$16$next \mul_op__insn$16
-    attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
-    switch { \n_i_rdy_data \p_valid_i_p_ready_o }
-      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
-      case 2'-1
-        assign { \mul_op__insn$16$next \mul_op__is_signed$15$next \mul_op__is_32bit$14$next \mul_op__write_cr0$13$next \mul_op__invert_out$12$next \mul_op__zero_a$11$next \mul_op__invert_a$10$next { \mul_op__oe__oe_ok$9$next \mul_op__oe__oe$8$next } { \mul_op__rc__rc_ok$7$next \mul_op__rc__rc$6$next } { \mul_op__imm_data__imm_ok$5$next \mul_op__imm_data__imm$4$next } \mul_op__fn_unit$3$next \mul_op__insn_type$2$next } { \mul_op__insn$57 \mul_op__is_signed$56 \mul_op__is_32bit$55 \mul_op__write_cr0$54 \mul_op__invert_out$53 \mul_op__zero_a$52 \mul_op__invert_a$51 { \mul_op__oe__oe_ok$50 \mul_op__oe__oe$49 } { \mul_op__rc__rc_ok$48 \mul_op__rc__rc$47 } { \mul_op__imm_data__imm_ok$46 \mul_op__imm_data__imm$45 } \mul_op__fn_unit$44 \mul_op__insn_type$43 }
-      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
-      case 2'1-
-        assign { \mul_op__insn$16$next \mul_op__is_signed$15$next \mul_op__is_32bit$14$next \mul_op__write_cr0$13$next \mul_op__invert_out$12$next \mul_op__zero_a$11$next \mul_op__invert_a$10$next { \mul_op__oe__oe_ok$9$next \mul_op__oe__oe$8$next } { \mul_op__rc__rc_ok$7$next \mul_op__rc__rc$6$next } { \mul_op__imm_data__imm_ok$5$next \mul_op__imm_data__imm$4$next } \mul_op__fn_unit$3$next \mul_op__insn_type$2$next } { \mul_op__insn$57 \mul_op__is_signed$56 \mul_op__is_32bit$55 \mul_op__write_cr0$54 \mul_op__invert_out$53 \mul_op__zero_a$52 \mul_op__invert_a$51 { \mul_op__oe__oe_ok$50 \mul_op__oe__oe$49 } { \mul_op__rc__rc_ok$48 \mul_op__rc__rc$47 } { \mul_op__imm_data__imm_ok$46 \mul_op__imm_data__imm$45 } \mul_op__fn_unit$44 \mul_op__insn_type$43 }
-    end
-    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:53"
+  wire width 1 \msb_test
+  process $group_4
+    assign \msb_test 1'0
+    assign \msb_test \target [63]
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:50"
+  wire width 1 \is_nzero
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71"
+  wire width 1 $36
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71"
+  cell $reduce_bool $37
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 64
+    parameter \Y_WIDTH 1
+    connect \A \target
+    connect \Y $36
+  end
+  process $group_5
+    assign \is_nzero 1'0
+    assign \is_nzero $36
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:51"
+  wire width 1 \is_positive
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77"
+  wire width 1 $38
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77"
+  cell $not $39
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \msb_test
+    connect \Y $38
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77"
+  wire width 1 $40
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77"
+  cell $and $41
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \is_nzero
+    connect \B $38
+    connect \Y $40
+  end
+  process $group_6
+    assign \is_positive 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:72"
+    switch { \is_cmp }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:72"
       case 1'1
-        assign \mul_op__imm_data__imm$4$next 64'0000000000000000000000000000000000000000000000000000000000000000
-        assign \mul_op__imm_data__imm_ok$5$next 1'0
-        assign \mul_op__rc__rc$6$next 1'0
-        assign \mul_op__rc__rc_ok$7$next 1'0
-        assign \mul_op__oe__oe$8$next 1'0
-        assign \mul_op__oe__oe_ok$9$next 1'0
+        assign \is_positive \msb_test
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:75"
+      case
+        assign \is_positive $40
     end
     sync init
-      update \mul_op__insn_type$2 7'0000000
-      update \mul_op__fn_unit$3 11'00000000000
-      update \mul_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000
-      update \mul_op__imm_data__imm_ok$5 1'0
-      update \mul_op__rc__rc$6 1'0
-      update \mul_op__rc__rc_ok$7 1'0
-      update \mul_op__oe__oe$8 1'0
-      update \mul_op__oe__oe_ok$9 1'0
-      update \mul_op__invert_a$10 1'0
-      update \mul_op__zero_a$11 1'0
-      update \mul_op__invert_out$12 1'0
-      update \mul_op__write_cr0$13 1'0
-      update \mul_op__is_32bit$14 1'0
-      update \mul_op__is_signed$15 1'0
-      update \mul_op__insn$16 32'00000000000000000000000000000000
-    sync posedge \clk
-      update \mul_op__insn_type$2 \mul_op__insn_type$2$next
-      update \mul_op__fn_unit$3 \mul_op__fn_unit$3$next
-      update \mul_op__imm_data__imm$4 \mul_op__imm_data__imm$4$next
-      update \mul_op__imm_data__imm_ok$5 \mul_op__imm_data__imm_ok$5$next
-      update \mul_op__rc__rc$6 \mul_op__rc__rc$6$next
-      update \mul_op__rc__rc_ok$7 \mul_op__rc__rc_ok$7$next
-      update \mul_op__oe__oe$8 \mul_op__oe__oe$8$next
-      update \mul_op__oe__oe_ok$9 \mul_op__oe__oe_ok$9$next
-      update \mul_op__invert_a$10 \mul_op__invert_a$10$next
-      update \mul_op__zero_a$11 \mul_op__zero_a$11$next
-      update \mul_op__invert_out$12 \mul_op__invert_out$12$next
-      update \mul_op__write_cr0$13 \mul_op__write_cr0$13$next
-      update \mul_op__is_32bit$14 \mul_op__is_32bit$14$next
-      update \mul_op__is_signed$15 \mul_op__is_signed$15$next
-      update \mul_op__insn$16 \mul_op__insn$16$next
   end
-  process $group_61
-    assign \o$next \o
-    attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
-    switch { \n_i_rdy_data \p_valid_i_p_ready_o }
-      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
-      case 2'-1
-        assign \o$next \o$58
-      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
-      case 2'1-
-        assign \o$next \o$58
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:52"
+  wire width 1 \is_negative
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:74"
+  wire width 1 $42
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:74"
+  cell $not $43
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \msb_test
+    connect \Y $42
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:74"
+  wire width 1 $44
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:74"
+  cell $and $45
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \is_nzero
+    connect \B $42
+    connect \Y $44
+  end
+  process $group_7
+    assign \is_negative 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:72"
+    switch { \is_cmp }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:72"
+      case 1'1
+        assign \is_negative $44
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:75"
+      case
+        assign \is_negative \msb_test
     end
     sync init
-      update \o 129'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
-    sync posedge \clk
-      update \o \o$next
   end
-  process $group_62
-    assign \xer_so$17$next \xer_so$17
-    attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
-    switch { \n_i_rdy_data \p_valid_i_p_ready_o }
-      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
-      case 2'-1
-        assign \xer_so$17$next \xer_so$59
-      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
-      case 2'1-
-        assign \xer_so$17$next \xer_so$59
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:57"
+  wire width 4 \cr0
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:82"
+  wire width 1 $46
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:82"
+  cell $not $47
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \is_nzero
+    connect \Y $46
+  end
+  process $group_8
+    assign \cr0 4'0000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:79"
+    switch { \is_cmpeqb }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:79"
+      case 1'1
+        assign \cr0 \cr_a
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81"
+      case
+        assign \cr0 { \is_negative \is_positive $46 \xer_so$24 }
     end
     sync init
-      update \xer_so$17 1'0
-    sync posedge \clk
-      update \xer_so$17 \xer_so$17$next
   end
-  process $group_63
-    assign \neg_res$18$next \neg_res$18
-    attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
-    switch { \n_i_rdy_data \p_valid_i_p_ready_o }
-      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
-      case 2'-1
-        assign \neg_res$18$next \neg_res$60
-      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
-      case 2'1-
-        assign \neg_res$18$next \neg_res$60
-    end
+  process $group_9
+    assign \o$20 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \o$20 \o$25 [63:0]
     sync init
-      update \neg_res$18 1'0
-    sync posedge \clk
-      update \neg_res$18 \neg_res$18$next
   end
-  process $group_64
-    assign \neg_res32$19$next \neg_res32$19
-    attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
-    switch { \n_i_rdy_data \p_valid_i_p_ready_o }
-      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
-      case 2'-1
-        assign \neg_res32$19$next \neg_res32$61
-      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
-      case 2'1-
-        assign \neg_res32$19$next \neg_res32$61
-    end
+  process $group_10
+    assign \o_ok$21 1'0
+    assign \o_ok$21 \o_ok
     sync init
-      update \neg_res32$19 1'0
-    sync posedge \clk
-      update \neg_res32$19 \neg_res32$19$next
   end
-  process $group_65
-    assign \n_valid_o 1'0
-    assign \n_valid_o \r_busy
+  process $group_11
+    assign \cr_a$22 4'0000
+    assign \cr_a$22 \cr0
     sync init
   end
-  process $group_66
-    assign \p_ready_o 1'0
-    assign \p_ready_o \n_i_rdy_data
+  process $group_12
+    assign \cr_a_ok 1'0
+    assign \cr_a_ok \logical_op__write_cr0
     sync init
   end
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe3.p"
-module \p$77
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153"
-  wire width 1 input 0 \p_valid_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154"
-  wire width 1 input 1 \p_ready_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158"
-  wire width 1 \trigger
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205"
-  wire width 1 $1
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205"
-  cell $and $2
+  process $group_13
+    assign \muxid$1 2'00
+    assign \muxid$1 \muxid
+    sync init
+  end
+  process $group_14
+    assign \logical_op__insn_type$2 7'0000000
+    assign \logical_op__fn_unit$3 11'00000000000
+    assign \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \logical_op__imm_data__imm_ok$5 1'0
+    assign \logical_op__rc__rc$6 1'0
+    assign \logical_op__rc__rc_ok$7 1'0
+    assign \logical_op__oe__oe$8 1'0
+    assign \logical_op__oe__oe_ok$9 1'0
+    assign \logical_op__invert_a$10 1'0
+    assign \logical_op__zero_a$11 1'0
+    assign \logical_op__input_carry$12 2'00
+    assign \logical_op__invert_out$13 1'0
+    assign \logical_op__write_cr0$14 1'0
+    assign \logical_op__output_carry$15 1'0
+    assign \logical_op__is_32bit$16 1'0
+    assign \logical_op__is_signed$17 1'0
+    assign \logical_op__data_len$18 4'0000
+    assign \logical_op__insn$19 32'00000000000000000000000000000000
+    assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_a$10 { \logical_op__oe__oe_ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__rc_ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_a { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type }
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:28"
+  wire width 1 \oe
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:29"
+  wire width 1 $48
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:29"
+  cell $and $49
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \p_valid_i
-    connect \B \p_ready_o
-    connect \Y $1
+    connect \A \logical_op__oe__oe
+    connect \B \logical_op__oe__oe_ok
+    connect \Y $48
   end
-  process $group_0
-    assign \trigger 1'0
-    assign \trigger $1
+  process $group_32
+    assign \oe 1'0
+    assign \oe $48
     sync init
   end
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe3.n"
-module \n$78
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
-  wire width 1 input 0 \n_valid_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
-  wire width 1 input 1 \n_ready_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251"
-  wire width 1 \trigger
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298"
-  wire width 1 $1
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298"
-  cell $and $2
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:56"
+  wire width 1 \so
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:32"
+  wire width 1 $50
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:32"
+  cell $or $51
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \n_ready_i
-    connect \B \n_valid_o
-    connect \Y $1
+    connect \A \xer_so
+    connect \B \xer_ov [0]
+    connect \Y $50
   end
-  process $group_0
-    assign \trigger 1'0
-    assign \trigger $1
+  process $group_33
+    assign \so 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30"
+    switch { \oe }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30"
+      case 1'1
+        assign \so $50
+    end
+    sync init
+  end
+  process $group_34
+    assign \xer_so$24 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30"
+    switch { \oe }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30"
+      case 1'1
+        assign \xer_so$24 \so
+    end
+    sync init
+  end
+  process $group_35
+    assign \xer_so_ok 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30"
+    switch { \oe }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30"
+      case 1'1
+        assign \xer_so_ok 1'1
+    end
+    sync init
+  end
+  process $group_36
+    assign \xer_ov$23 2'00
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30"
+    switch { \oe }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30"
+      case 1'1
+        assign \xer_ov$23 \xer_ov
+    end
+    sync init
+  end
+  process $group_37
+    assign \xer_ov_ok 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30"
+    switch { \oe }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30"
+      case 1'1
+        assign \xer_ov_ok 1'1
+    end
     sync init
   end
 end
 attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe3.mul3"
-module \mul3
+attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_end"
+module \pipe_end
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153"
+  wire width 1 input 2 \p_valid_i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154"
+  wire width 1 output 3 \p_ready_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
-  wire width 2 input 0 \muxid
+  wire width 2 input 4 \muxid
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
   attribute \enum_value_0000001 "OP_NOP"
@@ -92746,7 +94134,7 @@ module \mul3
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 7 input 1 \mul_op__insn_type
+  wire width 7 input 5 \logical_op__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -92760,41 +94148,71 @@ module \mul3
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 11 input 2 \mul_op__fn_unit
+  wire width 11 input 6 \logical_op__fn_unit
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 64 input 3 \mul_op__imm_data__imm
+  wire width 64 input 7 \logical_op__imm_data__imm
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 4 \mul_op__imm_data__imm_ok
+  wire width 1 input 8 \logical_op__imm_data__imm_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 5 \mul_op__rc__rc
+  wire width 1 input 9 \logical_op__rc__rc
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 6 \mul_op__rc__rc_ok
+  wire width 1 input 10 \logical_op__rc__rc_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 7 \mul_op__oe__oe
+  wire width 1 input 11 \logical_op__oe__oe
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 8 \mul_op__oe__oe_ok
+  wire width 1 input 12 \logical_op__oe__oe_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 9 \mul_op__invert_a
+  wire width 1 input 13 \logical_op__invert_a
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 10 \mul_op__zero_a
+  wire width 1 input 14 \logical_op__zero_a
+  attribute \enum_base_type "CryIn"
+  attribute \enum_value_00 "ZERO"
+  attribute \enum_value_01 "ONE"
+  attribute \enum_value_10 "CA"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 11 \mul_op__invert_out
+  wire width 2 input 15 \logical_op__input_carry
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 12 \mul_op__write_cr0
+  wire width 1 input 16 \logical_op__invert_out
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 13 \mul_op__is_32bit
+  wire width 1 input 17 \logical_op__write_cr0
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 14 \mul_op__is_signed
+  wire width 1 input 18 \logical_op__output_carry
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 32 input 15 \mul_op__insn
+  wire width 1 input 19 \logical_op__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 20 \logical_op__is_signed
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 4 input 21 \logical_op__data_len
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 input 22 \logical_op__insn
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
-  wire width 129 input 16 \o
+  wire width 64 input 23 \ra
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
-  wire width 1 input 17 \xer_so
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23"
-  wire width 1 input 18 \neg_res
+  wire width 64 input 24 \rb
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
+  wire width 1 input 25 \xer_so
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160"
+  wire width 1 input 26 \divisor_neg
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161"
+  wire width 1 input 27 \dividend_neg
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167"
+  wire width 1 input 28 \dive_abs_ov32
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168"
+  wire width 1 input 29 \dive_abs_ov64
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162"
+  wire width 1 input 30 \div_by_zero
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40"
+  wire width 64 input 31 \quotient_root
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:41"
+  wire width 192 input 32 \remainder
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
+  wire width 1 output 33 \n_valid_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
+  wire width 1 input 34 \n_ready_i
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
-  wire width 2 output 19 \muxid$1
+  wire width 2 output 35 \muxid$1
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
+  wire width 2 \muxid$1$next
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
   attribute \enum_value_0000001 "OP_NOP"
@@ -92869,7 +94287,9 @@ module \mul3
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 7 output 20 \mul_op__insn_type$2
+  wire width 7 output 36 \logical_op__insn_type$2
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 \logical_op__insn_type$2$next
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -92883,299 +94303,119 @@ module \mul3
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 11 output 21 \mul_op__fn_unit$3
+  wire width 11 output 37 \logical_op__fn_unit$3
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 64 output 22 \mul_op__imm_data__imm$4
+  wire width 11 \logical_op__fn_unit$3$next
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 23 \mul_op__imm_data__imm_ok$5
+  wire width 64 output 38 \logical_op__imm_data__imm$4
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 24 \mul_op__rc__rc$6
+  wire width 64 \logical_op__imm_data__imm$4$next
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 25 \mul_op__rc__rc_ok$7
+  wire width 1 output 39 \logical_op__imm_data__imm_ok$5
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 26 \mul_op__oe__oe$8
+  wire width 1 \logical_op__imm_data__imm_ok$5$next
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 27 \mul_op__oe__oe_ok$9
+  wire width 1 output 40 \logical_op__rc__rc$6
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 28 \mul_op__invert_a$10
+  wire width 1 \logical_op__rc__rc$6$next
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 29 \mul_op__zero_a$11
+  wire width 1 output 41 \logical_op__rc__rc_ok$7
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 30 \mul_op__invert_out$12
+  wire width 1 \logical_op__rc__rc_ok$7$next
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 31 \mul_op__write_cr0$13
+  wire width 1 output 42 \logical_op__oe__oe$8
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 32 \mul_op__is_32bit$14
+  wire width 1 \logical_op__oe__oe$8$next
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 33 \mul_op__is_signed$15
+  wire width 1 output 43 \logical_op__oe__oe_ok$9
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 32 output 34 \mul_op__insn$16
+  wire width 1 \logical_op__oe__oe_ok$9$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 44 \logical_op__invert_a$10
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \logical_op__invert_a$10$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 45 \logical_op__zero_a$11
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \logical_op__zero_a$11$next
+  attribute \enum_base_type "CryIn"
+  attribute \enum_value_00 "ZERO"
+  attribute \enum_value_01 "ONE"
+  attribute \enum_value_10 "CA"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 2 output 46 \logical_op__input_carry$12
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 2 \logical_op__input_carry$12$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 47 \logical_op__invert_out$13
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \logical_op__invert_out$13$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 48 \logical_op__write_cr0$14
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \logical_op__write_cr0$14$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 49 \logical_op__output_carry$15
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \logical_op__output_carry$15$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 50 \logical_op__is_32bit$16
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \logical_op__is_32bit$16$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 51 \logical_op__is_signed$17
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \logical_op__is_signed$17$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 4 output 52 \logical_op__data_len$18
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 4 \logical_op__data_len$18$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 output 53 \logical_op__insn$19
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \logical_op__insn$19$next
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 64 output 35 \o$17
+  wire width 64 output 54 \o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 36 \o_ok
+  wire width 64 \o$next
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 2 output 37 \xer_ov
+  wire width 1 output 55 \o_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 38 \xer_ov_ok
+  wire width 1 \o_ok$next
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 39 \xer_so$18
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:36"
-  wire width 1 \is_32bit
-  process $group_0
-    assign \is_32bit 1'0
-    assign \is_32bit \mul_op__is_32bit
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:40"
-  wire width 129 \mul_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41"
-  wire width 130 $19
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41"
-  wire width 130 $20
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41"
-  cell $neg $21
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 129
-    parameter \Y_WIDTH 130
-    connect \A \o
-    connect \Y $20
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
-  wire width 130 $22
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
-  cell $pos $23
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 129
-    parameter \Y_WIDTH 130
-    connect \A \o
-    connect \Y $22
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41"
-  wire width 130 $24
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41"
-  cell $mux $25
-    parameter \WIDTH 130
-    connect \A $22
-    connect \B $20
-    connect \S \neg_res
-    connect \Y $24
-  end
-  connect $19 $24
-  process $group_1
-    assign \mul_o 129'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
-    assign \mul_o $19 [128:0]
-    sync init
-  end
-  wire width 1 $verilog_initial_trigger
-  process $group_2
-    assign \o_ok 1'0
-    assign \o_ok 1'1
-    assign $verilog_initial_trigger $verilog_initial_trigger
-    sync init
-      update $verilog_initial_trigger 1'0
-  end
-  process $group_3
-    assign \o$17 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:45"
-    switch \mul_op__insn_type
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:47"
-      attribute \nmigen.decoding "OP_MUL_H32/52"
-      case 7'0110100
-        assign \o$17 { \mul_o [63:32] \mul_o [63:32] }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:50"
-      attribute \nmigen.decoding "OP_MUL_H64/51"
-      case 7'0110011
-        assign \o$17 \mul_o [127:64]
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:53"
-      attribute \nmigen.decoding ""
-      case
-        assign \o$17 \mul_o [63:0]
-    end
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:58"
-  wire width 1 \mul_ov
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:63"
-  wire width 1 $26
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:63"
-  cell $reduce_bool $27
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 33
-    parameter \Y_WIDTH 1
-    connect \A \mul_o [63:31]
-    connect \Y $26
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:63"
-  wire width 1 $28
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:63"
-  wire width 1 $29
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:63"
-  cell $reduce_and $30
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 33
-    parameter \Y_WIDTH 1
-    connect \A \mul_o [63:31]
-    connect \Y $29
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:63"
-  cell $not $31
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A $29
-    connect \Y $28
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:63"
-  wire width 1 $32
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:63"
-  cell $and $33
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A $26
-    connect \B $28
-    connect \Y $32
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:68"
-  wire width 1 $34
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:68"
-  cell $reduce_bool $35
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 65
-    parameter \Y_WIDTH 1
-    connect \A \mul_o [127:63]
-    connect \Y $34
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:68"
-  wire width 1 $36
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:68"
-  wire width 1 $37
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:68"
-  cell $reduce_and $38
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 65
-    parameter \Y_WIDTH 1
-    connect \A \mul_o [127:63]
-    connect \Y $37
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:68"
-  cell $not $39
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A $37
-    connect \Y $36
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:68"
-  wire width 1 $40
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:68"
-  cell $and $41
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A $34
-    connect \B $36
-    connect \Y $40
-  end
-  process $group_4
-    assign \mul_ov 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:45"
-    switch \mul_op__insn_type
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:47"
-      attribute \nmigen.decoding "OP_MUL_H32/52"
-      case 7'0110100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:50"
-      attribute \nmigen.decoding "OP_MUL_H64/51"
-      case 7'0110011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:53"
-      attribute \nmigen.decoding ""
-      case
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:59"
-        switch { \is_32bit }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:59"
-          case 1'1
-            assign \mul_ov $32
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:64"
-          case
-            assign \mul_ov $40
-        end
-    end
-    sync init
-  end
-  process $group_5
-    assign \xer_ov 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:45"
-    switch \mul_op__insn_type
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:47"
-      attribute \nmigen.decoding "OP_MUL_H32/52"
-      case 7'0110100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:50"
-      attribute \nmigen.decoding "OP_MUL_H64/51"
-      case 7'0110011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:53"
-      attribute \nmigen.decoding ""
-      case
-        assign \xer_ov { \mul_ov \mul_ov }
-    end
-    sync init
-  end
-  process $group_6
-    assign \xer_ov_ok 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:45"
-    switch \mul_op__insn_type
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:47"
-      attribute \nmigen.decoding "OP_MUL_H32/52"
-      case 7'0110100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:50"
-      attribute \nmigen.decoding "OP_MUL_H64/51"
-      case 7'0110011
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:53"
-      attribute \nmigen.decoding ""
-      case
-        assign \xer_ov_ok 1'1
-    end
-    sync init
-  end
-  process $group_7
-    assign \xer_so$18 1'0
-    assign \xer_so$18 \xer_so
-    sync init
-  end
-  process $group_8
-    assign \muxid$1 2'00
-    assign \muxid$1 \muxid
-    sync init
+  wire width 4 output 56 \cr_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 4 \cr_a$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 output 57 \cr_a_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 \cr_a_ok$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 2 output 58 \xer_ov
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 2 \xer_ov$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 output 59 \xer_ov_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 \xer_ov_ok$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 output 60 \xer_so$20
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 \xer_so$20$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 output 61 \xer_so_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 \xer_so_ok$next
+  cell \p$77 \p
+    connect \p_valid_i \p_valid_i
+    connect \p_ready_o \p_ready_o
   end
-  process $group_9
-    assign \mul_op__insn_type$2 7'0000000
-    assign \mul_op__fn_unit$3 11'00000000000
-    assign \mul_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \mul_op__imm_data__imm_ok$5 1'0
-    assign \mul_op__rc__rc$6 1'0
-    assign \mul_op__rc__rc_ok$7 1'0
-    assign \mul_op__oe__oe$8 1'0
-    assign \mul_op__oe__oe_ok$9 1'0
-    assign \mul_op__invert_a$10 1'0
-    assign \mul_op__zero_a$11 1'0
-    assign \mul_op__invert_out$12 1'0
-    assign \mul_op__write_cr0$13 1'0
-    assign \mul_op__is_32bit$14 1'0
-    assign \mul_op__is_signed$15 1'0
-    assign \mul_op__insn$16 32'00000000000000000000000000000000
-    assign { \mul_op__insn$16 \mul_op__is_signed$15 \mul_op__is_32bit$14 \mul_op__write_cr0$13 \mul_op__invert_out$12 \mul_op__zero_a$11 \mul_op__invert_a$10 { \mul_op__oe__oe_ok$9 \mul_op__oe__oe$8 } { \mul_op__rc__rc_ok$7 \mul_op__rc__rc$6 } { \mul_op__imm_data__imm_ok$5 \mul_op__imm_data__imm$4 } \mul_op__fn_unit$3 \mul_op__insn_type$2 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__invert_out \mul_op__zero_a \mul_op__invert_a { \mul_op__oe__oe_ok \mul_op__oe__oe } { \mul_op__rc__rc_ok \mul_op__rc__rc } { \mul_op__imm_data__imm_ok \mul_op__imm_data__imm } \mul_op__fn_unit \mul_op__insn_type }
-    sync init
+  cell \n$78 \n
+    connect \n_valid_o \n_valid_o
+    connect \n_ready_i \n_ready_i
   end
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe3.output"
-module \output$79
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
-  wire width 2 input 0 \muxid
+  wire width 2 \output_stage_muxid
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
   attribute \enum_value_0000001 "OP_NOP"
@@ -93250,7 +94490,7 @@ module \output$79
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 7 input 1 \mul_op__insn_type
+  wire width 7 \output_stage_logical_op__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -93264,45 +94504,61 @@ module \output$79
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 11 input 2 \mul_op__fn_unit
+  wire width 11 \output_stage_logical_op__fn_unit
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 64 input 3 \mul_op__imm_data__imm
+  wire width 64 \output_stage_logical_op__imm_data__imm
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 4 \mul_op__imm_data__imm_ok
+  wire width 1 \output_stage_logical_op__imm_data__imm_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 5 \mul_op__rc__rc
+  wire width 1 \output_stage_logical_op__rc__rc
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 6 \mul_op__rc__rc_ok
+  wire width 1 \output_stage_logical_op__rc__rc_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 7 \mul_op__oe__oe
+  wire width 1 \output_stage_logical_op__oe__oe
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 8 \mul_op__oe__oe_ok
+  wire width 1 \output_stage_logical_op__oe__oe_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 9 \mul_op__invert_a
+  wire width 1 \output_stage_logical_op__invert_a
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 10 \mul_op__zero_a
+  wire width 1 \output_stage_logical_op__zero_a
+  attribute \enum_base_type "CryIn"
+  attribute \enum_value_00 "ZERO"
+  attribute \enum_value_01 "ONE"
+  attribute \enum_value_10 "CA"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 11 \mul_op__invert_out
+  wire width 2 \output_stage_logical_op__input_carry
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 12 \mul_op__write_cr0
+  wire width 1 \output_stage_logical_op__invert_out
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 13 \mul_op__is_32bit
+  wire width 1 \output_stage_logical_op__write_cr0
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 14 \mul_op__is_signed
+  wire width 1 \output_stage_logical_op__output_carry
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 32 input 15 \mul_op__insn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 64 input 16 \o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 input 17 \o_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 4 input 18 \cr_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 2 input 19 \xer_ov
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 input 20 \xer_so
+  wire width 1 \output_stage_logical_op__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_stage_logical_op__is_signed
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 4 \output_stage_logical_op__data_len
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \output_stage_logical_op__insn
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
+  wire width 1 \output_stage_xer_so
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160"
+  wire width 1 \output_stage_divisor_neg
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161"
+  wire width 1 \output_stage_dividend_neg
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167"
+  wire width 1 \output_stage_dive_abs_ov32
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168"
+  wire width 1 \output_stage_dive_abs_ov64
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162"
+  wire width 1 \output_stage_div_by_zero
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40"
+  wire width 64 \output_stage_quotient_root
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:41"
+  wire width 192 \output_stage_remainder
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
-  wire width 2 output 21 \muxid$1
+  wire width 2 \output_stage_muxid$21
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
   attribute \enum_value_0000001 "OP_NOP"
@@ -93377,7 +94633,7 @@ module \output$79
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 7 output 22 \mul_op__insn_type$2
+  wire width 7 \output_stage_logical_op__insn_type$22
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -93391,409 +94647,245 @@ module \output$79
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 11 output 23 \mul_op__fn_unit$3
+  wire width 11 \output_stage_logical_op__fn_unit$23
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 64 output 24 \mul_op__imm_data__imm$4
+  wire width 64 \output_stage_logical_op__imm_data__imm$24
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 25 \mul_op__imm_data__imm_ok$5
+  wire width 1 \output_stage_logical_op__imm_data__imm_ok$25
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 26 \mul_op__rc__rc$6
+  wire width 1 \output_stage_logical_op__rc__rc$26
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 27 \mul_op__rc__rc_ok$7
+  wire width 1 \output_stage_logical_op__rc__rc_ok$27
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 28 \mul_op__oe__oe$8
+  wire width 1 \output_stage_logical_op__oe__oe$28
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 29 \mul_op__oe__oe_ok$9
+  wire width 1 \output_stage_logical_op__oe__oe_ok$29
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 30 \mul_op__invert_a$10
+  wire width 1 \output_stage_logical_op__invert_a$30
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 31 \mul_op__zero_a$11
+  wire width 1 \output_stage_logical_op__zero_a$31
+  attribute \enum_base_type "CryIn"
+  attribute \enum_value_00 "ZERO"
+  attribute \enum_value_01 "ONE"
+  attribute \enum_value_10 "CA"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 32 \mul_op__invert_out$12
+  wire width 2 \output_stage_logical_op__input_carry$32
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_stage_logical_op__invert_out$33
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_stage_logical_op__write_cr0$34
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_stage_logical_op__output_carry$35
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_stage_logical_op__is_32bit$36
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_stage_logical_op__is_signed$37
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 4 \output_stage_logical_op__data_len$38
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \output_stage_logical_op__insn$39
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 64 \output_stage_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 \output_stage_o_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 2 \output_stage_xer_ov
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 \output_stage_xer_ov_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 \output_stage_xer_so$40
+  cell \output_stage \output_stage
+    connect \muxid \output_stage_muxid
+    connect \logical_op__insn_type \output_stage_logical_op__insn_type
+    connect \logical_op__fn_unit \output_stage_logical_op__fn_unit
+    connect \logical_op__imm_data__imm \output_stage_logical_op__imm_data__imm
+    connect \logical_op__imm_data__imm_ok \output_stage_logical_op__imm_data__imm_ok
+    connect \logical_op__rc__rc \output_stage_logical_op__rc__rc
+    connect \logical_op__rc__rc_ok \output_stage_logical_op__rc__rc_ok
+    connect \logical_op__oe__oe \output_stage_logical_op__oe__oe
+    connect \logical_op__oe__oe_ok \output_stage_logical_op__oe__oe_ok
+    connect \logical_op__invert_a \output_stage_logical_op__invert_a
+    connect \logical_op__zero_a \output_stage_logical_op__zero_a
+    connect \logical_op__input_carry \output_stage_logical_op__input_carry
+    connect \logical_op__invert_out \output_stage_logical_op__invert_out
+    connect \logical_op__write_cr0 \output_stage_logical_op__write_cr0
+    connect \logical_op__output_carry \output_stage_logical_op__output_carry
+    connect \logical_op__is_32bit \output_stage_logical_op__is_32bit
+    connect \logical_op__is_signed \output_stage_logical_op__is_signed
+    connect \logical_op__data_len \output_stage_logical_op__data_len
+    connect \logical_op__insn \output_stage_logical_op__insn
+    connect \xer_so \output_stage_xer_so
+    connect \divisor_neg \output_stage_divisor_neg
+    connect \dividend_neg \output_stage_dividend_neg
+    connect \dive_abs_ov32 \output_stage_dive_abs_ov32
+    connect \dive_abs_ov64 \output_stage_dive_abs_ov64
+    connect \div_by_zero \output_stage_div_by_zero
+    connect \quotient_root \output_stage_quotient_root
+    connect \remainder \output_stage_remainder
+    connect \muxid$1 \output_stage_muxid$21
+    connect \logical_op__insn_type$2 \output_stage_logical_op__insn_type$22
+    connect \logical_op__fn_unit$3 \output_stage_logical_op__fn_unit$23
+    connect \logical_op__imm_data__imm$4 \output_stage_logical_op__imm_data__imm$24
+    connect \logical_op__imm_data__imm_ok$5 \output_stage_logical_op__imm_data__imm_ok$25
+    connect \logical_op__rc__rc$6 \output_stage_logical_op__rc__rc$26
+    connect \logical_op__rc__rc_ok$7 \output_stage_logical_op__rc__rc_ok$27
+    connect \logical_op__oe__oe$8 \output_stage_logical_op__oe__oe$28
+    connect \logical_op__oe__oe_ok$9 \output_stage_logical_op__oe__oe_ok$29
+    connect \logical_op__invert_a$10 \output_stage_logical_op__invert_a$30
+    connect \logical_op__zero_a$11 \output_stage_logical_op__zero_a$31
+    connect \logical_op__input_carry$12 \output_stage_logical_op__input_carry$32
+    connect \logical_op__invert_out$13 \output_stage_logical_op__invert_out$33
+    connect \logical_op__write_cr0$14 \output_stage_logical_op__write_cr0$34
+    connect \logical_op__output_carry$15 \output_stage_logical_op__output_carry$35
+    connect \logical_op__is_32bit$16 \output_stage_logical_op__is_32bit$36
+    connect \logical_op__is_signed$17 \output_stage_logical_op__is_signed$37
+    connect \logical_op__data_len$18 \output_stage_logical_op__data_len$38
+    connect \logical_op__insn$19 \output_stage_logical_op__insn$39
+    connect \o \output_stage_o
+    connect \o_ok \output_stage_o_ok
+    connect \xer_ov \output_stage_xer_ov
+    connect \xer_ov_ok \output_stage_xer_ov_ok
+    connect \xer_so$20 \output_stage_xer_so$40
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
+  wire width 2 \output_muxid
+  attribute \enum_base_type "MicrOp"
+  attribute \enum_value_0000000 "OP_ILLEGAL"
+  attribute \enum_value_0000001 "OP_NOP"
+  attribute \enum_value_0000010 "OP_ADD"
+  attribute \enum_value_0000011 "OP_ADDPCIS"
+  attribute \enum_value_0000100 "OP_AND"
+  attribute \enum_value_0000101 "OP_ATTN"
+  attribute \enum_value_0000110 "OP_B"
+  attribute \enum_value_0000111 "OP_BC"
+  attribute \enum_value_0001000 "OP_BCREG"
+  attribute \enum_value_0001001 "OP_BPERM"
+  attribute \enum_value_0001010 "OP_CMP"
+  attribute \enum_value_0001011 "OP_CMPB"
+  attribute \enum_value_0001100 "OP_CMPEQB"
+  attribute \enum_value_0001101 "OP_CMPRB"
+  attribute \enum_value_0001110 "OP_CNTZ"
+  attribute \enum_value_0001111 "OP_CRAND"
+  attribute \enum_value_0010000 "OP_CRANDC"
+  attribute \enum_value_0010001 "OP_CREQV"
+  attribute \enum_value_0010010 "OP_CRNAND"
+  attribute \enum_value_0010011 "OP_CRNOR"
+  attribute \enum_value_0010100 "OP_CROR"
+  attribute \enum_value_0010101 "OP_CRORC"
+  attribute \enum_value_0010110 "OP_CRXOR"
+  attribute \enum_value_0010111 "OP_DARN"
+  attribute \enum_value_0011000 "OP_DCBF"
+  attribute \enum_value_0011001 "OP_DCBST"
+  attribute \enum_value_0011010 "OP_DCBT"
+  attribute \enum_value_0011011 "OP_DCBTST"
+  attribute \enum_value_0011100 "OP_DCBZ"
+  attribute \enum_value_0011101 "OP_DIV"
+  attribute \enum_value_0011110 "OP_DIVE"
+  attribute \enum_value_0011111 "OP_EXTS"
+  attribute \enum_value_0100000 "OP_EXTSWSLI"
+  attribute \enum_value_0100001 "OP_ICBI"
+  attribute \enum_value_0100010 "OP_ICBT"
+  attribute \enum_value_0100011 "OP_ISEL"
+  attribute \enum_value_0100100 "OP_ISYNC"
+  attribute \enum_value_0100101 "OP_LOAD"
+  attribute \enum_value_0100110 "OP_STORE"
+  attribute \enum_value_0100111 "OP_MADDHD"
+  attribute \enum_value_0101000 "OP_MADDHDU"
+  attribute \enum_value_0101001 "OP_MADDLD"
+  attribute \enum_value_0101010 "OP_MCRF"
+  attribute \enum_value_0101011 "OP_MCRXR"
+  attribute \enum_value_0101100 "OP_MCRXRX"
+  attribute \enum_value_0101101 "OP_MFCR"
+  attribute \enum_value_0101110 "OP_MFSPR"
+  attribute \enum_value_0101111 "OP_MOD"
+  attribute \enum_value_0110000 "OP_MTCRF"
+  attribute \enum_value_0110001 "OP_MTSPR"
+  attribute \enum_value_0110010 "OP_MUL_L64"
+  attribute \enum_value_0110011 "OP_MUL_H64"
+  attribute \enum_value_0110100 "OP_MUL_H32"
+  attribute \enum_value_0110101 "OP_OR"
+  attribute \enum_value_0110110 "OP_POPCNT"
+  attribute \enum_value_0110111 "OP_PRTY"
+  attribute \enum_value_0111000 "OP_RLC"
+  attribute \enum_value_0111001 "OP_RLCL"
+  attribute \enum_value_0111010 "OP_RLCR"
+  attribute \enum_value_0111011 "OP_SETB"
+  attribute \enum_value_0111100 "OP_SHL"
+  attribute \enum_value_0111101 "OP_SHR"
+  attribute \enum_value_0111110 "OP_SYNC"
+  attribute \enum_value_0111111 "OP_TRAP"
+  attribute \enum_value_1000011 "OP_XOR"
+  attribute \enum_value_1000100 "OP_SIM_CONFIG"
+  attribute \enum_value_1000101 "OP_CROP"
+  attribute \enum_value_1000110 "OP_RFID"
+  attribute \enum_value_1000111 "OP_MFMSR"
+  attribute \enum_value_1001000 "OP_MTMSRD"
+  attribute \enum_value_1001001 "OP_SC"
+  attribute \enum_value_1001010 "OP_MTMSR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 33 \mul_op__write_cr0$13
+  wire width 7 \output_logical_op__insn_type
+  attribute \enum_base_type "Function"
+  attribute \enum_value_00000000000 "NONE"
+  attribute \enum_value_00000000010 "ALU"
+  attribute \enum_value_00000000100 "LDST"
+  attribute \enum_value_00000001000 "SHIFT_ROT"
+  attribute \enum_value_00000010000 "LOGICAL"
+  attribute \enum_value_00000100000 "BRANCH"
+  attribute \enum_value_00001000000 "CR"
+  attribute \enum_value_00010000000 "TRAP"
+  attribute \enum_value_00100000000 "MUL"
+  attribute \enum_value_01000000000 "DIV"
+  attribute \enum_value_10000000000 "SPR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 34 \mul_op__is_32bit$14
+  wire width 11 \output_logical_op__fn_unit
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 35 \mul_op__is_signed$15
+  wire width 64 \output_logical_op__imm_data__imm
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 32 output 36 \mul_op__insn$16
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 64 output 37 \o$17
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 38 \o_ok$18
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 4 output 39 \cr_a$19
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 40 \cr_a_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 2 output 41 \xer_ov$20
+  wire width 1 \output_logical_op__imm_data__imm_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_logical_op__rc__rc
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_logical_op__rc__rc_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_logical_op__oe__oe
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_logical_op__oe__oe_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_logical_op__invert_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_logical_op__zero_a
+  attribute \enum_base_type "CryIn"
+  attribute \enum_value_00 "ZERO"
+  attribute \enum_value_01 "ONE"
+  attribute \enum_value_10 "CA"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 2 \output_logical_op__input_carry
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_logical_op__invert_out
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_logical_op__write_cr0
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_logical_op__output_carry
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_logical_op__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_logical_op__is_signed
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 4 \output_logical_op__data_len
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \output_logical_op__insn
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 42 \xer_ov_ok
+  wire width 64 \output_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 43 \xer_so$21
+  wire width 1 \output_o_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 44 \xer_so_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:23"
-  wire width 65 \o$22
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:26"
-  wire width 65 $23
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:26"
-  wire width 64 $24
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:26"
-  cell $not $25
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 64
-    parameter \Y_WIDTH 64
-    connect \A \o
-    connect \Y $24
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:26"
-  cell $pos $26
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 64
-    parameter \Y_WIDTH 65
-    connect \A $24
-    connect \Y $23
-  end
+  wire width 4 \output_cr_a
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 65 $27
+  wire width 2 \output_xer_ov
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  cell $pos $28
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 64
-    parameter \Y_WIDTH 65
-    connect \A \o
-    connect \Y $27
-  end
-  process $group_0
-    assign \o$22 65'00000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:25"
-    switch { \mul_op__invert_out }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:25"
-      case 1'1
-        assign \o$22 $23
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:27"
-      case
-        assign \o$22 $27
-    end
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:35"
-  wire width 64 \target
-  process $group_1
-    assign \target 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \target \o$22 [63:0]
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:54"
-  wire width 1 \is_cmp
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:63"
-  wire width 1 $29
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:63"
-  cell $eq $30
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 7
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 7
-    parameter \Y_WIDTH 1
-    connect \A \mul_op__insn_type
-    connect \B 7'0001010
-    connect \Y $29
-  end
-  process $group_2
-    assign \is_cmp 1'0
-    assign \is_cmp $29
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:55"
-  wire width 1 \is_cmpeqb
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:64"
-  wire width 1 $31
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:64"
-  cell $eq $32
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 7
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 7
-    parameter \Y_WIDTH 1
-    connect \A \mul_op__insn_type
-    connect \B 7'0001100
-    connect \Y $31
-  end
-  process $group_3
-    assign \is_cmpeqb 1'0
-    assign \is_cmpeqb $31
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:53"
-  wire width 1 \msb_test
-  process $group_4
-    assign \msb_test 1'0
-    assign \msb_test \target [63]
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:50"
-  wire width 1 \is_nzero
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71"
-  wire width 1 $33
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71"
-  cell $reduce_bool $34
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 64
-    parameter \Y_WIDTH 1
-    connect \A \target
-    connect \Y $33
-  end
-  process $group_5
-    assign \is_nzero 1'0
-    assign \is_nzero $33
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:51"
-  wire width 1 \is_positive
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77"
-  wire width 1 $35
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77"
-  cell $not $36
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \msb_test
-    connect \Y $35
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77"
-  wire width 1 $37
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77"
-  cell $and $38
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \is_nzero
-    connect \B $35
-    connect \Y $37
-  end
-  process $group_6
-    assign \is_positive 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:72"
-    switch { \is_cmp }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:72"
-      case 1'1
-        assign \is_positive \msb_test
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:75"
-      case
-        assign \is_positive $37
-    end
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:52"
-  wire width 1 \is_negative
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:74"
-  wire width 1 $39
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:74"
-  cell $not $40
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \msb_test
-    connect \Y $39
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:74"
-  wire width 1 $41
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:74"
-  cell $and $42
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \is_nzero
-    connect \B $39
-    connect \Y $41
-  end
-  process $group_7
-    assign \is_negative 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:72"
-    switch { \is_cmp }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:72"
-      case 1'1
-        assign \is_negative $41
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:75"
-      case
-        assign \is_negative \msb_test
-    end
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:57"
-  wire width 4 \cr0
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:82"
-  wire width 1 $43
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:82"
-  cell $not $44
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \is_nzero
-    connect \Y $43
-  end
-  process $group_8
-    assign \cr0 4'0000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:79"
-    switch { \is_cmpeqb }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:79"
-      case 1'1
-        assign \cr0 \cr_a
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81"
-      case
-        assign \cr0 { \is_negative \is_positive $43 \xer_so$21 }
-    end
-    sync init
-  end
-  process $group_9
-    assign \o$17 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \o$17 \o$22 [63:0]
-    sync init
-  end
-  process $group_10
-    assign \o_ok$18 1'0
-    assign \o_ok$18 \o_ok
-    sync init
-  end
-  process $group_11
-    assign \cr_a$19 4'0000
-    assign \cr_a$19 \cr0
-    sync init
-  end
-  process $group_12
-    assign \cr_a_ok 1'0
-    assign \cr_a_ok \mul_op__write_cr0
-    sync init
-  end
-  process $group_13
-    assign \muxid$1 2'00
-    assign \muxid$1 \muxid
-    sync init
-  end
-  process $group_14
-    assign \mul_op__insn_type$2 7'0000000
-    assign \mul_op__fn_unit$3 11'00000000000
-    assign \mul_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \mul_op__imm_data__imm_ok$5 1'0
-    assign \mul_op__rc__rc$6 1'0
-    assign \mul_op__rc__rc_ok$7 1'0
-    assign \mul_op__oe__oe$8 1'0
-    assign \mul_op__oe__oe_ok$9 1'0
-    assign \mul_op__invert_a$10 1'0
-    assign \mul_op__zero_a$11 1'0
-    assign \mul_op__invert_out$12 1'0
-    assign \mul_op__write_cr0$13 1'0
-    assign \mul_op__is_32bit$14 1'0
-    assign \mul_op__is_signed$15 1'0
-    assign \mul_op__insn$16 32'00000000000000000000000000000000
-    assign { \mul_op__insn$16 \mul_op__is_signed$15 \mul_op__is_32bit$14 \mul_op__write_cr0$13 \mul_op__invert_out$12 \mul_op__zero_a$11 \mul_op__invert_a$10 { \mul_op__oe__oe_ok$9 \mul_op__oe__oe$8 } { \mul_op__rc__rc_ok$7 \mul_op__rc__rc$6 } { \mul_op__imm_data__imm_ok$5 \mul_op__imm_data__imm$4 } \mul_op__fn_unit$3 \mul_op__insn_type$2 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__invert_out \mul_op__zero_a \mul_op__invert_a { \mul_op__oe__oe_ok \mul_op__oe__oe } { \mul_op__rc__rc_ok \mul_op__rc__rc } { \mul_op__imm_data__imm_ok \mul_op__imm_data__imm } \mul_op__fn_unit \mul_op__insn_type }
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:28"
-  wire width 1 \oe
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:29"
-  wire width 1 $45
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:29"
-  cell $and $46
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \mul_op__oe__oe
-    connect \B \mul_op__oe__oe_ok
-    connect \Y $45
-  end
-  process $group_29
-    assign \oe 1'0
-    assign \oe $45
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:56"
-  wire width 1 \so
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:32"
-  wire width 1 $47
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:32"
-  cell $or $48
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \xer_so
-    connect \B \xer_ov [0]
-    connect \Y $47
-  end
-  process $group_30
-    assign \so 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30"
-    switch { \oe }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30"
-      case 1'1
-        assign \so $47
-    end
-    sync init
-  end
-  process $group_31
-    assign \xer_so$21 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30"
-    switch { \oe }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30"
-      case 1'1
-        assign \xer_so$21 \so
-    end
-    sync init
-  end
-  process $group_32
-    assign \xer_so_ok 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30"
-    switch { \oe }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30"
-      case 1'1
-        assign \xer_so_ok 1'1
-    end
-    sync init
-  end
-  process $group_33
-    assign \xer_ov$20 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30"
-    switch { \oe }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30"
-      case 1'1
-        assign \xer_ov$20 \xer_ov
-    end
-    sync init
-  end
-  process $group_34
-    assign \xer_ov_ok 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30"
-    switch { \oe }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30"
-      case 1'1
-        assign \xer_ov_ok 1'1
-    end
-    sync init
-  end
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe3"
-module \mul_pipe3
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153"
-  wire width 1 input 2 \p_valid_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154"
-  wire width 1 output 3 \p_ready_o
+  wire width 1 \output_xer_so
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
-  wire width 2 input 4 \muxid
+  wire width 2 \output_muxid$41
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
   attribute \enum_value_0000001 "OP_NOP"
@@ -93868,7 +94960,7 @@ module \mul_pipe3
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 7 input 5 \mul_op__insn_type
+  wire width 7 \output_logical_op__insn_type$42
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -93882,49 +94974,297 @@ module \mul_pipe3
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 11 input 6 \mul_op__fn_unit
+  wire width 11 \output_logical_op__fn_unit$43
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 64 input 7 \mul_op__imm_data__imm
+  wire width 64 \output_logical_op__imm_data__imm$44
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 8 \mul_op__imm_data__imm_ok
+  wire width 1 \output_logical_op__imm_data__imm_ok$45
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 9 \mul_op__rc__rc
+  wire width 1 \output_logical_op__rc__rc$46
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 10 \mul_op__rc__rc_ok
+  wire width 1 \output_logical_op__rc__rc_ok$47
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 11 \mul_op__oe__oe
+  wire width 1 \output_logical_op__oe__oe$48
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 12 \mul_op__oe__oe_ok
+  wire width 1 \output_logical_op__oe__oe_ok$49
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 13 \mul_op__invert_a
+  wire width 1 \output_logical_op__invert_a$50
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 14 \mul_op__zero_a
+  wire width 1 \output_logical_op__zero_a$51
+  attribute \enum_base_type "CryIn"
+  attribute \enum_value_00 "ZERO"
+  attribute \enum_value_01 "ONE"
+  attribute \enum_value_10 "CA"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 15 \mul_op__invert_out
+  wire width 2 \output_logical_op__input_carry$52
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 16 \mul_op__write_cr0
+  wire width 1 \output_logical_op__invert_out$53
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 17 \mul_op__is_32bit
+  wire width 1 \output_logical_op__write_cr0$54
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 18 \mul_op__is_signed
+  wire width 1 \output_logical_op__output_carry$55
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 32 input 19 \mul_op__insn
+  wire width 1 \output_logical_op__is_32bit$56
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_logical_op__is_signed$57
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 4 \output_logical_op__data_len$58
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \output_logical_op__insn$59
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 64 \output_o$60
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 \output_o_ok$61
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 4 \output_cr_a$62
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 \output_cr_a_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 2 \output_xer_ov$63
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 \output_xer_ov_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 \output_xer_so$64
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 \output_xer_so_ok
+  cell \output$79 \output
+    connect \muxid \output_muxid
+    connect \logical_op__insn_type \output_logical_op__insn_type
+    connect \logical_op__fn_unit \output_logical_op__fn_unit
+    connect \logical_op__imm_data__imm \output_logical_op__imm_data__imm
+    connect \logical_op__imm_data__imm_ok \output_logical_op__imm_data__imm_ok
+    connect \logical_op__rc__rc \output_logical_op__rc__rc
+    connect \logical_op__rc__rc_ok \output_logical_op__rc__rc_ok
+    connect \logical_op__oe__oe \output_logical_op__oe__oe
+    connect \logical_op__oe__oe_ok \output_logical_op__oe__oe_ok
+    connect \logical_op__invert_a \output_logical_op__invert_a
+    connect \logical_op__zero_a \output_logical_op__zero_a
+    connect \logical_op__input_carry \output_logical_op__input_carry
+    connect \logical_op__invert_out \output_logical_op__invert_out
+    connect \logical_op__write_cr0 \output_logical_op__write_cr0
+    connect \logical_op__output_carry \output_logical_op__output_carry
+    connect \logical_op__is_32bit \output_logical_op__is_32bit
+    connect \logical_op__is_signed \output_logical_op__is_signed
+    connect \logical_op__data_len \output_logical_op__data_len
+    connect \logical_op__insn \output_logical_op__insn
+    connect \o \output_o
+    connect \o_ok \output_o_ok
+    connect \cr_a \output_cr_a
+    connect \xer_ov \output_xer_ov
+    connect \xer_so \output_xer_so
+    connect \muxid$1 \output_muxid$41
+    connect \logical_op__insn_type$2 \output_logical_op__insn_type$42
+    connect \logical_op__fn_unit$3 \output_logical_op__fn_unit$43
+    connect \logical_op__imm_data__imm$4 \output_logical_op__imm_data__imm$44
+    connect \logical_op__imm_data__imm_ok$5 \output_logical_op__imm_data__imm_ok$45
+    connect \logical_op__rc__rc$6 \output_logical_op__rc__rc$46
+    connect \logical_op__rc__rc_ok$7 \output_logical_op__rc__rc_ok$47
+    connect \logical_op__oe__oe$8 \output_logical_op__oe__oe$48
+    connect \logical_op__oe__oe_ok$9 \output_logical_op__oe__oe_ok$49
+    connect \logical_op__invert_a$10 \output_logical_op__invert_a$50
+    connect \logical_op__zero_a$11 \output_logical_op__zero_a$51
+    connect \logical_op__input_carry$12 \output_logical_op__input_carry$52
+    connect \logical_op__invert_out$13 \output_logical_op__invert_out$53
+    connect \logical_op__write_cr0$14 \output_logical_op__write_cr0$54
+    connect \logical_op__output_carry$15 \output_logical_op__output_carry$55
+    connect \logical_op__is_32bit$16 \output_logical_op__is_32bit$56
+    connect \logical_op__is_signed$17 \output_logical_op__is_signed$57
+    connect \logical_op__data_len$18 \output_logical_op__data_len$58
+    connect \logical_op__insn$19 \output_logical_op__insn$59
+    connect \o$20 \output_o$60
+    connect \o_ok$21 \output_o_ok$61
+    connect \cr_a$22 \output_cr_a$62
+    connect \cr_a_ok \output_cr_a_ok
+    connect \xer_ov$23 \output_xer_ov$63
+    connect \xer_ov_ok \output_xer_ov_ok
+    connect \xer_so$24 \output_xer_so$64
+    connect \xer_so_ok \output_xer_so_ok
+  end
+  process $group_0
+    assign \output_stage_muxid 2'00
+    assign \output_stage_muxid \muxid
+    sync init
+  end
+  process $group_1
+    assign \output_stage_logical_op__insn_type 7'0000000
+    assign \output_stage_logical_op__fn_unit 11'00000000000
+    assign \output_stage_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \output_stage_logical_op__imm_data__imm_ok 1'0
+    assign \output_stage_logical_op__rc__rc 1'0
+    assign \output_stage_logical_op__rc__rc_ok 1'0
+    assign \output_stage_logical_op__oe__oe 1'0
+    assign \output_stage_logical_op__oe__oe_ok 1'0
+    assign \output_stage_logical_op__invert_a 1'0
+    assign \output_stage_logical_op__zero_a 1'0
+    assign \output_stage_logical_op__input_carry 2'00
+    assign \output_stage_logical_op__invert_out 1'0
+    assign \output_stage_logical_op__write_cr0 1'0
+    assign \output_stage_logical_op__output_carry 1'0
+    assign \output_stage_logical_op__is_32bit 1'0
+    assign \output_stage_logical_op__is_signed 1'0
+    assign \output_stage_logical_op__data_len 4'0000
+    assign \output_stage_logical_op__insn 32'00000000000000000000000000000000
+    assign { \output_stage_logical_op__insn \output_stage_logical_op__data_len \output_stage_logical_op__is_signed \output_stage_logical_op__is_32bit \output_stage_logical_op__output_carry \output_stage_logical_op__write_cr0 \output_stage_logical_op__invert_out \output_stage_logical_op__input_carry \output_stage_logical_op__zero_a \output_stage_logical_op__invert_a { \output_stage_logical_op__oe__oe_ok \output_stage_logical_op__oe__oe } { \output_stage_logical_op__rc__rc_ok \output_stage_logical_op__rc__rc } { \output_stage_logical_op__imm_data__imm_ok \output_stage_logical_op__imm_data__imm } \output_stage_logical_op__fn_unit \output_stage_logical_op__insn_type } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_a { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type }
+    sync init
+  end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
-  wire width 129 input 20 \o
+  wire width 64 \ra$65
+  process $group_19
+    assign \ra$65 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \ra$65 \ra
+    sync init
+  end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
-  wire width 1 input 21 \xer_so
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23"
-  wire width 1 input 22 \neg_res
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24"
-  wire width 1 input 23 \neg_res32
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
-  wire width 1 output 24 \n_valid_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
-  wire width 1 input 25 \n_ready_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
-  wire width 2 output 26 \muxid$1
+  wire width 64 \rb$66
+  process $group_20
+    assign \rb$66 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \rb$66 \rb
+    sync init
+  end
+  process $group_21
+    assign \output_stage_xer_so 1'0
+    assign \output_stage_xer_so \xer_so
+    sync init
+  end
+  process $group_22
+    assign \output_stage_divisor_neg 1'0
+    assign \output_stage_divisor_neg \divisor_neg
+    sync init
+  end
+  process $group_23
+    assign \output_stage_dividend_neg 1'0
+    assign \output_stage_dividend_neg \dividend_neg
+    sync init
+  end
+  process $group_24
+    assign \output_stage_dive_abs_ov32 1'0
+    assign \output_stage_dive_abs_ov32 \dive_abs_ov32
+    sync init
+  end
+  process $group_25
+    assign \output_stage_dive_abs_ov64 1'0
+    assign \output_stage_dive_abs_ov64 \dive_abs_ov64
+    sync init
+  end
+  process $group_26
+    assign \output_stage_div_by_zero 1'0
+    assign \output_stage_div_by_zero \div_by_zero
+    sync init
+  end
+  process $group_27
+    assign \output_stage_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \output_stage_quotient_root \quotient_root
+    sync init
+  end
+  process $group_28
+    assign \output_stage_remainder 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
+    assign \output_stage_remainder \remainder
+    sync init
+  end
+  process $group_29
+    assign \output_muxid 2'00
+    assign \output_muxid \output_stage_muxid$21
+    sync init
+  end
+  process $group_30
+    assign \output_logical_op__insn_type 7'0000000
+    assign \output_logical_op__fn_unit 11'00000000000
+    assign \output_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \output_logical_op__imm_data__imm_ok 1'0
+    assign \output_logical_op__rc__rc 1'0
+    assign \output_logical_op__rc__rc_ok 1'0
+    assign \output_logical_op__oe__oe 1'0
+    assign \output_logical_op__oe__oe_ok 1'0
+    assign \output_logical_op__invert_a 1'0
+    assign \output_logical_op__zero_a 1'0
+    assign \output_logical_op__input_carry 2'00
+    assign \output_logical_op__invert_out 1'0
+    assign \output_logical_op__write_cr0 1'0
+    assign \output_logical_op__output_carry 1'0
+    assign \output_logical_op__is_32bit 1'0
+    assign \output_logical_op__is_signed 1'0
+    assign \output_logical_op__data_len 4'0000
+    assign \output_logical_op__insn 32'00000000000000000000000000000000
+    assign { \output_logical_op__insn \output_logical_op__data_len \output_logical_op__is_signed \output_logical_op__is_32bit \output_logical_op__output_carry \output_logical_op__write_cr0 \output_logical_op__invert_out \output_logical_op__input_carry \output_logical_op__zero_a \output_logical_op__invert_a { \output_logical_op__oe__oe_ok \output_logical_op__oe__oe } { \output_logical_op__rc__rc_ok \output_logical_op__rc__rc } { \output_logical_op__imm_data__imm_ok \output_logical_op__imm_data__imm } \output_logical_op__fn_unit \output_logical_op__insn_type } { \output_stage_logical_op__insn$39 \output_stage_logical_op__data_len$38 \output_stage_logical_op__is_signed$37 \output_stage_logical_op__is_32bit$36 \output_stage_logical_op__output_carry$35 \output_stage_logical_op__write_cr0$34 \output_stage_logical_op__invert_out$33 \output_stage_logical_op__input_carry$32 \output_stage_logical_op__zero_a$31 \output_stage_logical_op__invert_a$30 { \output_stage_logical_op__oe__oe_ok$29 \output_stage_logical_op__oe__oe$28 } { \output_stage_logical_op__rc__rc_ok$27 \output_stage_logical_op__rc__rc$26 } { \output_stage_logical_op__imm_data__imm_ok$25 \output_stage_logical_op__imm_data__imm$24 } \output_stage_logical_op__fn_unit$23 \output_stage_logical_op__insn_type$22 }
+    sync init
+  end
+  process $group_48
+    assign \output_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \output_o_ok 1'0
+    assign { \output_o_ok \output_o } { \output_stage_o_ok \output_stage_o }
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 \cr_a_ok$67
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 4 \cr_a$68
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 \cr_a_ok$69
+  process $group_50
+    assign \output_cr_a 4'0000
+    assign \cr_a_ok$67 1'0
+    assign { \cr_a_ok$67 \output_cr_a } { \cr_a_ok$69 \cr_a$68 }
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 \xer_ov_ok$70
+  process $group_52
+    assign \output_xer_ov 2'00
+    assign \xer_ov_ok$70 1'0
+    assign { \xer_ov_ok$70 \output_xer_ov } { \output_stage_xer_ov_ok \output_stage_xer_ov }
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 \xer_so_ok$71
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 \xer_so_ok$72
+  process $group_54
+    assign \output_xer_so 1'0
+    assign \xer_so_ok$71 1'0
+    assign { \xer_so_ok$71 \output_xer_so } { \xer_so_ok$72 \output_stage_xer_so$40 }
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621"
+  wire width 1 \p_valid_i$73
+  process $group_56
+    assign \p_valid_i$73 1'0
+    assign \p_valid_i$73 \p_valid_i
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619"
+  wire width 1 \n_i_rdy_data
+  process $group_57
+    assign \n_i_rdy_data 1'0
+    assign \n_i_rdy_data \n_ready_i
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620"
+  wire width 1 \p_valid_i_p_ready_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624"
+  wire width 1 $74
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624"
+  cell $and $75
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \p_valid_i$73
+    connect \B \p_ready_o
+    connect \Y $74
+  end
+  process $group_58
+    assign \p_valid_i_p_ready_o 1'0
+    assign \p_valid_i_p_ready_o $74
+    sync init
+  end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
-  wire width 2 \muxid$1$next
+  wire width 2 \muxid$76
+  process $group_59
+    assign \muxid$76 2'00
+    assign \muxid$76 \output_muxid$41
+    sync init
+  end
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
   attribute \enum_value_0000001 "OP_NOP"
@@ -93999,9 +95339,7 @@ module \mul_pipe3
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 7 output 27 \mul_op__insn_type$2
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 7 \mul_op__insn_type$2$next
+  wire width 7 \logical_op__insn_type$77
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -94015,103 +95353,360 @@ module \mul_pipe3
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 11 output 28 \mul_op__fn_unit$3
+  wire width 11 \logical_op__fn_unit$78
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 11 \mul_op__fn_unit$3$next
+  wire width 64 \logical_op__imm_data__imm$79
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 64 output 29 \mul_op__imm_data__imm$4
+  wire width 1 \logical_op__imm_data__imm_ok$80
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 64 \mul_op__imm_data__imm$4$next
+  wire width 1 \logical_op__rc__rc$81
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 30 \mul_op__imm_data__imm_ok$5
+  wire width 1 \logical_op__rc__rc_ok$82
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_op__imm_data__imm_ok$5$next
+  wire width 1 \logical_op__oe__oe$83
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 31 \mul_op__rc__rc$6
+  wire width 1 \logical_op__oe__oe_ok$84
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_op__rc__rc$6$next
+  wire width 1 \logical_op__invert_a$85
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 32 \mul_op__rc__rc_ok$7
+  wire width 1 \logical_op__zero_a$86
+  attribute \enum_base_type "CryIn"
+  attribute \enum_value_00 "ZERO"
+  attribute \enum_value_01 "ONE"
+  attribute \enum_value_10 "CA"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_op__rc__rc_ok$7$next
+  wire width 2 \logical_op__input_carry$87
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 33 \mul_op__oe__oe$8
+  wire width 1 \logical_op__invert_out$88
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_op__oe__oe$8$next
+  wire width 1 \logical_op__write_cr0$89
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 34 \mul_op__oe__oe_ok$9
+  wire width 1 \logical_op__output_carry$90
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_op__oe__oe_ok$9$next
+  wire width 1 \logical_op__is_32bit$91
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 35 \mul_op__invert_a$10
+  wire width 1 \logical_op__is_signed$92
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_op__invert_a$10$next
+  wire width 4 \logical_op__data_len$93
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 36 \mul_op__zero_a$11
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_op__zero_a$11$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 37 \mul_op__invert_out$12
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_op__invert_out$12$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 38 \mul_op__write_cr0$13
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_op__write_cr0$13$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 39 \mul_op__is_32bit$14
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_op__is_32bit$14$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 40 \mul_op__is_signed$15
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_op__is_signed$15$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 32 output 41 \mul_op__insn$16
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 32 \mul_op__insn$16$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 64 output 42 \o$17
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 64 \o$17$next
+  wire width 32 \logical_op__insn$94
+  process $group_60
+    assign \logical_op__insn_type$77 7'0000000
+    assign \logical_op__fn_unit$78 11'00000000000
+    assign \logical_op__imm_data__imm$79 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \logical_op__imm_data__imm_ok$80 1'0
+    assign \logical_op__rc__rc$81 1'0
+    assign \logical_op__rc__rc_ok$82 1'0
+    assign \logical_op__oe__oe$83 1'0
+    assign \logical_op__oe__oe_ok$84 1'0
+    assign \logical_op__invert_a$85 1'0
+    assign \logical_op__zero_a$86 1'0
+    assign \logical_op__input_carry$87 2'00
+    assign \logical_op__invert_out$88 1'0
+    assign \logical_op__write_cr0$89 1'0
+    assign \logical_op__output_carry$90 1'0
+    assign \logical_op__is_32bit$91 1'0
+    assign \logical_op__is_signed$92 1'0
+    assign \logical_op__data_len$93 4'0000
+    assign \logical_op__insn$94 32'00000000000000000000000000000000
+    assign { \logical_op__insn$94 \logical_op__data_len$93 \logical_op__is_signed$92 \logical_op__is_32bit$91 \logical_op__output_carry$90 \logical_op__write_cr0$89 \logical_op__invert_out$88 \logical_op__input_carry$87 \logical_op__zero_a$86 \logical_op__invert_a$85 { \logical_op__oe__oe_ok$84 \logical_op__oe__oe$83 } { \logical_op__rc__rc_ok$82 \logical_op__rc__rc$81 } { \logical_op__imm_data__imm_ok$80 \logical_op__imm_data__imm$79 } \logical_op__fn_unit$78 \logical_op__insn_type$77 } { \output_logical_op__insn$59 \output_logical_op__data_len$58 \output_logical_op__is_signed$57 \output_logical_op__is_32bit$56 \output_logical_op__output_carry$55 \output_logical_op__write_cr0$54 \output_logical_op__invert_out$53 \output_logical_op__input_carry$52 \output_logical_op__zero_a$51 \output_logical_op__invert_a$50 { \output_logical_op__oe__oe_ok$49 \output_logical_op__oe__oe$48 } { \output_logical_op__rc__rc_ok$47 \output_logical_op__rc__rc$46 } { \output_logical_op__imm_data__imm_ok$45 \output_logical_op__imm_data__imm$44 } \output_logical_op__fn_unit$43 \output_logical_op__insn_type$42 }
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 64 \o$95
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 \o_ok$96
+  process $group_78
+    assign \o$95 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \o_ok$96 1'0
+    assign { \o_ok$96 \o$95 } { \output_o_ok$61 \output_o$60 }
+    sync init
+  end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 43 \o_ok
+  wire width 4 \cr_a$97
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 \o_ok$next
+  wire width 1 \cr_a_ok$98
+  process $group_80
+    assign \cr_a$97 4'0000
+    assign \cr_a_ok$98 1'0
+    assign { \cr_a_ok$98 \cr_a$97 } { \output_cr_a_ok \output_cr_a$62 }
+    sync init
+  end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 4 output 44 \cr_a
+  wire width 2 \xer_ov$99
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 4 \cr_a$next
+  wire width 1 \xer_ov_ok$100
+  process $group_82
+    assign \xer_ov$99 2'00
+    assign \xer_ov_ok$100 1'0
+    assign { \xer_ov_ok$100 \xer_ov$99 } { \output_xer_ov_ok \output_xer_ov$63 }
+    sync init
+  end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 45 \cr_a_ok
+  wire width 1 \xer_so$101
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 \cr_a_ok$next
+  wire width 1 \xer_so_ok$102
+  process $group_84
+    assign \xer_so$101 1'0
+    assign \xer_so_ok$102 1'0
+    assign { \xer_so_ok$102 \xer_so$101 } { \output_xer_so_ok \output_xer_so$64 }
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615"
+  wire width 1 \r_busy
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615"
+  wire width 1 \r_busy$next
+  process $group_86
+    assign \r_busy$next \r_busy
+    attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+    switch { \n_i_rdy_data \p_valid_i_p_ready_o }
+      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+      case 2'-1
+        assign \r_busy$next 1'1
+      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
+      case 2'1-
+        assign \r_busy$next 1'0
+    end
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
+      case 1'1
+        assign \r_busy$next 1'0
+    end
+    sync init
+      update \r_busy 1'0
+    sync posedge \coresync_clk
+      update \r_busy \r_busy$next
+  end
+  process $group_87
+    assign \muxid$1$next \muxid$1
+    attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+    switch { \n_i_rdy_data \p_valid_i_p_ready_o }
+      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+      case 2'-1
+        assign \muxid$1$next \muxid$76
+      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
+      case 2'1-
+        assign \muxid$1$next \muxid$76
+    end
+    sync init
+      update \muxid$1 2'00
+    sync posedge \coresync_clk
+      update \muxid$1 \muxid$1$next
+  end
+  process $group_88
+    assign \logical_op__insn_type$2$next \logical_op__insn_type$2
+    assign \logical_op__fn_unit$3$next \logical_op__fn_unit$3
+    assign \logical_op__imm_data__imm$4$next \logical_op__imm_data__imm$4
+    assign \logical_op__imm_data__imm_ok$5$next \logical_op__imm_data__imm_ok$5
+    assign \logical_op__rc__rc$6$next \logical_op__rc__rc$6
+    assign \logical_op__rc__rc_ok$7$next \logical_op__rc__rc_ok$7
+    assign \logical_op__oe__oe$8$next \logical_op__oe__oe$8
+    assign \logical_op__oe__oe_ok$9$next \logical_op__oe__oe_ok$9
+    assign \logical_op__invert_a$10$next \logical_op__invert_a$10
+    assign \logical_op__zero_a$11$next \logical_op__zero_a$11
+    assign \logical_op__input_carry$12$next \logical_op__input_carry$12
+    assign \logical_op__invert_out$13$next \logical_op__invert_out$13
+    assign \logical_op__write_cr0$14$next \logical_op__write_cr0$14
+    assign \logical_op__output_carry$15$next \logical_op__output_carry$15
+    assign \logical_op__is_32bit$16$next \logical_op__is_32bit$16
+    assign \logical_op__is_signed$17$next \logical_op__is_signed$17
+    assign \logical_op__data_len$18$next \logical_op__data_len$18
+    assign \logical_op__insn$19$next \logical_op__insn$19
+    attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+    switch { \n_i_rdy_data \p_valid_i_p_ready_o }
+      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+      case 2'-1
+        assign { \logical_op__insn$19$next \logical_op__data_len$18$next \logical_op__is_signed$17$next \logical_op__is_32bit$16$next \logical_op__output_carry$15$next \logical_op__write_cr0$14$next \logical_op__invert_out$13$next \logical_op__input_carry$12$next \logical_op__zero_a$11$next \logical_op__invert_a$10$next { \logical_op__oe__oe_ok$9$next \logical_op__oe__oe$8$next } { \logical_op__rc__rc_ok$7$next \logical_op__rc__rc$6$next } { \logical_op__imm_data__imm_ok$5$next \logical_op__imm_data__imm$4$next } \logical_op__fn_unit$3$next \logical_op__insn_type$2$next } { \logical_op__insn$94 \logical_op__data_len$93 \logical_op__is_signed$92 \logical_op__is_32bit$91 \logical_op__output_carry$90 \logical_op__write_cr0$89 \logical_op__invert_out$88 \logical_op__input_carry$87 \logical_op__zero_a$86 \logical_op__invert_a$85 { \logical_op__oe__oe_ok$84 \logical_op__oe__oe$83 } { \logical_op__rc__rc_ok$82 \logical_op__rc__rc$81 } { \logical_op__imm_data__imm_ok$80 \logical_op__imm_data__imm$79 } \logical_op__fn_unit$78 \logical_op__insn_type$77 }
+      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
+      case 2'1-
+        assign { \logical_op__insn$19$next \logical_op__data_len$18$next \logical_op__is_signed$17$next \logical_op__is_32bit$16$next \logical_op__output_carry$15$next \logical_op__write_cr0$14$next \logical_op__invert_out$13$next \logical_op__input_carry$12$next \logical_op__zero_a$11$next \logical_op__invert_a$10$next { \logical_op__oe__oe_ok$9$next \logical_op__oe__oe$8$next } { \logical_op__rc__rc_ok$7$next \logical_op__rc__rc$6$next } { \logical_op__imm_data__imm_ok$5$next \logical_op__imm_data__imm$4$next } \logical_op__fn_unit$3$next \logical_op__insn_type$2$next } { \logical_op__insn$94 \logical_op__data_len$93 \logical_op__is_signed$92 \logical_op__is_32bit$91 \logical_op__output_carry$90 \logical_op__write_cr0$89 \logical_op__invert_out$88 \logical_op__input_carry$87 \logical_op__zero_a$86 \logical_op__invert_a$85 { \logical_op__oe__oe_ok$84 \logical_op__oe__oe$83 } { \logical_op__rc__rc_ok$82 \logical_op__rc__rc$81 } { \logical_op__imm_data__imm_ok$80 \logical_op__imm_data__imm$79 } \logical_op__fn_unit$78 \logical_op__insn_type$77 }
+    end
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
+      case 1'1
+        assign \logical_op__imm_data__imm$4$next 64'0000000000000000000000000000000000000000000000000000000000000000
+        assign \logical_op__imm_data__imm_ok$5$next 1'0
+        assign \logical_op__rc__rc$6$next 1'0
+        assign \logical_op__rc__rc_ok$7$next 1'0
+        assign \logical_op__oe__oe$8$next 1'0
+        assign \logical_op__oe__oe_ok$9$next 1'0
+    end
+    sync init
+      update \logical_op__insn_type$2 7'0000000
+      update \logical_op__fn_unit$3 11'00000000000
+      update \logical_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000
+      update \logical_op__imm_data__imm_ok$5 1'0
+      update \logical_op__rc__rc$6 1'0
+      update \logical_op__rc__rc_ok$7 1'0
+      update \logical_op__oe__oe$8 1'0
+      update \logical_op__oe__oe_ok$9 1'0
+      update \logical_op__invert_a$10 1'0
+      update \logical_op__zero_a$11 1'0
+      update \logical_op__input_carry$12 2'00
+      update \logical_op__invert_out$13 1'0
+      update \logical_op__write_cr0$14 1'0
+      update \logical_op__output_carry$15 1'0
+      update \logical_op__is_32bit$16 1'0
+      update \logical_op__is_signed$17 1'0
+      update \logical_op__data_len$18 4'0000
+      update \logical_op__insn$19 32'00000000000000000000000000000000
+    sync posedge \coresync_clk
+      update \logical_op__insn_type$2 \logical_op__insn_type$2$next
+      update \logical_op__fn_unit$3 \logical_op__fn_unit$3$next
+      update \logical_op__imm_data__imm$4 \logical_op__imm_data__imm$4$next
+      update \logical_op__imm_data__imm_ok$5 \logical_op__imm_data__imm_ok$5$next
+      update \logical_op__rc__rc$6 \logical_op__rc__rc$6$next
+      update \logical_op__rc__rc_ok$7 \logical_op__rc__rc_ok$7$next
+      update \logical_op__oe__oe$8 \logical_op__oe__oe$8$next
+      update \logical_op__oe__oe_ok$9 \logical_op__oe__oe_ok$9$next
+      update \logical_op__invert_a$10 \logical_op__invert_a$10$next
+      update \logical_op__zero_a$11 \logical_op__zero_a$11$next
+      update \logical_op__input_carry$12 \logical_op__input_carry$12$next
+      update \logical_op__invert_out$13 \logical_op__invert_out$13$next
+      update \logical_op__write_cr0$14 \logical_op__write_cr0$14$next
+      update \logical_op__output_carry$15 \logical_op__output_carry$15$next
+      update \logical_op__is_32bit$16 \logical_op__is_32bit$16$next
+      update \logical_op__is_signed$17 \logical_op__is_signed$17$next
+      update \logical_op__data_len$18 \logical_op__data_len$18$next
+      update \logical_op__insn$19 \logical_op__insn$19$next
+  end
+  process $group_106
+    assign \o$next \o
+    assign \o_ok$next \o_ok
+    attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+    switch { \n_i_rdy_data \p_valid_i_p_ready_o }
+      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+      case 2'-1
+        assign { \o_ok$next \o$next } { \o_ok$96 \o$95 }
+      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
+      case 2'1-
+        assign { \o_ok$next \o$next } { \o_ok$96 \o$95 }
+    end
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
+      case 1'1
+        assign \o_ok$next 1'0
+    end
+    sync init
+      update \o 64'0000000000000000000000000000000000000000000000000000000000000000
+      update \o_ok 1'0
+    sync posedge \coresync_clk
+      update \o \o$next
+      update \o_ok \o_ok$next
+  end
+  process $group_108
+    assign \cr_a$next \cr_a
+    assign \cr_a_ok$next \cr_a_ok
+    attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+    switch { \n_i_rdy_data \p_valid_i_p_ready_o }
+      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+      case 2'-1
+        assign { \cr_a_ok$next \cr_a$next } { \cr_a_ok$98 \cr_a$97 }
+      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
+      case 2'1-
+        assign { \cr_a_ok$next \cr_a$next } { \cr_a_ok$98 \cr_a$97 }
+    end
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
+      case 1'1
+        assign \cr_a_ok$next 1'0
+    end
+    sync init
+      update \cr_a 4'0000
+      update \cr_a_ok 1'0
+    sync posedge \coresync_clk
+      update \cr_a \cr_a$next
+      update \cr_a_ok \cr_a_ok$next
+  end
+  process $group_110
+    assign \xer_ov$next \xer_ov
+    assign \xer_ov_ok$next \xer_ov_ok
+    attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+    switch { \n_i_rdy_data \p_valid_i_p_ready_o }
+      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+      case 2'-1
+        assign { \xer_ov_ok$next \xer_ov$next } { \xer_ov_ok$100 \xer_ov$99 }
+      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
+      case 2'1-
+        assign { \xer_ov_ok$next \xer_ov$next } { \xer_ov_ok$100 \xer_ov$99 }
+    end
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
+      case 1'1
+        assign \xer_ov_ok$next 1'0
+    end
+    sync init
+      update \xer_ov 2'00
+      update \xer_ov_ok 1'0
+    sync posedge \coresync_clk
+      update \xer_ov \xer_ov$next
+      update \xer_ov_ok \xer_ov_ok$next
+  end
+  process $group_112
+    assign \xer_so$20$next \xer_so$20
+    assign \xer_so_ok$next \xer_so_ok
+    attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+    switch { \n_i_rdy_data \p_valid_i_p_ready_o }
+      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+      case 2'-1
+        assign { \xer_so_ok$next \xer_so$20$next } { \xer_so_ok$102 \xer_so$101 }
+      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
+      case 2'1-
+        assign { \xer_so_ok$next \xer_so$20$next } { \xer_so_ok$102 \xer_so$101 }
+    end
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
+      case 1'1
+        assign \xer_so_ok$next 1'0
+    end
+    sync init
+      update \xer_so$20 1'0
+      update \xer_so_ok 1'0
+    sync posedge \coresync_clk
+      update \xer_so$20 \xer_so$20$next
+      update \xer_so_ok \xer_so_ok$next
+  end
+  process $group_114
+    assign \n_valid_o 1'0
+    assign \n_valid_o \r_busy
+    sync init
+  end
+  process $group_115
+    assign \p_ready_o 1'0
+    assign \p_ready_o \n_i_rdy_data
+    sync init
+  end
+  connect \cr_a$68 4'0000
+  connect \cr_a_ok$69 1'0
+  connect \xer_so_ok$72 1'0
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0"
+module \alu_div0
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 2 output 46 \xer_ov
+  wire width 1 output 1 \o_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 2 \xer_ov$next
+  wire width 1 output 2 \cr_a_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 47 \xer_ov_ok
+  wire width 1 output 3 \xer_ov_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 \xer_ov_ok$next
+  wire width 1 output 4 \xer_so_ok
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 5 \coresync_rst
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
+  wire width 1 output 6 \n_valid_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
+  wire width 1 input 7 \n_ready_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 48 \xer_so$18
+  wire width 64 output 8 \o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 \xer_so$18$next
+  wire width 4 output 9 \cr_a
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 49 \xer_so_ok
+  wire width 2 output 10 \xer_ov
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 \xer_so_ok$next
-  cell \p$77 \p
-    connect \p_valid_i \p_valid_i
-    connect \p_ready_o \p_ready_o
-  end
-  cell \n$78 \n
-    connect \n_valid_o \n_valid_o
-    connect \n_ready_i \n_ready_i
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
-  wire width 2 \mul3_muxid
+  wire width 1 output 11 \xer_so
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
   attribute \enum_value_0000001 "OP_NOP"
@@ -94186,7 +95781,7 @@ module \mul_pipe3
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 7 \mul3_mul_op__insn_type
+  wire width 7 input 12 \logical_op__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -94200,41 +95795,67 @@ module \mul_pipe3
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 11 \mul3_mul_op__fn_unit
+  wire width 11 input 13 \logical_op__fn_unit
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 64 \mul3_mul_op__imm_data__imm
+  wire width 64 input 14 \logical_op__imm_data__imm
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul3_mul_op__imm_data__imm_ok
+  wire width 1 input 15 \logical_op__imm_data__imm_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul3_mul_op__rc__rc
+  wire width 1 input 16 \logical_op__rc__rc
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul3_mul_op__rc__rc_ok
+  wire width 1 input 17 \logical_op__rc__rc_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul3_mul_op__oe__oe
+  wire width 1 input 18 \logical_op__oe__oe
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul3_mul_op__oe__oe_ok
+  wire width 1 input 19 \logical_op__oe__oe_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul3_mul_op__invert_a
+  wire width 1 input 20 \logical_op__invert_a
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul3_mul_op__zero_a
+  wire width 1 input 21 \logical_op__zero_a
+  attribute \enum_base_type "CryIn"
+  attribute \enum_value_00 "ZERO"
+  attribute \enum_value_01 "ONE"
+  attribute \enum_value_10 "CA"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul3_mul_op__invert_out
+  wire width 2 input 22 \logical_op__input_carry
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul3_mul_op__write_cr0
+  wire width 1 input 23 \logical_op__invert_out
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul3_mul_op__is_32bit
+  wire width 1 input 24 \logical_op__write_cr0
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul3_mul_op__is_signed
+  wire width 1 input 25 \logical_op__output_carry
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 32 \mul3_mul_op__insn
+  wire width 1 input 26 \logical_op__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 27 \logical_op__is_signed
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 4 input 28 \logical_op__data_len
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 input 29 \logical_op__insn
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
-  wire width 129 \mul3_o
+  wire width 64 input 30 \ra
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
-  wire width 1 \mul3_xer_so
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23"
-  wire width 1 \mul3_neg_res
+  wire width 64 input 31 \rb
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
+  wire width 1 input 32 \xer_so$1
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153"
+  wire width 1 input 33 \p_valid_i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154"
+  wire width 1 output 34 \p_ready_o
+  cell \p$70 \p
+    connect \p_valid_i \p_valid_i
+    connect \p_ready_o \p_ready_o
+  end
+  cell \n$71 \n
+    connect \n_valid_o \n_valid_o
+    connect \n_ready_i \n_ready_i
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
+  wire width 1 \pipe_start_n_valid_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
+  wire width 1 \pipe_start_n_ready_i
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
-  wire width 2 \mul3_muxid$19
+  wire width 2 \pipe_start_muxid
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
   attribute \enum_value_0000001 "OP_NOP"
@@ -94309,7 +95930,7 @@ module \mul_pipe3
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 7 \mul3_mul_op__insn_type$20
+  wire width 7 \pipe_start_logical_op__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -94323,87 +95944,71 @@ module \mul_pipe3
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 11 \mul3_mul_op__fn_unit$21
+  wire width 11 \pipe_start_logical_op__fn_unit
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 64 \mul3_mul_op__imm_data__imm$22
+  wire width 64 \pipe_start_logical_op__imm_data__imm
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul3_mul_op__imm_data__imm_ok$23
+  wire width 1 \pipe_start_logical_op__imm_data__imm_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul3_mul_op__rc__rc$24
+  wire width 1 \pipe_start_logical_op__rc__rc
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul3_mul_op__rc__rc_ok$25
+  wire width 1 \pipe_start_logical_op__rc__rc_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul3_mul_op__oe__oe$26
+  wire width 1 \pipe_start_logical_op__oe__oe
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul3_mul_op__oe__oe_ok$27
+  wire width 1 \pipe_start_logical_op__oe__oe_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul3_mul_op__invert_a$28
+  wire width 1 \pipe_start_logical_op__invert_a
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul3_mul_op__zero_a$29
+  wire width 1 \pipe_start_logical_op__zero_a
+  attribute \enum_base_type "CryIn"
+  attribute \enum_value_00 "ZERO"
+  attribute \enum_value_01 "ONE"
+  attribute \enum_value_10 "CA"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul3_mul_op__invert_out$30
+  wire width 2 \pipe_start_logical_op__input_carry
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul3_mul_op__write_cr0$31
+  wire width 1 \pipe_start_logical_op__invert_out
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul3_mul_op__is_32bit$32
+  wire width 1 \pipe_start_logical_op__write_cr0
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul3_mul_op__is_signed$33
+  wire width 1 \pipe_start_logical_op__output_carry
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 32 \mul3_mul_op__insn$34
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 64 \mul3_o$35
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 \mul3_o_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 2 \mul3_xer_ov
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 \mul3_xer_ov_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 \mul3_xer_so$36
-  cell \mul3 \mul3
-    connect \muxid \mul3_muxid
-    connect \mul_op__insn_type \mul3_mul_op__insn_type
-    connect \mul_op__fn_unit \mul3_mul_op__fn_unit
-    connect \mul_op__imm_data__imm \mul3_mul_op__imm_data__imm
-    connect \mul_op__imm_data__imm_ok \mul3_mul_op__imm_data__imm_ok
-    connect \mul_op__rc__rc \mul3_mul_op__rc__rc
-    connect \mul_op__rc__rc_ok \mul3_mul_op__rc__rc_ok
-    connect \mul_op__oe__oe \mul3_mul_op__oe__oe
-    connect \mul_op__oe__oe_ok \mul3_mul_op__oe__oe_ok
-    connect \mul_op__invert_a \mul3_mul_op__invert_a
-    connect \mul_op__zero_a \mul3_mul_op__zero_a
-    connect \mul_op__invert_out \mul3_mul_op__invert_out
-    connect \mul_op__write_cr0 \mul3_mul_op__write_cr0
-    connect \mul_op__is_32bit \mul3_mul_op__is_32bit
-    connect \mul_op__is_signed \mul3_mul_op__is_signed
-    connect \mul_op__insn \mul3_mul_op__insn
-    connect \o \mul3_o
-    connect \xer_so \mul3_xer_so
-    connect \neg_res \mul3_neg_res
-    connect \muxid$1 \mul3_muxid$19
-    connect \mul_op__insn_type$2 \mul3_mul_op__insn_type$20
-    connect \mul_op__fn_unit$3 \mul3_mul_op__fn_unit$21
-    connect \mul_op__imm_data__imm$4 \mul3_mul_op__imm_data__imm$22
-    connect \mul_op__imm_data__imm_ok$5 \mul3_mul_op__imm_data__imm_ok$23
-    connect \mul_op__rc__rc$6 \mul3_mul_op__rc__rc$24
-    connect \mul_op__rc__rc_ok$7 \mul3_mul_op__rc__rc_ok$25
-    connect \mul_op__oe__oe$8 \mul3_mul_op__oe__oe$26
-    connect \mul_op__oe__oe_ok$9 \mul3_mul_op__oe__oe_ok$27
-    connect \mul_op__invert_a$10 \mul3_mul_op__invert_a$28
-    connect \mul_op__zero_a$11 \mul3_mul_op__zero_a$29
-    connect \mul_op__invert_out$12 \mul3_mul_op__invert_out$30
-    connect \mul_op__write_cr0$13 \mul3_mul_op__write_cr0$31
-    connect \mul_op__is_32bit$14 \mul3_mul_op__is_32bit$32
-    connect \mul_op__is_signed$15 \mul3_mul_op__is_signed$33
-    connect \mul_op__insn$16 \mul3_mul_op__insn$34
-    connect \o$17 \mul3_o$35
-    connect \o_ok \mul3_o_ok
-    connect \xer_ov \mul3_xer_ov
-    connect \xer_ov_ok \mul3_xer_ov_ok
-    connect \xer_so$18 \mul3_xer_so$36
-  end
+  wire width 1 \pipe_start_logical_op__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \pipe_start_logical_op__is_signed
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 4 \pipe_start_logical_op__data_len
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \pipe_start_logical_op__insn
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
+  wire width 64 \pipe_start_ra
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
+  wire width 64 \pipe_start_rb
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
+  wire width 1 \pipe_start_xer_so
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160"
+  wire width 1 \pipe_start_divisor_neg
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161"
+  wire width 1 \pipe_start_dividend_neg
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167"
+  wire width 1 \pipe_start_dive_abs_ov32
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168"
+  wire width 1 \pipe_start_dive_abs_ov64
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162"
+  wire width 1 \pipe_start_div_by_zero
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18"
+  wire width 128 \pipe_start_dividend
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19"
+  wire width 64 \pipe_start_divisor_radicand
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21"
+  wire width 2 \pipe_start_operation
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153"
+  wire width 1 \pipe_start_p_valid_i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154"
+  wire width 1 \pipe_start_p_ready_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
-  wire width 2 \output_muxid
+  wire width 2 \pipe_start_muxid$2
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
   attribute \enum_value_0000001 "OP_NOP"
@@ -94478,7 +96083,7 @@ module \mul_pipe3
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 7 \output_mul_op__insn_type
+  wire width 7 \pipe_start_logical_op__insn_type$3
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -94492,45 +96097,115 @@ module \mul_pipe3
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 11 \output_mul_op__fn_unit
+  wire width 11 \pipe_start_logical_op__fn_unit$4
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 64 \output_mul_op__imm_data__imm
+  wire width 64 \pipe_start_logical_op__imm_data__imm$5
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \output_mul_op__imm_data__imm_ok
+  wire width 1 \pipe_start_logical_op__imm_data__imm_ok$6
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \output_mul_op__rc__rc
+  wire width 1 \pipe_start_logical_op__rc__rc$7
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \output_mul_op__rc__rc_ok
+  wire width 1 \pipe_start_logical_op__rc__rc_ok$8
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \output_mul_op__oe__oe
+  wire width 1 \pipe_start_logical_op__oe__oe$9
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \output_mul_op__oe__oe_ok
+  wire width 1 \pipe_start_logical_op__oe__oe_ok$10
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \output_mul_op__invert_a
+  wire width 1 \pipe_start_logical_op__invert_a$11
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \output_mul_op__zero_a
+  wire width 1 \pipe_start_logical_op__zero_a$12
+  attribute \enum_base_type "CryIn"
+  attribute \enum_value_00 "ZERO"
+  attribute \enum_value_01 "ONE"
+  attribute \enum_value_10 "CA"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \output_mul_op__invert_out
+  wire width 2 \pipe_start_logical_op__input_carry$13
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \output_mul_op__write_cr0
+  wire width 1 \pipe_start_logical_op__invert_out$14
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \output_mul_op__is_32bit
+  wire width 1 \pipe_start_logical_op__write_cr0$15
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \output_mul_op__is_signed
+  wire width 1 \pipe_start_logical_op__output_carry$16
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 32 \output_mul_op__insn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 64 \output_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 \output_o_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 4 \output_cr_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 2 \output_xer_ov
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 \output_xer_so
+  wire width 1 \pipe_start_logical_op__is_32bit$17
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \pipe_start_logical_op__is_signed$18
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 4 \pipe_start_logical_op__data_len$19
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \pipe_start_logical_op__insn$20
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
+  wire width 64 \pipe_start_ra$21
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
+  wire width 64 \pipe_start_rb$22
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
+  wire width 1 \pipe_start_xer_so$23
+  cell \pipe_start \pipe_start
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
+    connect \n_valid_o \pipe_start_n_valid_o
+    connect \n_ready_i \pipe_start_n_ready_i
+    connect \muxid \pipe_start_muxid
+    connect \logical_op__insn_type \pipe_start_logical_op__insn_type
+    connect \logical_op__fn_unit \pipe_start_logical_op__fn_unit
+    connect \logical_op__imm_data__imm \pipe_start_logical_op__imm_data__imm
+    connect \logical_op__imm_data__imm_ok \pipe_start_logical_op__imm_data__imm_ok
+    connect \logical_op__rc__rc \pipe_start_logical_op__rc__rc
+    connect \logical_op__rc__rc_ok \pipe_start_logical_op__rc__rc_ok
+    connect \logical_op__oe__oe \pipe_start_logical_op__oe__oe
+    connect \logical_op__oe__oe_ok \pipe_start_logical_op__oe__oe_ok
+    connect \logical_op__invert_a \pipe_start_logical_op__invert_a
+    connect \logical_op__zero_a \pipe_start_logical_op__zero_a
+    connect \logical_op__input_carry \pipe_start_logical_op__input_carry
+    connect \logical_op__invert_out \pipe_start_logical_op__invert_out
+    connect \logical_op__write_cr0 \pipe_start_logical_op__write_cr0
+    connect \logical_op__output_carry \pipe_start_logical_op__output_carry
+    connect \logical_op__is_32bit \pipe_start_logical_op__is_32bit
+    connect \logical_op__is_signed \pipe_start_logical_op__is_signed
+    connect \logical_op__data_len \pipe_start_logical_op__data_len
+    connect \logical_op__insn \pipe_start_logical_op__insn
+    connect \ra \pipe_start_ra
+    connect \rb \pipe_start_rb
+    connect \xer_so \pipe_start_xer_so
+    connect \divisor_neg \pipe_start_divisor_neg
+    connect \dividend_neg \pipe_start_dividend_neg
+    connect \dive_abs_ov32 \pipe_start_dive_abs_ov32
+    connect \dive_abs_ov64 \pipe_start_dive_abs_ov64
+    connect \div_by_zero \pipe_start_div_by_zero
+    connect \dividend \pipe_start_dividend
+    connect \divisor_radicand \pipe_start_divisor_radicand
+    connect \operation \pipe_start_operation
+    connect \p_valid_i \pipe_start_p_valid_i
+    connect \p_ready_o \pipe_start_p_ready_o
+    connect \muxid$1 \pipe_start_muxid$2
+    connect \logical_op__insn_type$2 \pipe_start_logical_op__insn_type$3
+    connect \logical_op__fn_unit$3 \pipe_start_logical_op__fn_unit$4
+    connect \logical_op__imm_data__imm$4 \pipe_start_logical_op__imm_data__imm$5
+    connect \logical_op__imm_data__imm_ok$5 \pipe_start_logical_op__imm_data__imm_ok$6
+    connect \logical_op__rc__rc$6 \pipe_start_logical_op__rc__rc$7
+    connect \logical_op__rc__rc_ok$7 \pipe_start_logical_op__rc__rc_ok$8
+    connect \logical_op__oe__oe$8 \pipe_start_logical_op__oe__oe$9
+    connect \logical_op__oe__oe_ok$9 \pipe_start_logical_op__oe__oe_ok$10
+    connect \logical_op__invert_a$10 \pipe_start_logical_op__invert_a$11
+    connect \logical_op__zero_a$11 \pipe_start_logical_op__zero_a$12
+    connect \logical_op__input_carry$12 \pipe_start_logical_op__input_carry$13
+    connect \logical_op__invert_out$13 \pipe_start_logical_op__invert_out$14
+    connect \logical_op__write_cr0$14 \pipe_start_logical_op__write_cr0$15
+    connect \logical_op__output_carry$15 \pipe_start_logical_op__output_carry$16
+    connect \logical_op__is_32bit$16 \pipe_start_logical_op__is_32bit$17
+    connect \logical_op__is_signed$17 \pipe_start_logical_op__is_signed$18
+    connect \logical_op__data_len$18 \pipe_start_logical_op__data_len$19
+    connect \logical_op__insn$19 \pipe_start_logical_op__insn$20
+    connect \ra$20 \pipe_start_ra$21
+    connect \rb$21 \pipe_start_rb$22
+    connect \xer_so$22 \pipe_start_xer_so$23
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153"
+  wire width 1 \pipe_middle_0_p_valid_i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154"
+  wire width 1 \pipe_middle_0_p_ready_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
-  wire width 2 \output_muxid$37
+  wire width 2 \pipe_middle_0_muxid
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
   attribute \enum_value_0000001 "OP_NOP"
@@ -94605,7 +96280,7 @@ module \mul_pipe3
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 7 \output_mul_op__insn_type$38
+  wire width 7 \pipe_middle_0_logical_op__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -94619,243 +96294,71 @@ module \mul_pipe3
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 11 \output_mul_op__fn_unit$39
+  wire width 11 \pipe_middle_0_logical_op__fn_unit
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 64 \output_mul_op__imm_data__imm$40
+  wire width 64 \pipe_middle_0_logical_op__imm_data__imm
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \output_mul_op__imm_data__imm_ok$41
+  wire width 1 \pipe_middle_0_logical_op__imm_data__imm_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \output_mul_op__rc__rc$42
+  wire width 1 \pipe_middle_0_logical_op__rc__rc
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \output_mul_op__rc__rc_ok$43
+  wire width 1 \pipe_middle_0_logical_op__rc__rc_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \output_mul_op__oe__oe$44
+  wire width 1 \pipe_middle_0_logical_op__oe__oe
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \output_mul_op__oe__oe_ok$45
+  wire width 1 \pipe_middle_0_logical_op__oe__oe_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \output_mul_op__invert_a$46
+  wire width 1 \pipe_middle_0_logical_op__invert_a
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \output_mul_op__zero_a$47
+  wire width 1 \pipe_middle_0_logical_op__zero_a
+  attribute \enum_base_type "CryIn"
+  attribute \enum_value_00 "ZERO"
+  attribute \enum_value_01 "ONE"
+  attribute \enum_value_10 "CA"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \output_mul_op__invert_out$48
+  wire width 2 \pipe_middle_0_logical_op__input_carry
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \output_mul_op__write_cr0$49
+  wire width 1 \pipe_middle_0_logical_op__invert_out
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \output_mul_op__is_32bit$50
+  wire width 1 \pipe_middle_0_logical_op__write_cr0
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \output_mul_op__is_signed$51
+  wire width 1 \pipe_middle_0_logical_op__output_carry
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 32 \output_mul_op__insn$52
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 64 \output_o$53
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 \output_o_ok$54
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 4 \output_cr_a$55
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 \output_cr_a_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 2 \output_xer_ov$56
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 \output_xer_ov_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 \output_xer_so$57
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 \output_xer_so_ok
-  cell \output$79 \output
-    connect \muxid \output_muxid
-    connect \mul_op__insn_type \output_mul_op__insn_type
-    connect \mul_op__fn_unit \output_mul_op__fn_unit
-    connect \mul_op__imm_data__imm \output_mul_op__imm_data__imm
-    connect \mul_op__imm_data__imm_ok \output_mul_op__imm_data__imm_ok
-    connect \mul_op__rc__rc \output_mul_op__rc__rc
-    connect \mul_op__rc__rc_ok \output_mul_op__rc__rc_ok
-    connect \mul_op__oe__oe \output_mul_op__oe__oe
-    connect \mul_op__oe__oe_ok \output_mul_op__oe__oe_ok
-    connect \mul_op__invert_a \output_mul_op__invert_a
-    connect \mul_op__zero_a \output_mul_op__zero_a
-    connect \mul_op__invert_out \output_mul_op__invert_out
-    connect \mul_op__write_cr0 \output_mul_op__write_cr0
-    connect \mul_op__is_32bit \output_mul_op__is_32bit
-    connect \mul_op__is_signed \output_mul_op__is_signed
-    connect \mul_op__insn \output_mul_op__insn
-    connect \o \output_o
-    connect \o_ok \output_o_ok
-    connect \cr_a \output_cr_a
-    connect \xer_ov \output_xer_ov
-    connect \xer_so \output_xer_so
-    connect \muxid$1 \output_muxid$37
-    connect \mul_op__insn_type$2 \output_mul_op__insn_type$38
-    connect \mul_op__fn_unit$3 \output_mul_op__fn_unit$39
-    connect \mul_op__imm_data__imm$4 \output_mul_op__imm_data__imm$40
-    connect \mul_op__imm_data__imm_ok$5 \output_mul_op__imm_data__imm_ok$41
-    connect \mul_op__rc__rc$6 \output_mul_op__rc__rc$42
-    connect \mul_op__rc__rc_ok$7 \output_mul_op__rc__rc_ok$43
-    connect \mul_op__oe__oe$8 \output_mul_op__oe__oe$44
-    connect \mul_op__oe__oe_ok$9 \output_mul_op__oe__oe_ok$45
-    connect \mul_op__invert_a$10 \output_mul_op__invert_a$46
-    connect \mul_op__zero_a$11 \output_mul_op__zero_a$47
-    connect \mul_op__invert_out$12 \output_mul_op__invert_out$48
-    connect \mul_op__write_cr0$13 \output_mul_op__write_cr0$49
-    connect \mul_op__is_32bit$14 \output_mul_op__is_32bit$50
-    connect \mul_op__is_signed$15 \output_mul_op__is_signed$51
-    connect \mul_op__insn$16 \output_mul_op__insn$52
-    connect \o$17 \output_o$53
-    connect \o_ok$18 \output_o_ok$54
-    connect \cr_a$19 \output_cr_a$55
-    connect \cr_a_ok \output_cr_a_ok
-    connect \xer_ov$20 \output_xer_ov$56
-    connect \xer_ov_ok \output_xer_ov_ok
-    connect \xer_so$21 \output_xer_so$57
-    connect \xer_so_ok \output_xer_so_ok
-  end
-  process $group_0
-    assign \mul3_muxid 2'00
-    assign \mul3_muxid \muxid
-    sync init
-  end
-  process $group_1
-    assign \mul3_mul_op__insn_type 7'0000000
-    assign \mul3_mul_op__fn_unit 11'00000000000
-    assign \mul3_mul_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \mul3_mul_op__imm_data__imm_ok 1'0
-    assign \mul3_mul_op__rc__rc 1'0
-    assign \mul3_mul_op__rc__rc_ok 1'0
-    assign \mul3_mul_op__oe__oe 1'0
-    assign \mul3_mul_op__oe__oe_ok 1'0
-    assign \mul3_mul_op__invert_a 1'0
-    assign \mul3_mul_op__zero_a 1'0
-    assign \mul3_mul_op__invert_out 1'0
-    assign \mul3_mul_op__write_cr0 1'0
-    assign \mul3_mul_op__is_32bit 1'0
-    assign \mul3_mul_op__is_signed 1'0
-    assign \mul3_mul_op__insn 32'00000000000000000000000000000000
-    assign { \mul3_mul_op__insn \mul3_mul_op__is_signed \mul3_mul_op__is_32bit \mul3_mul_op__write_cr0 \mul3_mul_op__invert_out \mul3_mul_op__zero_a \mul3_mul_op__invert_a { \mul3_mul_op__oe__oe_ok \mul3_mul_op__oe__oe } { \mul3_mul_op__rc__rc_ok \mul3_mul_op__rc__rc } { \mul3_mul_op__imm_data__imm_ok \mul3_mul_op__imm_data__imm } \mul3_mul_op__fn_unit \mul3_mul_op__insn_type } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__invert_out \mul_op__zero_a \mul_op__invert_a { \mul_op__oe__oe_ok \mul_op__oe__oe } { \mul_op__rc__rc_ok \mul_op__rc__rc } { \mul_op__imm_data__imm_ok \mul_op__imm_data__imm } \mul_op__fn_unit \mul_op__insn_type }
-    sync init
-  end
-  process $group_16
-    assign \mul3_o 129'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
-    assign \mul3_o \o
-    sync init
-  end
-  process $group_17
-    assign \mul3_xer_so 1'0
-    assign \mul3_xer_so \xer_so
-    sync init
-  end
-  process $group_18
-    assign \mul3_neg_res 1'0
-    assign \mul3_neg_res \neg_res
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24"
-  wire width 1 \neg_res32$58
-  process $group_19
-    assign \neg_res32$58 1'0
-    assign \neg_res32$58 \neg_res32
-    sync init
-  end
-  process $group_20
-    assign \output_muxid 2'00
-    assign \output_muxid \mul3_muxid$19
-    sync init
-  end
-  process $group_21
-    assign \output_mul_op__insn_type 7'0000000
-    assign \output_mul_op__fn_unit 11'00000000000
-    assign \output_mul_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \output_mul_op__imm_data__imm_ok 1'0
-    assign \output_mul_op__rc__rc 1'0
-    assign \output_mul_op__rc__rc_ok 1'0
-    assign \output_mul_op__oe__oe 1'0
-    assign \output_mul_op__oe__oe_ok 1'0
-    assign \output_mul_op__invert_a 1'0
-    assign \output_mul_op__zero_a 1'0
-    assign \output_mul_op__invert_out 1'0
-    assign \output_mul_op__write_cr0 1'0
-    assign \output_mul_op__is_32bit 1'0
-    assign \output_mul_op__is_signed 1'0
-    assign \output_mul_op__insn 32'00000000000000000000000000000000
-    assign { \output_mul_op__insn \output_mul_op__is_signed \output_mul_op__is_32bit \output_mul_op__write_cr0 \output_mul_op__invert_out \output_mul_op__zero_a \output_mul_op__invert_a { \output_mul_op__oe__oe_ok \output_mul_op__oe__oe } { \output_mul_op__rc__rc_ok \output_mul_op__rc__rc } { \output_mul_op__imm_data__imm_ok \output_mul_op__imm_data__imm } \output_mul_op__fn_unit \output_mul_op__insn_type } { \mul3_mul_op__insn$34 \mul3_mul_op__is_signed$33 \mul3_mul_op__is_32bit$32 \mul3_mul_op__write_cr0$31 \mul3_mul_op__invert_out$30 \mul3_mul_op__zero_a$29 \mul3_mul_op__invert_a$28 { \mul3_mul_op__oe__oe_ok$27 \mul3_mul_op__oe__oe$26 } { \mul3_mul_op__rc__rc_ok$25 \mul3_mul_op__rc__rc$24 } { \mul3_mul_op__imm_data__imm_ok$23 \mul3_mul_op__imm_data__imm$22 } \mul3_mul_op__fn_unit$21 \mul3_mul_op__insn_type$20 }
-    sync init
-  end
-  process $group_36
-    assign \output_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \output_o_ok 1'0
-    assign { \output_o_ok \output_o } { \mul3_o_ok \mul3_o$35 }
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 \cr_a_ok$59
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 4 \cr_a$60
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 \cr_a_ok$61
-  process $group_38
-    assign \output_cr_a 4'0000
-    assign \cr_a_ok$59 1'0
-    assign { \cr_a_ok$59 \output_cr_a } { \cr_a_ok$61 \cr_a$60 }
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 \xer_ov_ok$62
-  process $group_40
-    assign \output_xer_ov 2'00
-    assign \xer_ov_ok$62 1'0
-    assign { \xer_ov_ok$62 \output_xer_ov } { \mul3_xer_ov_ok \mul3_xer_ov }
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 \xer_so_ok$63
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 \xer_so_ok$64
-  process $group_42
-    assign \output_xer_so 1'0
-    assign \xer_so_ok$63 1'0
-    assign { \xer_so_ok$63 \output_xer_so } { \xer_so_ok$64 \mul3_xer_so$36 }
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621"
-  wire width 1 \p_valid_i$65
-  process $group_44
-    assign \p_valid_i$65 1'0
-    assign \p_valid_i$65 \p_valid_i
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619"
-  wire width 1 \n_i_rdy_data
-  process $group_45
-    assign \n_i_rdy_data 1'0
-    assign \n_i_rdy_data \n_ready_i
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620"
-  wire width 1 \p_valid_i_p_ready_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624"
-  wire width 1 $66
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624"
-  cell $and $67
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \p_valid_i$65
-    connect \B \p_ready_o
-    connect \Y $66
-  end
-  process $group_46
-    assign \p_valid_i_p_ready_o 1'0
-    assign \p_valid_i_p_ready_o $66
-    sync init
-  end
+  wire width 1 \pipe_middle_0_logical_op__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \pipe_middle_0_logical_op__is_signed
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 4 \pipe_middle_0_logical_op__data_len
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \pipe_middle_0_logical_op__insn
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
+  wire width 64 \pipe_middle_0_ra
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
+  wire width 64 \pipe_middle_0_rb
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
+  wire width 1 \pipe_middle_0_xer_so
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160"
+  wire width 1 \pipe_middle_0_divisor_neg
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161"
+  wire width 1 \pipe_middle_0_dividend_neg
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167"
+  wire width 1 \pipe_middle_0_dive_abs_ov32
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168"
+  wire width 1 \pipe_middle_0_dive_abs_ov64
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162"
+  wire width 1 \pipe_middle_0_div_by_zero
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18"
+  wire width 128 \pipe_middle_0_dividend
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19"
+  wire width 64 \pipe_middle_0_divisor_radicand
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21"
+  wire width 2 \pipe_middle_0_operation
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
+  wire width 1 \pipe_middle_0_n_valid_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
+  wire width 1 \pipe_middle_0_n_ready_i
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
-  wire width 2 \muxid$68
-  process $group_47
-    assign \muxid$68 2'00
-    assign \muxid$68 \output_muxid$37
-    sync init
-  end
+  wire width 2 \pipe_middle_0_muxid$24
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
   attribute \enum_value_0000001 "OP_NOP"
@@ -94930,7 +96433,7 @@ module \mul_pipe3
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 7 \mul_op__insn_type$69
+  wire width 7 \pipe_middle_0_logical_op__insn_type$25
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -94944,338 +96447,136 @@ module \mul_pipe3
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 11 \mul_op__fn_unit$70
+  wire width 11 \pipe_middle_0_logical_op__fn_unit$26
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 64 \mul_op__imm_data__imm$71
+  wire width 64 \pipe_middle_0_logical_op__imm_data__imm$27
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_op__imm_data__imm_ok$72
+  wire width 1 \pipe_middle_0_logical_op__imm_data__imm_ok$28
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_op__rc__rc$73
+  wire width 1 \pipe_middle_0_logical_op__rc__rc$29
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_op__rc__rc_ok$74
+  wire width 1 \pipe_middle_0_logical_op__rc__rc_ok$30
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_op__oe__oe$75
+  wire width 1 \pipe_middle_0_logical_op__oe__oe$31
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_op__oe__oe_ok$76
+  wire width 1 \pipe_middle_0_logical_op__oe__oe_ok$32
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_op__invert_a$77
+  wire width 1 \pipe_middle_0_logical_op__invert_a$33
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_op__zero_a$78
+  wire width 1 \pipe_middle_0_logical_op__zero_a$34
+  attribute \enum_base_type "CryIn"
+  attribute \enum_value_00 "ZERO"
+  attribute \enum_value_01 "ONE"
+  attribute \enum_value_10 "CA"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_op__invert_out$79
+  wire width 2 \pipe_middle_0_logical_op__input_carry$35
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_op__write_cr0$80
+  wire width 1 \pipe_middle_0_logical_op__invert_out$36
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_op__is_32bit$81
+  wire width 1 \pipe_middle_0_logical_op__write_cr0$37
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_op__is_signed$82
+  wire width 1 \pipe_middle_0_logical_op__output_carry$38
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 32 \mul_op__insn$83
-  process $group_48
-    assign \mul_op__insn_type$69 7'0000000
-    assign \mul_op__fn_unit$70 11'00000000000
-    assign \mul_op__imm_data__imm$71 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \mul_op__imm_data__imm_ok$72 1'0
-    assign \mul_op__rc__rc$73 1'0
-    assign \mul_op__rc__rc_ok$74 1'0
-    assign \mul_op__oe__oe$75 1'0
-    assign \mul_op__oe__oe_ok$76 1'0
-    assign \mul_op__invert_a$77 1'0
-    assign \mul_op__zero_a$78 1'0
-    assign \mul_op__invert_out$79 1'0
-    assign \mul_op__write_cr0$80 1'0
-    assign \mul_op__is_32bit$81 1'0
-    assign \mul_op__is_signed$82 1'0
-    assign \mul_op__insn$83 32'00000000000000000000000000000000
-    assign { \mul_op__insn$83 \mul_op__is_signed$82 \mul_op__is_32bit$81 \mul_op__write_cr0$80 \mul_op__invert_out$79 \mul_op__zero_a$78 \mul_op__invert_a$77 { \mul_op__oe__oe_ok$76 \mul_op__oe__oe$75 } { \mul_op__rc__rc_ok$74 \mul_op__rc__rc$73 } { \mul_op__imm_data__imm_ok$72 \mul_op__imm_data__imm$71 } \mul_op__fn_unit$70 \mul_op__insn_type$69 } { \output_mul_op__insn$52 \output_mul_op__is_signed$51 \output_mul_op__is_32bit$50 \output_mul_op__write_cr0$49 \output_mul_op__invert_out$48 \output_mul_op__zero_a$47 \output_mul_op__invert_a$46 { \output_mul_op__oe__oe_ok$45 \output_mul_op__oe__oe$44 } { \output_mul_op__rc__rc_ok$43 \output_mul_op__rc__rc$42 } { \output_mul_op__imm_data__imm_ok$41 \output_mul_op__imm_data__imm$40 } \output_mul_op__fn_unit$39 \output_mul_op__insn_type$38 }
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 64 \o$84
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 \o_ok$85
-  process $group_63
-    assign \o$84 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \o_ok$85 1'0
-    assign { \o_ok$85 \o$84 } { \output_o_ok$54 \output_o$53 }
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 4 \cr_a$86
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 \cr_a_ok$87
-  process $group_65
-    assign \cr_a$86 4'0000
-    assign \cr_a_ok$87 1'0
-    assign { \cr_a_ok$87 \cr_a$86 } { \output_cr_a_ok \output_cr_a$55 }
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 2 \xer_ov$88
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 \xer_ov_ok$89
-  process $group_67
-    assign \xer_ov$88 2'00
-    assign \xer_ov_ok$89 1'0
-    assign { \xer_ov_ok$89 \xer_ov$88 } { \output_xer_ov_ok \output_xer_ov$56 }
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 \xer_so$90
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 \xer_so_ok$91
-  process $group_69
-    assign \xer_so$90 1'0
-    assign \xer_so_ok$91 1'0
-    assign { \xer_so_ok$91 \xer_so$90 } { \output_xer_so_ok \output_xer_so$57 }
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615"
-  wire width 1 \r_busy
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615"
-  wire width 1 \r_busy$next
-  process $group_71
-    assign \r_busy$next \r_busy
-    attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
-    switch { \n_i_rdy_data \p_valid_i_p_ready_o }
-      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
-      case 2'-1
-        assign \r_busy$next 1'1
-      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
-      case 2'1-
-        assign \r_busy$next 1'0
-    end
-    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
-      case 1'1
-        assign \r_busy$next 1'0
-    end
-    sync init
-      update \r_busy 1'0
-    sync posedge \clk
-      update \r_busy \r_busy$next
-  end
-  process $group_72
-    assign \muxid$1$next \muxid$1
-    attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
-    switch { \n_i_rdy_data \p_valid_i_p_ready_o }
-      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
-      case 2'-1
-        assign \muxid$1$next \muxid$68
-      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
-      case 2'1-
-        assign \muxid$1$next \muxid$68
-    end
-    sync init
-      update \muxid$1 2'00
-    sync posedge \clk
-      update \muxid$1 \muxid$1$next
-  end
-  process $group_73
-    assign \mul_op__insn_type$2$next \mul_op__insn_type$2
-    assign \mul_op__fn_unit$3$next \mul_op__fn_unit$3
-    assign \mul_op__imm_data__imm$4$next \mul_op__imm_data__imm$4
-    assign \mul_op__imm_data__imm_ok$5$next \mul_op__imm_data__imm_ok$5
-    assign \mul_op__rc__rc$6$next \mul_op__rc__rc$6
-    assign \mul_op__rc__rc_ok$7$next \mul_op__rc__rc_ok$7
-    assign \mul_op__oe__oe$8$next \mul_op__oe__oe$8
-    assign \mul_op__oe__oe_ok$9$next \mul_op__oe__oe_ok$9
-    assign \mul_op__invert_a$10$next \mul_op__invert_a$10
-    assign \mul_op__zero_a$11$next \mul_op__zero_a$11
-    assign \mul_op__invert_out$12$next \mul_op__invert_out$12
-    assign \mul_op__write_cr0$13$next \mul_op__write_cr0$13
-    assign \mul_op__is_32bit$14$next \mul_op__is_32bit$14
-    assign \mul_op__is_signed$15$next \mul_op__is_signed$15
-    assign \mul_op__insn$16$next \mul_op__insn$16
-    attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
-    switch { \n_i_rdy_data \p_valid_i_p_ready_o }
-      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
-      case 2'-1
-        assign { \mul_op__insn$16$next \mul_op__is_signed$15$next \mul_op__is_32bit$14$next \mul_op__write_cr0$13$next \mul_op__invert_out$12$next \mul_op__zero_a$11$next \mul_op__invert_a$10$next { \mul_op__oe__oe_ok$9$next \mul_op__oe__oe$8$next } { \mul_op__rc__rc_ok$7$next \mul_op__rc__rc$6$next } { \mul_op__imm_data__imm_ok$5$next \mul_op__imm_data__imm$4$next } \mul_op__fn_unit$3$next \mul_op__insn_type$2$next } { \mul_op__insn$83 \mul_op__is_signed$82 \mul_op__is_32bit$81 \mul_op__write_cr0$80 \mul_op__invert_out$79 \mul_op__zero_a$78 \mul_op__invert_a$77 { \mul_op__oe__oe_ok$76 \mul_op__oe__oe$75 } { \mul_op__rc__rc_ok$74 \mul_op__rc__rc$73 } { \mul_op__imm_data__imm_ok$72 \mul_op__imm_data__imm$71 } \mul_op__fn_unit$70 \mul_op__insn_type$69 }
-      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
-      case 2'1-
-        assign { \mul_op__insn$16$next \mul_op__is_signed$15$next \mul_op__is_32bit$14$next \mul_op__write_cr0$13$next \mul_op__invert_out$12$next \mul_op__zero_a$11$next \mul_op__invert_a$10$next { \mul_op__oe__oe_ok$9$next \mul_op__oe__oe$8$next } { \mul_op__rc__rc_ok$7$next \mul_op__rc__rc$6$next } { \mul_op__imm_data__imm_ok$5$next \mul_op__imm_data__imm$4$next } \mul_op__fn_unit$3$next \mul_op__insn_type$2$next } { \mul_op__insn$83 \mul_op__is_signed$82 \mul_op__is_32bit$81 \mul_op__write_cr0$80 \mul_op__invert_out$79 \mul_op__zero_a$78 \mul_op__invert_a$77 { \mul_op__oe__oe_ok$76 \mul_op__oe__oe$75 } { \mul_op__rc__rc_ok$74 \mul_op__rc__rc$73 } { \mul_op__imm_data__imm_ok$72 \mul_op__imm_data__imm$71 } \mul_op__fn_unit$70 \mul_op__insn_type$69 }
-    end
-    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
-      case 1'1
-        assign \mul_op__imm_data__imm$4$next 64'0000000000000000000000000000000000000000000000000000000000000000
-        assign \mul_op__imm_data__imm_ok$5$next 1'0
-        assign \mul_op__rc__rc$6$next 1'0
-        assign \mul_op__rc__rc_ok$7$next 1'0
-        assign \mul_op__oe__oe$8$next 1'0
-        assign \mul_op__oe__oe_ok$9$next 1'0
-    end
-    sync init
-      update \mul_op__insn_type$2 7'0000000
-      update \mul_op__fn_unit$3 11'00000000000
-      update \mul_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000
-      update \mul_op__imm_data__imm_ok$5 1'0
-      update \mul_op__rc__rc$6 1'0
-      update \mul_op__rc__rc_ok$7 1'0
-      update \mul_op__oe__oe$8 1'0
-      update \mul_op__oe__oe_ok$9 1'0
-      update \mul_op__invert_a$10 1'0
-      update \mul_op__zero_a$11 1'0
-      update \mul_op__invert_out$12 1'0
-      update \mul_op__write_cr0$13 1'0
-      update \mul_op__is_32bit$14 1'0
-      update \mul_op__is_signed$15 1'0
-      update \mul_op__insn$16 32'00000000000000000000000000000000
-    sync posedge \clk
-      update \mul_op__insn_type$2 \mul_op__insn_type$2$next
-      update \mul_op__fn_unit$3 \mul_op__fn_unit$3$next
-      update \mul_op__imm_data__imm$4 \mul_op__imm_data__imm$4$next
-      update \mul_op__imm_data__imm_ok$5 \mul_op__imm_data__imm_ok$5$next
-      update \mul_op__rc__rc$6 \mul_op__rc__rc$6$next
-      update \mul_op__rc__rc_ok$7 \mul_op__rc__rc_ok$7$next
-      update \mul_op__oe__oe$8 \mul_op__oe__oe$8$next
-      update \mul_op__oe__oe_ok$9 \mul_op__oe__oe_ok$9$next
-      update \mul_op__invert_a$10 \mul_op__invert_a$10$next
-      update \mul_op__zero_a$11 \mul_op__zero_a$11$next
-      update \mul_op__invert_out$12 \mul_op__invert_out$12$next
-      update \mul_op__write_cr0$13 \mul_op__write_cr0$13$next
-      update \mul_op__is_32bit$14 \mul_op__is_32bit$14$next
-      update \mul_op__is_signed$15 \mul_op__is_signed$15$next
-      update \mul_op__insn$16 \mul_op__insn$16$next
-  end
-  process $group_88
-    assign \o$17$next \o$17
-    assign \o_ok$next \o_ok
-    attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
-    switch { \n_i_rdy_data \p_valid_i_p_ready_o }
-      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
-      case 2'-1
-        assign { \o_ok$next \o$17$next } { \o_ok$85 \o$84 }
-      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
-      case 2'1-
-        assign { \o_ok$next \o$17$next } { \o_ok$85 \o$84 }
-    end
-    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
-      case 1'1
-        assign \o_ok$next 1'0
-    end
-    sync init
-      update \o$17 64'0000000000000000000000000000000000000000000000000000000000000000
-      update \o_ok 1'0
-    sync posedge \clk
-      update \o$17 \o$17$next
-      update \o_ok \o_ok$next
-  end
-  process $group_90
-    assign \cr_a$next \cr_a
-    assign \cr_a_ok$next \cr_a_ok
-    attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
-    switch { \n_i_rdy_data \p_valid_i_p_ready_o }
-      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
-      case 2'-1
-        assign { \cr_a_ok$next \cr_a$next } { \cr_a_ok$87 \cr_a$86 }
-      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
-      case 2'1-
-        assign { \cr_a_ok$next \cr_a$next } { \cr_a_ok$87 \cr_a$86 }
-    end
-    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
-      case 1'1
-        assign \cr_a_ok$next 1'0
-    end
-    sync init
-      update \cr_a 4'0000
-      update \cr_a_ok 1'0
-    sync posedge \clk
-      update \cr_a \cr_a$next
-      update \cr_a_ok \cr_a_ok$next
-  end
-  process $group_92
-    assign \xer_ov$next \xer_ov
-    assign \xer_ov_ok$next \xer_ov_ok
-    attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
-    switch { \n_i_rdy_data \p_valid_i_p_ready_o }
-      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
-      case 2'-1
-        assign { \xer_ov_ok$next \xer_ov$next } { \xer_ov_ok$89 \xer_ov$88 }
-      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
-      case 2'1-
-        assign { \xer_ov_ok$next \xer_ov$next } { \xer_ov_ok$89 \xer_ov$88 }
-    end
-    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
-      case 1'1
-        assign \xer_ov_ok$next 1'0
-    end
-    sync init
-      update \xer_ov 2'00
-      update \xer_ov_ok 1'0
-    sync posedge \clk
-      update \xer_ov \xer_ov$next
-      update \xer_ov_ok \xer_ov_ok$next
-  end
-  process $group_94
-    assign \xer_so$18$next \xer_so$18
-    assign \xer_so_ok$next \xer_so_ok
-    attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
-    switch { \n_i_rdy_data \p_valid_i_p_ready_o }
-      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
-      case 2'-1
-        assign { \xer_so_ok$next \xer_so$18$next } { \xer_so_ok$91 \xer_so$90 }
-      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
-      case 2'1-
-        assign { \xer_so_ok$next \xer_so$18$next } { \xer_so_ok$91 \xer_so$90 }
-    end
-    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
-      case 1'1
-        assign \xer_so_ok$next 1'0
-    end
-    sync init
-      update \xer_so$18 1'0
-      update \xer_so_ok 1'0
-    sync posedge \clk
-      update \xer_so$18 \xer_so$18$next
-      update \xer_so_ok \xer_so_ok$next
-  end
-  process $group_96
-    assign \n_valid_o 1'0
-    assign \n_valid_o \r_busy
-    sync init
-  end
-  process $group_97
-    assign \p_ready_o 1'0
-    assign \p_ready_o \n_i_rdy_data
-    sync init
+  wire width 1 \pipe_middle_0_logical_op__is_32bit$39
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \pipe_middle_0_logical_op__is_signed$40
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 4 \pipe_middle_0_logical_op__data_len$41
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \pipe_middle_0_logical_op__insn$42
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
+  wire width 64 \pipe_middle_0_ra$43
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
+  wire width 64 \pipe_middle_0_rb$44
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
+  wire width 1 \pipe_middle_0_xer_so$45
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160"
+  wire width 1 \pipe_middle_0_divisor_neg$46
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161"
+  wire width 1 \pipe_middle_0_dividend_neg$47
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167"
+  wire width 1 \pipe_middle_0_dive_abs_ov32$48
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168"
+  wire width 1 \pipe_middle_0_dive_abs_ov64$49
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162"
+  wire width 1 \pipe_middle_0_div_by_zero$50
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40"
+  wire width 64 \pipe_middle_0_quotient_root
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:41"
+  wire width 192 \pipe_middle_0_remainder
+  cell \pipe_middle_0 \pipe_middle_0
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
+    connect \p_valid_i \pipe_middle_0_p_valid_i
+    connect \p_ready_o \pipe_middle_0_p_ready_o
+    connect \muxid \pipe_middle_0_muxid
+    connect \logical_op__insn_type \pipe_middle_0_logical_op__insn_type
+    connect \logical_op__fn_unit \pipe_middle_0_logical_op__fn_unit
+    connect \logical_op__imm_data__imm \pipe_middle_0_logical_op__imm_data__imm
+    connect \logical_op__imm_data__imm_ok \pipe_middle_0_logical_op__imm_data__imm_ok
+    connect \logical_op__rc__rc \pipe_middle_0_logical_op__rc__rc
+    connect \logical_op__rc__rc_ok \pipe_middle_0_logical_op__rc__rc_ok
+    connect \logical_op__oe__oe \pipe_middle_0_logical_op__oe__oe
+    connect \logical_op__oe__oe_ok \pipe_middle_0_logical_op__oe__oe_ok
+    connect \logical_op__invert_a \pipe_middle_0_logical_op__invert_a
+    connect \logical_op__zero_a \pipe_middle_0_logical_op__zero_a
+    connect \logical_op__input_carry \pipe_middle_0_logical_op__input_carry
+    connect \logical_op__invert_out \pipe_middle_0_logical_op__invert_out
+    connect \logical_op__write_cr0 \pipe_middle_0_logical_op__write_cr0
+    connect \logical_op__output_carry \pipe_middle_0_logical_op__output_carry
+    connect \logical_op__is_32bit \pipe_middle_0_logical_op__is_32bit
+    connect \logical_op__is_signed \pipe_middle_0_logical_op__is_signed
+    connect \logical_op__data_len \pipe_middle_0_logical_op__data_len
+    connect \logical_op__insn \pipe_middle_0_logical_op__insn
+    connect \ra \pipe_middle_0_ra
+    connect \rb \pipe_middle_0_rb
+    connect \xer_so \pipe_middle_0_xer_so
+    connect \divisor_neg \pipe_middle_0_divisor_neg
+    connect \dividend_neg \pipe_middle_0_dividend_neg
+    connect \dive_abs_ov32 \pipe_middle_0_dive_abs_ov32
+    connect \dive_abs_ov64 \pipe_middle_0_dive_abs_ov64
+    connect \div_by_zero \pipe_middle_0_div_by_zero
+    connect \dividend \pipe_middle_0_dividend
+    connect \divisor_radicand \pipe_middle_0_divisor_radicand
+    connect \operation \pipe_middle_0_operation
+    connect \n_valid_o \pipe_middle_0_n_valid_o
+    connect \n_ready_i \pipe_middle_0_n_ready_i
+    connect \muxid$1 \pipe_middle_0_muxid$24
+    connect \logical_op__insn_type$2 \pipe_middle_0_logical_op__insn_type$25
+    connect \logical_op__fn_unit$3 \pipe_middle_0_logical_op__fn_unit$26
+    connect \logical_op__imm_data__imm$4 \pipe_middle_0_logical_op__imm_data__imm$27
+    connect \logical_op__imm_data__imm_ok$5 \pipe_middle_0_logical_op__imm_data__imm_ok$28
+    connect \logical_op__rc__rc$6 \pipe_middle_0_logical_op__rc__rc$29
+    connect \logical_op__rc__rc_ok$7 \pipe_middle_0_logical_op__rc__rc_ok$30
+    connect \logical_op__oe__oe$8 \pipe_middle_0_logical_op__oe__oe$31
+    connect \logical_op__oe__oe_ok$9 \pipe_middle_0_logical_op__oe__oe_ok$32
+    connect \logical_op__invert_a$10 \pipe_middle_0_logical_op__invert_a$33
+    connect \logical_op__zero_a$11 \pipe_middle_0_logical_op__zero_a$34
+    connect \logical_op__input_carry$12 \pipe_middle_0_logical_op__input_carry$35
+    connect \logical_op__invert_out$13 \pipe_middle_0_logical_op__invert_out$36
+    connect \logical_op__write_cr0$14 \pipe_middle_0_logical_op__write_cr0$37
+    connect \logical_op__output_carry$15 \pipe_middle_0_logical_op__output_carry$38
+    connect \logical_op__is_32bit$16 \pipe_middle_0_logical_op__is_32bit$39
+    connect \logical_op__is_signed$17 \pipe_middle_0_logical_op__is_signed$40
+    connect \logical_op__data_len$18 \pipe_middle_0_logical_op__data_len$41
+    connect \logical_op__insn$19 \pipe_middle_0_logical_op__insn$42
+    connect \ra$20 \pipe_middle_0_ra$43
+    connect \rb$21 \pipe_middle_0_rb$44
+    connect \xer_so$22 \pipe_middle_0_xer_so$45
+    connect \divisor_neg$23 \pipe_middle_0_divisor_neg$46
+    connect \dividend_neg$24 \pipe_middle_0_dividend_neg$47
+    connect \dive_abs_ov32$25 \pipe_middle_0_dive_abs_ov32$48
+    connect \dive_abs_ov64$26 \pipe_middle_0_dive_abs_ov64$49
+    connect \div_by_zero$27 \pipe_middle_0_div_by_zero$50
+    connect \quotient_root \pipe_middle_0_quotient_root
+    connect \remainder \pipe_middle_0_remainder
   end
-  connect \cr_a$60 4'0000
-  connect \cr_a_ok$61 1'0
-  connect \xer_so_ok$64 1'0
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0"
-module \alu_mul0
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 2 \o_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 3 \cr_a_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 4 \xer_ov_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 5 \xer_so_ok
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
-  wire width 1 output 6 \n_valid_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
-  wire width 1 input 7 \n_ready_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 64 output 8 \o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 4 output 9 \cr_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 2 output 10 \xer_ov
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 11 \xer_so
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153"
+  wire width 1 \pipe_end_p_valid_i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154"
+  wire width 1 \pipe_end_p_ready_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
+  wire width 2 \pipe_end_muxid
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
   attribute \enum_value_0000001 "OP_NOP"
@@ -95350,7 +96651,7 @@ module \alu_mul0
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 7 input 12 \mul_op__insn_type
+  wire width 7 \pipe_end_logical_op__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -95364,57 +96665,69 @@ module \alu_mul0
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 11 input 13 \mul_op__fn_unit
+  wire width 11 \pipe_end_logical_op__fn_unit
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 64 input 14 \mul_op__imm_data__imm
+  wire width 64 \pipe_end_logical_op__imm_data__imm
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 15 \mul_op__imm_data__imm_ok
+  wire width 1 \pipe_end_logical_op__imm_data__imm_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 16 \mul_op__rc__rc
+  wire width 1 \pipe_end_logical_op__rc__rc
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 17 \mul_op__rc__rc_ok
+  wire width 1 \pipe_end_logical_op__rc__rc_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 18 \mul_op__oe__oe
+  wire width 1 \pipe_end_logical_op__oe__oe
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 19 \mul_op__oe__oe_ok
+  wire width 1 \pipe_end_logical_op__oe__oe_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 20 \mul_op__invert_a
+  wire width 1 \pipe_end_logical_op__invert_a
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 21 \mul_op__zero_a
+  wire width 1 \pipe_end_logical_op__zero_a
+  attribute \enum_base_type "CryIn"
+  attribute \enum_value_00 "ZERO"
+  attribute \enum_value_01 "ONE"
+  attribute \enum_value_10 "CA"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 22 \mul_op__invert_out
+  wire width 2 \pipe_end_logical_op__input_carry
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 23 \mul_op__write_cr0
+  wire width 1 \pipe_end_logical_op__invert_out
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 24 \mul_op__is_32bit
+  wire width 1 \pipe_end_logical_op__write_cr0
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 25 \mul_op__is_signed
+  wire width 1 \pipe_end_logical_op__output_carry
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 32 input 26 \mul_op__insn
+  wire width 1 \pipe_end_logical_op__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \pipe_end_logical_op__is_signed
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 4 \pipe_end_logical_op__data_len
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \pipe_end_logical_op__insn
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
-  wire width 64 input 27 \ra
+  wire width 64 \pipe_end_ra
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
-  wire width 64 input 28 \rb
+  wire width 64 \pipe_end_rb
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
-  wire width 1 input 29 \xer_so$1
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153"
-  wire width 1 input 30 \p_valid_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154"
-  wire width 1 output 31 \p_ready_o
-  cell \p$70 \p
-    connect \p_valid_i \p_valid_i
-    connect \p_ready_o \p_ready_o
-  end
-  cell \n$71 \n
-    connect \n_valid_o \n_valid_o
-    connect \n_ready_i \n_ready_i
-  end
+  wire width 1 \pipe_end_xer_so
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160"
+  wire width 1 \pipe_end_divisor_neg
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161"
+  wire width 1 \pipe_end_dividend_neg
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167"
+  wire width 1 \pipe_end_dive_abs_ov32
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168"
+  wire width 1 \pipe_end_dive_abs_ov64
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162"
+  wire width 1 \pipe_end_div_by_zero
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40"
+  wire width 64 \pipe_end_quotient_root
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:41"
+  wire width 192 \pipe_end_remainder
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
-  wire width 1 \mul_pipe1_n_valid_o
+  wire width 1 \pipe_end_n_valid_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
-  wire width 1 \mul_pipe1_n_ready_i
+  wire width 1 \pipe_end_n_ready_i
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
-  wire width 2 \mul_pipe1_muxid
+  wire width 2 \pipe_end_muxid$51
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
   attribute \enum_value_0000001 "OP_NOP"
@@ -95489,7 +96802,7 @@ module \alu_mul0
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 7 \mul_pipe1_mul_op__insn_type
+  wire width 7 \pipe_end_logical_op__insn_type$52
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -95503,224 +96816,373 @@ module \alu_mul0
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 11 \mul_pipe1_mul_op__fn_unit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 64 \mul_pipe1_mul_op__imm_data__imm
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_pipe1_mul_op__imm_data__imm_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_pipe1_mul_op__rc__rc
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_pipe1_mul_op__rc__rc_ok
+  wire width 11 \pipe_end_logical_op__fn_unit$53
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_pipe1_mul_op__oe__oe
+  wire width 64 \pipe_end_logical_op__imm_data__imm$54
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_pipe1_mul_op__oe__oe_ok
+  wire width 1 \pipe_end_logical_op__imm_data__imm_ok$55
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_pipe1_mul_op__invert_a
+  wire width 1 \pipe_end_logical_op__rc__rc$56
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_pipe1_mul_op__zero_a
+  wire width 1 \pipe_end_logical_op__rc__rc_ok$57
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_pipe1_mul_op__invert_out
+  wire width 1 \pipe_end_logical_op__oe__oe$58
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_pipe1_mul_op__write_cr0
+  wire width 1 \pipe_end_logical_op__oe__oe_ok$59
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_pipe1_mul_op__is_32bit
+  wire width 1 \pipe_end_logical_op__invert_a$60
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_pipe1_mul_op__is_signed
+  wire width 1 \pipe_end_logical_op__zero_a$61
+  attribute \enum_base_type "CryIn"
+  attribute \enum_value_00 "ZERO"
+  attribute \enum_value_01 "ONE"
+  attribute \enum_value_10 "CA"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 32 \mul_pipe1_mul_op__insn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
-  wire width 64 \mul_pipe1_ra
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
-  wire width 64 \mul_pipe1_rb
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
-  wire width 1 \mul_pipe1_xer_so
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11"
-  wire width 1 \mul_pipe1_neg_res
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12"
-  wire width 1 \mul_pipe1_neg_res32
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153"
-  wire width 1 \mul_pipe1_p_valid_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154"
-  wire width 1 \mul_pipe1_p_ready_o
+  wire width 2 \pipe_end_logical_op__input_carry$62
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \pipe_end_logical_op__invert_out$63
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \pipe_end_logical_op__write_cr0$64
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \pipe_end_logical_op__output_carry$65
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \pipe_end_logical_op__is_32bit$66
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \pipe_end_logical_op__is_signed$67
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 4 \pipe_end_logical_op__data_len$68
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \pipe_end_logical_op__insn$69
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 64 \pipe_end_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 \pipe_end_o_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 4 \pipe_end_cr_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 \pipe_end_cr_a_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 2 \pipe_end_xer_ov
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 \pipe_end_xer_ov_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 \pipe_end_xer_so$70
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 \pipe_end_xer_so_ok
+  cell \pipe_end \pipe_end
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
+    connect \p_valid_i \pipe_end_p_valid_i
+    connect \p_ready_o \pipe_end_p_ready_o
+    connect \muxid \pipe_end_muxid
+    connect \logical_op__insn_type \pipe_end_logical_op__insn_type
+    connect \logical_op__fn_unit \pipe_end_logical_op__fn_unit
+    connect \logical_op__imm_data__imm \pipe_end_logical_op__imm_data__imm
+    connect \logical_op__imm_data__imm_ok \pipe_end_logical_op__imm_data__imm_ok
+    connect \logical_op__rc__rc \pipe_end_logical_op__rc__rc
+    connect \logical_op__rc__rc_ok \pipe_end_logical_op__rc__rc_ok
+    connect \logical_op__oe__oe \pipe_end_logical_op__oe__oe
+    connect \logical_op__oe__oe_ok \pipe_end_logical_op__oe__oe_ok
+    connect \logical_op__invert_a \pipe_end_logical_op__invert_a
+    connect \logical_op__zero_a \pipe_end_logical_op__zero_a
+    connect \logical_op__input_carry \pipe_end_logical_op__input_carry
+    connect \logical_op__invert_out \pipe_end_logical_op__invert_out
+    connect \logical_op__write_cr0 \pipe_end_logical_op__write_cr0
+    connect \logical_op__output_carry \pipe_end_logical_op__output_carry
+    connect \logical_op__is_32bit \pipe_end_logical_op__is_32bit
+    connect \logical_op__is_signed \pipe_end_logical_op__is_signed
+    connect \logical_op__data_len \pipe_end_logical_op__data_len
+    connect \logical_op__insn \pipe_end_logical_op__insn
+    connect \ra \pipe_end_ra
+    connect \rb \pipe_end_rb
+    connect \xer_so \pipe_end_xer_so
+    connect \divisor_neg \pipe_end_divisor_neg
+    connect \dividend_neg \pipe_end_dividend_neg
+    connect \dive_abs_ov32 \pipe_end_dive_abs_ov32
+    connect \dive_abs_ov64 \pipe_end_dive_abs_ov64
+    connect \div_by_zero \pipe_end_div_by_zero
+    connect \quotient_root \pipe_end_quotient_root
+    connect \remainder \pipe_end_remainder
+    connect \n_valid_o \pipe_end_n_valid_o
+    connect \n_ready_i \pipe_end_n_ready_i
+    connect \muxid$1 \pipe_end_muxid$51
+    connect \logical_op__insn_type$2 \pipe_end_logical_op__insn_type$52
+    connect \logical_op__fn_unit$3 \pipe_end_logical_op__fn_unit$53
+    connect \logical_op__imm_data__imm$4 \pipe_end_logical_op__imm_data__imm$54
+    connect \logical_op__imm_data__imm_ok$5 \pipe_end_logical_op__imm_data__imm_ok$55
+    connect \logical_op__rc__rc$6 \pipe_end_logical_op__rc__rc$56
+    connect \logical_op__rc__rc_ok$7 \pipe_end_logical_op__rc__rc_ok$57
+    connect \logical_op__oe__oe$8 \pipe_end_logical_op__oe__oe$58
+    connect \logical_op__oe__oe_ok$9 \pipe_end_logical_op__oe__oe_ok$59
+    connect \logical_op__invert_a$10 \pipe_end_logical_op__invert_a$60
+    connect \logical_op__zero_a$11 \pipe_end_logical_op__zero_a$61
+    connect \logical_op__input_carry$12 \pipe_end_logical_op__input_carry$62
+    connect \logical_op__invert_out$13 \pipe_end_logical_op__invert_out$63
+    connect \logical_op__write_cr0$14 \pipe_end_logical_op__write_cr0$64
+    connect \logical_op__output_carry$15 \pipe_end_logical_op__output_carry$65
+    connect \logical_op__is_32bit$16 \pipe_end_logical_op__is_32bit$66
+    connect \logical_op__is_signed$17 \pipe_end_logical_op__is_signed$67
+    connect \logical_op__data_len$18 \pipe_end_logical_op__data_len$68
+    connect \logical_op__insn$19 \pipe_end_logical_op__insn$69
+    connect \o \pipe_end_o
+    connect \o_ok \pipe_end_o_ok
+    connect \cr_a \pipe_end_cr_a
+    connect \cr_a_ok \pipe_end_cr_a_ok
+    connect \xer_ov \pipe_end_xer_ov
+    connect \xer_ov_ok \pipe_end_xer_ov_ok
+    connect \xer_so$20 \pipe_end_xer_so$70
+    connect \xer_so_ok \pipe_end_xer_so_ok
+  end
+  process $group_0
+    assign \pipe_middle_0_p_valid_i 1'0
+    assign \pipe_middle_0_p_valid_i \pipe_start_n_valid_o
+    sync init
+  end
+  process $group_1
+    assign \pipe_start_n_ready_i 1'0
+    assign \pipe_start_n_ready_i \pipe_middle_0_p_ready_o
+    sync init
+  end
+  process $group_2
+    assign \pipe_middle_0_muxid 2'00
+    assign \pipe_middle_0_muxid \pipe_start_muxid
+    sync init
+  end
+  process $group_3
+    assign \pipe_middle_0_logical_op__insn_type 7'0000000
+    assign \pipe_middle_0_logical_op__fn_unit 11'00000000000
+    assign \pipe_middle_0_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \pipe_middle_0_logical_op__imm_data__imm_ok 1'0
+    assign \pipe_middle_0_logical_op__rc__rc 1'0
+    assign \pipe_middle_0_logical_op__rc__rc_ok 1'0
+    assign \pipe_middle_0_logical_op__oe__oe 1'0
+    assign \pipe_middle_0_logical_op__oe__oe_ok 1'0
+    assign \pipe_middle_0_logical_op__invert_a 1'0
+    assign \pipe_middle_0_logical_op__zero_a 1'0
+    assign \pipe_middle_0_logical_op__input_carry 2'00
+    assign \pipe_middle_0_logical_op__invert_out 1'0
+    assign \pipe_middle_0_logical_op__write_cr0 1'0
+    assign \pipe_middle_0_logical_op__output_carry 1'0
+    assign \pipe_middle_0_logical_op__is_32bit 1'0
+    assign \pipe_middle_0_logical_op__is_signed 1'0
+    assign \pipe_middle_0_logical_op__data_len 4'0000
+    assign \pipe_middle_0_logical_op__insn 32'00000000000000000000000000000000
+    assign { \pipe_middle_0_logical_op__insn \pipe_middle_0_logical_op__data_len \pipe_middle_0_logical_op__is_signed \pipe_middle_0_logical_op__is_32bit \pipe_middle_0_logical_op__output_carry \pipe_middle_0_logical_op__write_cr0 \pipe_middle_0_logical_op__invert_out \pipe_middle_0_logical_op__input_carry \pipe_middle_0_logical_op__zero_a \pipe_middle_0_logical_op__invert_a { \pipe_middle_0_logical_op__oe__oe_ok \pipe_middle_0_logical_op__oe__oe } { \pipe_middle_0_logical_op__rc__rc_ok \pipe_middle_0_logical_op__rc__rc } { \pipe_middle_0_logical_op__imm_data__imm_ok \pipe_middle_0_logical_op__imm_data__imm } \pipe_middle_0_logical_op__fn_unit \pipe_middle_0_logical_op__insn_type } { \pipe_start_logical_op__insn \pipe_start_logical_op__data_len \pipe_start_logical_op__is_signed \pipe_start_logical_op__is_32bit \pipe_start_logical_op__output_carry \pipe_start_logical_op__write_cr0 \pipe_start_logical_op__invert_out \pipe_start_logical_op__input_carry \pipe_start_logical_op__zero_a \pipe_start_logical_op__invert_a { \pipe_start_logical_op__oe__oe_ok \pipe_start_logical_op__oe__oe } { \pipe_start_logical_op__rc__rc_ok \pipe_start_logical_op__rc__rc } { \pipe_start_logical_op__imm_data__imm_ok \pipe_start_logical_op__imm_data__imm } \pipe_start_logical_op__fn_unit \pipe_start_logical_op__insn_type }
+    sync init
+  end
+  process $group_21
+    assign \pipe_middle_0_ra 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \pipe_middle_0_ra \pipe_start_ra
+    sync init
+  end
+  process $group_22
+    assign \pipe_middle_0_rb 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \pipe_middle_0_rb \pipe_start_rb
+    sync init
+  end
+  process $group_23
+    assign \pipe_middle_0_xer_so 1'0
+    assign \pipe_middle_0_xer_so \pipe_start_xer_so
+    sync init
+  end
+  process $group_24
+    assign \pipe_middle_0_divisor_neg 1'0
+    assign \pipe_middle_0_divisor_neg \pipe_start_divisor_neg
+    sync init
+  end
+  process $group_25
+    assign \pipe_middle_0_dividend_neg 1'0
+    assign \pipe_middle_0_dividend_neg \pipe_start_dividend_neg
+    sync init
+  end
+  process $group_26
+    assign \pipe_middle_0_dive_abs_ov32 1'0
+    assign \pipe_middle_0_dive_abs_ov32 \pipe_start_dive_abs_ov32
+    sync init
+  end
+  process $group_27
+    assign \pipe_middle_0_dive_abs_ov64 1'0
+    assign \pipe_middle_0_dive_abs_ov64 \pipe_start_dive_abs_ov64
+    sync init
+  end
+  process $group_28
+    assign \pipe_middle_0_div_by_zero 1'0
+    assign \pipe_middle_0_div_by_zero \pipe_start_div_by_zero
+    sync init
+  end
+  process $group_29
+    assign \pipe_middle_0_dividend 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
+    assign \pipe_middle_0_dividend \pipe_start_dividend
+    sync init
+  end
+  process $group_30
+    assign \pipe_middle_0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \pipe_middle_0_divisor_radicand \pipe_start_divisor_radicand
+    sync init
+  end
+  process $group_31
+    assign \pipe_middle_0_operation 2'00
+    assign \pipe_middle_0_operation \pipe_start_operation
+    sync init
+  end
+  process $group_32
+    assign \pipe_end_p_valid_i 1'0
+    assign \pipe_end_p_valid_i \pipe_middle_0_n_valid_o
+    sync init
+  end
+  process $group_33
+    assign \pipe_middle_0_n_ready_i 1'0
+    assign \pipe_middle_0_n_ready_i \pipe_end_p_ready_o
+    sync init
+  end
+  process $group_34
+    assign \pipe_end_muxid 2'00
+    assign \pipe_end_muxid \pipe_middle_0_muxid$24
+    sync init
+  end
+  process $group_35
+    assign \pipe_end_logical_op__insn_type 7'0000000
+    assign \pipe_end_logical_op__fn_unit 11'00000000000
+    assign \pipe_end_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \pipe_end_logical_op__imm_data__imm_ok 1'0
+    assign \pipe_end_logical_op__rc__rc 1'0
+    assign \pipe_end_logical_op__rc__rc_ok 1'0
+    assign \pipe_end_logical_op__oe__oe 1'0
+    assign \pipe_end_logical_op__oe__oe_ok 1'0
+    assign \pipe_end_logical_op__invert_a 1'0
+    assign \pipe_end_logical_op__zero_a 1'0
+    assign \pipe_end_logical_op__input_carry 2'00
+    assign \pipe_end_logical_op__invert_out 1'0
+    assign \pipe_end_logical_op__write_cr0 1'0
+    assign \pipe_end_logical_op__output_carry 1'0
+    assign \pipe_end_logical_op__is_32bit 1'0
+    assign \pipe_end_logical_op__is_signed 1'0
+    assign \pipe_end_logical_op__data_len 4'0000
+    assign \pipe_end_logical_op__insn 32'00000000000000000000000000000000
+    assign { \pipe_end_logical_op__insn \pipe_end_logical_op__data_len \pipe_end_logical_op__is_signed \pipe_end_logical_op__is_32bit \pipe_end_logical_op__output_carry \pipe_end_logical_op__write_cr0 \pipe_end_logical_op__invert_out \pipe_end_logical_op__input_carry \pipe_end_logical_op__zero_a \pipe_end_logical_op__invert_a { \pipe_end_logical_op__oe__oe_ok \pipe_end_logical_op__oe__oe } { \pipe_end_logical_op__rc__rc_ok \pipe_end_logical_op__rc__rc } { \pipe_end_logical_op__imm_data__imm_ok \pipe_end_logical_op__imm_data__imm } \pipe_end_logical_op__fn_unit \pipe_end_logical_op__insn_type } { \pipe_middle_0_logical_op__insn$42 \pipe_middle_0_logical_op__data_len$41 \pipe_middle_0_logical_op__is_signed$40 \pipe_middle_0_logical_op__is_32bit$39 \pipe_middle_0_logical_op__output_carry$38 \pipe_middle_0_logical_op__write_cr0$37 \pipe_middle_0_logical_op__invert_out$36 \pipe_middle_0_logical_op__input_carry$35 \pipe_middle_0_logical_op__zero_a$34 \pipe_middle_0_logical_op__invert_a$33 { \pipe_middle_0_logical_op__oe__oe_ok$32 \pipe_middle_0_logical_op__oe__oe$31 } { \pipe_middle_0_logical_op__rc__rc_ok$30 \pipe_middle_0_logical_op__rc__rc$29 } { \pipe_middle_0_logical_op__imm_data__imm_ok$28 \pipe_middle_0_logical_op__imm_data__imm$27 } \pipe_middle_0_logical_op__fn_unit$26 \pipe_middle_0_logical_op__insn_type$25 }
+    sync init
+  end
+  process $group_53
+    assign \pipe_end_ra 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \pipe_end_ra \pipe_middle_0_ra$43
+    sync init
+  end
+  process $group_54
+    assign \pipe_end_rb 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \pipe_end_rb \pipe_middle_0_rb$44
+    sync init
+  end
+  process $group_55
+    assign \pipe_end_xer_so 1'0
+    assign \pipe_end_xer_so \pipe_middle_0_xer_so$45
+    sync init
+  end
+  process $group_56
+    assign \pipe_end_divisor_neg 1'0
+    assign \pipe_end_divisor_neg \pipe_middle_0_divisor_neg$46
+    sync init
+  end
+  process $group_57
+    assign \pipe_end_dividend_neg 1'0
+    assign \pipe_end_dividend_neg \pipe_middle_0_dividend_neg$47
+    sync init
+  end
+  process $group_58
+    assign \pipe_end_dive_abs_ov32 1'0
+    assign \pipe_end_dive_abs_ov32 \pipe_middle_0_dive_abs_ov32$48
+    sync init
+  end
+  process $group_59
+    assign \pipe_end_dive_abs_ov64 1'0
+    assign \pipe_end_dive_abs_ov64 \pipe_middle_0_dive_abs_ov64$49
+    sync init
+  end
+  process $group_60
+    assign \pipe_end_div_by_zero 1'0
+    assign \pipe_end_div_by_zero \pipe_middle_0_div_by_zero$50
+    sync init
+  end
+  process $group_61
+    assign \pipe_end_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \pipe_end_quotient_root \pipe_middle_0_quotient_root
+    sync init
+  end
+  process $group_62
+    assign \pipe_end_remainder 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
+    assign \pipe_end_remainder \pipe_middle_0_remainder
+    sync init
+  end
+  process $group_63
+    assign \pipe_start_p_valid_i 1'0
+    assign \pipe_start_p_valid_i \p_valid_i
+    sync init
+  end
+  process $group_64
+    assign \p_ready_o 1'0
+    assign \p_ready_o \pipe_start_p_ready_o
+    sync init
+  end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
-  wire width 2 \mul_pipe1_muxid$2
-  attribute \enum_base_type "MicrOp"
-  attribute \enum_value_0000000 "OP_ILLEGAL"
-  attribute \enum_value_0000001 "OP_NOP"
-  attribute \enum_value_0000010 "OP_ADD"
-  attribute \enum_value_0000011 "OP_ADDPCIS"
-  attribute \enum_value_0000100 "OP_AND"
-  attribute \enum_value_0000101 "OP_ATTN"
-  attribute \enum_value_0000110 "OP_B"
-  attribute \enum_value_0000111 "OP_BC"
-  attribute \enum_value_0001000 "OP_BCREG"
-  attribute \enum_value_0001001 "OP_BPERM"
-  attribute \enum_value_0001010 "OP_CMP"
-  attribute \enum_value_0001011 "OP_CMPB"
-  attribute \enum_value_0001100 "OP_CMPEQB"
-  attribute \enum_value_0001101 "OP_CMPRB"
-  attribute \enum_value_0001110 "OP_CNTZ"
-  attribute \enum_value_0001111 "OP_CRAND"
-  attribute \enum_value_0010000 "OP_CRANDC"
-  attribute \enum_value_0010001 "OP_CREQV"
-  attribute \enum_value_0010010 "OP_CRNAND"
-  attribute \enum_value_0010011 "OP_CRNOR"
-  attribute \enum_value_0010100 "OP_CROR"
-  attribute \enum_value_0010101 "OP_CRORC"
-  attribute \enum_value_0010110 "OP_CRXOR"
-  attribute \enum_value_0010111 "OP_DARN"
-  attribute \enum_value_0011000 "OP_DCBF"
-  attribute \enum_value_0011001 "OP_DCBST"
-  attribute \enum_value_0011010 "OP_DCBT"
-  attribute \enum_value_0011011 "OP_DCBTST"
-  attribute \enum_value_0011100 "OP_DCBZ"
-  attribute \enum_value_0011101 "OP_DIV"
-  attribute \enum_value_0011110 "OP_DIVE"
-  attribute \enum_value_0011111 "OP_EXTS"
-  attribute \enum_value_0100000 "OP_EXTSWSLI"
-  attribute \enum_value_0100001 "OP_ICBI"
-  attribute \enum_value_0100010 "OP_ICBT"
-  attribute \enum_value_0100011 "OP_ISEL"
-  attribute \enum_value_0100100 "OP_ISYNC"
-  attribute \enum_value_0100101 "OP_LOAD"
-  attribute \enum_value_0100110 "OP_STORE"
-  attribute \enum_value_0100111 "OP_MADDHD"
-  attribute \enum_value_0101000 "OP_MADDHDU"
-  attribute \enum_value_0101001 "OP_MADDLD"
-  attribute \enum_value_0101010 "OP_MCRF"
-  attribute \enum_value_0101011 "OP_MCRXR"
-  attribute \enum_value_0101100 "OP_MCRXRX"
-  attribute \enum_value_0101101 "OP_MFCR"
-  attribute \enum_value_0101110 "OP_MFSPR"
-  attribute \enum_value_0101111 "OP_MOD"
-  attribute \enum_value_0110000 "OP_MTCRF"
-  attribute \enum_value_0110001 "OP_MTSPR"
-  attribute \enum_value_0110010 "OP_MUL_L64"
-  attribute \enum_value_0110011 "OP_MUL_H64"
-  attribute \enum_value_0110100 "OP_MUL_H32"
-  attribute \enum_value_0110101 "OP_OR"
-  attribute \enum_value_0110110 "OP_POPCNT"
-  attribute \enum_value_0110111 "OP_PRTY"
-  attribute \enum_value_0111000 "OP_RLC"
-  attribute \enum_value_0111001 "OP_RLCL"
-  attribute \enum_value_0111010 "OP_RLCR"
-  attribute \enum_value_0111011 "OP_SETB"
-  attribute \enum_value_0111100 "OP_SHL"
-  attribute \enum_value_0111101 "OP_SHR"
-  attribute \enum_value_0111110 "OP_SYNC"
-  attribute \enum_value_0111111 "OP_TRAP"
-  attribute \enum_value_1000011 "OP_XOR"
-  attribute \enum_value_1000100 "OP_SIM_CONFIG"
-  attribute \enum_value_1000101 "OP_CROP"
-  attribute \enum_value_1000110 "OP_RFID"
-  attribute \enum_value_1000111 "OP_MFMSR"
-  attribute \enum_value_1001000 "OP_MTMSRD"
-  attribute \enum_value_1001001 "OP_SC"
-  attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 7 \mul_pipe1_mul_op__insn_type$3
-  attribute \enum_base_type "Function"
-  attribute \enum_value_00000000000 "NONE"
-  attribute \enum_value_00000000010 "ALU"
-  attribute \enum_value_00000000100 "LDST"
-  attribute \enum_value_00000001000 "SHIFT_ROT"
-  attribute \enum_value_00000010000 "LOGICAL"
-  attribute \enum_value_00000100000 "BRANCH"
-  attribute \enum_value_00001000000 "CR"
-  attribute \enum_value_00010000000 "TRAP"
-  attribute \enum_value_00100000000 "MUL"
-  attribute \enum_value_01000000000 "DIV"
-  attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 11 \mul_pipe1_mul_op__fn_unit$4
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 64 \mul_pipe1_mul_op__imm_data__imm$5
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_pipe1_mul_op__imm_data__imm_ok$6
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_pipe1_mul_op__rc__rc$7
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_pipe1_mul_op__rc__rc_ok$8
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_pipe1_mul_op__oe__oe$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_pipe1_mul_op__oe__oe_ok$10
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_pipe1_mul_op__invert_a$11
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_pipe1_mul_op__zero_a$12
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_pipe1_mul_op__invert_out$13
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_pipe1_mul_op__write_cr0$14
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_pipe1_mul_op__is_32bit$15
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_pipe1_mul_op__is_signed$16
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 32 \mul_pipe1_mul_op__insn$17
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
-  wire width 64 \mul_pipe1_ra$18
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
-  wire width 64 \mul_pipe1_rb$19
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
-  wire width 1 \mul_pipe1_xer_so$20
-  cell \mul_pipe1 \mul_pipe1
-    connect \rst \rst
-    connect \clk \clk
-    connect \n_valid_o \mul_pipe1_n_valid_o
-    connect \n_ready_i \mul_pipe1_n_ready_i
-    connect \muxid \mul_pipe1_muxid
-    connect \mul_op__insn_type \mul_pipe1_mul_op__insn_type
-    connect \mul_op__fn_unit \mul_pipe1_mul_op__fn_unit
-    connect \mul_op__imm_data__imm \mul_pipe1_mul_op__imm_data__imm
-    connect \mul_op__imm_data__imm_ok \mul_pipe1_mul_op__imm_data__imm_ok
-    connect \mul_op__rc__rc \mul_pipe1_mul_op__rc__rc
-    connect \mul_op__rc__rc_ok \mul_pipe1_mul_op__rc__rc_ok
-    connect \mul_op__oe__oe \mul_pipe1_mul_op__oe__oe
-    connect \mul_op__oe__oe_ok \mul_pipe1_mul_op__oe__oe_ok
-    connect \mul_op__invert_a \mul_pipe1_mul_op__invert_a
-    connect \mul_op__zero_a \mul_pipe1_mul_op__zero_a
-    connect \mul_op__invert_out \mul_pipe1_mul_op__invert_out
-    connect \mul_op__write_cr0 \mul_pipe1_mul_op__write_cr0
-    connect \mul_op__is_32bit \mul_pipe1_mul_op__is_32bit
-    connect \mul_op__is_signed \mul_pipe1_mul_op__is_signed
-    connect \mul_op__insn \mul_pipe1_mul_op__insn
-    connect \ra \mul_pipe1_ra
-    connect \rb \mul_pipe1_rb
-    connect \xer_so \mul_pipe1_xer_so
-    connect \neg_res \mul_pipe1_neg_res
-    connect \neg_res32 \mul_pipe1_neg_res32
-    connect \p_valid_i \mul_pipe1_p_valid_i
-    connect \p_ready_o \mul_pipe1_p_ready_o
-    connect \muxid$1 \mul_pipe1_muxid$2
-    connect \mul_op__insn_type$2 \mul_pipe1_mul_op__insn_type$3
-    connect \mul_op__fn_unit$3 \mul_pipe1_mul_op__fn_unit$4
-    connect \mul_op__imm_data__imm$4 \mul_pipe1_mul_op__imm_data__imm$5
-    connect \mul_op__imm_data__imm_ok$5 \mul_pipe1_mul_op__imm_data__imm_ok$6
-    connect \mul_op__rc__rc$6 \mul_pipe1_mul_op__rc__rc$7
-    connect \mul_op__rc__rc_ok$7 \mul_pipe1_mul_op__rc__rc_ok$8
-    connect \mul_op__oe__oe$8 \mul_pipe1_mul_op__oe__oe$9
-    connect \mul_op__oe__oe_ok$9 \mul_pipe1_mul_op__oe__oe_ok$10
-    connect \mul_op__invert_a$10 \mul_pipe1_mul_op__invert_a$11
-    connect \mul_op__zero_a$11 \mul_pipe1_mul_op__zero_a$12
-    connect \mul_op__invert_out$12 \mul_pipe1_mul_op__invert_out$13
-    connect \mul_op__write_cr0$13 \mul_pipe1_mul_op__write_cr0$14
-    connect \mul_op__is_32bit$14 \mul_pipe1_mul_op__is_32bit$15
-    connect \mul_op__is_signed$15 \mul_pipe1_mul_op__is_signed$16
-    connect \mul_op__insn$16 \mul_pipe1_mul_op__insn$17
-    connect \ra$17 \mul_pipe1_ra$18
-    connect \rb$18 \mul_pipe1_rb$19
-    connect \xer_so$19 \mul_pipe1_xer_so$20
+  wire width 2 \muxid
+  process $group_65
+    assign \pipe_start_muxid$2 2'00
+    assign \pipe_start_muxid$2 \muxid
+    sync init
+  end
+  process $group_66
+    assign \pipe_start_logical_op__insn_type$3 7'0000000
+    assign \pipe_start_logical_op__fn_unit$4 11'00000000000
+    assign \pipe_start_logical_op__imm_data__imm$5 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \pipe_start_logical_op__imm_data__imm_ok$6 1'0
+    assign \pipe_start_logical_op__rc__rc$7 1'0
+    assign \pipe_start_logical_op__rc__rc_ok$8 1'0
+    assign \pipe_start_logical_op__oe__oe$9 1'0
+    assign \pipe_start_logical_op__oe__oe_ok$10 1'0
+    assign \pipe_start_logical_op__invert_a$11 1'0
+    assign \pipe_start_logical_op__zero_a$12 1'0
+    assign \pipe_start_logical_op__input_carry$13 2'00
+    assign \pipe_start_logical_op__invert_out$14 1'0
+    assign \pipe_start_logical_op__write_cr0$15 1'0
+    assign \pipe_start_logical_op__output_carry$16 1'0
+    assign \pipe_start_logical_op__is_32bit$17 1'0
+    assign \pipe_start_logical_op__is_signed$18 1'0
+    assign \pipe_start_logical_op__data_len$19 4'0000
+    assign \pipe_start_logical_op__insn$20 32'00000000000000000000000000000000
+    assign { \pipe_start_logical_op__insn$20 \pipe_start_logical_op__data_len$19 \pipe_start_logical_op__is_signed$18 \pipe_start_logical_op__is_32bit$17 \pipe_start_logical_op__output_carry$16 \pipe_start_logical_op__write_cr0$15 \pipe_start_logical_op__invert_out$14 \pipe_start_logical_op__input_carry$13 \pipe_start_logical_op__zero_a$12 \pipe_start_logical_op__invert_a$11 { \pipe_start_logical_op__oe__oe_ok$10 \pipe_start_logical_op__oe__oe$9 } { \pipe_start_logical_op__rc__rc_ok$8 \pipe_start_logical_op__rc__rc$7 } { \pipe_start_logical_op__imm_data__imm_ok$6 \pipe_start_logical_op__imm_data__imm$5 } \pipe_start_logical_op__fn_unit$4 \pipe_start_logical_op__insn_type$3 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_a { \logical_op__oe__oe_ok \logical_op__oe__oe } { \logical_op__rc__rc_ok \logical_op__rc__rc } { \logical_op__imm_data__imm_ok \logical_op__imm_data__imm } \logical_op__fn_unit \logical_op__insn_type }
+    sync init
+  end
+  process $group_84
+    assign \pipe_start_ra$21 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \pipe_start_ra$21 \ra
+    sync init
+  end
+  process $group_85
+    assign \pipe_start_rb$22 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \pipe_start_rb$22 \rb
+    sync init
+  end
+  process $group_86
+    assign \pipe_start_xer_so$23 1'0
+    assign \pipe_start_xer_so$23 \xer_so$1
+    sync init
+  end
+  process $group_87
+    assign \n_valid_o 1'0
+    assign \n_valid_o \pipe_end_n_valid_o
+    sync init
+  end
+  process $group_88
+    assign \pipe_end_n_ready_i 1'0
+    assign \pipe_end_n_ready_i \n_ready_i
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153"
-  wire width 1 \mul_pipe2_p_valid_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154"
-  wire width 1 \mul_pipe2_p_ready_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
-  wire width 2 \mul_pipe2_muxid
+  wire width 2 \muxid$71
+  process $group_89
+    assign \muxid$71 2'00
+    assign \muxid$71 \pipe_end_muxid$51
+    sync init
+  end
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
   attribute \enum_value_0000001 "OP_NOP"
@@ -95795,7 +97257,7 @@ module \alu_mul0
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 7 \mul_pipe2_mul_op__insn_type
+  wire width 7 \logical_op__insn_type$72
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -95809,985 +97271,196 @@ module \alu_mul0
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 11 \mul_pipe2_mul_op__fn_unit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 64 \mul_pipe2_mul_op__imm_data__imm
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_pipe2_mul_op__imm_data__imm_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_pipe2_mul_op__rc__rc
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_pipe2_mul_op__rc__rc_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_pipe2_mul_op__oe__oe
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_pipe2_mul_op__oe__oe_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_pipe2_mul_op__invert_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_pipe2_mul_op__zero_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_pipe2_mul_op__invert_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_pipe2_mul_op__write_cr0
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_pipe2_mul_op__is_32bit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_pipe2_mul_op__is_signed
+  wire width 11 \logical_op__fn_unit$73
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 32 \mul_pipe2_mul_op__insn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
-  wire width 64 \mul_pipe2_ra
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
-  wire width 64 \mul_pipe2_rb
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
-  wire width 1 \mul_pipe2_xer_so
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11"
-  wire width 1 \mul_pipe2_neg_res
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12"
-  wire width 1 \mul_pipe2_neg_res32
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
-  wire width 1 \mul_pipe2_n_valid_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
-  wire width 1 \mul_pipe2_n_ready_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
-  wire width 2 \mul_pipe2_muxid$21
-  attribute \enum_base_type "MicrOp"
-  attribute \enum_value_0000000 "OP_ILLEGAL"
-  attribute \enum_value_0000001 "OP_NOP"
-  attribute \enum_value_0000010 "OP_ADD"
-  attribute \enum_value_0000011 "OP_ADDPCIS"
-  attribute \enum_value_0000100 "OP_AND"
-  attribute \enum_value_0000101 "OP_ATTN"
-  attribute \enum_value_0000110 "OP_B"
-  attribute \enum_value_0000111 "OP_BC"
-  attribute \enum_value_0001000 "OP_BCREG"
-  attribute \enum_value_0001001 "OP_BPERM"
-  attribute \enum_value_0001010 "OP_CMP"
-  attribute \enum_value_0001011 "OP_CMPB"
-  attribute \enum_value_0001100 "OP_CMPEQB"
-  attribute \enum_value_0001101 "OP_CMPRB"
-  attribute \enum_value_0001110 "OP_CNTZ"
-  attribute \enum_value_0001111 "OP_CRAND"
-  attribute \enum_value_0010000 "OP_CRANDC"
-  attribute \enum_value_0010001 "OP_CREQV"
-  attribute \enum_value_0010010 "OP_CRNAND"
-  attribute \enum_value_0010011 "OP_CRNOR"
-  attribute \enum_value_0010100 "OP_CROR"
-  attribute \enum_value_0010101 "OP_CRORC"
-  attribute \enum_value_0010110 "OP_CRXOR"
-  attribute \enum_value_0010111 "OP_DARN"
-  attribute \enum_value_0011000 "OP_DCBF"
-  attribute \enum_value_0011001 "OP_DCBST"
-  attribute \enum_value_0011010 "OP_DCBT"
-  attribute \enum_value_0011011 "OP_DCBTST"
-  attribute \enum_value_0011100 "OP_DCBZ"
-  attribute \enum_value_0011101 "OP_DIV"
-  attribute \enum_value_0011110 "OP_DIVE"
-  attribute \enum_value_0011111 "OP_EXTS"
-  attribute \enum_value_0100000 "OP_EXTSWSLI"
-  attribute \enum_value_0100001 "OP_ICBI"
-  attribute \enum_value_0100010 "OP_ICBT"
-  attribute \enum_value_0100011 "OP_ISEL"
-  attribute \enum_value_0100100 "OP_ISYNC"
-  attribute \enum_value_0100101 "OP_LOAD"
-  attribute \enum_value_0100110 "OP_STORE"
-  attribute \enum_value_0100111 "OP_MADDHD"
-  attribute \enum_value_0101000 "OP_MADDHDU"
-  attribute \enum_value_0101001 "OP_MADDLD"
-  attribute \enum_value_0101010 "OP_MCRF"
-  attribute \enum_value_0101011 "OP_MCRXR"
-  attribute \enum_value_0101100 "OP_MCRXRX"
-  attribute \enum_value_0101101 "OP_MFCR"
-  attribute \enum_value_0101110 "OP_MFSPR"
-  attribute \enum_value_0101111 "OP_MOD"
-  attribute \enum_value_0110000 "OP_MTCRF"
-  attribute \enum_value_0110001 "OP_MTSPR"
-  attribute \enum_value_0110010 "OP_MUL_L64"
-  attribute \enum_value_0110011 "OP_MUL_H64"
-  attribute \enum_value_0110100 "OP_MUL_H32"
-  attribute \enum_value_0110101 "OP_OR"
-  attribute \enum_value_0110110 "OP_POPCNT"
-  attribute \enum_value_0110111 "OP_PRTY"
-  attribute \enum_value_0111000 "OP_RLC"
-  attribute \enum_value_0111001 "OP_RLCL"
-  attribute \enum_value_0111010 "OP_RLCR"
-  attribute \enum_value_0111011 "OP_SETB"
-  attribute \enum_value_0111100 "OP_SHL"
-  attribute \enum_value_0111101 "OP_SHR"
-  attribute \enum_value_0111110 "OP_SYNC"
-  attribute \enum_value_0111111 "OP_TRAP"
-  attribute \enum_value_1000011 "OP_XOR"
-  attribute \enum_value_1000100 "OP_SIM_CONFIG"
-  attribute \enum_value_1000101 "OP_CROP"
-  attribute \enum_value_1000110 "OP_RFID"
-  attribute \enum_value_1000111 "OP_MFMSR"
-  attribute \enum_value_1001000 "OP_MTMSRD"
-  attribute \enum_value_1001001 "OP_SC"
-  attribute \enum_value_1001010 "OP_MTMSR"
+  wire width 64 \logical_op__imm_data__imm$74
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 7 \mul_pipe2_mul_op__insn_type$22
-  attribute \enum_base_type "Function"
-  attribute \enum_value_00000000000 "NONE"
-  attribute \enum_value_00000000010 "ALU"
-  attribute \enum_value_00000000100 "LDST"
-  attribute \enum_value_00000001000 "SHIFT_ROT"
-  attribute \enum_value_00000010000 "LOGICAL"
-  attribute \enum_value_00000100000 "BRANCH"
-  attribute \enum_value_00001000000 "CR"
-  attribute \enum_value_00010000000 "TRAP"
-  attribute \enum_value_00100000000 "MUL"
-  attribute \enum_value_01000000000 "DIV"
-  attribute \enum_value_10000000000 "SPR"
+  wire width 1 \logical_op__imm_data__imm_ok$75
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 11 \mul_pipe2_mul_op__fn_unit$23
+  wire width 1 \logical_op__rc__rc$76
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 64 \mul_pipe2_mul_op__imm_data__imm$24
+  wire width 1 \logical_op__rc__rc_ok$77
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_pipe2_mul_op__imm_data__imm_ok$25
+  wire width 1 \logical_op__oe__oe$78
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_pipe2_mul_op__rc__rc$26
+  wire width 1 \logical_op__oe__oe_ok$79
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_pipe2_mul_op__rc__rc_ok$27
+  wire width 1 \logical_op__invert_a$80
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_pipe2_mul_op__oe__oe$28
+  wire width 1 \logical_op__zero_a$81
+  attribute \enum_base_type "CryIn"
+  attribute \enum_value_00 "ZERO"
+  attribute \enum_value_01 "ONE"
+  attribute \enum_value_10 "CA"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_pipe2_mul_op__oe__oe_ok$29
+  wire width 2 \logical_op__input_carry$82
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_pipe2_mul_op__invert_a$30
+  wire width 1 \logical_op__invert_out$83
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_pipe2_mul_op__zero_a$31
+  wire width 1 \logical_op__write_cr0$84
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_pipe2_mul_op__invert_out$32
+  wire width 1 \logical_op__output_carry$85
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_pipe2_mul_op__write_cr0$33
+  wire width 1 \logical_op__is_32bit$86
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_pipe2_mul_op__is_32bit$34
+  wire width 1 \logical_op__is_signed$87
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_pipe2_mul_op__is_signed$35
+  wire width 4 \logical_op__data_len$88
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 32 \mul_pipe2_mul_op__insn$36
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
-  wire width 129 \mul_pipe2_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
-  wire width 1 \mul_pipe2_xer_so$37
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23"
-  wire width 1 \mul_pipe2_neg_res$38
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24"
-  wire width 1 \mul_pipe2_neg_res32$39
-  cell \mul_pipe2 \mul_pipe2
-    connect \rst \rst
-    connect \clk \clk
-    connect \p_valid_i \mul_pipe2_p_valid_i
-    connect \p_ready_o \mul_pipe2_p_ready_o
-    connect \muxid \mul_pipe2_muxid
-    connect \mul_op__insn_type \mul_pipe2_mul_op__insn_type
-    connect \mul_op__fn_unit \mul_pipe2_mul_op__fn_unit
-    connect \mul_op__imm_data__imm \mul_pipe2_mul_op__imm_data__imm
-    connect \mul_op__imm_data__imm_ok \mul_pipe2_mul_op__imm_data__imm_ok
-    connect \mul_op__rc__rc \mul_pipe2_mul_op__rc__rc
-    connect \mul_op__rc__rc_ok \mul_pipe2_mul_op__rc__rc_ok
-    connect \mul_op__oe__oe \mul_pipe2_mul_op__oe__oe
-    connect \mul_op__oe__oe_ok \mul_pipe2_mul_op__oe__oe_ok
-    connect \mul_op__invert_a \mul_pipe2_mul_op__invert_a
-    connect \mul_op__zero_a \mul_pipe2_mul_op__zero_a
-    connect \mul_op__invert_out \mul_pipe2_mul_op__invert_out
-    connect \mul_op__write_cr0 \mul_pipe2_mul_op__write_cr0
-    connect \mul_op__is_32bit \mul_pipe2_mul_op__is_32bit
-    connect \mul_op__is_signed \mul_pipe2_mul_op__is_signed
-    connect \mul_op__insn \mul_pipe2_mul_op__insn
-    connect \ra \mul_pipe2_ra
-    connect \rb \mul_pipe2_rb
-    connect \xer_so \mul_pipe2_xer_so
-    connect \neg_res \mul_pipe2_neg_res
-    connect \neg_res32 \mul_pipe2_neg_res32
-    connect \n_valid_o \mul_pipe2_n_valid_o
-    connect \n_ready_i \mul_pipe2_n_ready_i
-    connect \muxid$1 \mul_pipe2_muxid$21
-    connect \mul_op__insn_type$2 \mul_pipe2_mul_op__insn_type$22
-    connect \mul_op__fn_unit$3 \mul_pipe2_mul_op__fn_unit$23
-    connect \mul_op__imm_data__imm$4 \mul_pipe2_mul_op__imm_data__imm$24
-    connect \mul_op__imm_data__imm_ok$5 \mul_pipe2_mul_op__imm_data__imm_ok$25
-    connect \mul_op__rc__rc$6 \mul_pipe2_mul_op__rc__rc$26
-    connect \mul_op__rc__rc_ok$7 \mul_pipe2_mul_op__rc__rc_ok$27
-    connect \mul_op__oe__oe$8 \mul_pipe2_mul_op__oe__oe$28
-    connect \mul_op__oe__oe_ok$9 \mul_pipe2_mul_op__oe__oe_ok$29
-    connect \mul_op__invert_a$10 \mul_pipe2_mul_op__invert_a$30
-    connect \mul_op__zero_a$11 \mul_pipe2_mul_op__zero_a$31
-    connect \mul_op__invert_out$12 \mul_pipe2_mul_op__invert_out$32
-    connect \mul_op__write_cr0$13 \mul_pipe2_mul_op__write_cr0$33
-    connect \mul_op__is_32bit$14 \mul_pipe2_mul_op__is_32bit$34
-    connect \mul_op__is_signed$15 \mul_pipe2_mul_op__is_signed$35
-    connect \mul_op__insn$16 \mul_pipe2_mul_op__insn$36
-    connect \o \mul_pipe2_o
-    connect \xer_so$17 \mul_pipe2_xer_so$37
-    connect \neg_res$18 \mul_pipe2_neg_res$38
-    connect \neg_res32$19 \mul_pipe2_neg_res32$39
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153"
-  wire width 1 \mul_pipe3_p_valid_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154"
-  wire width 1 \mul_pipe3_p_ready_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
-  wire width 2 \mul_pipe3_muxid
-  attribute \enum_base_type "MicrOp"
-  attribute \enum_value_0000000 "OP_ILLEGAL"
-  attribute \enum_value_0000001 "OP_NOP"
-  attribute \enum_value_0000010 "OP_ADD"
-  attribute \enum_value_0000011 "OP_ADDPCIS"
-  attribute \enum_value_0000100 "OP_AND"
-  attribute \enum_value_0000101 "OP_ATTN"
-  attribute \enum_value_0000110 "OP_B"
-  attribute \enum_value_0000111 "OP_BC"
-  attribute \enum_value_0001000 "OP_BCREG"
-  attribute \enum_value_0001001 "OP_BPERM"
-  attribute \enum_value_0001010 "OP_CMP"
-  attribute \enum_value_0001011 "OP_CMPB"
-  attribute \enum_value_0001100 "OP_CMPEQB"
-  attribute \enum_value_0001101 "OP_CMPRB"
-  attribute \enum_value_0001110 "OP_CNTZ"
-  attribute \enum_value_0001111 "OP_CRAND"
-  attribute \enum_value_0010000 "OP_CRANDC"
-  attribute \enum_value_0010001 "OP_CREQV"
-  attribute \enum_value_0010010 "OP_CRNAND"
-  attribute \enum_value_0010011 "OP_CRNOR"
-  attribute \enum_value_0010100 "OP_CROR"
-  attribute \enum_value_0010101 "OP_CRORC"
-  attribute \enum_value_0010110 "OP_CRXOR"
-  attribute \enum_value_0010111 "OP_DARN"
-  attribute \enum_value_0011000 "OP_DCBF"
-  attribute \enum_value_0011001 "OP_DCBST"
-  attribute \enum_value_0011010 "OP_DCBT"
-  attribute \enum_value_0011011 "OP_DCBTST"
-  attribute \enum_value_0011100 "OP_DCBZ"
-  attribute \enum_value_0011101 "OP_DIV"
-  attribute \enum_value_0011110 "OP_DIVE"
-  attribute \enum_value_0011111 "OP_EXTS"
-  attribute \enum_value_0100000 "OP_EXTSWSLI"
-  attribute \enum_value_0100001 "OP_ICBI"
-  attribute \enum_value_0100010 "OP_ICBT"
-  attribute \enum_value_0100011 "OP_ISEL"
-  attribute \enum_value_0100100 "OP_ISYNC"
-  attribute \enum_value_0100101 "OP_LOAD"
-  attribute \enum_value_0100110 "OP_STORE"
-  attribute \enum_value_0100111 "OP_MADDHD"
-  attribute \enum_value_0101000 "OP_MADDHDU"
-  attribute \enum_value_0101001 "OP_MADDLD"
-  attribute \enum_value_0101010 "OP_MCRF"
-  attribute \enum_value_0101011 "OP_MCRXR"
-  attribute \enum_value_0101100 "OP_MCRXRX"
-  attribute \enum_value_0101101 "OP_MFCR"
-  attribute \enum_value_0101110 "OP_MFSPR"
-  attribute \enum_value_0101111 "OP_MOD"
-  attribute \enum_value_0110000 "OP_MTCRF"
-  attribute \enum_value_0110001 "OP_MTSPR"
-  attribute \enum_value_0110010 "OP_MUL_L64"
-  attribute \enum_value_0110011 "OP_MUL_H64"
-  attribute \enum_value_0110100 "OP_MUL_H32"
-  attribute \enum_value_0110101 "OP_OR"
-  attribute \enum_value_0110110 "OP_POPCNT"
-  attribute \enum_value_0110111 "OP_PRTY"
-  attribute \enum_value_0111000 "OP_RLC"
-  attribute \enum_value_0111001 "OP_RLCL"
-  attribute \enum_value_0111010 "OP_RLCR"
-  attribute \enum_value_0111011 "OP_SETB"
-  attribute \enum_value_0111100 "OP_SHL"
-  attribute \enum_value_0111101 "OP_SHR"
-  attribute \enum_value_0111110 "OP_SYNC"
-  attribute \enum_value_0111111 "OP_TRAP"
-  attribute \enum_value_1000011 "OP_XOR"
-  attribute \enum_value_1000100 "OP_SIM_CONFIG"
-  attribute \enum_value_1000101 "OP_CROP"
-  attribute \enum_value_1000110 "OP_RFID"
-  attribute \enum_value_1000111 "OP_MFMSR"
-  attribute \enum_value_1001000 "OP_MTMSRD"
-  attribute \enum_value_1001001 "OP_SC"
-  attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 7 \mul_pipe3_mul_op__insn_type
-  attribute \enum_base_type "Function"
-  attribute \enum_value_00000000000 "NONE"
-  attribute \enum_value_00000000010 "ALU"
-  attribute \enum_value_00000000100 "LDST"
-  attribute \enum_value_00000001000 "SHIFT_ROT"
-  attribute \enum_value_00000010000 "LOGICAL"
-  attribute \enum_value_00000100000 "BRANCH"
-  attribute \enum_value_00001000000 "CR"
-  attribute \enum_value_00010000000 "TRAP"
-  attribute \enum_value_00100000000 "MUL"
-  attribute \enum_value_01000000000 "DIV"
-  attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 11 \mul_pipe3_mul_op__fn_unit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 64 \mul_pipe3_mul_op__imm_data__imm
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_pipe3_mul_op__imm_data__imm_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_pipe3_mul_op__rc__rc
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_pipe3_mul_op__rc__rc_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_pipe3_mul_op__oe__oe
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_pipe3_mul_op__oe__oe_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_pipe3_mul_op__invert_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_pipe3_mul_op__zero_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_pipe3_mul_op__invert_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_pipe3_mul_op__write_cr0
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_pipe3_mul_op__is_32bit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_pipe3_mul_op__is_signed
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 32 \mul_pipe3_mul_op__insn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
-  wire width 129 \mul_pipe3_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
-  wire width 1 \mul_pipe3_xer_so
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23"
-  wire width 1 \mul_pipe3_neg_res
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24"
-  wire width 1 \mul_pipe3_neg_res32
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
-  wire width 1 \mul_pipe3_n_valid_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
-  wire width 1 \mul_pipe3_n_ready_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
-  wire width 2 \mul_pipe3_muxid$40
-  attribute \enum_base_type "MicrOp"
-  attribute \enum_value_0000000 "OP_ILLEGAL"
-  attribute \enum_value_0000001 "OP_NOP"
-  attribute \enum_value_0000010 "OP_ADD"
-  attribute \enum_value_0000011 "OP_ADDPCIS"
-  attribute \enum_value_0000100 "OP_AND"
-  attribute \enum_value_0000101 "OP_ATTN"
-  attribute \enum_value_0000110 "OP_B"
-  attribute \enum_value_0000111 "OP_BC"
-  attribute \enum_value_0001000 "OP_BCREG"
-  attribute \enum_value_0001001 "OP_BPERM"
-  attribute \enum_value_0001010 "OP_CMP"
-  attribute \enum_value_0001011 "OP_CMPB"
-  attribute \enum_value_0001100 "OP_CMPEQB"
-  attribute \enum_value_0001101 "OP_CMPRB"
-  attribute \enum_value_0001110 "OP_CNTZ"
-  attribute \enum_value_0001111 "OP_CRAND"
-  attribute \enum_value_0010000 "OP_CRANDC"
-  attribute \enum_value_0010001 "OP_CREQV"
-  attribute \enum_value_0010010 "OP_CRNAND"
-  attribute \enum_value_0010011 "OP_CRNOR"
-  attribute \enum_value_0010100 "OP_CROR"
-  attribute \enum_value_0010101 "OP_CRORC"
-  attribute \enum_value_0010110 "OP_CRXOR"
-  attribute \enum_value_0010111 "OP_DARN"
-  attribute \enum_value_0011000 "OP_DCBF"
-  attribute \enum_value_0011001 "OP_DCBST"
-  attribute \enum_value_0011010 "OP_DCBT"
-  attribute \enum_value_0011011 "OP_DCBTST"
-  attribute \enum_value_0011100 "OP_DCBZ"
-  attribute \enum_value_0011101 "OP_DIV"
-  attribute \enum_value_0011110 "OP_DIVE"
-  attribute \enum_value_0011111 "OP_EXTS"
-  attribute \enum_value_0100000 "OP_EXTSWSLI"
-  attribute \enum_value_0100001 "OP_ICBI"
-  attribute \enum_value_0100010 "OP_ICBT"
-  attribute \enum_value_0100011 "OP_ISEL"
-  attribute \enum_value_0100100 "OP_ISYNC"
-  attribute \enum_value_0100101 "OP_LOAD"
-  attribute \enum_value_0100110 "OP_STORE"
-  attribute \enum_value_0100111 "OP_MADDHD"
-  attribute \enum_value_0101000 "OP_MADDHDU"
-  attribute \enum_value_0101001 "OP_MADDLD"
-  attribute \enum_value_0101010 "OP_MCRF"
-  attribute \enum_value_0101011 "OP_MCRXR"
-  attribute \enum_value_0101100 "OP_MCRXRX"
-  attribute \enum_value_0101101 "OP_MFCR"
-  attribute \enum_value_0101110 "OP_MFSPR"
-  attribute \enum_value_0101111 "OP_MOD"
-  attribute \enum_value_0110000 "OP_MTCRF"
-  attribute \enum_value_0110001 "OP_MTSPR"
-  attribute \enum_value_0110010 "OP_MUL_L64"
-  attribute \enum_value_0110011 "OP_MUL_H64"
-  attribute \enum_value_0110100 "OP_MUL_H32"
-  attribute \enum_value_0110101 "OP_OR"
-  attribute \enum_value_0110110 "OP_POPCNT"
-  attribute \enum_value_0110111 "OP_PRTY"
-  attribute \enum_value_0111000 "OP_RLC"
-  attribute \enum_value_0111001 "OP_RLCL"
-  attribute \enum_value_0111010 "OP_RLCR"
-  attribute \enum_value_0111011 "OP_SETB"
-  attribute \enum_value_0111100 "OP_SHL"
-  attribute \enum_value_0111101 "OP_SHR"
-  attribute \enum_value_0111110 "OP_SYNC"
-  attribute \enum_value_0111111 "OP_TRAP"
-  attribute \enum_value_1000011 "OP_XOR"
-  attribute \enum_value_1000100 "OP_SIM_CONFIG"
-  attribute \enum_value_1000101 "OP_CROP"
-  attribute \enum_value_1000110 "OP_RFID"
-  attribute \enum_value_1000111 "OP_MFMSR"
-  attribute \enum_value_1001000 "OP_MTMSRD"
-  attribute \enum_value_1001001 "OP_SC"
-  attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 7 \mul_pipe3_mul_op__insn_type$41
-  attribute \enum_base_type "Function"
-  attribute \enum_value_00000000000 "NONE"
-  attribute \enum_value_00000000010 "ALU"
-  attribute \enum_value_00000000100 "LDST"
-  attribute \enum_value_00000001000 "SHIFT_ROT"
-  attribute \enum_value_00000010000 "LOGICAL"
-  attribute \enum_value_00000100000 "BRANCH"
-  attribute \enum_value_00001000000 "CR"
-  attribute \enum_value_00010000000 "TRAP"
-  attribute \enum_value_00100000000 "MUL"
-  attribute \enum_value_01000000000 "DIV"
-  attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 11 \mul_pipe3_mul_op__fn_unit$42
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 64 \mul_pipe3_mul_op__imm_data__imm$43
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_pipe3_mul_op__imm_data__imm_ok$44
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_pipe3_mul_op__rc__rc$45
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_pipe3_mul_op__rc__rc_ok$46
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_pipe3_mul_op__oe__oe$47
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_pipe3_mul_op__oe__oe_ok$48
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_pipe3_mul_op__invert_a$49
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_pipe3_mul_op__zero_a$50
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_pipe3_mul_op__invert_out$51
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_pipe3_mul_op__write_cr0$52
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_pipe3_mul_op__is_32bit$53
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_pipe3_mul_op__is_signed$54
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 32 \mul_pipe3_mul_op__insn$55
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 64 \mul_pipe3_o$56
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 \mul_pipe3_o_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 4 \mul_pipe3_cr_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 \mul_pipe3_cr_a_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 2 \mul_pipe3_xer_ov
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 \mul_pipe3_xer_ov_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 \mul_pipe3_xer_so$57
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 \mul_pipe3_xer_so_ok
-  cell \mul_pipe3 \mul_pipe3
-    connect \rst \rst
-    connect \clk \clk
-    connect \p_valid_i \mul_pipe3_p_valid_i
-    connect \p_ready_o \mul_pipe3_p_ready_o
-    connect \muxid \mul_pipe3_muxid
-    connect \mul_op__insn_type \mul_pipe3_mul_op__insn_type
-    connect \mul_op__fn_unit \mul_pipe3_mul_op__fn_unit
-    connect \mul_op__imm_data__imm \mul_pipe3_mul_op__imm_data__imm
-    connect \mul_op__imm_data__imm_ok \mul_pipe3_mul_op__imm_data__imm_ok
-    connect \mul_op__rc__rc \mul_pipe3_mul_op__rc__rc
-    connect \mul_op__rc__rc_ok \mul_pipe3_mul_op__rc__rc_ok
-    connect \mul_op__oe__oe \mul_pipe3_mul_op__oe__oe
-    connect \mul_op__oe__oe_ok \mul_pipe3_mul_op__oe__oe_ok
-    connect \mul_op__invert_a \mul_pipe3_mul_op__invert_a
-    connect \mul_op__zero_a \mul_pipe3_mul_op__zero_a
-    connect \mul_op__invert_out \mul_pipe3_mul_op__invert_out
-    connect \mul_op__write_cr0 \mul_pipe3_mul_op__write_cr0
-    connect \mul_op__is_32bit \mul_pipe3_mul_op__is_32bit
-    connect \mul_op__is_signed \mul_pipe3_mul_op__is_signed
-    connect \mul_op__insn \mul_pipe3_mul_op__insn
-    connect \o \mul_pipe3_o
-    connect \xer_so \mul_pipe3_xer_so
-    connect \neg_res \mul_pipe3_neg_res
-    connect \neg_res32 \mul_pipe3_neg_res32
-    connect \n_valid_o \mul_pipe3_n_valid_o
-    connect \n_ready_i \mul_pipe3_n_ready_i
-    connect \muxid$1 \mul_pipe3_muxid$40
-    connect \mul_op__insn_type$2 \mul_pipe3_mul_op__insn_type$41
-    connect \mul_op__fn_unit$3 \mul_pipe3_mul_op__fn_unit$42
-    connect \mul_op__imm_data__imm$4 \mul_pipe3_mul_op__imm_data__imm$43
-    connect \mul_op__imm_data__imm_ok$5 \mul_pipe3_mul_op__imm_data__imm_ok$44
-    connect \mul_op__rc__rc$6 \mul_pipe3_mul_op__rc__rc$45
-    connect \mul_op__rc__rc_ok$7 \mul_pipe3_mul_op__rc__rc_ok$46
-    connect \mul_op__oe__oe$8 \mul_pipe3_mul_op__oe__oe$47
-    connect \mul_op__oe__oe_ok$9 \mul_pipe3_mul_op__oe__oe_ok$48
-    connect \mul_op__invert_a$10 \mul_pipe3_mul_op__invert_a$49
-    connect \mul_op__zero_a$11 \mul_pipe3_mul_op__zero_a$50
-    connect \mul_op__invert_out$12 \mul_pipe3_mul_op__invert_out$51
-    connect \mul_op__write_cr0$13 \mul_pipe3_mul_op__write_cr0$52
-    connect \mul_op__is_32bit$14 \mul_pipe3_mul_op__is_32bit$53
-    connect \mul_op__is_signed$15 \mul_pipe3_mul_op__is_signed$54
-    connect \mul_op__insn$16 \mul_pipe3_mul_op__insn$55
-    connect \o$17 \mul_pipe3_o$56
-    connect \o_ok \mul_pipe3_o_ok
-    connect \cr_a \mul_pipe3_cr_a
-    connect \cr_a_ok \mul_pipe3_cr_a_ok
-    connect \xer_ov \mul_pipe3_xer_ov
-    connect \xer_ov_ok \mul_pipe3_xer_ov_ok
-    connect \xer_so$18 \mul_pipe3_xer_so$57
-    connect \xer_so_ok \mul_pipe3_xer_so_ok
-  end
-  process $group_0
-    assign \mul_pipe2_p_valid_i 1'0
-    assign \mul_pipe2_p_valid_i \mul_pipe1_n_valid_o
+  wire width 32 \logical_op__insn$89
+  process $group_90
+    assign \logical_op__insn_type$72 7'0000000
+    assign \logical_op__fn_unit$73 11'00000000000
+    assign \logical_op__imm_data__imm$74 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \logical_op__imm_data__imm_ok$75 1'0
+    assign \logical_op__rc__rc$76 1'0
+    assign \logical_op__rc__rc_ok$77 1'0
+    assign \logical_op__oe__oe$78 1'0
+    assign \logical_op__oe__oe_ok$79 1'0
+    assign \logical_op__invert_a$80 1'0
+    assign \logical_op__zero_a$81 1'0
+    assign \logical_op__input_carry$82 2'00
+    assign \logical_op__invert_out$83 1'0
+    assign \logical_op__write_cr0$84 1'0
+    assign \logical_op__output_carry$85 1'0
+    assign \logical_op__is_32bit$86 1'0
+    assign \logical_op__is_signed$87 1'0
+    assign \logical_op__data_len$88 4'0000
+    assign \logical_op__insn$89 32'00000000000000000000000000000000
+    assign { \logical_op__insn$89 \logical_op__data_len$88 \logical_op__is_signed$87 \logical_op__is_32bit$86 \logical_op__output_carry$85 \logical_op__write_cr0$84 \logical_op__invert_out$83 \logical_op__input_carry$82 \logical_op__zero_a$81 \logical_op__invert_a$80 { \logical_op__oe__oe_ok$79 \logical_op__oe__oe$78 } { \logical_op__rc__rc_ok$77 \logical_op__rc__rc$76 } { \logical_op__imm_data__imm_ok$75 \logical_op__imm_data__imm$74 } \logical_op__fn_unit$73 \logical_op__insn_type$72 } { \pipe_end_logical_op__insn$69 \pipe_end_logical_op__data_len$68 \pipe_end_logical_op__is_signed$67 \pipe_end_logical_op__is_32bit$66 \pipe_end_logical_op__output_carry$65 \pipe_end_logical_op__write_cr0$64 \pipe_end_logical_op__invert_out$63 \pipe_end_logical_op__input_carry$62 \pipe_end_logical_op__zero_a$61 \pipe_end_logical_op__invert_a$60 { \pipe_end_logical_op__oe__oe_ok$59 \pipe_end_logical_op__oe__oe$58 } { \pipe_end_logical_op__rc__rc_ok$57 \pipe_end_logical_op__rc__rc$56 } { \pipe_end_logical_op__imm_data__imm_ok$55 \pipe_end_logical_op__imm_data__imm$54 } \pipe_end_logical_op__fn_unit$53 \pipe_end_logical_op__insn_type$52 }
     sync init
   end
-  process $group_1
-    assign \mul_pipe1_n_ready_i 1'0
-    assign \mul_pipe1_n_ready_i \mul_pipe2_p_ready_o
+  process $group_108
+    assign \o 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \o_ok 1'0
+    assign { \o_ok \o } { \pipe_end_o_ok \pipe_end_o }
     sync init
   end
-  process $group_2
-    assign \mul_pipe2_muxid 2'00
-    assign \mul_pipe2_muxid \mul_pipe1_muxid
+  process $group_110
+    assign \cr_a 4'0000
+    assign \cr_a_ok 1'0
+    assign { \cr_a_ok \cr_a } { \pipe_end_cr_a_ok \pipe_end_cr_a }
     sync init
   end
-  process $group_3
-    assign \mul_pipe2_mul_op__insn_type 7'0000000
-    assign \mul_pipe2_mul_op__fn_unit 11'00000000000
-    assign \mul_pipe2_mul_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \mul_pipe2_mul_op__imm_data__imm_ok 1'0
-    assign \mul_pipe2_mul_op__rc__rc 1'0
-    assign \mul_pipe2_mul_op__rc__rc_ok 1'0
-    assign \mul_pipe2_mul_op__oe__oe 1'0
-    assign \mul_pipe2_mul_op__oe__oe_ok 1'0
-    assign \mul_pipe2_mul_op__invert_a 1'0
-    assign \mul_pipe2_mul_op__zero_a 1'0
-    assign \mul_pipe2_mul_op__invert_out 1'0
-    assign \mul_pipe2_mul_op__write_cr0 1'0
-    assign \mul_pipe2_mul_op__is_32bit 1'0
-    assign \mul_pipe2_mul_op__is_signed 1'0
-    assign \mul_pipe2_mul_op__insn 32'00000000000000000000000000000000
-    assign { \mul_pipe2_mul_op__insn \mul_pipe2_mul_op__is_signed \mul_pipe2_mul_op__is_32bit \mul_pipe2_mul_op__write_cr0 \mul_pipe2_mul_op__invert_out \mul_pipe2_mul_op__zero_a \mul_pipe2_mul_op__invert_a { \mul_pipe2_mul_op__oe__oe_ok \mul_pipe2_mul_op__oe__oe } { \mul_pipe2_mul_op__rc__rc_ok \mul_pipe2_mul_op__rc__rc } { \mul_pipe2_mul_op__imm_data__imm_ok \mul_pipe2_mul_op__imm_data__imm } \mul_pipe2_mul_op__fn_unit \mul_pipe2_mul_op__insn_type } { \mul_pipe1_mul_op__insn \mul_pipe1_mul_op__is_signed \mul_pipe1_mul_op__is_32bit \mul_pipe1_mul_op__write_cr0 \mul_pipe1_mul_op__invert_out \mul_pipe1_mul_op__zero_a \mul_pipe1_mul_op__invert_a { \mul_pipe1_mul_op__oe__oe_ok \mul_pipe1_mul_op__oe__oe } { \mul_pipe1_mul_op__rc__rc_ok \mul_pipe1_mul_op__rc__rc } { \mul_pipe1_mul_op__imm_data__imm_ok \mul_pipe1_mul_op__imm_data__imm } \mul_pipe1_mul_op__fn_unit \mul_pipe1_mul_op__insn_type }
+  process $group_112
+    assign \xer_ov 2'00
+    assign \xer_ov_ok 1'0
+    assign { \xer_ov_ok \xer_ov } { \pipe_end_xer_ov_ok \pipe_end_xer_ov }
     sync init
   end
-  process $group_18
-    assign \mul_pipe2_ra 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \mul_pipe2_ra \mul_pipe1_ra
+  process $group_114
+    assign \xer_so 1'0
+    assign \xer_so_ok 1'0
+    assign { \xer_so_ok \xer_so } { \pipe_end_xer_so_ok \pipe_end_xer_so$70 }
     sync init
   end
-  process $group_19
-    assign \mul_pipe2_rb 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \mul_pipe2_rb \mul_pipe1_rb
-    sync init
+  connect \muxid 2'00
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.fus.div0.src_l"
+module \src_l$80
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+  wire width 3 input 2 \s_src
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+  wire width 3 input 3 \r_src
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
+  wire width 3 output 4 \q_src
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
+  wire width 3 \q_int
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
+  wire width 3 \q_int$next
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  wire width 3 $1
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  cell $not $2
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 3
+    parameter \Y_WIDTH 3
+    connect \A \r_src
+    connect \Y $1
   end
-  process $group_20
-    assign \mul_pipe2_xer_so 1'0
-    assign \mul_pipe2_xer_so \mul_pipe1_xer_so
-    sync init
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  wire width 3 $3
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  cell $and $4
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 3
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 3
+    parameter \Y_WIDTH 3
+    connect \A \q_int
+    connect \B $1
+    connect \Y $3
   end
-  process $group_21
-    assign \mul_pipe2_neg_res 1'0
-    assign \mul_pipe2_neg_res \mul_pipe1_neg_res
-    sync init
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  wire width 3 $5
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  cell $or $6
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 3
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 3
+    parameter \Y_WIDTH 3
+    connect \A $3
+    connect \B \s_src
+    connect \Y $5
   end
-  process $group_22
-    assign \mul_pipe2_neg_res32 1'0
-    assign \mul_pipe2_neg_res32 \mul_pipe1_neg_res32
+  process $group_0
+    assign \q_int$next \q_int
+    assign \q_int$next $5
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
+      case 1'1
+        assign \q_int$next 3'000
+    end
     sync init
+      update \q_int 3'000
+    sync posedge \coresync_clk
+      update \q_int \q_int$next
   end
-  process $group_23
-    assign \mul_pipe3_p_valid_i 1'0
-    assign \mul_pipe3_p_valid_i \mul_pipe2_n_valid_o
-    sync init
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  wire width 3 $7
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  cell $not $8
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 3
+    parameter \Y_WIDTH 3
+    connect \A \r_src
+    connect \Y $7
   end
-  process $group_24
-    assign \mul_pipe2_n_ready_i 1'0
-    assign \mul_pipe2_n_ready_i \mul_pipe3_p_ready_o
-    sync init
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  wire width 3 $9
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  cell $and $10
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 3
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 3
+    parameter \Y_WIDTH 3
+    connect \A \q_int
+    connect \B $7
+    connect \Y $9
   end
-  process $group_25
-    assign \mul_pipe3_muxid 2'00
-    assign \mul_pipe3_muxid \mul_pipe2_muxid$21
-    sync init
-  end
-  process $group_26
-    assign \mul_pipe3_mul_op__insn_type 7'0000000
-    assign \mul_pipe3_mul_op__fn_unit 11'00000000000
-    assign \mul_pipe3_mul_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \mul_pipe3_mul_op__imm_data__imm_ok 1'0
-    assign \mul_pipe3_mul_op__rc__rc 1'0
-    assign \mul_pipe3_mul_op__rc__rc_ok 1'0
-    assign \mul_pipe3_mul_op__oe__oe 1'0
-    assign \mul_pipe3_mul_op__oe__oe_ok 1'0
-    assign \mul_pipe3_mul_op__invert_a 1'0
-    assign \mul_pipe3_mul_op__zero_a 1'0
-    assign \mul_pipe3_mul_op__invert_out 1'0
-    assign \mul_pipe3_mul_op__write_cr0 1'0
-    assign \mul_pipe3_mul_op__is_32bit 1'0
-    assign \mul_pipe3_mul_op__is_signed 1'0
-    assign \mul_pipe3_mul_op__insn 32'00000000000000000000000000000000
-    assign { \mul_pipe3_mul_op__insn \mul_pipe3_mul_op__is_signed \mul_pipe3_mul_op__is_32bit \mul_pipe3_mul_op__write_cr0 \mul_pipe3_mul_op__invert_out \mul_pipe3_mul_op__zero_a \mul_pipe3_mul_op__invert_a { \mul_pipe3_mul_op__oe__oe_ok \mul_pipe3_mul_op__oe__oe } { \mul_pipe3_mul_op__rc__rc_ok \mul_pipe3_mul_op__rc__rc } { \mul_pipe3_mul_op__imm_data__imm_ok \mul_pipe3_mul_op__imm_data__imm } \mul_pipe3_mul_op__fn_unit \mul_pipe3_mul_op__insn_type } { \mul_pipe2_mul_op__insn$36 \mul_pipe2_mul_op__is_signed$35 \mul_pipe2_mul_op__is_32bit$34 \mul_pipe2_mul_op__write_cr0$33 \mul_pipe2_mul_op__invert_out$32 \mul_pipe2_mul_op__zero_a$31 \mul_pipe2_mul_op__invert_a$30 { \mul_pipe2_mul_op__oe__oe_ok$29 \mul_pipe2_mul_op__oe__oe$28 } { \mul_pipe2_mul_op__rc__rc_ok$27 \mul_pipe2_mul_op__rc__rc$26 } { \mul_pipe2_mul_op__imm_data__imm_ok$25 \mul_pipe2_mul_op__imm_data__imm$24 } \mul_pipe2_mul_op__fn_unit$23 \mul_pipe2_mul_op__insn_type$22 }
-    sync init
-  end
-  process $group_41
-    assign \mul_pipe3_o 129'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
-    assign \mul_pipe3_o \mul_pipe2_o
-    sync init
-  end
-  process $group_42
-    assign \mul_pipe3_xer_so 1'0
-    assign \mul_pipe3_xer_so \mul_pipe2_xer_so$37
-    sync init
-  end
-  process $group_43
-    assign \mul_pipe3_neg_res 1'0
-    assign \mul_pipe3_neg_res \mul_pipe2_neg_res$38
-    sync init
-  end
-  process $group_44
-    assign \mul_pipe3_neg_res32 1'0
-    assign \mul_pipe3_neg_res32 \mul_pipe2_neg_res32$39
-    sync init
-  end
-  process $group_45
-    assign \mul_pipe1_p_valid_i 1'0
-    assign \mul_pipe1_p_valid_i \p_valid_i
-    sync init
-  end
-  process $group_46
-    assign \p_ready_o 1'0
-    assign \p_ready_o \mul_pipe1_p_ready_o
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
-  wire width 2 \muxid
-  process $group_47
-    assign \mul_pipe1_muxid$2 2'00
-    assign \mul_pipe1_muxid$2 \muxid
-    sync init
-  end
-  process $group_48
-    assign \mul_pipe1_mul_op__insn_type$3 7'0000000
-    assign \mul_pipe1_mul_op__fn_unit$4 11'00000000000
-    assign \mul_pipe1_mul_op__imm_data__imm$5 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \mul_pipe1_mul_op__imm_data__imm_ok$6 1'0
-    assign \mul_pipe1_mul_op__rc__rc$7 1'0
-    assign \mul_pipe1_mul_op__rc__rc_ok$8 1'0
-    assign \mul_pipe1_mul_op__oe__oe$9 1'0
-    assign \mul_pipe1_mul_op__oe__oe_ok$10 1'0
-    assign \mul_pipe1_mul_op__invert_a$11 1'0
-    assign \mul_pipe1_mul_op__zero_a$12 1'0
-    assign \mul_pipe1_mul_op__invert_out$13 1'0
-    assign \mul_pipe1_mul_op__write_cr0$14 1'0
-    assign \mul_pipe1_mul_op__is_32bit$15 1'0
-    assign \mul_pipe1_mul_op__is_signed$16 1'0
-    assign \mul_pipe1_mul_op__insn$17 32'00000000000000000000000000000000
-    assign { \mul_pipe1_mul_op__insn$17 \mul_pipe1_mul_op__is_signed$16 \mul_pipe1_mul_op__is_32bit$15 \mul_pipe1_mul_op__write_cr0$14 \mul_pipe1_mul_op__invert_out$13 \mul_pipe1_mul_op__zero_a$12 \mul_pipe1_mul_op__invert_a$11 { \mul_pipe1_mul_op__oe__oe_ok$10 \mul_pipe1_mul_op__oe__oe$9 } { \mul_pipe1_mul_op__rc__rc_ok$8 \mul_pipe1_mul_op__rc__rc$7 } { \mul_pipe1_mul_op__imm_data__imm_ok$6 \mul_pipe1_mul_op__imm_data__imm$5 } \mul_pipe1_mul_op__fn_unit$4 \mul_pipe1_mul_op__insn_type$3 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__invert_out \mul_op__zero_a \mul_op__invert_a { \mul_op__oe__oe_ok \mul_op__oe__oe } { \mul_op__rc__rc_ok \mul_op__rc__rc } { \mul_op__imm_data__imm_ok \mul_op__imm_data__imm } \mul_op__fn_unit \mul_op__insn_type }
-    sync init
-  end
-  process $group_63
-    assign \mul_pipe1_ra$18 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \mul_pipe1_ra$18 \ra
-    sync init
-  end
-  process $group_64
-    assign \mul_pipe1_rb$19 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \mul_pipe1_rb$19 \rb
-    sync init
-  end
-  process $group_65
-    assign \mul_pipe1_xer_so$20 1'0
-    assign \mul_pipe1_xer_so$20 \xer_so$1
-    sync init
-  end
-  process $group_66
-    assign \n_valid_o 1'0
-    assign \n_valid_o \mul_pipe3_n_valid_o
-    sync init
-  end
-  process $group_67
-    assign \mul_pipe3_n_ready_i 1'0
-    assign \mul_pipe3_n_ready_i \n_ready_i
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
-  wire width 2 \muxid$58
-  process $group_68
-    assign \muxid$58 2'00
-    assign \muxid$58 \mul_pipe3_muxid$40
-    sync init
-  end
-  attribute \enum_base_type "MicrOp"
-  attribute \enum_value_0000000 "OP_ILLEGAL"
-  attribute \enum_value_0000001 "OP_NOP"
-  attribute \enum_value_0000010 "OP_ADD"
-  attribute \enum_value_0000011 "OP_ADDPCIS"
-  attribute \enum_value_0000100 "OP_AND"
-  attribute \enum_value_0000101 "OP_ATTN"
-  attribute \enum_value_0000110 "OP_B"
-  attribute \enum_value_0000111 "OP_BC"
-  attribute \enum_value_0001000 "OP_BCREG"
-  attribute \enum_value_0001001 "OP_BPERM"
-  attribute \enum_value_0001010 "OP_CMP"
-  attribute \enum_value_0001011 "OP_CMPB"
-  attribute \enum_value_0001100 "OP_CMPEQB"
-  attribute \enum_value_0001101 "OP_CMPRB"
-  attribute \enum_value_0001110 "OP_CNTZ"
-  attribute \enum_value_0001111 "OP_CRAND"
-  attribute \enum_value_0010000 "OP_CRANDC"
-  attribute \enum_value_0010001 "OP_CREQV"
-  attribute \enum_value_0010010 "OP_CRNAND"
-  attribute \enum_value_0010011 "OP_CRNOR"
-  attribute \enum_value_0010100 "OP_CROR"
-  attribute \enum_value_0010101 "OP_CRORC"
-  attribute \enum_value_0010110 "OP_CRXOR"
-  attribute \enum_value_0010111 "OP_DARN"
-  attribute \enum_value_0011000 "OP_DCBF"
-  attribute \enum_value_0011001 "OP_DCBST"
-  attribute \enum_value_0011010 "OP_DCBT"
-  attribute \enum_value_0011011 "OP_DCBTST"
-  attribute \enum_value_0011100 "OP_DCBZ"
-  attribute \enum_value_0011101 "OP_DIV"
-  attribute \enum_value_0011110 "OP_DIVE"
-  attribute \enum_value_0011111 "OP_EXTS"
-  attribute \enum_value_0100000 "OP_EXTSWSLI"
-  attribute \enum_value_0100001 "OP_ICBI"
-  attribute \enum_value_0100010 "OP_ICBT"
-  attribute \enum_value_0100011 "OP_ISEL"
-  attribute \enum_value_0100100 "OP_ISYNC"
-  attribute \enum_value_0100101 "OP_LOAD"
-  attribute \enum_value_0100110 "OP_STORE"
-  attribute \enum_value_0100111 "OP_MADDHD"
-  attribute \enum_value_0101000 "OP_MADDHDU"
-  attribute \enum_value_0101001 "OP_MADDLD"
-  attribute \enum_value_0101010 "OP_MCRF"
-  attribute \enum_value_0101011 "OP_MCRXR"
-  attribute \enum_value_0101100 "OP_MCRXRX"
-  attribute \enum_value_0101101 "OP_MFCR"
-  attribute \enum_value_0101110 "OP_MFSPR"
-  attribute \enum_value_0101111 "OP_MOD"
-  attribute \enum_value_0110000 "OP_MTCRF"
-  attribute \enum_value_0110001 "OP_MTSPR"
-  attribute \enum_value_0110010 "OP_MUL_L64"
-  attribute \enum_value_0110011 "OP_MUL_H64"
-  attribute \enum_value_0110100 "OP_MUL_H32"
-  attribute \enum_value_0110101 "OP_OR"
-  attribute \enum_value_0110110 "OP_POPCNT"
-  attribute \enum_value_0110111 "OP_PRTY"
-  attribute \enum_value_0111000 "OP_RLC"
-  attribute \enum_value_0111001 "OP_RLCL"
-  attribute \enum_value_0111010 "OP_RLCR"
-  attribute \enum_value_0111011 "OP_SETB"
-  attribute \enum_value_0111100 "OP_SHL"
-  attribute \enum_value_0111101 "OP_SHR"
-  attribute \enum_value_0111110 "OP_SYNC"
-  attribute \enum_value_0111111 "OP_TRAP"
-  attribute \enum_value_1000011 "OP_XOR"
-  attribute \enum_value_1000100 "OP_SIM_CONFIG"
-  attribute \enum_value_1000101 "OP_CROP"
-  attribute \enum_value_1000110 "OP_RFID"
-  attribute \enum_value_1000111 "OP_MFMSR"
-  attribute \enum_value_1001000 "OP_MTMSRD"
-  attribute \enum_value_1001001 "OP_SC"
-  attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 7 \mul_op__insn_type$59
-  attribute \enum_base_type "Function"
-  attribute \enum_value_00000000000 "NONE"
-  attribute \enum_value_00000000010 "ALU"
-  attribute \enum_value_00000000100 "LDST"
-  attribute \enum_value_00000001000 "SHIFT_ROT"
-  attribute \enum_value_00000010000 "LOGICAL"
-  attribute \enum_value_00000100000 "BRANCH"
-  attribute \enum_value_00001000000 "CR"
-  attribute \enum_value_00010000000 "TRAP"
-  attribute \enum_value_00100000000 "MUL"
-  attribute \enum_value_01000000000 "DIV"
-  attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 11 \mul_op__fn_unit$60
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 64 \mul_op__imm_data__imm$61
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_op__imm_data__imm_ok$62
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_op__rc__rc$63
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_op__rc__rc_ok$64
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_op__oe__oe$65
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_op__oe__oe_ok$66
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_op__invert_a$67
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_op__zero_a$68
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_op__invert_out$69
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_op__write_cr0$70
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_op__is_32bit$71
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \mul_op__is_signed$72
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 32 \mul_op__insn$73
-  process $group_69
-    assign \mul_op__insn_type$59 7'0000000
-    assign \mul_op__fn_unit$60 11'00000000000
-    assign \mul_op__imm_data__imm$61 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \mul_op__imm_data__imm_ok$62 1'0
-    assign \mul_op__rc__rc$63 1'0
-    assign \mul_op__rc__rc_ok$64 1'0
-    assign \mul_op__oe__oe$65 1'0
-    assign \mul_op__oe__oe_ok$66 1'0
-    assign \mul_op__invert_a$67 1'0
-    assign \mul_op__zero_a$68 1'0
-    assign \mul_op__invert_out$69 1'0
-    assign \mul_op__write_cr0$70 1'0
-    assign \mul_op__is_32bit$71 1'0
-    assign \mul_op__is_signed$72 1'0
-    assign \mul_op__insn$73 32'00000000000000000000000000000000
-    assign { \mul_op__insn$73 \mul_op__is_signed$72 \mul_op__is_32bit$71 \mul_op__write_cr0$70 \mul_op__invert_out$69 \mul_op__zero_a$68 \mul_op__invert_a$67 { \mul_op__oe__oe_ok$66 \mul_op__oe__oe$65 } { \mul_op__rc__rc_ok$64 \mul_op__rc__rc$63 } { \mul_op__imm_data__imm_ok$62 \mul_op__imm_data__imm$61 } \mul_op__fn_unit$60 \mul_op__insn_type$59 } { \mul_pipe3_mul_op__insn$55 \mul_pipe3_mul_op__is_signed$54 \mul_pipe3_mul_op__is_32bit$53 \mul_pipe3_mul_op__write_cr0$52 \mul_pipe3_mul_op__invert_out$51 \mul_pipe3_mul_op__zero_a$50 \mul_pipe3_mul_op__invert_a$49 { \mul_pipe3_mul_op__oe__oe_ok$48 \mul_pipe3_mul_op__oe__oe$47 } { \mul_pipe3_mul_op__rc__rc_ok$46 \mul_pipe3_mul_op__rc__rc$45 } { \mul_pipe3_mul_op__imm_data__imm_ok$44 \mul_pipe3_mul_op__imm_data__imm$43 } \mul_pipe3_mul_op__fn_unit$42 \mul_pipe3_mul_op__insn_type$41 }
-    sync init
-  end
-  process $group_84
-    assign \o 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \o_ok 1'0
-    assign { \o_ok \o } { \mul_pipe3_o_ok \mul_pipe3_o$56 }
-    sync init
-  end
-  process $group_86
-    assign \cr_a 4'0000
-    assign \cr_a_ok 1'0
-    assign { \cr_a_ok \cr_a } { \mul_pipe3_cr_a_ok \mul_pipe3_cr_a }
-    sync init
-  end
-  process $group_88
-    assign \xer_ov 2'00
-    assign \xer_ov_ok 1'0
-    assign { \xer_ov_ok \xer_ov } { \mul_pipe3_xer_ov_ok \mul_pipe3_xer_ov }
-    sync init
-  end
-  process $group_90
-    assign \xer_so 1'0
-    assign \xer_so_ok 1'0
-    assign { \xer_so_ok \xer_so } { \mul_pipe3_xer_so_ok \mul_pipe3_xer_so$57 }
-    sync init
-  end
-  connect \muxid 2'00
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.src_l"
-module \src_l$80
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
-  wire width 3 input 2 \s_src
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
-  wire width 3 input 3 \r_src
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
-  wire width 3 output 4 \q_src
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
-  wire width 3 \q_int
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
-  wire width 3 \q_int$next
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
-  wire width 3 $1
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
-  cell $not $2
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 3
-    parameter \Y_WIDTH 3
-    connect \A \r_src
-    connect \Y $1
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
-  wire width 3 $3
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
-  cell $and $4
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 3
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 3
-    parameter \Y_WIDTH 3
-    connect \A \q_int
-    connect \B $1
-    connect \Y $3
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
-  wire width 3 $5
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
-  cell $or $6
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 3
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 3
-    parameter \Y_WIDTH 3
-    connect \A $3
-    connect \B \s_src
-    connect \Y $5
-  end
-  process $group_0
-    assign \q_int$next \q_int
-    assign \q_int$next $5
-    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
-      case 1'1
-        assign \q_int$next 3'000
-    end
-    sync init
-      update \q_int 3'000
-    sync posedge \clk
-      update \q_int \q_int$next
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
-  wire width 3 $7
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
-  cell $not $8
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 3
-    parameter \Y_WIDTH 3
-    connect \A \r_src
-    connect \Y $7
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
-  wire width 3 $9
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
-  cell $and $10
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 3
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 3
-    parameter \Y_WIDTH 3
-    connect \A \q_int
-    connect \B $7
-    connect \Y $9
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
-  wire width 3 $11
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
-  cell $or $12
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 3
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 3
-    parameter \Y_WIDTH 3
-    connect \A $9
-    connect \B \s_src
-    connect \Y $11
-  end
-  process $group_1
-    assign \q_src 3'000
-    assign \q_src $11
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  wire width 3 $11
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  cell $or $12
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 3
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 3
+    parameter \Y_WIDTH 3
+    connect \A $9
+    connect \B \s_src
+    connect \Y $11
+  end
+  process $group_1
+    assign \q_src 3'000
+    assign \q_src $11
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
@@ -96829,12 +97502,12 @@ module \src_l$80
   end
 end
 attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.opc_l"
+attribute \nmigen.hierarchy "test_issuer.core.fus.div0.opc_l"
 module \opc_l$81
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
   wire width 1 input 2 \s_opc
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
@@ -96885,13 +97558,13 @@ module \opc_l$81
     assign \q_int$next \q_int
     assign \q_int$next $5
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \q_int$next 1'0
     end
     sync init
       update \q_int 1'0
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \q_int \q_int$next
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
@@ -96974,12 +97647,12 @@ module \opc_l$81
   end
 end
 attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.req_l"
+attribute \nmigen.hierarchy "test_issuer.core.fus.div0.req_l"
 module \req_l$82
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
   wire width 4 output 2 \q_req
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
@@ -97030,13 +97703,13 @@ module \req_l$82
     assign \q_int$next \q_int
     assign \q_int$next $5
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \q_int$next 4'0000
     end
     sync init
       update \q_int 4'0000
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \q_int \q_int$next
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
@@ -97119,12 +97792,12 @@ module \req_l$82
   end
 end
 attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.rst_l"
+attribute \nmigen.hierarchy "test_issuer.core.fus.div0.rst_l"
 module \rst_l$83
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
   wire width 1 input 2 \s_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
@@ -97173,13 +97846,13 @@ module \rst_l$83
     assign \q_int$next \q_int
     assign \q_int$next $5
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \q_int$next 1'0
     end
     sync init
       update \q_int 1'0
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \q_int \q_int$next
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
@@ -97264,12 +97937,12 @@ module \rst_l$83
   end
 end
 attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.rok_l"
+attribute \nmigen.hierarchy "test_issuer.core.fus.div0.rok_l"
 module \rok_l$84
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
   wire width 1 output 2 \q_rdok
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
@@ -97320,13 +97993,13 @@ module \rok_l$84
     assign \q_int$next \q_int
     assign \q_int$next $5
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \q_int$next 1'0
     end
     sync init
       update \q_int 1'0
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \q_int \q_int$next
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
@@ -97409,12 +98082,12 @@ module \rok_l$84
   end
 end
 attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alui_l"
+attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alui_l"
 module \alui_l$85
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
   wire width 1 output 2 \q_alui
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
@@ -97465,13 +98138,13 @@ module \alui_l$85
     assign \q_int$next \q_int
     assign \q_int$next $5
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \q_int$next 1'0
     end
     sync init
       update \q_int 1'0
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \q_int \q_int$next
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
@@ -97554,12 +98227,12 @@ module \alui_l$85
   end
 end
 attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_l"
+attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_l"
 module \alu_l$86
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
   wire width 1 output 2 \q_alu
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
@@ -97610,13 +98283,13 @@ module \alu_l$86
     assign \q_int$next \q_int
     assign \q_int$next $5
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \q_int$next 1'0
     end
     sync init
       update \q_int 1'0
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \q_int \q_int$next
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
@@ -97699,12 +98372,10 @@ module \alu_l$86
   end
 end
 attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.fus.mul0"
-module \mul0
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
+attribute \nmigen.hierarchy "test_issuer.core.fus.div0"
+module \div0
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
   attribute \enum_value_0000001 "OP_NOP"
@@ -97779,7 +98450,7 @@ module \mul0
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 7 input 2 \oper_i_alu_mul0__insn_type
+  wire width 7 input 1 \oper_i_alu_div0__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -97793,81 +98464,93 @@ module \mul0
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 11 input 3 \oper_i_alu_mul0__fn_unit
+  wire width 11 input 2 \oper_i_alu_div0__fn_unit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 input 3 \oper_i_alu_div0__imm_data__imm
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 64 input 4 \oper_i_alu_mul0__imm_data__imm
+  wire width 1 input 4 \oper_i_alu_div0__imm_data__imm_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 5 \oper_i_alu_mul0__imm_data__imm_ok
+  wire width 1 input 5 \oper_i_alu_div0__rc__rc
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 6 \oper_i_alu_mul0__rc__rc
+  wire width 1 input 6 \oper_i_alu_div0__rc__rc_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 7 \oper_i_alu_mul0__rc__rc_ok
+  wire width 1 input 7 \oper_i_alu_div0__oe__oe
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 8 \oper_i_alu_mul0__oe__oe
+  wire width 1 input 8 \oper_i_alu_div0__oe__oe_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 9 \oper_i_alu_mul0__oe__oe_ok
+  wire width 1 input 9 \oper_i_alu_div0__invert_a
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 10 \oper_i_alu_mul0__invert_a
+  wire width 1 input 10 \oper_i_alu_div0__zero_a
+  attribute \enum_base_type "CryIn"
+  attribute \enum_value_00 "ZERO"
+  attribute \enum_value_01 "ONE"
+  attribute \enum_value_10 "CA"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 11 \oper_i_alu_mul0__zero_a
+  wire width 2 input 11 \oper_i_alu_div0__input_carry
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 12 \oper_i_alu_mul0__invert_out
+  wire width 1 input 12 \oper_i_alu_div0__invert_out
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 13 \oper_i_alu_mul0__write_cr0
+  wire width 1 input 13 \oper_i_alu_div0__write_cr0
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 14 \oper_i_alu_mul0__is_32bit
+  wire width 1 input 14 \oper_i_alu_div0__output_carry
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 15 \oper_i_alu_mul0__is_signed
+  wire width 1 input 15 \oper_i_alu_div0__is_32bit
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 32 input 16 \oper_i_alu_mul0__insn
+  wire width 1 input 16 \oper_i_alu_div0__is_signed
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 4 input 17 \oper_i_alu_div0__data_len
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 input 18 \oper_i_alu_div0__insn
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
-  wire width 1 input 17 \cu_issue_i
+  wire width 1 input 19 \cu_issue_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:106"
-  wire width 1 output 18 \cu_busy_o
+  wire width 1 output 20 \cu_busy_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
-  wire width 3 input 19 \cu_rdmaskn_i
+  wire width 3 input 21 \cu_rdmaskn_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 3 output 20 \cu_rd__rel_o
+  wire width 3 output 22 \cu_rd__rel_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 3 input 21 \cu_rd__go_i
+  wire width 3 input 23 \cu_rd__go_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
-  wire width 64 input 22 \src1_i
+  wire width 64 input 24 \src1_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
-  wire width 64 input 23 \src2_i
+  wire width 64 input 25 \src2_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
-  wire width 1 input 24 \src3_i
+  wire width 1 input 26 \src3_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 25 \o_ok
+  wire width 1 output 27 \o_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 4 output 26 \cu_wr__rel_o
+  wire width 4 output 28 \cu_wr__rel_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 4 input 27 \cu_wr__go_i
+  wire width 4 input 29 \cu_wr__go_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
-  wire width 64 output 28 \dest1_o
+  wire width 64 output 30 \dest1_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 29 \cr_a_ok
+  wire width 1 output 31 \cr_a_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
-  wire width 4 output 30 \dest2_o
+  wire width 4 output 32 \dest2_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 31 \xer_ov_ok
+  wire width 1 output 33 \xer_ov_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
-  wire width 2 output 32 \dest3_o
+  wire width 2 output 34 \dest3_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 33 \xer_so_ok
+  wire width 1 output 35 \xer_so_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
-  wire width 1 output 34 \dest4_o
+  wire width 1 output 36 \dest4_o
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 37 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
-  wire width 1 \alu_mul0_n_valid_o
+  wire width 1 \alu_div0_n_valid_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
-  wire width 1 \alu_mul0_n_ready_i
+  wire width 1 \alu_div0_n_ready_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 64 \alu_mul0_o
+  wire width 64 \alu_div0_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 4 \alu_mul0_cr_a
+  wire width 4 \alu_div0_cr_a
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 2 \alu_mul0_xer_ov
+  wire width 2 \alu_div0_xer_ov
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 \alu_mul0_xer_so
+  wire width 1 \alu_div0_xer_so
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
   attribute \enum_value_0000001 "OP_NOP"
@@ -97942,7 +98625,7 @@ module \mul0
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 7 \alu_mul0_mul_op__insn_type
+  wire width 7 \alu_div0_logical_op__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -97956,76 +98639,89 @@ module \mul0
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 11 \alu_mul0_mul_op__fn_unit
+  wire width 11 \alu_div0_logical_op__fn_unit
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 64 \alu_mul0_mul_op__imm_data__imm
+  wire width 64 \alu_div0_logical_op__imm_data__imm
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \alu_mul0_mul_op__imm_data__imm_ok
+  wire width 1 \alu_div0_logical_op__imm_data__imm_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \alu_mul0_mul_op__rc__rc
+  wire width 1 \alu_div0_logical_op__rc__rc
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \alu_mul0_mul_op__rc__rc_ok
+  wire width 1 \alu_div0_logical_op__rc__rc_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \alu_mul0_mul_op__oe__oe
+  wire width 1 \alu_div0_logical_op__oe__oe
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \alu_mul0_mul_op__oe__oe_ok
+  wire width 1 \alu_div0_logical_op__oe__oe_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \alu_mul0_mul_op__invert_a
+  wire width 1 \alu_div0_logical_op__invert_a
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \alu_mul0_mul_op__zero_a
+  wire width 1 \alu_div0_logical_op__zero_a
+  attribute \enum_base_type "CryIn"
+  attribute \enum_value_00 "ZERO"
+  attribute \enum_value_01 "ONE"
+  attribute \enum_value_10 "CA"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \alu_mul0_mul_op__invert_out
+  wire width 2 \alu_div0_logical_op__input_carry
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \alu_mul0_mul_op__write_cr0
+  wire width 1 \alu_div0_logical_op__invert_out
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \alu_mul0_mul_op__is_32bit
+  wire width 1 \alu_div0_logical_op__write_cr0
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \alu_mul0_mul_op__is_signed
+  wire width 1 \alu_div0_logical_op__output_carry
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 32 \alu_mul0_mul_op__insn
+  wire width 1 \alu_div0_logical_op__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \alu_div0_logical_op__is_signed
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 4 \alu_div0_logical_op__data_len
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \alu_div0_logical_op__insn
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
-  wire width 64 \alu_mul0_ra
+  wire width 64 \alu_div0_ra
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
-  wire width 64 \alu_mul0_rb
+  wire width 64 \alu_div0_rb
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
-  wire width 1 \alu_mul0_xer_so$1
+  wire width 1 \alu_div0_xer_so$1
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153"
-  wire width 1 \alu_mul0_p_valid_i
+  wire width 1 \alu_div0_p_valid_i
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154"
-  wire width 1 \alu_mul0_p_ready_o
-  cell \alu_mul0 \alu_mul0
-    connect \rst \rst
-    connect \clk \clk
+  wire width 1 \alu_div0_p_ready_o
+  cell \alu_div0 \alu_div0
+    connect \coresync_clk \coresync_clk
     connect \o_ok \o_ok
     connect \cr_a_ok \cr_a_ok
     connect \xer_ov_ok \xer_ov_ok
     connect \xer_so_ok \xer_so_ok
-    connect \n_valid_o \alu_mul0_n_valid_o
-    connect \n_ready_i \alu_mul0_n_ready_i
-    connect \o \alu_mul0_o
-    connect \cr_a \alu_mul0_cr_a
-    connect \xer_ov \alu_mul0_xer_ov
-    connect \xer_so \alu_mul0_xer_so
-    connect \mul_op__insn_type \alu_mul0_mul_op__insn_type
-    connect \mul_op__fn_unit \alu_mul0_mul_op__fn_unit
-    connect \mul_op__imm_data__imm \alu_mul0_mul_op__imm_data__imm
-    connect \mul_op__imm_data__imm_ok \alu_mul0_mul_op__imm_data__imm_ok
-    connect \mul_op__rc__rc \alu_mul0_mul_op__rc__rc
-    connect \mul_op__rc__rc_ok \alu_mul0_mul_op__rc__rc_ok
-    connect \mul_op__oe__oe \alu_mul0_mul_op__oe__oe
-    connect \mul_op__oe__oe_ok \alu_mul0_mul_op__oe__oe_ok
-    connect \mul_op__invert_a \alu_mul0_mul_op__invert_a
-    connect \mul_op__zero_a \alu_mul0_mul_op__zero_a
-    connect \mul_op__invert_out \alu_mul0_mul_op__invert_out
-    connect \mul_op__write_cr0 \alu_mul0_mul_op__write_cr0
-    connect \mul_op__is_32bit \alu_mul0_mul_op__is_32bit
-    connect \mul_op__is_signed \alu_mul0_mul_op__is_signed
-    connect \mul_op__insn \alu_mul0_mul_op__insn
-    connect \ra \alu_mul0_ra
-    connect \rb \alu_mul0_rb
-    connect \xer_so$1 \alu_mul0_xer_so$1
-    connect \p_valid_i \alu_mul0_p_valid_i
-    connect \p_ready_o \alu_mul0_p_ready_o
+    connect \coresync_rst \coresync_rst
+    connect \n_valid_o \alu_div0_n_valid_o
+    connect \n_ready_i \alu_div0_n_ready_i
+    connect \o \alu_div0_o
+    connect \cr_a \alu_div0_cr_a
+    connect \xer_ov \alu_div0_xer_ov
+    connect \xer_so \alu_div0_xer_so
+    connect \logical_op__insn_type \alu_div0_logical_op__insn_type
+    connect \logical_op__fn_unit \alu_div0_logical_op__fn_unit
+    connect \logical_op__imm_data__imm \alu_div0_logical_op__imm_data__imm
+    connect \logical_op__imm_data__imm_ok \alu_div0_logical_op__imm_data__imm_ok
+    connect \logical_op__rc__rc \alu_div0_logical_op__rc__rc
+    connect \logical_op__rc__rc_ok \alu_div0_logical_op__rc__rc_ok
+    connect \logical_op__oe__oe \alu_div0_logical_op__oe__oe
+    connect \logical_op__oe__oe_ok \alu_div0_logical_op__oe__oe_ok
+    connect \logical_op__invert_a \alu_div0_logical_op__invert_a
+    connect \logical_op__zero_a \alu_div0_logical_op__zero_a
+    connect \logical_op__input_carry \alu_div0_logical_op__input_carry
+    connect \logical_op__invert_out \alu_div0_logical_op__invert_out
+    connect \logical_op__write_cr0 \alu_div0_logical_op__write_cr0
+    connect \logical_op__output_carry \alu_div0_logical_op__output_carry
+    connect \logical_op__is_32bit \alu_div0_logical_op__is_32bit
+    connect \logical_op__is_signed \alu_div0_logical_op__is_signed
+    connect \logical_op__data_len \alu_div0_logical_op__data_len
+    connect \logical_op__insn \alu_div0_logical_op__insn
+    connect \ra \alu_div0_ra
+    connect \rb \alu_div0_rb
+    connect \xer_so$1 \alu_div0_xer_so$1
+    connect \p_valid_i \alu_div0_p_valid_i
+    connect \p_ready_o \alu_div0_p_ready_o
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
   wire width 3 \src_l_s_src
@@ -98038,8 +98734,8 @@ module \mul0
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
   wire width 3 \src_l_q_src
   cell \src_l$80 \src_l
-    connect \rst \rst
-    connect \clk \clk
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
     connect \s_src \src_l_s_src
     connect \r_src \src_l_r_src
     connect \q_src \src_l_q_src
@@ -98055,8 +98751,8 @@ module \mul0
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
   wire width 1 \opc_l_q_opc
   cell \opc_l$81 \opc_l
-    connect \rst \rst
-    connect \clk \clk
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
     connect \s_opc \opc_l_s_opc
     connect \r_opc \opc_l_r_opc
     connect \q_opc \opc_l_q_opc
@@ -98068,8 +98764,8 @@ module \mul0
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
   wire width 4 \req_l_r_req
   cell \req_l$82 \req_l
-    connect \rst \rst
-    connect \clk \clk
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
     connect \q_req \req_l_q_req
     connect \s_req \req_l_s_req
     connect \r_req \req_l_r_req
@@ -98079,8 +98775,8 @@ module \mul0
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
   wire width 1 \rst_l_r_rst
   cell \rst_l$83 \rst_l
-    connect \rst \rst
-    connect \clk \clk
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
     connect \s_rst \rst_l_s_rst
     connect \r_rst \rst_l_r_rst
   end
@@ -98093,8 +98789,8 @@ module \mul0
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
   wire width 1 \rok_l_r_rdok$next
   cell \rok_l$84 \rok_l
-    connect \rst \rst
-    connect \clk \clk
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
     connect \q_rdok \rok_l_q_rdok
     connect \s_rdok \rok_l_s_rdok
     connect \r_rdok \rok_l_r_rdok
@@ -98108,8 +98804,8 @@ module \mul0
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
   wire width 1 \alui_l_s_alui
   cell \alui_l$85 \alui_l
-    connect \rst \rst
-    connect \clk \clk
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
     connect \q_alui \alui_l_q_alui
     connect \r_alui \alui_l_r_alui
     connect \s_alui \alui_l_s_alui
@@ -98123,8 +98819,8 @@ module \mul0
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
   wire width 1 \alu_l_s_alu
   cell \alu_l$86 \alu_l
-    connect \rst \rst
-    connect \clk \clk
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
     connect \q_alu \alu_l_q_alu
     connect \r_alu \alu_l_r_alu
     connect \s_alu \alu_l_s_alu
@@ -98204,7 +98900,7 @@ module \mul0
     assign \all_rd_dly$next \all_rd
     sync init
       update \all_rd_dly 1'0
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \all_rd_dly \all_rd_dly$next
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:192"
@@ -98241,7 +98937,7 @@ module \mul0
   wire width 1 \alu_done
   process $group_3
     assign \alu_done 1'0
-    assign \alu_done \alu_mul0_n_valid_o
+    assign \alu_done \alu_div0_n_valid_o
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198"
@@ -98253,7 +98949,7 @@ module \mul0
     assign \alu_done_dly$next \alu_done
     sync init
       update \alu_done_dly 1'0
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \alu_done_dly \alu_done_dly$next
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:199"
@@ -98314,13 +99010,13 @@ module \mul0
     assign \prev_wr_go$next \prev_wr_go
     assign \prev_wr_go$next $20
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \prev_wr_go$next 4'0000
     end
     sync init
       update \prev_wr_go 4'0000
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \prev_wr_go \prev_wr_go$next
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107"
@@ -98437,7 +99133,7 @@ module \mul0
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \alu_mul0_n_ready_i
+    connect \A \alu_div0_n_ready_i
     connect \Y $38
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:219"
@@ -98515,7 +99211,7 @@ module \mul0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A $48
-    connect \B \alu_mul0_n_ready_i
+    connect \B \alu_div0_n_ready_i
     connect \Y $50
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
@@ -98528,7 +99224,7 @@ module \mul0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A $50
-    connect \B \alu_mul0_n_valid_o
+    connect \B \alu_div0_n_valid_o
     connect \Y $52
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
@@ -98651,7 +99347,7 @@ module \mul0
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \alu_mul0_n_valid_o
+    connect \A \alu_div0_n_valid_o
     connect \B \cu_busy_o
     connect \Y $64
   end
@@ -98659,13 +99355,13 @@ module \mul0
     assign \rok_l_r_rdok$next \rok_l_r_rdok
     assign \rok_l_r_rdok$next $64
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \rok_l_r_rdok$next 1'1
     end
     sync init
       update \rok_l_r_rdok 1'1
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \rok_l_r_rdok \rok_l_r_rdok$next
   end
   process $group_17
@@ -98682,52 +99378,52 @@ module \mul0
     assign \opc_l_s_opc$next \opc_l_s_opc
     assign \opc_l_s_opc$next \cu_issue_i
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \opc_l_s_opc$next 1'0
     end
     sync init
       update \opc_l_s_opc 1'0
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \opc_l_s_opc \opc_l_s_opc$next
   end
   process $group_20
     assign \opc_l_r_opc$next \opc_l_r_opc
     assign \opc_l_r_opc$next \req_done
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \opc_l_r_opc$next 1'1
     end
     sync init
       update \opc_l_r_opc 1'1
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \opc_l_r_opc \opc_l_r_opc$next
   end
   process $group_21
     assign \src_l_s_src$next \src_l_s_src
     assign \src_l_s_src$next { \cu_issue_i \cu_issue_i \cu_issue_i }
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \src_l_s_src$next 3'000
     end
     sync init
       update \src_l_s_src 3'000
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \src_l_s_src \src_l_s_src$next
   end
   process $group_22
     assign \src_l_r_src$next \src_l_r_src
     assign \src_l_r_src$next \reset_r
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \src_l_r_src$next 3'111
     end
     sync init
       update \src_l_r_src 3'111
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \src_l_r_src \src_l_r_src$next
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:255"
@@ -98871,15 +99567,25 @@ module \mul0
   wire width 1 \oper_r__invert_a
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
   wire width 1 \oper_r__zero_a
+  attribute \enum_base_type "CryIn"
+  attribute \enum_value_00 "ZERO"
+  attribute \enum_value_01 "ONE"
+  attribute \enum_value_10 "CA"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 2 \oper_r__input_carry
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
   wire width 1 \oper_r__invert_out
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
   wire width 1 \oper_r__write_cr0
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \oper_r__output_carry
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
   wire width 1 \oper_r__is_32bit
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
   wire width 1 \oper_r__is_signed
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 4 \oper_r__data_len
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
   wire width 32 \oper_r__insn
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
   wire width 7 \oper_l__insn_type
@@ -98922,6 +99628,10 @@ module \mul0
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
   wire width 1 \oper_l__zero_a$next
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+  wire width 2 \oper_l__input_carry
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+  wire width 2 \oper_l__input_carry$next
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
   wire width 1 \oper_l__invert_out
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
   wire width 1 \oper_l__invert_out$next
@@ -98930,6 +99640,10 @@ module \mul0
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
   wire width 1 \oper_l__write_cr0$next
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+  wire width 1 \oper_l__output_carry
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+  wire width 1 \oper_l__output_carry$next
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
   wire width 1 \oper_l__is_32bit
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
   wire width 1 \oper_l__is_32bit$next
@@ -98938,16 +99652,20 @@ module \mul0
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
   wire width 1 \oper_l__is_signed$next
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+  wire width 4 \oper_l__data_len
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+  wire width 4 \oper_l__data_len$next
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
   wire width 32 \oper_l__insn
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
   wire width 32 \oper_l__insn$next
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
-  wire width 125 $70
+  wire width 132 $70
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
   cell $mux $71
-    parameter \WIDTH 125
-    connect \A { \oper_l__insn \oper_l__is_signed \oper_l__is_32bit \oper_l__write_cr0 \oper_l__invert_out \oper_l__zero_a \oper_l__invert_a { \oper_l__oe__oe_ok \oper_l__oe__oe } { \oper_l__rc__rc_ok \oper_l__rc__rc } { \oper_l__imm_data__imm_ok \oper_l__imm_data__imm } \oper_l__fn_unit \oper_l__insn_type }
-    connect \B { \oper_i_alu_mul0__insn \oper_i_alu_mul0__is_signed \oper_i_alu_mul0__is_32bit \oper_i_alu_mul0__write_cr0 \oper_i_alu_mul0__invert_out \oper_i_alu_mul0__zero_a \oper_i_alu_mul0__invert_a { \oper_i_alu_mul0__oe__oe_ok \oper_i_alu_mul0__oe__oe } { \oper_i_alu_mul0__rc__rc_ok \oper_i_alu_mul0__rc__rc } { \oper_i_alu_mul0__imm_data__imm_ok \oper_i_alu_mul0__imm_data__imm } \oper_i_alu_mul0__fn_unit \oper_i_alu_mul0__insn_type }
+    parameter \WIDTH 132
+    connect \A { \oper_l__insn \oper_l__data_len \oper_l__is_signed \oper_l__is_32bit \oper_l__output_carry \oper_l__write_cr0 \oper_l__invert_out \oper_l__input_carry \oper_l__zero_a \oper_l__invert_a { \oper_l__oe__oe_ok \oper_l__oe__oe } { \oper_l__rc__rc_ok \oper_l__rc__rc } { \oper_l__imm_data__imm_ok \oper_l__imm_data__imm } \oper_l__fn_unit \oper_l__insn_type }
+    connect \B { \oper_i_alu_div0__insn \oper_i_alu_div0__data_len \oper_i_alu_div0__is_signed \oper_i_alu_div0__is_32bit \oper_i_alu_div0__output_carry \oper_i_alu_div0__write_cr0 \oper_i_alu_div0__invert_out \oper_i_alu_div0__input_carry \oper_i_alu_div0__zero_a \oper_i_alu_div0__invert_a { \oper_i_alu_div0__oe__oe_ok \oper_i_alu_div0__oe__oe } { \oper_i_alu_div0__rc__rc_ok \oper_i_alu_div0__rc__rc } { \oper_i_alu_div0__imm_data__imm_ok \oper_i_alu_div0__imm_data__imm } \oper_i_alu_div0__fn_unit \oper_i_alu_div0__insn_type }
     connect \S \cu_issue_i
     connect \Y $70
   end
@@ -98962,15 +99680,18 @@ module \mul0
     assign \oper_r__oe__oe_ok 1'0
     assign \oper_r__invert_a 1'0
     assign \oper_r__zero_a 1'0
+    assign \oper_r__input_carry 2'00
     assign \oper_r__invert_out 1'0
     assign \oper_r__write_cr0 1'0
+    assign \oper_r__output_carry 1'0
     assign \oper_r__is_32bit 1'0
     assign \oper_r__is_signed 1'0
+    assign \oper_r__data_len 4'0000
     assign \oper_r__insn 32'00000000000000000000000000000000
-    assign { \oper_r__insn \oper_r__is_signed \oper_r__is_32bit \oper_r__write_cr0 \oper_r__invert_out \oper_r__zero_a \oper_r__invert_a { \oper_r__oe__oe_ok \oper_r__oe__oe } { \oper_r__rc__rc_ok \oper_r__rc__rc } { \oper_r__imm_data__imm_ok \oper_r__imm_data__imm } \oper_r__fn_unit \oper_r__insn_type } $70
+    assign { \oper_r__insn \oper_r__data_len \oper_r__is_signed \oper_r__is_32bit \oper_r__output_carry \oper_r__write_cr0 \oper_r__invert_out \oper_r__input_carry \oper_r__zero_a \oper_r__invert_a { \oper_r__oe__oe_ok \oper_r__oe__oe } { \oper_r__rc__rc_ok \oper_r__rc__rc } { \oper_r__imm_data__imm_ok \oper_r__imm_data__imm } \oper_r__fn_unit \oper_r__insn_type } $70
     sync init
   end
-  process $group_40
+  process $group_43
     assign \oper_l__insn_type$next \oper_l__insn_type
     assign \oper_l__fn_unit$next \oper_l__fn_unit
     assign \oper_l__imm_data__imm$next \oper_l__imm_data__imm
@@ -98981,19 +99702,22 @@ module \mul0
     assign \oper_l__oe__oe_ok$next \oper_l__oe__oe_ok
     assign \oper_l__invert_a$next \oper_l__invert_a
     assign \oper_l__zero_a$next \oper_l__zero_a
+    assign \oper_l__input_carry$next \oper_l__input_carry
     assign \oper_l__invert_out$next \oper_l__invert_out
     assign \oper_l__write_cr0$next \oper_l__write_cr0
+    assign \oper_l__output_carry$next \oper_l__output_carry
     assign \oper_l__is_32bit$next \oper_l__is_32bit
     assign \oper_l__is_signed$next \oper_l__is_signed
+    assign \oper_l__data_len$next \oper_l__data_len
     assign \oper_l__insn$next \oper_l__insn
     attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
     switch { \cu_issue_i }
       attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
       case 1'1
-        assign { \oper_l__insn$next \oper_l__is_signed$next \oper_l__is_32bit$next \oper_l__write_cr0$next \oper_l__invert_out$next \oper_l__zero_a$next \oper_l__invert_a$next { \oper_l__oe__oe_ok$next \oper_l__oe__oe$next } { \oper_l__rc__rc_ok$next \oper_l__rc__rc$next } { \oper_l__imm_data__imm_ok$next \oper_l__imm_data__imm$next } \oper_l__fn_unit$next \oper_l__insn_type$next } { \oper_i_alu_mul0__insn \oper_i_alu_mul0__is_signed \oper_i_alu_mul0__is_32bit \oper_i_alu_mul0__write_cr0 \oper_i_alu_mul0__invert_out \oper_i_alu_mul0__zero_a \oper_i_alu_mul0__invert_a { \oper_i_alu_mul0__oe__oe_ok \oper_i_alu_mul0__oe__oe } { \oper_i_alu_mul0__rc__rc_ok \oper_i_alu_mul0__rc__rc } { \oper_i_alu_mul0__imm_data__imm_ok \oper_i_alu_mul0__imm_data__imm } \oper_i_alu_mul0__fn_unit \oper_i_alu_mul0__insn_type }
+        assign { \oper_l__insn$next \oper_l__data_len$next \oper_l__is_signed$next \oper_l__is_32bit$next \oper_l__output_carry$next \oper_l__write_cr0$next \oper_l__invert_out$next \oper_l__input_carry$next \oper_l__zero_a$next \oper_l__invert_a$next { \oper_l__oe__oe_ok$next \oper_l__oe__oe$next } { \oper_l__rc__rc_ok$next \oper_l__rc__rc$next } { \oper_l__imm_data__imm_ok$next \oper_l__imm_data__imm$next } \oper_l__fn_unit$next \oper_l__insn_type$next } { \oper_i_alu_div0__insn \oper_i_alu_div0__data_len \oper_i_alu_div0__is_signed \oper_i_alu_div0__is_32bit \oper_i_alu_div0__output_carry \oper_i_alu_div0__write_cr0 \oper_i_alu_div0__invert_out \oper_i_alu_div0__input_carry \oper_i_alu_div0__zero_a \oper_i_alu_div0__invert_a { \oper_i_alu_div0__oe__oe_ok \oper_i_alu_div0__oe__oe } { \oper_i_alu_div0__rc__rc_ok \oper_i_alu_div0__rc__rc } { \oper_i_alu_div0__imm_data__imm_ok \oper_i_alu_div0__imm_data__imm } \oper_i_alu_div0__fn_unit \oper_i_alu_div0__insn_type }
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \oper_l__imm_data__imm$next 64'0000000000000000000000000000000000000000000000000000000000000000
         assign \oper_l__imm_data__imm_ok$next 1'0
@@ -99013,12 +99737,15 @@ module \mul0
       update \oper_l__oe__oe_ok 1'0
       update \oper_l__invert_a 1'0
       update \oper_l__zero_a 1'0
+      update \oper_l__input_carry 2'00
       update \oper_l__invert_out 1'0
       update \oper_l__write_cr0 1'0
+      update \oper_l__output_carry 1'0
       update \oper_l__is_32bit 1'0
       update \oper_l__is_signed 1'0
+      update \oper_l__data_len 4'0000
       update \oper_l__insn 32'00000000000000000000000000000000
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \oper_l__insn_type \oper_l__insn_type$next
       update \oper_l__fn_unit \oper_l__fn_unit$next
       update \oper_l__imm_data__imm \oper_l__imm_data__imm$next
@@ -99029,10 +99756,13 @@ module \mul0
       update \oper_l__oe__oe_ok \oper_l__oe__oe_ok$next
       update \oper_l__invert_a \oper_l__invert_a$next
       update \oper_l__zero_a \oper_l__zero_a$next
+      update \oper_l__input_carry \oper_l__input_carry$next
       update \oper_l__invert_out \oper_l__invert_out$next
       update \oper_l__write_cr0 \oper_l__write_cr0$next
+      update \oper_l__output_carry \oper_l__output_carry$next
       update \oper_l__is_32bit \oper_l__is_32bit$next
       update \oper_l__is_signed \oper_l__is_signed$next
+      update \oper_l__data_len \oper_l__data_len$next
       update \oper_l__insn \oper_l__insn$next
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
@@ -99063,11 +99793,11 @@ module \mul0
   cell $mux $75
     parameter \WIDTH 65
     connect \A { \data_r0_l__o_ok \data_r0_l__o }
-    connect \B { \o_ok \alu_mul0_o }
+    connect \B { \o_ok \alu_div0_o }
     connect \S $73
     connect \Y $72
   end
-  process $group_55
+  process $group_61
     assign \data_r0__o 64'0000000000000000000000000000000000000000000000000000000000000000
     assign \data_r0__o_ok 1'0
     assign { \data_r0__o_ok \data_r0__o } $72
@@ -99083,24 +99813,24 @@ module \mul0
     connect \A \alu_pulsem
     connect \Y $76
   end
-  process $group_57
+  process $group_63
     assign \data_r0_l__o$next \data_r0_l__o
     assign \data_r0_l__o_ok$next \data_r0_l__o_ok
     attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
     switch { $76 }
       attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
       case 1'1
-        assign { \data_r0_l__o_ok$next \data_r0_l__o$next } { \o_ok \alu_mul0_o }
+        assign { \data_r0_l__o_ok$next \data_r0_l__o$next } { \o_ok \alu_div0_o }
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \data_r0_l__o_ok$next 1'0
     end
     sync init
       update \data_r0_l__o 64'0000000000000000000000000000000000000000000000000000000000000000
       update \data_r0_l__o_ok 1'0
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \data_r0_l__o \data_r0_l__o$next
       update \data_r0_l__o_ok \data_r0_l__o_ok$next
   end
@@ -99132,11 +99862,11 @@ module \mul0
   cell $mux $81
     parameter \WIDTH 5
     connect \A { \data_r1_l__cr_a_ok \data_r1_l__cr_a }
-    connect \B { \cr_a_ok \alu_mul0_cr_a }
+    connect \B { \cr_a_ok \alu_div0_cr_a }
     connect \S $79
     connect \Y $78
   end
-  process $group_59
+  process $group_65
     assign \data_r1__cr_a 4'0000
     assign \data_r1__cr_a_ok 1'0
     assign { \data_r1__cr_a_ok \data_r1__cr_a } $78
@@ -99152,24 +99882,24 @@ module \mul0
     connect \A \alu_pulsem
     connect \Y $82
   end
-  process $group_61
+  process $group_67
     assign \data_r1_l__cr_a$next \data_r1_l__cr_a
     assign \data_r1_l__cr_a_ok$next \data_r1_l__cr_a_ok
     attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
     switch { $82 }
       attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
       case 1'1
-        assign { \data_r1_l__cr_a_ok$next \data_r1_l__cr_a$next } { \cr_a_ok \alu_mul0_cr_a }
+        assign { \data_r1_l__cr_a_ok$next \data_r1_l__cr_a$next } { \cr_a_ok \alu_div0_cr_a }
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \data_r1_l__cr_a_ok$next 1'0
     end
     sync init
       update \data_r1_l__cr_a 4'0000
       update \data_r1_l__cr_a_ok 1'0
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \data_r1_l__cr_a \data_r1_l__cr_a$next
       update \data_r1_l__cr_a_ok \data_r1_l__cr_a_ok$next
   end
@@ -99201,11 +99931,11 @@ module \mul0
   cell $mux $87
     parameter \WIDTH 3
     connect \A { \data_r2_l__xer_ov_ok \data_r2_l__xer_ov }
-    connect \B { \xer_ov_ok \alu_mul0_xer_ov }
+    connect \B { \xer_ov_ok \alu_div0_xer_ov }
     connect \S $85
     connect \Y $84
   end
-  process $group_63
+  process $group_69
     assign \data_r2__xer_ov 2'00
     assign \data_r2__xer_ov_ok 1'0
     assign { \data_r2__xer_ov_ok \data_r2__xer_ov } $84
@@ -99221,24 +99951,24 @@ module \mul0
     connect \A \alu_pulsem
     connect \Y $88
   end
-  process $group_65
+  process $group_71
     assign \data_r2_l__xer_ov$next \data_r2_l__xer_ov
     assign \data_r2_l__xer_ov_ok$next \data_r2_l__xer_ov_ok
     attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
     switch { $88 }
       attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
       case 1'1
-        assign { \data_r2_l__xer_ov_ok$next \data_r2_l__xer_ov$next } { \xer_ov_ok \alu_mul0_xer_ov }
+        assign { \data_r2_l__xer_ov_ok$next \data_r2_l__xer_ov$next } { \xer_ov_ok \alu_div0_xer_ov }
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \data_r2_l__xer_ov_ok$next 1'0
     end
     sync init
       update \data_r2_l__xer_ov 2'00
       update \data_r2_l__xer_ov_ok 1'0
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \data_r2_l__xer_ov \data_r2_l__xer_ov$next
       update \data_r2_l__xer_ov_ok \data_r2_l__xer_ov_ok$next
   end
@@ -99270,11 +100000,11 @@ module \mul0
   cell $mux $93
     parameter \WIDTH 2
     connect \A { \data_r3_l__xer_so_ok \data_r3_l__xer_so }
-    connect \B { \xer_so_ok \alu_mul0_xer_so }
+    connect \B { \xer_so_ok \alu_div0_xer_so }
     connect \S $91
     connect \Y $90
   end
-  process $group_67
+  process $group_73
     assign \data_r3__xer_so 1'0
     assign \data_r3__xer_so_ok 1'0
     assign { \data_r3__xer_so_ok \data_r3__xer_so } $90
@@ -99290,24 +100020,24 @@ module \mul0
     connect \A \alu_pulsem
     connect \Y $94
   end
-  process $group_69
+  process $group_75
     assign \data_r3_l__xer_so$next \data_r3_l__xer_so
     assign \data_r3_l__xer_so_ok$next \data_r3_l__xer_so_ok
     attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
     switch { $94 }
       attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
       case 1'1
-        assign { \data_r3_l__xer_so_ok$next \data_r3_l__xer_so$next } { \xer_so_ok \alu_mul0_xer_so }
+        assign { \data_r3_l__xer_so_ok$next \data_r3_l__xer_so$next } { \xer_so_ok \alu_div0_xer_so }
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \data_r3_l__xer_so_ok$next 1'0
     end
     sync init
       update \data_r3_l__xer_so 1'0
       update \data_r3_l__xer_so_ok 1'0
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \data_r3_l__xer_so \data_r3_l__xer_so$next
       update \data_r3_l__xer_so_ok \data_r3_l__xer_so_ok$next
   end
@@ -99363,28 +100093,31 @@ module \mul0
     connect \B \cu_busy_o
     connect \Y $102
   end
-  process $group_71
+  process $group_77
     assign \cu_wrmask_o 4'0000
     assign \cu_wrmask_o { $102 $100 $98 $96 }
     sync init
   end
-  process $group_72
-    assign \alu_mul0_mul_op__insn_type 7'0000000
-    assign \alu_mul0_mul_op__fn_unit 11'00000000000
-    assign \alu_mul0_mul_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \alu_mul0_mul_op__imm_data__imm_ok 1'0
-    assign \alu_mul0_mul_op__rc__rc 1'0
-    assign \alu_mul0_mul_op__rc__rc_ok 1'0
-    assign \alu_mul0_mul_op__oe__oe 1'0
-    assign \alu_mul0_mul_op__oe__oe_ok 1'0
-    assign \alu_mul0_mul_op__invert_a 1'0
-    assign \alu_mul0_mul_op__zero_a 1'0
-    assign \alu_mul0_mul_op__invert_out 1'0
-    assign \alu_mul0_mul_op__write_cr0 1'0
-    assign \alu_mul0_mul_op__is_32bit 1'0
-    assign \alu_mul0_mul_op__is_signed 1'0
-    assign \alu_mul0_mul_op__insn 32'00000000000000000000000000000000
-    assign { \alu_mul0_mul_op__insn \alu_mul0_mul_op__is_signed \alu_mul0_mul_op__is_32bit \alu_mul0_mul_op__write_cr0 \alu_mul0_mul_op__invert_out \alu_mul0_mul_op__zero_a \alu_mul0_mul_op__invert_a { \alu_mul0_mul_op__oe__oe_ok \alu_mul0_mul_op__oe__oe } { \alu_mul0_mul_op__rc__rc_ok \alu_mul0_mul_op__rc__rc } { \alu_mul0_mul_op__imm_data__imm_ok \alu_mul0_mul_op__imm_data__imm } \alu_mul0_mul_op__fn_unit \alu_mul0_mul_op__insn_type } { \oper_r__insn \oper_r__is_signed \oper_r__is_32bit \oper_r__write_cr0 \oper_r__invert_out \oper_r__zero_a \oper_r__invert_a { \oper_r__oe__oe_ok \oper_r__oe__oe } { \oper_r__rc__rc_ok \oper_r__rc__rc } { \oper_r__imm_data__imm_ok \oper_r__imm_data__imm } \oper_r__fn_unit \oper_r__insn_type }
+  process $group_78
+    assign \alu_div0_logical_op__insn_type 7'0000000
+    assign \alu_div0_logical_op__fn_unit 11'00000000000
+    assign \alu_div0_logical_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \alu_div0_logical_op__imm_data__imm_ok 1'0
+    assign \alu_div0_logical_op__rc__rc 1'0
+    assign \alu_div0_logical_op__rc__rc_ok 1'0
+    assign \alu_div0_logical_op__oe__oe 1'0
+    assign \alu_div0_logical_op__oe__oe_ok 1'0
+    assign \alu_div0_logical_op__invert_a 1'0
+    assign \alu_div0_logical_op__zero_a 1'0
+    assign \alu_div0_logical_op__input_carry 2'00
+    assign \alu_div0_logical_op__invert_out 1'0
+    assign \alu_div0_logical_op__write_cr0 1'0
+    assign \alu_div0_logical_op__output_carry 1'0
+    assign \alu_div0_logical_op__is_32bit 1'0
+    assign \alu_div0_logical_op__is_signed 1'0
+    assign \alu_div0_logical_op__data_len 4'0000
+    assign \alu_div0_logical_op__insn 32'00000000000000000000000000000000
+    assign { \alu_div0_logical_op__insn \alu_div0_logical_op__data_len \alu_div0_logical_op__is_signed \alu_div0_logical_op__is_32bit \alu_div0_logical_op__output_carry \alu_div0_logical_op__write_cr0 \alu_div0_logical_op__invert_out \alu_div0_logical_op__input_carry \alu_div0_logical_op__zero_a \alu_div0_logical_op__invert_a { \alu_div0_logical_op__oe__oe_ok \alu_div0_logical_op__oe__oe } { \alu_div0_logical_op__rc__rc_ok \alu_div0_logical_op__rc__rc } { \alu_div0_logical_op__imm_data__imm_ok \alu_div0_logical_op__imm_data__imm } \alu_div0_logical_op__fn_unit \alu_div0_logical_op__insn_type } { \oper_r__insn \oper_r__data_len \oper_r__is_signed \oper_r__is_32bit \oper_r__output_carry \oper_r__write_cr0 \oper_r__invert_out \oper_r__input_carry \oper_r__zero_a \oper_r__invert_a { \oper_r__oe__oe_ok \oper_r__oe__oe } { \oper_r__rc__rc_ok \oper_r__rc__rc } { \oper_r__imm_data__imm_ok \oper_r__imm_data__imm } \oper_r__fn_unit \oper_r__insn_type }
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:166"
@@ -99399,7 +100132,7 @@ module \mul0
     connect \S \oper_r__zero_a
     connect \Y $104
   end
-  process $group_87
+  process $group_96
     assign \src_sel 1'0
     assign \src_sel $104
     sync init
@@ -99416,7 +100149,7 @@ module \mul0
     connect \S \oper_r__zero_a
     connect \Y $106
   end
-  process $group_88
+  process $group_97
     assign \src_or_imm 64'0000000000000000000000000000000000000000000000000000000000000000
     assign \src_or_imm $106
     sync init
@@ -99433,7 +100166,7 @@ module \mul0
     connect \S \oper_r__imm_data__imm_ok
     connect \Y $109
   end
-  process $group_89
+  process $group_98
     assign \src_sel$108 1'0
     assign \src_sel$108 $109
     sync init
@@ -99450,7 +100183,7 @@ module \mul0
     connect \S \oper_r__imm_data__imm_ok
     connect \Y $112
   end
-  process $group_90
+  process $group_99
     assign \src_or_imm$111 64'0000000000000000000000000000000000000000000000000000000000000000
     assign \src_or_imm$111 $112
     sync init
@@ -99469,12 +100202,12 @@ module \mul0
     connect \S \src_sel
     connect \Y $114
   end
-  process $group_91
-    assign \alu_mul0_ra 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \alu_mul0_ra $114
+  process $group_100
+    assign \alu_div0_ra 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \alu_div0_ra $114
     sync init
   end
-  process $group_92
+  process $group_101
     assign \src_r0$next \src_r0
     attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
     switch { \src_sel }
@@ -99484,7 +100217,7 @@ module \mul0
     end
     sync init
       update \src_r0 64'0000000000000000000000000000000000000000000000000000000000000000
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \src_r0 \src_r0$next
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
@@ -99501,12 +100234,12 @@ module \mul0
     connect \S \src_sel$108
     connect \Y $116
   end
-  process $group_93
-    assign \alu_mul0_rb 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \alu_mul0_rb $116
+  process $group_102
+    assign \alu_div0_rb 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \alu_div0_rb $116
     sync init
   end
-  process $group_94
+  process $group_103
     assign \src_r1$next \src_r1
     attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
     switch { \src_sel$108 }
@@ -99516,7 +100249,7 @@ module \mul0
     end
     sync init
       update \src_r1 64'0000000000000000000000000000000000000000000000000000000000000000
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \src_r1 \src_r1$next
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
@@ -99533,12 +100266,12 @@ module \mul0
     connect \S \src_l_q_src [2]
     connect \Y $118
   end
-  process $group_95
-    assign \alu_mul0_xer_so$1 1'0
-    assign \alu_mul0_xer_so$1 $118
+  process $group_104
+    assign \alu_div0_xer_so$1 1'0
+    assign \alu_div0_xer_so$1 $118
     sync init
   end
-  process $group_96
+  process $group_105
     assign \src_r2$next \src_r2
     attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
     switch { \src_l_q_src [2] }
@@ -99548,12 +100281,12 @@ module \mul0
     end
     sync init
       update \src_r2 1'0
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \src_r2 \src_r2$next
   end
-  process $group_97
-    assign \alu_mul0_p_valid_i 1'0
-    assign \alu_mul0_p_valid_i \alui_l_q_alui
+  process $group_106
+    assign \alu_div0_p_valid_i 1'0
+    assign \alu_div0_p_valid_i \alui_l_q_alui
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:329"
@@ -99565,31 +100298,31 @@ module \mul0
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \alu_mul0_p_ready_o
+    connect \A \alu_div0_p_ready_o
     connect \B \alui_l_q_alui
     connect \Y $120
   end
-  process $group_98
+  process $group_107
     assign \alui_l_r_alui$next \alui_l_r_alui
     assign \alui_l_r_alui$next $120
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \alui_l_r_alui$next 1'1
     end
     sync init
       update \alui_l_r_alui 1'1
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \alui_l_r_alui \alui_l_r_alui$next
   end
-  process $group_99
+  process $group_108
     assign \alui_l_s_alui 1'0
     assign \alui_l_s_alui \all_rd_pulse
     sync init
   end
-  process $group_100
-    assign \alu_mul0_n_ready_i 1'0
-    assign \alu_mul0_n_ready_i \alu_l_q_alu
+  process $group_109
+    assign \alu_div0_n_ready_i 1'0
+    assign \alu_div0_n_ready_i \alu_l_q_alu
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:336"
@@ -99601,29 +100334,29 @@ module \mul0
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \alu_mul0_n_valid_o
+    connect \A \alu_div0_n_valid_o
     connect \B \alu_l_q_alu
     connect \Y $122
   end
-  process $group_101
+  process $group_110
     assign \alu_l_r_alu$next \alu_l_r_alu
     assign \alu_l_r_alu$next $122
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \alu_l_r_alu$next 1'1
     end
     sync init
       update \alu_l_r_alu 1'1
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \alu_l_r_alu \alu_l_r_alu$next
   end
-  process $group_102
+  process $group_111
     assign \alu_l_s_alu 1'0
     assign \alu_l_s_alu \all_rd_pulse
     sync init
   end
-  process $group_103
+  process $group_112
     assign \cu_busy_o 1'0
     assign \cu_busy_o \opc_l_q_opc
     sync init
@@ -99697,7 +100430,7 @@ module \mul0
     connect \B $132
     connect \Y $134
   end
-  process $group_104
+  process $group_113
     assign \cu_rd__rel_o 3'000
     assign \cu_rd__rel_o $134
     sync init
@@ -99782,7 +100515,7 @@ module \mul0
     connect \B \cu_wrmask_o
     connect \Y $146
   end
-  process $group_105
+  process $group_114
     assign \cu_wr__rel_o 4'0000
     assign \cu_wr__rel_o $146
     sync init
@@ -99800,7 +100533,7 @@ module \mul0
     connect \B \cu_busy_o
     connect \Y $148
   end
-  process $group_106
+  process $group_115
     assign \dest1_o 64'0000000000000000000000000000000000000000000000000000000000000000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
     switch { $148 }
@@ -99823,7 +100556,7 @@ module \mul0
     connect \B \cu_busy_o
     connect \Y $150
   end
-  process $group_107
+  process $group_116
     assign \dest2_o 4'0000
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
     switch { $150 }
@@ -99846,7 +100579,7 @@ module \mul0
     connect \B \cu_busy_o
     connect \Y $152
   end
-  process $group_108
+  process $group_117
     assign \dest3_o 2'00
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
     switch { $152 }
@@ -99869,7 +100602,7 @@ module \mul0
     connect \B \cu_busy_o
     connect \Y $154
   end
-  process $group_109
+  process $group_118
     assign \dest4_o 1'0
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
     switch { $154 }
@@ -99883,7 +100616,7 @@ module \mul0
   connect \cu_shadown_i 1'1
 end
 attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.p"
+attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.p"
 module \p$87
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153"
   wire width 1 input 0 \p_valid_i
@@ -99911,7 +100644,7 @@ module \p$87
   end
 end
 attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.n"
+attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.n"
 module \n$88
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
   wire width 1 input 0 \n_valid_o
@@ -99939,8 +100672,8 @@ module \n$88
   end
 end
 attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe.p"
-module \p$90
+attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe1.p"
+module \p$89
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153"
   wire width 1 input 0 \p_valid_i
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154"
@@ -99967,8 +100700,8 @@ module \p$90
   end
 end
 attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe.n"
-module \n$91
+attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe1.n"
+module \n$90
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
   wire width 1 input 0 \n_valid_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
@@ -99995,8 +100728,8 @@ module \n$91
   end
 end
 attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe.input"
-module \input$92
+attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe1.input"
+module \input$91
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
   wire width 2 input 0 \muxid
   attribute \enum_base_type "MicrOp"
@@ -100073,7 +100806,7 @@ module \input$92
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 7 input 1 \sr_op__insn_type
+  wire width 7 input 1 \mul_op__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -100087,47 +100820,41 @@ module \input$92
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 11 input 2 \sr_op__fn_unit
+  wire width 11 input 2 \mul_op__fn_unit
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 64 input 3 \sr_op__imm_data__imm
+  wire width 64 input 3 \mul_op__imm_data__imm
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 4 \sr_op__imm_data__imm_ok
+  wire width 1 input 4 \mul_op__imm_data__imm_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 5 \sr_op__rc__rc
+  wire width 1 input 5 \mul_op__rc__rc
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 6 \sr_op__rc__rc_ok
+  wire width 1 input 6 \mul_op__rc__rc_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 7 \sr_op__oe__oe
+  wire width 1 input 7 \mul_op__oe__oe
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 8 \sr_op__oe__oe_ok
-  attribute \enum_base_type "CryIn"
-  attribute \enum_value_00 "ZERO"
-  attribute \enum_value_01 "ONE"
-  attribute \enum_value_10 "CA"
+  wire width 1 input 8 \mul_op__oe__oe_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 2 input 10 \sr_op__input_carry
+  wire width 1 input 9 \mul_op__invert_a
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 11 \sr_op__output_carry
+  wire width 1 input 10 \mul_op__zero_a
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 12 \sr_op__input_cr
+  wire width 1 input 11 \mul_op__invert_out
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 13 \sr_op__output_cr
+  wire width 1 input 12 \mul_op__write_cr0
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 14 \sr_op__is_32bit
+  wire width 1 input 13 \mul_op__is_32bit
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 15 \sr_op__is_signed
+  wire width 1 input 14 \mul_op__is_signed
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 32 input 16 \sr_op__insn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
-  wire width 64 input 17 \ra
+  wire width 32 input 15 \mul_op__insn
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
-  wire width 64 input 18 \rb
+  wire width 64 input 16 \ra
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
-  wire width 64 input 19 \rc
+  wire width 64 input 17 \rb
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
-  wire width 2 input 20 \xer_ca
+  wire width 1 input 18 \xer_so
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
-  wire width 2 output 21 \muxid$1
+  wire width 2 output 19 \muxid$1
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
   attribute \enum_value_0000001 "OP_NOP"
@@ -100202,7 +100929,7 @@ module \input$92
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 7 output 22 \sr_op__insn_type$2
+  wire width 7 output 20 \mul_op__insn_type$2
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -100216,50 +100943,62 @@ module \input$92
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 11 output 23 \sr_op__fn_unit$3
+  wire width 11 output 21 \mul_op__fn_unit$3
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 64 output 24 \sr_op__imm_data__imm$4
+  wire width 64 output 22 \mul_op__imm_data__imm$4
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 25 \sr_op__imm_data__imm_ok$5
+  wire width 1 output 23 \mul_op__imm_data__imm_ok$5
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 26 \sr_op__rc__rc$6
+  wire width 1 output 24 \mul_op__rc__rc$6
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 27 \sr_op__rc__rc_ok$7
+  wire width 1 output 25 \mul_op__rc__rc_ok$7
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 28 \sr_op__oe__oe$8
+  wire width 1 output 26 \mul_op__oe__oe$8
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 29 \sr_op__oe__oe_ok$9
-  attribute \enum_base_type "CryIn"
-  attribute \enum_value_00 "ZERO"
-  attribute \enum_value_01 "ONE"
-  attribute \enum_value_10 "CA"
+  wire width 1 output 27 \mul_op__oe__oe_ok$9
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 2 output 31 \sr_op__input_carry$10
+  wire width 1 output 28 \mul_op__invert_a$10
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 32 \sr_op__output_carry$11
+  wire width 1 output 29 \mul_op__zero_a$11
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 33 \sr_op__input_cr$12
+  wire width 1 output 30 \mul_op__invert_out$12
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 34 \sr_op__output_cr$13
+  wire width 1 output 31 \mul_op__write_cr0$13
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 35 \sr_op__is_32bit$14
+  wire width 1 output 32 \mul_op__is_32bit$14
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 36 \sr_op__is_signed$15
+  wire width 1 output 33 \mul_op__is_signed$15
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 32 output 37 \sr_op__insn$16
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
-  wire width 64 output 38 \ra$17
+  wire width 32 output 34 \mul_op__insn$16
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
-  wire width 64 output 39 \rb$18
+  wire width 64 output 35 \ra$17
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
-  wire width 64 output 40 \rc$19
+  wire width 64 output 36 \rb$18
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
-  wire width 2 output 41 \xer_ca$20
+  wire width 1 output 37 \xer_so$19
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20"
   wire width 64 \a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:24"
+  wire width 64 $20
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:24"
+  cell $not $21
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 64
+    parameter \Y_WIDTH 64
+    connect \A \ra
+    connect \Y $20
+  end
   process $group_0
     assign \a 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \a \ra
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:23"
+    switch { \mul_op__invert_a }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:23"
+      case 1'1
+        assign \a $20
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:25"
+      case
+        assign \a \ra
+    end
     sync init
   end
   process $group_1
@@ -100268,21 +101007,12 @@ module \input$92
     sync init
   end
   process $group_2
-    assign \xer_ca$20 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:36"
-    switch \sr_op__input_carry
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:37"
-      attribute \nmigen.decoding "ZERO/0"
-      case 2'00
-        assign \xer_ca$20 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:39"
-      attribute \nmigen.decoding "ONE/1"
-      case 2'01
-        assign \xer_ca$20 2'11
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:41"
-      attribute \nmigen.decoding "CA/2"
-      case 2'10
-        assign \xer_ca$20 \xer_ca
+    assign \xer_so$19 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:47"
+    switch { \mul_op__oe__oe_ok }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:47"
+      case 1'1
+        assign \xer_so$19 \xer_so
     end
     sync init
   end
@@ -100292,833 +101022,583 @@ module \input$92
     sync init
   end
   process $group_4
-    assign \sr_op__insn_type$2 7'0000000
-    assign \sr_op__fn_unit$3 11'00000000000
-    assign \sr_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \sr_op__imm_data__imm_ok$5 1'0
-    assign \sr_op__rc__rc$6 1'0
-    assign \sr_op__rc__rc_ok$7 1'0
-    assign \sr_op__oe__oe$8 1'0
-    assign \sr_op__oe__oe_ok$9 1'0
-    assign { } 0'0
-    assign \sr_op__input_carry$10 2'00
-    assign \sr_op__output_carry$11 1'0
-    assign \sr_op__input_cr$12 1'0
-    assign \sr_op__output_cr$13 1'0
-    assign \sr_op__is_32bit$14 1'0
-    assign \sr_op__is_signed$15 1'0
-    assign \sr_op__insn$16 32'00000000000000000000000000000000
-    assign { \sr_op__insn$16 \sr_op__is_signed$15 \sr_op__is_32bit$14 \sr_op__output_cr$13 \sr_op__input_cr$12 \sr_op__output_carry$11 \sr_op__input_carry$10 { } { \sr_op__oe__oe_ok$9 \sr_op__oe__oe$8 } { \sr_op__rc__rc_ok$7 \sr_op__rc__rc$6 } { \sr_op__imm_data__imm_ok$5 \sr_op__imm_data__imm$4 } \sr_op__fn_unit$3 \sr_op__insn_type$2 } { \sr_op__insn \sr_op__is_signed \sr_op__is_32bit \sr_op__output_cr \sr_op__input_cr \sr_op__output_carry \sr_op__input_carry { } { \sr_op__oe__oe_ok \sr_op__oe__oe } { \sr_op__rc__rc_ok \sr_op__rc__rc } { \sr_op__imm_data__imm_ok \sr_op__imm_data__imm } \sr_op__fn_unit \sr_op__insn_type }
+    assign \mul_op__insn_type$2 7'0000000
+    assign \mul_op__fn_unit$3 11'00000000000
+    assign \mul_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \mul_op__imm_data__imm_ok$5 1'0
+    assign \mul_op__rc__rc$6 1'0
+    assign \mul_op__rc__rc_ok$7 1'0
+    assign \mul_op__oe__oe$8 1'0
+    assign \mul_op__oe__oe_ok$9 1'0
+    assign \mul_op__invert_a$10 1'0
+    assign \mul_op__zero_a$11 1'0
+    assign \mul_op__invert_out$12 1'0
+    assign \mul_op__write_cr0$13 1'0
+    assign \mul_op__is_32bit$14 1'0
+    assign \mul_op__is_signed$15 1'0
+    assign \mul_op__insn$16 32'00000000000000000000000000000000
+    assign { \mul_op__insn$16 \mul_op__is_signed$15 \mul_op__is_32bit$14 \mul_op__write_cr0$13 \mul_op__invert_out$12 \mul_op__zero_a$11 \mul_op__invert_a$10 { \mul_op__oe__oe_ok$9 \mul_op__oe__oe$8 } { \mul_op__rc__rc_ok$7 \mul_op__rc__rc$6 } { \mul_op__imm_data__imm_ok$5 \mul_op__imm_data__imm$4 } \mul_op__fn_unit$3 \mul_op__insn_type$2 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__invert_out \mul_op__zero_a \mul_op__invert_a { \mul_op__oe__oe_ok \mul_op__oe__oe } { \mul_op__rc__rc_ok \mul_op__rc__rc } { \mul_op__imm_data__imm_ok \mul_op__imm_data__imm } \mul_op__fn_unit \mul_op__insn_type }
     sync init
   end
-  process $group_20
+  process $group_19
     assign \rb$18 64'0000000000000000000000000000000000000000000000000000000000000000
     assign \rb$18 \rb
     sync init
   end
-  process $group_21
-    assign \rc$19 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \rc$19 \rc
-    sync init
-  end
 end
 attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe.main.rotator.rotl"
-module \rotl
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:8"
-  wire width 64 input 0 \a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:9"
-  wire width 6 input 1 \b
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:11"
-  wire width 64 output 2 \o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:19"
-  wire width 64 $1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:18"
-  wire width 8 $2
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:18"
-  cell $sub $3
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 7
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 6
-    parameter \Y_WIDTH 8
-    connect \A 7'1000000
-    connect \B \b
-    connect \Y $2
+attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe1.mul1"
+module \mul1
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
+  wire width 2 input 0 \muxid
+  attribute \enum_base_type "MicrOp"
+  attribute \enum_value_0000000 "OP_ILLEGAL"
+  attribute \enum_value_0000001 "OP_NOP"
+  attribute \enum_value_0000010 "OP_ADD"
+  attribute \enum_value_0000011 "OP_ADDPCIS"
+  attribute \enum_value_0000100 "OP_AND"
+  attribute \enum_value_0000101 "OP_ATTN"
+  attribute \enum_value_0000110 "OP_B"
+  attribute \enum_value_0000111 "OP_BC"
+  attribute \enum_value_0001000 "OP_BCREG"
+  attribute \enum_value_0001001 "OP_BPERM"
+  attribute \enum_value_0001010 "OP_CMP"
+  attribute \enum_value_0001011 "OP_CMPB"
+  attribute \enum_value_0001100 "OP_CMPEQB"
+  attribute \enum_value_0001101 "OP_CMPRB"
+  attribute \enum_value_0001110 "OP_CNTZ"
+  attribute \enum_value_0001111 "OP_CRAND"
+  attribute \enum_value_0010000 "OP_CRANDC"
+  attribute \enum_value_0010001 "OP_CREQV"
+  attribute \enum_value_0010010 "OP_CRNAND"
+  attribute \enum_value_0010011 "OP_CRNOR"
+  attribute \enum_value_0010100 "OP_CROR"
+  attribute \enum_value_0010101 "OP_CRORC"
+  attribute \enum_value_0010110 "OP_CRXOR"
+  attribute \enum_value_0010111 "OP_DARN"
+  attribute \enum_value_0011000 "OP_DCBF"
+  attribute \enum_value_0011001 "OP_DCBST"
+  attribute \enum_value_0011010 "OP_DCBT"
+  attribute \enum_value_0011011 "OP_DCBTST"
+  attribute \enum_value_0011100 "OP_DCBZ"
+  attribute \enum_value_0011101 "OP_DIV"
+  attribute \enum_value_0011110 "OP_DIVE"
+  attribute \enum_value_0011111 "OP_EXTS"
+  attribute \enum_value_0100000 "OP_EXTSWSLI"
+  attribute \enum_value_0100001 "OP_ICBI"
+  attribute \enum_value_0100010 "OP_ICBT"
+  attribute \enum_value_0100011 "OP_ISEL"
+  attribute \enum_value_0100100 "OP_ISYNC"
+  attribute \enum_value_0100101 "OP_LOAD"
+  attribute \enum_value_0100110 "OP_STORE"
+  attribute \enum_value_0100111 "OP_MADDHD"
+  attribute \enum_value_0101000 "OP_MADDHDU"
+  attribute \enum_value_0101001 "OP_MADDLD"
+  attribute \enum_value_0101010 "OP_MCRF"
+  attribute \enum_value_0101011 "OP_MCRXR"
+  attribute \enum_value_0101100 "OP_MCRXRX"
+  attribute \enum_value_0101101 "OP_MFCR"
+  attribute \enum_value_0101110 "OP_MFSPR"
+  attribute \enum_value_0101111 "OP_MOD"
+  attribute \enum_value_0110000 "OP_MTCRF"
+  attribute \enum_value_0110001 "OP_MTSPR"
+  attribute \enum_value_0110010 "OP_MUL_L64"
+  attribute \enum_value_0110011 "OP_MUL_H64"
+  attribute \enum_value_0110100 "OP_MUL_H32"
+  attribute \enum_value_0110101 "OP_OR"
+  attribute \enum_value_0110110 "OP_POPCNT"
+  attribute \enum_value_0110111 "OP_PRTY"
+  attribute \enum_value_0111000 "OP_RLC"
+  attribute \enum_value_0111001 "OP_RLCL"
+  attribute \enum_value_0111010 "OP_RLCR"
+  attribute \enum_value_0111011 "OP_SETB"
+  attribute \enum_value_0111100 "OP_SHL"
+  attribute \enum_value_0111101 "OP_SHR"
+  attribute \enum_value_0111110 "OP_SYNC"
+  attribute \enum_value_0111111 "OP_TRAP"
+  attribute \enum_value_1000011 "OP_XOR"
+  attribute \enum_value_1000100 "OP_SIM_CONFIG"
+  attribute \enum_value_1000101 "OP_CROP"
+  attribute \enum_value_1000110 "OP_RFID"
+  attribute \enum_value_1000111 "OP_MFMSR"
+  attribute \enum_value_1001000 "OP_MTMSRD"
+  attribute \enum_value_1001001 "OP_SC"
+  attribute \enum_value_1001010 "OP_MTMSR"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 input 1 \mul_op__insn_type
+  attribute \enum_base_type "Function"
+  attribute \enum_value_00000000000 "NONE"
+  attribute \enum_value_00000000010 "ALU"
+  attribute \enum_value_00000000100 "LDST"
+  attribute \enum_value_00000001000 "SHIFT_ROT"
+  attribute \enum_value_00000010000 "LOGICAL"
+  attribute \enum_value_00000100000 "BRANCH"
+  attribute \enum_value_00001000000 "CR"
+  attribute \enum_value_00010000000 "TRAP"
+  attribute \enum_value_00100000000 "MUL"
+  attribute \enum_value_01000000000 "DIV"
+  attribute \enum_value_10000000000 "SPR"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 input 2 \mul_op__fn_unit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 input 3 \mul_op__imm_data__imm
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 4 \mul_op__imm_data__imm_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 5 \mul_op__rc__rc
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 6 \mul_op__rc__rc_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 7 \mul_op__oe__oe
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 8 \mul_op__oe__oe_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 9 \mul_op__invert_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 10 \mul_op__zero_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 11 \mul_op__invert_out
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 12 \mul_op__write_cr0
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 13 \mul_op__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 14 \mul_op__is_signed
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 input 15 \mul_op__insn
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
+  wire width 64 input 16 \ra
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
+  wire width 64 input 17 \rb
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
+  wire width 1 input 18 \xer_so
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
+  wire width 2 output 19 \muxid$1
+  attribute \enum_base_type "MicrOp"
+  attribute \enum_value_0000000 "OP_ILLEGAL"
+  attribute \enum_value_0000001 "OP_NOP"
+  attribute \enum_value_0000010 "OP_ADD"
+  attribute \enum_value_0000011 "OP_ADDPCIS"
+  attribute \enum_value_0000100 "OP_AND"
+  attribute \enum_value_0000101 "OP_ATTN"
+  attribute \enum_value_0000110 "OP_B"
+  attribute \enum_value_0000111 "OP_BC"
+  attribute \enum_value_0001000 "OP_BCREG"
+  attribute \enum_value_0001001 "OP_BPERM"
+  attribute \enum_value_0001010 "OP_CMP"
+  attribute \enum_value_0001011 "OP_CMPB"
+  attribute \enum_value_0001100 "OP_CMPEQB"
+  attribute \enum_value_0001101 "OP_CMPRB"
+  attribute \enum_value_0001110 "OP_CNTZ"
+  attribute \enum_value_0001111 "OP_CRAND"
+  attribute \enum_value_0010000 "OP_CRANDC"
+  attribute \enum_value_0010001 "OP_CREQV"
+  attribute \enum_value_0010010 "OP_CRNAND"
+  attribute \enum_value_0010011 "OP_CRNOR"
+  attribute \enum_value_0010100 "OP_CROR"
+  attribute \enum_value_0010101 "OP_CRORC"
+  attribute \enum_value_0010110 "OP_CRXOR"
+  attribute \enum_value_0010111 "OP_DARN"
+  attribute \enum_value_0011000 "OP_DCBF"
+  attribute \enum_value_0011001 "OP_DCBST"
+  attribute \enum_value_0011010 "OP_DCBT"
+  attribute \enum_value_0011011 "OP_DCBTST"
+  attribute \enum_value_0011100 "OP_DCBZ"
+  attribute \enum_value_0011101 "OP_DIV"
+  attribute \enum_value_0011110 "OP_DIVE"
+  attribute \enum_value_0011111 "OP_EXTS"
+  attribute \enum_value_0100000 "OP_EXTSWSLI"
+  attribute \enum_value_0100001 "OP_ICBI"
+  attribute \enum_value_0100010 "OP_ICBT"
+  attribute \enum_value_0100011 "OP_ISEL"
+  attribute \enum_value_0100100 "OP_ISYNC"
+  attribute \enum_value_0100101 "OP_LOAD"
+  attribute \enum_value_0100110 "OP_STORE"
+  attribute \enum_value_0100111 "OP_MADDHD"
+  attribute \enum_value_0101000 "OP_MADDHDU"
+  attribute \enum_value_0101001 "OP_MADDLD"
+  attribute \enum_value_0101010 "OP_MCRF"
+  attribute \enum_value_0101011 "OP_MCRXR"
+  attribute \enum_value_0101100 "OP_MCRXRX"
+  attribute \enum_value_0101101 "OP_MFCR"
+  attribute \enum_value_0101110 "OP_MFSPR"
+  attribute \enum_value_0101111 "OP_MOD"
+  attribute \enum_value_0110000 "OP_MTCRF"
+  attribute \enum_value_0110001 "OP_MTSPR"
+  attribute \enum_value_0110010 "OP_MUL_L64"
+  attribute \enum_value_0110011 "OP_MUL_H64"
+  attribute \enum_value_0110100 "OP_MUL_H32"
+  attribute \enum_value_0110101 "OP_OR"
+  attribute \enum_value_0110110 "OP_POPCNT"
+  attribute \enum_value_0110111 "OP_PRTY"
+  attribute \enum_value_0111000 "OP_RLC"
+  attribute \enum_value_0111001 "OP_RLCL"
+  attribute \enum_value_0111010 "OP_RLCR"
+  attribute \enum_value_0111011 "OP_SETB"
+  attribute \enum_value_0111100 "OP_SHL"
+  attribute \enum_value_0111101 "OP_SHR"
+  attribute \enum_value_0111110 "OP_SYNC"
+  attribute \enum_value_0111111 "OP_TRAP"
+  attribute \enum_value_1000011 "OP_XOR"
+  attribute \enum_value_1000100 "OP_SIM_CONFIG"
+  attribute \enum_value_1000101 "OP_CROP"
+  attribute \enum_value_1000110 "OP_RFID"
+  attribute \enum_value_1000111 "OP_MFMSR"
+  attribute \enum_value_1001000 "OP_MTMSRD"
+  attribute \enum_value_1001001 "OP_SC"
+  attribute \enum_value_1001010 "OP_MTMSR"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 output 20 \mul_op__insn_type$2
+  attribute \enum_base_type "Function"
+  attribute \enum_value_00000000000 "NONE"
+  attribute \enum_value_00000000010 "ALU"
+  attribute \enum_value_00000000100 "LDST"
+  attribute \enum_value_00000001000 "SHIFT_ROT"
+  attribute \enum_value_00000010000 "LOGICAL"
+  attribute \enum_value_00000100000 "BRANCH"
+  attribute \enum_value_00001000000 "CR"
+  attribute \enum_value_00010000000 "TRAP"
+  attribute \enum_value_00100000000 "MUL"
+  attribute \enum_value_01000000000 "DIV"
+  attribute \enum_value_10000000000 "SPR"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 output 21 \mul_op__fn_unit$3
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 output 22 \mul_op__imm_data__imm$4
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 23 \mul_op__imm_data__imm_ok$5
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 24 \mul_op__rc__rc$6
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 25 \mul_op__rc__rc_ok$7
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 26 \mul_op__oe__oe$8
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 27 \mul_op__oe__oe_ok$9
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 28 \mul_op__invert_a$10
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 29 \mul_op__zero_a$11
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 30 \mul_op__invert_out$12
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 31 \mul_op__write_cr0$13
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 32 \mul_op__is_32bit$14
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 33 \mul_op__is_signed$15
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 output 34 \mul_op__insn$16
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
+  wire width 64 output 35 \ra$17
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
+  wire width 64 output 36 \rb$18
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
+  wire width 1 output 37 \xer_so$19
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11"
+  wire width 1 output 38 \neg_res
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12"
+  wire width 1 output 39 \neg_res32
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:30"
+  wire width 1 \is_32bit
+  process $group_0
+    assign \is_32bit 1'0
+    assign \is_32bit \mul_op__is_32bit
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:19"
-  cell $shift $4
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:31"
+  wire width 1 \sign_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:38"
+  wire width 1 $20
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:38"
+  cell $mux $21
+    parameter \WIDTH 1
+    connect \A \ra [63]
+    connect \B \ra [31]
+    connect \S \mul_op__is_32bit
+    connect \Y $20
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:38"
+  wire width 1 $22
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:38"
+  cell $and $23
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 128
+    parameter \A_WIDTH 1
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 8
-    parameter \Y_WIDTH 64
-    connect \A { \a \a }
-    connect \B $2
-    connect \Y $1
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $20
+    connect \B \mul_op__is_signed
+    connect \Y $22
   end
-  process $group_0
-    assign \o 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \o $1
+  process $group_1
+    assign \sign_a 1'0
+    assign \sign_a $22
     sync init
   end
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe.main.rotator"
-module \rotator
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:47"
-  wire width 5 input 0 \me
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:48"
-  wire width 5 input 1 \mb
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:50"
-  wire width 1 input 2 \mb_extra
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:52"
-  wire width 64 input 3 \rs
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:51"
-  wire width 64 input 4 \ra
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:53"
-  wire width 7 input 5 \shift
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:54"
-  wire width 1 input 6 \is_32bit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:56"
-  wire width 1 input 7 \arith
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:55"
-  wire width 1 input 8 \right_shift
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:57"
-  wire width 1 input 9 \clear_left
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:58"
-  wire width 1 input 10 \clear_right
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:59"
-  wire width 1 input 11 \sign_ext_rs
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:61"
-  wire width 64 output 12 \result_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:62"
-  wire width 1 output 13 \carry_out_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:8"
-  wire width 64 \rotl_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:9"
-  wire width 6 \rotl_b
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:11"
-  wire width 64 \rotl_o
-  cell \rotl \rotl
-    connect \a \rotl_a
-    connect \b \rotl_b
-    connect \o \rotl_o
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:78"
-  wire width 32 \hi32
-  process $group_0
-    assign \hi32 32'00000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:82"
-    switch { \sign_ext_rs \is_32bit }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:82"
-      case 2'-1
-        assign \hi32 \rs [31:0]
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:84"
-      case 2'1-
-        assign \hi32 { \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:87"
-      case
-        assign \hi32 \rs [63:32]
-    end
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:79"
-  wire width 64 \repl32
-  process $group_1
-    assign \repl32 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \repl32 { \hi32 \rs [31:0] }
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:91"
-  wire width 6 \shift_signed
-  process $group_2
-    assign \shift_signed 6'000000
-    assign \shift_signed \shift [5:0]
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:70"
-  wire width 6 \rot_count
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:96"
-  wire width 7 $1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:96"
-  wire width 7 $2
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:96"
-  cell $neg $3
-    parameter \A_SIGNED 1
-    parameter \A_WIDTH 6
-    parameter \Y_WIDTH 7
-    connect \A \shift_signed
-    connect \Y $2
-  end
-  connect $1 $2
-  process $group_3
-    assign \rot_count 6'000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:95"
-    switch { \right_shift }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:95"
-      case 1'1
-        assign \rot_count $1 [5:0]
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:97"
-      case
-        assign \rot_count \shift [5:0]
-    end
-    sync init
-  end
-  process $group_4
-    assign \rotl_a 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \rotl_a \repl32
-    sync init
-  end
-  process $group_5
-    assign \rotl_b 6'000000
-    assign \rotl_b \rot_count
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:71"
-  wire width 64 \rot
-  process $group_6
-    assign \rot 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \rot \rotl_o
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:72"
-  wire width 7 \sh
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:107"
-  wire width 1 $4
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:107"
-  cell $not $5
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \is_32bit
-    connect \Y $4
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:32"
+  wire width 1 \sign_b
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:39"
+  wire width 1 $24
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:39"
+  cell $mux $25
+    parameter \WIDTH 1
+    connect \A \rb [63]
+    connect \B \rb [31]
+    connect \S \mul_op__is_32bit
+    connect \Y $24
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:107"
-  wire width 1 $6
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:107"
-  cell $and $7
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:39"
+  wire width 1 $26
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:39"
+  cell $and $27
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \shift [6]
-    connect \B $4
-    connect \Y $6
+    connect \A $24
+    connect \B \mul_op__is_signed
+    connect \Y $26
   end
-  process $group_7
-    assign \sh 7'0000000
-    assign \sh { $6 \shift [5:0] }
+  process $group_2
+    assign \sign_b 1'0
+    assign \sign_b $26
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:73"
-  wire width 7 \mb$8
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:48"
-  wire width 7 $9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:48"
-  cell $pos $10
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 5
-    parameter \Y_WIDTH 7
-    connect \A \mb
-    connect \Y $9
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:123"
-  wire width 1 $11
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:123"
-  cell $not $12
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:33"
+  wire width 1 \sign32_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:40"
+  wire width 1 $28
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:40"
+  cell $and $29
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \sh [5]
-    connect \Y $11
+    connect \A \ra [31]
+    connect \B \mul_op__is_signed
+    connect \Y $28
   end
-  process $group_8
-    assign \mb$8 7'0000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:113"
-    switch { \right_shift \clear_left }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:113"
-      case 2'-1
-        assign \mb$8 $9
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:115"
-        switch { \is_32bit }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:115"
-          case 1'1
-            assign \mb$8 [6:5] 2'01
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:117"
-          case
-            assign \mb$8 [6:5] { 1'0 \mb_extra }
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:119"
-      case 2'1-
-        assign \mb$8 \sh
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:122"
-        switch { \is_32bit }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:122"
-          case 1'1
-            assign \mb$8 [6:5] { \sh [5] $11 }
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:124"
-      case
-        assign \mb$8 { 1'0 \is_32bit 5'00000 }
-    end
+  process $group_3
+    assign \sign32_a 1'0
+    assign \sign32_a $28
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:74"
-  wire width 7 \me$13
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:128"
-  wire width 1 $14
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:128"
-  cell $and $15
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:34"
+  wire width 1 \sign32_b
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:41"
+  wire width 1 $30
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:41"
+  cell $and $31
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \clear_right
-    connect \B \is_32bit
-    connect \Y $14
+    connect \A \rb [31]
+    connect \B \mul_op__is_signed
+    connect \Y $30
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:131"
-  wire width 1 $16
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:131"
-  cell $not $17
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \clear_left
-    connect \Y $16
+  process $group_4
+    assign \sign32_b 1'0
+    assign \sign32_b $30
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:131"
-  wire width 1 $18
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:131"
-  cell $and $19
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:44"
+  wire width 1 $32
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:44"
+  cell $xor $33
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \clear_right
-    connect \B $16
-    connect \Y $18
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:136"
-  wire width 6 $20
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:136"
-  cell $not $21
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 6
-    parameter \Y_WIDTH 6
-    connect \A \sh [5:0]
-    connect \Y $20
+    connect \A \sign_a
+    connect \B \sign_b
+    connect \Y $32
   end
-  process $group_9
-    assign \me$13 7'0000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:128"
-    switch { $18 $14 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:128"
-      case 2'-1
-        assign \me$13 { 2'01 \me }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:131"
-      case 2'1-
-        assign \me$13 { 1'0 \mb_extra \mb }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:134"
-      case
-        assign \me$13 { \sh [6] $20 }
-    end
+  process $group_5
+    assign \neg_res 1'0
+    assign \neg_res $32
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:14"
-  wire width 64 \right_mask
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:15"
-  wire width 1 $22
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:15"
-  cell $le $23
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:45"
+  wire width 1 $34
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:45"
+  cell $xor $35
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 7
+    parameter \A_WIDTH 1
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 7
+    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \mb$8
-    connect \B 7'1000000
-    connect \Y $22
+    connect \A \sign32_a
+    connect \B \sign32_b
+    connect \Y $34
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:16"
-  wire width 257 $24
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:16"
-  wire width 8 $25
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:16"
-  cell $sub $26
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-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 7
-    parameter \Y_WIDTH 8
-    connect \A 7'1000000
-    connect \B \mb$8
-    connect \Y $25
+  process $group_6
+    assign \neg_res32 1'0
+    assign \neg_res32 $34
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:16"
-  wire width 256 $27
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:16"
-  cell $sshl $28
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:50"
+  wire width 64 \abs_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:52"
+  wire width 65 $36
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:52"
+  wire width 65 $37
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:52"
+  cell $neg $38
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 8
-    parameter \Y_WIDTH 256
-    connect \A 1'1
-    connect \B $25
-    connect \Y $27
+    parameter \A_WIDTH 64
+    parameter \Y_WIDTH 65
+    connect \A \ra
+    connect \Y $37
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:16"
-  wire width 257 $29
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:16"
-  cell $sub $30
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
+  wire width 65 $39
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
+  cell $pos $40
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 256
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 257
-    connect \A $27
-    connect \B 1'1
-    connect \Y $29
+    parameter \A_WIDTH 64
+    parameter \Y_WIDTH 65
+    connect \A \ra
+    connect \Y $39
   end
-  connect $24 $29
-  process $group_10
-    assign \right_mask 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:15"
-    switch { $22 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:15"
-      case 1'1
-        assign \right_mask $24 [63:0]
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-    sync init
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:52"
+  wire width 65 $41
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:52"
+  cell $mux $42
+    parameter \WIDTH 65
+    connect \A $39
+    connect \B $37
+    connect \S \sign_a
+    connect \Y $41
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:75"
-  wire width 64 \mr
-  process $group_11
-    assign \mr 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \mr \right_mask
+  connect $36 $41
+  process $group_7
+    assign \abs_a 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \abs_a $36 [63:0]
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:21"
-  wire width 64 \left_mask
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:22"
-  wire width 257 $31
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:22"
-  wire width 257 $32
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:22"
-  wire width 8 $33
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:22"
-  cell $sub $34
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 6
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 7
-    parameter \Y_WIDTH 8
-    connect \A 6'111111
-    connect \B \me$13
-    connect \Y $33
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-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:22"
-  wire width 256 $35
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:22"
-  cell $sshl $36
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:51"
+  wire width 64 \abs_b
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:53"
+  wire width 65 $43
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:53"
+  wire width 65 $44
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:53"
+  cell $neg $45
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 8
-    parameter \Y_WIDTH 256
-    connect \A 1'1
-    connect \B $33
-    connect \Y $35
+    parameter \A_WIDTH 64
+    parameter \Y_WIDTH 65
+    connect \A \rb
+    connect \Y $44
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:22"
-  wire width 257 $37
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:22"
-  cell $sub $38
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
+  wire width 65 $46
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
+  cell $pos $47
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 256
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 257
-    connect \A $35
-    connect \B 1'1
-    connect \Y $37
+    parameter \A_WIDTH 64
+    parameter \Y_WIDTH 65
+    connect \A \rb
+    connect \Y $46
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:22"
-  cell $not $39
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 257
-    parameter \Y_WIDTH 257
-    connect \A $37
-    connect \Y $32
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:53"
+  wire width 65 $48
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:53"
+  cell $mux $49
+    parameter \WIDTH 65
+    connect \A $46
+    connect \B $44
+    connect \S \sign_b
+    connect \Y $48
   end
-  connect $31 $32
-  process $group_12
-    assign \left_mask 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \left_mask $31 [63:0]
+  connect $43 $48
+  process $group_8
+    assign \abs_b 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \abs_b $43 [63:0]
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:76"
-  wire width 64 \ml
-  process $group_13
-    assign \ml 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \ml \left_mask
-    sync init
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:34"
+  wire width 32 $50
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:34"
+  cell $mux $51
+    parameter \WIDTH 32
+    connect \A \abs_a [63:32]
+    connect \B 32'00000000000000000000000000000000
+    connect \S \is_32bit
+    connect \Y $50
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:77"
-  wire width 2 \output_mode
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:147"
-  wire width 1 $40
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:147"
-  cell $not $41
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \clear_right
-    connect \Y $40
+  process $group_9
+    assign \ra$17 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \ra$17 [31:0] \abs_a [31:0]
+    assign \ra$17 [63:32] $50
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:147"
-  wire width 1 $42
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:147"
-  cell $and $43
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \clear_left
-    connect \B $40
-    connect \Y $42
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-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:147"
-  wire width 1 $44
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:147"
-  cell $or $45
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A $42
-    connect \B \right_shift
-    connect \Y $44
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:148"
-  wire width 1 $46
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:148"
-  cell $and $47
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \arith
-    connect \B \repl32 [63]
-    connect \Y $46
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:150"
-  wire width 1 $48
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:150"
-  cell $gt $49
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 6
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 6
-    parameter \Y_WIDTH 1
-    connect \A \mb$8 [5:0]
-    connect \B \me$13 [5:0]
-    connect \Y $48
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-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:150"
-  wire width 1 $50
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:150"
-  cell $and $51
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \clear_right
-    connect \B $48
-    connect \Y $50
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-  process $group_14
-    assign \output_mode 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:147"
-    switch { $44 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:147"
-      case 1'1
-        assign \output_mode { 1'1 $46 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:149"
-      case
-        assign \output_mode { 1'0 $50 }
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-    sync init
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-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:156"
-  wire width 64 $52
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:156"
-  cell $and $53
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 64
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 64
-    parameter \Y_WIDTH 64
-    connect \A \mr
-    connect \B \ml
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:34"
+  wire width 32 $52
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:34"
+  cell $mux $53
+    parameter \WIDTH 32
+    connect \A \abs_b [63:32]
+    connect \B 32'00000000000000000000000000000000
+    connect \S \is_32bit
     connect \Y $52
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:156"
-  wire width 64 $54
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:156"
-  cell $and $55
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 64
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 64
-    parameter \Y_WIDTH 64
-    connect \A \rot
-    connect \B $52
-    connect \Y $54
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-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:156"
-  wire width 64 $56
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:156"
-  wire width 64 $57
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:156"
-  cell $and $58
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 64
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 64
-    parameter \Y_WIDTH 64
-    connect \A \mr
-    connect \B \ml
-    connect \Y $57
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:156"
-  cell $not $59
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 64
-    parameter \Y_WIDTH 64
-    connect \A $57
-    connect \Y $56
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-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:156"
-  wire width 64 $60
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:156"
-  cell $and $61
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 64
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 64
-    parameter \Y_WIDTH 64
-    connect \A \ra
-    connect \B $56
-    connect \Y $60
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:156"
-  wire width 64 $62
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:156"
-  cell $or $63
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 64
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 64
-    parameter \Y_WIDTH 64
-    connect \A $54
-    connect \B $60
-    connect \Y $62
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-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:158"
-  wire width 64 $64
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:158"
-  cell $or $65
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 64
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 64
-    parameter \Y_WIDTH 64
-    connect \A \mr
-    connect \B \ml
-    connect \Y $64
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:158"
-  wire width 64 $66
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:158"
-  cell $and $67
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 64
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 64
-    parameter \Y_WIDTH 64
-    connect \A \rot
-    connect \B $64
-    connect \Y $66
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-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:158"
-  wire width 64 $68
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:158"
-  wire width 64 $69
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:158"
-  cell $or $70
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 64
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 64
-    parameter \Y_WIDTH 64
-    connect \A \mr
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-    connect \Y $69
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:158"
-  cell $not $71
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 64
-    parameter \Y_WIDTH 64
-    connect \A $69
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-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:158"
-  wire width 64 $72
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:158"
-  cell $and $73
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 64
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 64
-    parameter \Y_WIDTH 64
-    connect \A \ra
-    connect \B $68
-    connect \Y $72
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-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:158"
-  wire width 64 $74
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:158"
-  cell $or $75
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 64
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 64
-    parameter \Y_WIDTH 64
-    connect \A $66
-    connect \B $72
-    connect \Y $74
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-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:160"
-  wire width 64 $76
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:160"
-  cell $and $77
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 64
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 64
-    parameter \Y_WIDTH 64
-    connect \A \rot
-    connect \B \mr
-    connect \Y $76
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:162"
-  wire width 64 $78
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:162"
-  cell $not $79
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 64
-    parameter \Y_WIDTH 64
-    connect \A \mr
-    connect \Y $78
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-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:162"
-  wire width 64 $80
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:162"
-  cell $or $81
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 64
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 64
-    parameter \Y_WIDTH 64
-    connect \A \rot
-    connect \B $78
-    connect \Y $80
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-  process $group_15
-    assign \result_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:154"
-    switch \output_mode
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:155"
-      case 2'00
-        assign \result_o $62
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:157"
-      case 2'01
-        assign \result_o $74
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:159"
-      case 2'10
-        assign \result_o $76
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:161"
-      case 2'11
-        assign \result_o $80
-    end
+  process $group_10
+    assign \rb$18 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \rb$18 [31:0] \abs_b [31:0]
+    assign \rb$18 [63:32] $52
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:164"
-  wire width 1 $82
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:164"
-  wire width 64 $83
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:164"
-  cell $not $84
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 64
-    parameter \Y_WIDTH 64
-    connect \A \ml
-    connect \Y $83
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-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:164"
-  wire width 64 $85
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:164"
-  cell $and $86
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 64
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 64
-    parameter \Y_WIDTH 64
-    connect \A \rs
-    connect \B $83
-    connect \Y $85
+  process $group_11
+    assign \xer_so$19 1'0
+    assign \xer_so$19 \xer_so
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:164"
-  cell $reduce_bool $87
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 64
-    parameter \Y_WIDTH 1
-    connect \A $85
-    connect \Y $82
+  process $group_12
+    assign \muxid$1 2'00
+    assign \muxid$1 \muxid
+    sync init
   end
-  process $group_16
-    assign \carry_out_o 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:154"
-    switch \output_mode
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:155"
-      case 2'00
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:157"
-      case 2'01
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:159"
-      case 2'10
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:161"
-      case 2'11
-        assign \carry_out_o $82
-    end
+  process $group_13
+    assign \mul_op__insn_type$2 7'0000000
+    assign \mul_op__fn_unit$3 11'00000000000
+    assign \mul_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \mul_op__imm_data__imm_ok$5 1'0
+    assign \mul_op__rc__rc$6 1'0
+    assign \mul_op__rc__rc_ok$7 1'0
+    assign \mul_op__oe__oe$8 1'0
+    assign \mul_op__oe__oe_ok$9 1'0
+    assign \mul_op__invert_a$10 1'0
+    assign \mul_op__zero_a$11 1'0
+    assign \mul_op__invert_out$12 1'0
+    assign \mul_op__write_cr0$13 1'0
+    assign \mul_op__is_32bit$14 1'0
+    assign \mul_op__is_signed$15 1'0
+    assign \mul_op__insn$16 32'00000000000000000000000000000000
+    assign { \mul_op__insn$16 \mul_op__is_signed$15 \mul_op__is_32bit$14 \mul_op__write_cr0$13 \mul_op__invert_out$12 \mul_op__zero_a$11 \mul_op__invert_a$10 { \mul_op__oe__oe_ok$9 \mul_op__oe__oe$8 } { \mul_op__rc__rc_ok$7 \mul_op__rc__rc$6 } { \mul_op__imm_data__imm_ok$5 \mul_op__imm_data__imm$4 } \mul_op__fn_unit$3 \mul_op__insn_type$2 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__invert_out \mul_op__zero_a \mul_op__invert_a { \mul_op__oe__oe_ok \mul_op__oe__oe } { \mul_op__rc__rc_ok \mul_op__rc__rc } { \mul_op__imm_data__imm_ok \mul_op__imm_data__imm } \mul_op__fn_unit \mul_op__insn_type }
     sync init
   end
 end
 attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe.main"
-module \main$93
+attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe1"
+module \mul_pipe1
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
+  wire width 1 output 2 \n_valid_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
+  wire width 1 input 3 \n_ready_i
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
-  wire width 2 input 0 \muxid
+  wire width 2 output 4 \muxid
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
+  wire width 2 \muxid$next
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
   attribute \enum_value_0000001 "OP_NOP"
@@ -101193,7 +101673,9 @@ module \main$93
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 7 input 1 \sr_op__insn_type
+  wire width 7 output 5 \mul_op__insn_type
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 \mul_op__insn_type$next
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -101207,45 +101689,87 @@ module \main$93
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 11 input 2 \sr_op__fn_unit
+  wire width 11 output 6 \mul_op__fn_unit
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 64 input 3 \sr_op__imm_data__imm
+  wire width 11 \mul_op__fn_unit$next
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 4 \sr_op__imm_data__imm_ok
+  wire width 64 output 7 \mul_op__imm_data__imm
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 5 \sr_op__rc__rc
+  wire width 64 \mul_op__imm_data__imm$next
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 6 \sr_op__rc__rc_ok
+  wire width 1 output 8 \mul_op__imm_data__imm_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 7 \sr_op__oe__oe
+  wire width 1 \mul_op__imm_data__imm_ok$next
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 8 \sr_op__oe__oe_ok
-  attribute \enum_base_type "CryIn"
-  attribute \enum_value_00 "ZERO"
-  attribute \enum_value_01 "ONE"
-  attribute \enum_value_10 "CA"
+  wire width 1 output 9 \mul_op__rc__rc
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 2 input 10 \sr_op__input_carry
+  wire width 1 \mul_op__rc__rc$next
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 11 \sr_op__output_carry
+  wire width 1 output 10 \mul_op__rc__rc_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 12 \sr_op__input_cr
+  wire width 1 \mul_op__rc__rc_ok$next
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 13 \sr_op__output_cr
+  wire width 1 output 11 \mul_op__oe__oe
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 14 \sr_op__is_32bit
+  wire width 1 \mul_op__oe__oe$next
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 15 \sr_op__is_signed
+  wire width 1 output 12 \mul_op__oe__oe_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 32 input 16 \sr_op__insn
+  wire width 1 \mul_op__oe__oe_ok$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 13 \mul_op__invert_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_op__invert_a$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 14 \mul_op__zero_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_op__zero_a$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 15 \mul_op__invert_out
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_op__invert_out$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 16 \mul_op__write_cr0
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_op__write_cr0$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 17 \mul_op__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_op__is_32bit$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 18 \mul_op__is_signed
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_op__is_signed$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 output 19 \mul_op__insn
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \mul_op__insn$next
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
-  wire width 64 input 17 \ra
+  wire width 64 output 20 \ra
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
-  wire width 64 input 18 \rb
+  wire width 64 \ra$next
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
-  wire width 64 input 19 \rc
+  wire width 64 output 21 \rb
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
+  wire width 64 \rb$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
+  wire width 1 output 22 \xer_so
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
+  wire width 1 \xer_so$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11"
+  wire width 1 output 23 \neg_res
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11"
+  wire width 1 \neg_res$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12"
+  wire width 1 output 24 \neg_res32
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12"
+  wire width 1 \neg_res32$next
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153"
+  wire width 1 input 25 \p_valid_i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154"
+  wire width 1 output 26 \p_ready_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
-  wire width 2 output 20 \muxid$1
+  wire width 2 input 27 \muxid$1
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
   attribute \enum_value_0000001 "OP_NOP"
@@ -101320,7 +101844,7 @@ module \main$93
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 7 output 21 \sr_op__insn_type$2
+  wire width 7 input 28 \mul_op__insn_type$2
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -101334,263 +101858,49 @@ module \main$93
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 11 output 22 \sr_op__fn_unit$3
+  wire width 11 input 29 \mul_op__fn_unit$3
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 64 output 23 \sr_op__imm_data__imm$4
+  wire width 64 input 30 \mul_op__imm_data__imm$4
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 24 \sr_op__imm_data__imm_ok$5
+  wire width 1 input 31 \mul_op__imm_data__imm_ok$5
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 25 \sr_op__rc__rc$6
+  wire width 1 input 32 \mul_op__rc__rc$6
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 26 \sr_op__rc__rc_ok$7
+  wire width 1 input 33 \mul_op__rc__rc_ok$7
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 27 \sr_op__oe__oe$8
+  wire width 1 input 34 \mul_op__oe__oe$8
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 28 \sr_op__oe__oe_ok$9
-  attribute \enum_base_type "CryIn"
-  attribute \enum_value_00 "ZERO"
-  attribute \enum_value_01 "ONE"
-  attribute \enum_value_10 "CA"
+  wire width 1 input 35 \mul_op__oe__oe_ok$9
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 2 output 30 \sr_op__input_carry$10
+  wire width 1 input 36 \mul_op__invert_a$10
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 31 \sr_op__output_carry$11
+  wire width 1 input 37 \mul_op__zero_a$11
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 32 \sr_op__input_cr$12
+  wire width 1 input 38 \mul_op__invert_out$12
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 33 \sr_op__output_cr$13
+  wire width 1 input 39 \mul_op__write_cr0$13
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 34 \sr_op__is_32bit$14
+  wire width 1 input 40 \mul_op__is_32bit$14
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 35 \sr_op__is_signed$15
+  wire width 1 input 41 \mul_op__is_signed$15
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 32 output 36 \sr_op__insn$16
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 64 output 37 \o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 38 \o_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 2 output 39 \xer_ca
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:47"
-  wire width 5 \rotator_me
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:48"
-  wire width 5 \rotator_mb
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:50"
-  wire width 1 \rotator_mb_extra
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:52"
-  wire width 64 \rotator_rs
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:51"
-  wire width 64 \rotator_ra
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:53"
-  wire width 7 \rotator_shift
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:54"
-  wire width 1 \rotator_is_32bit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:56"
-  wire width 1 \rotator_arith
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:55"
-  wire width 1 \rotator_right_shift
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:57"
-  wire width 1 \rotator_clear_left
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:58"
-  wire width 1 \rotator_clear_right
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:59"
-  wire width 1 \rotator_sign_ext_rs
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:61"
-  wire width 64 \rotator_result_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:62"
-  wire width 1 \rotator_carry_out_o
-  cell \rotator \rotator
-    connect \me \rotator_me
-    connect \mb \rotator_mb
-    connect \mb_extra \rotator_mb_extra
-    connect \rs \rotator_rs
-    connect \ra \rotator_ra
-    connect \shift \rotator_shift
-    connect \is_32bit \rotator_is_32bit
-    connect \arith \rotator_arith
-    connect \right_shift \rotator_right_shift
-    connect \clear_left \rotator_clear_left
-    connect \clear_right \rotator_clear_right
-    connect \sign_ext_rs \rotator_sign_ext_rs
-    connect \result_o \rotator_result_o
-    connect \carry_out_o \rotator_carry_out_o
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:42"
-  wire width 5 \mb
-  process $group_0
-    assign \mb 5'00000
-    assign \mb { \sr_op__insn [10] \sr_op__insn [9] \sr_op__insn [8] \sr_op__insn [7] \sr_op__insn [6] }
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:43"
-  wire width 5 \me
-  process $group_1
-    assign \me 5'00000
-    assign \me { \sr_op__insn [5] \sr_op__insn [4] \sr_op__insn [3] \sr_op__insn [2] \sr_op__insn [1] }
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:44"
-  wire width 1 \mb_extra
-  process $group_2
-    assign \mb_extra 1'0
-    assign \mb_extra { \sr_op__insn [10] \sr_op__insn [9] \sr_op__insn [8] \sr_op__insn [7] \sr_op__insn [6] \sr_op__insn [5] } [0]
-    sync init
-  end
-  process $group_3
-    assign \rotator_me 5'00000
-    assign \rotator_me \me
-    sync init
-  end
-  process $group_4
-    assign \rotator_mb 5'00000
-    assign \rotator_mb \mb
-    sync init
-  end
-  process $group_5
-    assign \rotator_mb_extra 1'0
-    assign \rotator_mb_extra \mb_extra
-    sync init
-  end
-  process $group_6
-    assign \rotator_rs 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \rotator_rs \rc
-    sync init
-  end
-  process $group_7
-    assign \rotator_ra 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \rotator_ra \ra
-    sync init
-  end
-  process $group_8
-    assign \rotator_shift 7'0000000
-    assign \rotator_shift \rb [6:0]
-    sync init
-  end
-  process $group_9
-    assign \rotator_is_32bit 1'0
-    assign \rotator_is_32bit \sr_op__is_32bit
-    sync init
-  end
-  process $group_10
-    assign \rotator_arith 1'0
-    assign \rotator_arith \sr_op__is_signed
-    sync init
-  end
-  process $group_11
-    assign \o_ok 1'0
-    assign \o_ok 1'1
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:66"
-    switch \sr_op__insn_type
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:67"
-      attribute \nmigen.decoding "OP_SHL/60"
-      case 7'0111100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:68"
-      attribute \nmigen.decoding "OP_SHR/61"
-      case 7'0111101
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:69"
-      attribute \nmigen.decoding "OP_RLC/56"
-      case 7'0111000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:70"
-      attribute \nmigen.decoding "OP_RLCL/57"
-      case 7'0111001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:71"
-      attribute \nmigen.decoding "OP_RLCR/58"
-      case 7'0111010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:72"
-      attribute \nmigen.decoding "OP_EXTSWSLI/32"
-      case 7'0100000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:73"
-      attribute \nmigen.decoding ""
-      case
-        assign \o_ok 1'0
-    end
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:65"
-  wire width 4 \mode
-  process $group_12
-    assign \mode 4'0000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:66"
-    switch \sr_op__insn_type
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:67"
-      attribute \nmigen.decoding "OP_SHL/60"
-      case 7'0111100
-        assign \mode 4'0000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:68"
-      attribute \nmigen.decoding "OP_SHR/61"
-      case 7'0111101
-        assign \mode 4'0001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:69"
-      attribute \nmigen.decoding "OP_RLC/56"
-      case 7'0111000
-        assign \mode 4'0110
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:70"
-      attribute \nmigen.decoding "OP_RLCL/57"
-      case 7'0111001
-        assign \mode 4'0010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:71"
-      attribute \nmigen.decoding "OP_RLCR/58"
-      case 7'0111010
-        assign \mode 4'0100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:72"
-      attribute \nmigen.decoding "OP_EXTSWSLI/32"
-      case 7'0100000
-        assign \mode 4'1000
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:73"
-      attribute \nmigen.decoding ""
-      case
-    end
-    sync init
-  end
-  process $group_13
-    assign \rotator_right_shift 1'0
-    assign \rotator_clear_left 1'0
-    assign \rotator_clear_right 1'0
-    assign \rotator_sign_ext_rs 1'0
-    assign { \rotator_sign_ext_rs \rotator_clear_right \rotator_clear_left \rotator_right_shift } \mode
-    sync init
-  end
-  process $group_17
-    assign \o 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \o \rotator_result_o
-    sync init
-  end
-  process $group_18
-    assign \xer_ca 2'00
-    assign \xer_ca { \rotator_carry_out_o \rotator_carry_out_o }
-    sync init
-  end
-  process $group_19
-    assign \muxid$1 2'00
-    assign \muxid$1 \muxid
-    sync init
+  wire width 32 input 42 \mul_op__insn$16
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
+  wire width 64 input 43 \ra$17
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
+  wire width 64 input 44 \rb$18
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
+  wire width 1 input 45 \xer_so$19
+  cell \p$89 \p
+    connect \p_valid_i \p_valid_i
+    connect \p_ready_o \p_ready_o
   end
-  process $group_20
-    assign \sr_op__insn_type$2 7'0000000
-    assign \sr_op__fn_unit$3 11'00000000000
-    assign \sr_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \sr_op__imm_data__imm_ok$5 1'0
-    assign \sr_op__rc__rc$6 1'0
-    assign \sr_op__rc__rc_ok$7 1'0
-    assign \sr_op__oe__oe$8 1'0
-    assign \sr_op__oe__oe_ok$9 1'0
-    assign { } 0'0
-    assign \sr_op__input_carry$10 2'00
-    assign \sr_op__output_carry$11 1'0
-    assign \sr_op__input_cr$12 1'0
-    assign \sr_op__output_cr$13 1'0
-    assign \sr_op__is_32bit$14 1'0
-    assign \sr_op__is_signed$15 1'0
-    assign \sr_op__insn$16 32'00000000000000000000000000000000
-    assign { \sr_op__insn$16 \sr_op__is_signed$15 \sr_op__is_32bit$14 \sr_op__output_cr$13 \sr_op__input_cr$12 \sr_op__output_carry$11 \sr_op__input_carry$10 { } { \sr_op__oe__oe_ok$9 \sr_op__oe__oe$8 } { \sr_op__rc__rc_ok$7 \sr_op__rc__rc$6 } { \sr_op__imm_data__imm_ok$5 \sr_op__imm_data__imm$4 } \sr_op__fn_unit$3 \sr_op__insn_type$2 } { \sr_op__insn \sr_op__is_signed \sr_op__is_32bit \sr_op__output_cr \sr_op__input_cr \sr_op__output_carry \sr_op__input_carry { } { \sr_op__oe__oe_ok \sr_op__oe__oe } { \sr_op__rc__rc_ok \sr_op__rc__rc } { \sr_op__imm_data__imm_ok \sr_op__imm_data__imm } \sr_op__fn_unit \sr_op__insn_type }
-    sync init
+  cell \n$90 \n
+    connect \n_valid_o \n_valid_o
+    connect \n_ready_i \n_ready_i
   end
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe.output"
-module \output$94
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
-  wire width 2 input 0 \muxid
+  wire width 2 \input_muxid
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
   attribute \enum_value_0000001 "OP_NOP"
@@ -101665,7 +101975,7 @@ module \output$94
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 7 input 1 \sr_op__insn_type
+  wire width 7 \input_mul_op__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -101679,47 +101989,41 @@ module \output$94
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 11 input 2 \sr_op__fn_unit
+  wire width 11 \input_mul_op__fn_unit
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 64 input 3 \sr_op__imm_data__imm
+  wire width 64 \input_mul_op__imm_data__imm
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 4 \sr_op__imm_data__imm_ok
+  wire width 1 \input_mul_op__imm_data__imm_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 5 \sr_op__rc__rc
+  wire width 1 \input_mul_op__rc__rc
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 6 \sr_op__rc__rc_ok
+  wire width 1 \input_mul_op__rc__rc_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 7 \sr_op__oe__oe
+  wire width 1 \input_mul_op__oe__oe
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 8 \sr_op__oe__oe_ok
-  attribute \enum_base_type "CryIn"
-  attribute \enum_value_00 "ZERO"
-  attribute \enum_value_01 "ONE"
-  attribute \enum_value_10 "CA"
+  wire width 1 \input_mul_op__oe__oe_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 2 input 10 \sr_op__input_carry
+  wire width 1 \input_mul_op__invert_a
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 11 \sr_op__output_carry
+  wire width 1 \input_mul_op__zero_a
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 12 \sr_op__input_cr
+  wire width 1 \input_mul_op__invert_out
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 13 \sr_op__output_cr
+  wire width 1 \input_mul_op__write_cr0
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 14 \sr_op__is_32bit
+  wire width 1 \input_mul_op__is_32bit
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 15 \sr_op__is_signed
+  wire width 1 \input_mul_op__is_signed
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 32 input 16 \sr_op__insn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 64 input 17 \o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 input 18 \o_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 4 input 19 \cr_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 2 input 20 \xer_ca
+  wire width 32 \input_mul_op__insn
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
+  wire width 64 \input_ra
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
+  wire width 64 \input_rb
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
+  wire width 1 \input_xer_so
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
-  wire width 2 output 21 \muxid$1
+  wire width 2 \input_muxid$20
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
   attribute \enum_value_0000001 "OP_NOP"
@@ -101794,7 +102098,7 @@ module \output$94
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 7 output 22 \sr_op__insn_type$2
+  wire width 7 \input_mul_op__insn_type$21
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -101808,317 +102112,81 @@ module \output$94
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 11 output 23 \sr_op__fn_unit$3
+  wire width 11 \input_mul_op__fn_unit$22
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 64 output 24 \sr_op__imm_data__imm$4
+  wire width 64 \input_mul_op__imm_data__imm$23
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 25 \sr_op__imm_data__imm_ok$5
+  wire width 1 \input_mul_op__imm_data__imm_ok$24
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 26 \sr_op__rc__rc$6
+  wire width 1 \input_mul_op__rc__rc$25
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 27 \sr_op__rc__rc_ok$7
+  wire width 1 \input_mul_op__rc__rc_ok$26
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 28 \sr_op__oe__oe$8
+  wire width 1 \input_mul_op__oe__oe$27
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 29 \sr_op__oe__oe_ok$9
-  attribute \enum_base_type "CryIn"
-  attribute \enum_value_00 "ZERO"
-  attribute \enum_value_01 "ONE"
-  attribute \enum_value_10 "CA"
+  wire width 1 \input_mul_op__oe__oe_ok$28
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 2 output 31 \sr_op__input_carry$10
+  wire width 1 \input_mul_op__invert_a$29
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 32 \sr_op__output_carry$11
+  wire width 1 \input_mul_op__zero_a$30
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 33 \sr_op__input_cr$12
+  wire width 1 \input_mul_op__invert_out$31
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 34 \sr_op__output_cr$13
+  wire width 1 \input_mul_op__write_cr0$32
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 35 \sr_op__is_32bit$14
+  wire width 1 \input_mul_op__is_32bit$33
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 36 \sr_op__is_signed$15
+  wire width 1 \input_mul_op__is_signed$34
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 32 output 37 \sr_op__insn$16
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 64 output 38 \o$17
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 39 \o_ok$18
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 4 output 40 \cr_a$19
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 41 \cr_a_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 2 output 42 \xer_ca$20
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 43 \xer_ca_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:23"
-  wire width 65 \o$21
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 65 $22
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  cell $pos $23
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 64
-    parameter \Y_WIDTH 65
-    connect \A \o
-    connect \Y $22
-  end
-  process $group_0
-    assign \o$21 65'00000000000000000000000000000000000000000000000000000000000000000
-    assign \o$21 $22
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:35"
-  wire width 64 \target
-  process $group_1
-    assign \target 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \target \o$21 [63:0]
-    sync init
-  end
-  process $group_2
-    assign \xer_ca$20 2'00
-    assign \xer_ca$20 \xer_ca
-    sync init
-  end
-  process $group_3
-    assign \xer_ca_ok 1'0
-    assign \xer_ca_ok \sr_op__output_carry
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:54"
-  wire width 1 \is_cmp
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:63"
-  wire width 1 $24
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:63"
-  cell $eq $25
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 7
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 7
-    parameter \Y_WIDTH 1
-    connect \A \sr_op__insn_type
-    connect \B 7'0001010
-    connect \Y $24
-  end
-  process $group_4
-    assign \is_cmp 1'0
-    assign \is_cmp $24
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:55"
-  wire width 1 \is_cmpeqb
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:64"
-  wire width 1 $26
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:64"
-  cell $eq $27
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 7
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 7
-    parameter \Y_WIDTH 1
-    connect \A \sr_op__insn_type
-    connect \B 7'0001100
-    connect \Y $26
-  end
-  process $group_5
-    assign \is_cmpeqb 1'0
-    assign \is_cmpeqb $26
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:53"
-  wire width 1 \msb_test
-  process $group_6
-    assign \msb_test 1'0
-    assign \msb_test \target [63]
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:50"
-  wire width 1 \is_nzero
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71"
-  wire width 1 $28
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71"
-  cell $reduce_bool $29
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 64
-    parameter \Y_WIDTH 1
-    connect \A \target
-    connect \Y $28
-  end
-  process $group_7
-    assign \is_nzero 1'0
-    assign \is_nzero $28
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:51"
-  wire width 1 \is_positive
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77"
-  wire width 1 $30
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77"
-  cell $not $31
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \msb_test
-    connect \Y $30
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77"
-  wire width 1 $32
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77"
-  cell $and $33
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \is_nzero
-    connect \B $30
-    connect \Y $32
-  end
-  process $group_8
-    assign \is_positive 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:72"
-    switch { \is_cmp }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:72"
-      case 1'1
-        assign \is_positive \msb_test
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:75"
-      case
-        assign \is_positive $32
-    end
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:52"
-  wire width 1 \is_negative
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:74"
-  wire width 1 $34
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:74"
-  cell $not $35
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \msb_test
-    connect \Y $34
+  wire width 32 \input_mul_op__insn$35
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
+  wire width 64 \input_ra$36
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
+  wire width 64 \input_rb$37
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
+  wire width 1 \input_xer_so$38
+  cell \input$91 \input
+    connect \muxid \input_muxid
+    connect \mul_op__insn_type \input_mul_op__insn_type
+    connect \mul_op__fn_unit \input_mul_op__fn_unit
+    connect \mul_op__imm_data__imm \input_mul_op__imm_data__imm
+    connect \mul_op__imm_data__imm_ok \input_mul_op__imm_data__imm_ok
+    connect \mul_op__rc__rc \input_mul_op__rc__rc
+    connect \mul_op__rc__rc_ok \input_mul_op__rc__rc_ok
+    connect \mul_op__oe__oe \input_mul_op__oe__oe
+    connect \mul_op__oe__oe_ok \input_mul_op__oe__oe_ok
+    connect \mul_op__invert_a \input_mul_op__invert_a
+    connect \mul_op__zero_a \input_mul_op__zero_a
+    connect \mul_op__invert_out \input_mul_op__invert_out
+    connect \mul_op__write_cr0 \input_mul_op__write_cr0
+    connect \mul_op__is_32bit \input_mul_op__is_32bit
+    connect \mul_op__is_signed \input_mul_op__is_signed
+    connect \mul_op__insn \input_mul_op__insn
+    connect \ra \input_ra
+    connect \rb \input_rb
+    connect \xer_so \input_xer_so
+    connect \muxid$1 \input_muxid$20
+    connect \mul_op__insn_type$2 \input_mul_op__insn_type$21
+    connect \mul_op__fn_unit$3 \input_mul_op__fn_unit$22
+    connect \mul_op__imm_data__imm$4 \input_mul_op__imm_data__imm$23
+    connect \mul_op__imm_data__imm_ok$5 \input_mul_op__imm_data__imm_ok$24
+    connect \mul_op__rc__rc$6 \input_mul_op__rc__rc$25
+    connect \mul_op__rc__rc_ok$7 \input_mul_op__rc__rc_ok$26
+    connect \mul_op__oe__oe$8 \input_mul_op__oe__oe$27
+    connect \mul_op__oe__oe_ok$9 \input_mul_op__oe__oe_ok$28
+    connect \mul_op__invert_a$10 \input_mul_op__invert_a$29
+    connect \mul_op__zero_a$11 \input_mul_op__zero_a$30
+    connect \mul_op__invert_out$12 \input_mul_op__invert_out$31
+    connect \mul_op__write_cr0$13 \input_mul_op__write_cr0$32
+    connect \mul_op__is_32bit$14 \input_mul_op__is_32bit$33
+    connect \mul_op__is_signed$15 \input_mul_op__is_signed$34
+    connect \mul_op__insn$16 \input_mul_op__insn$35
+    connect \ra$17 \input_ra$36
+    connect \rb$18 \input_rb$37
+    connect \xer_so$19 \input_xer_so$38
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:74"
-  wire width 1 $36
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:74"
-  cell $and $37
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \is_nzero
-    connect \B $34
-    connect \Y $36
-  end
-  process $group_9
-    assign \is_negative 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:72"
-    switch { \is_cmp }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:72"
-      case 1'1
-        assign \is_negative $36
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:75"
-      case
-        assign \is_negative \msb_test
-    end
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:57"
-  wire width 4 \cr0
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:82"
-  wire width 1 $38
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:82"
-  cell $not $39
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \is_nzero
-    connect \Y $38
-  end
-  process $group_10
-    assign \cr0 4'0000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:79"
-    switch { \is_cmpeqb }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:79"
-      case 1'1
-        assign \cr0 \cr_a
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81"
-      case
-        assign \cr0 { \is_negative \is_positive $38 1'0 }
-    end
-    sync init
-  end
-  process $group_11
-    assign \o$17 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \o$17 \o$21 [63:0]
-    sync init
-  end
-  process $group_12
-    assign \o_ok$18 1'0
-    assign \o_ok$18 \o_ok
-    sync init
-  end
-  process $group_13
-    assign \cr_a$19 4'0000
-    assign \cr_a$19 \cr0
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 $40
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  cell $pos $41
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 0
-    parameter \Y_WIDTH 1
-    connect \A { }
-    connect \Y $40
-  end
-  process $group_14
-    assign \cr_a_ok 1'0
-    assign \cr_a_ok $40
-    sync init
-  end
-  process $group_15
-    assign \muxid$1 2'00
-    assign \muxid$1 \muxid
-    sync init
-  end
-  process $group_16
-    assign \sr_op__insn_type$2 7'0000000
-    assign \sr_op__fn_unit$3 11'00000000000
-    assign \sr_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \sr_op__imm_data__imm_ok$5 1'0
-    assign \sr_op__rc__rc$6 1'0
-    assign \sr_op__rc__rc_ok$7 1'0
-    assign \sr_op__oe__oe$8 1'0
-    assign \sr_op__oe__oe_ok$9 1'0
-    assign { } 0'0
-    assign \sr_op__input_carry$10 2'00
-    assign \sr_op__output_carry$11 1'0
-    assign \sr_op__input_cr$12 1'0
-    assign \sr_op__output_cr$13 1'0
-    assign \sr_op__is_32bit$14 1'0
-    assign \sr_op__is_signed$15 1'0
-    assign \sr_op__insn$16 32'00000000000000000000000000000000
-    assign { \sr_op__insn$16 \sr_op__is_signed$15 \sr_op__is_32bit$14 \sr_op__output_cr$13 \sr_op__input_cr$12 \sr_op__output_carry$11 \sr_op__input_carry$10 { } { \sr_op__oe__oe_ok$9 \sr_op__oe__oe$8 } { \sr_op__rc__rc_ok$7 \sr_op__rc__rc$6 } { \sr_op__imm_data__imm_ok$5 \sr_op__imm_data__imm$4 } \sr_op__fn_unit$3 \sr_op__insn_type$2 } { \sr_op__insn \sr_op__is_signed \sr_op__is_32bit \sr_op__output_cr \sr_op__input_cr \sr_op__output_carry \sr_op__input_carry { } { \sr_op__oe__oe_ok \sr_op__oe__oe } { \sr_op__rc__rc_ok \sr_op__rc__rc } { \sr_op__imm_data__imm_ok \sr_op__imm_data__imm } \sr_op__fn_unit \sr_op__insn_type }
-    sync init
-  end
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe"
-module \pipe$89
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153"
-  wire width 1 input 2 \p_valid_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154"
-  wire width 1 output 3 \p_ready_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
-  wire width 2 input 4 \muxid
+  wire width 2 \mul1_muxid
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
   attribute \enum_value_0000001 "OP_NOP"
@@ -102193,7 +102261,7 @@ module \pipe$89
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 7 input 5 \sr_op__insn_type
+  wire width 7 \mul1_mul_op__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -102207,53 +102275,41 @@ module \pipe$89
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 11 input 6 \sr_op__fn_unit
+  wire width 11 \mul1_mul_op__fn_unit
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 64 input 7 \sr_op__imm_data__imm
+  wire width 64 \mul1_mul_op__imm_data__imm
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 8 \sr_op__imm_data__imm_ok
+  wire width 1 \mul1_mul_op__imm_data__imm_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 9 \sr_op__rc__rc
+  wire width 1 \mul1_mul_op__rc__rc
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 10 \sr_op__rc__rc_ok
+  wire width 1 \mul1_mul_op__rc__rc_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 11 \sr_op__oe__oe
+  wire width 1 \mul1_mul_op__oe__oe
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 12 \sr_op__oe__oe_ok
-  attribute \enum_base_type "CryIn"
-  attribute \enum_value_00 "ZERO"
-  attribute \enum_value_01 "ONE"
-  attribute \enum_value_10 "CA"
+  wire width 1 \mul1_mul_op__oe__oe_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 2 input 14 \sr_op__input_carry
+  wire width 1 \mul1_mul_op__invert_a
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 15 \sr_op__output_carry
+  wire width 1 \mul1_mul_op__zero_a
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 16 \sr_op__input_cr
+  wire width 1 \mul1_mul_op__invert_out
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 17 \sr_op__output_cr
+  wire width 1 \mul1_mul_op__write_cr0
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 18 \sr_op__is_32bit
+  wire width 1 \mul1_mul_op__is_32bit
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 19 \sr_op__is_signed
+  wire width 1 \mul1_mul_op__is_signed
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 32 input 20 \sr_op__insn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
-  wire width 64 input 21 \ra
+  wire width 32 \mul1_mul_op__insn
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
-  wire width 64 input 22 \rb
+  wire width 64 \mul1_ra
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
-  wire width 64 input 23 \rc
+  wire width 64 \mul1_rb
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
-  wire width 2 input 24 \xer_ca
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
-  wire width 1 output 25 \n_valid_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
-  wire width 1 input 26 \n_ready_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
-  wire width 2 output 27 \muxid$1
+  wire width 1 \mul1_xer_so
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
-  wire width 2 \muxid$1$next
+  wire width 2 \mul1_muxid$39
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
   attribute \enum_value_0000001 "OP_NOP"
@@ -102328,9 +102384,7 @@ module \pipe$89
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 7 output 28 \sr_op__insn_type$2
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 7 \sr_op__insn_type$2$next
+  wire width 7 \mul1_mul_op__insn_type$40
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -102344,99 +102398,204 @@ module \pipe$89
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 11 output 29 \sr_op__fn_unit$3
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 11 \sr_op__fn_unit$3$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 64 output 30 \sr_op__imm_data__imm$4
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 64 \sr_op__imm_data__imm$4$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 31 \sr_op__imm_data__imm_ok$5
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \sr_op__imm_data__imm_ok$5$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 32 \sr_op__rc__rc$6
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \sr_op__rc__rc$6$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 33 \sr_op__rc__rc_ok$7
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \sr_op__rc__rc_ok$7$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 34 \sr_op__oe__oe$8
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \sr_op__oe__oe$8$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 35 \sr_op__oe__oe_ok$9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \sr_op__oe__oe_ok$9$next
-  attribute \enum_base_type "CryIn"
-  attribute \enum_value_00 "ZERO"
-  attribute \enum_value_01 "ONE"
-  attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 2 output 37 \sr_op__input_carry$10
+  wire width 11 \mul1_mul_op__fn_unit$41
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 2 \sr_op__input_carry$10$next
+  wire width 64 \mul1_mul_op__imm_data__imm$42
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 38 \sr_op__output_carry$11
+  wire width 1 \mul1_mul_op__imm_data__imm_ok$43
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \sr_op__output_carry$11$next
+  wire width 1 \mul1_mul_op__rc__rc$44
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 39 \sr_op__input_cr$12
+  wire width 1 \mul1_mul_op__rc__rc_ok$45
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \sr_op__input_cr$12$next
+  wire width 1 \mul1_mul_op__oe__oe$46
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 40 \sr_op__output_cr$13
+  wire width 1 \mul1_mul_op__oe__oe_ok$47
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \sr_op__output_cr$13$next
+  wire width 1 \mul1_mul_op__invert_a$48
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 41 \sr_op__is_32bit$14
+  wire width 1 \mul1_mul_op__zero_a$49
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \sr_op__is_32bit$14$next
+  wire width 1 \mul1_mul_op__invert_out$50
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 output 42 \sr_op__is_signed$15
+  wire width 1 \mul1_mul_op__write_cr0$51
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \sr_op__is_signed$15$next
+  wire width 1 \mul1_mul_op__is_32bit$52
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 32 output 43 \sr_op__insn$16
+  wire width 1 \mul1_mul_op__is_signed$53
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 32 \sr_op__insn$16$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 64 output 44 \o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 64 \o$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 45 \o_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 \o_ok$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 4 output 46 \cr_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 4 \cr_a$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 47 \cr_a_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 \cr_a_ok$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 2 output 48 \xer_ca$17
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 2 \xer_ca$17$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 49 \xer_ca_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 \xer_ca_ok$next
-  cell \p$90 \p
-    connect \p_valid_i \p_valid_i
-    connect \p_ready_o \p_ready_o
+  wire width 32 \mul1_mul_op__insn$54
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
+  wire width 64 \mul1_ra$55
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
+  wire width 64 \mul1_rb$56
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
+  wire width 1 \mul1_xer_so$57
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11"
+  wire width 1 \mul1_neg_res
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12"
+  wire width 1 \mul1_neg_res32
+  cell \mul1 \mul1
+    connect \muxid \mul1_muxid
+    connect \mul_op__insn_type \mul1_mul_op__insn_type
+    connect \mul_op__fn_unit \mul1_mul_op__fn_unit
+    connect \mul_op__imm_data__imm \mul1_mul_op__imm_data__imm
+    connect \mul_op__imm_data__imm_ok \mul1_mul_op__imm_data__imm_ok
+    connect \mul_op__rc__rc \mul1_mul_op__rc__rc
+    connect \mul_op__rc__rc_ok \mul1_mul_op__rc__rc_ok
+    connect \mul_op__oe__oe \mul1_mul_op__oe__oe
+    connect \mul_op__oe__oe_ok \mul1_mul_op__oe__oe_ok
+    connect \mul_op__invert_a \mul1_mul_op__invert_a
+    connect \mul_op__zero_a \mul1_mul_op__zero_a
+    connect \mul_op__invert_out \mul1_mul_op__invert_out
+    connect \mul_op__write_cr0 \mul1_mul_op__write_cr0
+    connect \mul_op__is_32bit \mul1_mul_op__is_32bit
+    connect \mul_op__is_signed \mul1_mul_op__is_signed
+    connect \mul_op__insn \mul1_mul_op__insn
+    connect \ra \mul1_ra
+    connect \rb \mul1_rb
+    connect \xer_so \mul1_xer_so
+    connect \muxid$1 \mul1_muxid$39
+    connect \mul_op__insn_type$2 \mul1_mul_op__insn_type$40
+    connect \mul_op__fn_unit$3 \mul1_mul_op__fn_unit$41
+    connect \mul_op__imm_data__imm$4 \mul1_mul_op__imm_data__imm$42
+    connect \mul_op__imm_data__imm_ok$5 \mul1_mul_op__imm_data__imm_ok$43
+    connect \mul_op__rc__rc$6 \mul1_mul_op__rc__rc$44
+    connect \mul_op__rc__rc_ok$7 \mul1_mul_op__rc__rc_ok$45
+    connect \mul_op__oe__oe$8 \mul1_mul_op__oe__oe$46
+    connect \mul_op__oe__oe_ok$9 \mul1_mul_op__oe__oe_ok$47
+    connect \mul_op__invert_a$10 \mul1_mul_op__invert_a$48
+    connect \mul_op__zero_a$11 \mul1_mul_op__zero_a$49
+    connect \mul_op__invert_out$12 \mul1_mul_op__invert_out$50
+    connect \mul_op__write_cr0$13 \mul1_mul_op__write_cr0$51
+    connect \mul_op__is_32bit$14 \mul1_mul_op__is_32bit$52
+    connect \mul_op__is_signed$15 \mul1_mul_op__is_signed$53
+    connect \mul_op__insn$16 \mul1_mul_op__insn$54
+    connect \ra$17 \mul1_ra$55
+    connect \rb$18 \mul1_rb$56
+    connect \xer_so$19 \mul1_xer_so$57
+    connect \neg_res \mul1_neg_res
+    connect \neg_res32 \mul1_neg_res32
   end
-  cell \n$91 \n
-    connect \n_valid_o \n_valid_o
-    connect \n_ready_i \n_ready_i
+  process $group_0
+    assign \input_muxid 2'00
+    assign \input_muxid \muxid$1
+    sync init
+  end
+  process $group_1
+    assign \input_mul_op__insn_type 7'0000000
+    assign \input_mul_op__fn_unit 11'00000000000
+    assign \input_mul_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \input_mul_op__imm_data__imm_ok 1'0
+    assign \input_mul_op__rc__rc 1'0
+    assign \input_mul_op__rc__rc_ok 1'0
+    assign \input_mul_op__oe__oe 1'0
+    assign \input_mul_op__oe__oe_ok 1'0
+    assign \input_mul_op__invert_a 1'0
+    assign \input_mul_op__zero_a 1'0
+    assign \input_mul_op__invert_out 1'0
+    assign \input_mul_op__write_cr0 1'0
+    assign \input_mul_op__is_32bit 1'0
+    assign \input_mul_op__is_signed 1'0
+    assign \input_mul_op__insn 32'00000000000000000000000000000000
+    assign { \input_mul_op__insn \input_mul_op__is_signed \input_mul_op__is_32bit \input_mul_op__write_cr0 \input_mul_op__invert_out \input_mul_op__zero_a \input_mul_op__invert_a { \input_mul_op__oe__oe_ok \input_mul_op__oe__oe } { \input_mul_op__rc__rc_ok \input_mul_op__rc__rc } { \input_mul_op__imm_data__imm_ok \input_mul_op__imm_data__imm } \input_mul_op__fn_unit \input_mul_op__insn_type } { \mul_op__insn$16 \mul_op__is_signed$15 \mul_op__is_32bit$14 \mul_op__write_cr0$13 \mul_op__invert_out$12 \mul_op__zero_a$11 \mul_op__invert_a$10 { \mul_op__oe__oe_ok$9 \mul_op__oe__oe$8 } { \mul_op__rc__rc_ok$7 \mul_op__rc__rc$6 } { \mul_op__imm_data__imm_ok$5 \mul_op__imm_data__imm$4 } \mul_op__fn_unit$3 \mul_op__insn_type$2 }
+    sync init
+  end
+  process $group_16
+    assign \input_ra 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \input_ra \ra$17
+    sync init
+  end
+  process $group_17
+    assign \input_rb 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \input_rb \rb$18
+    sync init
+  end
+  process $group_18
+    assign \input_xer_so 1'0
+    assign \input_xer_so \xer_so$19
+    sync init
+  end
+  process $group_19
+    assign \mul1_muxid 2'00
+    assign \mul1_muxid \input_muxid$20
+    sync init
+  end
+  process $group_20
+    assign \mul1_mul_op__insn_type 7'0000000
+    assign \mul1_mul_op__fn_unit 11'00000000000
+    assign \mul1_mul_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \mul1_mul_op__imm_data__imm_ok 1'0
+    assign \mul1_mul_op__rc__rc 1'0
+    assign \mul1_mul_op__rc__rc_ok 1'0
+    assign \mul1_mul_op__oe__oe 1'0
+    assign \mul1_mul_op__oe__oe_ok 1'0
+    assign \mul1_mul_op__invert_a 1'0
+    assign \mul1_mul_op__zero_a 1'0
+    assign \mul1_mul_op__invert_out 1'0
+    assign \mul1_mul_op__write_cr0 1'0
+    assign \mul1_mul_op__is_32bit 1'0
+    assign \mul1_mul_op__is_signed 1'0
+    assign \mul1_mul_op__insn 32'00000000000000000000000000000000
+    assign { \mul1_mul_op__insn \mul1_mul_op__is_signed \mul1_mul_op__is_32bit \mul1_mul_op__write_cr0 \mul1_mul_op__invert_out \mul1_mul_op__zero_a \mul1_mul_op__invert_a { \mul1_mul_op__oe__oe_ok \mul1_mul_op__oe__oe } { \mul1_mul_op__rc__rc_ok \mul1_mul_op__rc__rc } { \mul1_mul_op__imm_data__imm_ok \mul1_mul_op__imm_data__imm } \mul1_mul_op__fn_unit \mul1_mul_op__insn_type } { \input_mul_op__insn$35 \input_mul_op__is_signed$34 \input_mul_op__is_32bit$33 \input_mul_op__write_cr0$32 \input_mul_op__invert_out$31 \input_mul_op__zero_a$30 \input_mul_op__invert_a$29 { \input_mul_op__oe__oe_ok$28 \input_mul_op__oe__oe$27 } { \input_mul_op__rc__rc_ok$26 \input_mul_op__rc__rc$25 } { \input_mul_op__imm_data__imm_ok$24 \input_mul_op__imm_data__imm$23 } \input_mul_op__fn_unit$22 \input_mul_op__insn_type$21 }
+    sync init
+  end
+  process $group_35
+    assign \mul1_ra 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \mul1_ra \input_ra$36
+    sync init
+  end
+  process $group_36
+    assign \mul1_rb 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \mul1_rb \input_rb$37
+    sync init
+  end
+  process $group_37
+    assign \mul1_xer_so 1'0
+    assign \mul1_xer_so \input_xer_so$38
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621"
+  wire width 1 \p_valid_i$58
+  process $group_38
+    assign \p_valid_i$58 1'0
+    assign \p_valid_i$58 \p_valid_i
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619"
+  wire width 1 \n_i_rdy_data
+  process $group_39
+    assign \n_i_rdy_data 1'0
+    assign \n_i_rdy_data \n_ready_i
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620"
+  wire width 1 \p_valid_i_p_ready_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624"
+  wire width 1 $59
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624"
+  cell $and $60
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \p_valid_i$58
+    connect \B \p_ready_o
+    connect \Y $59
+  end
+  process $group_40
+    assign \p_valid_i_p_ready_o 1'0
+    assign \p_valid_i_p_ready_o $59
+    sync init
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
-  wire width 2 \input_muxid
+  wire width 2 \muxid$61
+  process $group_41
+    assign \muxid$61 2'00
+    assign \muxid$61 \mul1_muxid$39
+    sync init
+  end
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
   attribute \enum_value_0000001 "OP_NOP"
@@ -102511,7 +102670,7 @@ module \pipe$89
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 7 \input_sr_op__insn_type
+  wire width 7 \mul_op__insn_type$62
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -102525,69 +102684,370 @@ module \pipe$89
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 11 \input_sr_op__fn_unit
+  wire width 11 \mul_op__fn_unit$63
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 64 \input_sr_op__imm_data__imm
+  wire width 64 \mul_op__imm_data__imm$64
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \input_sr_op__imm_data__imm_ok
+  wire width 1 \mul_op__imm_data__imm_ok$65
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \input_sr_op__rc__rc
+  wire width 1 \mul_op__rc__rc$66
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \input_sr_op__rc__rc_ok
+  wire width 1 \mul_op__rc__rc_ok$67
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \input_sr_op__oe__oe
+  wire width 1 \mul_op__oe__oe$68
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \input_sr_op__oe__oe_ok
-  attribute \enum_base_type "CryIn"
-  attribute \enum_value_00 "ZERO"
-  attribute \enum_value_01 "ONE"
-  attribute \enum_value_10 "CA"
+  wire width 1 \mul_op__oe__oe_ok$69
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 2 \input_sr_op__input_carry
+  wire width 1 \mul_op__invert_a$70
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \input_sr_op__output_carry
+  wire width 1 \mul_op__zero_a$71
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \input_sr_op__input_cr
+  wire width 1 \mul_op__invert_out$72
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \input_sr_op__output_cr
+  wire width 1 \mul_op__write_cr0$73
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \input_sr_op__is_32bit
+  wire width 1 \mul_op__is_32bit$74
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \input_sr_op__is_signed
+  wire width 1 \mul_op__is_signed$75
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 32 \input_sr_op__insn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
-  wire width 64 \input_ra
+  wire width 32 \mul_op__insn$76
+  process $group_42
+    assign \mul_op__insn_type$62 7'0000000
+    assign \mul_op__fn_unit$63 11'00000000000
+    assign \mul_op__imm_data__imm$64 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \mul_op__imm_data__imm_ok$65 1'0
+    assign \mul_op__rc__rc$66 1'0
+    assign \mul_op__rc__rc_ok$67 1'0
+    assign \mul_op__oe__oe$68 1'0
+    assign \mul_op__oe__oe_ok$69 1'0
+    assign \mul_op__invert_a$70 1'0
+    assign \mul_op__zero_a$71 1'0
+    assign \mul_op__invert_out$72 1'0
+    assign \mul_op__write_cr0$73 1'0
+    assign \mul_op__is_32bit$74 1'0
+    assign \mul_op__is_signed$75 1'0
+    assign \mul_op__insn$76 32'00000000000000000000000000000000
+    assign { \mul_op__insn$76 \mul_op__is_signed$75 \mul_op__is_32bit$74 \mul_op__write_cr0$73 \mul_op__invert_out$72 \mul_op__zero_a$71 \mul_op__invert_a$70 { \mul_op__oe__oe_ok$69 \mul_op__oe__oe$68 } { \mul_op__rc__rc_ok$67 \mul_op__rc__rc$66 } { \mul_op__imm_data__imm_ok$65 \mul_op__imm_data__imm$64 } \mul_op__fn_unit$63 \mul_op__insn_type$62 } { \mul1_mul_op__insn$54 \mul1_mul_op__is_signed$53 \mul1_mul_op__is_32bit$52 \mul1_mul_op__write_cr0$51 \mul1_mul_op__invert_out$50 \mul1_mul_op__zero_a$49 \mul1_mul_op__invert_a$48 { \mul1_mul_op__oe__oe_ok$47 \mul1_mul_op__oe__oe$46 } { \mul1_mul_op__rc__rc_ok$45 \mul1_mul_op__rc__rc$44 } { \mul1_mul_op__imm_data__imm_ok$43 \mul1_mul_op__imm_data__imm$42 } \mul1_mul_op__fn_unit$41 \mul1_mul_op__insn_type$40 }
+    sync init
+  end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
-  wire width 64 \input_rb
+  wire width 64 \ra$77
+  process $group_57
+    assign \ra$77 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \ra$77 \mul1_ra$55
+    sync init
+  end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
-  wire width 64 \input_rc
+  wire width 64 \rb$78
+  process $group_58
+    assign \rb$78 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \rb$78 \mul1_rb$56
+    sync init
+  end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
-  wire width 2 \input_xer_ca
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
-  wire width 2 \input_muxid$18
-  attribute \enum_base_type "MicrOp"
-  attribute \enum_value_0000000 "OP_ILLEGAL"
-  attribute \enum_value_0000001 "OP_NOP"
-  attribute \enum_value_0000010 "OP_ADD"
-  attribute \enum_value_0000011 "OP_ADDPCIS"
-  attribute \enum_value_0000100 "OP_AND"
-  attribute \enum_value_0000101 "OP_ATTN"
-  attribute \enum_value_0000110 "OP_B"
-  attribute \enum_value_0000111 "OP_BC"
-  attribute \enum_value_0001000 "OP_BCREG"
-  attribute \enum_value_0001001 "OP_BPERM"
-  attribute \enum_value_0001010 "OP_CMP"
-  attribute \enum_value_0001011 "OP_CMPB"
-  attribute \enum_value_0001100 "OP_CMPEQB"
-  attribute \enum_value_0001101 "OP_CMPRB"
-  attribute \enum_value_0001110 "OP_CNTZ"
-  attribute \enum_value_0001111 "OP_CRAND"
-  attribute \enum_value_0010000 "OP_CRANDC"
-  attribute \enum_value_0010001 "OP_CREQV"
-  attribute \enum_value_0010010 "OP_CRNAND"
-  attribute \enum_value_0010011 "OP_CRNOR"
-  attribute \enum_value_0010100 "OP_CROR"
+  wire width 1 \xer_so$79
+  process $group_59
+    assign \xer_so$79 1'0
+    assign \xer_so$79 \mul1_xer_so$57
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11"
+  wire width 1 \neg_res$80
+  process $group_60
+    assign \neg_res$80 1'0
+    assign \neg_res$80 \mul1_neg_res
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12"
+  wire width 1 \neg_res32$81
+  process $group_61
+    assign \neg_res32$81 1'0
+    assign \neg_res32$81 \mul1_neg_res32
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615"
+  wire width 1 \r_busy
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615"
+  wire width 1 \r_busy$next
+  process $group_62
+    assign \r_busy$next \r_busy
+    attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+    switch { \n_i_rdy_data \p_valid_i_p_ready_o }
+      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+      case 2'-1
+        assign \r_busy$next 1'1
+      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
+      case 2'1-
+        assign \r_busy$next 1'0
+    end
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
+      case 1'1
+        assign \r_busy$next 1'0
+    end
+    sync init
+      update \r_busy 1'0
+    sync posedge \coresync_clk
+      update \r_busy \r_busy$next
+  end
+  process $group_63
+    assign \muxid$next \muxid
+    attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+    switch { \n_i_rdy_data \p_valid_i_p_ready_o }
+      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+      case 2'-1
+        assign \muxid$next \muxid$61
+      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
+      case 2'1-
+        assign \muxid$next \muxid$61
+    end
+    sync init
+      update \muxid 2'00
+    sync posedge \coresync_clk
+      update \muxid \muxid$next
+  end
+  process $group_64
+    assign \mul_op__insn_type$next \mul_op__insn_type
+    assign \mul_op__fn_unit$next \mul_op__fn_unit
+    assign \mul_op__imm_data__imm$next \mul_op__imm_data__imm
+    assign \mul_op__imm_data__imm_ok$next \mul_op__imm_data__imm_ok
+    assign \mul_op__rc__rc$next \mul_op__rc__rc
+    assign \mul_op__rc__rc_ok$next \mul_op__rc__rc_ok
+    assign \mul_op__oe__oe$next \mul_op__oe__oe
+    assign \mul_op__oe__oe_ok$next \mul_op__oe__oe_ok
+    assign \mul_op__invert_a$next \mul_op__invert_a
+    assign \mul_op__zero_a$next \mul_op__zero_a
+    assign \mul_op__invert_out$next \mul_op__invert_out
+    assign \mul_op__write_cr0$next \mul_op__write_cr0
+    assign \mul_op__is_32bit$next \mul_op__is_32bit
+    assign \mul_op__is_signed$next \mul_op__is_signed
+    assign \mul_op__insn$next \mul_op__insn
+    attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+    switch { \n_i_rdy_data \p_valid_i_p_ready_o }
+      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+      case 2'-1
+        assign { \mul_op__insn$next \mul_op__is_signed$next \mul_op__is_32bit$next \mul_op__write_cr0$next \mul_op__invert_out$next \mul_op__zero_a$next \mul_op__invert_a$next { \mul_op__oe__oe_ok$next \mul_op__oe__oe$next } { \mul_op__rc__rc_ok$next \mul_op__rc__rc$next } { \mul_op__imm_data__imm_ok$next \mul_op__imm_data__imm$next } \mul_op__fn_unit$next \mul_op__insn_type$next } { \mul_op__insn$76 \mul_op__is_signed$75 \mul_op__is_32bit$74 \mul_op__write_cr0$73 \mul_op__invert_out$72 \mul_op__zero_a$71 \mul_op__invert_a$70 { \mul_op__oe__oe_ok$69 \mul_op__oe__oe$68 } { \mul_op__rc__rc_ok$67 \mul_op__rc__rc$66 } { \mul_op__imm_data__imm_ok$65 \mul_op__imm_data__imm$64 } \mul_op__fn_unit$63 \mul_op__insn_type$62 }
+      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
+      case 2'1-
+        assign { \mul_op__insn$next \mul_op__is_signed$next \mul_op__is_32bit$next \mul_op__write_cr0$next \mul_op__invert_out$next \mul_op__zero_a$next \mul_op__invert_a$next { \mul_op__oe__oe_ok$next \mul_op__oe__oe$next } { \mul_op__rc__rc_ok$next \mul_op__rc__rc$next } { \mul_op__imm_data__imm_ok$next \mul_op__imm_data__imm$next } \mul_op__fn_unit$next \mul_op__insn_type$next } { \mul_op__insn$76 \mul_op__is_signed$75 \mul_op__is_32bit$74 \mul_op__write_cr0$73 \mul_op__invert_out$72 \mul_op__zero_a$71 \mul_op__invert_a$70 { \mul_op__oe__oe_ok$69 \mul_op__oe__oe$68 } { \mul_op__rc__rc_ok$67 \mul_op__rc__rc$66 } { \mul_op__imm_data__imm_ok$65 \mul_op__imm_data__imm$64 } \mul_op__fn_unit$63 \mul_op__insn_type$62 }
+    end
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
+      case 1'1
+        assign \mul_op__imm_data__imm$next 64'0000000000000000000000000000000000000000000000000000000000000000
+        assign \mul_op__imm_data__imm_ok$next 1'0
+        assign \mul_op__rc__rc$next 1'0
+        assign \mul_op__rc__rc_ok$next 1'0
+        assign \mul_op__oe__oe$next 1'0
+        assign \mul_op__oe__oe_ok$next 1'0
+    end
+    sync init
+      update \mul_op__insn_type 7'0000000
+      update \mul_op__fn_unit 11'00000000000
+      update \mul_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
+      update \mul_op__imm_data__imm_ok 1'0
+      update \mul_op__rc__rc 1'0
+      update \mul_op__rc__rc_ok 1'0
+      update \mul_op__oe__oe 1'0
+      update \mul_op__oe__oe_ok 1'0
+      update \mul_op__invert_a 1'0
+      update \mul_op__zero_a 1'0
+      update \mul_op__invert_out 1'0
+      update \mul_op__write_cr0 1'0
+      update \mul_op__is_32bit 1'0
+      update \mul_op__is_signed 1'0
+      update \mul_op__insn 32'00000000000000000000000000000000
+    sync posedge \coresync_clk
+      update \mul_op__insn_type \mul_op__insn_type$next
+      update \mul_op__fn_unit \mul_op__fn_unit$next
+      update \mul_op__imm_data__imm \mul_op__imm_data__imm$next
+      update \mul_op__imm_data__imm_ok \mul_op__imm_data__imm_ok$next
+      update \mul_op__rc__rc \mul_op__rc__rc$next
+      update \mul_op__rc__rc_ok \mul_op__rc__rc_ok$next
+      update \mul_op__oe__oe \mul_op__oe__oe$next
+      update \mul_op__oe__oe_ok \mul_op__oe__oe_ok$next
+      update \mul_op__invert_a \mul_op__invert_a$next
+      update \mul_op__zero_a \mul_op__zero_a$next
+      update \mul_op__invert_out \mul_op__invert_out$next
+      update \mul_op__write_cr0 \mul_op__write_cr0$next
+      update \mul_op__is_32bit \mul_op__is_32bit$next
+      update \mul_op__is_signed \mul_op__is_signed$next
+      update \mul_op__insn \mul_op__insn$next
+  end
+  process $group_79
+    assign \ra$next \ra
+    attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+    switch { \n_i_rdy_data \p_valid_i_p_ready_o }
+      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+      case 2'-1
+        assign \ra$next \ra$77
+      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
+      case 2'1-
+        assign \ra$next \ra$77
+    end
+    sync init
+      update \ra 64'0000000000000000000000000000000000000000000000000000000000000000
+    sync posedge \coresync_clk
+      update \ra \ra$next
+  end
+  process $group_80
+    assign \rb$next \rb
+    attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+    switch { \n_i_rdy_data \p_valid_i_p_ready_o }
+      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+      case 2'-1
+        assign \rb$next \rb$78
+      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
+      case 2'1-
+        assign \rb$next \rb$78
+    end
+    sync init
+      update \rb 64'0000000000000000000000000000000000000000000000000000000000000000
+    sync posedge \coresync_clk
+      update \rb \rb$next
+  end
+  process $group_81
+    assign \xer_so$next \xer_so
+    attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+    switch { \n_i_rdy_data \p_valid_i_p_ready_o }
+      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+      case 2'-1
+        assign \xer_so$next \xer_so$79
+      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
+      case 2'1-
+        assign \xer_so$next \xer_so$79
+    end
+    sync init
+      update \xer_so 1'0
+    sync posedge \coresync_clk
+      update \xer_so \xer_so$next
+  end
+  process $group_82
+    assign \neg_res$next \neg_res
+    attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+    switch { \n_i_rdy_data \p_valid_i_p_ready_o }
+      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+      case 2'-1
+        assign \neg_res$next \neg_res$80
+      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
+      case 2'1-
+        assign \neg_res$next \neg_res$80
+    end
+    sync init
+      update \neg_res 1'0
+    sync posedge \coresync_clk
+      update \neg_res \neg_res$next
+  end
+  process $group_83
+    assign \neg_res32$next \neg_res32
+    attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+    switch { \n_i_rdy_data \p_valid_i_p_ready_o }
+      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+      case 2'-1
+        assign \neg_res32$next \neg_res32$81
+      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
+      case 2'1-
+        assign \neg_res32$next \neg_res32$81
+    end
+    sync init
+      update \neg_res32 1'0
+    sync posedge \coresync_clk
+      update \neg_res32 \neg_res32$next
+  end
+  process $group_84
+    assign \n_valid_o 1'0
+    assign \n_valid_o \r_busy
+    sync init
+  end
+  process $group_85
+    assign \p_ready_o 1'0
+    assign \p_ready_o \n_i_rdy_data
+    sync init
+  end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe2.p"
+module \p$92
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153"
+  wire width 1 input 0 \p_valid_i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154"
+  wire width 1 input 1 \p_ready_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158"
+  wire width 1 \trigger
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205"
+  wire width 1 $1
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205"
+  cell $and $2
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \p_valid_i
+    connect \B \p_ready_o
+    connect \Y $1
+  end
+  process $group_0
+    assign \trigger 1'0
+    assign \trigger $1
+    sync init
+  end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe2.n"
+module \n$93
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
+  wire width 1 input 0 \n_valid_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
+  wire width 1 input 1 \n_ready_i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251"
+  wire width 1 \trigger
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298"
+  wire width 1 $1
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298"
+  cell $and $2
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \n_ready_i
+    connect \B \n_valid_o
+    connect \Y $1
+  end
+  process $group_0
+    assign \trigger 1'0
+    assign \trigger $1
+    sync init
+  end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe2.mul2"
+module \mul2
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
+  wire width 2 input 0 \muxid
+  attribute \enum_base_type "MicrOp"
+  attribute \enum_value_0000000 "OP_ILLEGAL"
+  attribute \enum_value_0000001 "OP_NOP"
+  attribute \enum_value_0000010 "OP_ADD"
+  attribute \enum_value_0000011 "OP_ADDPCIS"
+  attribute \enum_value_0000100 "OP_AND"
+  attribute \enum_value_0000101 "OP_ATTN"
+  attribute \enum_value_0000110 "OP_B"
+  attribute \enum_value_0000111 "OP_BC"
+  attribute \enum_value_0001000 "OP_BCREG"
+  attribute \enum_value_0001001 "OP_BPERM"
+  attribute \enum_value_0001010 "OP_CMP"
+  attribute \enum_value_0001011 "OP_CMPB"
+  attribute \enum_value_0001100 "OP_CMPEQB"
+  attribute \enum_value_0001101 "OP_CMPRB"
+  attribute \enum_value_0001110 "OP_CNTZ"
+  attribute \enum_value_0001111 "OP_CRAND"
+  attribute \enum_value_0010000 "OP_CRANDC"
+  attribute \enum_value_0010001 "OP_CREQV"
+  attribute \enum_value_0010010 "OP_CRNAND"
+  attribute \enum_value_0010011 "OP_CRNOR"
+  attribute \enum_value_0010100 "OP_CROR"
   attribute \enum_value_0010101 "OP_CRORC"
   attribute \enum_value_0010110 "OP_CRXOR"
   attribute \enum_value_0010111 "OP_DARN"
@@ -102640,7 +103100,7 @@ module \pipe$89
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 7 \input_sr_op__insn_type$19
+  wire width 7 input 1 \mul_op__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -102654,89 +103114,45 @@ module \pipe$89
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 11 \input_sr_op__fn_unit$20
+  wire width 11 input 2 \mul_op__fn_unit
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 64 \input_sr_op__imm_data__imm$21
+  wire width 64 input 3 \mul_op__imm_data__imm
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \input_sr_op__imm_data__imm_ok$22
+  wire width 1 input 4 \mul_op__imm_data__imm_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \input_sr_op__rc__rc$23
+  wire width 1 input 5 \mul_op__rc__rc
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \input_sr_op__rc__rc_ok$24
+  wire width 1 input 6 \mul_op__rc__rc_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \input_sr_op__oe__oe$25
+  wire width 1 input 7 \mul_op__oe__oe
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \input_sr_op__oe__oe_ok$26
-  attribute \enum_base_type "CryIn"
-  attribute \enum_value_00 "ZERO"
-  attribute \enum_value_01 "ONE"
-  attribute \enum_value_10 "CA"
+  wire width 1 input 8 \mul_op__oe__oe_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 2 \input_sr_op__input_carry$27
+  wire width 1 input 9 \mul_op__invert_a
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \input_sr_op__output_carry$28
+  wire width 1 input 10 \mul_op__zero_a
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \input_sr_op__input_cr$29
+  wire width 1 input 11 \mul_op__invert_out
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \input_sr_op__output_cr$30
+  wire width 1 input 12 \mul_op__write_cr0
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \input_sr_op__is_32bit$31
+  wire width 1 input 13 \mul_op__is_32bit
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \input_sr_op__is_signed$32
+  wire width 1 input 14 \mul_op__is_signed
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 32 \input_sr_op__insn$33
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
-  wire width 64 \input_ra$34
+  wire width 32 input 15 \mul_op__insn
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
-  wire width 64 \input_rb$35
+  wire width 64 input 16 \ra
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
-  wire width 64 \input_rc$36
+  wire width 64 input 17 \rb
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
-  wire width 2 \input_xer_ca$37
-  cell \input$92 \input
-    connect \muxid \input_muxid
-    connect \sr_op__insn_type \input_sr_op__insn_type
-    connect \sr_op__fn_unit \input_sr_op__fn_unit
-    connect \sr_op__imm_data__imm \input_sr_op__imm_data__imm
-    connect \sr_op__imm_data__imm_ok \input_sr_op__imm_data__imm_ok
-    connect \sr_op__rc__rc \input_sr_op__rc__rc
-    connect \sr_op__rc__rc_ok \input_sr_op__rc__rc_ok
-    connect \sr_op__oe__oe \input_sr_op__oe__oe
-    connect \sr_op__oe__oe_ok \input_sr_op__oe__oe_ok
-    connect \sr_op__input_carry \input_sr_op__input_carry
-    connect \sr_op__output_carry \input_sr_op__output_carry
-    connect \sr_op__input_cr \input_sr_op__input_cr
-    connect \sr_op__output_cr \input_sr_op__output_cr
-    connect \sr_op__is_32bit \input_sr_op__is_32bit
-    connect \sr_op__is_signed \input_sr_op__is_signed
-    connect \sr_op__insn \input_sr_op__insn
-    connect \ra \input_ra
-    connect \rb \input_rb
-    connect \rc \input_rc
-    connect \xer_ca \input_xer_ca
-    connect \muxid$1 \input_muxid$18
-    connect \sr_op__insn_type$2 \input_sr_op__insn_type$19
-    connect \sr_op__fn_unit$3 \input_sr_op__fn_unit$20
-    connect \sr_op__imm_data__imm$4 \input_sr_op__imm_data__imm$21
-    connect \sr_op__imm_data__imm_ok$5 \input_sr_op__imm_data__imm_ok$22
-    connect \sr_op__rc__rc$6 \input_sr_op__rc__rc$23
-    connect \sr_op__rc__rc_ok$7 \input_sr_op__rc__rc_ok$24
-    connect \sr_op__oe__oe$8 \input_sr_op__oe__oe$25
-    connect \sr_op__oe__oe_ok$9 \input_sr_op__oe__oe_ok$26
-    connect \sr_op__input_carry$10 \input_sr_op__input_carry$27
-    connect \sr_op__output_carry$11 \input_sr_op__output_carry$28
-    connect \sr_op__input_cr$12 \input_sr_op__input_cr$29
-    connect \sr_op__output_cr$13 \input_sr_op__output_cr$30
-    connect \sr_op__is_32bit$14 \input_sr_op__is_32bit$31
-    connect \sr_op__is_signed$15 \input_sr_op__is_signed$32
-    connect \sr_op__insn$16 \input_sr_op__insn$33
-    connect \ra$17 \input_ra$34
-    connect \rb$18 \input_rb$35
-    connect \rc$19 \input_rc$36
-    connect \xer_ca$20 \input_xer_ca$37
-  end
+  wire width 1 input 18 \xer_so
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11"
+  wire width 1 input 19 \neg_res
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12"
+  wire width 1 input 20 \neg_res32
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
-  wire width 2 \main_muxid
+  wire width 2 output 21 \muxid$1
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
   attribute \enum_value_0000001 "OP_NOP"
@@ -102811,7 +103227,7 @@ module \pipe$89
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 7 \main_sr_op__insn_type
+  wire width 7 output 22 \mul_op__insn_type$2
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -102825,45 +103241,122 @@ module \pipe$89
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 11 \main_sr_op__fn_unit
+  wire width 11 output 23 \mul_op__fn_unit$3
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 64 \main_sr_op__imm_data__imm
+  wire width 64 output 24 \mul_op__imm_data__imm$4
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \main_sr_op__imm_data__imm_ok
+  wire width 1 output 25 \mul_op__imm_data__imm_ok$5
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \main_sr_op__rc__rc
+  wire width 1 output 26 \mul_op__rc__rc$6
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \main_sr_op__rc__rc_ok
+  wire width 1 output 27 \mul_op__rc__rc_ok$7
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \main_sr_op__oe__oe
+  wire width 1 output 28 \mul_op__oe__oe$8
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \main_sr_op__oe__oe_ok
-  attribute \enum_base_type "CryIn"
-  attribute \enum_value_00 "ZERO"
-  attribute \enum_value_01 "ONE"
-  attribute \enum_value_10 "CA"
+  wire width 1 output 29 \mul_op__oe__oe_ok$9
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 2 \main_sr_op__input_carry
+  wire width 1 output 30 \mul_op__invert_a$10
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \main_sr_op__output_carry
+  wire width 1 output 31 \mul_op__zero_a$11
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \main_sr_op__input_cr
+  wire width 1 output 32 \mul_op__invert_out$12
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \main_sr_op__output_cr
+  wire width 1 output 33 \mul_op__write_cr0$13
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \main_sr_op__is_32bit
+  wire width 1 output 34 \mul_op__is_32bit$14
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \main_sr_op__is_signed
+  wire width 1 output 35 \mul_op__is_signed$15
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 32 \main_sr_op__insn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
-  wire width 64 \main_ra
+  wire width 32 output 36 \mul_op__insn$16
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
-  wire width 64 \main_rb
+  wire width 129 output 37 \o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
-  wire width 64 \main_rc
+  wire width 1 output 38 \xer_so$17
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23"
+  wire width 1 output 39 \neg_res$18
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24"
+  wire width 1 output 40 \neg_res32$19
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28"
+  wire width 129 $20
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28"
+  wire width 128 $21
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28"
+  cell $mul $22
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 64
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 64
+    parameter \Y_WIDTH 128
+    connect \A \ra
+    connect \B \rb
+    connect \Y $21
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28"
+  cell $pos $23
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 128
+    parameter \Y_WIDTH 129
+    connect \A $21
+    connect \Y $20
+  end
+  process $group_0
+    assign \o 129'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
+    assign \o $20
+    sync init
+  end
+  process $group_1
+    assign \neg_res$18 1'0
+    assign \neg_res$18 \neg_res
+    sync init
+  end
+  process $group_2
+    assign \neg_res32$19 1'0
+    assign \neg_res32$19 \neg_res32
+    sync init
+  end
+  process $group_3
+    assign \xer_so$17 1'0
+    assign \xer_so$17 \xer_so
+    sync init
+  end
+  process $group_4
+    assign \muxid$1 2'00
+    assign \muxid$1 \muxid
+    sync init
+  end
+  process $group_5
+    assign \mul_op__insn_type$2 7'0000000
+    assign \mul_op__fn_unit$3 11'00000000000
+    assign \mul_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \mul_op__imm_data__imm_ok$5 1'0
+    assign \mul_op__rc__rc$6 1'0
+    assign \mul_op__rc__rc_ok$7 1'0
+    assign \mul_op__oe__oe$8 1'0
+    assign \mul_op__oe__oe_ok$9 1'0
+    assign \mul_op__invert_a$10 1'0
+    assign \mul_op__zero_a$11 1'0
+    assign \mul_op__invert_out$12 1'0
+    assign \mul_op__write_cr0$13 1'0
+    assign \mul_op__is_32bit$14 1'0
+    assign \mul_op__is_signed$15 1'0
+    assign \mul_op__insn$16 32'00000000000000000000000000000000
+    assign { \mul_op__insn$16 \mul_op__is_signed$15 \mul_op__is_32bit$14 \mul_op__write_cr0$13 \mul_op__invert_out$12 \mul_op__zero_a$11 \mul_op__invert_a$10 { \mul_op__oe__oe_ok$9 \mul_op__oe__oe$8 } { \mul_op__rc__rc_ok$7 \mul_op__rc__rc$6 } { \mul_op__imm_data__imm_ok$5 \mul_op__imm_data__imm$4 } \mul_op__fn_unit$3 \mul_op__insn_type$2 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__invert_out \mul_op__zero_a \mul_op__invert_a { \mul_op__oe__oe_ok \mul_op__oe__oe } { \mul_op__rc__rc_ok \mul_op__rc__rc } { \mul_op__imm_data__imm_ok \mul_op__imm_data__imm } \mul_op__fn_unit \mul_op__insn_type }
+    sync init
+  end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe2"
+module \mul_pipe2
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153"
+  wire width 1 input 2 \p_valid_i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154"
+  wire width 1 output 3 \p_ready_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
-  wire width 2 \main_muxid$38
+  wire width 2 input 4 \muxid
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
   attribute \enum_value_0000001 "OP_NOP"
@@ -102938,7 +103431,7 @@ module \pipe$89
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 7 \main_sr_op__insn_type$39
+  wire width 7 input 5 \mul_op__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -102952,85 +103445,51 @@ module \pipe$89
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 11 \main_sr_op__fn_unit$40
+  wire width 11 input 6 \mul_op__fn_unit
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 64 \main_sr_op__imm_data__imm$41
+  wire width 64 input 7 \mul_op__imm_data__imm
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \main_sr_op__imm_data__imm_ok$42
+  wire width 1 input 8 \mul_op__imm_data__imm_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \main_sr_op__rc__rc$43
+  wire width 1 input 9 \mul_op__rc__rc
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \main_sr_op__rc__rc_ok$44
+  wire width 1 input 10 \mul_op__rc__rc_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \main_sr_op__oe__oe$45
+  wire width 1 input 11 \mul_op__oe__oe
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \main_sr_op__oe__oe_ok$46
-  attribute \enum_base_type "CryIn"
-  attribute \enum_value_00 "ZERO"
-  attribute \enum_value_01 "ONE"
-  attribute \enum_value_10 "CA"
+  wire width 1 input 12 \mul_op__oe__oe_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 2 \main_sr_op__input_carry$47
+  wire width 1 input 13 \mul_op__invert_a
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \main_sr_op__output_carry$48
+  wire width 1 input 14 \mul_op__zero_a
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \main_sr_op__input_cr$49
+  wire width 1 input 15 \mul_op__invert_out
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \main_sr_op__output_cr$50
+  wire width 1 input 16 \mul_op__write_cr0
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \main_sr_op__is_32bit$51
+  wire width 1 input 17 \mul_op__is_32bit
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \main_sr_op__is_signed$52
+  wire width 1 input 18 \mul_op__is_signed
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 32 \main_sr_op__insn$53
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 64 \main_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 \main_o_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 2 \main_xer_ca
-  cell \main$93 \main
-    connect \muxid \main_muxid
-    connect \sr_op__insn_type \main_sr_op__insn_type
-    connect \sr_op__fn_unit \main_sr_op__fn_unit
-    connect \sr_op__imm_data__imm \main_sr_op__imm_data__imm
-    connect \sr_op__imm_data__imm_ok \main_sr_op__imm_data__imm_ok
-    connect \sr_op__rc__rc \main_sr_op__rc__rc
-    connect \sr_op__rc__rc_ok \main_sr_op__rc__rc_ok
-    connect \sr_op__oe__oe \main_sr_op__oe__oe
-    connect \sr_op__oe__oe_ok \main_sr_op__oe__oe_ok
-    connect \sr_op__input_carry \main_sr_op__input_carry
-    connect \sr_op__output_carry \main_sr_op__output_carry
-    connect \sr_op__input_cr \main_sr_op__input_cr
-    connect \sr_op__output_cr \main_sr_op__output_cr
-    connect \sr_op__is_32bit \main_sr_op__is_32bit
-    connect \sr_op__is_signed \main_sr_op__is_signed
-    connect \sr_op__insn \main_sr_op__insn
-    connect \ra \main_ra
-    connect \rb \main_rb
-    connect \rc \main_rc
-    connect \muxid$1 \main_muxid$38
-    connect \sr_op__insn_type$2 \main_sr_op__insn_type$39
-    connect \sr_op__fn_unit$3 \main_sr_op__fn_unit$40
-    connect \sr_op__imm_data__imm$4 \main_sr_op__imm_data__imm$41
-    connect \sr_op__imm_data__imm_ok$5 \main_sr_op__imm_data__imm_ok$42
-    connect \sr_op__rc__rc$6 \main_sr_op__rc__rc$43
-    connect \sr_op__rc__rc_ok$7 \main_sr_op__rc__rc_ok$44
-    connect \sr_op__oe__oe$8 \main_sr_op__oe__oe$45
-    connect \sr_op__oe__oe_ok$9 \main_sr_op__oe__oe_ok$46
-    connect \sr_op__input_carry$10 \main_sr_op__input_carry$47
-    connect \sr_op__output_carry$11 \main_sr_op__output_carry$48
-    connect \sr_op__input_cr$12 \main_sr_op__input_cr$49
-    connect \sr_op__output_cr$13 \main_sr_op__output_cr$50
-    connect \sr_op__is_32bit$14 \main_sr_op__is_32bit$51
-    connect \sr_op__is_signed$15 \main_sr_op__is_signed$52
-    connect \sr_op__insn$16 \main_sr_op__insn$53
-    connect \o \main_o
-    connect \o_ok \main_o_ok
-    connect \xer_ca \main_xer_ca
-  end
+  wire width 32 input 19 \mul_op__insn
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
+  wire width 64 input 20 \ra
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
+  wire width 64 input 21 \rb
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
+  wire width 1 input 22 \xer_so
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11"
+  wire width 1 input 23 \neg_res
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12"
+  wire width 1 input 24 \neg_res32
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
+  wire width 1 output 25 \n_valid_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
+  wire width 1 input 26 \n_ready_i
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
-  wire width 2 \output_muxid
+  wire width 2 output 27 \muxid$1
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
+  wire width 2 \muxid$1$next
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
   attribute \enum_value_0000001 "OP_NOP"
@@ -103105,7 +103564,9 @@ module \pipe$89
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 7 \output_sr_op__insn_type
+  wire width 7 output 28 \mul_op__insn_type$2
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 \mul_op__insn_type$2$next
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -103119,47 +103580,87 @@ module \pipe$89
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 11 \output_sr_op__fn_unit
+  wire width 11 output 29 \mul_op__fn_unit$3
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 64 \output_sr_op__imm_data__imm
+  wire width 11 \mul_op__fn_unit$3$next
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \output_sr_op__imm_data__imm_ok
+  wire width 64 output 30 \mul_op__imm_data__imm$4
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \output_sr_op__rc__rc
+  wire width 64 \mul_op__imm_data__imm$4$next
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \output_sr_op__rc__rc_ok
+  wire width 1 output 31 \mul_op__imm_data__imm_ok$5
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \output_sr_op__oe__oe
+  wire width 1 \mul_op__imm_data__imm_ok$5$next
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \output_sr_op__oe__oe_ok
-  attribute \enum_base_type "CryIn"
-  attribute \enum_value_00 "ZERO"
-  attribute \enum_value_01 "ONE"
-  attribute \enum_value_10 "CA"
+  wire width 1 output 32 \mul_op__rc__rc$6
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 2 \output_sr_op__input_carry
+  wire width 1 \mul_op__rc__rc$6$next
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \output_sr_op__output_carry
+  wire width 1 output 33 \mul_op__rc__rc_ok$7
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \output_sr_op__input_cr
+  wire width 1 \mul_op__rc__rc_ok$7$next
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \output_sr_op__output_cr
+  wire width 1 output 34 \mul_op__oe__oe$8
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \output_sr_op__is_32bit
+  wire width 1 \mul_op__oe__oe$8$next
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \output_sr_op__is_signed
+  wire width 1 output 35 \mul_op__oe__oe_ok$9
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 32 \output_sr_op__insn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 64 \output_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 \output_o_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 4 \output_cr_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 2 \output_xer_ca
+  wire width 1 \mul_op__oe__oe_ok$9$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 36 \mul_op__invert_a$10
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_op__invert_a$10$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 37 \mul_op__zero_a$11
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_op__zero_a$11$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 38 \mul_op__invert_out$12
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_op__invert_out$12$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 39 \mul_op__write_cr0$13
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_op__write_cr0$13$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 40 \mul_op__is_32bit$14
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_op__is_32bit$14$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 41 \mul_op__is_signed$15
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_op__is_signed$15$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 output 42 \mul_op__insn$16
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \mul_op__insn$16$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
+  wire width 129 output 43 \o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
+  wire width 129 \o$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
+  wire width 1 output 44 \xer_so$17
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
+  wire width 1 \xer_so$17$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23"
+  wire width 1 output 45 \neg_res$18
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23"
+  wire width 1 \neg_res$18$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24"
+  wire width 1 output 46 \neg_res32$19
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24"
+  wire width 1 \neg_res32$19$next
+  cell \p$92 \p
+    connect \p_valid_i \p_valid_i
+    connect \p_ready_o \p_ready_o
+  end
+  cell \n$93 \n
+    connect \n_valid_o \n_valid_o
+    connect \n_ready_i \n_ready_i
+  end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
-  wire width 2 \output_muxid$54
+  wire width 2 \mul2_muxid
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
   attribute \enum_value_0000001 "OP_NOP"
@@ -103234,7 +103735,7 @@ module \pipe$89
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 7 \output_sr_op__insn_type$55
+  wire width 7 \mul2_mul_op__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -103248,279 +103749,45 @@ module \pipe$89
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 11 \output_sr_op__fn_unit$56
+  wire width 11 \mul2_mul_op__fn_unit
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 64 \output_sr_op__imm_data__imm$57
+  wire width 64 \mul2_mul_op__imm_data__imm
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \output_sr_op__imm_data__imm_ok$58
+  wire width 1 \mul2_mul_op__imm_data__imm_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \output_sr_op__rc__rc$59
+  wire width 1 \mul2_mul_op__rc__rc
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \output_sr_op__rc__rc_ok$60
+  wire width 1 \mul2_mul_op__rc__rc_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \output_sr_op__oe__oe$61
+  wire width 1 \mul2_mul_op__oe__oe
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \output_sr_op__oe__oe_ok$62
-  attribute \enum_base_type "CryIn"
-  attribute \enum_value_00 "ZERO"
-  attribute \enum_value_01 "ONE"
-  attribute \enum_value_10 "CA"
+  wire width 1 \mul2_mul_op__oe__oe_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 2 \output_sr_op__input_carry$63
+  wire width 1 \mul2_mul_op__invert_a
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \output_sr_op__output_carry$64
+  wire width 1 \mul2_mul_op__zero_a
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \output_sr_op__input_cr$65
+  wire width 1 \mul2_mul_op__invert_out
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \output_sr_op__output_cr$66
+  wire width 1 \mul2_mul_op__write_cr0
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \output_sr_op__is_32bit$67
+  wire width 1 \mul2_mul_op__is_32bit
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \output_sr_op__is_signed$68
+  wire width 1 \mul2_mul_op__is_signed
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 32 \output_sr_op__insn$69
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 64 \output_o$70
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 \output_o_ok$71
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 4 \output_cr_a$72
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 \output_cr_a_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 2 \output_xer_ca$73
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 \output_xer_ca_ok
-  cell \output$94 \output
-    connect \muxid \output_muxid
-    connect \sr_op__insn_type \output_sr_op__insn_type
-    connect \sr_op__fn_unit \output_sr_op__fn_unit
-    connect \sr_op__imm_data__imm \output_sr_op__imm_data__imm
-    connect \sr_op__imm_data__imm_ok \output_sr_op__imm_data__imm_ok
-    connect \sr_op__rc__rc \output_sr_op__rc__rc
-    connect \sr_op__rc__rc_ok \output_sr_op__rc__rc_ok
-    connect \sr_op__oe__oe \output_sr_op__oe__oe
-    connect \sr_op__oe__oe_ok \output_sr_op__oe__oe_ok
-    connect \sr_op__input_carry \output_sr_op__input_carry
-    connect \sr_op__output_carry \output_sr_op__output_carry
-    connect \sr_op__input_cr \output_sr_op__input_cr
-    connect \sr_op__output_cr \output_sr_op__output_cr
-    connect \sr_op__is_32bit \output_sr_op__is_32bit
-    connect \sr_op__is_signed \output_sr_op__is_signed
-    connect \sr_op__insn \output_sr_op__insn
-    connect \o \output_o
-    connect \o_ok \output_o_ok
-    connect \cr_a \output_cr_a
-    connect \xer_ca \output_xer_ca
-    connect \muxid$1 \output_muxid$54
-    connect \sr_op__insn_type$2 \output_sr_op__insn_type$55
-    connect \sr_op__fn_unit$3 \output_sr_op__fn_unit$56
-    connect \sr_op__imm_data__imm$4 \output_sr_op__imm_data__imm$57
-    connect \sr_op__imm_data__imm_ok$5 \output_sr_op__imm_data__imm_ok$58
-    connect \sr_op__rc__rc$6 \output_sr_op__rc__rc$59
-    connect \sr_op__rc__rc_ok$7 \output_sr_op__rc__rc_ok$60
-    connect \sr_op__oe__oe$8 \output_sr_op__oe__oe$61
-    connect \sr_op__oe__oe_ok$9 \output_sr_op__oe__oe_ok$62
-    connect \sr_op__input_carry$10 \output_sr_op__input_carry$63
-    connect \sr_op__output_carry$11 \output_sr_op__output_carry$64
-    connect \sr_op__input_cr$12 \output_sr_op__input_cr$65
-    connect \sr_op__output_cr$13 \output_sr_op__output_cr$66
-    connect \sr_op__is_32bit$14 \output_sr_op__is_32bit$67
-    connect \sr_op__is_signed$15 \output_sr_op__is_signed$68
-    connect \sr_op__insn$16 \output_sr_op__insn$69
-    connect \o$17 \output_o$70
-    connect \o_ok$18 \output_o_ok$71
-    connect \cr_a$19 \output_cr_a$72
-    connect \cr_a_ok \output_cr_a_ok
-    connect \xer_ca$20 \output_xer_ca$73
-    connect \xer_ca_ok \output_xer_ca_ok
-  end
-  process $group_0
-    assign \input_muxid 2'00
-    assign \input_muxid \muxid
-    sync init
-  end
-  process $group_1
-    assign \input_sr_op__insn_type 7'0000000
-    assign \input_sr_op__fn_unit 11'00000000000
-    assign \input_sr_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \input_sr_op__imm_data__imm_ok 1'0
-    assign \input_sr_op__rc__rc 1'0
-    assign \input_sr_op__rc__rc_ok 1'0
-    assign \input_sr_op__oe__oe 1'0
-    assign \input_sr_op__oe__oe_ok 1'0
-    assign { } 0'0
-    assign \input_sr_op__input_carry 2'00
-    assign \input_sr_op__output_carry 1'0
-    assign \input_sr_op__input_cr 1'0
-    assign \input_sr_op__output_cr 1'0
-    assign \input_sr_op__is_32bit 1'0
-    assign \input_sr_op__is_signed 1'0
-    assign \input_sr_op__insn 32'00000000000000000000000000000000
-    assign { \input_sr_op__insn \input_sr_op__is_signed \input_sr_op__is_32bit \input_sr_op__output_cr \input_sr_op__input_cr \input_sr_op__output_carry \input_sr_op__input_carry { } { \input_sr_op__oe__oe_ok \input_sr_op__oe__oe } { \input_sr_op__rc__rc_ok \input_sr_op__rc__rc } { \input_sr_op__imm_data__imm_ok \input_sr_op__imm_data__imm } \input_sr_op__fn_unit \input_sr_op__insn_type } { \sr_op__insn \sr_op__is_signed \sr_op__is_32bit \sr_op__output_cr \sr_op__input_cr \sr_op__output_carry \sr_op__input_carry { } { \sr_op__oe__oe_ok \sr_op__oe__oe } { \sr_op__rc__rc_ok \sr_op__rc__rc } { \sr_op__imm_data__imm_ok \sr_op__imm_data__imm } \sr_op__fn_unit \sr_op__insn_type }
-    sync init
-  end
-  process $group_17
-    assign \input_ra 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \input_ra \ra
-    sync init
-  end
-  process $group_18
-    assign \input_rb 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \input_rb \rb
-    sync init
-  end
-  process $group_19
-    assign \input_rc 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \input_rc \rc
-    sync init
-  end
-  process $group_20
-    assign \input_xer_ca 2'00
-    assign \input_xer_ca \xer_ca
-    sync init
-  end
-  process $group_21
-    assign \main_muxid 2'00
-    assign \main_muxid \input_muxid$18
-    sync init
-  end
-  process $group_22
-    assign \main_sr_op__insn_type 7'0000000
-    assign \main_sr_op__fn_unit 11'00000000000
-    assign \main_sr_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \main_sr_op__imm_data__imm_ok 1'0
-    assign \main_sr_op__rc__rc 1'0
-    assign \main_sr_op__rc__rc_ok 1'0
-    assign \main_sr_op__oe__oe 1'0
-    assign \main_sr_op__oe__oe_ok 1'0
-    assign { } 0'0
-    assign \main_sr_op__input_carry 2'00
-    assign \main_sr_op__output_carry 1'0
-    assign \main_sr_op__input_cr 1'0
-    assign \main_sr_op__output_cr 1'0
-    assign \main_sr_op__is_32bit 1'0
-    assign \main_sr_op__is_signed 1'0
-    assign \main_sr_op__insn 32'00000000000000000000000000000000
-    assign { \main_sr_op__insn \main_sr_op__is_signed \main_sr_op__is_32bit \main_sr_op__output_cr \main_sr_op__input_cr \main_sr_op__output_carry \main_sr_op__input_carry { } { \main_sr_op__oe__oe_ok \main_sr_op__oe__oe } { \main_sr_op__rc__rc_ok \main_sr_op__rc__rc } { \main_sr_op__imm_data__imm_ok \main_sr_op__imm_data__imm } \main_sr_op__fn_unit \main_sr_op__insn_type } { \input_sr_op__insn$33 \input_sr_op__is_signed$32 \input_sr_op__is_32bit$31 \input_sr_op__output_cr$30 \input_sr_op__input_cr$29 \input_sr_op__output_carry$28 \input_sr_op__input_carry$27 { } { \input_sr_op__oe__oe_ok$26 \input_sr_op__oe__oe$25 } { \input_sr_op__rc__rc_ok$24 \input_sr_op__rc__rc$23 } { \input_sr_op__imm_data__imm_ok$22 \input_sr_op__imm_data__imm$21 } \input_sr_op__fn_unit$20 \input_sr_op__insn_type$19 }
-    sync init
-  end
-  process $group_38
-    assign \main_ra 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \main_ra \input_ra$34
-    sync init
-  end
-  process $group_39
-    assign \main_rb 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \main_rb \input_rb$35
-    sync init
-  end
-  process $group_40
-    assign \main_rc 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \main_rc \input_rc$36
-    sync init
-  end
+  wire width 32 \mul2_mul_op__insn
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
-  wire width 2 \xer_ca$74
-  process $group_41
-    assign \xer_ca$74 2'00
-    assign \xer_ca$74 \input_xer_ca$37
-    sync init
-  end
-  process $group_42
-    assign \output_muxid 2'00
-    assign \output_muxid \main_muxid$38
-    sync init
-  end
-  process $group_43
-    assign \output_sr_op__insn_type 7'0000000
-    assign \output_sr_op__fn_unit 11'00000000000
-    assign \output_sr_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \output_sr_op__imm_data__imm_ok 1'0
-    assign \output_sr_op__rc__rc 1'0
-    assign \output_sr_op__rc__rc_ok 1'0
-    assign \output_sr_op__oe__oe 1'0
-    assign \output_sr_op__oe__oe_ok 1'0
-    assign { } 0'0
-    assign \output_sr_op__input_carry 2'00
-    assign \output_sr_op__output_carry 1'0
-    assign \output_sr_op__input_cr 1'0
-    assign \output_sr_op__output_cr 1'0
-    assign \output_sr_op__is_32bit 1'0
-    assign \output_sr_op__is_signed 1'0
-    assign \output_sr_op__insn 32'00000000000000000000000000000000
-    assign { \output_sr_op__insn \output_sr_op__is_signed \output_sr_op__is_32bit \output_sr_op__output_cr \output_sr_op__input_cr \output_sr_op__output_carry \output_sr_op__input_carry { } { \output_sr_op__oe__oe_ok \output_sr_op__oe__oe } { \output_sr_op__rc__rc_ok \output_sr_op__rc__rc } { \output_sr_op__imm_data__imm_ok \output_sr_op__imm_data__imm } \output_sr_op__fn_unit \output_sr_op__insn_type } { \main_sr_op__insn$53 \main_sr_op__is_signed$52 \main_sr_op__is_32bit$51 \main_sr_op__output_cr$50 \main_sr_op__input_cr$49 \main_sr_op__output_carry$48 \main_sr_op__input_carry$47 { } { \main_sr_op__oe__oe_ok$46 \main_sr_op__oe__oe$45 } { \main_sr_op__rc__rc_ok$44 \main_sr_op__rc__rc$43 } { \main_sr_op__imm_data__imm_ok$42 \main_sr_op__imm_data__imm$41 } \main_sr_op__fn_unit$40 \main_sr_op__insn_type$39 }
-    sync init
-  end
-  process $group_59
-    assign \output_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \output_o_ok 1'0
-    assign { \output_o_ok \output_o } { \main_o_ok \main_o }
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 \cr_a_ok$75
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 4 \cr_a$76
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 \cr_a_ok$77
-  process $group_61
-    assign \output_cr_a 4'0000
-    assign \cr_a_ok$75 1'0
-    assign { \cr_a_ok$75 \output_cr_a } { \cr_a_ok$77 \cr_a$76 }
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 \xer_ca_ok$78
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 \xer_ca_ok$79
-  process $group_63
-    assign \output_xer_ca 2'00
-    assign \xer_ca_ok$78 1'0
-    assign { \xer_ca_ok$78 \output_xer_ca } { \xer_ca_ok$79 \main_xer_ca }
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621"
-  wire width 1 \p_valid_i$80
-  process $group_65
-    assign \p_valid_i$80 1'0
-    assign \p_valid_i$80 \p_valid_i
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619"
-  wire width 1 \n_i_rdy_data
-  process $group_66
-    assign \n_i_rdy_data 1'0
-    assign \n_i_rdy_data \n_ready_i
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620"
-  wire width 1 \p_valid_i_p_ready_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624"
-  wire width 1 $81
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624"
-  cell $and $82
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \p_valid_i$80
-    connect \B \p_ready_o
-    connect \Y $81
-  end
-  process $group_67
-    assign \p_valid_i_p_ready_o 1'0
-    assign \p_valid_i_p_ready_o $81
-    sync init
-  end
+  wire width 64 \mul2_ra
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
+  wire width 64 \mul2_rb
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
+  wire width 1 \mul2_xer_so
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11"
+  wire width 1 \mul2_neg_res
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12"
+  wire width 1 \mul2_neg_res32
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
-  wire width 2 \muxid$83
-  process $group_68
-    assign \muxid$83 2'00
-    assign \muxid$83 \output_muxid$54
-    sync init
-  end
+  wire width 2 \mul2_muxid$20
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
   attribute \enum_value_0000001 "OP_NOP"
@@ -103595,7 +103862,7 @@ module \pipe$89
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 7 \sr_op__insn_type$84
+  wire width 7 \mul2_mul_op__insn_type$21
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -103609,308 +103876,174 @@ module \pipe$89
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 11 \sr_op__fn_unit$85
+  wire width 11 \mul2_mul_op__fn_unit$22
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 64 \sr_op__imm_data__imm$86
+  wire width 64 \mul2_mul_op__imm_data__imm$23
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \sr_op__imm_data__imm_ok$87
+  wire width 1 \mul2_mul_op__imm_data__imm_ok$24
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \sr_op__rc__rc$88
+  wire width 1 \mul2_mul_op__rc__rc$25
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \sr_op__rc__rc_ok$89
+  wire width 1 \mul2_mul_op__rc__rc_ok$26
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \sr_op__oe__oe$90
+  wire width 1 \mul2_mul_op__oe__oe$27
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \sr_op__oe__oe_ok$91
-  attribute \enum_base_type "CryIn"
-  attribute \enum_value_00 "ZERO"
-  attribute \enum_value_01 "ONE"
-  attribute \enum_value_10 "CA"
+  wire width 1 \mul2_mul_op__oe__oe_ok$28
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 2 \sr_op__input_carry$92
+  wire width 1 \mul2_mul_op__invert_a$29
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \sr_op__output_carry$93
+  wire width 1 \mul2_mul_op__zero_a$30
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \sr_op__input_cr$94
+  wire width 1 \mul2_mul_op__invert_out$31
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \sr_op__output_cr$95
+  wire width 1 \mul2_mul_op__write_cr0$32
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \sr_op__is_32bit$96
+  wire width 1 \mul2_mul_op__is_32bit$33
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \sr_op__is_signed$97
+  wire width 1 \mul2_mul_op__is_signed$34
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 32 \sr_op__insn$98
-  process $group_69
-    assign \sr_op__insn_type$84 7'0000000
-    assign \sr_op__fn_unit$85 11'00000000000
-    assign \sr_op__imm_data__imm$86 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \sr_op__imm_data__imm_ok$87 1'0
-    assign \sr_op__rc__rc$88 1'0
-    assign \sr_op__rc__rc_ok$89 1'0
-    assign \sr_op__oe__oe$90 1'0
-    assign \sr_op__oe__oe_ok$91 1'0
-    assign { } 0'0
-    assign \sr_op__input_carry$92 2'00
-    assign \sr_op__output_carry$93 1'0
-    assign \sr_op__input_cr$94 1'0
-    assign \sr_op__output_cr$95 1'0
-    assign \sr_op__is_32bit$96 1'0
-    assign \sr_op__is_signed$97 1'0
-    assign \sr_op__insn$98 32'00000000000000000000000000000000
-    assign { \sr_op__insn$98 \sr_op__is_signed$97 \sr_op__is_32bit$96 \sr_op__output_cr$95 \sr_op__input_cr$94 \sr_op__output_carry$93 \sr_op__input_carry$92 { } { \sr_op__oe__oe_ok$91 \sr_op__oe__oe$90 } { \sr_op__rc__rc_ok$89 \sr_op__rc__rc$88 } { \sr_op__imm_data__imm_ok$87 \sr_op__imm_data__imm$86 } \sr_op__fn_unit$85 \sr_op__insn_type$84 } { \output_sr_op__insn$69 \output_sr_op__is_signed$68 \output_sr_op__is_32bit$67 \output_sr_op__output_cr$66 \output_sr_op__input_cr$65 \output_sr_op__output_carry$64 \output_sr_op__input_carry$63 { } { \output_sr_op__oe__oe_ok$62 \output_sr_op__oe__oe$61 } { \output_sr_op__rc__rc_ok$60 \output_sr_op__rc__rc$59 } { \output_sr_op__imm_data__imm_ok$58 \output_sr_op__imm_data__imm$57 } \output_sr_op__fn_unit$56 \output_sr_op__insn_type$55 }
-    sync init
+  wire width 32 \mul2_mul_op__insn$35
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
+  wire width 129 \mul2_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
+  wire width 1 \mul2_xer_so$36
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23"
+  wire width 1 \mul2_neg_res$37
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24"
+  wire width 1 \mul2_neg_res32$38
+  cell \mul2 \mul2
+    connect \muxid \mul2_muxid
+    connect \mul_op__insn_type \mul2_mul_op__insn_type
+    connect \mul_op__fn_unit \mul2_mul_op__fn_unit
+    connect \mul_op__imm_data__imm \mul2_mul_op__imm_data__imm
+    connect \mul_op__imm_data__imm_ok \mul2_mul_op__imm_data__imm_ok
+    connect \mul_op__rc__rc \mul2_mul_op__rc__rc
+    connect \mul_op__rc__rc_ok \mul2_mul_op__rc__rc_ok
+    connect \mul_op__oe__oe \mul2_mul_op__oe__oe
+    connect \mul_op__oe__oe_ok \mul2_mul_op__oe__oe_ok
+    connect \mul_op__invert_a \mul2_mul_op__invert_a
+    connect \mul_op__zero_a \mul2_mul_op__zero_a
+    connect \mul_op__invert_out \mul2_mul_op__invert_out
+    connect \mul_op__write_cr0 \mul2_mul_op__write_cr0
+    connect \mul_op__is_32bit \mul2_mul_op__is_32bit
+    connect \mul_op__is_signed \mul2_mul_op__is_signed
+    connect \mul_op__insn \mul2_mul_op__insn
+    connect \ra \mul2_ra
+    connect \rb \mul2_rb
+    connect \xer_so \mul2_xer_so
+    connect \neg_res \mul2_neg_res
+    connect \neg_res32 \mul2_neg_res32
+    connect \muxid$1 \mul2_muxid$20
+    connect \mul_op__insn_type$2 \mul2_mul_op__insn_type$21
+    connect \mul_op__fn_unit$3 \mul2_mul_op__fn_unit$22
+    connect \mul_op__imm_data__imm$4 \mul2_mul_op__imm_data__imm$23
+    connect \mul_op__imm_data__imm_ok$5 \mul2_mul_op__imm_data__imm_ok$24
+    connect \mul_op__rc__rc$6 \mul2_mul_op__rc__rc$25
+    connect \mul_op__rc__rc_ok$7 \mul2_mul_op__rc__rc_ok$26
+    connect \mul_op__oe__oe$8 \mul2_mul_op__oe__oe$27
+    connect \mul_op__oe__oe_ok$9 \mul2_mul_op__oe__oe_ok$28
+    connect \mul_op__invert_a$10 \mul2_mul_op__invert_a$29
+    connect \mul_op__zero_a$11 \mul2_mul_op__zero_a$30
+    connect \mul_op__invert_out$12 \mul2_mul_op__invert_out$31
+    connect \mul_op__write_cr0$13 \mul2_mul_op__write_cr0$32
+    connect \mul_op__is_32bit$14 \mul2_mul_op__is_32bit$33
+    connect \mul_op__is_signed$15 \mul2_mul_op__is_signed$34
+    connect \mul_op__insn$16 \mul2_mul_op__insn$35
+    connect \o \mul2_o
+    connect \xer_so$17 \mul2_xer_so$36
+    connect \neg_res$18 \mul2_neg_res$37
+    connect \neg_res32$19 \mul2_neg_res32$38
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 64 \o$99
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 \o_ok$100
-  process $group_85
-    assign \o$99 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \o_ok$100 1'0
-    assign { \o_ok$100 \o$99 } { \output_o_ok$71 \output_o$70 }
+  process $group_0
+    assign \mul2_muxid 2'00
+    assign \mul2_muxid \muxid
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 4 \cr_a$101
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 \cr_a_ok$102
-  process $group_87
-    assign \cr_a$101 4'0000
-    assign \cr_a_ok$102 1'0
-    assign { \cr_a_ok$102 \cr_a$101 } { \output_cr_a_ok \output_cr_a$72 }
+  process $group_1
+    assign \mul2_mul_op__insn_type 7'0000000
+    assign \mul2_mul_op__fn_unit 11'00000000000
+    assign \mul2_mul_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \mul2_mul_op__imm_data__imm_ok 1'0
+    assign \mul2_mul_op__rc__rc 1'0
+    assign \mul2_mul_op__rc__rc_ok 1'0
+    assign \mul2_mul_op__oe__oe 1'0
+    assign \mul2_mul_op__oe__oe_ok 1'0
+    assign \mul2_mul_op__invert_a 1'0
+    assign \mul2_mul_op__zero_a 1'0
+    assign \mul2_mul_op__invert_out 1'0
+    assign \mul2_mul_op__write_cr0 1'0
+    assign \mul2_mul_op__is_32bit 1'0
+    assign \mul2_mul_op__is_signed 1'0
+    assign \mul2_mul_op__insn 32'00000000000000000000000000000000
+    assign { \mul2_mul_op__insn \mul2_mul_op__is_signed \mul2_mul_op__is_32bit \mul2_mul_op__write_cr0 \mul2_mul_op__invert_out \mul2_mul_op__zero_a \mul2_mul_op__invert_a { \mul2_mul_op__oe__oe_ok \mul2_mul_op__oe__oe } { \mul2_mul_op__rc__rc_ok \mul2_mul_op__rc__rc } { \mul2_mul_op__imm_data__imm_ok \mul2_mul_op__imm_data__imm } \mul2_mul_op__fn_unit \mul2_mul_op__insn_type } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__invert_out \mul_op__zero_a \mul_op__invert_a { \mul_op__oe__oe_ok \mul_op__oe__oe } { \mul_op__rc__rc_ok \mul_op__rc__rc } { \mul_op__imm_data__imm_ok \mul_op__imm_data__imm } \mul_op__fn_unit \mul_op__insn_type }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 2 \xer_ca$103
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 \xer_ca_ok$104
-  process $group_89
-    assign \xer_ca$103 2'00
-    assign \xer_ca_ok$104 1'0
-    assign { \xer_ca_ok$104 \xer_ca$103 } { \output_xer_ca_ok \output_xer_ca$73 }
+  process $group_16
+    assign \mul2_ra 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \mul2_ra \ra
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615"
-  wire width 1 \r_busy
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615"
-  wire width 1 \r_busy$next
-  process $group_91
-    assign \r_busy$next \r_busy
-    attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
-    switch { \n_i_rdy_data \p_valid_i_p_ready_o }
-      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
-      case 2'-1
-        assign \r_busy$next 1'1
-      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
-      case 2'1-
-        assign \r_busy$next 1'0
-    end
-    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
-      case 1'1
-        assign \r_busy$next 1'0
-    end
+  process $group_17
+    assign \mul2_rb 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \mul2_rb \rb
     sync init
-      update \r_busy 1'0
-    sync posedge \clk
-      update \r_busy \r_busy$next
   end
-  process $group_92
-    assign \muxid$1$next \muxid$1
-    attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
-    switch { \n_i_rdy_data \p_valid_i_p_ready_o }
-      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
-      case 2'-1
-        assign \muxid$1$next \muxid$83
-      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
-      case 2'1-
-        assign \muxid$1$next \muxid$83
-    end
+  process $group_18
+    assign \mul2_xer_so 1'0
+    assign \mul2_xer_so \xer_so
     sync init
-      update \muxid$1 2'00
-    sync posedge \clk
-      update \muxid$1 \muxid$1$next
   end
-  process $group_93
-    assign \sr_op__insn_type$2$next \sr_op__insn_type$2
-    assign \sr_op__fn_unit$3$next \sr_op__fn_unit$3
-    assign \sr_op__imm_data__imm$4$next \sr_op__imm_data__imm$4
-    assign \sr_op__imm_data__imm_ok$5$next \sr_op__imm_data__imm_ok$5
-    assign \sr_op__rc__rc$6$next \sr_op__rc__rc$6
-    assign \sr_op__rc__rc_ok$7$next \sr_op__rc__rc_ok$7
-    assign \sr_op__oe__oe$8$next \sr_op__oe__oe$8
-    assign \sr_op__oe__oe_ok$9$next \sr_op__oe__oe_ok$9
-    assign { } { }
-    assign \sr_op__input_carry$10$next \sr_op__input_carry$10
-    assign \sr_op__output_carry$11$next \sr_op__output_carry$11
-    assign \sr_op__input_cr$12$next \sr_op__input_cr$12
-    assign \sr_op__output_cr$13$next \sr_op__output_cr$13
-    assign \sr_op__is_32bit$14$next \sr_op__is_32bit$14
-    assign \sr_op__is_signed$15$next \sr_op__is_signed$15
-    assign \sr_op__insn$16$next \sr_op__insn$16
-    attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
-    switch { \n_i_rdy_data \p_valid_i_p_ready_o }
-      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
-      case 2'-1
-        assign { \sr_op__insn$16$next \sr_op__is_signed$15$next \sr_op__is_32bit$14$next \sr_op__output_cr$13$next \sr_op__input_cr$12$next \sr_op__output_carry$11$next \sr_op__input_carry$10$next { } { \sr_op__oe__oe_ok$9$next \sr_op__oe__oe$8$next } { \sr_op__rc__rc_ok$7$next \sr_op__rc__rc$6$next } { \sr_op__imm_data__imm_ok$5$next \sr_op__imm_data__imm$4$next } \sr_op__fn_unit$3$next \sr_op__insn_type$2$next } { \sr_op__insn$98 \sr_op__is_signed$97 \sr_op__is_32bit$96 \sr_op__output_cr$95 \sr_op__input_cr$94 \sr_op__output_carry$93 \sr_op__input_carry$92 { } { \sr_op__oe__oe_ok$91 \sr_op__oe__oe$90 } { \sr_op__rc__rc_ok$89 \sr_op__rc__rc$88 } { \sr_op__imm_data__imm_ok$87 \sr_op__imm_data__imm$86 } \sr_op__fn_unit$85 \sr_op__insn_type$84 }
-      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
-      case 2'1-
-        assign { \sr_op__insn$16$next \sr_op__is_signed$15$next \sr_op__is_32bit$14$next \sr_op__output_cr$13$next \sr_op__input_cr$12$next \sr_op__output_carry$11$next \sr_op__input_carry$10$next { } { \sr_op__oe__oe_ok$9$next \sr_op__oe__oe$8$next } { \sr_op__rc__rc_ok$7$next \sr_op__rc__rc$6$next } { \sr_op__imm_data__imm_ok$5$next \sr_op__imm_data__imm$4$next } \sr_op__fn_unit$3$next \sr_op__insn_type$2$next } { \sr_op__insn$98 \sr_op__is_signed$97 \sr_op__is_32bit$96 \sr_op__output_cr$95 \sr_op__input_cr$94 \sr_op__output_carry$93 \sr_op__input_carry$92 { } { \sr_op__oe__oe_ok$91 \sr_op__oe__oe$90 } { \sr_op__rc__rc_ok$89 \sr_op__rc__rc$88 } { \sr_op__imm_data__imm_ok$87 \sr_op__imm_data__imm$86 } \sr_op__fn_unit$85 \sr_op__insn_type$84 }
-    end
-    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
-      case 1'1
-        assign \sr_op__imm_data__imm$4$next 64'0000000000000000000000000000000000000000000000000000000000000000
-        assign \sr_op__imm_data__imm_ok$5$next 1'0
-        assign \sr_op__rc__rc$6$next 1'0
-        assign \sr_op__rc__rc_ok$7$next 1'0
-        assign \sr_op__oe__oe$8$next 1'0
-        assign \sr_op__oe__oe_ok$9$next 1'0
-    end
+  process $group_19
+    assign \mul2_neg_res 1'0
+    assign \mul2_neg_res \neg_res
     sync init
-      update \sr_op__insn_type$2 7'0000000
-      update \sr_op__fn_unit$3 11'00000000000
-      update \sr_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000
-      update \sr_op__imm_data__imm_ok$5 1'0
-      update \sr_op__rc__rc$6 1'0
-      update \sr_op__rc__rc_ok$7 1'0
-      update \sr_op__oe__oe$8 1'0
-      update \sr_op__oe__oe_ok$9 1'0
-      update { } 0'0
-      update \sr_op__input_carry$10 2'00
-      update \sr_op__output_carry$11 1'0
-      update \sr_op__input_cr$12 1'0
-      update \sr_op__output_cr$13 1'0
-      update \sr_op__is_32bit$14 1'0
-      update \sr_op__is_signed$15 1'0
-      update \sr_op__insn$16 32'00000000000000000000000000000000
-    sync posedge \clk
-      update \sr_op__insn_type$2 \sr_op__insn_type$2$next
-      update \sr_op__fn_unit$3 \sr_op__fn_unit$3$next
-      update \sr_op__imm_data__imm$4 \sr_op__imm_data__imm$4$next
-      update \sr_op__imm_data__imm_ok$5 \sr_op__imm_data__imm_ok$5$next
-      update \sr_op__rc__rc$6 \sr_op__rc__rc$6$next
-      update \sr_op__rc__rc_ok$7 \sr_op__rc__rc_ok$7$next
-      update \sr_op__oe__oe$8 \sr_op__oe__oe$8$next
-      update \sr_op__oe__oe_ok$9 \sr_op__oe__oe_ok$9$next
-      update { } { }
-      update \sr_op__input_carry$10 \sr_op__input_carry$10$next
-      update \sr_op__output_carry$11 \sr_op__output_carry$11$next
-      update \sr_op__input_cr$12 \sr_op__input_cr$12$next
-      update \sr_op__output_cr$13 \sr_op__output_cr$13$next
-      update \sr_op__is_32bit$14 \sr_op__is_32bit$14$next
-      update \sr_op__is_signed$15 \sr_op__is_signed$15$next
-      update \sr_op__insn$16 \sr_op__insn$16$next
   end
-  process $group_109
-    assign \o$next \o
-    assign \o_ok$next \o_ok
-    attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
-    switch { \n_i_rdy_data \p_valid_i_p_ready_o }
-      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
-      case 2'-1
-        assign { \o_ok$next \o$next } { \o_ok$100 \o$99 }
-      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
-      case 2'1-
-        assign { \o_ok$next \o$next } { \o_ok$100 \o$99 }
-    end
-    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
-      case 1'1
-        assign \o_ok$next 1'0
-    end
+  process $group_20
+    assign \mul2_neg_res32 1'0
+    assign \mul2_neg_res32 \neg_res32
     sync init
-      update \o 64'0000000000000000000000000000000000000000000000000000000000000000
-      update \o_ok 1'0
-    sync posedge \clk
-      update \o \o$next
-      update \o_ok \o_ok$next
   end
-  process $group_111
-    assign \cr_a$next \cr_a
-    assign \cr_a_ok$next \cr_a_ok
-    attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
-    switch { \n_i_rdy_data \p_valid_i_p_ready_o }
-      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
-      case 2'-1
-        assign { \cr_a_ok$next \cr_a$next } { \cr_a_ok$102 \cr_a$101 }
-      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
-      case 2'1-
-        assign { \cr_a_ok$next \cr_a$next } { \cr_a_ok$102 \cr_a$101 }
-    end
-    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
-      case 1'1
-        assign \cr_a_ok$next 1'0
-    end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621"
+  wire width 1 \p_valid_i$39
+  process $group_21
+    assign \p_valid_i$39 1'0
+    assign \p_valid_i$39 \p_valid_i
     sync init
-      update \cr_a 4'0000
-      update \cr_a_ok 1'0
-    sync posedge \clk
-      update \cr_a \cr_a$next
-      update \cr_a_ok \cr_a_ok$next
   end
-  process $group_113
-    assign \xer_ca$17$next \xer_ca$17
-    assign \xer_ca_ok$next \xer_ca_ok
-    attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
-    switch { \n_i_rdy_data \p_valid_i_p_ready_o }
-      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
-      case 2'-1
-        assign { \xer_ca_ok$next \xer_ca$17$next } { \xer_ca_ok$104 \xer_ca$103 }
-      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
-      case 2'1-
-        assign { \xer_ca_ok$next \xer_ca$17$next } { \xer_ca_ok$104 \xer_ca$103 }
-    end
-    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
-      case 1'1
-        assign \xer_ca_ok$next 1'0
-    end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619"
+  wire width 1 \n_i_rdy_data
+  process $group_22
+    assign \n_i_rdy_data 1'0
+    assign \n_i_rdy_data \n_ready_i
     sync init
-      update \xer_ca$17 2'00
-      update \xer_ca_ok 1'0
-    sync posedge \clk
-      update \xer_ca$17 \xer_ca$17$next
-      update \xer_ca_ok \xer_ca_ok$next
   end
-  process $group_115
-    assign \n_valid_o 1'0
-    assign \n_valid_o \r_busy
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620"
+  wire width 1 \p_valid_i_p_ready_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624"
+  wire width 1 $40
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624"
+  cell $and $41
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \p_valid_i$39
+    connect \B \p_ready_o
+    connect \Y $40
+  end
+  process $group_23
+    assign \p_valid_i_p_ready_o 1'0
+    assign \p_valid_i_p_ready_o $40
     sync init
   end
-  process $group_116
-    assign \p_ready_o 1'0
-    assign \p_ready_o \n_i_rdy_data
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
+  wire width 2 \muxid$42
+  process $group_24
+    assign \muxid$42 2'00
+    assign \muxid$42 \mul2_muxid$20
     sync init
   end
-  connect \cr_a$76 4'0000
-  connect \cr_a_ok$77 1'0
-  connect \xer_ca_ok$79 1'0
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0"
-module \alu_shift_rot0
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 2 \o_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 3 \cr_a_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 4 \xer_ca_ok
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
-  wire width 1 output 5 \n_valid_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
-  wire width 1 input 6 \n_ready_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 64 output 7 \o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 4 output 8 \cr_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 2 output 9 \xer_ca
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
   attribute \enum_value_0000001 "OP_NOP"
@@ -103985,7 +104118,7 @@ module \alu_shift_rot0
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 7 input 10 \sr_op__insn_type
+  wire width 7 \mul_op__insn_type$43
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -103999,196 +104132,325 @@ module \alu_shift_rot0
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 11 input 11 \sr_op__fn_unit
+  wire width 11 \mul_op__fn_unit$44
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 64 input 12 \sr_op__imm_data__imm
+  wire width 64 \mul_op__imm_data__imm$45
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 13 \sr_op__imm_data__imm_ok
+  wire width 1 \mul_op__imm_data__imm_ok$46
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 14 \sr_op__rc__rc
+  wire width 1 \mul_op__rc__rc$47
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 15 \sr_op__rc__rc_ok
+  wire width 1 \mul_op__rc__rc_ok$48
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 16 \sr_op__oe__oe
+  wire width 1 \mul_op__oe__oe$49
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 17 \sr_op__oe__oe_ok
-  attribute \enum_base_type "CryIn"
-  attribute \enum_value_00 "ZERO"
-  attribute \enum_value_01 "ONE"
-  attribute \enum_value_10 "CA"
+  wire width 1 \mul_op__oe__oe_ok$50
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 2 input 19 \sr_op__input_carry
+  wire width 1 \mul_op__invert_a$51
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 20 \sr_op__output_carry
+  wire width 1 \mul_op__zero_a$52
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 21 \sr_op__input_cr
+  wire width 1 \mul_op__invert_out$53
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 22 \sr_op__output_cr
+  wire width 1 \mul_op__write_cr0$54
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 23 \sr_op__is_32bit
+  wire width 1 \mul_op__is_32bit$55
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 24 \sr_op__is_signed
+  wire width 1 \mul_op__is_signed$56
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 32 input 25 \sr_op__insn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
-  wire width 64 input 26 \ra
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
-  wire width 64 input 27 \rb
+  wire width 32 \mul_op__insn$57
+  process $group_25
+    assign \mul_op__insn_type$43 7'0000000
+    assign \mul_op__fn_unit$44 11'00000000000
+    assign \mul_op__imm_data__imm$45 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \mul_op__imm_data__imm_ok$46 1'0
+    assign \mul_op__rc__rc$47 1'0
+    assign \mul_op__rc__rc_ok$48 1'0
+    assign \mul_op__oe__oe$49 1'0
+    assign \mul_op__oe__oe_ok$50 1'0
+    assign \mul_op__invert_a$51 1'0
+    assign \mul_op__zero_a$52 1'0
+    assign \mul_op__invert_out$53 1'0
+    assign \mul_op__write_cr0$54 1'0
+    assign \mul_op__is_32bit$55 1'0
+    assign \mul_op__is_signed$56 1'0
+    assign \mul_op__insn$57 32'00000000000000000000000000000000
+    assign { \mul_op__insn$57 \mul_op__is_signed$56 \mul_op__is_32bit$55 \mul_op__write_cr0$54 \mul_op__invert_out$53 \mul_op__zero_a$52 \mul_op__invert_a$51 { \mul_op__oe__oe_ok$50 \mul_op__oe__oe$49 } { \mul_op__rc__rc_ok$48 \mul_op__rc__rc$47 } { \mul_op__imm_data__imm_ok$46 \mul_op__imm_data__imm$45 } \mul_op__fn_unit$44 \mul_op__insn_type$43 } { \mul2_mul_op__insn$35 \mul2_mul_op__is_signed$34 \mul2_mul_op__is_32bit$33 \mul2_mul_op__write_cr0$32 \mul2_mul_op__invert_out$31 \mul2_mul_op__zero_a$30 \mul2_mul_op__invert_a$29 { \mul2_mul_op__oe__oe_ok$28 \mul2_mul_op__oe__oe$27 } { \mul2_mul_op__rc__rc_ok$26 \mul2_mul_op__rc__rc$25 } { \mul2_mul_op__imm_data__imm_ok$24 \mul2_mul_op__imm_data__imm$23 } \mul2_mul_op__fn_unit$22 \mul2_mul_op__insn_type$21 }
+    sync init
+  end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
-  wire width 64 input 28 \rc
+  wire width 129 \o$58
+  process $group_40
+    assign \o$58 129'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
+    assign \o$58 \mul2_o
+    sync init
+  end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
-  wire width 2 input 29 \xer_ca$1
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153"
-  wire width 1 input 30 \p_valid_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154"
-  wire width 1 output 31 \p_ready_o
-  cell \p$87 \p
-    connect \p_valid_i \p_valid_i
-    connect \p_ready_o \p_ready_o
+  wire width 1 \xer_so$59
+  process $group_41
+    assign \xer_so$59 1'0
+    assign \xer_so$59 \mul2_xer_so$36
+    sync init
   end
-  cell \n$88 \n
-    connect \n_valid_o \n_valid_o
-    connect \n_ready_i \n_ready_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23"
+  wire width 1 \neg_res$60
+  process $group_42
+    assign \neg_res$60 1'0
+    assign \neg_res$60 \mul2_neg_res$37
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153"
-  wire width 1 \pipe_p_valid_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154"
-  wire width 1 \pipe_p_ready_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
-  wire width 2 \pipe_muxid
-  attribute \enum_base_type "MicrOp"
-  attribute \enum_value_0000000 "OP_ILLEGAL"
-  attribute \enum_value_0000001 "OP_NOP"
-  attribute \enum_value_0000010 "OP_ADD"
-  attribute \enum_value_0000011 "OP_ADDPCIS"
-  attribute \enum_value_0000100 "OP_AND"
-  attribute \enum_value_0000101 "OP_ATTN"
-  attribute \enum_value_0000110 "OP_B"
-  attribute \enum_value_0000111 "OP_BC"
-  attribute \enum_value_0001000 "OP_BCREG"
-  attribute \enum_value_0001001 "OP_BPERM"
-  attribute \enum_value_0001010 "OP_CMP"
-  attribute \enum_value_0001011 "OP_CMPB"
-  attribute \enum_value_0001100 "OP_CMPEQB"
-  attribute \enum_value_0001101 "OP_CMPRB"
-  attribute \enum_value_0001110 "OP_CNTZ"
-  attribute \enum_value_0001111 "OP_CRAND"
-  attribute \enum_value_0010000 "OP_CRANDC"
-  attribute \enum_value_0010001 "OP_CREQV"
-  attribute \enum_value_0010010 "OP_CRNAND"
-  attribute \enum_value_0010011 "OP_CRNOR"
-  attribute \enum_value_0010100 "OP_CROR"
-  attribute \enum_value_0010101 "OP_CRORC"
-  attribute \enum_value_0010110 "OP_CRXOR"
-  attribute \enum_value_0010111 "OP_DARN"
-  attribute \enum_value_0011000 "OP_DCBF"
-  attribute \enum_value_0011001 "OP_DCBST"
-  attribute \enum_value_0011010 "OP_DCBT"
-  attribute \enum_value_0011011 "OP_DCBTST"
-  attribute \enum_value_0011100 "OP_DCBZ"
-  attribute \enum_value_0011101 "OP_DIV"
-  attribute \enum_value_0011110 "OP_DIVE"
-  attribute \enum_value_0011111 "OP_EXTS"
-  attribute \enum_value_0100000 "OP_EXTSWSLI"
-  attribute \enum_value_0100001 "OP_ICBI"
-  attribute \enum_value_0100010 "OP_ICBT"
-  attribute \enum_value_0100011 "OP_ISEL"
-  attribute \enum_value_0100100 "OP_ISYNC"
-  attribute \enum_value_0100101 "OP_LOAD"
-  attribute \enum_value_0100110 "OP_STORE"
-  attribute \enum_value_0100111 "OP_MADDHD"
-  attribute \enum_value_0101000 "OP_MADDHDU"
-  attribute \enum_value_0101001 "OP_MADDLD"
-  attribute \enum_value_0101010 "OP_MCRF"
-  attribute \enum_value_0101011 "OP_MCRXR"
-  attribute \enum_value_0101100 "OP_MCRXRX"
-  attribute \enum_value_0101101 "OP_MFCR"
-  attribute \enum_value_0101110 "OP_MFSPR"
-  attribute \enum_value_0101111 "OP_MOD"
-  attribute \enum_value_0110000 "OP_MTCRF"
-  attribute \enum_value_0110001 "OP_MTSPR"
-  attribute \enum_value_0110010 "OP_MUL_L64"
-  attribute \enum_value_0110011 "OP_MUL_H64"
-  attribute \enum_value_0110100 "OP_MUL_H32"
-  attribute \enum_value_0110101 "OP_OR"
-  attribute \enum_value_0110110 "OP_POPCNT"
-  attribute \enum_value_0110111 "OP_PRTY"
-  attribute \enum_value_0111000 "OP_RLC"
-  attribute \enum_value_0111001 "OP_RLCL"
-  attribute \enum_value_0111010 "OP_RLCR"
-  attribute \enum_value_0111011 "OP_SETB"
-  attribute \enum_value_0111100 "OP_SHL"
-  attribute \enum_value_0111101 "OP_SHR"
-  attribute \enum_value_0111110 "OP_SYNC"
-  attribute \enum_value_0111111 "OP_TRAP"
-  attribute \enum_value_1000011 "OP_XOR"
-  attribute \enum_value_1000100 "OP_SIM_CONFIG"
-  attribute \enum_value_1000101 "OP_CROP"
-  attribute \enum_value_1000110 "OP_RFID"
-  attribute \enum_value_1000111 "OP_MFMSR"
-  attribute \enum_value_1001000 "OP_MTMSRD"
-  attribute \enum_value_1001001 "OP_SC"
-  attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 7 \pipe_sr_op__insn_type
-  attribute \enum_base_type "Function"
-  attribute \enum_value_00000000000 "NONE"
-  attribute \enum_value_00000000010 "ALU"
-  attribute \enum_value_00000000100 "LDST"
-  attribute \enum_value_00000001000 "SHIFT_ROT"
-  attribute \enum_value_00000010000 "LOGICAL"
-  attribute \enum_value_00000100000 "BRANCH"
-  attribute \enum_value_00001000000 "CR"
-  attribute \enum_value_00010000000 "TRAP"
-  attribute \enum_value_00100000000 "MUL"
-  attribute \enum_value_01000000000 "DIV"
-  attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 11 \pipe_sr_op__fn_unit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 64 \pipe_sr_op__imm_data__imm
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \pipe_sr_op__imm_data__imm_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \pipe_sr_op__rc__rc
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \pipe_sr_op__rc__rc_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \pipe_sr_op__oe__oe
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \pipe_sr_op__oe__oe_ok
-  attribute \enum_base_type "CryIn"
-  attribute \enum_value_00 "ZERO"
-  attribute \enum_value_01 "ONE"
-  attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 2 \pipe_sr_op__input_carry
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \pipe_sr_op__output_carry
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \pipe_sr_op__input_cr
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \pipe_sr_op__output_cr
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \pipe_sr_op__is_32bit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \pipe_sr_op__is_signed
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 32 \pipe_sr_op__insn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
-  wire width 64 \pipe_ra
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
-  wire width 64 \pipe_rb
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
-  wire width 64 \pipe_rc
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
-  wire width 2 \pipe_xer_ca
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24"
+  wire width 1 \neg_res32$61
+  process $group_43
+    assign \neg_res32$61 1'0
+    assign \neg_res32$61 \mul2_neg_res32$38
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615"
+  wire width 1 \r_busy
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615"
+  wire width 1 \r_busy$next
+  process $group_44
+    assign \r_busy$next \r_busy
+    attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+    switch { \n_i_rdy_data \p_valid_i_p_ready_o }
+      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+      case 2'-1
+        assign \r_busy$next 1'1
+      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
+      case 2'1-
+        assign \r_busy$next 1'0
+    end
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
+      case 1'1
+        assign \r_busy$next 1'0
+    end
+    sync init
+      update \r_busy 1'0
+    sync posedge \coresync_clk
+      update \r_busy \r_busy$next
+  end
+  process $group_45
+    assign \muxid$1$next \muxid$1
+    attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+    switch { \n_i_rdy_data \p_valid_i_p_ready_o }
+      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+      case 2'-1
+        assign \muxid$1$next \muxid$42
+      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
+      case 2'1-
+        assign \muxid$1$next \muxid$42
+    end
+    sync init
+      update \muxid$1 2'00
+    sync posedge \coresync_clk
+      update \muxid$1 \muxid$1$next
+  end
+  process $group_46
+    assign \mul_op__insn_type$2$next \mul_op__insn_type$2
+    assign \mul_op__fn_unit$3$next \mul_op__fn_unit$3
+    assign \mul_op__imm_data__imm$4$next \mul_op__imm_data__imm$4
+    assign \mul_op__imm_data__imm_ok$5$next \mul_op__imm_data__imm_ok$5
+    assign \mul_op__rc__rc$6$next \mul_op__rc__rc$6
+    assign \mul_op__rc__rc_ok$7$next \mul_op__rc__rc_ok$7
+    assign \mul_op__oe__oe$8$next \mul_op__oe__oe$8
+    assign \mul_op__oe__oe_ok$9$next \mul_op__oe__oe_ok$9
+    assign \mul_op__invert_a$10$next \mul_op__invert_a$10
+    assign \mul_op__zero_a$11$next \mul_op__zero_a$11
+    assign \mul_op__invert_out$12$next \mul_op__invert_out$12
+    assign \mul_op__write_cr0$13$next \mul_op__write_cr0$13
+    assign \mul_op__is_32bit$14$next \mul_op__is_32bit$14
+    assign \mul_op__is_signed$15$next \mul_op__is_signed$15
+    assign \mul_op__insn$16$next \mul_op__insn$16
+    attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+    switch { \n_i_rdy_data \p_valid_i_p_ready_o }
+      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+      case 2'-1
+        assign { \mul_op__insn$16$next \mul_op__is_signed$15$next \mul_op__is_32bit$14$next \mul_op__write_cr0$13$next \mul_op__invert_out$12$next \mul_op__zero_a$11$next \mul_op__invert_a$10$next { \mul_op__oe__oe_ok$9$next \mul_op__oe__oe$8$next } { \mul_op__rc__rc_ok$7$next \mul_op__rc__rc$6$next } { \mul_op__imm_data__imm_ok$5$next \mul_op__imm_data__imm$4$next } \mul_op__fn_unit$3$next \mul_op__insn_type$2$next } { \mul_op__insn$57 \mul_op__is_signed$56 \mul_op__is_32bit$55 \mul_op__write_cr0$54 \mul_op__invert_out$53 \mul_op__zero_a$52 \mul_op__invert_a$51 { \mul_op__oe__oe_ok$50 \mul_op__oe__oe$49 } { \mul_op__rc__rc_ok$48 \mul_op__rc__rc$47 } { \mul_op__imm_data__imm_ok$46 \mul_op__imm_data__imm$45 } \mul_op__fn_unit$44 \mul_op__insn_type$43 }
+      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
+      case 2'1-
+        assign { \mul_op__insn$16$next \mul_op__is_signed$15$next \mul_op__is_32bit$14$next \mul_op__write_cr0$13$next \mul_op__invert_out$12$next \mul_op__zero_a$11$next \mul_op__invert_a$10$next { \mul_op__oe__oe_ok$9$next \mul_op__oe__oe$8$next } { \mul_op__rc__rc_ok$7$next \mul_op__rc__rc$6$next } { \mul_op__imm_data__imm_ok$5$next \mul_op__imm_data__imm$4$next } \mul_op__fn_unit$3$next \mul_op__insn_type$2$next } { \mul_op__insn$57 \mul_op__is_signed$56 \mul_op__is_32bit$55 \mul_op__write_cr0$54 \mul_op__invert_out$53 \mul_op__zero_a$52 \mul_op__invert_a$51 { \mul_op__oe__oe_ok$50 \mul_op__oe__oe$49 } { \mul_op__rc__rc_ok$48 \mul_op__rc__rc$47 } { \mul_op__imm_data__imm_ok$46 \mul_op__imm_data__imm$45 } \mul_op__fn_unit$44 \mul_op__insn_type$43 }
+    end
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
+      case 1'1
+        assign \mul_op__imm_data__imm$4$next 64'0000000000000000000000000000000000000000000000000000000000000000
+        assign \mul_op__imm_data__imm_ok$5$next 1'0
+        assign \mul_op__rc__rc$6$next 1'0
+        assign \mul_op__rc__rc_ok$7$next 1'0
+        assign \mul_op__oe__oe$8$next 1'0
+        assign \mul_op__oe__oe_ok$9$next 1'0
+    end
+    sync init
+      update \mul_op__insn_type$2 7'0000000
+      update \mul_op__fn_unit$3 11'00000000000
+      update \mul_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000
+      update \mul_op__imm_data__imm_ok$5 1'0
+      update \mul_op__rc__rc$6 1'0
+      update \mul_op__rc__rc_ok$7 1'0
+      update \mul_op__oe__oe$8 1'0
+      update \mul_op__oe__oe_ok$9 1'0
+      update \mul_op__invert_a$10 1'0
+      update \mul_op__zero_a$11 1'0
+      update \mul_op__invert_out$12 1'0
+      update \mul_op__write_cr0$13 1'0
+      update \mul_op__is_32bit$14 1'0
+      update \mul_op__is_signed$15 1'0
+      update \mul_op__insn$16 32'00000000000000000000000000000000
+    sync posedge \coresync_clk
+      update \mul_op__insn_type$2 \mul_op__insn_type$2$next
+      update \mul_op__fn_unit$3 \mul_op__fn_unit$3$next
+      update \mul_op__imm_data__imm$4 \mul_op__imm_data__imm$4$next
+      update \mul_op__imm_data__imm_ok$5 \mul_op__imm_data__imm_ok$5$next
+      update \mul_op__rc__rc$6 \mul_op__rc__rc$6$next
+      update \mul_op__rc__rc_ok$7 \mul_op__rc__rc_ok$7$next
+      update \mul_op__oe__oe$8 \mul_op__oe__oe$8$next
+      update \mul_op__oe__oe_ok$9 \mul_op__oe__oe_ok$9$next
+      update \mul_op__invert_a$10 \mul_op__invert_a$10$next
+      update \mul_op__zero_a$11 \mul_op__zero_a$11$next
+      update \mul_op__invert_out$12 \mul_op__invert_out$12$next
+      update \mul_op__write_cr0$13 \mul_op__write_cr0$13$next
+      update \mul_op__is_32bit$14 \mul_op__is_32bit$14$next
+      update \mul_op__is_signed$15 \mul_op__is_signed$15$next
+      update \mul_op__insn$16 \mul_op__insn$16$next
+  end
+  process $group_61
+    assign \o$next \o
+    attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+    switch { \n_i_rdy_data \p_valid_i_p_ready_o }
+      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+      case 2'-1
+        assign \o$next \o$58
+      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
+      case 2'1-
+        assign \o$next \o$58
+    end
+    sync init
+      update \o 129'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
+    sync posedge \coresync_clk
+      update \o \o$next
+  end
+  process $group_62
+    assign \xer_so$17$next \xer_so$17
+    attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+    switch { \n_i_rdy_data \p_valid_i_p_ready_o }
+      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+      case 2'-1
+        assign \xer_so$17$next \xer_so$59
+      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
+      case 2'1-
+        assign \xer_so$17$next \xer_so$59
+    end
+    sync init
+      update \xer_so$17 1'0
+    sync posedge \coresync_clk
+      update \xer_so$17 \xer_so$17$next
+  end
+  process $group_63
+    assign \neg_res$18$next \neg_res$18
+    attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+    switch { \n_i_rdy_data \p_valid_i_p_ready_o }
+      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+      case 2'-1
+        assign \neg_res$18$next \neg_res$60
+      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
+      case 2'1-
+        assign \neg_res$18$next \neg_res$60
+    end
+    sync init
+      update \neg_res$18 1'0
+    sync posedge \coresync_clk
+      update \neg_res$18 \neg_res$18$next
+  end
+  process $group_64
+    assign \neg_res32$19$next \neg_res32$19
+    attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+    switch { \n_i_rdy_data \p_valid_i_p_ready_o }
+      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+      case 2'-1
+        assign \neg_res32$19$next \neg_res32$61
+      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
+      case 2'1-
+        assign \neg_res32$19$next \neg_res32$61
+    end
+    sync init
+      update \neg_res32$19 1'0
+    sync posedge \coresync_clk
+      update \neg_res32$19 \neg_res32$19$next
+  end
+  process $group_65
+    assign \n_valid_o 1'0
+    assign \n_valid_o \r_busy
+    sync init
+  end
+  process $group_66
+    assign \p_ready_o 1'0
+    assign \p_ready_o \n_i_rdy_data
+    sync init
+  end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe3.p"
+module \p$94
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153"
+  wire width 1 input 0 \p_valid_i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154"
+  wire width 1 input 1 \p_ready_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158"
+  wire width 1 \trigger
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205"
+  wire width 1 $1
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205"
+  cell $and $2
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \p_valid_i
+    connect \B \p_ready_o
+    connect \Y $1
+  end
+  process $group_0
+    assign \trigger 1'0
+    assign \trigger $1
+    sync init
+  end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe3.n"
+module \n$95
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
-  wire width 1 \pipe_n_valid_o
+  wire width 1 input 0 \n_valid_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
-  wire width 1 \pipe_n_ready_i
+  wire width 1 input 1 \n_ready_i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251"
+  wire width 1 \trigger
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298"
+  wire width 1 $1
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298"
+  cell $and $2
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \n_ready_i
+    connect \B \n_valid_o
+    connect \Y $1
+  end
+  process $group_0
+    assign \trigger 1'0
+    assign \trigger $1
+    sync init
+  end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe3.mul3"
+module \mul3
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
-  wire width 2 \pipe_muxid$2
+  wire width 2 input 0 \muxid
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
   attribute \enum_value_0000001 "OP_NOP"
@@ -104263,7 +104525,7 @@ module \alu_shift_rot0
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 7 \pipe_sr_op__insn_type$3
+  wire width 7 input 1 \mul_op__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -104277,173 +104539,41 @@ module \alu_shift_rot0
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 11 \pipe_sr_op__fn_unit$4
+  wire width 11 input 2 \mul_op__fn_unit
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 64 \pipe_sr_op__imm_data__imm$5
+  wire width 64 input 3 \mul_op__imm_data__imm
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \pipe_sr_op__imm_data__imm_ok$6
+  wire width 1 input 4 \mul_op__imm_data__imm_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \pipe_sr_op__rc__rc$7
+  wire width 1 input 5 \mul_op__rc__rc
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \pipe_sr_op__rc__rc_ok$8
+  wire width 1 input 6 \mul_op__rc__rc_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \pipe_sr_op__oe__oe$9
+  wire width 1 input 7 \mul_op__oe__oe
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \pipe_sr_op__oe__oe_ok$10
-  attribute \enum_base_type "CryIn"
-  attribute \enum_value_00 "ZERO"
-  attribute \enum_value_01 "ONE"
-  attribute \enum_value_10 "CA"
+  wire width 1 input 8 \mul_op__oe__oe_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 2 \pipe_sr_op__input_carry$11
+  wire width 1 input 9 \mul_op__invert_a
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \pipe_sr_op__output_carry$12
+  wire width 1 input 10 \mul_op__zero_a
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \pipe_sr_op__input_cr$13
+  wire width 1 input 11 \mul_op__invert_out
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \pipe_sr_op__output_cr$14
+  wire width 1 input 12 \mul_op__write_cr0
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \pipe_sr_op__is_32bit$15
+  wire width 1 input 13 \mul_op__is_32bit
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \pipe_sr_op__is_signed$16
+  wire width 1 input 14 \mul_op__is_signed
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 32 \pipe_sr_op__insn$17
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 64 \pipe_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 \pipe_o_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 4 \pipe_cr_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 \pipe_cr_a_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 2 \pipe_xer_ca$18
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 \pipe_xer_ca_ok
-  cell \pipe$89 \pipe
-    connect \rst \rst
-    connect \clk \clk
-    connect \p_valid_i \pipe_p_valid_i
-    connect \p_ready_o \pipe_p_ready_o
-    connect \muxid \pipe_muxid
-    connect \sr_op__insn_type \pipe_sr_op__insn_type
-    connect \sr_op__fn_unit \pipe_sr_op__fn_unit
-    connect \sr_op__imm_data__imm \pipe_sr_op__imm_data__imm
-    connect \sr_op__imm_data__imm_ok \pipe_sr_op__imm_data__imm_ok
-    connect \sr_op__rc__rc \pipe_sr_op__rc__rc
-    connect \sr_op__rc__rc_ok \pipe_sr_op__rc__rc_ok
-    connect \sr_op__oe__oe \pipe_sr_op__oe__oe
-    connect \sr_op__oe__oe_ok \pipe_sr_op__oe__oe_ok
-    connect \sr_op__input_carry \pipe_sr_op__input_carry
-    connect \sr_op__output_carry \pipe_sr_op__output_carry
-    connect \sr_op__input_cr \pipe_sr_op__input_cr
-    connect \sr_op__output_cr \pipe_sr_op__output_cr
-    connect \sr_op__is_32bit \pipe_sr_op__is_32bit
-    connect \sr_op__is_signed \pipe_sr_op__is_signed
-    connect \sr_op__insn \pipe_sr_op__insn
-    connect \ra \pipe_ra
-    connect \rb \pipe_rb
-    connect \rc \pipe_rc
-    connect \xer_ca \pipe_xer_ca
-    connect \n_valid_o \pipe_n_valid_o
-    connect \n_ready_i \pipe_n_ready_i
-    connect \muxid$1 \pipe_muxid$2
-    connect \sr_op__insn_type$2 \pipe_sr_op__insn_type$3
-    connect \sr_op__fn_unit$3 \pipe_sr_op__fn_unit$4
-    connect \sr_op__imm_data__imm$4 \pipe_sr_op__imm_data__imm$5
-    connect \sr_op__imm_data__imm_ok$5 \pipe_sr_op__imm_data__imm_ok$6
-    connect \sr_op__rc__rc$6 \pipe_sr_op__rc__rc$7
-    connect \sr_op__rc__rc_ok$7 \pipe_sr_op__rc__rc_ok$8
-    connect \sr_op__oe__oe$8 \pipe_sr_op__oe__oe$9
-    connect \sr_op__oe__oe_ok$9 \pipe_sr_op__oe__oe_ok$10
-    connect \sr_op__input_carry$10 \pipe_sr_op__input_carry$11
-    connect \sr_op__output_carry$11 \pipe_sr_op__output_carry$12
-    connect \sr_op__input_cr$12 \pipe_sr_op__input_cr$13
-    connect \sr_op__output_cr$13 \pipe_sr_op__output_cr$14
-    connect \sr_op__is_32bit$14 \pipe_sr_op__is_32bit$15
-    connect \sr_op__is_signed$15 \pipe_sr_op__is_signed$16
-    connect \sr_op__insn$16 \pipe_sr_op__insn$17
-    connect \o \pipe_o
-    connect \o_ok \pipe_o_ok
-    connect \cr_a \pipe_cr_a
-    connect \cr_a_ok \pipe_cr_a_ok
-    connect \xer_ca$17 \pipe_xer_ca$18
-    connect \xer_ca_ok \pipe_xer_ca_ok
-  end
-  process $group_0
-    assign \pipe_p_valid_i 1'0
-    assign \pipe_p_valid_i \p_valid_i
-    sync init
-  end
-  process $group_1
-    assign \p_ready_o 1'0
-    assign \p_ready_o \pipe_p_ready_o
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
-  wire width 2 \muxid
-  process $group_2
-    assign \pipe_muxid 2'00
-    assign \pipe_muxid \muxid
-    sync init
-  end
-  process $group_3
-    assign \pipe_sr_op__insn_type 7'0000000
-    assign \pipe_sr_op__fn_unit 11'00000000000
-    assign \pipe_sr_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \pipe_sr_op__imm_data__imm_ok 1'0
-    assign \pipe_sr_op__rc__rc 1'0
-    assign \pipe_sr_op__rc__rc_ok 1'0
-    assign \pipe_sr_op__oe__oe 1'0
-    assign \pipe_sr_op__oe__oe_ok 1'0
-    assign { } 0'0
-    assign \pipe_sr_op__input_carry 2'00
-    assign \pipe_sr_op__output_carry 1'0
-    assign \pipe_sr_op__input_cr 1'0
-    assign \pipe_sr_op__output_cr 1'0
-    assign \pipe_sr_op__is_32bit 1'0
-    assign \pipe_sr_op__is_signed 1'0
-    assign \pipe_sr_op__insn 32'00000000000000000000000000000000
-    assign { \pipe_sr_op__insn \pipe_sr_op__is_signed \pipe_sr_op__is_32bit \pipe_sr_op__output_cr \pipe_sr_op__input_cr \pipe_sr_op__output_carry \pipe_sr_op__input_carry { } { \pipe_sr_op__oe__oe_ok \pipe_sr_op__oe__oe } { \pipe_sr_op__rc__rc_ok \pipe_sr_op__rc__rc } { \pipe_sr_op__imm_data__imm_ok \pipe_sr_op__imm_data__imm } \pipe_sr_op__fn_unit \pipe_sr_op__insn_type } { \sr_op__insn \sr_op__is_signed \sr_op__is_32bit \sr_op__output_cr \sr_op__input_cr \sr_op__output_carry \sr_op__input_carry { } { \sr_op__oe__oe_ok \sr_op__oe__oe } { \sr_op__rc__rc_ok \sr_op__rc__rc } { \sr_op__imm_data__imm_ok \sr_op__imm_data__imm } \sr_op__fn_unit \sr_op__insn_type }
-    sync init
-  end
-  process $group_19
-    assign \pipe_ra 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \pipe_ra \ra
-    sync init
-  end
-  process $group_20
-    assign \pipe_rb 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \pipe_rb \rb
-    sync init
-  end
-  process $group_21
-    assign \pipe_rc 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \pipe_rc \rc
-    sync init
-  end
-  process $group_22
-    assign \pipe_xer_ca 2'00
-    assign \pipe_xer_ca \xer_ca$1
-    sync init
-  end
-  process $group_23
-    assign \n_valid_o 1'0
-    assign \n_valid_o \pipe_n_valid_o
-    sync init
-  end
-  process $group_24
-    assign \pipe_n_ready_i 1'0
-    assign \pipe_n_ready_i \n_ready_i
-    sync init
-  end
+  wire width 32 input 15 \mul_op__insn
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
+  wire width 129 input 16 \o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
+  wire width 1 input 17 \xer_so
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23"
+  wire width 1 input 18 \neg_res
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
-  wire width 2 \muxid$19
-  process $group_25
-    assign \muxid$19 2'00
-    assign \muxid$19 \pipe_muxid$2
-    sync init
-  end
+  wire width 2 output 19 \muxid$1
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
   attribute \enum_value_0000001 "OP_NOP"
@@ -104518,7 +104648,7 @@ module \alu_shift_rot0
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 7 \sr_op__insn_type$20
+  wire width 7 output 20 \mul_op__insn_type$2
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -104532,1099 +104662,917 @@ module \alu_shift_rot0
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 11 \sr_op__fn_unit$21
+  wire width 11 output 21 \mul_op__fn_unit$3
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 64 \sr_op__imm_data__imm$22
+  wire width 64 output 22 \mul_op__imm_data__imm$4
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \sr_op__imm_data__imm_ok$23
+  wire width 1 output 23 \mul_op__imm_data__imm_ok$5
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \sr_op__rc__rc$24
+  wire width 1 output 24 \mul_op__rc__rc$6
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \sr_op__rc__rc_ok$25
+  wire width 1 output 25 \mul_op__rc__rc_ok$7
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \sr_op__oe__oe$26
+  wire width 1 output 26 \mul_op__oe__oe$8
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \sr_op__oe__oe_ok$27
-  attribute \enum_base_type "CryIn"
-  attribute \enum_value_00 "ZERO"
-  attribute \enum_value_01 "ONE"
-  attribute \enum_value_10 "CA"
+  wire width 1 output 27 \mul_op__oe__oe_ok$9
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 2 \sr_op__input_carry$28
+  wire width 1 output 28 \mul_op__invert_a$10
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \sr_op__output_carry$29
+  wire width 1 output 29 \mul_op__zero_a$11
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \sr_op__input_cr$30
+  wire width 1 output 30 \mul_op__invert_out$12
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \sr_op__output_cr$31
+  wire width 1 output 31 \mul_op__write_cr0$13
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \sr_op__is_32bit$32
+  wire width 1 output 32 \mul_op__is_32bit$14
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \sr_op__is_signed$33
+  wire width 1 output 33 \mul_op__is_signed$15
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 32 \sr_op__insn$34
-  process $group_26
-    assign \sr_op__insn_type$20 7'0000000
-    assign \sr_op__fn_unit$21 11'00000000000
-    assign \sr_op__imm_data__imm$22 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \sr_op__imm_data__imm_ok$23 1'0
-    assign \sr_op__rc__rc$24 1'0
-    assign \sr_op__rc__rc_ok$25 1'0
-    assign \sr_op__oe__oe$26 1'0
-    assign \sr_op__oe__oe_ok$27 1'0
-    assign { } 0'0
-    assign \sr_op__input_carry$28 2'00
-    assign \sr_op__output_carry$29 1'0
-    assign \sr_op__input_cr$30 1'0
-    assign \sr_op__output_cr$31 1'0
-    assign \sr_op__is_32bit$32 1'0
-    assign \sr_op__is_signed$33 1'0
-    assign \sr_op__insn$34 32'00000000000000000000000000000000
-    assign { \sr_op__insn$34 \sr_op__is_signed$33 \sr_op__is_32bit$32 \sr_op__output_cr$31 \sr_op__input_cr$30 \sr_op__output_carry$29 \sr_op__input_carry$28 { } { \sr_op__oe__oe_ok$27 \sr_op__oe__oe$26 } { \sr_op__rc__rc_ok$25 \sr_op__rc__rc$24 } { \sr_op__imm_data__imm_ok$23 \sr_op__imm_data__imm$22 } \sr_op__fn_unit$21 \sr_op__insn_type$20 } { \pipe_sr_op__insn$17 \pipe_sr_op__is_signed$16 \pipe_sr_op__is_32bit$15 \pipe_sr_op__output_cr$14 \pipe_sr_op__input_cr$13 \pipe_sr_op__output_carry$12 \pipe_sr_op__input_carry$11 { } { \pipe_sr_op__oe__oe_ok$10 \pipe_sr_op__oe__oe$9 } { \pipe_sr_op__rc__rc_ok$8 \pipe_sr_op__rc__rc$7 } { \pipe_sr_op__imm_data__imm_ok$6 \pipe_sr_op__imm_data__imm$5 } \pipe_sr_op__fn_unit$4 \pipe_sr_op__insn_type$3 }
-    sync init
-  end
-  process $group_42
-    assign \o 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \o_ok 1'0
-    assign { \o_ok \o } { \pipe_o_ok \pipe_o }
-    sync init
-  end
-  process $group_44
-    assign \cr_a 4'0000
-    assign \cr_a_ok 1'0
-    assign { \cr_a_ok \cr_a } { \pipe_cr_a_ok \pipe_cr_a }
-    sync init
-  end
-  process $group_46
-    assign \xer_ca 2'00
-    assign \xer_ca_ok 1'0
-    assign { \xer_ca_ok \xer_ca } { \pipe_xer_ca_ok \pipe_xer_ca$18 }
-    sync init
-  end
-  connect \muxid 2'00
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.src_l"
-module \src_l$95
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
-  wire width 4 input 2 \s_src
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
-  wire width 4 input 3 \r_src
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
-  wire width 4 output 4 \q_src
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
-  wire width 4 \q_int
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
-  wire width 4 \q_int$next
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
-  wire width 4 $1
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
-  cell $not $2
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 4
-    parameter \Y_WIDTH 4
-    connect \A \r_src
-    connect \Y $1
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
-  wire width 4 $3
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
-  cell $and $4
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 4
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 4
-    parameter \Y_WIDTH 4
-    connect \A \q_int
-    connect \B $1
-    connect \Y $3
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
-  wire width 4 $5
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
-  cell $or $6
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 4
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 4
-    parameter \Y_WIDTH 4
-    connect \A $3
-    connect \B \s_src
-    connect \Y $5
-  end
+  wire width 32 output 34 \mul_op__insn$16
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 64 output 35 \o$17
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 output 36 \o_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 2 output 37 \xer_ov
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 output 38 \xer_ov_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 output 39 \xer_so$18
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:36"
+  wire width 1 \is_32bit
   process $group_0
-    assign \q_int$next \q_int
-    assign \q_int$next $5
-    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
-      case 1'1
-        assign \q_int$next 4'0000
-    end
+    assign \is_32bit 1'0
+    assign \is_32bit \mul_op__is_32bit
     sync init
-      update \q_int 4'0000
-    sync posedge \clk
-      update \q_int \q_int$next
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
-  wire width 4 $7
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
-  cell $not $8
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:40"
+  wire width 129 \mul_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41"
+  wire width 130 $19
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41"
+  wire width 130 $20
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41"
+  cell $neg $21
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 4
-    parameter \Y_WIDTH 4
-    connect \A \r_src
-    connect \Y $7
+    parameter \A_WIDTH 129
+    parameter \Y_WIDTH 130
+    connect \A \o
+    connect \Y $20
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
-  wire width 4 $9
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
-  cell $and $10
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
+  wire width 130 $22
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
+  cell $pos $23
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 4
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 4
-    parameter \Y_WIDTH 4
-    connect \A \q_int
-    connect \B $7
-    connect \Y $9
+    parameter \A_WIDTH 129
+    parameter \Y_WIDTH 130
+    connect \A \o
+    connect \Y $22
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
-  wire width 4 $11
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
-  cell $or $12
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 4
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 4
-    parameter \Y_WIDTH 4
-    connect \A $9
-    connect \B \s_src
-    connect \Y $11
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41"
+  wire width 130 $24
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41"
+  cell $mux $25
+    parameter \WIDTH 130
+    connect \A $22
+    connect \B $20
+    connect \S \neg_res
+    connect \Y $24
   end
+  connect $19 $24
   process $group_1
-    assign \q_src 4'0000
-    assign \q_src $11
+    assign \mul_o 129'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
+    assign \mul_o $19 [128:0]
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
-  wire width 4 \qn_src
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
-  wire width 4 $13
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
-  cell $not $14
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 4
-    parameter \Y_WIDTH 4
-    connect \A \q_src
-    connect \Y $13
-  end
+  wire width 1 $verilog_initial_trigger
   process $group_2
-    assign \qn_src 4'0000
-    assign \qn_src $13
+    assign \o_ok 1'0
+    assign \o_ok 1'1
+    assign $verilog_initial_trigger $verilog_initial_trigger
     sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62"
-  wire width 4 \qlq_src
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
-  wire width 4 $15
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
-  cell $or $16
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 4
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 4
-    parameter \Y_WIDTH 4
-    connect \A \q_src
-    connect \B \q_int
-    connect \Y $15
+      update $verilog_initial_trigger 1'0
   end
   process $group_3
-    assign \qlq_src 4'0000
-    assign \qlq_src $15
+    assign \o$17 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:45"
+    switch \mul_op__insn_type
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:47"
+      attribute \nmigen.decoding "OP_MUL_H32/52"
+      case 7'0110100
+        assign \o$17 { \mul_o [63:32] \mul_o [63:32] }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:50"
+      attribute \nmigen.decoding "OP_MUL_H64/51"
+      case 7'0110011
+        assign \o$17 \mul_o [127:64]
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:53"
+      attribute \nmigen.decoding ""
+      case
+        assign \o$17 \mul_o [63:0]
+    end
     sync init
   end
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.opc_l"
-module \opc_l$96
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
-  wire width 1 input 2 \s_opc
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
-  wire width 1 input 3 \r_opc
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
-  wire width 1 output 4 \q_opc
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
-  wire width 1 \q_int
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
-  wire width 1 \q_int$next
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
-  wire width 1 $1
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
-  cell $not $2
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \r_opc
-    connect \Y $1
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
-  wire width 1 $3
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
-  cell $and $4
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:58"
+  wire width 1 \mul_ov
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:63"
+  wire width 1 $26
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:63"
+  cell $reduce_bool $27
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
+    parameter \A_WIDTH 33
     parameter \Y_WIDTH 1
-    connect \A \q_int
-    connect \B $1
-    connect \Y $3
+    connect \A \mul_o [63:31]
+    connect \Y $26
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
-  wire width 1 $5
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
-  cell $or $6
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:63"
+  wire width 1 $28
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:63"
+  wire width 1 $29
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:63"
+  cell $reduce_and $30
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
+    parameter \A_WIDTH 33
     parameter \Y_WIDTH 1
-    connect \A $3
-    connect \B \s_opc
-    connect \Y $5
-  end
-  process $group_0
-    assign \q_int$next \q_int
-    assign \q_int$next $5
-    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
-      case 1'1
-        assign \q_int$next 1'0
-    end
-    sync init
-      update \q_int 1'0
-    sync posedge \clk
-      update \q_int \q_int$next
+    connect \A \mul_o [63:31]
+    connect \Y $29
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
-  wire width 1 $7
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
-  cell $not $8
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:63"
+  cell $not $31
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \r_opc
-    connect \Y $7
+    connect \A $29
+    connect \Y $28
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
-  wire width 1 $9
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
-  cell $and $10
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:63"
+  wire width 1 $32
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:63"
+  cell $and $33
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \q_int
-    connect \B $7
-    connect \Y $9
+    connect \A $26
+    connect \B $28
+    connect \Y $32
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
-  wire width 1 $11
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
-  cell $or $12
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:68"
+  wire width 1 $34
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:68"
+  cell $reduce_bool $35
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
+    parameter \A_WIDTH 65
     parameter \Y_WIDTH 1
-    connect \A $9
-    connect \B \s_opc
-    connect \Y $11
+    connect \A \mul_o [127:63]
+    connect \Y $34
   end
-  process $group_1
-    assign \q_opc 1'0
-    assign \q_opc $11
-    sync init
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:68"
+  wire width 1 $36
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:68"
+  wire width 1 $37
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:68"
+  cell $reduce_and $38
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 65
+    parameter \Y_WIDTH 1
+    connect \A \mul_o [127:63]
+    connect \Y $37
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
-  wire width 1 \qn_opc
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
-  wire width 1 $13
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
-  cell $not $14
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:68"
+  cell $not $39
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \q_opc
-    connect \Y $13
-  end
-  process $group_2
-    assign \qn_opc 1'0
-    assign \qn_opc $13
-    sync init
+    connect \A $37
+    connect \Y $36
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62"
-  wire width 1 \qlq_opc
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
-  wire width 1 $15
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
-  cell $or $16
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:68"
+  wire width 1 $40
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:68"
+  cell $and $41
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \q_opc
-    connect \B \q_int
-    connect \Y $15
+    connect \A $34
+    connect \B $36
+    connect \Y $40
   end
-  process $group_3
-    assign \qlq_opc 1'0
-    assign \qlq_opc $15
+  process $group_4
+    assign \mul_ov 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:45"
+    switch \mul_op__insn_type
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:47"
+      attribute \nmigen.decoding "OP_MUL_H32/52"
+      case 7'0110100
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:50"
+      attribute \nmigen.decoding "OP_MUL_H64/51"
+      case 7'0110011
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:53"
+      attribute \nmigen.decoding ""
+      case
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:59"
+        switch { \is_32bit }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:59"
+          case 1'1
+            assign \mul_ov $32
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:64"
+          case
+            assign \mul_ov $40
+        end
+    end
     sync init
   end
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.req_l"
-module \req_l$97
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
-  wire width 3 output 2 \q_req
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
-  wire width 3 input 3 \s_req
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
-  wire width 3 input 4 \r_req
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
-  wire width 3 \q_int
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
-  wire width 3 \q_int$next
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
-  wire width 3 $1
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
-  cell $not $2
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 3
-    parameter \Y_WIDTH 3
-    connect \A \r_req
-    connect \Y $1
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
-  wire width 3 $3
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
-  cell $and $4
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 3
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 3
-    parameter \Y_WIDTH 3
-    connect \A \q_int
-    connect \B $1
-    connect \Y $3
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
-  wire width 3 $5
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
-  cell $or $6
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 3
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 3
-    parameter \Y_WIDTH 3
-    connect \A $3
-    connect \B \s_req
-    connect \Y $5
+  process $group_5
+    assign \xer_ov 2'00
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:45"
+    switch \mul_op__insn_type
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:47"
+      attribute \nmigen.decoding "OP_MUL_H32/52"
+      case 7'0110100
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:50"
+      attribute \nmigen.decoding "OP_MUL_H64/51"
+      case 7'0110011
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:53"
+      attribute \nmigen.decoding ""
+      case
+        assign \xer_ov { \mul_ov \mul_ov }
+    end
+    sync init
   end
-  process $group_0
-    assign \q_int$next \q_int
-    assign \q_int$next $5
-    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
-      case 1'1
-        assign \q_int$next 3'000
+  process $group_6
+    assign \xer_ov_ok 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:45"
+    switch \mul_op__insn_type
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:47"
+      attribute \nmigen.decoding "OP_MUL_H32/52"
+      case 7'0110100
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:50"
+      attribute \nmigen.decoding "OP_MUL_H64/51"
+      case 7'0110011
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:53"
+      attribute \nmigen.decoding ""
+      case
+        assign \xer_ov_ok 1'1
     end
     sync init
-      update \q_int 3'000
-    sync posedge \clk
-      update \q_int \q_int$next
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
-  wire width 3 $7
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
-  cell $not $8
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 3
-    parameter \Y_WIDTH 3
-    connect \A \r_req
-    connect \Y $7
+  process $group_7
+    assign \xer_so$18 1'0
+    assign \xer_so$18 \xer_so
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
-  wire width 3 $9
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
-  cell $and $10
+  process $group_8
+    assign \muxid$1 2'00
+    assign \muxid$1 \muxid
+    sync init
+  end
+  process $group_9
+    assign \mul_op__insn_type$2 7'0000000
+    assign \mul_op__fn_unit$3 11'00000000000
+    assign \mul_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \mul_op__imm_data__imm_ok$5 1'0
+    assign \mul_op__rc__rc$6 1'0
+    assign \mul_op__rc__rc_ok$7 1'0
+    assign \mul_op__oe__oe$8 1'0
+    assign \mul_op__oe__oe_ok$9 1'0
+    assign \mul_op__invert_a$10 1'0
+    assign \mul_op__zero_a$11 1'0
+    assign \mul_op__invert_out$12 1'0
+    assign \mul_op__write_cr0$13 1'0
+    assign \mul_op__is_32bit$14 1'0
+    assign \mul_op__is_signed$15 1'0
+    assign \mul_op__insn$16 32'00000000000000000000000000000000
+    assign { \mul_op__insn$16 \mul_op__is_signed$15 \mul_op__is_32bit$14 \mul_op__write_cr0$13 \mul_op__invert_out$12 \mul_op__zero_a$11 \mul_op__invert_a$10 { \mul_op__oe__oe_ok$9 \mul_op__oe__oe$8 } { \mul_op__rc__rc_ok$7 \mul_op__rc__rc$6 } { \mul_op__imm_data__imm_ok$5 \mul_op__imm_data__imm$4 } \mul_op__fn_unit$3 \mul_op__insn_type$2 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__invert_out \mul_op__zero_a \mul_op__invert_a { \mul_op__oe__oe_ok \mul_op__oe__oe } { \mul_op__rc__rc_ok \mul_op__rc__rc } { \mul_op__imm_data__imm_ok \mul_op__imm_data__imm } \mul_op__fn_unit \mul_op__insn_type }
+    sync init
+  end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe3.output"
+module \output$96
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
+  wire width 2 input 0 \muxid
+  attribute \enum_base_type "MicrOp"
+  attribute \enum_value_0000000 "OP_ILLEGAL"
+  attribute \enum_value_0000001 "OP_NOP"
+  attribute \enum_value_0000010 "OP_ADD"
+  attribute \enum_value_0000011 "OP_ADDPCIS"
+  attribute \enum_value_0000100 "OP_AND"
+  attribute \enum_value_0000101 "OP_ATTN"
+  attribute \enum_value_0000110 "OP_B"
+  attribute \enum_value_0000111 "OP_BC"
+  attribute \enum_value_0001000 "OP_BCREG"
+  attribute \enum_value_0001001 "OP_BPERM"
+  attribute \enum_value_0001010 "OP_CMP"
+  attribute \enum_value_0001011 "OP_CMPB"
+  attribute \enum_value_0001100 "OP_CMPEQB"
+  attribute \enum_value_0001101 "OP_CMPRB"
+  attribute \enum_value_0001110 "OP_CNTZ"
+  attribute \enum_value_0001111 "OP_CRAND"
+  attribute \enum_value_0010000 "OP_CRANDC"
+  attribute \enum_value_0010001 "OP_CREQV"
+  attribute \enum_value_0010010 "OP_CRNAND"
+  attribute \enum_value_0010011 "OP_CRNOR"
+  attribute \enum_value_0010100 "OP_CROR"
+  attribute \enum_value_0010101 "OP_CRORC"
+  attribute \enum_value_0010110 "OP_CRXOR"
+  attribute \enum_value_0010111 "OP_DARN"
+  attribute \enum_value_0011000 "OP_DCBF"
+  attribute \enum_value_0011001 "OP_DCBST"
+  attribute \enum_value_0011010 "OP_DCBT"
+  attribute \enum_value_0011011 "OP_DCBTST"
+  attribute \enum_value_0011100 "OP_DCBZ"
+  attribute \enum_value_0011101 "OP_DIV"
+  attribute \enum_value_0011110 "OP_DIVE"
+  attribute \enum_value_0011111 "OP_EXTS"
+  attribute \enum_value_0100000 "OP_EXTSWSLI"
+  attribute \enum_value_0100001 "OP_ICBI"
+  attribute \enum_value_0100010 "OP_ICBT"
+  attribute \enum_value_0100011 "OP_ISEL"
+  attribute \enum_value_0100100 "OP_ISYNC"
+  attribute \enum_value_0100101 "OP_LOAD"
+  attribute \enum_value_0100110 "OP_STORE"
+  attribute \enum_value_0100111 "OP_MADDHD"
+  attribute \enum_value_0101000 "OP_MADDHDU"
+  attribute \enum_value_0101001 "OP_MADDLD"
+  attribute \enum_value_0101010 "OP_MCRF"
+  attribute \enum_value_0101011 "OP_MCRXR"
+  attribute \enum_value_0101100 "OP_MCRXRX"
+  attribute \enum_value_0101101 "OP_MFCR"
+  attribute \enum_value_0101110 "OP_MFSPR"
+  attribute \enum_value_0101111 "OP_MOD"
+  attribute \enum_value_0110000 "OP_MTCRF"
+  attribute \enum_value_0110001 "OP_MTSPR"
+  attribute \enum_value_0110010 "OP_MUL_L64"
+  attribute \enum_value_0110011 "OP_MUL_H64"
+  attribute \enum_value_0110100 "OP_MUL_H32"
+  attribute \enum_value_0110101 "OP_OR"
+  attribute \enum_value_0110110 "OP_POPCNT"
+  attribute \enum_value_0110111 "OP_PRTY"
+  attribute \enum_value_0111000 "OP_RLC"
+  attribute \enum_value_0111001 "OP_RLCL"
+  attribute \enum_value_0111010 "OP_RLCR"
+  attribute \enum_value_0111011 "OP_SETB"
+  attribute \enum_value_0111100 "OP_SHL"
+  attribute \enum_value_0111101 "OP_SHR"
+  attribute \enum_value_0111110 "OP_SYNC"
+  attribute \enum_value_0111111 "OP_TRAP"
+  attribute \enum_value_1000011 "OP_XOR"
+  attribute \enum_value_1000100 "OP_SIM_CONFIG"
+  attribute \enum_value_1000101 "OP_CROP"
+  attribute \enum_value_1000110 "OP_RFID"
+  attribute \enum_value_1000111 "OP_MFMSR"
+  attribute \enum_value_1001000 "OP_MTMSRD"
+  attribute \enum_value_1001001 "OP_SC"
+  attribute \enum_value_1001010 "OP_MTMSR"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 input 1 \mul_op__insn_type
+  attribute \enum_base_type "Function"
+  attribute \enum_value_00000000000 "NONE"
+  attribute \enum_value_00000000010 "ALU"
+  attribute \enum_value_00000000100 "LDST"
+  attribute \enum_value_00000001000 "SHIFT_ROT"
+  attribute \enum_value_00000010000 "LOGICAL"
+  attribute \enum_value_00000100000 "BRANCH"
+  attribute \enum_value_00001000000 "CR"
+  attribute \enum_value_00010000000 "TRAP"
+  attribute \enum_value_00100000000 "MUL"
+  attribute \enum_value_01000000000 "DIV"
+  attribute \enum_value_10000000000 "SPR"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 input 2 \mul_op__fn_unit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 input 3 \mul_op__imm_data__imm
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 4 \mul_op__imm_data__imm_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 5 \mul_op__rc__rc
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 6 \mul_op__rc__rc_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 7 \mul_op__oe__oe
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 8 \mul_op__oe__oe_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 9 \mul_op__invert_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 10 \mul_op__zero_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 11 \mul_op__invert_out
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 12 \mul_op__write_cr0
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 13 \mul_op__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 14 \mul_op__is_signed
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 input 15 \mul_op__insn
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 64 input 16 \o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 input 17 \o_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 4 input 18 \cr_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 2 input 19 \xer_ov
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 input 20 \xer_so
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
+  wire width 2 output 21 \muxid$1
+  attribute \enum_base_type "MicrOp"
+  attribute \enum_value_0000000 "OP_ILLEGAL"
+  attribute \enum_value_0000001 "OP_NOP"
+  attribute \enum_value_0000010 "OP_ADD"
+  attribute \enum_value_0000011 "OP_ADDPCIS"
+  attribute \enum_value_0000100 "OP_AND"
+  attribute \enum_value_0000101 "OP_ATTN"
+  attribute \enum_value_0000110 "OP_B"
+  attribute \enum_value_0000111 "OP_BC"
+  attribute \enum_value_0001000 "OP_BCREG"
+  attribute \enum_value_0001001 "OP_BPERM"
+  attribute \enum_value_0001010 "OP_CMP"
+  attribute \enum_value_0001011 "OP_CMPB"
+  attribute \enum_value_0001100 "OP_CMPEQB"
+  attribute \enum_value_0001101 "OP_CMPRB"
+  attribute \enum_value_0001110 "OP_CNTZ"
+  attribute \enum_value_0001111 "OP_CRAND"
+  attribute \enum_value_0010000 "OP_CRANDC"
+  attribute \enum_value_0010001 "OP_CREQV"
+  attribute \enum_value_0010010 "OP_CRNAND"
+  attribute \enum_value_0010011 "OP_CRNOR"
+  attribute \enum_value_0010100 "OP_CROR"
+  attribute \enum_value_0010101 "OP_CRORC"
+  attribute \enum_value_0010110 "OP_CRXOR"
+  attribute \enum_value_0010111 "OP_DARN"
+  attribute \enum_value_0011000 "OP_DCBF"
+  attribute \enum_value_0011001 "OP_DCBST"
+  attribute \enum_value_0011010 "OP_DCBT"
+  attribute \enum_value_0011011 "OP_DCBTST"
+  attribute \enum_value_0011100 "OP_DCBZ"
+  attribute \enum_value_0011101 "OP_DIV"
+  attribute \enum_value_0011110 "OP_DIVE"
+  attribute \enum_value_0011111 "OP_EXTS"
+  attribute \enum_value_0100000 "OP_EXTSWSLI"
+  attribute \enum_value_0100001 "OP_ICBI"
+  attribute \enum_value_0100010 "OP_ICBT"
+  attribute \enum_value_0100011 "OP_ISEL"
+  attribute \enum_value_0100100 "OP_ISYNC"
+  attribute \enum_value_0100101 "OP_LOAD"
+  attribute \enum_value_0100110 "OP_STORE"
+  attribute \enum_value_0100111 "OP_MADDHD"
+  attribute \enum_value_0101000 "OP_MADDHDU"
+  attribute \enum_value_0101001 "OP_MADDLD"
+  attribute \enum_value_0101010 "OP_MCRF"
+  attribute \enum_value_0101011 "OP_MCRXR"
+  attribute \enum_value_0101100 "OP_MCRXRX"
+  attribute \enum_value_0101101 "OP_MFCR"
+  attribute \enum_value_0101110 "OP_MFSPR"
+  attribute \enum_value_0101111 "OP_MOD"
+  attribute \enum_value_0110000 "OP_MTCRF"
+  attribute \enum_value_0110001 "OP_MTSPR"
+  attribute \enum_value_0110010 "OP_MUL_L64"
+  attribute \enum_value_0110011 "OP_MUL_H64"
+  attribute \enum_value_0110100 "OP_MUL_H32"
+  attribute \enum_value_0110101 "OP_OR"
+  attribute \enum_value_0110110 "OP_POPCNT"
+  attribute \enum_value_0110111 "OP_PRTY"
+  attribute \enum_value_0111000 "OP_RLC"
+  attribute \enum_value_0111001 "OP_RLCL"
+  attribute \enum_value_0111010 "OP_RLCR"
+  attribute \enum_value_0111011 "OP_SETB"
+  attribute \enum_value_0111100 "OP_SHL"
+  attribute \enum_value_0111101 "OP_SHR"
+  attribute \enum_value_0111110 "OP_SYNC"
+  attribute \enum_value_0111111 "OP_TRAP"
+  attribute \enum_value_1000011 "OP_XOR"
+  attribute \enum_value_1000100 "OP_SIM_CONFIG"
+  attribute \enum_value_1000101 "OP_CROP"
+  attribute \enum_value_1000110 "OP_RFID"
+  attribute \enum_value_1000111 "OP_MFMSR"
+  attribute \enum_value_1001000 "OP_MTMSRD"
+  attribute \enum_value_1001001 "OP_SC"
+  attribute \enum_value_1001010 "OP_MTMSR"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 output 22 \mul_op__insn_type$2
+  attribute \enum_base_type "Function"
+  attribute \enum_value_00000000000 "NONE"
+  attribute \enum_value_00000000010 "ALU"
+  attribute \enum_value_00000000100 "LDST"
+  attribute \enum_value_00000001000 "SHIFT_ROT"
+  attribute \enum_value_00000010000 "LOGICAL"
+  attribute \enum_value_00000100000 "BRANCH"
+  attribute \enum_value_00001000000 "CR"
+  attribute \enum_value_00010000000 "TRAP"
+  attribute \enum_value_00100000000 "MUL"
+  attribute \enum_value_01000000000 "DIV"
+  attribute \enum_value_10000000000 "SPR"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 output 23 \mul_op__fn_unit$3
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 output 24 \mul_op__imm_data__imm$4
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 25 \mul_op__imm_data__imm_ok$5
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 26 \mul_op__rc__rc$6
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 27 \mul_op__rc__rc_ok$7
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 28 \mul_op__oe__oe$8
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 29 \mul_op__oe__oe_ok$9
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 30 \mul_op__invert_a$10
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 31 \mul_op__zero_a$11
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 32 \mul_op__invert_out$12
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 33 \mul_op__write_cr0$13
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 34 \mul_op__is_32bit$14
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 35 \mul_op__is_signed$15
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 output 36 \mul_op__insn$16
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 64 output 37 \o$17
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 output 38 \o_ok$18
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 4 output 39 \cr_a$19
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 output 40 \cr_a_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 2 output 41 \xer_ov$20
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 output 42 \xer_ov_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 output 43 \xer_so$21
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 output 44 \xer_so_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:23"
+  wire width 65 \o$22
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:26"
+  wire width 65 $23
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:26"
+  wire width 64 $24
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:26"
+  cell $not $25
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 3
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 3
-    parameter \Y_WIDTH 3
-    connect \A \q_int
-    connect \B $7
-    connect \Y $9
+    parameter \A_WIDTH 64
+    parameter \Y_WIDTH 64
+    connect \A \o
+    connect \Y $24
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
-  wire width 3 $11
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
-  cell $or $12
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:26"
+  cell $pos $26
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 3
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 3
-    parameter \Y_WIDTH 3
-    connect \A $9
-    connect \B \s_req
-    connect \Y $11
+    parameter \A_WIDTH 64
+    parameter \Y_WIDTH 65
+    connect \A $24
+    connect \Y $23
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 65 $27
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  cell $pos $28
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 64
+    parameter \Y_WIDTH 65
+    connect \A \o
+    connect \Y $27
   end
+  process $group_0
+    assign \o$22 65'00000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:25"
+    switch { \mul_op__invert_out }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:25"
+      case 1'1
+        assign \o$22 $23
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:27"
+      case
+        assign \o$22 $27
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:35"
+  wire width 64 \target
   process $group_1
-    assign \q_req 3'000
-    assign \q_req $11
+    assign \target 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \target \o$22 [63:0]
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
-  wire width 3 \qn_req
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
-  wire width 3 $13
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
-  cell $not $14
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:54"
+  wire width 1 \is_cmp
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:63"
+  wire width 1 $29
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:63"
+  cell $eq $30
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 3
-    parameter \Y_WIDTH 3
-    connect \A \q_req
-    connect \Y $13
+    parameter \A_WIDTH 7
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 7
+    parameter \Y_WIDTH 1
+    connect \A \mul_op__insn_type
+    connect \B 7'0001010
+    connect \Y $29
   end
   process $group_2
-    assign \qn_req 3'000
-    assign \qn_req $13
+    assign \is_cmp 1'0
+    assign \is_cmp $29
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62"
-  wire width 3 \qlq_req
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
-  wire width 3 $15
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
-  cell $or $16
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:55"
+  wire width 1 \is_cmpeqb
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:64"
+  wire width 1 $31
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:64"
+  cell $eq $32
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 3
+    parameter \A_WIDTH 7
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 3
-    parameter \Y_WIDTH 3
-    connect \A \q_req
-    connect \B \q_int
-    connect \Y $15
+    parameter \B_WIDTH 7
+    parameter \Y_WIDTH 1
+    connect \A \mul_op__insn_type
+    connect \B 7'0001100
+    connect \Y $31
   end
   process $group_3
-    assign \qlq_req 3'000
-    assign \qlq_req $15
+    assign \is_cmpeqb 1'0
+    assign \is_cmpeqb $31
     sync init
   end
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.rst_l"
-module \rst_l$98
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
-  wire width 1 input 2 \s_rst
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
-  wire width 1 input 3 \r_rst
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
-  wire width 1 \q_int
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
-  wire width 1 \q_int$next
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
-  wire width 1 $1
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
-  cell $not $2
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:53"
+  wire width 1 \msb_test
+  process $group_4
+    assign \msb_test 1'0
+    assign \msb_test \target [63]
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:50"
+  wire width 1 \is_nzero
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71"
+  wire width 1 $33
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71"
+  cell $reduce_bool $34
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
+    parameter \A_WIDTH 64
     parameter \Y_WIDTH 1
-    connect \A \r_rst
-    connect \Y $1
+    connect \A \target
+    connect \Y $33
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
-  wire width 1 $3
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
-  cell $and $4
+  process $group_5
+    assign \is_nzero 1'0
+    assign \is_nzero $33
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:51"
+  wire width 1 \is_positive
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77"
+  wire width 1 $35
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77"
+  cell $not $36
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \q_int
-    connect \B $1
-    connect \Y $3
+    connect \A \msb_test
+    connect \Y $35
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
-  wire width 1 $5
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
-  cell $or $6
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77"
+  wire width 1 $37
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77"
+  cell $and $38
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $3
-    connect \B \s_rst
-    connect \Y $5
+    connect \A \is_nzero
+    connect \B $35
+    connect \Y $37
   end
-  process $group_0
-    assign \q_int$next \q_int
-    assign \q_int$next $5
-    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+  process $group_6
+    assign \is_positive 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:72"
+    switch { \is_cmp }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:72"
       case 1'1
-        assign \q_int$next 1'0
+        assign \is_positive \msb_test
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:75"
+      case
+        assign \is_positive $37
     end
     sync init
-      update \q_int 1'0
-    sync posedge \clk
-      update \q_int \q_int$next
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
-  wire width 1 \q_rst
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
-  wire width 1 $7
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
-  cell $not $8
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:52"
+  wire width 1 \is_negative
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:74"
+  wire width 1 $39
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:74"
+  cell $not $40
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \r_rst
-    connect \Y $7
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
-  wire width 1 $9
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
-  cell $and $10
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \q_int
-    connect \B $7
-    connect \Y $9
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
-  wire width 1 $11
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
-  cell $or $12
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A $9
-    connect \B \s_rst
-    connect \Y $11
-  end
-  process $group_1
-    assign \q_rst 1'0
-    assign \q_rst $11
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
-  wire width 1 \qn_rst
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
-  wire width 1 $13
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
-  cell $not $14
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \q_rst
-    connect \Y $13
-  end
-  process $group_2
-    assign \qn_rst 1'0
-    assign \qn_rst $13
-    sync init
+    connect \A \msb_test
+    connect \Y $39
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62"
-  wire width 1 \qlq_rst
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
-  wire width 1 $15
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
-  cell $or $16
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:74"
+  wire width 1 $41
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:74"
+  cell $and $42
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \q_rst
-    connect \B \q_int
-    connect \Y $15
+    connect \A \is_nzero
+    connect \B $39
+    connect \Y $41
   end
-  process $group_3
-    assign \qlq_rst 1'0
-    assign \qlq_rst $15
+  process $group_7
+    assign \is_negative 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:72"
+    switch { \is_cmp }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:72"
+      case 1'1
+        assign \is_negative $41
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:75"
+      case
+        assign \is_negative \msb_test
+    end
     sync init
   end
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.rok_l"
-module \rok_l$99
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
-  wire width 1 output 2 \q_rdok
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
-  wire width 1 input 3 \s_rdok
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
-  wire width 1 input 4 \r_rdok
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
-  wire width 1 \q_int
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
-  wire width 1 \q_int$next
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
-  wire width 1 $1
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
-  cell $not $2
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \r_rdok
-    connect \Y $1
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
-  wire width 1 $3
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
-  cell $and $4
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \q_int
-    connect \B $1
-    connect \Y $3
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
-  wire width 1 $5
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
-  cell $or $6
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:57"
+  wire width 4 \cr0
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:82"
+  wire width 1 $43
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:82"
+  cell $not $44
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $3
-    connect \B \s_rdok
-    connect \Y $5
+    connect \A \is_nzero
+    connect \Y $43
   end
-  process $group_0
-    assign \q_int$next \q_int
-    assign \q_int$next $5
-    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+  process $group_8
+    assign \cr0 4'0000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:79"
+    switch { \is_cmpeqb }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:79"
       case 1'1
-        assign \q_int$next 1'0
+        assign \cr0 \cr_a
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81"
+      case
+        assign \cr0 { \is_negative \is_positive $43 \xer_so$21 }
     end
     sync init
-      update \q_int 1'0
-    sync posedge \clk
-      update \q_int \q_int$next
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
-  wire width 1 $7
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
-  cell $not $8
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \r_rdok
-    connect \Y $7
+  process $group_9
+    assign \o$17 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \o$17 \o$22 [63:0]
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
-  wire width 1 $9
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
-  cell $and $10
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \q_int
-    connect \B $7
-    connect \Y $9
+  process $group_10
+    assign \o_ok$18 1'0
+    assign \o_ok$18 \o_ok
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
-  wire width 1 $11
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
-  cell $or $12
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A $9
-    connect \B \s_rdok
-    connect \Y $11
+  process $group_11
+    assign \cr_a$19 4'0000
+    assign \cr_a$19 \cr0
+    sync init
   end
-  process $group_1
-    assign \q_rdok 1'0
-    assign \q_rdok $11
+  process $group_12
+    assign \cr_a_ok 1'0
+    assign \cr_a_ok \mul_op__write_cr0
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
-  wire width 1 \qn_rdok
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
-  wire width 1 $13
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
-  cell $not $14
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \q_rdok
-    connect \Y $13
+  process $group_13
+    assign \muxid$1 2'00
+    assign \muxid$1 \muxid
+    sync init
   end
-  process $group_2
-    assign \qn_rdok 1'0
-    assign \qn_rdok $13
+  process $group_14
+    assign \mul_op__insn_type$2 7'0000000
+    assign \mul_op__fn_unit$3 11'00000000000
+    assign \mul_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \mul_op__imm_data__imm_ok$5 1'0
+    assign \mul_op__rc__rc$6 1'0
+    assign \mul_op__rc__rc_ok$7 1'0
+    assign \mul_op__oe__oe$8 1'0
+    assign \mul_op__oe__oe_ok$9 1'0
+    assign \mul_op__invert_a$10 1'0
+    assign \mul_op__zero_a$11 1'0
+    assign \mul_op__invert_out$12 1'0
+    assign \mul_op__write_cr0$13 1'0
+    assign \mul_op__is_32bit$14 1'0
+    assign \mul_op__is_signed$15 1'0
+    assign \mul_op__insn$16 32'00000000000000000000000000000000
+    assign { \mul_op__insn$16 \mul_op__is_signed$15 \mul_op__is_32bit$14 \mul_op__write_cr0$13 \mul_op__invert_out$12 \mul_op__zero_a$11 \mul_op__invert_a$10 { \mul_op__oe__oe_ok$9 \mul_op__oe__oe$8 } { \mul_op__rc__rc_ok$7 \mul_op__rc__rc$6 } { \mul_op__imm_data__imm_ok$5 \mul_op__imm_data__imm$4 } \mul_op__fn_unit$3 \mul_op__insn_type$2 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__invert_out \mul_op__zero_a \mul_op__invert_a { \mul_op__oe__oe_ok \mul_op__oe__oe } { \mul_op__rc__rc_ok \mul_op__rc__rc } { \mul_op__imm_data__imm_ok \mul_op__imm_data__imm } \mul_op__fn_unit \mul_op__insn_type }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62"
-  wire width 1 \qlq_rdok
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
-  wire width 1 $15
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
-  cell $or $16
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:28"
+  wire width 1 \oe
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:29"
+  wire width 1 $45
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:29"
+  cell $and $46
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \q_rdok
-    connect \B \q_int
-    connect \Y $15
+    connect \A \mul_op__oe__oe
+    connect \B \mul_op__oe__oe_ok
+    connect \Y $45
   end
-  process $group_3
-    assign \qlq_rdok 1'0
-    assign \qlq_rdok $15
+  process $group_29
+    assign \oe 1'0
+    assign \oe $45
     sync init
   end
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alui_l"
-module \alui_l$100
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
-  wire width 1 output 2 \q_alui
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
-  wire width 1 input 3 \r_alui
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
-  wire width 1 input 4 \s_alui
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
-  wire width 1 \q_int
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
-  wire width 1 \q_int$next
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
-  wire width 1 $1
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
-  cell $not $2
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \r_alui
-    connect \Y $1
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
-  wire width 1 $3
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
-  cell $and $4
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \q_int
-    connect \B $1
-    connect \Y $3
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
-  wire width 1 $5
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
-  cell $or $6
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:56"
+  wire width 1 \so
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:32"
+  wire width 1 $47
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:32"
+  cell $or $48
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $3
-    connect \B \s_alui
-    connect \Y $5
+    connect \A \xer_so
+    connect \B \xer_ov [0]
+    connect \Y $47
   end
-  process $group_0
-    assign \q_int$next \q_int
-    assign \q_int$next $5
-    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+  process $group_30
+    assign \so 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30"
+    switch { \oe }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30"
       case 1'1
-        assign \q_int$next 1'0
+        assign \so $47
     end
     sync init
-      update \q_int 1'0
-    sync posedge \clk
-      update \q_int \q_int$next
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
-  wire width 1 $7
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
-  cell $not $8
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \r_alui
-    connect \Y $7
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
-  wire width 1 $9
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
-  cell $and $10
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \q_int
-    connect \B $7
-    connect \Y $9
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
-  wire width 1 $11
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
-  cell $or $12
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A $9
-    connect \B \s_alui
-    connect \Y $11
   end
-  process $group_1
-    assign \q_alui 1'0
-    assign \q_alui $11
+  process $group_31
+    assign \xer_so$21 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30"
+    switch { \oe }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30"
+      case 1'1
+        assign \xer_so$21 \so
+    end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
-  wire width 1 \qn_alui
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
-  wire width 1 $13
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
-  cell $not $14
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \q_alui
-    connect \Y $13
-  end
-  process $group_2
-    assign \qn_alui 1'0
-    assign \qn_alui $13
+  process $group_32
+    assign \xer_so_ok 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30"
+    switch { \oe }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30"
+      case 1'1
+        assign \xer_so_ok 1'1
+    end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62"
-  wire width 1 \qlq_alui
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
-  wire width 1 $15
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
-  cell $or $16
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \q_alui
-    connect \B \q_int
-    connect \Y $15
-  end
-  process $group_3
-    assign \qlq_alui 1'0
-    assign \qlq_alui $15
+  process $group_33
+    assign \xer_ov$20 2'00
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30"
+    switch { \oe }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30"
+      case 1'1
+        assign \xer_ov$20 \xer_ov
+    end
     sync init
   end
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_l"
-module \alu_l$101
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
-  wire width 1 output 2 \q_alu
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
-  wire width 1 input 3 \r_alu
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
-  wire width 1 input 4 \s_alu
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
-  wire width 1 \q_int
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
-  wire width 1 \q_int$next
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
-  wire width 1 $1
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
-  cell $not $2
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \r_alu
-    connect \Y $1
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
-  wire width 1 $3
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
-  cell $and $4
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \q_int
-    connect \B $1
-    connect \Y $3
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
-  wire width 1 $5
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
-  cell $or $6
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A $3
-    connect \B \s_alu
-    connect \Y $5
-  end
-  process $group_0
-    assign \q_int$next \q_int
-    assign \q_int$next $5
-    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+  process $group_34
+    assign \xer_ov_ok 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30"
+    switch { \oe }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30"
       case 1'1
-        assign \q_int$next 1'0
+        assign \xer_ov_ok 1'1
     end
-    sync init
-      update \q_int 1'0
-    sync posedge \clk
-      update \q_int \q_int$next
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
-  wire width 1 $7
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
-  cell $not $8
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \r_alu
-    connect \Y $7
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
-  wire width 1 $9
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
-  cell $and $10
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \q_int
-    connect \B $7
-    connect \Y $9
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
-  wire width 1 $11
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
-  cell $or $12
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A $9
-    connect \B \s_alu
-    connect \Y $11
-  end
-  process $group_1
-    assign \q_alu 1'0
-    assign \q_alu $11
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
-  wire width 1 \qn_alu
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
-  wire width 1 $13
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
-  cell $not $14
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \q_alu
-    connect \Y $13
-  end
-  process $group_2
-    assign \qn_alu 1'0
-    assign \qn_alu $13
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62"
-  wire width 1 \qlq_alu
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
-  wire width 1 $15
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
-  cell $or $16
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \q_alu
-    connect \B \q_int
-    connect \Y $15
-  end
-  process $group_3
-    assign \qlq_alu 1'0
-    assign \qlq_alu $15
     sync init
   end
 end
 attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0"
-module \shiftrot0
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
+attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe3"
+module \mul_pipe3
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153"
+  wire width 1 input 2 \p_valid_i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154"
+  wire width 1 output 3 \p_ready_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
+  wire width 2 input 4 \muxid
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
   attribute \enum_value_0000001 "OP_NOP"
@@ -105699,7 +105647,7 @@ module \shiftrot0
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 7 input 2 \oper_i_alu_shift_rot0__insn_type
+  wire width 7 input 5 \mul_op__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -105713,81 +105661,236 @@ module \shiftrot0
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 11 input 3 \oper_i_alu_shift_rot0__fn_unit
+  wire width 11 input 6 \mul_op__fn_unit
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 64 input 4 \oper_i_alu_shift_rot0__imm_data__imm
+  wire width 64 input 7 \mul_op__imm_data__imm
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 5 \oper_i_alu_shift_rot0__imm_data__imm_ok
+  wire width 1 input 8 \mul_op__imm_data__imm_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 6 \oper_i_alu_shift_rot0__rc__rc
+  wire width 1 input 9 \mul_op__rc__rc
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 7 \oper_i_alu_shift_rot0__rc__rc_ok
+  wire width 1 input 10 \mul_op__rc__rc_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 8 \oper_i_alu_shift_rot0__oe__oe
+  wire width 1 input 11 \mul_op__oe__oe
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 9 \oper_i_alu_shift_rot0__oe__oe_ok
-  attribute \enum_base_type "CryIn"
-  attribute \enum_value_00 "ZERO"
-  attribute \enum_value_01 "ONE"
-  attribute \enum_value_10 "CA"
+  wire width 1 input 12 \mul_op__oe__oe_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 2 input 11 \oper_i_alu_shift_rot0__input_carry
+  wire width 1 input 13 \mul_op__invert_a
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 12 \oper_i_alu_shift_rot0__output_carry
+  wire width 1 input 14 \mul_op__zero_a
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 13 \oper_i_alu_shift_rot0__input_cr
+  wire width 1 input 15 \mul_op__invert_out
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 14 \oper_i_alu_shift_rot0__output_cr
+  wire width 1 input 16 \mul_op__write_cr0
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 15 \oper_i_alu_shift_rot0__is_32bit
+  wire width 1 input 17 \mul_op__is_32bit
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 16 \oper_i_alu_shift_rot0__is_signed
+  wire width 1 input 18 \mul_op__is_signed
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 32 input 17 \oper_i_alu_shift_rot0__insn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
-  wire width 1 input 18 \cu_issue_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:106"
-  wire width 1 output 19 \cu_busy_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
-  wire width 4 input 20 \cu_rdmaskn_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 4 output 21 \cu_rd__rel_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 4 input 22 \cu_rd__go_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
-  wire width 64 input 23 \src1_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
-  wire width 64 input 24 \src2_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
-  wire width 64 input 25 \src3_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
-  wire width 2 input 26 \src4_i
+  wire width 32 input 19 \mul_op__insn
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
+  wire width 129 input 20 \o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
+  wire width 1 input 21 \xer_so
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23"
+  wire width 1 input 22 \neg_res
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24"
+  wire width 1 input 23 \neg_res32
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
+  wire width 1 output 24 \n_valid_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
+  wire width 1 input 25 \n_ready_i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
+  wire width 2 output 26 \muxid$1
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
+  wire width 2 \muxid$1$next
+  attribute \enum_base_type "MicrOp"
+  attribute \enum_value_0000000 "OP_ILLEGAL"
+  attribute \enum_value_0000001 "OP_NOP"
+  attribute \enum_value_0000010 "OP_ADD"
+  attribute \enum_value_0000011 "OP_ADDPCIS"
+  attribute \enum_value_0000100 "OP_AND"
+  attribute \enum_value_0000101 "OP_ATTN"
+  attribute \enum_value_0000110 "OP_B"
+  attribute \enum_value_0000111 "OP_BC"
+  attribute \enum_value_0001000 "OP_BCREG"
+  attribute \enum_value_0001001 "OP_BPERM"
+  attribute \enum_value_0001010 "OP_CMP"
+  attribute \enum_value_0001011 "OP_CMPB"
+  attribute \enum_value_0001100 "OP_CMPEQB"
+  attribute \enum_value_0001101 "OP_CMPRB"
+  attribute \enum_value_0001110 "OP_CNTZ"
+  attribute \enum_value_0001111 "OP_CRAND"
+  attribute \enum_value_0010000 "OP_CRANDC"
+  attribute \enum_value_0010001 "OP_CREQV"
+  attribute \enum_value_0010010 "OP_CRNAND"
+  attribute \enum_value_0010011 "OP_CRNOR"
+  attribute \enum_value_0010100 "OP_CROR"
+  attribute \enum_value_0010101 "OP_CRORC"
+  attribute \enum_value_0010110 "OP_CRXOR"
+  attribute \enum_value_0010111 "OP_DARN"
+  attribute \enum_value_0011000 "OP_DCBF"
+  attribute \enum_value_0011001 "OP_DCBST"
+  attribute \enum_value_0011010 "OP_DCBT"
+  attribute \enum_value_0011011 "OP_DCBTST"
+  attribute \enum_value_0011100 "OP_DCBZ"
+  attribute \enum_value_0011101 "OP_DIV"
+  attribute \enum_value_0011110 "OP_DIVE"
+  attribute \enum_value_0011111 "OP_EXTS"
+  attribute \enum_value_0100000 "OP_EXTSWSLI"
+  attribute \enum_value_0100001 "OP_ICBI"
+  attribute \enum_value_0100010 "OP_ICBT"
+  attribute \enum_value_0100011 "OP_ISEL"
+  attribute \enum_value_0100100 "OP_ISYNC"
+  attribute \enum_value_0100101 "OP_LOAD"
+  attribute \enum_value_0100110 "OP_STORE"
+  attribute \enum_value_0100111 "OP_MADDHD"
+  attribute \enum_value_0101000 "OP_MADDHDU"
+  attribute \enum_value_0101001 "OP_MADDLD"
+  attribute \enum_value_0101010 "OP_MCRF"
+  attribute \enum_value_0101011 "OP_MCRXR"
+  attribute \enum_value_0101100 "OP_MCRXRX"
+  attribute \enum_value_0101101 "OP_MFCR"
+  attribute \enum_value_0101110 "OP_MFSPR"
+  attribute \enum_value_0101111 "OP_MOD"
+  attribute \enum_value_0110000 "OP_MTCRF"
+  attribute \enum_value_0110001 "OP_MTSPR"
+  attribute \enum_value_0110010 "OP_MUL_L64"
+  attribute \enum_value_0110011 "OP_MUL_H64"
+  attribute \enum_value_0110100 "OP_MUL_H32"
+  attribute \enum_value_0110101 "OP_OR"
+  attribute \enum_value_0110110 "OP_POPCNT"
+  attribute \enum_value_0110111 "OP_PRTY"
+  attribute \enum_value_0111000 "OP_RLC"
+  attribute \enum_value_0111001 "OP_RLCL"
+  attribute \enum_value_0111010 "OP_RLCR"
+  attribute \enum_value_0111011 "OP_SETB"
+  attribute \enum_value_0111100 "OP_SHL"
+  attribute \enum_value_0111101 "OP_SHR"
+  attribute \enum_value_0111110 "OP_SYNC"
+  attribute \enum_value_0111111 "OP_TRAP"
+  attribute \enum_value_1000011 "OP_XOR"
+  attribute \enum_value_1000100 "OP_SIM_CONFIG"
+  attribute \enum_value_1000101 "OP_CROP"
+  attribute \enum_value_1000110 "OP_RFID"
+  attribute \enum_value_1000111 "OP_MFMSR"
+  attribute \enum_value_1001000 "OP_MTMSRD"
+  attribute \enum_value_1001001 "OP_SC"
+  attribute \enum_value_1001010 "OP_MTMSR"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 output 27 \mul_op__insn_type$2
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 \mul_op__insn_type$2$next
+  attribute \enum_base_type "Function"
+  attribute \enum_value_00000000000 "NONE"
+  attribute \enum_value_00000000010 "ALU"
+  attribute \enum_value_00000000100 "LDST"
+  attribute \enum_value_00000001000 "SHIFT_ROT"
+  attribute \enum_value_00000010000 "LOGICAL"
+  attribute \enum_value_00000100000 "BRANCH"
+  attribute \enum_value_00001000000 "CR"
+  attribute \enum_value_00010000000 "TRAP"
+  attribute \enum_value_00100000000 "MUL"
+  attribute \enum_value_01000000000 "DIV"
+  attribute \enum_value_10000000000 "SPR"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 output 28 \mul_op__fn_unit$3
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 \mul_op__fn_unit$3$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 output 29 \mul_op__imm_data__imm$4
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 \mul_op__imm_data__imm$4$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 30 \mul_op__imm_data__imm_ok$5
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_op__imm_data__imm_ok$5$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 31 \mul_op__rc__rc$6
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_op__rc__rc$6$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 32 \mul_op__rc__rc_ok$7
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_op__rc__rc_ok$7$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 33 \mul_op__oe__oe$8
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_op__oe__oe$8$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 34 \mul_op__oe__oe_ok$9
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_op__oe__oe_ok$9$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 35 \mul_op__invert_a$10
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_op__invert_a$10$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 36 \mul_op__zero_a$11
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_op__zero_a$11$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 37 \mul_op__invert_out$12
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_op__invert_out$12$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 38 \mul_op__write_cr0$13
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_op__write_cr0$13$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 39 \mul_op__is_32bit$14
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_op__is_32bit$14$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 40 \mul_op__is_signed$15
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_op__is_signed$15$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 output 41 \mul_op__insn$16
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \mul_op__insn$16$next
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 27 \o_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 3 output 28 \cu_wr__rel_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 3 input 29 \cu_wr__go_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
-  wire width 64 output 30 \dest1_o
+  wire width 64 output 42 \o$17
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 31 \cr_a_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
-  wire width 4 output 32 \dest2_o
+  wire width 64 \o$17$next
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 33 \xer_ca_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
-  wire width 2 output 34 \dest3_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
-  wire width 1 \alu_shift_rot0_n_valid_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
-  wire width 1 \alu_shift_rot0_n_ready_i
+  wire width 1 output 43 \o_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 64 \alu_shift_rot0_o
+  wire width 1 \o_ok$next
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 4 \alu_shift_rot0_cr_a
+  wire width 4 output 44 \cr_a
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 2 \alu_shift_rot0_xer_ca
+  wire width 4 \cr_a$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 output 45 \cr_a_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 \cr_a_ok$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 2 output 46 \xer_ov
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 2 \xer_ov$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 output 47 \xer_ov_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 \xer_ov_ok$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 output 48 \xer_so$18
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 \xer_so$18$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 output 49 \xer_so_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 \xer_so_ok$next
+  cell \p$94 \p
+    connect \p_valid_i \p_valid_i
+    connect \p_ready_o \p_ready_o
+  end
+  cell \n$95 \n
+    connect \n_valid_o \n_valid_o
+    connect \n_ready_i \n_ready_i
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
+  wire width 2 \mul3_muxid
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
   attribute \enum_value_0000001 "OP_NOP"
@@ -105862,7 +105965,7 @@ module \shiftrot0
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 7 \alu_shift_rot0_sr_op__insn_type
+  wire width 7 \mul3_mul_op__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -105876,821 +105979,1082 @@ module \shiftrot0
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 11 \alu_shift_rot0_sr_op__fn_unit
+  wire width 11 \mul3_mul_op__fn_unit
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 64 \alu_shift_rot0_sr_op__imm_data__imm
+  wire width 64 \mul3_mul_op__imm_data__imm
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \alu_shift_rot0_sr_op__imm_data__imm_ok
+  wire width 1 \mul3_mul_op__imm_data__imm_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \alu_shift_rot0_sr_op__rc__rc
+  wire width 1 \mul3_mul_op__rc__rc
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \alu_shift_rot0_sr_op__rc__rc_ok
+  wire width 1 \mul3_mul_op__rc__rc_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \alu_shift_rot0_sr_op__oe__oe
+  wire width 1 \mul3_mul_op__oe__oe
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \alu_shift_rot0_sr_op__oe__oe_ok
-  attribute \enum_base_type "CryIn"
-  attribute \enum_value_00 "ZERO"
-  attribute \enum_value_01 "ONE"
-  attribute \enum_value_10 "CA"
+  wire width 1 \mul3_mul_op__oe__oe_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 2 \alu_shift_rot0_sr_op__input_carry
+  wire width 1 \mul3_mul_op__invert_a
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \alu_shift_rot0_sr_op__output_carry
+  wire width 1 \mul3_mul_op__zero_a
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \alu_shift_rot0_sr_op__input_cr
+  wire width 1 \mul3_mul_op__invert_out
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \alu_shift_rot0_sr_op__output_cr
+  wire width 1 \mul3_mul_op__write_cr0
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \alu_shift_rot0_sr_op__is_32bit
+  wire width 1 \mul3_mul_op__is_32bit
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \alu_shift_rot0_sr_op__is_signed
+  wire width 1 \mul3_mul_op__is_signed
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 32 \alu_shift_rot0_sr_op__insn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
-  wire width 64 \alu_shift_rot0_ra
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
-  wire width 64 \alu_shift_rot0_rb
+  wire width 32 \mul3_mul_op__insn
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
-  wire width 64 \alu_shift_rot0_rc
+  wire width 129 \mul3_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
-  wire width 2 \alu_shift_rot0_xer_ca$1
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153"
-  wire width 1 \alu_shift_rot0_p_valid_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154"
-  wire width 1 \alu_shift_rot0_p_ready_o
-  cell \alu_shift_rot0 \alu_shift_rot0
-    connect \rst \rst
-    connect \clk \clk
-    connect \o_ok \o_ok
-    connect \cr_a_ok \cr_a_ok
-    connect \xer_ca_ok \xer_ca_ok
-    connect \n_valid_o \alu_shift_rot0_n_valid_o
-    connect \n_ready_i \alu_shift_rot0_n_ready_i
-    connect \o \alu_shift_rot0_o
-    connect \cr_a \alu_shift_rot0_cr_a
-    connect \xer_ca \alu_shift_rot0_xer_ca
-    connect \sr_op__insn_type \alu_shift_rot0_sr_op__insn_type
-    connect \sr_op__fn_unit \alu_shift_rot0_sr_op__fn_unit
-    connect \sr_op__imm_data__imm \alu_shift_rot0_sr_op__imm_data__imm
-    connect \sr_op__imm_data__imm_ok \alu_shift_rot0_sr_op__imm_data__imm_ok
-    connect \sr_op__rc__rc \alu_shift_rot0_sr_op__rc__rc
-    connect \sr_op__rc__rc_ok \alu_shift_rot0_sr_op__rc__rc_ok
-    connect \sr_op__oe__oe \alu_shift_rot0_sr_op__oe__oe
-    connect \sr_op__oe__oe_ok \alu_shift_rot0_sr_op__oe__oe_ok
-    connect \sr_op__input_carry \alu_shift_rot0_sr_op__input_carry
-    connect \sr_op__output_carry \alu_shift_rot0_sr_op__output_carry
-    connect \sr_op__input_cr \alu_shift_rot0_sr_op__input_cr
-    connect \sr_op__output_cr \alu_shift_rot0_sr_op__output_cr
-    connect \sr_op__is_32bit \alu_shift_rot0_sr_op__is_32bit
-    connect \sr_op__is_signed \alu_shift_rot0_sr_op__is_signed
-    connect \sr_op__insn \alu_shift_rot0_sr_op__insn
-    connect \ra \alu_shift_rot0_ra
-    connect \rb \alu_shift_rot0_rb
-    connect \rc \alu_shift_rot0_rc
-    connect \xer_ca$1 \alu_shift_rot0_xer_ca$1
-    connect \p_valid_i \alu_shift_rot0_p_valid_i
-    connect \p_ready_o \alu_shift_rot0_p_ready_o
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
-  wire width 4 \src_l_s_src
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
-  wire width 4 \src_l_s_src$next
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
-  wire width 4 \src_l_r_src
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
-  wire width 4 \src_l_r_src$next
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
-  wire width 4 \src_l_q_src
-  cell \src_l$95 \src_l
-    connect \rst \rst
-    connect \clk \clk
-    connect \s_src \src_l_s_src
-    connect \r_src \src_l_r_src
-    connect \q_src \src_l_q_src
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
-  wire width 1 \opc_l_s_opc
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
-  wire width 1 \opc_l_s_opc$next
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
-  wire width 1 \opc_l_r_opc
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
-  wire width 1 \opc_l_r_opc$next
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
-  wire width 1 \opc_l_q_opc
-  cell \opc_l$96 \opc_l
-    connect \rst \rst
-    connect \clk \clk
-    connect \s_opc \opc_l_s_opc
-    connect \r_opc \opc_l_r_opc
-    connect \q_opc \opc_l_q_opc
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
-  wire width 3 \req_l_q_req
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
-  wire width 3 \req_l_s_req
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
-  wire width 3 \req_l_r_req
-  cell \req_l$97 \req_l
-    connect \rst \rst
-    connect \clk \clk
-    connect \q_req \req_l_q_req
-    connect \s_req \req_l_s_req
-    connect \r_req \req_l_r_req
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
-  wire width 1 \rst_l_s_rst
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
-  wire width 1 \rst_l_r_rst
-  cell \rst_l$98 \rst_l
-    connect \rst \rst
-    connect \clk \clk
-    connect \s_rst \rst_l_s_rst
-    connect \r_rst \rst_l_r_rst
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
-  wire width 1 \rok_l_q_rdok
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
-  wire width 1 \rok_l_s_rdok
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
-  wire width 1 \rok_l_r_rdok
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
-  wire width 1 \rok_l_r_rdok$next
-  cell \rok_l$99 \rok_l
-    connect \rst \rst
-    connect \clk \clk
-    connect \q_rdok \rok_l_q_rdok
-    connect \s_rdok \rok_l_s_rdok
-    connect \r_rdok \rok_l_r_rdok
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
-  wire width 1 \alui_l_q_alui
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
-  wire width 1 \alui_l_r_alui
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
-  wire width 1 \alui_l_r_alui$next
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
-  wire width 1 \alui_l_s_alui
-  cell \alui_l$100 \alui_l
-    connect \rst \rst
-    connect \clk \clk
-    connect \q_alui \alui_l_q_alui
-    connect \r_alui \alui_l_r_alui
-    connect \s_alui \alui_l_s_alui
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
-  wire width 1 \alu_l_q_alu
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
-  wire width 1 \alu_l_r_alu
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
-  wire width 1 \alu_l_r_alu$next
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
-  wire width 1 \alu_l_s_alu
-  cell \alu_l$101 \alu_l
-    connect \rst \rst
-    connect \clk \clk
-    connect \q_alu \alu_l_q_alu
-    connect \r_alu \alu_l_r_alu
-    connect \s_alu \alu_l_s_alu
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:186"
-  wire width 1 \all_rd
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:187"
-  wire width 1 $2
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:187"
-  cell $and $3
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \cu_busy_o
-    connect \B \rok_l_q_rdok
-    connect \Y $2
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188"
-  wire width 1 $4
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188"
-  wire width 4 $5
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188"
-  cell $not $6
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 4
-    parameter \Y_WIDTH 4
-    connect \A \cu_rd__rel_o
-    connect \Y $5
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188"
-  wire width 4 $7
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188"
-  cell $or $8
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 4
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 4
-    parameter \Y_WIDTH 4
-    connect \A $5
-    connect \B \cu_rd__go_i
-    connect \Y $7
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188"
-  cell $reduce_and $9
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 4
-    parameter \Y_WIDTH 1
-    connect \A $7
-    connect \Y $4
+  wire width 1 \mul3_xer_so
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23"
+  wire width 1 \mul3_neg_res
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
+  wire width 2 \mul3_muxid$19
+  attribute \enum_base_type "MicrOp"
+  attribute \enum_value_0000000 "OP_ILLEGAL"
+  attribute \enum_value_0000001 "OP_NOP"
+  attribute \enum_value_0000010 "OP_ADD"
+  attribute \enum_value_0000011 "OP_ADDPCIS"
+  attribute \enum_value_0000100 "OP_AND"
+  attribute \enum_value_0000101 "OP_ATTN"
+  attribute \enum_value_0000110 "OP_B"
+  attribute \enum_value_0000111 "OP_BC"
+  attribute \enum_value_0001000 "OP_BCREG"
+  attribute \enum_value_0001001 "OP_BPERM"
+  attribute \enum_value_0001010 "OP_CMP"
+  attribute \enum_value_0001011 "OP_CMPB"
+  attribute \enum_value_0001100 "OP_CMPEQB"
+  attribute \enum_value_0001101 "OP_CMPRB"
+  attribute \enum_value_0001110 "OP_CNTZ"
+  attribute \enum_value_0001111 "OP_CRAND"
+  attribute \enum_value_0010000 "OP_CRANDC"
+  attribute \enum_value_0010001 "OP_CREQV"
+  attribute \enum_value_0010010 "OP_CRNAND"
+  attribute \enum_value_0010011 "OP_CRNOR"
+  attribute \enum_value_0010100 "OP_CROR"
+  attribute \enum_value_0010101 "OP_CRORC"
+  attribute \enum_value_0010110 "OP_CRXOR"
+  attribute \enum_value_0010111 "OP_DARN"
+  attribute \enum_value_0011000 "OP_DCBF"
+  attribute \enum_value_0011001 "OP_DCBST"
+  attribute \enum_value_0011010 "OP_DCBT"
+  attribute \enum_value_0011011 "OP_DCBTST"
+  attribute \enum_value_0011100 "OP_DCBZ"
+  attribute \enum_value_0011101 "OP_DIV"
+  attribute \enum_value_0011110 "OP_DIVE"
+  attribute \enum_value_0011111 "OP_EXTS"
+  attribute \enum_value_0100000 "OP_EXTSWSLI"
+  attribute \enum_value_0100001 "OP_ICBI"
+  attribute \enum_value_0100010 "OP_ICBT"
+  attribute \enum_value_0100011 "OP_ISEL"
+  attribute \enum_value_0100100 "OP_ISYNC"
+  attribute \enum_value_0100101 "OP_LOAD"
+  attribute \enum_value_0100110 "OP_STORE"
+  attribute \enum_value_0100111 "OP_MADDHD"
+  attribute \enum_value_0101000 "OP_MADDHDU"
+  attribute \enum_value_0101001 "OP_MADDLD"
+  attribute \enum_value_0101010 "OP_MCRF"
+  attribute \enum_value_0101011 "OP_MCRXR"
+  attribute \enum_value_0101100 "OP_MCRXRX"
+  attribute \enum_value_0101101 "OP_MFCR"
+  attribute \enum_value_0101110 "OP_MFSPR"
+  attribute \enum_value_0101111 "OP_MOD"
+  attribute \enum_value_0110000 "OP_MTCRF"
+  attribute \enum_value_0110001 "OP_MTSPR"
+  attribute \enum_value_0110010 "OP_MUL_L64"
+  attribute \enum_value_0110011 "OP_MUL_H64"
+  attribute \enum_value_0110100 "OP_MUL_H32"
+  attribute \enum_value_0110101 "OP_OR"
+  attribute \enum_value_0110110 "OP_POPCNT"
+  attribute \enum_value_0110111 "OP_PRTY"
+  attribute \enum_value_0111000 "OP_RLC"
+  attribute \enum_value_0111001 "OP_RLCL"
+  attribute \enum_value_0111010 "OP_RLCR"
+  attribute \enum_value_0111011 "OP_SETB"
+  attribute \enum_value_0111100 "OP_SHL"
+  attribute \enum_value_0111101 "OP_SHR"
+  attribute \enum_value_0111110 "OP_SYNC"
+  attribute \enum_value_0111111 "OP_TRAP"
+  attribute \enum_value_1000011 "OP_XOR"
+  attribute \enum_value_1000100 "OP_SIM_CONFIG"
+  attribute \enum_value_1000101 "OP_CROP"
+  attribute \enum_value_1000110 "OP_RFID"
+  attribute \enum_value_1000111 "OP_MFMSR"
+  attribute \enum_value_1001000 "OP_MTMSRD"
+  attribute \enum_value_1001001 "OP_SC"
+  attribute \enum_value_1001010 "OP_MTMSR"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 \mul3_mul_op__insn_type$20
+  attribute \enum_base_type "Function"
+  attribute \enum_value_00000000000 "NONE"
+  attribute \enum_value_00000000010 "ALU"
+  attribute \enum_value_00000000100 "LDST"
+  attribute \enum_value_00000001000 "SHIFT_ROT"
+  attribute \enum_value_00000010000 "LOGICAL"
+  attribute \enum_value_00000100000 "BRANCH"
+  attribute \enum_value_00001000000 "CR"
+  attribute \enum_value_00010000000 "TRAP"
+  attribute \enum_value_00100000000 "MUL"
+  attribute \enum_value_01000000000 "DIV"
+  attribute \enum_value_10000000000 "SPR"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 \mul3_mul_op__fn_unit$21
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 \mul3_mul_op__imm_data__imm$22
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul3_mul_op__imm_data__imm_ok$23
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul3_mul_op__rc__rc$24
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul3_mul_op__rc__rc_ok$25
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul3_mul_op__oe__oe$26
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul3_mul_op__oe__oe_ok$27
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul3_mul_op__invert_a$28
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul3_mul_op__zero_a$29
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul3_mul_op__invert_out$30
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul3_mul_op__write_cr0$31
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul3_mul_op__is_32bit$32
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul3_mul_op__is_signed$33
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \mul3_mul_op__insn$34
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 64 \mul3_o$35
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 \mul3_o_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 2 \mul3_xer_ov
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 \mul3_xer_ov_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 \mul3_xer_so$36
+  cell \mul3 \mul3
+    connect \muxid \mul3_muxid
+    connect \mul_op__insn_type \mul3_mul_op__insn_type
+    connect \mul_op__fn_unit \mul3_mul_op__fn_unit
+    connect \mul_op__imm_data__imm \mul3_mul_op__imm_data__imm
+    connect \mul_op__imm_data__imm_ok \mul3_mul_op__imm_data__imm_ok
+    connect \mul_op__rc__rc \mul3_mul_op__rc__rc
+    connect \mul_op__rc__rc_ok \mul3_mul_op__rc__rc_ok
+    connect \mul_op__oe__oe \mul3_mul_op__oe__oe
+    connect \mul_op__oe__oe_ok \mul3_mul_op__oe__oe_ok
+    connect \mul_op__invert_a \mul3_mul_op__invert_a
+    connect \mul_op__zero_a \mul3_mul_op__zero_a
+    connect \mul_op__invert_out \mul3_mul_op__invert_out
+    connect \mul_op__write_cr0 \mul3_mul_op__write_cr0
+    connect \mul_op__is_32bit \mul3_mul_op__is_32bit
+    connect \mul_op__is_signed \mul3_mul_op__is_signed
+    connect \mul_op__insn \mul3_mul_op__insn
+    connect \o \mul3_o
+    connect \xer_so \mul3_xer_so
+    connect \neg_res \mul3_neg_res
+    connect \muxid$1 \mul3_muxid$19
+    connect \mul_op__insn_type$2 \mul3_mul_op__insn_type$20
+    connect \mul_op__fn_unit$3 \mul3_mul_op__fn_unit$21
+    connect \mul_op__imm_data__imm$4 \mul3_mul_op__imm_data__imm$22
+    connect \mul_op__imm_data__imm_ok$5 \mul3_mul_op__imm_data__imm_ok$23
+    connect \mul_op__rc__rc$6 \mul3_mul_op__rc__rc$24
+    connect \mul_op__rc__rc_ok$7 \mul3_mul_op__rc__rc_ok$25
+    connect \mul_op__oe__oe$8 \mul3_mul_op__oe__oe$26
+    connect \mul_op__oe__oe_ok$9 \mul3_mul_op__oe__oe_ok$27
+    connect \mul_op__invert_a$10 \mul3_mul_op__invert_a$28
+    connect \mul_op__zero_a$11 \mul3_mul_op__zero_a$29
+    connect \mul_op__invert_out$12 \mul3_mul_op__invert_out$30
+    connect \mul_op__write_cr0$13 \mul3_mul_op__write_cr0$31
+    connect \mul_op__is_32bit$14 \mul3_mul_op__is_32bit$32
+    connect \mul_op__is_signed$15 \mul3_mul_op__is_signed$33
+    connect \mul_op__insn$16 \mul3_mul_op__insn$34
+    connect \o$17 \mul3_o$35
+    connect \o_ok \mul3_o_ok
+    connect \xer_ov \mul3_xer_ov
+    connect \xer_ov_ok \mul3_xer_ov_ok
+    connect \xer_so$18 \mul3_xer_so$36
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188"
-  wire width 1 $10
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188"
-  cell $and $11
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A $2
-    connect \B $4
-    connect \Y $10
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
+  wire width 2 \output_muxid
+  attribute \enum_base_type "MicrOp"
+  attribute \enum_value_0000000 "OP_ILLEGAL"
+  attribute \enum_value_0000001 "OP_NOP"
+  attribute \enum_value_0000010 "OP_ADD"
+  attribute \enum_value_0000011 "OP_ADDPCIS"
+  attribute \enum_value_0000100 "OP_AND"
+  attribute \enum_value_0000101 "OP_ATTN"
+  attribute \enum_value_0000110 "OP_B"
+  attribute \enum_value_0000111 "OP_BC"
+  attribute \enum_value_0001000 "OP_BCREG"
+  attribute \enum_value_0001001 "OP_BPERM"
+  attribute \enum_value_0001010 "OP_CMP"
+  attribute \enum_value_0001011 "OP_CMPB"
+  attribute \enum_value_0001100 "OP_CMPEQB"
+  attribute \enum_value_0001101 "OP_CMPRB"
+  attribute \enum_value_0001110 "OP_CNTZ"
+  attribute \enum_value_0001111 "OP_CRAND"
+  attribute \enum_value_0010000 "OP_CRANDC"
+  attribute \enum_value_0010001 "OP_CREQV"
+  attribute \enum_value_0010010 "OP_CRNAND"
+  attribute \enum_value_0010011 "OP_CRNOR"
+  attribute \enum_value_0010100 "OP_CROR"
+  attribute \enum_value_0010101 "OP_CRORC"
+  attribute \enum_value_0010110 "OP_CRXOR"
+  attribute \enum_value_0010111 "OP_DARN"
+  attribute \enum_value_0011000 "OP_DCBF"
+  attribute \enum_value_0011001 "OP_DCBST"
+  attribute \enum_value_0011010 "OP_DCBT"
+  attribute \enum_value_0011011 "OP_DCBTST"
+  attribute \enum_value_0011100 "OP_DCBZ"
+  attribute \enum_value_0011101 "OP_DIV"
+  attribute \enum_value_0011110 "OP_DIVE"
+  attribute \enum_value_0011111 "OP_EXTS"
+  attribute \enum_value_0100000 "OP_EXTSWSLI"
+  attribute \enum_value_0100001 "OP_ICBI"
+  attribute \enum_value_0100010 "OP_ICBT"
+  attribute \enum_value_0100011 "OP_ISEL"
+  attribute \enum_value_0100100 "OP_ISYNC"
+  attribute \enum_value_0100101 "OP_LOAD"
+  attribute \enum_value_0100110 "OP_STORE"
+  attribute \enum_value_0100111 "OP_MADDHD"
+  attribute \enum_value_0101000 "OP_MADDHDU"
+  attribute \enum_value_0101001 "OP_MADDLD"
+  attribute \enum_value_0101010 "OP_MCRF"
+  attribute \enum_value_0101011 "OP_MCRXR"
+  attribute \enum_value_0101100 "OP_MCRXRX"
+  attribute \enum_value_0101101 "OP_MFCR"
+  attribute \enum_value_0101110 "OP_MFSPR"
+  attribute \enum_value_0101111 "OP_MOD"
+  attribute \enum_value_0110000 "OP_MTCRF"
+  attribute \enum_value_0110001 "OP_MTSPR"
+  attribute \enum_value_0110010 "OP_MUL_L64"
+  attribute \enum_value_0110011 "OP_MUL_H64"
+  attribute \enum_value_0110100 "OP_MUL_H32"
+  attribute \enum_value_0110101 "OP_OR"
+  attribute \enum_value_0110110 "OP_POPCNT"
+  attribute \enum_value_0110111 "OP_PRTY"
+  attribute \enum_value_0111000 "OP_RLC"
+  attribute \enum_value_0111001 "OP_RLCL"
+  attribute \enum_value_0111010 "OP_RLCR"
+  attribute \enum_value_0111011 "OP_SETB"
+  attribute \enum_value_0111100 "OP_SHL"
+  attribute \enum_value_0111101 "OP_SHR"
+  attribute \enum_value_0111110 "OP_SYNC"
+  attribute \enum_value_0111111 "OP_TRAP"
+  attribute \enum_value_1000011 "OP_XOR"
+  attribute \enum_value_1000100 "OP_SIM_CONFIG"
+  attribute \enum_value_1000101 "OP_CROP"
+  attribute \enum_value_1000110 "OP_RFID"
+  attribute \enum_value_1000111 "OP_MFMSR"
+  attribute \enum_value_1001000 "OP_MTMSRD"
+  attribute \enum_value_1001001 "OP_SC"
+  attribute \enum_value_1001010 "OP_MTMSR"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 \output_mul_op__insn_type
+  attribute \enum_base_type "Function"
+  attribute \enum_value_00000000000 "NONE"
+  attribute \enum_value_00000000010 "ALU"
+  attribute \enum_value_00000000100 "LDST"
+  attribute \enum_value_00000001000 "SHIFT_ROT"
+  attribute \enum_value_00000010000 "LOGICAL"
+  attribute \enum_value_00000100000 "BRANCH"
+  attribute \enum_value_00001000000 "CR"
+  attribute \enum_value_00010000000 "TRAP"
+  attribute \enum_value_00100000000 "MUL"
+  attribute \enum_value_01000000000 "DIV"
+  attribute \enum_value_10000000000 "SPR"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 \output_mul_op__fn_unit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 \output_mul_op__imm_data__imm
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_mul_op__imm_data__imm_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_mul_op__rc__rc
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_mul_op__rc__rc_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_mul_op__oe__oe
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_mul_op__oe__oe_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_mul_op__invert_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_mul_op__zero_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_mul_op__invert_out
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_mul_op__write_cr0
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_mul_op__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_mul_op__is_signed
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \output_mul_op__insn
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 64 \output_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 \output_o_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 4 \output_cr_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 2 \output_xer_ov
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 \output_xer_so
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
+  wire width 2 \output_muxid$37
+  attribute \enum_base_type "MicrOp"
+  attribute \enum_value_0000000 "OP_ILLEGAL"
+  attribute \enum_value_0000001 "OP_NOP"
+  attribute \enum_value_0000010 "OP_ADD"
+  attribute \enum_value_0000011 "OP_ADDPCIS"
+  attribute \enum_value_0000100 "OP_AND"
+  attribute \enum_value_0000101 "OP_ATTN"
+  attribute \enum_value_0000110 "OP_B"
+  attribute \enum_value_0000111 "OP_BC"
+  attribute \enum_value_0001000 "OP_BCREG"
+  attribute \enum_value_0001001 "OP_BPERM"
+  attribute \enum_value_0001010 "OP_CMP"
+  attribute \enum_value_0001011 "OP_CMPB"
+  attribute \enum_value_0001100 "OP_CMPEQB"
+  attribute \enum_value_0001101 "OP_CMPRB"
+  attribute \enum_value_0001110 "OP_CNTZ"
+  attribute \enum_value_0001111 "OP_CRAND"
+  attribute \enum_value_0010000 "OP_CRANDC"
+  attribute \enum_value_0010001 "OP_CREQV"
+  attribute \enum_value_0010010 "OP_CRNAND"
+  attribute \enum_value_0010011 "OP_CRNOR"
+  attribute \enum_value_0010100 "OP_CROR"
+  attribute \enum_value_0010101 "OP_CRORC"
+  attribute \enum_value_0010110 "OP_CRXOR"
+  attribute \enum_value_0010111 "OP_DARN"
+  attribute \enum_value_0011000 "OP_DCBF"
+  attribute \enum_value_0011001 "OP_DCBST"
+  attribute \enum_value_0011010 "OP_DCBT"
+  attribute \enum_value_0011011 "OP_DCBTST"
+  attribute \enum_value_0011100 "OP_DCBZ"
+  attribute \enum_value_0011101 "OP_DIV"
+  attribute \enum_value_0011110 "OP_DIVE"
+  attribute \enum_value_0011111 "OP_EXTS"
+  attribute \enum_value_0100000 "OP_EXTSWSLI"
+  attribute \enum_value_0100001 "OP_ICBI"
+  attribute \enum_value_0100010 "OP_ICBT"
+  attribute \enum_value_0100011 "OP_ISEL"
+  attribute \enum_value_0100100 "OP_ISYNC"
+  attribute \enum_value_0100101 "OP_LOAD"
+  attribute \enum_value_0100110 "OP_STORE"
+  attribute \enum_value_0100111 "OP_MADDHD"
+  attribute \enum_value_0101000 "OP_MADDHDU"
+  attribute \enum_value_0101001 "OP_MADDLD"
+  attribute \enum_value_0101010 "OP_MCRF"
+  attribute \enum_value_0101011 "OP_MCRXR"
+  attribute \enum_value_0101100 "OP_MCRXRX"
+  attribute \enum_value_0101101 "OP_MFCR"
+  attribute \enum_value_0101110 "OP_MFSPR"
+  attribute \enum_value_0101111 "OP_MOD"
+  attribute \enum_value_0110000 "OP_MTCRF"
+  attribute \enum_value_0110001 "OP_MTSPR"
+  attribute \enum_value_0110010 "OP_MUL_L64"
+  attribute \enum_value_0110011 "OP_MUL_H64"
+  attribute \enum_value_0110100 "OP_MUL_H32"
+  attribute \enum_value_0110101 "OP_OR"
+  attribute \enum_value_0110110 "OP_POPCNT"
+  attribute \enum_value_0110111 "OP_PRTY"
+  attribute \enum_value_0111000 "OP_RLC"
+  attribute \enum_value_0111001 "OP_RLCL"
+  attribute \enum_value_0111010 "OP_RLCR"
+  attribute \enum_value_0111011 "OP_SETB"
+  attribute \enum_value_0111100 "OP_SHL"
+  attribute \enum_value_0111101 "OP_SHR"
+  attribute \enum_value_0111110 "OP_SYNC"
+  attribute \enum_value_0111111 "OP_TRAP"
+  attribute \enum_value_1000011 "OP_XOR"
+  attribute \enum_value_1000100 "OP_SIM_CONFIG"
+  attribute \enum_value_1000101 "OP_CROP"
+  attribute \enum_value_1000110 "OP_RFID"
+  attribute \enum_value_1000111 "OP_MFMSR"
+  attribute \enum_value_1001000 "OP_MTMSRD"
+  attribute \enum_value_1001001 "OP_SC"
+  attribute \enum_value_1001010 "OP_MTMSR"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 \output_mul_op__insn_type$38
+  attribute \enum_base_type "Function"
+  attribute \enum_value_00000000000 "NONE"
+  attribute \enum_value_00000000010 "ALU"
+  attribute \enum_value_00000000100 "LDST"
+  attribute \enum_value_00000001000 "SHIFT_ROT"
+  attribute \enum_value_00000010000 "LOGICAL"
+  attribute \enum_value_00000100000 "BRANCH"
+  attribute \enum_value_00001000000 "CR"
+  attribute \enum_value_00010000000 "TRAP"
+  attribute \enum_value_00100000000 "MUL"
+  attribute \enum_value_01000000000 "DIV"
+  attribute \enum_value_10000000000 "SPR"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 \output_mul_op__fn_unit$39
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 \output_mul_op__imm_data__imm$40
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_mul_op__imm_data__imm_ok$41
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_mul_op__rc__rc$42
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_mul_op__rc__rc_ok$43
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_mul_op__oe__oe$44
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_mul_op__oe__oe_ok$45
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_mul_op__invert_a$46
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_mul_op__zero_a$47
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_mul_op__invert_out$48
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_mul_op__write_cr0$49
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_mul_op__is_32bit$50
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_mul_op__is_signed$51
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \output_mul_op__insn$52
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 64 \output_o$53
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 \output_o_ok$54
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 4 \output_cr_a$55
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 \output_cr_a_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 2 \output_xer_ov$56
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 \output_xer_ov_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 \output_xer_so$57
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 \output_xer_so_ok
+  cell \output$96 \output
+    connect \muxid \output_muxid
+    connect \mul_op__insn_type \output_mul_op__insn_type
+    connect \mul_op__fn_unit \output_mul_op__fn_unit
+    connect \mul_op__imm_data__imm \output_mul_op__imm_data__imm
+    connect \mul_op__imm_data__imm_ok \output_mul_op__imm_data__imm_ok
+    connect \mul_op__rc__rc \output_mul_op__rc__rc
+    connect \mul_op__rc__rc_ok \output_mul_op__rc__rc_ok
+    connect \mul_op__oe__oe \output_mul_op__oe__oe
+    connect \mul_op__oe__oe_ok \output_mul_op__oe__oe_ok
+    connect \mul_op__invert_a \output_mul_op__invert_a
+    connect \mul_op__zero_a \output_mul_op__zero_a
+    connect \mul_op__invert_out \output_mul_op__invert_out
+    connect \mul_op__write_cr0 \output_mul_op__write_cr0
+    connect \mul_op__is_32bit \output_mul_op__is_32bit
+    connect \mul_op__is_signed \output_mul_op__is_signed
+    connect \mul_op__insn \output_mul_op__insn
+    connect \o \output_o
+    connect \o_ok \output_o_ok
+    connect \cr_a \output_cr_a
+    connect \xer_ov \output_xer_ov
+    connect \xer_so \output_xer_so
+    connect \muxid$1 \output_muxid$37
+    connect \mul_op__insn_type$2 \output_mul_op__insn_type$38
+    connect \mul_op__fn_unit$3 \output_mul_op__fn_unit$39
+    connect \mul_op__imm_data__imm$4 \output_mul_op__imm_data__imm$40
+    connect \mul_op__imm_data__imm_ok$5 \output_mul_op__imm_data__imm_ok$41
+    connect \mul_op__rc__rc$6 \output_mul_op__rc__rc$42
+    connect \mul_op__rc__rc_ok$7 \output_mul_op__rc__rc_ok$43
+    connect \mul_op__oe__oe$8 \output_mul_op__oe__oe$44
+    connect \mul_op__oe__oe_ok$9 \output_mul_op__oe__oe_ok$45
+    connect \mul_op__invert_a$10 \output_mul_op__invert_a$46
+    connect \mul_op__zero_a$11 \output_mul_op__zero_a$47
+    connect \mul_op__invert_out$12 \output_mul_op__invert_out$48
+    connect \mul_op__write_cr0$13 \output_mul_op__write_cr0$49
+    connect \mul_op__is_32bit$14 \output_mul_op__is_32bit$50
+    connect \mul_op__is_signed$15 \output_mul_op__is_signed$51
+    connect \mul_op__insn$16 \output_mul_op__insn$52
+    connect \o$17 \output_o$53
+    connect \o_ok$18 \output_o_ok$54
+    connect \cr_a$19 \output_cr_a$55
+    connect \cr_a_ok \output_cr_a_ok
+    connect \xer_ov$20 \output_xer_ov$56
+    connect \xer_ov_ok \output_xer_ov_ok
+    connect \xer_so$21 \output_xer_so$57
+    connect \xer_so_ok \output_xer_so_ok
   end
   process $group_0
-    assign \all_rd 1'0
-    assign \all_rd $10
+    assign \mul3_muxid 2'00
+    assign \mul3_muxid \muxid
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:191"
-  wire width 1 \all_rd_dly
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:191"
-  wire width 1 \all_rd_dly$next
   process $group_1
-    assign \all_rd_dly$next \all_rd_dly
-    assign \all_rd_dly$next \all_rd
-    sync init
-      update \all_rd_dly 1'0
-    sync posedge \clk
-      update \all_rd_dly \all_rd_dly$next
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:192"
-  wire width 1 \all_rd_pulse
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:194"
-  wire width 1 $12
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:194"
-  cell $not $13
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \all_rd_dly
-    connect \Y $12
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:194"
-  wire width 1 $14
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:194"
-  cell $and $15
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \all_rd
-    connect \B $12
-    connect \Y $14
-  end
-  process $group_2
-    assign \all_rd_pulse 1'0
-    assign \all_rd_pulse $14
+    assign \mul3_mul_op__insn_type 7'0000000
+    assign \mul3_mul_op__fn_unit 11'00000000000
+    assign \mul3_mul_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \mul3_mul_op__imm_data__imm_ok 1'0
+    assign \mul3_mul_op__rc__rc 1'0
+    assign \mul3_mul_op__rc__rc_ok 1'0
+    assign \mul3_mul_op__oe__oe 1'0
+    assign \mul3_mul_op__oe__oe_ok 1'0
+    assign \mul3_mul_op__invert_a 1'0
+    assign \mul3_mul_op__zero_a 1'0
+    assign \mul3_mul_op__invert_out 1'0
+    assign \mul3_mul_op__write_cr0 1'0
+    assign \mul3_mul_op__is_32bit 1'0
+    assign \mul3_mul_op__is_signed 1'0
+    assign \mul3_mul_op__insn 32'00000000000000000000000000000000
+    assign { \mul3_mul_op__insn \mul3_mul_op__is_signed \mul3_mul_op__is_32bit \mul3_mul_op__write_cr0 \mul3_mul_op__invert_out \mul3_mul_op__zero_a \mul3_mul_op__invert_a { \mul3_mul_op__oe__oe_ok \mul3_mul_op__oe__oe } { \mul3_mul_op__rc__rc_ok \mul3_mul_op__rc__rc } { \mul3_mul_op__imm_data__imm_ok \mul3_mul_op__imm_data__imm } \mul3_mul_op__fn_unit \mul3_mul_op__insn_type } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__invert_out \mul_op__zero_a \mul_op__invert_a { \mul_op__oe__oe_ok \mul_op__oe__oe } { \mul_op__rc__rc_ok \mul_op__rc__rc } { \mul_op__imm_data__imm_ok \mul_op__imm_data__imm } \mul_op__fn_unit \mul_op__insn_type }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:197"
-  wire width 1 \alu_done
-  process $group_3
-    assign \alu_done 1'0
-    assign \alu_done \alu_shift_rot0_n_valid_o
+  process $group_16
+    assign \mul3_o 129'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
+    assign \mul3_o \o
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198"
-  wire width 1 \alu_done_dly
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198"
-  wire width 1 \alu_done_dly$next
-  process $group_4
-    assign \alu_done_dly$next \alu_done_dly
-    assign \alu_done_dly$next \alu_done
+  process $group_17
+    assign \mul3_xer_so 1'0
+    assign \mul3_xer_so \xer_so
     sync init
-      update \alu_done_dly 1'0
-    sync posedge \clk
-      update \alu_done_dly \alu_done_dly$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:199"
-  wire width 1 \alu_pulse
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:203"
-  wire width 1 $16
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:203"
-  cell $not $17
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \alu_done_dly
-    connect \Y $16
+  process $group_18
+    assign \mul3_neg_res 1'0
+    assign \mul3_neg_res \neg_res
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:203"
-  wire width 1 $18
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:203"
-  cell $and $19
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \alu_done
-    connect \B $16
-    connect \Y $18
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24"
+  wire width 1 \neg_res32$58
+  process $group_19
+    assign \neg_res32$58 1'0
+    assign \neg_res32$58 \neg_res32
+    sync init
   end
-  process $group_5
-    assign \alu_pulse 1'0
-    assign \alu_pulse $18
+  process $group_20
+    assign \output_muxid 2'00
+    assign \output_muxid \mul3_muxid$19
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:200"
-  wire width 3 \alu_pulsem
-  process $group_6
-    assign \alu_pulsem 3'000
-    assign \alu_pulsem { \alu_pulse \alu_pulse \alu_pulse }
+  process $group_21
+    assign \output_mul_op__insn_type 7'0000000
+    assign \output_mul_op__fn_unit 11'00000000000
+    assign \output_mul_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \output_mul_op__imm_data__imm_ok 1'0
+    assign \output_mul_op__rc__rc 1'0
+    assign \output_mul_op__rc__rc_ok 1'0
+    assign \output_mul_op__oe__oe 1'0
+    assign \output_mul_op__oe__oe_ok 1'0
+    assign \output_mul_op__invert_a 1'0
+    assign \output_mul_op__zero_a 1'0
+    assign \output_mul_op__invert_out 1'0
+    assign \output_mul_op__write_cr0 1'0
+    assign \output_mul_op__is_32bit 1'0
+    assign \output_mul_op__is_signed 1'0
+    assign \output_mul_op__insn 32'00000000000000000000000000000000
+    assign { \output_mul_op__insn \output_mul_op__is_signed \output_mul_op__is_32bit \output_mul_op__write_cr0 \output_mul_op__invert_out \output_mul_op__zero_a \output_mul_op__invert_a { \output_mul_op__oe__oe_ok \output_mul_op__oe__oe } { \output_mul_op__rc__rc_ok \output_mul_op__rc__rc } { \output_mul_op__imm_data__imm_ok \output_mul_op__imm_data__imm } \output_mul_op__fn_unit \output_mul_op__insn_type } { \mul3_mul_op__insn$34 \mul3_mul_op__is_signed$33 \mul3_mul_op__is_32bit$32 \mul3_mul_op__write_cr0$31 \mul3_mul_op__invert_out$30 \mul3_mul_op__zero_a$29 \mul3_mul_op__invert_a$28 { \mul3_mul_op__oe__oe_ok$27 \mul3_mul_op__oe__oe$26 } { \mul3_mul_op__rc__rc_ok$25 \mul3_mul_op__rc__rc$24 } { \mul3_mul_op__imm_data__imm_ok$23 \mul3_mul_op__imm_data__imm$22 } \mul3_mul_op__fn_unit$21 \mul3_mul_op__insn_type$20 }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:207"
-  wire width 3 \prev_wr_go
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:207"
-  wire width 3 \prev_wr_go$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
-  wire width 3 $20
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
-  cell $and $21
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 3
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 3
-    parameter \Y_WIDTH 3
-    connect \A \cu_wr__go_i
-    connect \B { \cu_busy_o \cu_busy_o \cu_busy_o }
-    connect \Y $20
+  process $group_36
+    assign \output_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \output_o_ok 1'0
+    assign { \output_o_ok \output_o } { \mul3_o_ok \mul3_o$35 }
+    sync init
   end
-  process $group_7
-    assign \prev_wr_go$next \prev_wr_go
-    assign \prev_wr_go$next $20
-    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
-      case 1'1
-        assign \prev_wr_go$next 3'000
-    end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 \cr_a_ok$59
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 4 \cr_a$60
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 \cr_a_ok$61
+  process $group_38
+    assign \output_cr_a 4'0000
+    assign \cr_a_ok$59 1'0
+    assign { \cr_a_ok$59 \output_cr_a } { \cr_a_ok$61 \cr_a$60 }
     sync init
-      update \prev_wr_go 3'000
-    sync posedge \clk
-      update \prev_wr_go \prev_wr_go$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107"
-  wire width 1 \cu_done_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
-  wire width 1 $22
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
-  wire width 1 $23
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
-  wire width 3 $24
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96"
-  wire width 3 \cu_wrmask_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
-  cell $not $25
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 3
-    parameter \Y_WIDTH 3
-    connect \A \cu_wrmask_o
-    connect \Y $24
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 \xer_ov_ok$62
+  process $group_40
+    assign \output_xer_ov 2'00
+    assign \xer_ov_ok$62 1'0
+    assign { \xer_ov_ok$62 \output_xer_ov } { \mul3_xer_ov_ok \mul3_xer_ov }
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
-  wire width 3 $26
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
-  cell $and $27
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 3
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 3
-    parameter \Y_WIDTH 3
-    connect \A \cu_wr__rel_o
-    connect \B $24
-    connect \Y $26
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 \xer_so_ok$63
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 \xer_so_ok$64
+  process $group_42
+    assign \output_xer_so 1'0
+    assign \xer_so_ok$63 1'0
+    assign { \xer_so_ok$63 \output_xer_so } { \xer_so_ok$64 \mul3_xer_so$36 }
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
-  cell $reduce_bool $28
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 3
-    parameter \Y_WIDTH 1
-    connect \A $26
-    connect \Y $23
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621"
+  wire width 1 \p_valid_i$65
+  process $group_44
+    assign \p_valid_i$65 1'0
+    assign \p_valid_i$65 \p_valid_i
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
-  cell $not $29
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A $23
-    connect \Y $22
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619"
+  wire width 1 \n_i_rdy_data
+  process $group_45
+    assign \n_i_rdy_data 1'0
+    assign \n_i_rdy_data \n_ready_i
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
-  wire width 1 $30
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
-  cell $and $31
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620"
+  wire width 1 \p_valid_i_p_ready_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624"
+  wire width 1 $66
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624"
+  cell $and $67
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \cu_busy_o
-    connect \B $22
-    connect \Y $30
+    connect \A \p_valid_i$65
+    connect \B \p_ready_o
+    connect \Y $66
   end
-  process $group_8
-    assign \cu_done_o 1'0
-    assign \cu_done_o $30
+  process $group_46
+    assign \p_valid_i_p_ready_o 1'0
+    assign \p_valid_i_p_ready_o $66
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214"
-  wire width 1 \wr_any
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:218"
-  wire width 1 $32
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:218"
-  cell $reduce_bool $33
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 3
-    parameter \Y_WIDTH 1
-    connect \A \cu_wr__go_i
-    connect \Y $32
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:218"
-  wire width 1 $34
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:218"
-  cell $reduce_bool $35
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 3
-    parameter \Y_WIDTH 1
-    connect \A \prev_wr_go
-    connect \Y $34
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
+  wire width 2 \muxid$68
+  process $group_47
+    assign \muxid$68 2'00
+    assign \muxid$68 \output_muxid$37
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:218"
-  wire width 1 $36
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:218"
-  cell $or $37
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A $32
-    connect \B $34
-    connect \Y $36
+  attribute \enum_base_type "MicrOp"
+  attribute \enum_value_0000000 "OP_ILLEGAL"
+  attribute \enum_value_0000001 "OP_NOP"
+  attribute \enum_value_0000010 "OP_ADD"
+  attribute \enum_value_0000011 "OP_ADDPCIS"
+  attribute \enum_value_0000100 "OP_AND"
+  attribute \enum_value_0000101 "OP_ATTN"
+  attribute \enum_value_0000110 "OP_B"
+  attribute \enum_value_0000111 "OP_BC"
+  attribute \enum_value_0001000 "OP_BCREG"
+  attribute \enum_value_0001001 "OP_BPERM"
+  attribute \enum_value_0001010 "OP_CMP"
+  attribute \enum_value_0001011 "OP_CMPB"
+  attribute \enum_value_0001100 "OP_CMPEQB"
+  attribute \enum_value_0001101 "OP_CMPRB"
+  attribute \enum_value_0001110 "OP_CNTZ"
+  attribute \enum_value_0001111 "OP_CRAND"
+  attribute \enum_value_0010000 "OP_CRANDC"
+  attribute \enum_value_0010001 "OP_CREQV"
+  attribute \enum_value_0010010 "OP_CRNAND"
+  attribute \enum_value_0010011 "OP_CRNOR"
+  attribute \enum_value_0010100 "OP_CROR"
+  attribute \enum_value_0010101 "OP_CRORC"
+  attribute \enum_value_0010110 "OP_CRXOR"
+  attribute \enum_value_0010111 "OP_DARN"
+  attribute \enum_value_0011000 "OP_DCBF"
+  attribute \enum_value_0011001 "OP_DCBST"
+  attribute \enum_value_0011010 "OP_DCBT"
+  attribute \enum_value_0011011 "OP_DCBTST"
+  attribute \enum_value_0011100 "OP_DCBZ"
+  attribute \enum_value_0011101 "OP_DIV"
+  attribute \enum_value_0011110 "OP_DIVE"
+  attribute \enum_value_0011111 "OP_EXTS"
+  attribute \enum_value_0100000 "OP_EXTSWSLI"
+  attribute \enum_value_0100001 "OP_ICBI"
+  attribute \enum_value_0100010 "OP_ICBT"
+  attribute \enum_value_0100011 "OP_ISEL"
+  attribute \enum_value_0100100 "OP_ISYNC"
+  attribute \enum_value_0100101 "OP_LOAD"
+  attribute \enum_value_0100110 "OP_STORE"
+  attribute \enum_value_0100111 "OP_MADDHD"
+  attribute \enum_value_0101000 "OP_MADDHDU"
+  attribute \enum_value_0101001 "OP_MADDLD"
+  attribute \enum_value_0101010 "OP_MCRF"
+  attribute \enum_value_0101011 "OP_MCRXR"
+  attribute \enum_value_0101100 "OP_MCRXRX"
+  attribute \enum_value_0101101 "OP_MFCR"
+  attribute \enum_value_0101110 "OP_MFSPR"
+  attribute \enum_value_0101111 "OP_MOD"
+  attribute \enum_value_0110000 "OP_MTCRF"
+  attribute \enum_value_0110001 "OP_MTSPR"
+  attribute \enum_value_0110010 "OP_MUL_L64"
+  attribute \enum_value_0110011 "OP_MUL_H64"
+  attribute \enum_value_0110100 "OP_MUL_H32"
+  attribute \enum_value_0110101 "OP_OR"
+  attribute \enum_value_0110110 "OP_POPCNT"
+  attribute \enum_value_0110111 "OP_PRTY"
+  attribute \enum_value_0111000 "OP_RLC"
+  attribute \enum_value_0111001 "OP_RLCL"
+  attribute \enum_value_0111010 "OP_RLCR"
+  attribute \enum_value_0111011 "OP_SETB"
+  attribute \enum_value_0111100 "OP_SHL"
+  attribute \enum_value_0111101 "OP_SHR"
+  attribute \enum_value_0111110 "OP_SYNC"
+  attribute \enum_value_0111111 "OP_TRAP"
+  attribute \enum_value_1000011 "OP_XOR"
+  attribute \enum_value_1000100 "OP_SIM_CONFIG"
+  attribute \enum_value_1000101 "OP_CROP"
+  attribute \enum_value_1000110 "OP_RFID"
+  attribute \enum_value_1000111 "OP_MFMSR"
+  attribute \enum_value_1001000 "OP_MTMSRD"
+  attribute \enum_value_1001001 "OP_SC"
+  attribute \enum_value_1001010 "OP_MTMSR"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 \mul_op__insn_type$69
+  attribute \enum_base_type "Function"
+  attribute \enum_value_00000000000 "NONE"
+  attribute \enum_value_00000000010 "ALU"
+  attribute \enum_value_00000000100 "LDST"
+  attribute \enum_value_00000001000 "SHIFT_ROT"
+  attribute \enum_value_00000010000 "LOGICAL"
+  attribute \enum_value_00000100000 "BRANCH"
+  attribute \enum_value_00001000000 "CR"
+  attribute \enum_value_00010000000 "TRAP"
+  attribute \enum_value_00100000000 "MUL"
+  attribute \enum_value_01000000000 "DIV"
+  attribute \enum_value_10000000000 "SPR"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 \mul_op__fn_unit$70
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 \mul_op__imm_data__imm$71
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_op__imm_data__imm_ok$72
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_op__rc__rc$73
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_op__rc__rc_ok$74
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_op__oe__oe$75
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_op__oe__oe_ok$76
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_op__invert_a$77
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_op__zero_a$78
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_op__invert_out$79
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_op__write_cr0$80
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_op__is_32bit$81
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_op__is_signed$82
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \mul_op__insn$83
+  process $group_48
+    assign \mul_op__insn_type$69 7'0000000
+    assign \mul_op__fn_unit$70 11'00000000000
+    assign \mul_op__imm_data__imm$71 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \mul_op__imm_data__imm_ok$72 1'0
+    assign \mul_op__rc__rc$73 1'0
+    assign \mul_op__rc__rc_ok$74 1'0
+    assign \mul_op__oe__oe$75 1'0
+    assign \mul_op__oe__oe_ok$76 1'0
+    assign \mul_op__invert_a$77 1'0
+    assign \mul_op__zero_a$78 1'0
+    assign \mul_op__invert_out$79 1'0
+    assign \mul_op__write_cr0$80 1'0
+    assign \mul_op__is_32bit$81 1'0
+    assign \mul_op__is_signed$82 1'0
+    assign \mul_op__insn$83 32'00000000000000000000000000000000
+    assign { \mul_op__insn$83 \mul_op__is_signed$82 \mul_op__is_32bit$81 \mul_op__write_cr0$80 \mul_op__invert_out$79 \mul_op__zero_a$78 \mul_op__invert_a$77 { \mul_op__oe__oe_ok$76 \mul_op__oe__oe$75 } { \mul_op__rc__rc_ok$74 \mul_op__rc__rc$73 } { \mul_op__imm_data__imm_ok$72 \mul_op__imm_data__imm$71 } \mul_op__fn_unit$70 \mul_op__insn_type$69 } { \output_mul_op__insn$52 \output_mul_op__is_signed$51 \output_mul_op__is_32bit$50 \output_mul_op__write_cr0$49 \output_mul_op__invert_out$48 \output_mul_op__zero_a$47 \output_mul_op__invert_a$46 { \output_mul_op__oe__oe_ok$45 \output_mul_op__oe__oe$44 } { \output_mul_op__rc__rc_ok$43 \output_mul_op__rc__rc$42 } { \output_mul_op__imm_data__imm_ok$41 \output_mul_op__imm_data__imm$40 } \output_mul_op__fn_unit$39 \output_mul_op__insn_type$38 }
+    sync init
   end
-  process $group_9
-    assign \wr_any 1'0
-    assign \wr_any $36
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 64 \o$84
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 \o_ok$85
+  process $group_63
+    assign \o$84 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \o_ok$85 1'0
+    assign { \o_ok$85 \o$84 } { \output_o_ok$54 \output_o$53 }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215"
-  wire width 1 \req_done
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:219"
-  wire width 1 $38
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:219"
-  cell $not $39
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \alu_shift_rot0_n_ready_i
-    connect \Y $38
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 4 \cr_a$86
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 \cr_a_ok$87
+  process $group_65
+    assign \cr_a$86 4'0000
+    assign \cr_a_ok$87 1'0
+    assign { \cr_a_ok$87 \cr_a$86 } { \output_cr_a_ok \output_cr_a$55 }
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:219"
-  wire width 1 $40
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:219"
-  cell $and $41
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \wr_any
-    connect \B $38
-    connect \Y $40
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 2 \xer_ov$88
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 \xer_ov_ok$89
+  process $group_67
+    assign \xer_ov$88 2'00
+    assign \xer_ov_ok$89 1'0
+    assign { \xer_ov_ok$89 \xer_ov$88 } { \output_xer_ov_ok \output_xer_ov$56 }
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:220"
-  wire width 3 $42
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:220"
-  cell $and $43
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 3
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 3
-    parameter \Y_WIDTH 3
-    connect \A \req_l_q_req
-    connect \B \cu_wrmask_o
-    connect \Y $42
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 \xer_so$90
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 \xer_so_ok$91
+  process $group_69
+    assign \xer_so$90 1'0
+    assign \xer_so_ok$91 1'0
+    assign { \xer_so_ok$91 \xer_so$90 } { \output_xer_so_ok \output_xer_so$57 }
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:220"
-  wire width 1 $44
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:220"
-  cell $eq $45
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 3
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A $42
-    connect \B 1'0
-    connect \Y $44
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:220"
-  wire width 1 $46
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:220"
-  cell $and $47
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A $40
-    connect \B $44
-    connect \Y $46
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
-  wire width 1 $48
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
-  cell $eq $49
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 3
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \cu_wrmask_o
-    connect \B 1'0
-    connect \Y $48
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
-  wire width 1 $50
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
-  cell $and $51
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A $48
-    connect \B \alu_shift_rot0_n_ready_i
-    connect \Y $50
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
-  wire width 1 $52
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
-  cell $and $53
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A $50
-    connect \B \alu_shift_rot0_n_valid_o
-    connect \Y $52
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
-  wire width 1 $54
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
-  cell $and $55
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A $52
-    connect \B \cu_busy_o
-    connect \Y $54
-  end
-  process $group_10
-    assign \req_done 1'0
-    assign \req_done $46
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
-    switch { $54 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615"
+  wire width 1 \r_busy
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615"
+  wire width 1 \r_busy$next
+  process $group_71
+    assign \r_busy$next \r_busy
+    attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+    switch { \n_i_rdy_data \p_valid_i_p_ready_o }
+      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+      case 2'-1
+        assign \r_busy$next 1'1
+      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
+      case 2'1-
+        assign \r_busy$next 1'0
+    end
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
       case 1'1
-        assign \req_done 1'1
+        assign \r_busy$next 1'0
     end
     sync init
+      update \r_busy 1'0
+    sync posedge \coresync_clk
+      update \r_busy \r_busy$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:229"
-  wire width 1 \reset
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:103"
-  wire width 1 \cu_go_die_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233"
-  wire width 1 $56
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233"
-  cell $or $57
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \req_done
-    connect \B \cu_go_die_i
-    connect \Y $56
-  end
-  process $group_11
-    assign \reset 1'0
-    assign \reset $56
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230"
-  wire width 1 \rst_r
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:234"
-  wire width 1 $58
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:234"
-  cell $or $59
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \cu_issue_i
-    connect \B \cu_go_die_i
-    connect \Y $58
-  end
-  process $group_12
-    assign \rst_r 1'0
-    assign \rst_r $58
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231"
-  wire width 3 \reset_w
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:235"
-  wire width 3 $60
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:235"
-  cell $or $61
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 3
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 3
-    parameter \Y_WIDTH 3
-    connect \A \cu_wr__go_i
-    connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i }
-    connect \Y $60
-  end
-  process $group_13
-    assign \reset_w 3'000
-    assign \reset_w $60
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232"
-  wire width 4 \reset_r
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:236"
-  wire width 4 $62
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:236"
-  cell $or $63
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 4
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 4
-    parameter \Y_WIDTH 4
-    connect \A \cu_rd__go_i
-    connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i }
-    connect \Y $62
-  end
-  process $group_14
-    assign \reset_r 4'0000
-    assign \reset_r $62
-    sync init
-  end
-  process $group_15
-    assign \rok_l_s_rdok 1'0
-    assign \rok_l_s_rdok \cu_issue_i
+  process $group_72
+    assign \muxid$1$next \muxid$1
+    attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+    switch { \n_i_rdy_data \p_valid_i_p_ready_o }
+      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+      case 2'-1
+        assign \muxid$1$next \muxid$68
+      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
+      case 2'1-
+        assign \muxid$1$next \muxid$68
+    end
     sync init
+      update \muxid$1 2'00
+    sync posedge \coresync_clk
+      update \muxid$1 \muxid$1$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:240"
-  wire width 1 $64
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:240"
-  cell $and $65
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \alu_shift_rot0_n_valid_o
-    connect \B \cu_busy_o
-    connect \Y $64
-  end
-  process $group_16
-    assign \rok_l_r_rdok$next \rok_l_r_rdok
-    assign \rok_l_r_rdok$next $64
+  process $group_73
+    assign \mul_op__insn_type$2$next \mul_op__insn_type$2
+    assign \mul_op__fn_unit$3$next \mul_op__fn_unit$3
+    assign \mul_op__imm_data__imm$4$next \mul_op__imm_data__imm$4
+    assign \mul_op__imm_data__imm_ok$5$next \mul_op__imm_data__imm_ok$5
+    assign \mul_op__rc__rc$6$next \mul_op__rc__rc$6
+    assign \mul_op__rc__rc_ok$7$next \mul_op__rc__rc_ok$7
+    assign \mul_op__oe__oe$8$next \mul_op__oe__oe$8
+    assign \mul_op__oe__oe_ok$9$next \mul_op__oe__oe_ok$9
+    assign \mul_op__invert_a$10$next \mul_op__invert_a$10
+    assign \mul_op__zero_a$11$next \mul_op__zero_a$11
+    assign \mul_op__invert_out$12$next \mul_op__invert_out$12
+    assign \mul_op__write_cr0$13$next \mul_op__write_cr0$13
+    assign \mul_op__is_32bit$14$next \mul_op__is_32bit$14
+    assign \mul_op__is_signed$15$next \mul_op__is_signed$15
+    assign \mul_op__insn$16$next \mul_op__insn$16
+    attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+    switch { \n_i_rdy_data \p_valid_i_p_ready_o }
+      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+      case 2'-1
+        assign { \mul_op__insn$16$next \mul_op__is_signed$15$next \mul_op__is_32bit$14$next \mul_op__write_cr0$13$next \mul_op__invert_out$12$next \mul_op__zero_a$11$next \mul_op__invert_a$10$next { \mul_op__oe__oe_ok$9$next \mul_op__oe__oe$8$next } { \mul_op__rc__rc_ok$7$next \mul_op__rc__rc$6$next } { \mul_op__imm_data__imm_ok$5$next \mul_op__imm_data__imm$4$next } \mul_op__fn_unit$3$next \mul_op__insn_type$2$next } { \mul_op__insn$83 \mul_op__is_signed$82 \mul_op__is_32bit$81 \mul_op__write_cr0$80 \mul_op__invert_out$79 \mul_op__zero_a$78 \mul_op__invert_a$77 { \mul_op__oe__oe_ok$76 \mul_op__oe__oe$75 } { \mul_op__rc__rc_ok$74 \mul_op__rc__rc$73 } { \mul_op__imm_data__imm_ok$72 \mul_op__imm_data__imm$71 } \mul_op__fn_unit$70 \mul_op__insn_type$69 }
+      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
+      case 2'1-
+        assign { \mul_op__insn$16$next \mul_op__is_signed$15$next \mul_op__is_32bit$14$next \mul_op__write_cr0$13$next \mul_op__invert_out$12$next \mul_op__zero_a$11$next \mul_op__invert_a$10$next { \mul_op__oe__oe_ok$9$next \mul_op__oe__oe$8$next } { \mul_op__rc__rc_ok$7$next \mul_op__rc__rc$6$next } { \mul_op__imm_data__imm_ok$5$next \mul_op__imm_data__imm$4$next } \mul_op__fn_unit$3$next \mul_op__insn_type$2$next } { \mul_op__insn$83 \mul_op__is_signed$82 \mul_op__is_32bit$81 \mul_op__write_cr0$80 \mul_op__invert_out$79 \mul_op__zero_a$78 \mul_op__invert_a$77 { \mul_op__oe__oe_ok$76 \mul_op__oe__oe$75 } { \mul_op__rc__rc_ok$74 \mul_op__rc__rc$73 } { \mul_op__imm_data__imm_ok$72 \mul_op__imm_data__imm$71 } \mul_op__fn_unit$70 \mul_op__insn_type$69 }
+    end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
-        assign \rok_l_r_rdok$next 1'1
+        assign \mul_op__imm_data__imm$4$next 64'0000000000000000000000000000000000000000000000000000000000000000
+        assign \mul_op__imm_data__imm_ok$5$next 1'0
+        assign \mul_op__rc__rc$6$next 1'0
+        assign \mul_op__rc__rc_ok$7$next 1'0
+        assign \mul_op__oe__oe$8$next 1'0
+        assign \mul_op__oe__oe_ok$9$next 1'0
     end
     sync init
-      update \rok_l_r_rdok 1'1
-    sync posedge \clk
-      update \rok_l_r_rdok \rok_l_r_rdok$next
-  end
-  process $group_17
-    assign \rst_l_s_rst 1'0
-    assign \rst_l_s_rst \all_rd
-    sync init
-  end
-  process $group_18
-    assign \rst_l_r_rst 1'1
-    assign \rst_l_r_rst \rst_r
-    sync init
+      update \mul_op__insn_type$2 7'0000000
+      update \mul_op__fn_unit$3 11'00000000000
+      update \mul_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000
+      update \mul_op__imm_data__imm_ok$5 1'0
+      update \mul_op__rc__rc$6 1'0
+      update \mul_op__rc__rc_ok$7 1'0
+      update \mul_op__oe__oe$8 1'0
+      update \mul_op__oe__oe_ok$9 1'0
+      update \mul_op__invert_a$10 1'0
+      update \mul_op__zero_a$11 1'0
+      update \mul_op__invert_out$12 1'0
+      update \mul_op__write_cr0$13 1'0
+      update \mul_op__is_32bit$14 1'0
+      update \mul_op__is_signed$15 1'0
+      update \mul_op__insn$16 32'00000000000000000000000000000000
+    sync posedge \coresync_clk
+      update \mul_op__insn_type$2 \mul_op__insn_type$2$next
+      update \mul_op__fn_unit$3 \mul_op__fn_unit$3$next
+      update \mul_op__imm_data__imm$4 \mul_op__imm_data__imm$4$next
+      update \mul_op__imm_data__imm_ok$5 \mul_op__imm_data__imm_ok$5$next
+      update \mul_op__rc__rc$6 \mul_op__rc__rc$6$next
+      update \mul_op__rc__rc_ok$7 \mul_op__rc__rc_ok$7$next
+      update \mul_op__oe__oe$8 \mul_op__oe__oe$8$next
+      update \mul_op__oe__oe_ok$9 \mul_op__oe__oe_ok$9$next
+      update \mul_op__invert_a$10 \mul_op__invert_a$10$next
+      update \mul_op__zero_a$11 \mul_op__zero_a$11$next
+      update \mul_op__invert_out$12 \mul_op__invert_out$12$next
+      update \mul_op__write_cr0$13 \mul_op__write_cr0$13$next
+      update \mul_op__is_32bit$14 \mul_op__is_32bit$14$next
+      update \mul_op__is_signed$15 \mul_op__is_signed$15$next
+      update \mul_op__insn$16 \mul_op__insn$16$next
   end
-  process $group_19
-    assign \opc_l_s_opc$next \opc_l_s_opc
-    assign \opc_l_s_opc$next \cu_issue_i
+  process $group_88
+    assign \o$17$next \o$17
+    assign \o_ok$next \o_ok
+    attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+    switch { \n_i_rdy_data \p_valid_i_p_ready_o }
+      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+      case 2'-1
+        assign { \o_ok$next \o$17$next } { \o_ok$85 \o$84 }
+      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
+      case 2'1-
+        assign { \o_ok$next \o$17$next } { \o_ok$85 \o$84 }
+    end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
-        assign \opc_l_s_opc$next 1'0
+        assign \o_ok$next 1'0
     end
     sync init
-      update \opc_l_s_opc 1'0
-    sync posedge \clk
-      update \opc_l_s_opc \opc_l_s_opc$next
+      update \o$17 64'0000000000000000000000000000000000000000000000000000000000000000
+      update \o_ok 1'0
+    sync posedge \coresync_clk
+      update \o$17 \o$17$next
+      update \o_ok \o_ok$next
   end
-  process $group_20
-    assign \opc_l_r_opc$next \opc_l_r_opc
-    assign \opc_l_r_opc$next \req_done
+  process $group_90
+    assign \cr_a$next \cr_a
+    assign \cr_a_ok$next \cr_a_ok
+    attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+    switch { \n_i_rdy_data \p_valid_i_p_ready_o }
+      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+      case 2'-1
+        assign { \cr_a_ok$next \cr_a$next } { \cr_a_ok$87 \cr_a$86 }
+      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
+      case 2'1-
+        assign { \cr_a_ok$next \cr_a$next } { \cr_a_ok$87 \cr_a$86 }
+    end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
-        assign \opc_l_r_opc$next 1'1
+        assign \cr_a_ok$next 1'0
     end
     sync init
-      update \opc_l_r_opc 1'1
-    sync posedge \clk
-      update \opc_l_r_opc \opc_l_r_opc$next
+      update \cr_a 4'0000
+      update \cr_a_ok 1'0
+    sync posedge \coresync_clk
+      update \cr_a \cr_a$next
+      update \cr_a_ok \cr_a_ok$next
   end
-  process $group_21
-    assign \src_l_s_src$next \src_l_s_src
-    assign \src_l_s_src$next { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i }
+  process $group_92
+    assign \xer_ov$next \xer_ov
+    assign \xer_ov_ok$next \xer_ov_ok
+    attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+    switch { \n_i_rdy_data \p_valid_i_p_ready_o }
+      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+      case 2'-1
+        assign { \xer_ov_ok$next \xer_ov$next } { \xer_ov_ok$89 \xer_ov$88 }
+      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
+      case 2'1-
+        assign { \xer_ov_ok$next \xer_ov$next } { \xer_ov_ok$89 \xer_ov$88 }
+    end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
-        assign \src_l_s_src$next 4'0000
+        assign \xer_ov_ok$next 1'0
     end
     sync init
-      update \src_l_s_src 4'0000
-    sync posedge \clk
-      update \src_l_s_src \src_l_s_src$next
+      update \xer_ov 2'00
+      update \xer_ov_ok 1'0
+    sync posedge \coresync_clk
+      update \xer_ov \xer_ov$next
+      update \xer_ov_ok \xer_ov_ok$next
   end
-  process $group_22
-    assign \src_l_r_src$next \src_l_r_src
-    assign \src_l_r_src$next \reset_r
+  process $group_94
+    assign \xer_so$18$next \xer_so$18
+    assign \xer_so_ok$next \xer_so_ok
+    attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+    switch { \n_i_rdy_data \p_valid_i_p_ready_o }
+      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+      case 2'-1
+        assign { \xer_so_ok$next \xer_so$18$next } { \xer_so_ok$91 \xer_so$90 }
+      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
+      case 2'1-
+        assign { \xer_so_ok$next \xer_so$18$next } { \xer_so_ok$91 \xer_so$90 }
+    end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
-        assign \src_l_r_src$next 4'1111
+        assign \xer_so_ok$next 1'0
     end
     sync init
-      update \src_l_r_src 4'1111
-    sync posedge \clk
-      update \src_l_r_src \src_l_r_src$next
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:255"
-  wire width 3 $66
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:255"
-  cell $and $67
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 3
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 3
-    parameter \Y_WIDTH 3
-    connect \A \alu_pulsem
-    connect \B \cu_wrmask_o
-    connect \Y $66
+      update \xer_so$18 1'0
+      update \xer_so_ok 1'0
+    sync posedge \coresync_clk
+      update \xer_so$18 \xer_so$18$next
+      update \xer_so_ok \xer_so_ok$next
   end
-  process $group_23
-    assign \req_l_s_req 3'000
-    assign \req_l_s_req $66
+  process $group_96
+    assign \n_valid_o 1'0
+    assign \n_valid_o \r_busy
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:256"
-  wire width 3 $68
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:256"
-  cell $or $69
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 3
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 3
-    parameter \Y_WIDTH 3
-    connect \A \reset_w
-    connect \B \prev_wr_go
-    connect \Y $68
-  end
-  process $group_24
-    assign \req_l_r_req 3'111
-    assign \req_l_r_req $68
+  process $group_97
+    assign \p_ready_o 1'0
+    assign \p_ready_o \n_i_rdy_data
     sync init
   end
+  connect \cr_a$60 4'0000
+  connect \cr_a_ok$61 1'0
+  connect \xer_so_ok$64 1'0
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0"
+module \alu_mul0
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 output 1 \o_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 output 2 \cr_a_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 output 3 \xer_ov_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 output 4 \xer_so_ok
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 5 \coresync_rst
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
+  wire width 1 output 6 \n_valid_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
+  wire width 1 input 7 \n_ready_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 64 output 8 \o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 4 output 9 \cr_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 2 output 10 \xer_ov
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 output 11 \xer_so
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
   attribute \enum_value_0000001 "OP_NOP"
@@ -106765,7 +107129,7 @@ module \shiftrot0
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 7 \oper_r__insn_type
+  wire width 7 input 12 \mul_op__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -106779,1361 +107143,1771 @@ module \shiftrot0
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 11 \oper_r__fn_unit
+  wire width 11 input 13 \mul_op__fn_unit
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 64 \oper_r__imm_data__imm
+  wire width 64 input 14 \mul_op__imm_data__imm
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \oper_r__imm_data__imm_ok
+  wire width 1 input 15 \mul_op__imm_data__imm_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \oper_r__rc__rc
+  wire width 1 input 16 \mul_op__rc__rc
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \oper_r__rc__rc_ok
+  wire width 1 input 17 \mul_op__rc__rc_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \oper_r__oe__oe
+  wire width 1 input 18 \mul_op__oe__oe
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \oper_r__oe__oe_ok
-  attribute \enum_base_type "CryIn"
-  attribute \enum_value_00 "ZERO"
-  attribute \enum_value_01 "ONE"
-  attribute \enum_value_10 "CA"
+  wire width 1 input 19 \mul_op__oe__oe_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 2 \oper_r__input_carry
+  wire width 1 input 20 \mul_op__invert_a
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \oper_r__output_carry
+  wire width 1 input 21 \mul_op__zero_a
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \oper_r__input_cr
+  wire width 1 input 22 \mul_op__invert_out
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \oper_r__output_cr
+  wire width 1 input 23 \mul_op__write_cr0
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \oper_r__is_32bit
+  wire width 1 input 24 \mul_op__is_32bit
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \oper_r__is_signed
+  wire width 1 input 25 \mul_op__is_signed
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 32 \oper_r__insn
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
-  wire width 7 \oper_l__insn_type
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
-  wire width 7 \oper_l__insn_type$next
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
-  wire width 11 \oper_l__fn_unit
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
-  wire width 11 \oper_l__fn_unit$next
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
-  wire width 64 \oper_l__imm_data__imm
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
-  wire width 64 \oper_l__imm_data__imm$next
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
-  wire width 1 \oper_l__imm_data__imm_ok
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
-  wire width 1 \oper_l__imm_data__imm_ok$next
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
-  wire width 1 \oper_l__rc__rc
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
-  wire width 1 \oper_l__rc__rc$next
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
-  wire width 1 \oper_l__rc__rc_ok
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
-  wire width 1 \oper_l__rc__rc_ok$next
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
-  wire width 1 \oper_l__oe__oe
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
-  wire width 1 \oper_l__oe__oe$next
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
-  wire width 1 \oper_l__oe__oe_ok
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
-  wire width 1 \oper_l__oe__oe_ok$next
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
-  wire width 2 \oper_l__input_carry
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
-  wire width 2 \oper_l__input_carry$next
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
-  wire width 1 \oper_l__output_carry
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
-  wire width 1 \oper_l__output_carry$next
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
-  wire width 1 \oper_l__input_cr
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
-  wire width 1 \oper_l__input_cr$next
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
-  wire width 1 \oper_l__output_cr
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
-  wire width 1 \oper_l__output_cr$next
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
-  wire width 1 \oper_l__is_32bit
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
-  wire width 1 \oper_l__is_32bit$next
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
-  wire width 1 \oper_l__is_signed
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
-  wire width 1 \oper_l__is_signed$next
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
-  wire width 32 \oper_l__insn
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
-  wire width 32 \oper_l__insn$next
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
-  wire width 126 $70
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
-  cell $mux $71
-    parameter \WIDTH 126
-    connect \A { \oper_l__insn \oper_l__is_signed \oper_l__is_32bit \oper_l__output_cr \oper_l__input_cr \oper_l__output_carry \oper_l__input_carry { } { \oper_l__oe__oe_ok \oper_l__oe__oe } { \oper_l__rc__rc_ok \oper_l__rc__rc } { \oper_l__imm_data__imm_ok \oper_l__imm_data__imm } \oper_l__fn_unit \oper_l__insn_type }
-    connect \B { \oper_i_alu_shift_rot0__insn \oper_i_alu_shift_rot0__is_signed \oper_i_alu_shift_rot0__is_32bit \oper_i_alu_shift_rot0__output_cr \oper_i_alu_shift_rot0__input_cr \oper_i_alu_shift_rot0__output_carry \oper_i_alu_shift_rot0__input_carry { } { \oper_i_alu_shift_rot0__oe__oe_ok \oper_i_alu_shift_rot0__oe__oe } { \oper_i_alu_shift_rot0__rc__rc_ok \oper_i_alu_shift_rot0__rc__rc } { \oper_i_alu_shift_rot0__imm_data__imm_ok \oper_i_alu_shift_rot0__imm_data__imm } \oper_i_alu_shift_rot0__fn_unit \oper_i_alu_shift_rot0__insn_type }
-    connect \S \cu_issue_i
-    connect \Y $70
-  end
-  process $group_25
-    assign \oper_r__insn_type 7'0000000
-    assign \oper_r__fn_unit 11'00000000000
-    assign \oper_r__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \oper_r__imm_data__imm_ok 1'0
-    assign \oper_r__rc__rc 1'0
-    assign \oper_r__rc__rc_ok 1'0
-    assign \oper_r__oe__oe 1'0
-    assign \oper_r__oe__oe_ok 1'0
-    assign { } 0'0
-    assign \oper_r__input_carry 2'00
-    assign \oper_r__output_carry 1'0
-    assign \oper_r__input_cr 1'0
-    assign \oper_r__output_cr 1'0
-    assign \oper_r__is_32bit 1'0
-    assign \oper_r__is_signed 1'0
-    assign \oper_r__insn 32'00000000000000000000000000000000
-    assign { \oper_r__insn \oper_r__is_signed \oper_r__is_32bit \oper_r__output_cr \oper_r__input_cr \oper_r__output_carry \oper_r__input_carry { } { \oper_r__oe__oe_ok \oper_r__oe__oe } { \oper_r__rc__rc_ok \oper_r__rc__rc } { \oper_r__imm_data__imm_ok \oper_r__imm_data__imm } \oper_r__fn_unit \oper_r__insn_type } $70
-    sync init
-  end
-  process $group_41
-    assign \oper_l__insn_type$next \oper_l__insn_type
-    assign \oper_l__fn_unit$next \oper_l__fn_unit
-    assign \oper_l__imm_data__imm$next \oper_l__imm_data__imm
-    assign \oper_l__imm_data__imm_ok$next \oper_l__imm_data__imm_ok
-    assign \oper_l__rc__rc$next \oper_l__rc__rc
-    assign \oper_l__rc__rc_ok$next \oper_l__rc__rc_ok
-    assign \oper_l__oe__oe$next \oper_l__oe__oe
-    assign \oper_l__oe__oe_ok$next \oper_l__oe__oe_ok
-    assign { } { }
-    assign \oper_l__input_carry$next \oper_l__input_carry
-    assign \oper_l__output_carry$next \oper_l__output_carry
-    assign \oper_l__input_cr$next \oper_l__input_cr
-    assign \oper_l__output_cr$next \oper_l__output_cr
-    assign \oper_l__is_32bit$next \oper_l__is_32bit
-    assign \oper_l__is_signed$next \oper_l__is_signed
-    assign \oper_l__insn$next \oper_l__insn
-    attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
-    switch { \cu_issue_i }
-      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
-      case 1'1
-        assign { \oper_l__insn$next \oper_l__is_signed$next \oper_l__is_32bit$next \oper_l__output_cr$next \oper_l__input_cr$next \oper_l__output_carry$next \oper_l__input_carry$next { } { \oper_l__oe__oe_ok$next \oper_l__oe__oe$next } { \oper_l__rc__rc_ok$next \oper_l__rc__rc$next } { \oper_l__imm_data__imm_ok$next \oper_l__imm_data__imm$next } \oper_l__fn_unit$next \oper_l__insn_type$next } { \oper_i_alu_shift_rot0__insn \oper_i_alu_shift_rot0__is_signed \oper_i_alu_shift_rot0__is_32bit \oper_i_alu_shift_rot0__output_cr \oper_i_alu_shift_rot0__input_cr \oper_i_alu_shift_rot0__output_carry \oper_i_alu_shift_rot0__input_carry { } { \oper_i_alu_shift_rot0__oe__oe_ok \oper_i_alu_shift_rot0__oe__oe } { \oper_i_alu_shift_rot0__rc__rc_ok \oper_i_alu_shift_rot0__rc__rc } { \oper_i_alu_shift_rot0__imm_data__imm_ok \oper_i_alu_shift_rot0__imm_data__imm } \oper_i_alu_shift_rot0__fn_unit \oper_i_alu_shift_rot0__insn_type }
-    end
-    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
-      case 1'1
-        assign \oper_l__imm_data__imm$next 64'0000000000000000000000000000000000000000000000000000000000000000
-        assign \oper_l__imm_data__imm_ok$next 1'0
-        assign \oper_l__rc__rc$next 1'0
-        assign \oper_l__rc__rc_ok$next 1'0
-        assign \oper_l__oe__oe$next 1'0
-        assign \oper_l__oe__oe_ok$next 1'0
-    end
-    sync init
-      update \oper_l__insn_type 7'0000000
-      update \oper_l__fn_unit 11'00000000000
-      update \oper_l__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
-      update \oper_l__imm_data__imm_ok 1'0
-      update \oper_l__rc__rc 1'0
-      update \oper_l__rc__rc_ok 1'0
-      update \oper_l__oe__oe 1'0
-      update \oper_l__oe__oe_ok 1'0
-      update { } 0'0
-      update \oper_l__input_carry 2'00
-      update \oper_l__output_carry 1'0
-      update \oper_l__input_cr 1'0
-      update \oper_l__output_cr 1'0
-      update \oper_l__is_32bit 1'0
-      update \oper_l__is_signed 1'0
-      update \oper_l__insn 32'00000000000000000000000000000000
-    sync posedge \clk
-      update \oper_l__insn_type \oper_l__insn_type$next
-      update \oper_l__fn_unit \oper_l__fn_unit$next
-      update \oper_l__imm_data__imm \oper_l__imm_data__imm$next
-      update \oper_l__imm_data__imm_ok \oper_l__imm_data__imm_ok$next
-      update \oper_l__rc__rc \oper_l__rc__rc$next
-      update \oper_l__rc__rc_ok \oper_l__rc__rc_ok$next
-      update \oper_l__oe__oe \oper_l__oe__oe$next
-      update \oper_l__oe__oe_ok \oper_l__oe__oe_ok$next
-      update { } { }
-      update \oper_l__input_carry \oper_l__input_carry$next
-      update \oper_l__output_carry \oper_l__output_carry$next
-      update \oper_l__input_cr \oper_l__input_cr$next
-      update \oper_l__output_cr \oper_l__output_cr$next
-      update \oper_l__is_32bit \oper_l__is_32bit$next
-      update \oper_l__is_signed \oper_l__is_signed$next
-      update \oper_l__insn \oper_l__insn$next
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
-  wire width 64 \data_r0__o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
-  wire width 1 \data_r0__o_ok
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
-  wire width 64 \data_r0_l__o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
-  wire width 64 \data_r0_l__o$next
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
-  wire width 1 \data_r0_l__o_ok
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
-  wire width 1 \data_r0_l__o_ok$next
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
-  wire width 65 $72
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744"
-  wire width 1 $73
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744"
-  cell $reduce_bool $74
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 3
-    parameter \Y_WIDTH 1
-    connect \A \alu_pulsem
-    connect \Y $73
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
-  cell $mux $75
-    parameter \WIDTH 65
-    connect \A { \data_r0_l__o_ok \data_r0_l__o }
-    connect \B { \o_ok \alu_shift_rot0_o }
-    connect \S $73
-    connect \Y $72
+  wire width 32 input 26 \mul_op__insn
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
+  wire width 64 input 27 \ra
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
+  wire width 64 input 28 \rb
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
+  wire width 1 input 29 \xer_so$1
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153"
+  wire width 1 input 30 \p_valid_i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154"
+  wire width 1 output 31 \p_ready_o
+  cell \p$87 \p
+    connect \p_valid_i \p_valid_i
+    connect \p_ready_o \p_ready_o
   end
-  process $group_57
-    assign \data_r0__o 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \data_r0__o_ok 1'0
-    assign { \data_r0__o_ok \data_r0__o } $72
-    sync init
+  cell \n$88 \n
+    connect \n_valid_o \n_valid_o
+    connect \n_ready_i \n_ready_i
   end
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
-  wire width 1 $76
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
-  cell $reduce_bool $77
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 3
-    parameter \Y_WIDTH 1
-    connect \A \alu_pulsem
-    connect \Y $76
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
+  wire width 1 \mul_pipe1_n_valid_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
+  wire width 1 \mul_pipe1_n_ready_i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
+  wire width 2 \mul_pipe1_muxid
+  attribute \enum_base_type "MicrOp"
+  attribute \enum_value_0000000 "OP_ILLEGAL"
+  attribute \enum_value_0000001 "OP_NOP"
+  attribute \enum_value_0000010 "OP_ADD"
+  attribute \enum_value_0000011 "OP_ADDPCIS"
+  attribute \enum_value_0000100 "OP_AND"
+  attribute \enum_value_0000101 "OP_ATTN"
+  attribute \enum_value_0000110 "OP_B"
+  attribute \enum_value_0000111 "OP_BC"
+  attribute \enum_value_0001000 "OP_BCREG"
+  attribute \enum_value_0001001 "OP_BPERM"
+  attribute \enum_value_0001010 "OP_CMP"
+  attribute \enum_value_0001011 "OP_CMPB"
+  attribute \enum_value_0001100 "OP_CMPEQB"
+  attribute \enum_value_0001101 "OP_CMPRB"
+  attribute \enum_value_0001110 "OP_CNTZ"
+  attribute \enum_value_0001111 "OP_CRAND"
+  attribute \enum_value_0010000 "OP_CRANDC"
+  attribute \enum_value_0010001 "OP_CREQV"
+  attribute \enum_value_0010010 "OP_CRNAND"
+  attribute \enum_value_0010011 "OP_CRNOR"
+  attribute \enum_value_0010100 "OP_CROR"
+  attribute \enum_value_0010101 "OP_CRORC"
+  attribute \enum_value_0010110 "OP_CRXOR"
+  attribute \enum_value_0010111 "OP_DARN"
+  attribute \enum_value_0011000 "OP_DCBF"
+  attribute \enum_value_0011001 "OP_DCBST"
+  attribute \enum_value_0011010 "OP_DCBT"
+  attribute \enum_value_0011011 "OP_DCBTST"
+  attribute \enum_value_0011100 "OP_DCBZ"
+  attribute \enum_value_0011101 "OP_DIV"
+  attribute \enum_value_0011110 "OP_DIVE"
+  attribute \enum_value_0011111 "OP_EXTS"
+  attribute \enum_value_0100000 "OP_EXTSWSLI"
+  attribute \enum_value_0100001 "OP_ICBI"
+  attribute \enum_value_0100010 "OP_ICBT"
+  attribute \enum_value_0100011 "OP_ISEL"
+  attribute \enum_value_0100100 "OP_ISYNC"
+  attribute \enum_value_0100101 "OP_LOAD"
+  attribute \enum_value_0100110 "OP_STORE"
+  attribute \enum_value_0100111 "OP_MADDHD"
+  attribute \enum_value_0101000 "OP_MADDHDU"
+  attribute \enum_value_0101001 "OP_MADDLD"
+  attribute \enum_value_0101010 "OP_MCRF"
+  attribute \enum_value_0101011 "OP_MCRXR"
+  attribute \enum_value_0101100 "OP_MCRXRX"
+  attribute \enum_value_0101101 "OP_MFCR"
+  attribute \enum_value_0101110 "OP_MFSPR"
+  attribute \enum_value_0101111 "OP_MOD"
+  attribute \enum_value_0110000 "OP_MTCRF"
+  attribute \enum_value_0110001 "OP_MTSPR"
+  attribute \enum_value_0110010 "OP_MUL_L64"
+  attribute \enum_value_0110011 "OP_MUL_H64"
+  attribute \enum_value_0110100 "OP_MUL_H32"
+  attribute \enum_value_0110101 "OP_OR"
+  attribute \enum_value_0110110 "OP_POPCNT"
+  attribute \enum_value_0110111 "OP_PRTY"
+  attribute \enum_value_0111000 "OP_RLC"
+  attribute \enum_value_0111001 "OP_RLCL"
+  attribute \enum_value_0111010 "OP_RLCR"
+  attribute \enum_value_0111011 "OP_SETB"
+  attribute \enum_value_0111100 "OP_SHL"
+  attribute \enum_value_0111101 "OP_SHR"
+  attribute \enum_value_0111110 "OP_SYNC"
+  attribute \enum_value_0111111 "OP_TRAP"
+  attribute \enum_value_1000011 "OP_XOR"
+  attribute \enum_value_1000100 "OP_SIM_CONFIG"
+  attribute \enum_value_1000101 "OP_CROP"
+  attribute \enum_value_1000110 "OP_RFID"
+  attribute \enum_value_1000111 "OP_MFMSR"
+  attribute \enum_value_1001000 "OP_MTMSRD"
+  attribute \enum_value_1001001 "OP_SC"
+  attribute \enum_value_1001010 "OP_MTMSR"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 \mul_pipe1_mul_op__insn_type
+  attribute \enum_base_type "Function"
+  attribute \enum_value_00000000000 "NONE"
+  attribute \enum_value_00000000010 "ALU"
+  attribute \enum_value_00000000100 "LDST"
+  attribute \enum_value_00000001000 "SHIFT_ROT"
+  attribute \enum_value_00000010000 "LOGICAL"
+  attribute \enum_value_00000100000 "BRANCH"
+  attribute \enum_value_00001000000 "CR"
+  attribute \enum_value_00010000000 "TRAP"
+  attribute \enum_value_00100000000 "MUL"
+  attribute \enum_value_01000000000 "DIV"
+  attribute \enum_value_10000000000 "SPR"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 \mul_pipe1_mul_op__fn_unit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 \mul_pipe1_mul_op__imm_data__imm
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_pipe1_mul_op__imm_data__imm_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_pipe1_mul_op__rc__rc
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_pipe1_mul_op__rc__rc_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_pipe1_mul_op__oe__oe
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_pipe1_mul_op__oe__oe_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_pipe1_mul_op__invert_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_pipe1_mul_op__zero_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_pipe1_mul_op__invert_out
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_pipe1_mul_op__write_cr0
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_pipe1_mul_op__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_pipe1_mul_op__is_signed
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \mul_pipe1_mul_op__insn
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
+  wire width 64 \mul_pipe1_ra
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
+  wire width 64 \mul_pipe1_rb
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
+  wire width 1 \mul_pipe1_xer_so
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11"
+  wire width 1 \mul_pipe1_neg_res
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12"
+  wire width 1 \mul_pipe1_neg_res32
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153"
+  wire width 1 \mul_pipe1_p_valid_i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154"
+  wire width 1 \mul_pipe1_p_ready_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
+  wire width 2 \mul_pipe1_muxid$2
+  attribute \enum_base_type "MicrOp"
+  attribute \enum_value_0000000 "OP_ILLEGAL"
+  attribute \enum_value_0000001 "OP_NOP"
+  attribute \enum_value_0000010 "OP_ADD"
+  attribute \enum_value_0000011 "OP_ADDPCIS"
+  attribute \enum_value_0000100 "OP_AND"
+  attribute \enum_value_0000101 "OP_ATTN"
+  attribute \enum_value_0000110 "OP_B"
+  attribute \enum_value_0000111 "OP_BC"
+  attribute \enum_value_0001000 "OP_BCREG"
+  attribute \enum_value_0001001 "OP_BPERM"
+  attribute \enum_value_0001010 "OP_CMP"
+  attribute \enum_value_0001011 "OP_CMPB"
+  attribute \enum_value_0001100 "OP_CMPEQB"
+  attribute \enum_value_0001101 "OP_CMPRB"
+  attribute \enum_value_0001110 "OP_CNTZ"
+  attribute \enum_value_0001111 "OP_CRAND"
+  attribute \enum_value_0010000 "OP_CRANDC"
+  attribute \enum_value_0010001 "OP_CREQV"
+  attribute \enum_value_0010010 "OP_CRNAND"
+  attribute \enum_value_0010011 "OP_CRNOR"
+  attribute \enum_value_0010100 "OP_CROR"
+  attribute \enum_value_0010101 "OP_CRORC"
+  attribute \enum_value_0010110 "OP_CRXOR"
+  attribute \enum_value_0010111 "OP_DARN"
+  attribute \enum_value_0011000 "OP_DCBF"
+  attribute \enum_value_0011001 "OP_DCBST"
+  attribute \enum_value_0011010 "OP_DCBT"
+  attribute \enum_value_0011011 "OP_DCBTST"
+  attribute \enum_value_0011100 "OP_DCBZ"
+  attribute \enum_value_0011101 "OP_DIV"
+  attribute \enum_value_0011110 "OP_DIVE"
+  attribute \enum_value_0011111 "OP_EXTS"
+  attribute \enum_value_0100000 "OP_EXTSWSLI"
+  attribute \enum_value_0100001 "OP_ICBI"
+  attribute \enum_value_0100010 "OP_ICBT"
+  attribute \enum_value_0100011 "OP_ISEL"
+  attribute \enum_value_0100100 "OP_ISYNC"
+  attribute \enum_value_0100101 "OP_LOAD"
+  attribute \enum_value_0100110 "OP_STORE"
+  attribute \enum_value_0100111 "OP_MADDHD"
+  attribute \enum_value_0101000 "OP_MADDHDU"
+  attribute \enum_value_0101001 "OP_MADDLD"
+  attribute \enum_value_0101010 "OP_MCRF"
+  attribute \enum_value_0101011 "OP_MCRXR"
+  attribute \enum_value_0101100 "OP_MCRXRX"
+  attribute \enum_value_0101101 "OP_MFCR"
+  attribute \enum_value_0101110 "OP_MFSPR"
+  attribute \enum_value_0101111 "OP_MOD"
+  attribute \enum_value_0110000 "OP_MTCRF"
+  attribute \enum_value_0110001 "OP_MTSPR"
+  attribute \enum_value_0110010 "OP_MUL_L64"
+  attribute \enum_value_0110011 "OP_MUL_H64"
+  attribute \enum_value_0110100 "OP_MUL_H32"
+  attribute \enum_value_0110101 "OP_OR"
+  attribute \enum_value_0110110 "OP_POPCNT"
+  attribute \enum_value_0110111 "OP_PRTY"
+  attribute \enum_value_0111000 "OP_RLC"
+  attribute \enum_value_0111001 "OP_RLCL"
+  attribute \enum_value_0111010 "OP_RLCR"
+  attribute \enum_value_0111011 "OP_SETB"
+  attribute \enum_value_0111100 "OP_SHL"
+  attribute \enum_value_0111101 "OP_SHR"
+  attribute \enum_value_0111110 "OP_SYNC"
+  attribute \enum_value_0111111 "OP_TRAP"
+  attribute \enum_value_1000011 "OP_XOR"
+  attribute \enum_value_1000100 "OP_SIM_CONFIG"
+  attribute \enum_value_1000101 "OP_CROP"
+  attribute \enum_value_1000110 "OP_RFID"
+  attribute \enum_value_1000111 "OP_MFMSR"
+  attribute \enum_value_1001000 "OP_MTMSRD"
+  attribute \enum_value_1001001 "OP_SC"
+  attribute \enum_value_1001010 "OP_MTMSR"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 \mul_pipe1_mul_op__insn_type$3
+  attribute \enum_base_type "Function"
+  attribute \enum_value_00000000000 "NONE"
+  attribute \enum_value_00000000010 "ALU"
+  attribute \enum_value_00000000100 "LDST"
+  attribute \enum_value_00000001000 "SHIFT_ROT"
+  attribute \enum_value_00000010000 "LOGICAL"
+  attribute \enum_value_00000100000 "BRANCH"
+  attribute \enum_value_00001000000 "CR"
+  attribute \enum_value_00010000000 "TRAP"
+  attribute \enum_value_00100000000 "MUL"
+  attribute \enum_value_01000000000 "DIV"
+  attribute \enum_value_10000000000 "SPR"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 \mul_pipe1_mul_op__fn_unit$4
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 \mul_pipe1_mul_op__imm_data__imm$5
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_pipe1_mul_op__imm_data__imm_ok$6
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_pipe1_mul_op__rc__rc$7
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_pipe1_mul_op__rc__rc_ok$8
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_pipe1_mul_op__oe__oe$9
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_pipe1_mul_op__oe__oe_ok$10
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_pipe1_mul_op__invert_a$11
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_pipe1_mul_op__zero_a$12
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_pipe1_mul_op__invert_out$13
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_pipe1_mul_op__write_cr0$14
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_pipe1_mul_op__is_32bit$15
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_pipe1_mul_op__is_signed$16
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \mul_pipe1_mul_op__insn$17
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
+  wire width 64 \mul_pipe1_ra$18
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
+  wire width 64 \mul_pipe1_rb$19
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
+  wire width 1 \mul_pipe1_xer_so$20
+  cell \mul_pipe1 \mul_pipe1
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
+    connect \n_valid_o \mul_pipe1_n_valid_o
+    connect \n_ready_i \mul_pipe1_n_ready_i
+    connect \muxid \mul_pipe1_muxid
+    connect \mul_op__insn_type \mul_pipe1_mul_op__insn_type
+    connect \mul_op__fn_unit \mul_pipe1_mul_op__fn_unit
+    connect \mul_op__imm_data__imm \mul_pipe1_mul_op__imm_data__imm
+    connect \mul_op__imm_data__imm_ok \mul_pipe1_mul_op__imm_data__imm_ok
+    connect \mul_op__rc__rc \mul_pipe1_mul_op__rc__rc
+    connect \mul_op__rc__rc_ok \mul_pipe1_mul_op__rc__rc_ok
+    connect \mul_op__oe__oe \mul_pipe1_mul_op__oe__oe
+    connect \mul_op__oe__oe_ok \mul_pipe1_mul_op__oe__oe_ok
+    connect \mul_op__invert_a \mul_pipe1_mul_op__invert_a
+    connect \mul_op__zero_a \mul_pipe1_mul_op__zero_a
+    connect \mul_op__invert_out \mul_pipe1_mul_op__invert_out
+    connect \mul_op__write_cr0 \mul_pipe1_mul_op__write_cr0
+    connect \mul_op__is_32bit \mul_pipe1_mul_op__is_32bit
+    connect \mul_op__is_signed \mul_pipe1_mul_op__is_signed
+    connect \mul_op__insn \mul_pipe1_mul_op__insn
+    connect \ra \mul_pipe1_ra
+    connect \rb \mul_pipe1_rb
+    connect \xer_so \mul_pipe1_xer_so
+    connect \neg_res \mul_pipe1_neg_res
+    connect \neg_res32 \mul_pipe1_neg_res32
+    connect \p_valid_i \mul_pipe1_p_valid_i
+    connect \p_ready_o \mul_pipe1_p_ready_o
+    connect \muxid$1 \mul_pipe1_muxid$2
+    connect \mul_op__insn_type$2 \mul_pipe1_mul_op__insn_type$3
+    connect \mul_op__fn_unit$3 \mul_pipe1_mul_op__fn_unit$4
+    connect \mul_op__imm_data__imm$4 \mul_pipe1_mul_op__imm_data__imm$5
+    connect \mul_op__imm_data__imm_ok$5 \mul_pipe1_mul_op__imm_data__imm_ok$6
+    connect \mul_op__rc__rc$6 \mul_pipe1_mul_op__rc__rc$7
+    connect \mul_op__rc__rc_ok$7 \mul_pipe1_mul_op__rc__rc_ok$8
+    connect \mul_op__oe__oe$8 \mul_pipe1_mul_op__oe__oe$9
+    connect \mul_op__oe__oe_ok$9 \mul_pipe1_mul_op__oe__oe_ok$10
+    connect \mul_op__invert_a$10 \mul_pipe1_mul_op__invert_a$11
+    connect \mul_op__zero_a$11 \mul_pipe1_mul_op__zero_a$12
+    connect \mul_op__invert_out$12 \mul_pipe1_mul_op__invert_out$13
+    connect \mul_op__write_cr0$13 \mul_pipe1_mul_op__write_cr0$14
+    connect \mul_op__is_32bit$14 \mul_pipe1_mul_op__is_32bit$15
+    connect \mul_op__is_signed$15 \mul_pipe1_mul_op__is_signed$16
+    connect \mul_op__insn$16 \mul_pipe1_mul_op__insn$17
+    connect \ra$17 \mul_pipe1_ra$18
+    connect \rb$18 \mul_pipe1_rb$19
+    connect \xer_so$19 \mul_pipe1_xer_so$20
   end
-  process $group_59
-    assign \data_r0_l__o$next \data_r0_l__o
-    assign \data_r0_l__o_ok$next \data_r0_l__o_ok
-    attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
-    switch { $76 }
-      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
-      case 1'1
-        assign { \data_r0_l__o_ok$next \data_r0_l__o$next } { \o_ok \alu_shift_rot0_o }
-    end
-    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
-      case 1'1
-        assign \data_r0_l__o_ok$next 1'0
-    end
-    sync init
-      update \data_r0_l__o 64'0000000000000000000000000000000000000000000000000000000000000000
-      update \data_r0_l__o_ok 1'0
-    sync posedge \clk
-      update \data_r0_l__o \data_r0_l__o$next
-      update \data_r0_l__o_ok \data_r0_l__o_ok$next
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
-  wire width 4 \data_r1__cr_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
-  wire width 1 \data_r1__cr_a_ok
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
-  wire width 4 \data_r1_l__cr_a
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
-  wire width 4 \data_r1_l__cr_a$next
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
-  wire width 1 \data_r1_l__cr_a_ok
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
-  wire width 1 \data_r1_l__cr_a_ok$next
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
-  wire width 5 $78
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744"
-  wire width 1 $79
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744"
-  cell $reduce_bool $80
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 3
-    parameter \Y_WIDTH 1
-    connect \A \alu_pulsem
-    connect \Y $79
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
-  cell $mux $81
-    parameter \WIDTH 5
-    connect \A { \data_r1_l__cr_a_ok \data_r1_l__cr_a }
-    connect \B { \cr_a_ok \alu_shift_rot0_cr_a }
-    connect \S $79
-    connect \Y $78
-  end
-  process $group_61
-    assign \data_r1__cr_a 4'0000
-    assign \data_r1__cr_a_ok 1'0
-    assign { \data_r1__cr_a_ok \data_r1__cr_a } $78
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
-  wire width 1 $82
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
-  cell $reduce_bool $83
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 3
-    parameter \Y_WIDTH 1
-    connect \A \alu_pulsem
-    connect \Y $82
-  end
-  process $group_63
-    assign \data_r1_l__cr_a$next \data_r1_l__cr_a
-    assign \data_r1_l__cr_a_ok$next \data_r1_l__cr_a_ok
-    attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
-    switch { $82 }
-      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
-      case 1'1
-        assign { \data_r1_l__cr_a_ok$next \data_r1_l__cr_a$next } { \cr_a_ok \alu_shift_rot0_cr_a }
-    end
-    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
-      case 1'1
-        assign \data_r1_l__cr_a_ok$next 1'0
-    end
-    sync init
-      update \data_r1_l__cr_a 4'0000
-      update \data_r1_l__cr_a_ok 1'0
-    sync posedge \clk
-      update \data_r1_l__cr_a \data_r1_l__cr_a$next
-      update \data_r1_l__cr_a_ok \data_r1_l__cr_a_ok$next
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
-  wire width 2 \data_r2__xer_ca
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
-  wire width 1 \data_r2__xer_ca_ok
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
-  wire width 2 \data_r2_l__xer_ca
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
-  wire width 2 \data_r2_l__xer_ca$next
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
-  wire width 1 \data_r2_l__xer_ca_ok
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
-  wire width 1 \data_r2_l__xer_ca_ok$next
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
-  wire width 3 $84
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744"
-  wire width 1 $85
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744"
-  cell $reduce_bool $86
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 3
-    parameter \Y_WIDTH 1
-    connect \A \alu_pulsem
-    connect \Y $85
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
-  cell $mux $87
-    parameter \WIDTH 3
-    connect \A { \data_r2_l__xer_ca_ok \data_r2_l__xer_ca }
-    connect \B { \xer_ca_ok \alu_shift_rot0_xer_ca }
-    connect \S $85
-    connect \Y $84
-  end
-  process $group_65
-    assign \data_r2__xer_ca 2'00
-    assign \data_r2__xer_ca_ok 1'0
-    assign { \data_r2__xer_ca_ok \data_r2__xer_ca } $84
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
-  wire width 1 $88
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
-  cell $reduce_bool $89
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 3
-    parameter \Y_WIDTH 1
-    connect \A \alu_pulsem
-    connect \Y $88
-  end
-  process $group_67
-    assign \data_r2_l__xer_ca$next \data_r2_l__xer_ca
-    assign \data_r2_l__xer_ca_ok$next \data_r2_l__xer_ca_ok
-    attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
-    switch { $88 }
-      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
-      case 1'1
-        assign { \data_r2_l__xer_ca_ok$next \data_r2_l__xer_ca$next } { \xer_ca_ok \alu_shift_rot0_xer_ca }
-    end
-    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
-      case 1'1
-        assign \data_r2_l__xer_ca_ok$next 1'0
-    end
-    sync init
-      update \data_r2_l__xer_ca 2'00
-      update \data_r2_l__xer_ca_ok 1'0
-    sync posedge \clk
-      update \data_r2_l__xer_ca \data_r2_l__xer_ca$next
-      update \data_r2_l__xer_ca_ok \data_r2_l__xer_ca_ok$next
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278"
-  wire width 1 $90
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278"
-  cell $and $91
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \data_r0__o_ok
-    connect \B \cu_busy_o
-    connect \Y $90
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278"
-  wire width 1 $92
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278"
-  cell $and $93
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \data_r1__cr_a_ok
-    connect \B \cu_busy_o
-    connect \Y $92
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278"
-  wire width 1 $94
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278"
-  cell $and $95
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \data_r2__xer_ca_ok
-    connect \B \cu_busy_o
-    connect \Y $94
-  end
-  process $group_69
-    assign \cu_wrmask_o 3'000
-    assign \cu_wrmask_o { $94 $92 $90 }
-    sync init
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153"
+  wire width 1 \mul_pipe2_p_valid_i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154"
+  wire width 1 \mul_pipe2_p_ready_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
+  wire width 2 \mul_pipe2_muxid
+  attribute \enum_base_type "MicrOp"
+  attribute \enum_value_0000000 "OP_ILLEGAL"
+  attribute \enum_value_0000001 "OP_NOP"
+  attribute \enum_value_0000010 "OP_ADD"
+  attribute \enum_value_0000011 "OP_ADDPCIS"
+  attribute \enum_value_0000100 "OP_AND"
+  attribute \enum_value_0000101 "OP_ATTN"
+  attribute \enum_value_0000110 "OP_B"
+  attribute \enum_value_0000111 "OP_BC"
+  attribute \enum_value_0001000 "OP_BCREG"
+  attribute \enum_value_0001001 "OP_BPERM"
+  attribute \enum_value_0001010 "OP_CMP"
+  attribute \enum_value_0001011 "OP_CMPB"
+  attribute \enum_value_0001100 "OP_CMPEQB"
+  attribute \enum_value_0001101 "OP_CMPRB"
+  attribute \enum_value_0001110 "OP_CNTZ"
+  attribute \enum_value_0001111 "OP_CRAND"
+  attribute \enum_value_0010000 "OP_CRANDC"
+  attribute \enum_value_0010001 "OP_CREQV"
+  attribute \enum_value_0010010 "OP_CRNAND"
+  attribute \enum_value_0010011 "OP_CRNOR"
+  attribute \enum_value_0010100 "OP_CROR"
+  attribute \enum_value_0010101 "OP_CRORC"
+  attribute \enum_value_0010110 "OP_CRXOR"
+  attribute \enum_value_0010111 "OP_DARN"
+  attribute \enum_value_0011000 "OP_DCBF"
+  attribute \enum_value_0011001 "OP_DCBST"
+  attribute \enum_value_0011010 "OP_DCBT"
+  attribute \enum_value_0011011 "OP_DCBTST"
+  attribute \enum_value_0011100 "OP_DCBZ"
+  attribute \enum_value_0011101 "OP_DIV"
+  attribute \enum_value_0011110 "OP_DIVE"
+  attribute \enum_value_0011111 "OP_EXTS"
+  attribute \enum_value_0100000 "OP_EXTSWSLI"
+  attribute \enum_value_0100001 "OP_ICBI"
+  attribute \enum_value_0100010 "OP_ICBT"
+  attribute \enum_value_0100011 "OP_ISEL"
+  attribute \enum_value_0100100 "OP_ISYNC"
+  attribute \enum_value_0100101 "OP_LOAD"
+  attribute \enum_value_0100110 "OP_STORE"
+  attribute \enum_value_0100111 "OP_MADDHD"
+  attribute \enum_value_0101000 "OP_MADDHDU"
+  attribute \enum_value_0101001 "OP_MADDLD"
+  attribute \enum_value_0101010 "OP_MCRF"
+  attribute \enum_value_0101011 "OP_MCRXR"
+  attribute \enum_value_0101100 "OP_MCRXRX"
+  attribute \enum_value_0101101 "OP_MFCR"
+  attribute \enum_value_0101110 "OP_MFSPR"
+  attribute \enum_value_0101111 "OP_MOD"
+  attribute \enum_value_0110000 "OP_MTCRF"
+  attribute \enum_value_0110001 "OP_MTSPR"
+  attribute \enum_value_0110010 "OP_MUL_L64"
+  attribute \enum_value_0110011 "OP_MUL_H64"
+  attribute \enum_value_0110100 "OP_MUL_H32"
+  attribute \enum_value_0110101 "OP_OR"
+  attribute \enum_value_0110110 "OP_POPCNT"
+  attribute \enum_value_0110111 "OP_PRTY"
+  attribute \enum_value_0111000 "OP_RLC"
+  attribute \enum_value_0111001 "OP_RLCL"
+  attribute \enum_value_0111010 "OP_RLCR"
+  attribute \enum_value_0111011 "OP_SETB"
+  attribute \enum_value_0111100 "OP_SHL"
+  attribute \enum_value_0111101 "OP_SHR"
+  attribute \enum_value_0111110 "OP_SYNC"
+  attribute \enum_value_0111111 "OP_TRAP"
+  attribute \enum_value_1000011 "OP_XOR"
+  attribute \enum_value_1000100 "OP_SIM_CONFIG"
+  attribute \enum_value_1000101 "OP_CROP"
+  attribute \enum_value_1000110 "OP_RFID"
+  attribute \enum_value_1000111 "OP_MFMSR"
+  attribute \enum_value_1001000 "OP_MTMSRD"
+  attribute \enum_value_1001001 "OP_SC"
+  attribute \enum_value_1001010 "OP_MTMSR"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 \mul_pipe2_mul_op__insn_type
+  attribute \enum_base_type "Function"
+  attribute \enum_value_00000000000 "NONE"
+  attribute \enum_value_00000000010 "ALU"
+  attribute \enum_value_00000000100 "LDST"
+  attribute \enum_value_00000001000 "SHIFT_ROT"
+  attribute \enum_value_00000010000 "LOGICAL"
+  attribute \enum_value_00000100000 "BRANCH"
+  attribute \enum_value_00001000000 "CR"
+  attribute \enum_value_00010000000 "TRAP"
+  attribute \enum_value_00100000000 "MUL"
+  attribute \enum_value_01000000000 "DIV"
+  attribute \enum_value_10000000000 "SPR"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 \mul_pipe2_mul_op__fn_unit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 \mul_pipe2_mul_op__imm_data__imm
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_pipe2_mul_op__imm_data__imm_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_pipe2_mul_op__rc__rc
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_pipe2_mul_op__rc__rc_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_pipe2_mul_op__oe__oe
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_pipe2_mul_op__oe__oe_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_pipe2_mul_op__invert_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_pipe2_mul_op__zero_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_pipe2_mul_op__invert_out
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_pipe2_mul_op__write_cr0
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_pipe2_mul_op__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_pipe2_mul_op__is_signed
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \mul_pipe2_mul_op__insn
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
+  wire width 64 \mul_pipe2_ra
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
+  wire width 64 \mul_pipe2_rb
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
+  wire width 1 \mul_pipe2_xer_so
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11"
+  wire width 1 \mul_pipe2_neg_res
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12"
+  wire width 1 \mul_pipe2_neg_res32
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
+  wire width 1 \mul_pipe2_n_valid_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
+  wire width 1 \mul_pipe2_n_ready_i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
+  wire width 2 \mul_pipe2_muxid$21
+  attribute \enum_base_type "MicrOp"
+  attribute \enum_value_0000000 "OP_ILLEGAL"
+  attribute \enum_value_0000001 "OP_NOP"
+  attribute \enum_value_0000010 "OP_ADD"
+  attribute \enum_value_0000011 "OP_ADDPCIS"
+  attribute \enum_value_0000100 "OP_AND"
+  attribute \enum_value_0000101 "OP_ATTN"
+  attribute \enum_value_0000110 "OP_B"
+  attribute \enum_value_0000111 "OP_BC"
+  attribute \enum_value_0001000 "OP_BCREG"
+  attribute \enum_value_0001001 "OP_BPERM"
+  attribute \enum_value_0001010 "OP_CMP"
+  attribute \enum_value_0001011 "OP_CMPB"
+  attribute \enum_value_0001100 "OP_CMPEQB"
+  attribute \enum_value_0001101 "OP_CMPRB"
+  attribute \enum_value_0001110 "OP_CNTZ"
+  attribute \enum_value_0001111 "OP_CRAND"
+  attribute \enum_value_0010000 "OP_CRANDC"
+  attribute \enum_value_0010001 "OP_CREQV"
+  attribute \enum_value_0010010 "OP_CRNAND"
+  attribute \enum_value_0010011 "OP_CRNOR"
+  attribute \enum_value_0010100 "OP_CROR"
+  attribute \enum_value_0010101 "OP_CRORC"
+  attribute \enum_value_0010110 "OP_CRXOR"
+  attribute \enum_value_0010111 "OP_DARN"
+  attribute \enum_value_0011000 "OP_DCBF"
+  attribute \enum_value_0011001 "OP_DCBST"
+  attribute \enum_value_0011010 "OP_DCBT"
+  attribute \enum_value_0011011 "OP_DCBTST"
+  attribute \enum_value_0011100 "OP_DCBZ"
+  attribute \enum_value_0011101 "OP_DIV"
+  attribute \enum_value_0011110 "OP_DIVE"
+  attribute \enum_value_0011111 "OP_EXTS"
+  attribute \enum_value_0100000 "OP_EXTSWSLI"
+  attribute \enum_value_0100001 "OP_ICBI"
+  attribute \enum_value_0100010 "OP_ICBT"
+  attribute \enum_value_0100011 "OP_ISEL"
+  attribute \enum_value_0100100 "OP_ISYNC"
+  attribute \enum_value_0100101 "OP_LOAD"
+  attribute \enum_value_0100110 "OP_STORE"
+  attribute \enum_value_0100111 "OP_MADDHD"
+  attribute \enum_value_0101000 "OP_MADDHDU"
+  attribute \enum_value_0101001 "OP_MADDLD"
+  attribute \enum_value_0101010 "OP_MCRF"
+  attribute \enum_value_0101011 "OP_MCRXR"
+  attribute \enum_value_0101100 "OP_MCRXRX"
+  attribute \enum_value_0101101 "OP_MFCR"
+  attribute \enum_value_0101110 "OP_MFSPR"
+  attribute \enum_value_0101111 "OP_MOD"
+  attribute \enum_value_0110000 "OP_MTCRF"
+  attribute \enum_value_0110001 "OP_MTSPR"
+  attribute \enum_value_0110010 "OP_MUL_L64"
+  attribute \enum_value_0110011 "OP_MUL_H64"
+  attribute \enum_value_0110100 "OP_MUL_H32"
+  attribute \enum_value_0110101 "OP_OR"
+  attribute \enum_value_0110110 "OP_POPCNT"
+  attribute \enum_value_0110111 "OP_PRTY"
+  attribute \enum_value_0111000 "OP_RLC"
+  attribute \enum_value_0111001 "OP_RLCL"
+  attribute \enum_value_0111010 "OP_RLCR"
+  attribute \enum_value_0111011 "OP_SETB"
+  attribute \enum_value_0111100 "OP_SHL"
+  attribute \enum_value_0111101 "OP_SHR"
+  attribute \enum_value_0111110 "OP_SYNC"
+  attribute \enum_value_0111111 "OP_TRAP"
+  attribute \enum_value_1000011 "OP_XOR"
+  attribute \enum_value_1000100 "OP_SIM_CONFIG"
+  attribute \enum_value_1000101 "OP_CROP"
+  attribute \enum_value_1000110 "OP_RFID"
+  attribute \enum_value_1000111 "OP_MFMSR"
+  attribute \enum_value_1001000 "OP_MTMSRD"
+  attribute \enum_value_1001001 "OP_SC"
+  attribute \enum_value_1001010 "OP_MTMSR"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 \mul_pipe2_mul_op__insn_type$22
+  attribute \enum_base_type "Function"
+  attribute \enum_value_00000000000 "NONE"
+  attribute \enum_value_00000000010 "ALU"
+  attribute \enum_value_00000000100 "LDST"
+  attribute \enum_value_00000001000 "SHIFT_ROT"
+  attribute \enum_value_00000010000 "LOGICAL"
+  attribute \enum_value_00000100000 "BRANCH"
+  attribute \enum_value_00001000000 "CR"
+  attribute \enum_value_00010000000 "TRAP"
+  attribute \enum_value_00100000000 "MUL"
+  attribute \enum_value_01000000000 "DIV"
+  attribute \enum_value_10000000000 "SPR"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 \mul_pipe2_mul_op__fn_unit$23
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 \mul_pipe2_mul_op__imm_data__imm$24
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_pipe2_mul_op__imm_data__imm_ok$25
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_pipe2_mul_op__rc__rc$26
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_pipe2_mul_op__rc__rc_ok$27
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_pipe2_mul_op__oe__oe$28
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_pipe2_mul_op__oe__oe_ok$29
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_pipe2_mul_op__invert_a$30
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_pipe2_mul_op__zero_a$31
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_pipe2_mul_op__invert_out$32
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_pipe2_mul_op__write_cr0$33
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_pipe2_mul_op__is_32bit$34
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_pipe2_mul_op__is_signed$35
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \mul_pipe2_mul_op__insn$36
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
+  wire width 129 \mul_pipe2_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
+  wire width 1 \mul_pipe2_xer_so$37
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23"
+  wire width 1 \mul_pipe2_neg_res$38
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24"
+  wire width 1 \mul_pipe2_neg_res32$39
+  cell \mul_pipe2 \mul_pipe2
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
+    connect \p_valid_i \mul_pipe2_p_valid_i
+    connect \p_ready_o \mul_pipe2_p_ready_o
+    connect \muxid \mul_pipe2_muxid
+    connect \mul_op__insn_type \mul_pipe2_mul_op__insn_type
+    connect \mul_op__fn_unit \mul_pipe2_mul_op__fn_unit
+    connect \mul_op__imm_data__imm \mul_pipe2_mul_op__imm_data__imm
+    connect \mul_op__imm_data__imm_ok \mul_pipe2_mul_op__imm_data__imm_ok
+    connect \mul_op__rc__rc \mul_pipe2_mul_op__rc__rc
+    connect \mul_op__rc__rc_ok \mul_pipe2_mul_op__rc__rc_ok
+    connect \mul_op__oe__oe \mul_pipe2_mul_op__oe__oe
+    connect \mul_op__oe__oe_ok \mul_pipe2_mul_op__oe__oe_ok
+    connect \mul_op__invert_a \mul_pipe2_mul_op__invert_a
+    connect \mul_op__zero_a \mul_pipe2_mul_op__zero_a
+    connect \mul_op__invert_out \mul_pipe2_mul_op__invert_out
+    connect \mul_op__write_cr0 \mul_pipe2_mul_op__write_cr0
+    connect \mul_op__is_32bit \mul_pipe2_mul_op__is_32bit
+    connect \mul_op__is_signed \mul_pipe2_mul_op__is_signed
+    connect \mul_op__insn \mul_pipe2_mul_op__insn
+    connect \ra \mul_pipe2_ra
+    connect \rb \mul_pipe2_rb
+    connect \xer_so \mul_pipe2_xer_so
+    connect \neg_res \mul_pipe2_neg_res
+    connect \neg_res32 \mul_pipe2_neg_res32
+    connect \n_valid_o \mul_pipe2_n_valid_o
+    connect \n_ready_i \mul_pipe2_n_ready_i
+    connect \muxid$1 \mul_pipe2_muxid$21
+    connect \mul_op__insn_type$2 \mul_pipe2_mul_op__insn_type$22
+    connect \mul_op__fn_unit$3 \mul_pipe2_mul_op__fn_unit$23
+    connect \mul_op__imm_data__imm$4 \mul_pipe2_mul_op__imm_data__imm$24
+    connect \mul_op__imm_data__imm_ok$5 \mul_pipe2_mul_op__imm_data__imm_ok$25
+    connect \mul_op__rc__rc$6 \mul_pipe2_mul_op__rc__rc$26
+    connect \mul_op__rc__rc_ok$7 \mul_pipe2_mul_op__rc__rc_ok$27
+    connect \mul_op__oe__oe$8 \mul_pipe2_mul_op__oe__oe$28
+    connect \mul_op__oe__oe_ok$9 \mul_pipe2_mul_op__oe__oe_ok$29
+    connect \mul_op__invert_a$10 \mul_pipe2_mul_op__invert_a$30
+    connect \mul_op__zero_a$11 \mul_pipe2_mul_op__zero_a$31
+    connect \mul_op__invert_out$12 \mul_pipe2_mul_op__invert_out$32
+    connect \mul_op__write_cr0$13 \mul_pipe2_mul_op__write_cr0$33
+    connect \mul_op__is_32bit$14 \mul_pipe2_mul_op__is_32bit$34
+    connect \mul_op__is_signed$15 \mul_pipe2_mul_op__is_signed$35
+    connect \mul_op__insn$16 \mul_pipe2_mul_op__insn$36
+    connect \o \mul_pipe2_o
+    connect \xer_so$17 \mul_pipe2_xer_so$37
+    connect \neg_res$18 \mul_pipe2_neg_res$38
+    connect \neg_res32$19 \mul_pipe2_neg_res32$39
   end
-  process $group_70
-    assign \alu_shift_rot0_sr_op__insn_type 7'0000000
-    assign \alu_shift_rot0_sr_op__fn_unit 11'00000000000
-    assign \alu_shift_rot0_sr_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \alu_shift_rot0_sr_op__imm_data__imm_ok 1'0
-    assign \alu_shift_rot0_sr_op__rc__rc 1'0
-    assign \alu_shift_rot0_sr_op__rc__rc_ok 1'0
-    assign \alu_shift_rot0_sr_op__oe__oe 1'0
-    assign \alu_shift_rot0_sr_op__oe__oe_ok 1'0
-    assign { } 0'0
-    assign \alu_shift_rot0_sr_op__input_carry 2'00
-    assign \alu_shift_rot0_sr_op__output_carry 1'0
-    assign \alu_shift_rot0_sr_op__input_cr 1'0
-    assign \alu_shift_rot0_sr_op__output_cr 1'0
-    assign \alu_shift_rot0_sr_op__is_32bit 1'0
-    assign \alu_shift_rot0_sr_op__is_signed 1'0
-    assign \alu_shift_rot0_sr_op__insn 32'00000000000000000000000000000000
-    assign { \alu_shift_rot0_sr_op__insn \alu_shift_rot0_sr_op__is_signed \alu_shift_rot0_sr_op__is_32bit \alu_shift_rot0_sr_op__output_cr \alu_shift_rot0_sr_op__input_cr \alu_shift_rot0_sr_op__output_carry \alu_shift_rot0_sr_op__input_carry { } { \alu_shift_rot0_sr_op__oe__oe_ok \alu_shift_rot0_sr_op__oe__oe } { \alu_shift_rot0_sr_op__rc__rc_ok \alu_shift_rot0_sr_op__rc__rc } { \alu_shift_rot0_sr_op__imm_data__imm_ok \alu_shift_rot0_sr_op__imm_data__imm } \alu_shift_rot0_sr_op__fn_unit \alu_shift_rot0_sr_op__insn_type } { \oper_r__insn \oper_r__is_signed \oper_r__is_32bit \oper_r__output_cr \oper_r__input_cr \oper_r__output_carry \oper_r__input_carry { } { \oper_r__oe__oe_ok \oper_r__oe__oe } { \oper_r__rc__rc_ok \oper_r__rc__rc } { \oper_r__imm_data__imm_ok \oper_r__imm_data__imm } \oper_r__fn_unit \oper_r__insn_type }
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:166"
-  wire width 1 \src_sel
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:167"
-  wire width 1 $96
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:167"
-  cell $mux $97
-    parameter \WIDTH 1
-    connect \A \src_l_q_src [1]
-    connect \B \opc_l_q_opc
-    connect \S \oper_r__imm_data__imm_ok
-    connect \Y $96
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153"
+  wire width 1 \mul_pipe3_p_valid_i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154"
+  wire width 1 \mul_pipe3_p_ready_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
+  wire width 2 \mul_pipe3_muxid
+  attribute \enum_base_type "MicrOp"
+  attribute \enum_value_0000000 "OP_ILLEGAL"
+  attribute \enum_value_0000001 "OP_NOP"
+  attribute \enum_value_0000010 "OP_ADD"
+  attribute \enum_value_0000011 "OP_ADDPCIS"
+  attribute \enum_value_0000100 "OP_AND"
+  attribute \enum_value_0000101 "OP_ATTN"
+  attribute \enum_value_0000110 "OP_B"
+  attribute \enum_value_0000111 "OP_BC"
+  attribute \enum_value_0001000 "OP_BCREG"
+  attribute \enum_value_0001001 "OP_BPERM"
+  attribute \enum_value_0001010 "OP_CMP"
+  attribute \enum_value_0001011 "OP_CMPB"
+  attribute \enum_value_0001100 "OP_CMPEQB"
+  attribute \enum_value_0001101 "OP_CMPRB"
+  attribute \enum_value_0001110 "OP_CNTZ"
+  attribute \enum_value_0001111 "OP_CRAND"
+  attribute \enum_value_0010000 "OP_CRANDC"
+  attribute \enum_value_0010001 "OP_CREQV"
+  attribute \enum_value_0010010 "OP_CRNAND"
+  attribute \enum_value_0010011 "OP_CRNOR"
+  attribute \enum_value_0010100 "OP_CROR"
+  attribute \enum_value_0010101 "OP_CRORC"
+  attribute \enum_value_0010110 "OP_CRXOR"
+  attribute \enum_value_0010111 "OP_DARN"
+  attribute \enum_value_0011000 "OP_DCBF"
+  attribute \enum_value_0011001 "OP_DCBST"
+  attribute \enum_value_0011010 "OP_DCBT"
+  attribute \enum_value_0011011 "OP_DCBTST"
+  attribute \enum_value_0011100 "OP_DCBZ"
+  attribute \enum_value_0011101 "OP_DIV"
+  attribute \enum_value_0011110 "OP_DIVE"
+  attribute \enum_value_0011111 "OP_EXTS"
+  attribute \enum_value_0100000 "OP_EXTSWSLI"
+  attribute \enum_value_0100001 "OP_ICBI"
+  attribute \enum_value_0100010 "OP_ICBT"
+  attribute \enum_value_0100011 "OP_ISEL"
+  attribute \enum_value_0100100 "OP_ISYNC"
+  attribute \enum_value_0100101 "OP_LOAD"
+  attribute \enum_value_0100110 "OP_STORE"
+  attribute \enum_value_0100111 "OP_MADDHD"
+  attribute \enum_value_0101000 "OP_MADDHDU"
+  attribute \enum_value_0101001 "OP_MADDLD"
+  attribute \enum_value_0101010 "OP_MCRF"
+  attribute \enum_value_0101011 "OP_MCRXR"
+  attribute \enum_value_0101100 "OP_MCRXRX"
+  attribute \enum_value_0101101 "OP_MFCR"
+  attribute \enum_value_0101110 "OP_MFSPR"
+  attribute \enum_value_0101111 "OP_MOD"
+  attribute \enum_value_0110000 "OP_MTCRF"
+  attribute \enum_value_0110001 "OP_MTSPR"
+  attribute \enum_value_0110010 "OP_MUL_L64"
+  attribute \enum_value_0110011 "OP_MUL_H64"
+  attribute \enum_value_0110100 "OP_MUL_H32"
+  attribute \enum_value_0110101 "OP_OR"
+  attribute \enum_value_0110110 "OP_POPCNT"
+  attribute \enum_value_0110111 "OP_PRTY"
+  attribute \enum_value_0111000 "OP_RLC"
+  attribute \enum_value_0111001 "OP_RLCL"
+  attribute \enum_value_0111010 "OP_RLCR"
+  attribute \enum_value_0111011 "OP_SETB"
+  attribute \enum_value_0111100 "OP_SHL"
+  attribute \enum_value_0111101 "OP_SHR"
+  attribute \enum_value_0111110 "OP_SYNC"
+  attribute \enum_value_0111111 "OP_TRAP"
+  attribute \enum_value_1000011 "OP_XOR"
+  attribute \enum_value_1000100 "OP_SIM_CONFIG"
+  attribute \enum_value_1000101 "OP_CROP"
+  attribute \enum_value_1000110 "OP_RFID"
+  attribute \enum_value_1000111 "OP_MFMSR"
+  attribute \enum_value_1001000 "OP_MTMSRD"
+  attribute \enum_value_1001001 "OP_SC"
+  attribute \enum_value_1001010 "OP_MTMSR"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 \mul_pipe3_mul_op__insn_type
+  attribute \enum_base_type "Function"
+  attribute \enum_value_00000000000 "NONE"
+  attribute \enum_value_00000000010 "ALU"
+  attribute \enum_value_00000000100 "LDST"
+  attribute \enum_value_00000001000 "SHIFT_ROT"
+  attribute \enum_value_00000010000 "LOGICAL"
+  attribute \enum_value_00000100000 "BRANCH"
+  attribute \enum_value_00001000000 "CR"
+  attribute \enum_value_00010000000 "TRAP"
+  attribute \enum_value_00100000000 "MUL"
+  attribute \enum_value_01000000000 "DIV"
+  attribute \enum_value_10000000000 "SPR"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 \mul_pipe3_mul_op__fn_unit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 \mul_pipe3_mul_op__imm_data__imm
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_pipe3_mul_op__imm_data__imm_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_pipe3_mul_op__rc__rc
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_pipe3_mul_op__rc__rc_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_pipe3_mul_op__oe__oe
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_pipe3_mul_op__oe__oe_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_pipe3_mul_op__invert_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_pipe3_mul_op__zero_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_pipe3_mul_op__invert_out
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_pipe3_mul_op__write_cr0
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_pipe3_mul_op__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_pipe3_mul_op__is_signed
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \mul_pipe3_mul_op__insn
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
+  wire width 129 \mul_pipe3_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
+  wire width 1 \mul_pipe3_xer_so
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23"
+  wire width 1 \mul_pipe3_neg_res
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24"
+  wire width 1 \mul_pipe3_neg_res32
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
+  wire width 1 \mul_pipe3_n_valid_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
+  wire width 1 \mul_pipe3_n_ready_i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
+  wire width 2 \mul_pipe3_muxid$40
+  attribute \enum_base_type "MicrOp"
+  attribute \enum_value_0000000 "OP_ILLEGAL"
+  attribute \enum_value_0000001 "OP_NOP"
+  attribute \enum_value_0000010 "OP_ADD"
+  attribute \enum_value_0000011 "OP_ADDPCIS"
+  attribute \enum_value_0000100 "OP_AND"
+  attribute \enum_value_0000101 "OP_ATTN"
+  attribute \enum_value_0000110 "OP_B"
+  attribute \enum_value_0000111 "OP_BC"
+  attribute \enum_value_0001000 "OP_BCREG"
+  attribute \enum_value_0001001 "OP_BPERM"
+  attribute \enum_value_0001010 "OP_CMP"
+  attribute \enum_value_0001011 "OP_CMPB"
+  attribute \enum_value_0001100 "OP_CMPEQB"
+  attribute \enum_value_0001101 "OP_CMPRB"
+  attribute \enum_value_0001110 "OP_CNTZ"
+  attribute \enum_value_0001111 "OP_CRAND"
+  attribute \enum_value_0010000 "OP_CRANDC"
+  attribute \enum_value_0010001 "OP_CREQV"
+  attribute \enum_value_0010010 "OP_CRNAND"
+  attribute \enum_value_0010011 "OP_CRNOR"
+  attribute \enum_value_0010100 "OP_CROR"
+  attribute \enum_value_0010101 "OP_CRORC"
+  attribute \enum_value_0010110 "OP_CRXOR"
+  attribute \enum_value_0010111 "OP_DARN"
+  attribute \enum_value_0011000 "OP_DCBF"
+  attribute \enum_value_0011001 "OP_DCBST"
+  attribute \enum_value_0011010 "OP_DCBT"
+  attribute \enum_value_0011011 "OP_DCBTST"
+  attribute \enum_value_0011100 "OP_DCBZ"
+  attribute \enum_value_0011101 "OP_DIV"
+  attribute \enum_value_0011110 "OP_DIVE"
+  attribute \enum_value_0011111 "OP_EXTS"
+  attribute \enum_value_0100000 "OP_EXTSWSLI"
+  attribute \enum_value_0100001 "OP_ICBI"
+  attribute \enum_value_0100010 "OP_ICBT"
+  attribute \enum_value_0100011 "OP_ISEL"
+  attribute \enum_value_0100100 "OP_ISYNC"
+  attribute \enum_value_0100101 "OP_LOAD"
+  attribute \enum_value_0100110 "OP_STORE"
+  attribute \enum_value_0100111 "OP_MADDHD"
+  attribute \enum_value_0101000 "OP_MADDHDU"
+  attribute \enum_value_0101001 "OP_MADDLD"
+  attribute \enum_value_0101010 "OP_MCRF"
+  attribute \enum_value_0101011 "OP_MCRXR"
+  attribute \enum_value_0101100 "OP_MCRXRX"
+  attribute \enum_value_0101101 "OP_MFCR"
+  attribute \enum_value_0101110 "OP_MFSPR"
+  attribute \enum_value_0101111 "OP_MOD"
+  attribute \enum_value_0110000 "OP_MTCRF"
+  attribute \enum_value_0110001 "OP_MTSPR"
+  attribute \enum_value_0110010 "OP_MUL_L64"
+  attribute \enum_value_0110011 "OP_MUL_H64"
+  attribute \enum_value_0110100 "OP_MUL_H32"
+  attribute \enum_value_0110101 "OP_OR"
+  attribute \enum_value_0110110 "OP_POPCNT"
+  attribute \enum_value_0110111 "OP_PRTY"
+  attribute \enum_value_0111000 "OP_RLC"
+  attribute \enum_value_0111001 "OP_RLCL"
+  attribute \enum_value_0111010 "OP_RLCR"
+  attribute \enum_value_0111011 "OP_SETB"
+  attribute \enum_value_0111100 "OP_SHL"
+  attribute \enum_value_0111101 "OP_SHR"
+  attribute \enum_value_0111110 "OP_SYNC"
+  attribute \enum_value_0111111 "OP_TRAP"
+  attribute \enum_value_1000011 "OP_XOR"
+  attribute \enum_value_1000100 "OP_SIM_CONFIG"
+  attribute \enum_value_1000101 "OP_CROP"
+  attribute \enum_value_1000110 "OP_RFID"
+  attribute \enum_value_1000111 "OP_MFMSR"
+  attribute \enum_value_1001000 "OP_MTMSRD"
+  attribute \enum_value_1001001 "OP_SC"
+  attribute \enum_value_1001010 "OP_MTMSR"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 \mul_pipe3_mul_op__insn_type$41
+  attribute \enum_base_type "Function"
+  attribute \enum_value_00000000000 "NONE"
+  attribute \enum_value_00000000010 "ALU"
+  attribute \enum_value_00000000100 "LDST"
+  attribute \enum_value_00000001000 "SHIFT_ROT"
+  attribute \enum_value_00000010000 "LOGICAL"
+  attribute \enum_value_00000100000 "BRANCH"
+  attribute \enum_value_00001000000 "CR"
+  attribute \enum_value_00010000000 "TRAP"
+  attribute \enum_value_00100000000 "MUL"
+  attribute \enum_value_01000000000 "DIV"
+  attribute \enum_value_10000000000 "SPR"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 \mul_pipe3_mul_op__fn_unit$42
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 \mul_pipe3_mul_op__imm_data__imm$43
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_pipe3_mul_op__imm_data__imm_ok$44
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_pipe3_mul_op__rc__rc$45
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_pipe3_mul_op__rc__rc_ok$46
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_pipe3_mul_op__oe__oe$47
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_pipe3_mul_op__oe__oe_ok$48
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_pipe3_mul_op__invert_a$49
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_pipe3_mul_op__zero_a$50
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_pipe3_mul_op__invert_out$51
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_pipe3_mul_op__write_cr0$52
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_pipe3_mul_op__is_32bit$53
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_pipe3_mul_op__is_signed$54
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \mul_pipe3_mul_op__insn$55
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 64 \mul_pipe3_o$56
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 \mul_pipe3_o_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 4 \mul_pipe3_cr_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 \mul_pipe3_cr_a_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 2 \mul_pipe3_xer_ov
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 \mul_pipe3_xer_ov_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 \mul_pipe3_xer_so$57
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 \mul_pipe3_xer_so_ok
+  cell \mul_pipe3 \mul_pipe3
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
+    connect \p_valid_i \mul_pipe3_p_valid_i
+    connect \p_ready_o \mul_pipe3_p_ready_o
+    connect \muxid \mul_pipe3_muxid
+    connect \mul_op__insn_type \mul_pipe3_mul_op__insn_type
+    connect \mul_op__fn_unit \mul_pipe3_mul_op__fn_unit
+    connect \mul_op__imm_data__imm \mul_pipe3_mul_op__imm_data__imm
+    connect \mul_op__imm_data__imm_ok \mul_pipe3_mul_op__imm_data__imm_ok
+    connect \mul_op__rc__rc \mul_pipe3_mul_op__rc__rc
+    connect \mul_op__rc__rc_ok \mul_pipe3_mul_op__rc__rc_ok
+    connect \mul_op__oe__oe \mul_pipe3_mul_op__oe__oe
+    connect \mul_op__oe__oe_ok \mul_pipe3_mul_op__oe__oe_ok
+    connect \mul_op__invert_a \mul_pipe3_mul_op__invert_a
+    connect \mul_op__zero_a \mul_pipe3_mul_op__zero_a
+    connect \mul_op__invert_out \mul_pipe3_mul_op__invert_out
+    connect \mul_op__write_cr0 \mul_pipe3_mul_op__write_cr0
+    connect \mul_op__is_32bit \mul_pipe3_mul_op__is_32bit
+    connect \mul_op__is_signed \mul_pipe3_mul_op__is_signed
+    connect \mul_op__insn \mul_pipe3_mul_op__insn
+    connect \o \mul_pipe3_o
+    connect \xer_so \mul_pipe3_xer_so
+    connect \neg_res \mul_pipe3_neg_res
+    connect \neg_res32 \mul_pipe3_neg_res32
+    connect \n_valid_o \mul_pipe3_n_valid_o
+    connect \n_ready_i \mul_pipe3_n_ready_i
+    connect \muxid$1 \mul_pipe3_muxid$40
+    connect \mul_op__insn_type$2 \mul_pipe3_mul_op__insn_type$41
+    connect \mul_op__fn_unit$3 \mul_pipe3_mul_op__fn_unit$42
+    connect \mul_op__imm_data__imm$4 \mul_pipe3_mul_op__imm_data__imm$43
+    connect \mul_op__imm_data__imm_ok$5 \mul_pipe3_mul_op__imm_data__imm_ok$44
+    connect \mul_op__rc__rc$6 \mul_pipe3_mul_op__rc__rc$45
+    connect \mul_op__rc__rc_ok$7 \mul_pipe3_mul_op__rc__rc_ok$46
+    connect \mul_op__oe__oe$8 \mul_pipe3_mul_op__oe__oe$47
+    connect \mul_op__oe__oe_ok$9 \mul_pipe3_mul_op__oe__oe_ok$48
+    connect \mul_op__invert_a$10 \mul_pipe3_mul_op__invert_a$49
+    connect \mul_op__zero_a$11 \mul_pipe3_mul_op__zero_a$50
+    connect \mul_op__invert_out$12 \mul_pipe3_mul_op__invert_out$51
+    connect \mul_op__write_cr0$13 \mul_pipe3_mul_op__write_cr0$52
+    connect \mul_op__is_32bit$14 \mul_pipe3_mul_op__is_32bit$53
+    connect \mul_op__is_signed$15 \mul_pipe3_mul_op__is_signed$54
+    connect \mul_op__insn$16 \mul_pipe3_mul_op__insn$55
+    connect \o$17 \mul_pipe3_o$56
+    connect \o_ok \mul_pipe3_o_ok
+    connect \cr_a \mul_pipe3_cr_a
+    connect \cr_a_ok \mul_pipe3_cr_a_ok
+    connect \xer_ov \mul_pipe3_xer_ov
+    connect \xer_ov_ok \mul_pipe3_xer_ov_ok
+    connect \xer_so$18 \mul_pipe3_xer_so$57
+    connect \xer_so_ok \mul_pipe3_xer_so_ok
   end
-  process $group_86
-    assign \src_sel 1'0
-    assign \src_sel $96
+  process $group_0
+    assign \mul_pipe2_p_valid_i 1'0
+    assign \mul_pipe2_p_valid_i \mul_pipe1_n_valid_o
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:165"
-  wire width 64 \src_or_imm
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168"
-  wire width 64 $98
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168"
-  cell $mux $99
-    parameter \WIDTH 64
-    connect \A \src2_i
-    connect \B \oper_r__imm_data__imm
-    connect \S \oper_r__imm_data__imm_ok
-    connect \Y $98
-  end
-  process $group_87
-    assign \src_or_imm 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \src_or_imm $98
+  process $group_1
+    assign \mul_pipe1_n_ready_i 1'0
+    assign \mul_pipe1_n_ready_i \mul_pipe2_p_ready_o
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
-  wire width 64 \src_r0
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
-  wire width 64 \src_r0$next
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
-  wire width 64 $100
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
-  cell $mux $101
-    parameter \WIDTH 64
-    connect \A \src_r0
-    connect \B \src1_i
-    connect \S \src_l_q_src [0]
-    connect \Y $100
-  end
-  process $group_88
-    assign \alu_shift_rot0_ra 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \alu_shift_rot0_ra $100
+  process $group_2
+    assign \mul_pipe2_muxid 2'00
+    assign \mul_pipe2_muxid \mul_pipe1_muxid
     sync init
   end
-  process $group_89
-    assign \src_r0$next \src_r0
-    attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
-    switch { \src_l_q_src [0] }
-      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
-      case 1'1
-        assign \src_r0$next \src1_i
-    end
+  process $group_3
+    assign \mul_pipe2_mul_op__insn_type 7'0000000
+    assign \mul_pipe2_mul_op__fn_unit 11'00000000000
+    assign \mul_pipe2_mul_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \mul_pipe2_mul_op__imm_data__imm_ok 1'0
+    assign \mul_pipe2_mul_op__rc__rc 1'0
+    assign \mul_pipe2_mul_op__rc__rc_ok 1'0
+    assign \mul_pipe2_mul_op__oe__oe 1'0
+    assign \mul_pipe2_mul_op__oe__oe_ok 1'0
+    assign \mul_pipe2_mul_op__invert_a 1'0
+    assign \mul_pipe2_mul_op__zero_a 1'0
+    assign \mul_pipe2_mul_op__invert_out 1'0
+    assign \mul_pipe2_mul_op__write_cr0 1'0
+    assign \mul_pipe2_mul_op__is_32bit 1'0
+    assign \mul_pipe2_mul_op__is_signed 1'0
+    assign \mul_pipe2_mul_op__insn 32'00000000000000000000000000000000
+    assign { \mul_pipe2_mul_op__insn \mul_pipe2_mul_op__is_signed \mul_pipe2_mul_op__is_32bit \mul_pipe2_mul_op__write_cr0 \mul_pipe2_mul_op__invert_out \mul_pipe2_mul_op__zero_a \mul_pipe2_mul_op__invert_a { \mul_pipe2_mul_op__oe__oe_ok \mul_pipe2_mul_op__oe__oe } { \mul_pipe2_mul_op__rc__rc_ok \mul_pipe2_mul_op__rc__rc } { \mul_pipe2_mul_op__imm_data__imm_ok \mul_pipe2_mul_op__imm_data__imm } \mul_pipe2_mul_op__fn_unit \mul_pipe2_mul_op__insn_type } { \mul_pipe1_mul_op__insn \mul_pipe1_mul_op__is_signed \mul_pipe1_mul_op__is_32bit \mul_pipe1_mul_op__write_cr0 \mul_pipe1_mul_op__invert_out \mul_pipe1_mul_op__zero_a \mul_pipe1_mul_op__invert_a { \mul_pipe1_mul_op__oe__oe_ok \mul_pipe1_mul_op__oe__oe } { \mul_pipe1_mul_op__rc__rc_ok \mul_pipe1_mul_op__rc__rc } { \mul_pipe1_mul_op__imm_data__imm_ok \mul_pipe1_mul_op__imm_data__imm } \mul_pipe1_mul_op__fn_unit \mul_pipe1_mul_op__insn_type }
     sync init
-      update \src_r0 64'0000000000000000000000000000000000000000000000000000000000000000
-    sync posedge \clk
-      update \src_r0 \src_r0$next
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
-  wire width 64 \src_r1
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
-  wire width 64 \src_r1$next
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
-  wire width 64 $102
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
-  cell $mux $103
-    parameter \WIDTH 64
-    connect \A \src_r1
-    connect \B \src_or_imm
-    connect \S \src_sel
-    connect \Y $102
   end
-  process $group_90
-    assign \alu_shift_rot0_rb 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \alu_shift_rot0_rb $102
+  process $group_18
+    assign \mul_pipe2_ra 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \mul_pipe2_ra \mul_pipe1_ra
     sync init
   end
-  process $group_91
-    assign \src_r1$next \src_r1
-    attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
-    switch { \src_sel }
-      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
-      case 1'1
-        assign \src_r1$next \src_or_imm
-    end
+  process $group_19
+    assign \mul_pipe2_rb 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \mul_pipe2_rb \mul_pipe1_rb
     sync init
-      update \src_r1 64'0000000000000000000000000000000000000000000000000000000000000000
-    sync posedge \clk
-      update \src_r1 \src_r1$next
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
-  wire width 64 \src_r2
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
-  wire width 64 \src_r2$next
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
-  wire width 64 $104
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
-  cell $mux $105
-    parameter \WIDTH 64
-    connect \A \src_r2
-    connect \B \src3_i
-    connect \S \src_l_q_src [2]
-    connect \Y $104
   end
-  process $group_92
-    assign \alu_shift_rot0_rc 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \alu_shift_rot0_rc $104
+  process $group_20
+    assign \mul_pipe2_xer_so 1'0
+    assign \mul_pipe2_xer_so \mul_pipe1_xer_so
     sync init
   end
-  process $group_93
-    assign \src_r2$next \src_r2
-    attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
-    switch { \src_l_q_src [2] }
-      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
-      case 1'1
-        assign \src_r2$next \src3_i
-    end
+  process $group_21
+    assign \mul_pipe2_neg_res 1'0
+    assign \mul_pipe2_neg_res \mul_pipe1_neg_res
     sync init
-      update \src_r2 64'0000000000000000000000000000000000000000000000000000000000000000
-    sync posedge \clk
-      update \src_r2 \src_r2$next
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
-  wire width 2 \src_r3
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
-  wire width 2 \src_r3$next
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
-  wire width 2 $106
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
-  cell $mux $107
-    parameter \WIDTH 2
-    connect \A \src_r3
-    connect \B \src4_i
-    connect \S \src_l_q_src [3]
-    connect \Y $106
+  process $group_22
+    assign \mul_pipe2_neg_res32 1'0
+    assign \mul_pipe2_neg_res32 \mul_pipe1_neg_res32
+    sync init
   end
-  process $group_94
-    assign \alu_shift_rot0_xer_ca$1 2'00
-    assign \alu_shift_rot0_xer_ca$1 $106
+  process $group_23
+    assign \mul_pipe3_p_valid_i 1'0
+    assign \mul_pipe3_p_valid_i \mul_pipe2_n_valid_o
     sync init
   end
-  process $group_95
-    assign \src_r3$next \src_r3
-    attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
-    switch { \src_l_q_src [3] }
-      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
-      case 1'1
-        assign \src_r3$next \src4_i
-    end
+  process $group_24
+    assign \mul_pipe2_n_ready_i 1'0
+    assign \mul_pipe2_n_ready_i \mul_pipe3_p_ready_o
     sync init
-      update \src_r3 2'00
-    sync posedge \clk
-      update \src_r3 \src_r3$next
   end
-  process $group_96
-    assign \alu_shift_rot0_p_valid_i 1'0
-    assign \alu_shift_rot0_p_valid_i \alui_l_q_alui
+  process $group_25
+    assign \mul_pipe3_muxid 2'00
+    assign \mul_pipe3_muxid \mul_pipe2_muxid$21
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:329"
-  wire width 1 $108
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:329"
-  cell $and $109
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \alu_shift_rot0_p_ready_o
-    connect \B \alui_l_q_alui
-    connect \Y $108
-  end
-  process $group_97
-    assign \alui_l_r_alui$next \alui_l_r_alui
-    assign \alui_l_r_alui$next $108
-    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
-      case 1'1
-        assign \alui_l_r_alui$next 1'1
-    end
+  process $group_26
+    assign \mul_pipe3_mul_op__insn_type 7'0000000
+    assign \mul_pipe3_mul_op__fn_unit 11'00000000000
+    assign \mul_pipe3_mul_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \mul_pipe3_mul_op__imm_data__imm_ok 1'0
+    assign \mul_pipe3_mul_op__rc__rc 1'0
+    assign \mul_pipe3_mul_op__rc__rc_ok 1'0
+    assign \mul_pipe3_mul_op__oe__oe 1'0
+    assign \mul_pipe3_mul_op__oe__oe_ok 1'0
+    assign \mul_pipe3_mul_op__invert_a 1'0
+    assign \mul_pipe3_mul_op__zero_a 1'0
+    assign \mul_pipe3_mul_op__invert_out 1'0
+    assign \mul_pipe3_mul_op__write_cr0 1'0
+    assign \mul_pipe3_mul_op__is_32bit 1'0
+    assign \mul_pipe3_mul_op__is_signed 1'0
+    assign \mul_pipe3_mul_op__insn 32'00000000000000000000000000000000
+    assign { \mul_pipe3_mul_op__insn \mul_pipe3_mul_op__is_signed \mul_pipe3_mul_op__is_32bit \mul_pipe3_mul_op__write_cr0 \mul_pipe3_mul_op__invert_out \mul_pipe3_mul_op__zero_a \mul_pipe3_mul_op__invert_a { \mul_pipe3_mul_op__oe__oe_ok \mul_pipe3_mul_op__oe__oe } { \mul_pipe3_mul_op__rc__rc_ok \mul_pipe3_mul_op__rc__rc } { \mul_pipe3_mul_op__imm_data__imm_ok \mul_pipe3_mul_op__imm_data__imm } \mul_pipe3_mul_op__fn_unit \mul_pipe3_mul_op__insn_type } { \mul_pipe2_mul_op__insn$36 \mul_pipe2_mul_op__is_signed$35 \mul_pipe2_mul_op__is_32bit$34 \mul_pipe2_mul_op__write_cr0$33 \mul_pipe2_mul_op__invert_out$32 \mul_pipe2_mul_op__zero_a$31 \mul_pipe2_mul_op__invert_a$30 { \mul_pipe2_mul_op__oe__oe_ok$29 \mul_pipe2_mul_op__oe__oe$28 } { \mul_pipe2_mul_op__rc__rc_ok$27 \mul_pipe2_mul_op__rc__rc$26 } { \mul_pipe2_mul_op__imm_data__imm_ok$25 \mul_pipe2_mul_op__imm_data__imm$24 } \mul_pipe2_mul_op__fn_unit$23 \mul_pipe2_mul_op__insn_type$22 }
     sync init
-      update \alui_l_r_alui 1'1
-    sync posedge \clk
-      update \alui_l_r_alui \alui_l_r_alui$next
   end
-  process $group_98
-    assign \alui_l_s_alui 1'0
-    assign \alui_l_s_alui \all_rd_pulse
+  process $group_41
+    assign \mul_pipe3_o 129'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
+    assign \mul_pipe3_o \mul_pipe2_o
     sync init
   end
-  process $group_99
-    assign \alu_shift_rot0_n_ready_i 1'0
-    assign \alu_shift_rot0_n_ready_i \alu_l_q_alu
+  process $group_42
+    assign \mul_pipe3_xer_so 1'0
+    assign \mul_pipe3_xer_so \mul_pipe2_xer_so$37
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:336"
-  wire width 1 $110
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:336"
-  cell $and $111
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \alu_shift_rot0_n_valid_o
-    connect \B \alu_l_q_alu
-    connect \Y $110
-  end
-  process $group_100
-    assign \alu_l_r_alu$next \alu_l_r_alu
-    assign \alu_l_r_alu$next $110
-    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
-      case 1'1
-        assign \alu_l_r_alu$next 1'1
-    end
+  process $group_43
+    assign \mul_pipe3_neg_res 1'0
+    assign \mul_pipe3_neg_res \mul_pipe2_neg_res$38
     sync init
-      update \alu_l_r_alu 1'1
-    sync posedge \clk
-      update \alu_l_r_alu \alu_l_r_alu$next
   end
-  process $group_101
-    assign \alu_l_s_alu 1'0
-    assign \alu_l_s_alu \all_rd_pulse
+  process $group_44
+    assign \mul_pipe3_neg_res32 1'0
+    assign \mul_pipe3_neg_res32 \mul_pipe2_neg_res32$39
     sync init
   end
-  process $group_102
-    assign \cu_busy_o 1'0
-    assign \cu_busy_o \opc_l_q_opc
+  process $group_45
+    assign \mul_pipe1_p_valid_i 1'0
+    assign \mul_pipe1_p_valid_i \p_valid_i
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
-  wire width 4 $112
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
-  cell $and $113
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 4
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 4
-    parameter \Y_WIDTH 4
-    connect \A \src_l_q_src
-    connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o }
-    connect \Y $112
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:172"
-  wire width 1 $114
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:172"
-  cell $not $115
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \oper_r__imm_data__imm_ok
-    connect \Y $114
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
-  wire width 4 $116
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
-  cell $and $117
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 4
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 4
-    parameter \Y_WIDTH 4
-    connect \A $112
-    connect \B { 1'1 1'1 $114 1'1 }
-    connect \Y $116
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
-  wire width 4 $118
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
-  cell $not $119
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 4
-    parameter \Y_WIDTH 4
-    connect \A \cu_rdmaskn_i
-    connect \Y $118
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
-  wire width 4 $120
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
-  cell $and $121
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 4
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 4
-    parameter \Y_WIDTH 4
-    connect \A $116
-    connect \B $118
-    connect \Y $120
+  process $group_46
+    assign \p_ready_o 1'0
+    assign \p_ready_o \mul_pipe1_p_ready_o
+    sync init
   end
-  process $group_103
-    assign \cu_rd__rel_o 4'0000
-    assign \cu_rd__rel_o $120
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
+  wire width 2 \muxid
+  process $group_47
+    assign \mul_pipe1_muxid$2 2'00
+    assign \mul_pipe1_muxid$2 \muxid
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:101"
-  wire width 1 \cu_shadown_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352"
-  wire width 1 $122
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352"
-  cell $and $123
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \cu_busy_o
-    connect \B \cu_shadown_i
-    connect \Y $122
+  process $group_48
+    assign \mul_pipe1_mul_op__insn_type$3 7'0000000
+    assign \mul_pipe1_mul_op__fn_unit$4 11'00000000000
+    assign \mul_pipe1_mul_op__imm_data__imm$5 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \mul_pipe1_mul_op__imm_data__imm_ok$6 1'0
+    assign \mul_pipe1_mul_op__rc__rc$7 1'0
+    assign \mul_pipe1_mul_op__rc__rc_ok$8 1'0
+    assign \mul_pipe1_mul_op__oe__oe$9 1'0
+    assign \mul_pipe1_mul_op__oe__oe_ok$10 1'0
+    assign \mul_pipe1_mul_op__invert_a$11 1'0
+    assign \mul_pipe1_mul_op__zero_a$12 1'0
+    assign \mul_pipe1_mul_op__invert_out$13 1'0
+    assign \mul_pipe1_mul_op__write_cr0$14 1'0
+    assign \mul_pipe1_mul_op__is_32bit$15 1'0
+    assign \mul_pipe1_mul_op__is_signed$16 1'0
+    assign \mul_pipe1_mul_op__insn$17 32'00000000000000000000000000000000
+    assign { \mul_pipe1_mul_op__insn$17 \mul_pipe1_mul_op__is_signed$16 \mul_pipe1_mul_op__is_32bit$15 \mul_pipe1_mul_op__write_cr0$14 \mul_pipe1_mul_op__invert_out$13 \mul_pipe1_mul_op__zero_a$12 \mul_pipe1_mul_op__invert_a$11 { \mul_pipe1_mul_op__oe__oe_ok$10 \mul_pipe1_mul_op__oe__oe$9 } { \mul_pipe1_mul_op__rc__rc_ok$8 \mul_pipe1_mul_op__rc__rc$7 } { \mul_pipe1_mul_op__imm_data__imm_ok$6 \mul_pipe1_mul_op__imm_data__imm$5 } \mul_pipe1_mul_op__fn_unit$4 \mul_pipe1_mul_op__insn_type$3 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__invert_out \mul_op__zero_a \mul_op__invert_a { \mul_op__oe__oe_ok \mul_op__oe__oe } { \mul_op__rc__rc_ok \mul_op__rc__rc } { \mul_op__imm_data__imm_ok \mul_op__imm_data__imm } \mul_op__fn_unit \mul_op__insn_type }
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352"
-  wire width 1 $124
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352"
-  cell $and $125
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \cu_busy_o
-    connect \B \cu_shadown_i
-    connect \Y $124
+  process $group_63
+    assign \mul_pipe1_ra$18 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \mul_pipe1_ra$18 \ra
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352"
-  wire width 1 $126
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352"
-  cell $and $127
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \cu_busy_o
-    connect \B \cu_shadown_i
-    connect \Y $126
+  process $group_64
+    assign \mul_pipe1_rb$19 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \mul_pipe1_rb$19 \rb
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:353"
-  wire width 3 $128
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:353"
-  cell $and $129
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 3
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 3
-    parameter \Y_WIDTH 3
-    connect \A \req_l_q_req
-    connect \B { $122 $124 $126 }
-    connect \Y $128
+  process $group_65
+    assign \mul_pipe1_xer_so$20 1'0
+    assign \mul_pipe1_xer_so$20 \xer_so$1
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:353"
-  wire width 3 $130
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:353"
-  cell $and $131
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 3
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 3
-    parameter \Y_WIDTH 3
-    connect \A $128
-    connect \B \cu_wrmask_o
-    connect \Y $130
+  process $group_66
+    assign \n_valid_o 1'0
+    assign \n_valid_o \mul_pipe3_n_valid_o
+    sync init
   end
-  process $group_104
-    assign \cu_wr__rel_o 3'000
-    assign \cu_wr__rel_o $130
+  process $group_67
+    assign \mul_pipe3_n_ready_i 1'0
+    assign \mul_pipe3_n_ready_i \n_ready_i
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
-  wire width 1 $132
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
-  cell $and $133
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \cu_wr__go_i [0]
-    connect \B \cu_busy_o
-    connect \Y $132
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
+  wire width 2 \muxid$58
+  process $group_68
+    assign \muxid$58 2'00
+    assign \muxid$58 \mul_pipe3_muxid$40
+    sync init
   end
-  process $group_105
-    assign \dest1_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
-    switch { $132 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
-      case 1'1
-        assign \dest1_o { \data_r0__o_ok \data_r0__o } [63:0]
-    end
+  attribute \enum_base_type "MicrOp"
+  attribute \enum_value_0000000 "OP_ILLEGAL"
+  attribute \enum_value_0000001 "OP_NOP"
+  attribute \enum_value_0000010 "OP_ADD"
+  attribute \enum_value_0000011 "OP_ADDPCIS"
+  attribute \enum_value_0000100 "OP_AND"
+  attribute \enum_value_0000101 "OP_ATTN"
+  attribute \enum_value_0000110 "OP_B"
+  attribute \enum_value_0000111 "OP_BC"
+  attribute \enum_value_0001000 "OP_BCREG"
+  attribute \enum_value_0001001 "OP_BPERM"
+  attribute \enum_value_0001010 "OP_CMP"
+  attribute \enum_value_0001011 "OP_CMPB"
+  attribute \enum_value_0001100 "OP_CMPEQB"
+  attribute \enum_value_0001101 "OP_CMPRB"
+  attribute \enum_value_0001110 "OP_CNTZ"
+  attribute \enum_value_0001111 "OP_CRAND"
+  attribute \enum_value_0010000 "OP_CRANDC"
+  attribute \enum_value_0010001 "OP_CREQV"
+  attribute \enum_value_0010010 "OP_CRNAND"
+  attribute \enum_value_0010011 "OP_CRNOR"
+  attribute \enum_value_0010100 "OP_CROR"
+  attribute \enum_value_0010101 "OP_CRORC"
+  attribute \enum_value_0010110 "OP_CRXOR"
+  attribute \enum_value_0010111 "OP_DARN"
+  attribute \enum_value_0011000 "OP_DCBF"
+  attribute \enum_value_0011001 "OP_DCBST"
+  attribute \enum_value_0011010 "OP_DCBT"
+  attribute \enum_value_0011011 "OP_DCBTST"
+  attribute \enum_value_0011100 "OP_DCBZ"
+  attribute \enum_value_0011101 "OP_DIV"
+  attribute \enum_value_0011110 "OP_DIVE"
+  attribute \enum_value_0011111 "OP_EXTS"
+  attribute \enum_value_0100000 "OP_EXTSWSLI"
+  attribute \enum_value_0100001 "OP_ICBI"
+  attribute \enum_value_0100010 "OP_ICBT"
+  attribute \enum_value_0100011 "OP_ISEL"
+  attribute \enum_value_0100100 "OP_ISYNC"
+  attribute \enum_value_0100101 "OP_LOAD"
+  attribute \enum_value_0100110 "OP_STORE"
+  attribute \enum_value_0100111 "OP_MADDHD"
+  attribute \enum_value_0101000 "OP_MADDHDU"
+  attribute \enum_value_0101001 "OP_MADDLD"
+  attribute \enum_value_0101010 "OP_MCRF"
+  attribute \enum_value_0101011 "OP_MCRXR"
+  attribute \enum_value_0101100 "OP_MCRXRX"
+  attribute \enum_value_0101101 "OP_MFCR"
+  attribute \enum_value_0101110 "OP_MFSPR"
+  attribute \enum_value_0101111 "OP_MOD"
+  attribute \enum_value_0110000 "OP_MTCRF"
+  attribute \enum_value_0110001 "OP_MTSPR"
+  attribute \enum_value_0110010 "OP_MUL_L64"
+  attribute \enum_value_0110011 "OP_MUL_H64"
+  attribute \enum_value_0110100 "OP_MUL_H32"
+  attribute \enum_value_0110101 "OP_OR"
+  attribute \enum_value_0110110 "OP_POPCNT"
+  attribute \enum_value_0110111 "OP_PRTY"
+  attribute \enum_value_0111000 "OP_RLC"
+  attribute \enum_value_0111001 "OP_RLCL"
+  attribute \enum_value_0111010 "OP_RLCR"
+  attribute \enum_value_0111011 "OP_SETB"
+  attribute \enum_value_0111100 "OP_SHL"
+  attribute \enum_value_0111101 "OP_SHR"
+  attribute \enum_value_0111110 "OP_SYNC"
+  attribute \enum_value_0111111 "OP_TRAP"
+  attribute \enum_value_1000011 "OP_XOR"
+  attribute \enum_value_1000100 "OP_SIM_CONFIG"
+  attribute \enum_value_1000101 "OP_CROP"
+  attribute \enum_value_1000110 "OP_RFID"
+  attribute \enum_value_1000111 "OP_MFMSR"
+  attribute \enum_value_1001000 "OP_MTMSRD"
+  attribute \enum_value_1001001 "OP_SC"
+  attribute \enum_value_1001010 "OP_MTMSR"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 \mul_op__insn_type$59
+  attribute \enum_base_type "Function"
+  attribute \enum_value_00000000000 "NONE"
+  attribute \enum_value_00000000010 "ALU"
+  attribute \enum_value_00000000100 "LDST"
+  attribute \enum_value_00000001000 "SHIFT_ROT"
+  attribute \enum_value_00000010000 "LOGICAL"
+  attribute \enum_value_00000100000 "BRANCH"
+  attribute \enum_value_00001000000 "CR"
+  attribute \enum_value_00010000000 "TRAP"
+  attribute \enum_value_00100000000 "MUL"
+  attribute \enum_value_01000000000 "DIV"
+  attribute \enum_value_10000000000 "SPR"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 \mul_op__fn_unit$60
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 \mul_op__imm_data__imm$61
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_op__imm_data__imm_ok$62
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_op__rc__rc$63
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_op__rc__rc_ok$64
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_op__oe__oe$65
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_op__oe__oe_ok$66
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_op__invert_a$67
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_op__zero_a$68
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_op__invert_out$69
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_op__write_cr0$70
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_op__is_32bit$71
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \mul_op__is_signed$72
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \mul_op__insn$73
+  process $group_69
+    assign \mul_op__insn_type$59 7'0000000
+    assign \mul_op__fn_unit$60 11'00000000000
+    assign \mul_op__imm_data__imm$61 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \mul_op__imm_data__imm_ok$62 1'0
+    assign \mul_op__rc__rc$63 1'0
+    assign \mul_op__rc__rc_ok$64 1'0
+    assign \mul_op__oe__oe$65 1'0
+    assign \mul_op__oe__oe_ok$66 1'0
+    assign \mul_op__invert_a$67 1'0
+    assign \mul_op__zero_a$68 1'0
+    assign \mul_op__invert_out$69 1'0
+    assign \mul_op__write_cr0$70 1'0
+    assign \mul_op__is_32bit$71 1'0
+    assign \mul_op__is_signed$72 1'0
+    assign \mul_op__insn$73 32'00000000000000000000000000000000
+    assign { \mul_op__insn$73 \mul_op__is_signed$72 \mul_op__is_32bit$71 \mul_op__write_cr0$70 \mul_op__invert_out$69 \mul_op__zero_a$68 \mul_op__invert_a$67 { \mul_op__oe__oe_ok$66 \mul_op__oe__oe$65 } { \mul_op__rc__rc_ok$64 \mul_op__rc__rc$63 } { \mul_op__imm_data__imm_ok$62 \mul_op__imm_data__imm$61 } \mul_op__fn_unit$60 \mul_op__insn_type$59 } { \mul_pipe3_mul_op__insn$55 \mul_pipe3_mul_op__is_signed$54 \mul_pipe3_mul_op__is_32bit$53 \mul_pipe3_mul_op__write_cr0$52 \mul_pipe3_mul_op__invert_out$51 \mul_pipe3_mul_op__zero_a$50 \mul_pipe3_mul_op__invert_a$49 { \mul_pipe3_mul_op__oe__oe_ok$48 \mul_pipe3_mul_op__oe__oe$47 } { \mul_pipe3_mul_op__rc__rc_ok$46 \mul_pipe3_mul_op__rc__rc$45 } { \mul_pipe3_mul_op__imm_data__imm_ok$44 \mul_pipe3_mul_op__imm_data__imm$43 } \mul_pipe3_mul_op__fn_unit$42 \mul_pipe3_mul_op__insn_type$41 }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
-  wire width 1 $134
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
-  cell $and $135
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \cu_wr__go_i [1]
-    connect \B \cu_busy_o
-    connect \Y $134
+  process $group_84
+    assign \o 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \o_ok 1'0
+    assign { \o_ok \o } { \mul_pipe3_o_ok \mul_pipe3_o$56 }
+    sync init
   end
-  process $group_106
-    assign \dest2_o 4'0000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
-    switch { $134 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
-      case 1'1
-        assign \dest2_o { \data_r1__cr_a_ok \data_r1__cr_a } [3:0]
-    end
+  process $group_86
+    assign \cr_a 4'0000
+    assign \cr_a_ok 1'0
+    assign { \cr_a_ok \cr_a } { \mul_pipe3_cr_a_ok \mul_pipe3_cr_a }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
-  wire width 1 $136
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
-  cell $and $137
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \cu_wr__go_i [2]
-    connect \B \cu_busy_o
-    connect \Y $136
+  process $group_88
+    assign \xer_ov 2'00
+    assign \xer_ov_ok 1'0
+    assign { \xer_ov_ok \xer_ov } { \mul_pipe3_xer_ov_ok \mul_pipe3_xer_ov }
+    sync init
   end
-  process $group_107
-    assign \dest3_o 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
-    switch { $136 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
-      case 1'1
-        assign \dest3_o { \data_r2__xer_ca_ok \data_r2__xer_ca } [1:0]
-    end
+  process $group_90
+    assign \xer_so 1'0
+    assign \xer_so_ok 1'0
+    assign { \xer_so_ok \xer_so } { \mul_pipe3_xer_so_ok \mul_pipe3_xer_so$57 }
     sync init
   end
-  connect \cu_go_die_i 1'0
-  connect \cu_shadown_i 1'1
+  connect \muxid 2'00
 end
 attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.opc_l"
-module \opc_l$102
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
+attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.src_l"
+module \src_l$97
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
-  wire width 1 input 2 \s_opc
+  wire width 3 input 2 \s_src
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
-  wire width 1 input 3 \r_opc
+  wire width 3 input 3 \r_src
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
-  wire width 1 output 4 \q_opc
+  wire width 3 output 4 \q_src
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
-  wire width 1 \q_int
+  wire width 3 \q_int
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
-  wire width 1 \q_int$next
+  wire width 3 \q_int$next
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
-  wire width 1 $1
+  wire width 3 $1
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
   cell $not $2
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \r_opc
+    parameter \A_WIDTH 3
+    parameter \Y_WIDTH 3
+    connect \A \r_src
     connect \Y $1
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
-  wire width 1 $3
+  wire width 3 $3
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
   cell $and $4
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
+    parameter \A_WIDTH 3
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
+    parameter \B_WIDTH 3
+    parameter \Y_WIDTH 3
     connect \A \q_int
     connect \B $1
     connect \Y $3
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
-  wire width 1 $5
+  wire width 3 $5
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
   cell $or $6
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
+    parameter \A_WIDTH 3
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
+    parameter \B_WIDTH 3
+    parameter \Y_WIDTH 3
     connect \A $3
-    connect \B \s_opc
+    connect \B \s_src
     connect \Y $5
   end
   process $group_0
     assign \q_int$next \q_int
     assign \q_int$next $5
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
-        assign \q_int$next 1'0
+        assign \q_int$next 3'000
     end
     sync init
-      update \q_int 1'0
-    sync posedge \clk
+      update \q_int 3'000
+    sync posedge \coresync_clk
       update \q_int \q_int$next
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
-  wire width 1 $7
+  wire width 3 $7
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
   cell $not $8
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \r_opc
+    parameter \A_WIDTH 3
+    parameter \Y_WIDTH 3
+    connect \A \r_src
     connect \Y $7
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
-  wire width 1 $9
+  wire width 3 $9
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
   cell $and $10
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
+    parameter \A_WIDTH 3
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
+    parameter \B_WIDTH 3
+    parameter \Y_WIDTH 3
     connect \A \q_int
     connect \B $7
     connect \Y $9
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
-  wire width 1 $11
+  wire width 3 $11
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
   cell $or $12
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
+    parameter \A_WIDTH 3
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
+    parameter \B_WIDTH 3
+    parameter \Y_WIDTH 3
     connect \A $9
-    connect \B \s_opc
+    connect \B \s_src
     connect \Y $11
   end
   process $group_1
-    assign \q_opc 1'0
-    assign \q_opc $11
+    assign \q_src 3'000
+    assign \q_src $11
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
-  wire width 1 \qn_opc
+  wire width 3 \qn_src
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
-  wire width 1 $13
+  wire width 3 $13
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
   cell $not $14
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \q_opc
+    parameter \A_WIDTH 3
+    parameter \Y_WIDTH 3
+    connect \A \q_src
     connect \Y $13
   end
   process $group_2
-    assign \qn_opc 1'0
-    assign \qn_opc $13
+    assign \qn_src 3'000
+    assign \qn_src $13
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62"
-  wire width 1 \qlq_opc
+  wire width 3 \qlq_src
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
-  wire width 1 $15
+  wire width 3 $15
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
   cell $or $16
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
+    parameter \A_WIDTH 3
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \q_opc
+    parameter \B_WIDTH 3
+    parameter \Y_WIDTH 3
+    connect \A \q_src
     connect \B \q_int
     connect \Y $15
   end
   process $group_3
-    assign \qlq_opc 1'0
-    assign \qlq_opc $15
+    assign \qlq_src 3'000
+    assign \qlq_src $15
     sync init
   end
 end
 attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.src_l"
-module \src_l$103
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
+attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.opc_l"
+module \opc_l$98
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
-  wire width 3 input 2 \s_src
+  wire width 1 input 2 \s_opc
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
-  wire width 3 input 3 \r_src
+  wire width 1 input 3 \r_opc
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
-  wire width 3 output 4 \q_src
+  wire width 1 output 4 \q_opc
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
-  wire width 3 \q_int
+  wire width 1 \q_int
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
-  wire width 3 \q_int$next
+  wire width 1 \q_int$next
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
-  wire width 3 $1
+  wire width 1 $1
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
   cell $not $2
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 3
-    parameter \Y_WIDTH 3
-    connect \A \r_src
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \r_opc
     connect \Y $1
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
-  wire width 3 $3
+  wire width 1 $3
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
   cell $and $4
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 3
+    parameter \A_WIDTH 1
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 3
-    parameter \Y_WIDTH 3
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
     connect \A \q_int
     connect \B $1
     connect \Y $3
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
-  wire width 3 $5
+  wire width 1 $5
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
   cell $or $6
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 3
+    parameter \A_WIDTH 1
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 3
-    parameter \Y_WIDTH 3
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
     connect \A $3
-    connect \B \s_src
+    connect \B \s_opc
     connect \Y $5
   end
   process $group_0
     assign \q_int$next \q_int
     assign \q_int$next $5
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
-        assign \q_int$next 3'000
+        assign \q_int$next 1'0
     end
     sync init
-      update \q_int 3'000
-    sync posedge \clk
+      update \q_int 1'0
+    sync posedge \coresync_clk
       update \q_int \q_int$next
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
-  wire width 3 $7
+  wire width 1 $7
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
   cell $not $8
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 3
-    parameter \Y_WIDTH 3
-    connect \A \r_src
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \r_opc
     connect \Y $7
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
-  wire width 3 $9
+  wire width 1 $9
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
   cell $and $10
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 3
+    parameter \A_WIDTH 1
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 3
-    parameter \Y_WIDTH 3
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
     connect \A \q_int
     connect \B $7
     connect \Y $9
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
-  wire width 3 $11
+  wire width 1 $11
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
   cell $or $12
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 3
+    parameter \A_WIDTH 1
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 3
-    parameter \Y_WIDTH 3
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
     connect \A $9
-    connect \B \s_src
+    connect \B \s_opc
     connect \Y $11
   end
   process $group_1
-    assign \q_src 3'000
-    assign \q_src $11
+    assign \q_opc 1'0
+    assign \q_opc $11
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
-  wire width 3 \qn_src
+  wire width 1 \qn_opc
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
-  wire width 3 $13
+  wire width 1 $13
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
   cell $not $14
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 3
-    parameter \Y_WIDTH 3
-    connect \A \q_src
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \q_opc
     connect \Y $13
   end
   process $group_2
-    assign \qn_src 3'000
-    assign \qn_src $13
+    assign \qn_opc 1'0
+    assign \qn_opc $13
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62"
-  wire width 3 \qlq_src
+  wire width 1 \qlq_opc
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
-  wire width 3 $15
+  wire width 1 $15
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
   cell $or $16
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 3
+    parameter \A_WIDTH 1
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 3
-    parameter \Y_WIDTH 3
-    connect \A \q_src
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \q_opc
     connect \B \q_int
     connect \Y $15
   end
   process $group_3
-    assign \qlq_src 3'000
-    assign \qlq_src $15
+    assign \qlq_opc 1'0
+    assign \qlq_opc $15
     sync init
   end
 end
 attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.alu_l"
-module \alu_l$104
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
+attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.req_l"
+module \req_l$99
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
+  wire width 4 output 2 \q_req
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
-  wire width 1 input 2 \s_alu
+  wire width 4 input 3 \s_req
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
-  wire width 1 input 3 \r_alu
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
-  wire width 1 output 4 \q_alu
+  wire width 4 input 4 \r_req
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
-  wire width 1 \q_int
+  wire width 4 \q_int
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
-  wire width 1 \q_int$next
+  wire width 4 \q_int$next
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
-  wire width 1 $1
+  wire width 4 $1
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
   cell $not $2
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \r_alu
+    parameter \A_WIDTH 4
+    parameter \Y_WIDTH 4
+    connect \A \r_req
     connect \Y $1
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
-  wire width 1 $3
+  wire width 4 $3
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
   cell $and $4
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
+    parameter \A_WIDTH 4
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
+    parameter \B_WIDTH 4
+    parameter \Y_WIDTH 4
     connect \A \q_int
     connect \B $1
     connect \Y $3
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
-  wire width 1 $5
+  wire width 4 $5
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
   cell $or $6
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
+    parameter \A_WIDTH 4
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
+    parameter \B_WIDTH 4
+    parameter \Y_WIDTH 4
     connect \A $3
-    connect \B \s_alu
+    connect \B \s_req
     connect \Y $5
   end
   process $group_0
     assign \q_int$next \q_int
     assign \q_int$next $5
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
-        assign \q_int$next 1'0
+        assign \q_int$next 4'0000
     end
     sync init
-      update \q_int 1'0
-    sync posedge \clk
+      update \q_int 4'0000
+    sync posedge \coresync_clk
       update \q_int \q_int$next
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
-  wire width 1 $7
+  wire width 4 $7
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
   cell $not $8
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \r_alu
+    parameter \A_WIDTH 4
+    parameter \Y_WIDTH 4
+    connect \A \r_req
     connect \Y $7
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
-  wire width 1 $9
+  wire width 4 $9
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
   cell $and $10
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
+    parameter \A_WIDTH 4
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
+    parameter \B_WIDTH 4
+    parameter \Y_WIDTH 4
     connect \A \q_int
     connect \B $7
     connect \Y $9
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
-  wire width 1 $11
+  wire width 4 $11
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
   cell $or $12
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
+    parameter \A_WIDTH 4
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
+    parameter \B_WIDTH 4
+    parameter \Y_WIDTH 4
     connect \A $9
-    connect \B \s_alu
+    connect \B \s_req
     connect \Y $11
   end
   process $group_1
-    assign \q_alu 1'0
-    assign \q_alu $11
+    assign \q_req 4'0000
+    assign \q_req $11
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
-  wire width 1 \qn_alu
+  wire width 4 \qn_req
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
-  wire width 1 $13
+  wire width 4 $13
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
   cell $not $14
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \q_alu
+    parameter \A_WIDTH 4
+    parameter \Y_WIDTH 4
+    connect \A \q_req
     connect \Y $13
   end
   process $group_2
-    assign \qn_alu 1'0
-    assign \qn_alu $13
+    assign \qn_req 4'0000
+    assign \qn_req $13
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62"
-  wire width 1 \qlq_alu
+  wire width 4 \qlq_req
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
-  wire width 1 $15
+  wire width 4 $15
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
   cell $or $16
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
+    parameter \A_WIDTH 4
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \q_alu
+    parameter \B_WIDTH 4
+    parameter \Y_WIDTH 4
+    connect \A \q_req
     connect \B \q_int
     connect \Y $15
   end
   process $group_3
-    assign \qlq_alu 1'0
-    assign \qlq_alu $15
+    assign \qlq_req 4'0000
+    assign \qlq_req $15
     sync init
   end
 end
 attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.adr_l"
-module \adr_l
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
+attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.rst_l"
+module \rst_l$100
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
-  wire width 1 input 2 \s_adr
+  wire width 1 input 2 \s_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
-  wire width 1 input 3 \r_adr
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
-  wire width 1 output 4 \q_adr
+  wire width 1 input 3 \r_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
   wire width 1 \q_int
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
@@ -108145,7 +108919,7 @@ module \adr_l
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \r_adr
+    connect \A \r_rst
     connect \Y $1
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
@@ -108171,22 +108945,24 @@ module \adr_l
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A $3
-    connect \B \s_adr
+    connect \B \s_rst
     connect \Y $5
   end
   process $group_0
     assign \q_int$next \q_int
     assign \q_int$next $5
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \q_int$next 1'0
     end
     sync init
       update \q_int 1'0
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \q_int \q_int$next
   end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
+  wire width 1 \q_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
   wire width 1 $7
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
@@ -108194,7 +108970,7 @@ module \adr_l
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \r_adr
+    connect \A \r_rst
     connect \Y $7
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
@@ -108220,16 +108996,16 @@ module \adr_l
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A $9
-    connect \B \s_adr
+    connect \B \s_rst
     connect \Y $11
   end
   process $group_1
-    assign \q_adr 1'0
-    assign \q_adr $11
+    assign \q_rst 1'0
+    assign \q_rst $11
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
-  wire width 1 \qn_adr
+  wire width 1 \qn_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
   wire width 1 $13
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
@@ -108237,16 +109013,16 @@ module \adr_l
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \q_adr
+    connect \A \q_rst
     connect \Y $13
   end
   process $group_2
-    assign \qn_adr 1'0
-    assign \qn_adr $13
+    assign \qn_rst 1'0
+    assign \qn_rst $13
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62"
-  wire width 1 \qlq_adr
+  wire width 1 \qlq_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
   wire width 1 $15
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
@@ -108256,29 +109032,29 @@ module \adr_l
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \q_adr
+    connect \A \q_rst
     connect \B \q_int
     connect \Y $15
   end
   process $group_3
-    assign \qlq_adr 1'0
-    assign \qlq_adr $15
+    assign \qlq_rst 1'0
+    assign \qlq_rst $15
     sync init
   end
 end
 attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.lod_l"
-module \lod_l
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
+attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.rok_l"
+module \rok_l$101
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
+  wire width 1 output 2 \q_rdok
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
-  wire width 1 input 2 \s_lod
+  wire width 1 input 3 \s_rdok
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
-  wire width 1 input 3 \r_lod
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
-  wire width 1 output 4 \qn_lod
+  wire width 1 input 4 \r_rdok
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
   wire width 1 \q_int
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
@@ -108290,7 +109066,7 @@ module \lod_l
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \r_lod
+    connect \A \r_rdok
     connect \Y $1
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
@@ -108316,24 +109092,22 @@ module \lod_l
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A $3
-    connect \B \s_lod
+    connect \B \s_rdok
     connect \Y $5
   end
   process $group_0
     assign \q_int$next \q_int
     assign \q_int$next $5
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \q_int$next 1'0
     end
     sync init
       update \q_int 1'0
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \q_int \q_int$next
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
-  wire width 1 \q_lod
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
   wire width 1 $7
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
@@ -108341,7 +109115,7 @@ module \lod_l
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \r_lod
+    connect \A \r_rdok
     connect \Y $7
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
@@ -108367,14 +109141,16 @@ module \lod_l
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A $9
-    connect \B \s_lod
+    connect \B \s_rdok
     connect \Y $11
   end
   process $group_1
-    assign \q_lod 1'0
-    assign \q_lod $11
+    assign \q_rdok 1'0
+    assign \q_rdok $11
     sync init
   end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
+  wire width 1 \qn_rdok
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
   wire width 1 $13
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
@@ -108382,16 +109158,16 @@ module \lod_l
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \q_lod
+    connect \A \q_rdok
     connect \Y $13
   end
   process $group_2
-    assign \qn_lod 1'0
-    assign \qn_lod $13
+    assign \qn_rdok 1'0
+    assign \qn_rdok $13
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62"
-  wire width 1 \qlq_lod
+  wire width 1 \qlq_rdok
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
   wire width 1 $15
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
@@ -108401,29 +109177,29 @@ module \lod_l
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \q_lod
+    connect \A \q_rdok
     connect \B \q_int
     connect \Y $15
   end
   process $group_3
-    assign \qlq_lod 1'0
-    assign \qlq_lod $15
+    assign \qlq_rdok 1'0
+    assign \qlq_rdok $15
     sync init
   end
 end
 attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.sto_l"
-module \sto_l
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
-  wire width 1 input 2 \s_sto
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
-  wire width 1 input 3 \r_sto
+attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alui_l"
+module \alui_l$102
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
-  wire width 1 output 4 \q_sto
+  wire width 1 output 2 \q_alui
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+  wire width 1 input 3 \r_alui
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+  wire width 1 input 4 \s_alui
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
   wire width 1 \q_int
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
@@ -108435,7 +109211,7 @@ module \sto_l
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \r_sto
+    connect \A \r_alui
     connect \Y $1
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
@@ -108461,20 +109237,20 @@ module \sto_l
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A $3
-    connect \B \s_sto
+    connect \B \s_alui
     connect \Y $5
   end
   process $group_0
     assign \q_int$next \q_int
     assign \q_int$next $5
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \q_int$next 1'0
     end
     sync init
       update \q_int 1'0
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \q_int \q_int$next
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
@@ -108484,7 +109260,7 @@ module \sto_l
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \r_sto
+    connect \A \r_alui
     connect \Y $7
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
@@ -108510,16 +109286,16 @@ module \sto_l
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A $9
-    connect \B \s_sto
+    connect \B \s_alui
     connect \Y $11
   end
   process $group_1
-    assign \q_sto 1'0
-    assign \q_sto $11
+    assign \q_alui 1'0
+    assign \q_alui $11
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
-  wire width 1 \qn_sto
+  wire width 1 \qn_alui
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
   wire width 1 $13
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
@@ -108527,16 +109303,16 @@ module \sto_l
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \q_sto
+    connect \A \q_alui
     connect \Y $13
   end
   process $group_2
-    assign \qn_sto 1'0
-    assign \qn_sto $13
+    assign \qn_alui 1'0
+    assign \qn_alui $13
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62"
-  wire width 1 \qlq_sto
+  wire width 1 \qlq_alui
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
   wire width 1 $15
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
@@ -108546,29 +109322,29 @@ module \sto_l
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \q_sto
+    connect \A \q_alui
     connect \B \q_int
     connect \Y $15
   end
   process $group_3
-    assign \qlq_sto 1'0
-    assign \qlq_sto $15
+    assign \qlq_alui 1'0
+    assign \qlq_alui $15
     sync init
   end
 end
 attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.wri_l"
-module \wri_l
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
-  wire width 1 input 2 \s_wri
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
-  wire width 1 input 3 \r_wri
+attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_l"
+module \alu_l$103
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
-  wire width 1 output 4 \q_wri
+  wire width 1 output 2 \q_alu
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+  wire width 1 input 3 \r_alu
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+  wire width 1 input 4 \s_alu
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
   wire width 1 \q_int
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
@@ -108580,7 +109356,7 @@ module \wri_l
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \r_wri
+    connect \A \r_alu
     connect \Y $1
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
@@ -108606,20 +109382,20 @@ module \wri_l
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A $3
-    connect \B \s_wri
+    connect \B \s_alu
     connect \Y $5
   end
   process $group_0
     assign \q_int$next \q_int
     assign \q_int$next $5
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \q_int$next 1'0
     end
     sync init
       update \q_int 1'0
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \q_int \q_int$next
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
@@ -108629,7 +109405,7 @@ module \wri_l
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \r_wri
+    connect \A \r_alu
     connect \Y $7
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
@@ -108655,451 +109431,16 @@ module \wri_l
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A $9
-    connect \B \s_wri
-    connect \Y $11
-  end
-  process $group_1
-    assign \q_wri 1'0
-    assign \q_wri $11
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
-  wire width 1 \qn_wri
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
-  wire width 1 $13
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
-  cell $not $14
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \q_wri
-    connect \Y $13
-  end
-  process $group_2
-    assign \qn_wri 1'0
-    assign \qn_wri $13
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62"
-  wire width 1 \qlq_wri
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
-  wire width 1 $15
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
-  cell $or $16
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \q_wri
-    connect \B \q_int
-    connect \Y $15
-  end
-  process $group_3
-    assign \qlq_wri 1'0
-    assign \qlq_wri $15
-    sync init
-  end
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.upd_l"
-module \upd_l
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
-  wire width 1 input 2 \s_upd
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
-  wire width 1 input 3 \r_upd
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
-  wire width 1 output 4 \q_upd
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
-  wire width 1 \q_int
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
-  wire width 1 \q_int$next
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
-  wire width 1 $1
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
-  cell $not $2
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \r_upd
-    connect \Y $1
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
-  wire width 1 $3
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
-  cell $and $4
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \q_int
-    connect \B $1
-    connect \Y $3
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
-  wire width 1 $5
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
-  cell $or $6
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A $3
-    connect \B \s_upd
-    connect \Y $5
-  end
-  process $group_0
-    assign \q_int$next \q_int
-    assign \q_int$next $5
-    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
-      case 1'1
-        assign \q_int$next 1'0
-    end
-    sync init
-      update \q_int 1'0
-    sync posedge \clk
-      update \q_int \q_int$next
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
-  wire width 1 $7
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
-  cell $not $8
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \r_upd
-    connect \Y $7
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
-  wire width 1 $9
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
-  cell $and $10
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \q_int
-    connect \B $7
-    connect \Y $9
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
-  wire width 1 $11
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
-  cell $or $12
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A $9
-    connect \B \s_upd
-    connect \Y $11
-  end
-  process $group_1
-    assign \q_upd 1'0
-    assign \q_upd $11
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
-  wire width 1 \qn_upd
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
-  wire width 1 $13
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
-  cell $not $14
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \q_upd
-    connect \Y $13
-  end
-  process $group_2
-    assign \qn_upd 1'0
-    assign \qn_upd $13
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62"
-  wire width 1 \qlq_upd
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
-  wire width 1 $15
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
-  cell $or $16
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \q_upd
-    connect \B \q_int
-    connect \Y $15
-  end
-  process $group_3
-    assign \qlq_upd 1'0
-    assign \qlq_upd $15
-    sync init
-  end
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.rst_l"
-module \rst_l$105
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
-  wire width 1 input 2 \s_rst
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
-  wire width 1 input 3 \r_rst
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
-  wire width 1 output 4 \q_rst
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
-  wire width 1 \q_int
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
-  wire width 1 \q_int$next
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
-  wire width 1 $1
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
-  cell $not $2
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \r_rst
-    connect \Y $1
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
-  wire width 1 $3
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
-  cell $and $4
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \q_int
-    connect \B $1
-    connect \Y $3
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
-  wire width 1 $5
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
-  cell $or $6
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A $3
-    connect \B \s_rst
-    connect \Y $5
-  end
-  process $group_0
-    assign \q_int$next \q_int
-    assign \q_int$next $5
-    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
-      case 1'1
-        assign \q_int$next 1'0
-    end
-    sync init
-      update \q_int 1'0
-    sync posedge \clk
-      update \q_int \q_int$next
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
-  wire width 1 $7
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
-  cell $not $8
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \r_rst
-    connect \Y $7
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
-  wire width 1 $9
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
-  cell $and $10
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \q_int
-    connect \B $7
-    connect \Y $9
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
-  wire width 1 $11
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
-  cell $or $12
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A $9
-    connect \B \s_rst
-    connect \Y $11
-  end
-  process $group_1
-    assign \q_rst 1'0
-    assign \q_rst $11
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
-  wire width 1 \qn_rst
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
-  wire width 1 $13
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
-  cell $not $14
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \q_rst
-    connect \Y $13
-  end
-  process $group_2
-    assign \qn_rst 1'0
-    assign \qn_rst $13
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62"
-  wire width 1 \qlq_rst
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
-  wire width 1 $15
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
-  cell $or $16
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \q_rst
-    connect \B \q_int
-    connect \Y $15
-  end
-  process $group_3
-    assign \qlq_rst 1'0
-    assign \qlq_rst $15
-    sync init
-  end
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.lsd_l"
-module \lsd_l
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
-  wire width 1 input 2 \s_lsd
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
-  wire width 1 input 3 \r_lsd
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
-  wire width 1 output 4 \q_lsd
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
-  wire width 1 \q_int
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
-  wire width 1 \q_int$next
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
-  wire width 1 $1
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
-  cell $not $2
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \r_lsd
-    connect \Y $1
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
-  wire width 1 $3
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
-  cell $and $4
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \q_int
-    connect \B $1
-    connect \Y $3
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
-  wire width 1 $5
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
-  cell $or $6
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A $3
-    connect \B \s_lsd
-    connect \Y $5
-  end
-  process $group_0
-    assign \q_int$next \q_int
-    assign \q_int$next $5
-    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
-      case 1'1
-        assign \q_int$next 1'0
-    end
-    sync init
-      update \q_int 1'0
-    sync posedge \clk
-      update \q_int \q_int$next
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
-  wire width 1 $7
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
-  cell $not $8
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \r_lsd
-    connect \Y $7
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
-  wire width 1 $9
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
-  cell $and $10
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \q_int
-    connect \B $7
-    connect \Y $9
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
-  wire width 1 $11
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
-  cell $or $12
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A $9
-    connect \B \s_lsd
+    connect \B \s_alu
     connect \Y $11
   end
   process $group_1
-    assign \q_lsd 1'0
-    assign \q_lsd $11
+    assign \q_alu 1'0
+    assign \q_alu $11
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
-  wire width 1 \qn_lsd
+  wire width 1 \qn_alu
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
   wire width 1 $13
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
@@ -109107,16 +109448,16 @@ module \lsd_l
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \q_lsd
+    connect \A \q_alu
     connect \Y $13
   end
   process $group_2
-    assign \qn_lsd 1'0
-    assign \qn_lsd $13
+    assign \qn_alu 1'0
+    assign \qn_alu $13
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62"
-  wire width 1 \qlq_lsd
+  wire width 1 \qlq_alu
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
   wire width 1 $15
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
@@ -109126,31 +109467,21 @@ module \lsd_l
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \q_lsd
+    connect \A \q_alu
     connect \B \q_int
     connect \Y $15
   end
   process $group_3
-    assign \qlq_lsd 1'0
-    assign \qlq_lsd $15
+    assign \qlq_alu 1'0
+    assign \qlq_alu $15
     sync init
   end
 end
 attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0"
-module \ldst0
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 1 input 0 \cu_ad__go_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 1 output 1 \cu_ad__rel_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 1 input 2 \cu_st__go_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 1 output 3 \cu_st__rel_o
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 4 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 5 \clk
+attribute \nmigen.hierarchy "test_issuer.core.fus.mul0"
+module \mul0
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
   attribute \enum_value_0000001 "OP_NOP"
@@ -109225,100 +109556,255 @@ module \ldst0
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 7 input 6 \oper_i_ldst_ldst0__insn_type
+  wire width 7 input 1 \oper_i_alu_mul0__insn_type
+  attribute \enum_base_type "Function"
+  attribute \enum_value_00000000000 "NONE"
+  attribute \enum_value_00000000010 "ALU"
+  attribute \enum_value_00000000100 "LDST"
+  attribute \enum_value_00000001000 "SHIFT_ROT"
+  attribute \enum_value_00000010000 "LOGICAL"
+  attribute \enum_value_00000100000 "BRANCH"
+  attribute \enum_value_00001000000 "CR"
+  attribute \enum_value_00010000000 "TRAP"
+  attribute \enum_value_00100000000 "MUL"
+  attribute \enum_value_01000000000 "DIV"
+  attribute \enum_value_10000000000 "SPR"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 input 2 \oper_i_alu_mul0__fn_unit
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 64 input 7 \oper_i_ldst_ldst0__imm_data__imm
+  wire width 64 input 3 \oper_i_alu_mul0__imm_data__imm
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 8 \oper_i_ldst_ldst0__imm_data__imm_ok
+  wire width 1 input 4 \oper_i_alu_mul0__imm_data__imm_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 9 \oper_i_ldst_ldst0__zero_a
+  wire width 1 input 5 \oper_i_alu_mul0__rc__rc
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 10 \oper_i_ldst_ldst0__rc__rc
+  wire width 1 input 6 \oper_i_alu_mul0__rc__rc_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 11 \oper_i_ldst_ldst0__rc__rc_ok
+  wire width 1 input 7 \oper_i_alu_mul0__oe__oe
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 12 \oper_i_ldst_ldst0__oe__oe
+  wire width 1 input 8 \oper_i_alu_mul0__oe__oe_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 13 \oper_i_ldst_ldst0__oe__oe_ok
+  wire width 1 input 9 \oper_i_alu_mul0__invert_a
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 14 \oper_i_ldst_ldst0__is_32bit
+  wire width 1 input 10 \oper_i_alu_mul0__zero_a
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 15 \oper_i_ldst_ldst0__is_signed
+  wire width 1 input 11 \oper_i_alu_mul0__invert_out
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 4 input 16 \oper_i_ldst_ldst0__data_len
+  wire width 1 input 12 \oper_i_alu_mul0__write_cr0
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 17 \oper_i_ldst_ldst0__byte_reverse
+  wire width 1 input 13 \oper_i_alu_mul0__is_32bit
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 18 \oper_i_ldst_ldst0__sign_extend
-  attribute \enum_base_type "LDSTMode"
-  attribute \enum_value_00 "NONE"
-  attribute \enum_value_01 "update"
-  attribute \enum_value_10 "cix"
-  attribute \enum_value_11 "cx"
+  wire width 1 input 14 \oper_i_alu_mul0__is_signed
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 2 input 19 \oper_i_ldst_ldst0__ldst_mode
+  wire width 32 input 15 \oper_i_alu_mul0__insn
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
-  wire width 1 input 20 \cu_issue_i
+  wire width 1 input 16 \cu_issue_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:106"
-  wire width 1 output 21 \cu_busy_o
+  wire width 1 output 17 \cu_busy_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
-  wire width 3 input 22 \cu_rdmaskn_i
+  wire width 3 input 18 \cu_rdmaskn_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 3 output 23 \cu_rd__rel_o
+  wire width 3 output 19 \cu_rd__rel_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 3 input 24 \cu_rd__go_i
+  wire width 3 input 20 \cu_rd__go_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
-  wire width 64 input 25 \src1_i
+  wire width 64 input 21 \src1_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
-  wire width 64 input 26 \src2_i
+  wire width 64 input 22 \src2_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
-  wire width 64 input 27 \src3_i
+  wire width 1 input 23 \src3_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 output 24 \o_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 2 output 28 \cu_wr__rel_o
+  wire width 4 output 25 \cu_wr__rel_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 2 input 29 \cu_wr__go_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 64 output 30 \o
+  wire width 4 input 26 \cu_wr__go_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
+  wire width 64 output 27 \dest1_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 64 output 31 \ea
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:95"
-  wire width 1 output 32 \ldst_port0_is_ld_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:96"
-  wire width 1 output 33 \ldst_port0_is_st_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99"
-  wire width 4 output 34 \ldst_port0_data_len
+  wire width 1 output 28 \cr_a_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
+  wire width 4 output 29 \dest2_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 96 output 35 \ldst_port0_addr_i
+  wire width 1 output 30 \xer_ov_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
+  wire width 2 output 31 \dest3_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 36 \ldst_port0_addr_i_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:107"
-  wire width 1 input 37 \ldst_port0_addr_exc_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:106"
-  wire width 1 input 38 \ldst_port0_addr_ok_o
+  wire width 1 output 32 \xer_so_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
+  wire width 1 output 33 \dest4_o
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 34 \coresync_rst
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
+  wire width 1 \alu_mul0_n_valid_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
+  wire width 1 \alu_mul0_n_ready_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 64 input 39 \ldst_port0_ld_data_o
+  wire width 64 \alu_mul0_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 input 40 \ldst_port0_ld_data_o_ok
+  wire width 4 \alu_mul0_cr_a
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 64 output 41 \ldst_port0_st_data_i
+  wire width 2 \alu_mul0_xer_ov
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 42 \ldst_port0_st_data_i_ok
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
-  wire width 1 \opc_l_s_opc
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
-  wire width 1 \opc_l_s_opc$next
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
-  wire width 1 \opc_l_r_opc
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
-  wire width 1 \opc_l_r_opc$next
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
-  wire width 1 \opc_l_q_opc
-  cell \opc_l$102 \opc_l
-    connect \rst \rst
-    connect \clk \clk
-    connect \s_opc \opc_l_s_opc
-    connect \r_opc \opc_l_r_opc
-    connect \q_opc \opc_l_q_opc
+  wire width 1 \alu_mul0_xer_so
+  attribute \enum_base_type "MicrOp"
+  attribute \enum_value_0000000 "OP_ILLEGAL"
+  attribute \enum_value_0000001 "OP_NOP"
+  attribute \enum_value_0000010 "OP_ADD"
+  attribute \enum_value_0000011 "OP_ADDPCIS"
+  attribute \enum_value_0000100 "OP_AND"
+  attribute \enum_value_0000101 "OP_ATTN"
+  attribute \enum_value_0000110 "OP_B"
+  attribute \enum_value_0000111 "OP_BC"
+  attribute \enum_value_0001000 "OP_BCREG"
+  attribute \enum_value_0001001 "OP_BPERM"
+  attribute \enum_value_0001010 "OP_CMP"
+  attribute \enum_value_0001011 "OP_CMPB"
+  attribute \enum_value_0001100 "OP_CMPEQB"
+  attribute \enum_value_0001101 "OP_CMPRB"
+  attribute \enum_value_0001110 "OP_CNTZ"
+  attribute \enum_value_0001111 "OP_CRAND"
+  attribute \enum_value_0010000 "OP_CRANDC"
+  attribute \enum_value_0010001 "OP_CREQV"
+  attribute \enum_value_0010010 "OP_CRNAND"
+  attribute \enum_value_0010011 "OP_CRNOR"
+  attribute \enum_value_0010100 "OP_CROR"
+  attribute \enum_value_0010101 "OP_CRORC"
+  attribute \enum_value_0010110 "OP_CRXOR"
+  attribute \enum_value_0010111 "OP_DARN"
+  attribute \enum_value_0011000 "OP_DCBF"
+  attribute \enum_value_0011001 "OP_DCBST"
+  attribute \enum_value_0011010 "OP_DCBT"
+  attribute \enum_value_0011011 "OP_DCBTST"
+  attribute \enum_value_0011100 "OP_DCBZ"
+  attribute \enum_value_0011101 "OP_DIV"
+  attribute \enum_value_0011110 "OP_DIVE"
+  attribute \enum_value_0011111 "OP_EXTS"
+  attribute \enum_value_0100000 "OP_EXTSWSLI"
+  attribute \enum_value_0100001 "OP_ICBI"
+  attribute \enum_value_0100010 "OP_ICBT"
+  attribute \enum_value_0100011 "OP_ISEL"
+  attribute \enum_value_0100100 "OP_ISYNC"
+  attribute \enum_value_0100101 "OP_LOAD"
+  attribute \enum_value_0100110 "OP_STORE"
+  attribute \enum_value_0100111 "OP_MADDHD"
+  attribute \enum_value_0101000 "OP_MADDHDU"
+  attribute \enum_value_0101001 "OP_MADDLD"
+  attribute \enum_value_0101010 "OP_MCRF"
+  attribute \enum_value_0101011 "OP_MCRXR"
+  attribute \enum_value_0101100 "OP_MCRXRX"
+  attribute \enum_value_0101101 "OP_MFCR"
+  attribute \enum_value_0101110 "OP_MFSPR"
+  attribute \enum_value_0101111 "OP_MOD"
+  attribute \enum_value_0110000 "OP_MTCRF"
+  attribute \enum_value_0110001 "OP_MTSPR"
+  attribute \enum_value_0110010 "OP_MUL_L64"
+  attribute \enum_value_0110011 "OP_MUL_H64"
+  attribute \enum_value_0110100 "OP_MUL_H32"
+  attribute \enum_value_0110101 "OP_OR"
+  attribute \enum_value_0110110 "OP_POPCNT"
+  attribute \enum_value_0110111 "OP_PRTY"
+  attribute \enum_value_0111000 "OP_RLC"
+  attribute \enum_value_0111001 "OP_RLCL"
+  attribute \enum_value_0111010 "OP_RLCR"
+  attribute \enum_value_0111011 "OP_SETB"
+  attribute \enum_value_0111100 "OP_SHL"
+  attribute \enum_value_0111101 "OP_SHR"
+  attribute \enum_value_0111110 "OP_SYNC"
+  attribute \enum_value_0111111 "OP_TRAP"
+  attribute \enum_value_1000011 "OP_XOR"
+  attribute \enum_value_1000100 "OP_SIM_CONFIG"
+  attribute \enum_value_1000101 "OP_CROP"
+  attribute \enum_value_1000110 "OP_RFID"
+  attribute \enum_value_1000111 "OP_MFMSR"
+  attribute \enum_value_1001000 "OP_MTMSRD"
+  attribute \enum_value_1001001 "OP_SC"
+  attribute \enum_value_1001010 "OP_MTMSR"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 \alu_mul0_mul_op__insn_type
+  attribute \enum_base_type "Function"
+  attribute \enum_value_00000000000 "NONE"
+  attribute \enum_value_00000000010 "ALU"
+  attribute \enum_value_00000000100 "LDST"
+  attribute \enum_value_00000001000 "SHIFT_ROT"
+  attribute \enum_value_00000010000 "LOGICAL"
+  attribute \enum_value_00000100000 "BRANCH"
+  attribute \enum_value_00001000000 "CR"
+  attribute \enum_value_00010000000 "TRAP"
+  attribute \enum_value_00100000000 "MUL"
+  attribute \enum_value_01000000000 "DIV"
+  attribute \enum_value_10000000000 "SPR"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 \alu_mul0_mul_op__fn_unit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 \alu_mul0_mul_op__imm_data__imm
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \alu_mul0_mul_op__imm_data__imm_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \alu_mul0_mul_op__rc__rc
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \alu_mul0_mul_op__rc__rc_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \alu_mul0_mul_op__oe__oe
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \alu_mul0_mul_op__oe__oe_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \alu_mul0_mul_op__invert_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \alu_mul0_mul_op__zero_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \alu_mul0_mul_op__invert_out
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \alu_mul0_mul_op__write_cr0
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \alu_mul0_mul_op__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \alu_mul0_mul_op__is_signed
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \alu_mul0_mul_op__insn
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
+  wire width 64 \alu_mul0_ra
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
+  wire width 64 \alu_mul0_rb
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
+  wire width 1 \alu_mul0_xer_so$1
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153"
+  wire width 1 \alu_mul0_p_valid_i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154"
+  wire width 1 \alu_mul0_p_ready_o
+  cell \alu_mul0 \alu_mul0
+    connect \coresync_clk \coresync_clk
+    connect \o_ok \o_ok
+    connect \cr_a_ok \cr_a_ok
+    connect \xer_ov_ok \xer_ov_ok
+    connect \xer_so_ok \xer_so_ok
+    connect \coresync_rst \coresync_rst
+    connect \n_valid_o \alu_mul0_n_valid_o
+    connect \n_ready_i \alu_mul0_n_ready_i
+    connect \o \alu_mul0_o
+    connect \cr_a \alu_mul0_cr_a
+    connect \xer_ov \alu_mul0_xer_ov
+    connect \xer_so \alu_mul0_xer_so
+    connect \mul_op__insn_type \alu_mul0_mul_op__insn_type
+    connect \mul_op__fn_unit \alu_mul0_mul_op__fn_unit
+    connect \mul_op__imm_data__imm \alu_mul0_mul_op__imm_data__imm
+    connect \mul_op__imm_data__imm_ok \alu_mul0_mul_op__imm_data__imm_ok
+    connect \mul_op__rc__rc \alu_mul0_mul_op__rc__rc
+    connect \mul_op__rc__rc_ok \alu_mul0_mul_op__rc__rc_ok
+    connect \mul_op__oe__oe \alu_mul0_mul_op__oe__oe
+    connect \mul_op__oe__oe_ok \alu_mul0_mul_op__oe__oe_ok
+    connect \mul_op__invert_a \alu_mul0_mul_op__invert_a
+    connect \mul_op__zero_a \alu_mul0_mul_op__zero_a
+    connect \mul_op__invert_out \alu_mul0_mul_op__invert_out
+    connect \mul_op__write_cr0 \alu_mul0_mul_op__write_cr0
+    connect \mul_op__is_32bit \alu_mul0_mul_op__is_32bit
+    connect \mul_op__is_signed \alu_mul0_mul_op__is_signed
+    connect \mul_op__insn \alu_mul0_mul_op__insn
+    connect \ra \alu_mul0_ra
+    connect \rb \alu_mul0_rb
+    connect \xer_so$1 \alu_mul0_xer_so$1
+    connect \p_valid_i \alu_mul0_p_valid_i
+    connect \p_ready_o \alu_mul0_p_ready_o
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
   wire width 3 \src_l_s_src
@@ -109330,583 +109816,733 @@ module \ldst0
   wire width 3 \src_l_r_src$next
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
   wire width 3 \src_l_q_src
-  cell \src_l$103 \src_l
-    connect \rst \rst
-    connect \clk \clk
+  cell \src_l$97 \src_l
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
     connect \s_src \src_l_s_src
     connect \r_src \src_l_r_src
     connect \q_src \src_l_q_src
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
-  wire width 1 \alu_l_s_alu
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
-  wire width 1 \alu_l_r_alu
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
-  wire width 1 \alu_l_q_alu
-  cell \alu_l$104 \alu_l
-    connect \rst \rst
-    connect \clk \clk
-    connect \s_alu \alu_l_s_alu
-    connect \r_alu \alu_l_r_alu
-    connect \q_alu \alu_l_q_alu
-  end
+  wire width 1 \opc_l_s_opc
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
-  wire width 1 \adr_l_s_adr
+  wire width 1 \opc_l_s_opc$next
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
-  wire width 1 \adr_l_r_adr
+  wire width 1 \opc_l_r_opc
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
-  wire width 1 \adr_l_r_adr$next
+  wire width 1 \opc_l_r_opc$next
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
-  wire width 1 \adr_l_q_adr
-  cell \adr_l \adr_l
-    connect \rst \rst
-    connect \clk \clk
-    connect \s_adr \adr_l_s_adr
-    connect \r_adr \adr_l_r_adr
-    connect \q_adr \adr_l_q_adr
+  wire width 1 \opc_l_q_opc
+  cell \opc_l$98 \opc_l
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
+    connect \s_opc \opc_l_s_opc
+    connect \r_opc \opc_l_r_opc
+    connect \q_opc \opc_l_q_opc
   end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
+  wire width 4 \req_l_q_req
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
-  wire width 1 \lod_l_s_lod
+  wire width 4 \req_l_s_req
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
-  wire width 1 \lod_l_r_lod
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
-  wire width 1 \lod_l_qn_lod
-  cell \lod_l \lod_l
-    connect \rst \rst
-    connect \clk \clk
-    connect \s_lod \lod_l_s_lod
-    connect \r_lod \lod_l_r_lod
-    connect \qn_lod \lod_l_qn_lod
+  wire width 4 \req_l_r_req
+  cell \req_l$99 \req_l
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
+    connect \q_req \req_l_q_req
+    connect \s_req \req_l_s_req
+    connect \r_req \req_l_r_req
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
-  wire width 1 \sto_l_s_sto
+  wire width 1 \rst_l_s_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
-  wire width 1 \sto_l_r_sto
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
-  wire width 1 \sto_l_q_sto
-  cell \sto_l \sto_l
-    connect \rst \rst
-    connect \clk \clk
-    connect \s_sto \sto_l_s_sto
-    connect \r_sto \sto_l_r_sto
-    connect \q_sto \sto_l_q_sto
+  wire width 1 \rst_l_r_rst
+  cell \rst_l$100 \rst_l
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
+    connect \s_rst \rst_l_s_rst
+    connect \r_rst \rst_l_r_rst
   end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
+  wire width 1 \rok_l_q_rdok
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
-  wire width 1 \wri_l_s_wri
+  wire width 1 \rok_l_s_rdok
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
-  wire width 1 \wri_l_r_wri
+  wire width 1 \rok_l_r_rdok
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
-  wire width 1 \wri_l_r_wri$next
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
-  wire width 1 \wri_l_q_wri
-  cell \wri_l \wri_l
-    connect \rst \rst
-    connect \clk \clk
-    connect \s_wri \wri_l_s_wri
-    connect \r_wri \wri_l_r_wri
-    connect \q_wri \wri_l_q_wri
+  wire width 1 \rok_l_r_rdok$next
+  cell \rok_l$101 \rok_l
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
+    connect \q_rdok \rok_l_q_rdok
+    connect \s_rdok \rok_l_s_rdok
+    connect \r_rdok \rok_l_r_rdok
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
-  wire width 1 \upd_l_s_upd
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
-  wire width 1 \upd_l_s_upd$next
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
+  wire width 1 \alui_l_q_alui
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
-  wire width 1 \upd_l_r_upd
+  wire width 1 \alui_l_r_alui
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
-  wire width 1 \upd_l_r_upd$next
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
-  wire width 1 \upd_l_q_upd
-  cell \upd_l \upd_l
-    connect \rst \rst
-    connect \clk \clk
-    connect \s_upd \upd_l_s_upd
-    connect \r_upd \upd_l_r_upd
-    connect \q_upd \upd_l_q_upd
-  end
+  wire width 1 \alui_l_r_alui$next
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
-  wire width 1 \rst_l_s_rst
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
-  wire width 1 \rst_l_r_rst
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
-  wire width 1 \rst_l_q_rst
-  cell \rst_l$105 \rst_l
-    connect \rst \rst
-    connect \clk \clk
-    connect \s_rst \rst_l_s_rst
-    connect \r_rst \rst_l_r_rst
-    connect \q_rst \rst_l_q_rst
+  wire width 1 \alui_l_s_alui
+  cell \alui_l$102 \alui_l
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
+    connect \q_alui \alui_l_q_alui
+    connect \r_alui \alui_l_r_alui
+    connect \s_alui \alui_l_s_alui
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
-  wire width 1 \lsd_l_s_lsd
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
+  wire width 1 \alu_l_q_alu
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
-  wire width 1 \lsd_l_r_lsd
+  wire width 1 \alu_l_r_alu
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
-  wire width 1 \lsd_l_r_lsd$next
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
-  wire width 1 \lsd_l_q_lsd
-  cell \lsd_l \lsd_l
-    connect \rst \rst
-    connect \clk \clk
-    connect \s_lsd \lsd_l_s_lsd
-    connect \r_lsd \lsd_l_r_lsd
-    connect \q_lsd \lsd_l_q_lsd
+  wire width 1 \alu_l_r_alu$next
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+  wire width 1 \alu_l_s_alu
+  cell \alu_l$103 \alu_l
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
+    connect \q_alu \alu_l_q_alu
+    connect \r_alu \alu_l_r_alu
+    connect \s_alu \alu_l_s_alu
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:289"
-  wire width 1 \reset_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:103"
-  wire width 1 \cu_go_die_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:293"
-  wire width 1 $1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:293"
-  cell $or $2
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:186"
+  wire width 1 \all_rd
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:187"
+  wire width 1 $2
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:187"
+  cell $and $3
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \cu_issue_i
-    connect \B \cu_go_die_i
-    connect \Y $1
+    connect \A \cu_busy_o
+    connect \B \rok_l_q_rdok
+    connect \Y $2
   end
-  process $group_0
-    assign \reset_i 1'0
-    assign \reset_i $1
-    sync init
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188"
+  wire width 1 $4
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188"
+  wire width 3 $5
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188"
+  cell $not $6
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 3
+    parameter \Y_WIDTH 3
+    connect \A \cu_rd__rel_o
+    connect \Y $5
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:285"
-  wire width 1 \reset_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:275"
-  wire width 1 \wr_reset
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:294"
-  wire width 1 $3
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:294"
-  cell $or $4
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188"
+  wire width 3 $7
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188"
+  cell $or $8
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
+    parameter \A_WIDTH 3
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \wr_reset
-    connect \B \cu_go_die_i
-    connect \Y $3
+    parameter \B_WIDTH 3
+    parameter \Y_WIDTH 3
+    connect \A $5
+    connect \B \cu_rd__go_i
+    connect \Y $7
   end
-  process $group_1
-    assign \reset_o 1'0
-    assign \reset_o $3
-    sync init
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188"
+  cell $reduce_and $9
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 3
+    parameter \Y_WIDTH 1
+    connect \A $7
+    connect \Y $4
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:286"
-  wire width 1 \reset_w
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:295"
-  wire width 1 $5
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:295"
-  cell $or $6
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188"
+  wire width 1 $10
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188"
+  cell $and $11
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \cu_wr__go_i [0]
-    connect \B \cu_go_die_i
-    connect \Y $5
+    connect \A $2
+    connect \B $4
+    connect \Y $10
   end
-  process $group_2
-    assign \reset_w 1'0
-    assign \reset_w $5
+  process $group_0
+    assign \all_rd 1'0
+    assign \all_rd $10
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:287"
-  wire width 1 \reset_u
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:296"
-  wire width 1 $7
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:296"
-  cell $or $8
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:191"
+  wire width 1 \all_rd_dly
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:191"
+  wire width 1 \all_rd_dly$next
+  process $group_1
+    assign \all_rd_dly$next \all_rd_dly
+    assign \all_rd_dly$next \all_rd
+    sync init
+      update \all_rd_dly 1'0
+    sync posedge \coresync_clk
+      update \all_rd_dly \all_rd_dly$next
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:192"
+  wire width 1 \all_rd_pulse
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:194"
+  wire width 1 $12
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:194"
+  cell $not $13
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \cu_wr__go_i [1]
-    connect \B \cu_go_die_i
-    connect \Y $7
-  end
-  process $group_3
-    assign \reset_u 1'0
-    assign \reset_u $7
-    sync init
+    connect \A \all_rd_dly
+    connect \Y $12
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:291"
-  wire width 1 \reset_s
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:297"
-  wire width 1 $9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:297"
-  cell $or $10
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:194"
+  wire width 1 $14
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:194"
+  cell $and $15
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \cu_st__go_i
-    connect \B \cu_go_die_i
-    connect \Y $9
+    connect \A \all_rd
+    connect \B $12
+    connect \Y $14
   end
-  process $group_4
-    assign \reset_s 1'0
-    assign \reset_s $9
+  process $group_2
+    assign \all_rd_pulse 1'0
+    assign \all_rd_pulse $14
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:290"
-  wire width 3 \reset_r
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:298"
-  wire width 3 $11
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:298"
-  cell $or $12
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 3
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 3
-    parameter \Y_WIDTH 3
-    connect \A \cu_rd__go_i
-    connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i }
-    connect \Y $11
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:197"
+  wire width 1 \alu_done
+  process $group_3
+    assign \alu_done 1'0
+    assign \alu_done \alu_mul0_n_valid_o
+    sync init
   end
-  process $group_5
-    assign \reset_r 3'000
-    assign \reset_r $11
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198"
+  wire width 1 \alu_done_dly
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198"
+  wire width 1 \alu_done_dly$next
+  process $group_4
+    assign \alu_done_dly$next \alu_done_dly
+    assign \alu_done_dly$next \alu_done
     sync init
+      update \alu_done_dly 1'0
+    sync posedge \coresync_clk
+      update \alu_done_dly \alu_done_dly$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:288"
-  wire width 1 \reset_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:299"
-  wire width 1 $13
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:299"
-  cell $or $14
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:199"
+  wire width 1 \alu_pulse
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:203"
+  wire width 1 $16
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:203"
+  cell $not $17
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \alu_done_dly
+    connect \Y $16
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:203"
+  wire width 1 $18
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:203"
+  cell $and $19
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \cu_ad__go_i
-    connect \B \cu_go_die_i
-    connect \Y $13
+    connect \A \alu_done
+    connect \B $16
+    connect \Y $18
   end
-  process $group_6
-    assign \reset_a 1'0
-    assign \reset_a $13
+  process $group_5
+    assign \alu_pulse 1'0
+    assign \alu_pulse $18
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:301"
-  wire width 1 \p_st_go
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:301"
-  wire width 1 \p_st_go$next
-  process $group_7
-    assign \p_st_go$next \p_st_go
-    assign \p_st_go$next \cu_st__go_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:200"
+  wire width 4 \alu_pulsem
+  process $group_6
+    assign \alu_pulsem 4'0000
+    assign \alu_pulsem { \alu_pulse \alu_pulse \alu_pulse \alu_pulse }
     sync init
-      update \p_st_go 1'0
-    sync posedge \clk
-      update \p_st_go \p_st_go$next
   end
-  process $group_8
-    assign \opc_l_s_opc$next \opc_l_s_opc
-    assign \opc_l_s_opc$next \cu_issue_i
-    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
-      case 1'1
-        assign \opc_l_s_opc$next 1'0
-    end
-    sync init
-      update \opc_l_s_opc 1'0
-    sync posedge \clk
-      update \opc_l_s_opc \opc_l_s_opc$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:207"
+  wire width 4 \prev_wr_go
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:207"
+  wire width 4 \prev_wr_go$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
+  wire width 4 $20
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
+  cell $and $21
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 4
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 4
+    parameter \Y_WIDTH 4
+    connect \A \cu_wr__go_i
+    connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o }
+    connect \Y $20
   end
-  process $group_9
-    assign \opc_l_r_opc$next \opc_l_r_opc
-    assign \opc_l_r_opc$next \reset_o
+  process $group_7
+    assign \prev_wr_go$next \prev_wr_go
+    assign \prev_wr_go$next $20
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
-        assign \opc_l_r_opc$next 1'1
+        assign \prev_wr_go$next 4'0000
     end
     sync init
-      update \opc_l_r_opc 1'1
-    sync posedge \clk
-      update \opc_l_r_opc \opc_l_r_opc$next
+      update \prev_wr_go 4'0000
+    sync posedge \coresync_clk
+      update \prev_wr_go \prev_wr_go$next
   end
-  process $group_10
-    assign \src_l_s_src$next \src_l_s_src
-    assign \src_l_s_src$next { \cu_issue_i \cu_issue_i \cu_issue_i }
-    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
-      case 1'1
-        assign \src_l_s_src$next 3'000
-    end
-    sync init
-      update \src_l_s_src 3'000
-    sync posedge \clk
-      update \src_l_s_src \src_l_s_src$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107"
+  wire width 1 \cu_done_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
+  wire width 1 $22
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
+  wire width 1 $23
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
+  wire width 4 $24
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96"
+  wire width 4 \cu_wrmask_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
+  cell $not $25
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 4
+    parameter \Y_WIDTH 4
+    connect \A \cu_wrmask_o
+    connect \Y $24
   end
-  process $group_11
-    assign \src_l_r_src$next \src_l_r_src
-    assign \src_l_r_src$next \reset_r
-    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
-      case 1'1
-        assign \src_l_r_src$next 3'111
-    end
-    sync init
-      update \src_l_r_src 3'111
-    sync posedge \clk
-      update \src_l_r_src \src_l_r_src$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
+  wire width 4 $26
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
+  cell $and $27
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 4
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 4
+    parameter \Y_WIDTH 4
+    connect \A \cu_wr__rel_o
+    connect \B $24
+    connect \Y $26
   end
-  process $group_12
-    assign \alu_l_s_alu 1'0
-    assign \alu_l_s_alu \reset_i
-    sync init
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
+  cell $reduce_bool $28
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 4
+    parameter \Y_WIDTH 1
+    connect \A $26
+    connect \Y $23
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:269"
-  wire width 1 \alu_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:269"
-  wire width 1 \alu_ok$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:331"
-  wire width 1 $15
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:268"
-  wire width 1 \alu_valid
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:331"
-  cell $not $16
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
+  cell $not $29
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \alu_valid
-    connect \Y $15
+    connect \A $23
+    connect \Y $22
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:331"
-  wire width 1 $17
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:331"
-  cell $and $18
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
+  wire width 1 $30
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
+  cell $and $31
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \alu_ok
-    connect \B $15
-    connect \Y $17
+    connect \A \cu_busy_o
+    connect \B $22
+    connect \Y $30
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:331"
-  wire width 1 $19
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:273"
-  wire width 1 \rda_any
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:331"
-  cell $not $20
+  process $group_8
+    assign \cu_done_o 1'0
+    assign \cu_done_o $30
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214"
+  wire width 1 \wr_any
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:218"
+  wire width 1 $32
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:218"
+  cell $reduce_bool $33
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
+    parameter \A_WIDTH 4
     parameter \Y_WIDTH 1
-    connect \A \rda_any
-    connect \Y $19
+    connect \A \cu_wr__go_i
+    connect \Y $32
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:331"
-  wire width 1 $21
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:331"
-  cell $and $22
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:218"
+  wire width 1 $34
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:218"
+  cell $reduce_bool $35
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 4
+    parameter \Y_WIDTH 1
+    connect \A \prev_wr_go
+    connect \Y $34
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:218"
+  wire width 1 $36
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:218"
+  cell $or $37
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $17
-    connect \B $19
-    connect \Y $21
+    connect \A $32
+    connect \B $34
+    connect \Y $36
   end
-  process $group_13
-    assign \alu_l_r_alu 1'1
-    assign \alu_l_r_alu $21
+  process $group_9
+    assign \wr_any 1'0
+    assign \wr_any $36
     sync init
   end
-  process $group_14
-    assign \adr_l_s_adr 1'0
-    assign \adr_l_s_adr \reset_i
-    sync init
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215"
+  wire width 1 \req_done
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:219"
+  wire width 1 $38
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:219"
+  cell $not $39
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \alu_mul0_n_ready_i
+    connect \Y $38
   end
-  process $group_15
-    assign \adr_l_r_adr$next \adr_l_r_adr
-    assign \adr_l_r_adr$next \reset_a
-    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
-      case 1'1
-        assign \adr_l_r_adr$next 1'1
-    end
-    sync init
-      update \adr_l_r_adr 1'1
-    sync posedge \clk
-      update \adr_l_r_adr \adr_l_r_adr$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:219"
+  wire width 1 $40
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:219"
+  cell $and $41
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_any
+    connect \B $38
+    connect \Y $40
   end
-  process $group_16
-    assign \lod_l_s_lod 1'0
-    assign \lod_l_s_lod \reset_i
-    sync init
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:220"
+  wire width 4 $42
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:220"
+  cell $and $43
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 4
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 4
+    parameter \Y_WIDTH 4
+    connect \A \req_l_q_req
+    connect \B \cu_wrmask_o
+    connect \Y $42
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:271"
-  wire width 1 \ld_ok
-  process $group_17
-    assign \lod_l_r_lod 1'1
-    assign \lod_l_r_lod \ld_ok
-    sync init
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:220"
+  wire width 1 $44
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:220"
+  cell $eq $45
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 4
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $42
+    connect \B 1'0
+    connect \Y $44
   end
-  process $group_18
-    assign \wri_l_s_wri 1'0
-    assign \wri_l_s_wri \cu_issue_i
-    sync init
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:220"
+  wire width 1 $46
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:220"
+  cell $and $47
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $40
+    connect \B $44
+    connect \Y $46
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:343"
-  wire width 2 $23
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107"
-  wire width 1 \cu_done_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:343"
-  wire width 2 $24
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:343"
-  cell $or $25
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
+  wire width 1 $48
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
+  cell $eq $49
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 4
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \cu_wrmask_o
+    connect \B 1'0
+    connect \Y $48
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
+  wire width 1 $50
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
+  cell $and $51
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 2
-    parameter \Y_WIDTH 2
-    connect \A \reset_w
-    connect \B { \cu_done_o \cu_done_o }
-    connect \Y $24
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $48
+    connect \B \alu_mul0_n_ready_i
+    connect \Y $50
   end
-  connect $23 $24
-  process $group_19
-    assign \wri_l_r_wri$next \wri_l_r_wri
-    assign \wri_l_r_wri$next $23 [0]
-    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
-      case 1'1
-        assign \wri_l_r_wri$next 1'1
-    end
-    sync init
-      update \wri_l_r_wri 1'1
-    sync posedge \clk
-      update \wri_l_r_wri \wri_l_r_wri$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
+  wire width 1 $52
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
+  cell $and $53
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $50
+    connect \B \alu_mul0_n_valid_o
+    connect \Y $52
   end
-  process $group_20
-    assign \upd_l_s_upd$next \upd_l_s_upd
-    assign \upd_l_s_upd$next \reset_i
-    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
-      case 1'1
-        assign \upd_l_s_upd$next 1'0
-    end
-    sync init
-      update \upd_l_s_upd 1'0
-    sync posedge \clk
-      update \upd_l_s_upd \upd_l_s_upd$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
+  wire width 1 $54
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
+  cell $and $55
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $52
+    connect \B \cu_busy_o
+    connect \Y $54
   end
-  process $group_21
-    assign \upd_l_r_upd$next \upd_l_r_upd
-    assign \upd_l_r_upd$next \reset_u
-    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+  process $group_10
+    assign \req_done 1'0
+    assign \req_done $46
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
+    switch { $54 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
       case 1'1
-        assign \upd_l_r_upd$next 1'1
+        assign \req_done 1'1
     end
     sync init
-      update \upd_l_r_upd 1'1
-    sync posedge \clk
-      update \upd_l_r_upd \upd_l_r_upd$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:270"
-  wire width 1 \addr_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:265"
-  wire width 1 \op_is_st
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:350"
-  wire width 1 $26
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:350"
-  cell $and $27
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:229"
+  wire width 1 \reset
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:103"
+  wire width 1 \cu_go_die_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233"
+  wire width 1 $56
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233"
+  cell $or $57
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \addr_ok
-    connect \B \op_is_st
-    connect \Y $26
+    connect \A \req_done
+    connect \B \cu_go_die_i
+    connect \Y $56
   end
-  process $group_22
-    assign \sto_l_s_sto 1'0
-    assign \sto_l_s_sto $26
+  process $group_11
+    assign \reset 1'0
+    assign \reset $56
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:351"
-  wire width 1 $28
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:351"
-  cell $or $29
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230"
+  wire width 1 \rst_r
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:234"
+  wire width 1 $58
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:234"
+  cell $or $59
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \reset_s
-    connect \B \p_st_go
-    connect \Y $28
+    connect \A \cu_issue_i
+    connect \B \cu_go_die_i
+    connect \Y $58
   end
-  process $group_23
-    assign \sto_l_r_sto 1'1
-    assign \sto_l_r_sto $28
+  process $group_12
+    assign \rst_r 1'0
+    assign \rst_r $58
     sync init
   end
-  process $group_24
-    assign \lsd_l_s_lsd 1'0
-    assign \lsd_l_s_lsd \cu_issue_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231"
+  wire width 4 \reset_w
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:235"
+  wire width 4 $60
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:235"
+  cell $or $61
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 4
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 4
+    parameter \Y_WIDTH 4
+    connect \A \cu_wr__go_i
+    connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i }
+    connect \Y $60
+  end
+  process $group_13
+    assign \reset_w 4'0000
+    assign \reset_w $60
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:355"
-  wire width 1 $30
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:355"
-  cell $or $31
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232"
+  wire width 3 \reset_r
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:236"
+  wire width 3 $62
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:236"
+  cell $or $63
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
+    parameter \A_WIDTH 3
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \reset_s
-    connect \B \p_st_go
-    connect \Y $30
+    parameter \B_WIDTH 3
+    parameter \Y_WIDTH 3
+    connect \A \cu_rd__go_i
+    connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i }
+    connect \Y $62
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:355"
-  wire width 1 $32
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:355"
-  cell $or $33
+  process $group_14
+    assign \reset_r 3'000
+    assign \reset_r $62
+    sync init
+  end
+  process $group_15
+    assign \rok_l_s_rdok 1'0
+    assign \rok_l_s_rdok \cu_issue_i
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:240"
+  wire width 1 $64
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:240"
+  cell $and $65
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $30
-    connect \B \ld_ok
-    connect \Y $32
+    connect \A \alu_mul0_n_valid_o
+    connect \B \cu_busy_o
+    connect \Y $64
   end
-  process $group_25
-    assign \lsd_l_r_lsd$next \lsd_l_r_lsd
-    assign \lsd_l_r_lsd$next $32
-    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+  process $group_16
+    assign \rok_l_r_rdok$next \rok_l_r_rdok
+    assign \rok_l_r_rdok$next $64
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
       case 1'1
-        assign \lsd_l_r_lsd$next 1'1
+        assign \rok_l_r_rdok$next 1'1
     end
     sync init
-      update \lsd_l_r_lsd 1'1
-    sync posedge \clk
-      update \lsd_l_r_lsd \lsd_l_r_lsd$next
+      update \rok_l_r_rdok 1'1
+    sync posedge \coresync_clk
+      update \rok_l_r_rdok \rok_l_r_rdok$next
   end
-  process $group_26
+  process $group_17
     assign \rst_l_s_rst 1'0
-    assign \rst_l_s_rst \addr_ok
+    assign \rst_l_s_rst \all_rd
     sync init
   end
-  process $group_27
+  process $group_18
     assign \rst_l_r_rst 1'1
-    assign \rst_l_r_rst \cu_issue_i
+    assign \rst_l_r_rst \rst_r
+    sync init
+  end
+  process $group_19
+    assign \opc_l_s_opc$next \opc_l_s_opc
+    assign \opc_l_s_opc$next \cu_issue_i
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
+      case 1'1
+        assign \opc_l_s_opc$next 1'0
+    end
+    sync init
+      update \opc_l_s_opc 1'0
+    sync posedge \coresync_clk
+      update \opc_l_s_opc \opc_l_s_opc$next
+  end
+  process $group_20
+    assign \opc_l_r_opc$next \opc_l_r_opc
+    assign \opc_l_r_opc$next \req_done
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
+      case 1'1
+        assign \opc_l_r_opc$next 1'1
+    end
+    sync init
+      update \opc_l_r_opc 1'1
+    sync posedge \coresync_clk
+      update \opc_l_r_opc \opc_l_r_opc$next
+  end
+  process $group_21
+    assign \src_l_s_src$next \src_l_s_src
+    assign \src_l_s_src$next { \cu_issue_i \cu_issue_i \cu_issue_i }
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
+      case 1'1
+        assign \src_l_s_src$next 3'000
+    end
+    sync init
+      update \src_l_s_src 3'000
+    sync posedge \coresync_clk
+      update \src_l_s_src \src_l_s_src$next
+  end
+  process $group_22
+    assign \src_l_r_src$next \src_l_r_src
+    assign \src_l_r_src$next \reset_r
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
+      case 1'1
+        assign \src_l_r_src$next 3'111
+    end
+    sync init
+      update \src_l_r_src 3'111
+    sync posedge \coresync_clk
+      update \src_l_r_src \src_l_r_src$next
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:255"
+  wire width 4 $66
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:255"
+  cell $and $67
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 4
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 4
+    parameter \Y_WIDTH 4
+    connect \A \alu_pulsem
+    connect \B \cu_wrmask_o
+    connect \Y $66
+  end
+  process $group_23
+    assign \req_l_s_req 4'0000
+    assign \req_l_s_req $66
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:256"
+  wire width 4 $68
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:256"
+  cell $or $69
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 4
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 4
+    parameter \Y_WIDTH 4
+    connect \A \reset_w
+    connect \B \prev_wr_go
+    connect \Y $68
+  end
+  process $group_24
+    assign \req_l_r_req 4'1111
+    assign \req_l_r_req $68
     sync init
   end
   attribute \enum_base_type "MicrOp"
@@ -109984,13 +110620,25 @@ module \ldst0
   attribute \enum_value_1001010 "OP_MTMSR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
   wire width 7 \oper_r__insn_type
+  attribute \enum_base_type "Function"
+  attribute \enum_value_00000000000 "NONE"
+  attribute \enum_value_00000000010 "ALU"
+  attribute \enum_value_00000000100 "LDST"
+  attribute \enum_value_00000001000 "SHIFT_ROT"
+  attribute \enum_value_00000010000 "LOGICAL"
+  attribute \enum_value_00000100000 "BRANCH"
+  attribute \enum_value_00001000000 "CR"
+  attribute \enum_value_00010000000 "TRAP"
+  attribute \enum_value_00100000000 "MUL"
+  attribute \enum_value_01000000000 "DIV"
+  attribute \enum_value_10000000000 "SPR"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 \oper_r__fn_unit
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
   wire width 64 \oper_r__imm_data__imm
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
   wire width 1 \oper_r__imm_data__imm_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \oper_r__zero_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
   wire width 1 \oper_r__rc__rc
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
   wire width 1 \oper_r__rc__rc_ok
@@ -109999,27 +110647,28 @@ module \ldst0
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
   wire width 1 \oper_r__oe__oe_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \oper_r__is_32bit
+  wire width 1 \oper_r__invert_a
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \oper_r__is_signed
+  wire width 1 \oper_r__zero_a
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 4 \oper_r__data_len
+  wire width 1 \oper_r__invert_out
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \oper_r__byte_reverse
+  wire width 1 \oper_r__write_cr0
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \oper_r__sign_extend
-  attribute \enum_base_type "LDSTMode"
-  attribute \enum_value_00 "NONE"
-  attribute \enum_value_01 "update"
-  attribute \enum_value_10 "cix"
-  attribute \enum_value_11 "cx"
+  wire width 1 \oper_r__is_32bit
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 2 \oper_r__ldst_mode
+  wire width 1 \oper_r__is_signed
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \oper_r__insn
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
   wire width 7 \oper_l__insn_type
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
   wire width 7 \oper_l__insn_type$next
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+  wire width 11 \oper_l__fn_unit
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+  wire width 11 \oper_l__fn_unit$next
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
   wire width 64 \oper_l__imm_data__imm
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
   wire width 64 \oper_l__imm_data__imm$next
@@ -110028,10 +110677,6 @@ module \ldst0
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
   wire width 1 \oper_l__imm_data__imm_ok$next
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
-  wire width 1 \oper_l__zero_a
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
-  wire width 1 \oper_l__zero_a$next
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
   wire width 1 \oper_l__rc__rc
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
   wire width 1 \oper_l__rc__rc$next
@@ -110048,80 +110693,86 @@ module \ldst0
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
   wire width 1 \oper_l__oe__oe_ok$next
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
-  wire width 1 \oper_l__is_32bit
+  wire width 1 \oper_l__invert_a
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
-  wire width 1 \oper_l__is_32bit$next
+  wire width 1 \oper_l__invert_a$next
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
-  wire width 1 \oper_l__is_signed
+  wire width 1 \oper_l__zero_a
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
-  wire width 1 \oper_l__is_signed$next
+  wire width 1 \oper_l__zero_a$next
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
-  wire width 4 \oper_l__data_len
+  wire width 1 \oper_l__invert_out
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
-  wire width 4 \oper_l__data_len$next
+  wire width 1 \oper_l__invert_out$next
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
-  wire width 1 \oper_l__byte_reverse
+  wire width 1 \oper_l__write_cr0
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
-  wire width 1 \oper_l__byte_reverse$next
+  wire width 1 \oper_l__write_cr0$next
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
-  wire width 1 \oper_l__sign_extend
+  wire width 1 \oper_l__is_32bit
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
-  wire width 1 \oper_l__sign_extend$next
+  wire width 1 \oper_l__is_32bit$next
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
-  wire width 2 \oper_l__ldst_mode
+  wire width 1 \oper_l__is_signed
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
-  wire width 2 \oper_l__ldst_mode$next
+  wire width 1 \oper_l__is_signed$next
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+  wire width 32 \oper_l__insn
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+  wire width 32 \oper_l__insn$next
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
-  wire width 87 $34
+  wire width 125 $70
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
-  cell $mux $35
-    parameter \WIDTH 87
-    connect \A { \oper_l__ldst_mode \oper_l__sign_extend \oper_l__byte_reverse \oper_l__data_len \oper_l__is_signed \oper_l__is_32bit { \oper_l__oe__oe_ok \oper_l__oe__oe } { \oper_l__rc__rc_ok \oper_l__rc__rc } \oper_l__zero_a { \oper_l__imm_data__imm_ok \oper_l__imm_data__imm } \oper_l__insn_type }
-    connect \B { \oper_i_ldst_ldst0__ldst_mode \oper_i_ldst_ldst0__sign_extend \oper_i_ldst_ldst0__byte_reverse \oper_i_ldst_ldst0__data_len \oper_i_ldst_ldst0__is_signed \oper_i_ldst_ldst0__is_32bit { \oper_i_ldst_ldst0__oe__oe_ok \oper_i_ldst_ldst0__oe__oe } { \oper_i_ldst_ldst0__rc__rc_ok \oper_i_ldst_ldst0__rc__rc } \oper_i_ldst_ldst0__zero_a { \oper_i_ldst_ldst0__imm_data__imm_ok \oper_i_ldst_ldst0__imm_data__imm } \oper_i_ldst_ldst0__insn_type }
+  cell $mux $71
+    parameter \WIDTH 125
+    connect \A { \oper_l__insn \oper_l__is_signed \oper_l__is_32bit \oper_l__write_cr0 \oper_l__invert_out \oper_l__zero_a \oper_l__invert_a { \oper_l__oe__oe_ok \oper_l__oe__oe } { \oper_l__rc__rc_ok \oper_l__rc__rc } { \oper_l__imm_data__imm_ok \oper_l__imm_data__imm } \oper_l__fn_unit \oper_l__insn_type }
+    connect \B { \oper_i_alu_mul0__insn \oper_i_alu_mul0__is_signed \oper_i_alu_mul0__is_32bit \oper_i_alu_mul0__write_cr0 \oper_i_alu_mul0__invert_out \oper_i_alu_mul0__zero_a \oper_i_alu_mul0__invert_a { \oper_i_alu_mul0__oe__oe_ok \oper_i_alu_mul0__oe__oe } { \oper_i_alu_mul0__rc__rc_ok \oper_i_alu_mul0__rc__rc } { \oper_i_alu_mul0__imm_data__imm_ok \oper_i_alu_mul0__imm_data__imm } \oper_i_alu_mul0__fn_unit \oper_i_alu_mul0__insn_type }
     connect \S \cu_issue_i
-    connect \Y $34
+    connect \Y $70
   end
-  process $group_28
+  process $group_25
     assign \oper_r__insn_type 7'0000000
+    assign \oper_r__fn_unit 11'00000000000
     assign \oper_r__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
     assign \oper_r__imm_data__imm_ok 1'0
-    assign \oper_r__zero_a 1'0
     assign \oper_r__rc__rc 1'0
     assign \oper_r__rc__rc_ok 1'0
     assign \oper_r__oe__oe 1'0
     assign \oper_r__oe__oe_ok 1'0
+    assign \oper_r__invert_a 1'0
+    assign \oper_r__zero_a 1'0
+    assign \oper_r__invert_out 1'0
+    assign \oper_r__write_cr0 1'0
     assign \oper_r__is_32bit 1'0
     assign \oper_r__is_signed 1'0
-    assign \oper_r__data_len 4'0000
-    assign \oper_r__byte_reverse 1'0
-    assign \oper_r__sign_extend 1'0
-    assign \oper_r__ldst_mode 2'00
-    assign { \oper_r__ldst_mode \oper_r__sign_extend \oper_r__byte_reverse \oper_r__data_len \oper_r__is_signed \oper_r__is_32bit { \oper_r__oe__oe_ok \oper_r__oe__oe } { \oper_r__rc__rc_ok \oper_r__rc__rc } \oper_r__zero_a { \oper_r__imm_data__imm_ok \oper_r__imm_data__imm } \oper_r__insn_type } $34
+    assign \oper_r__insn 32'00000000000000000000000000000000
+    assign { \oper_r__insn \oper_r__is_signed \oper_r__is_32bit \oper_r__write_cr0 \oper_r__invert_out \oper_r__zero_a \oper_r__invert_a { \oper_r__oe__oe_ok \oper_r__oe__oe } { \oper_r__rc__rc_ok \oper_r__rc__rc } { \oper_r__imm_data__imm_ok \oper_r__imm_data__imm } \oper_r__fn_unit \oper_r__insn_type } $70
     sync init
   end
-  process $group_42
+  process $group_40
     assign \oper_l__insn_type$next \oper_l__insn_type
+    assign \oper_l__fn_unit$next \oper_l__fn_unit
     assign \oper_l__imm_data__imm$next \oper_l__imm_data__imm
     assign \oper_l__imm_data__imm_ok$next \oper_l__imm_data__imm_ok
-    assign \oper_l__zero_a$next \oper_l__zero_a
     assign \oper_l__rc__rc$next \oper_l__rc__rc
     assign \oper_l__rc__rc_ok$next \oper_l__rc__rc_ok
     assign \oper_l__oe__oe$next \oper_l__oe__oe
     assign \oper_l__oe__oe_ok$next \oper_l__oe__oe_ok
+    assign \oper_l__invert_a$next \oper_l__invert_a
+    assign \oper_l__zero_a$next \oper_l__zero_a
+    assign \oper_l__invert_out$next \oper_l__invert_out
+    assign \oper_l__write_cr0$next \oper_l__write_cr0
     assign \oper_l__is_32bit$next \oper_l__is_32bit
     assign \oper_l__is_signed$next \oper_l__is_signed
-    assign \oper_l__data_len$next \oper_l__data_len
-    assign \oper_l__byte_reverse$next \oper_l__byte_reverse
-    assign \oper_l__sign_extend$next \oper_l__sign_extend
-    assign \oper_l__ldst_mode$next \oper_l__ldst_mode
+    assign \oper_l__insn$next \oper_l__insn
     attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
     switch { \cu_issue_i }
       attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
       case 1'1
-        assign { \oper_l__ldst_mode$next \oper_l__sign_extend$next \oper_l__byte_reverse$next \oper_l__data_len$next \oper_l__is_signed$next \oper_l__is_32bit$next { \oper_l__oe__oe_ok$next \oper_l__oe__oe$next } { \oper_l__rc__rc_ok$next \oper_l__rc__rc$next } \oper_l__zero_a$next { \oper_l__imm_data__imm_ok$next \oper_l__imm_data__imm$next } \oper_l__insn_type$next } { \oper_i_ldst_ldst0__ldst_mode \oper_i_ldst_ldst0__sign_extend \oper_i_ldst_ldst0__byte_reverse \oper_i_ldst_ldst0__data_len \oper_i_ldst_ldst0__is_signed \oper_i_ldst_ldst0__is_32bit { \oper_i_ldst_ldst0__oe__oe_ok \oper_i_ldst_ldst0__oe__oe } { \oper_i_ldst_ldst0__rc__rc_ok \oper_i_ldst_ldst0__rc__rc } \oper_i_ldst_ldst0__zero_a { \oper_i_ldst_ldst0__imm_data__imm_ok \oper_i_ldst_ldst0__imm_data__imm } \oper_i_ldst_ldst0__insn_type }
+        assign { \oper_l__insn$next \oper_l__is_signed$next \oper_l__is_32bit$next \oper_l__write_cr0$next \oper_l__invert_out$next \oper_l__zero_a$next \oper_l__invert_a$next { \oper_l__oe__oe_ok$next \oper_l__oe__oe$next } { \oper_l__rc__rc_ok$next \oper_l__rc__rc$next } { \oper_l__imm_data__imm_ok$next \oper_l__imm_data__imm$next } \oper_l__fn_unit$next \oper_l__insn_type$next } { \oper_i_alu_mul0__insn \oper_i_alu_mul0__is_signed \oper_i_alu_mul0__is_32bit \oper_i_alu_mul0__write_cr0 \oper_i_alu_mul0__invert_out \oper_i_alu_mul0__zero_a \oper_i_alu_mul0__invert_a { \oper_i_alu_mul0__oe__oe_ok \oper_i_alu_mul0__oe__oe } { \oper_i_alu_mul0__rc__rc_ok \oper_i_alu_mul0__rc__rc } { \oper_i_alu_mul0__imm_data__imm_ok \oper_i_alu_mul0__imm_data__imm } \oper_i_alu_mul0__fn_unit \oper_i_alu_mul0__insn_type }
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \oper_l__imm_data__imm$next 64'0000000000000000000000000000000000000000000000000000000000000000
         assign \oper_l__imm_data__imm_ok$next 1'0
@@ -110132,378 +110783,634 @@ module \ldst0
     end
     sync init
       update \oper_l__insn_type 7'0000000
+      update \oper_l__fn_unit 11'00000000000
       update \oper_l__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
       update \oper_l__imm_data__imm_ok 1'0
-      update \oper_l__zero_a 1'0
       update \oper_l__rc__rc 1'0
       update \oper_l__rc__rc_ok 1'0
       update \oper_l__oe__oe 1'0
       update \oper_l__oe__oe_ok 1'0
+      update \oper_l__invert_a 1'0
+      update \oper_l__zero_a 1'0
+      update \oper_l__invert_out 1'0
+      update \oper_l__write_cr0 1'0
       update \oper_l__is_32bit 1'0
       update \oper_l__is_signed 1'0
-      update \oper_l__data_len 4'0000
-      update \oper_l__byte_reverse 1'0
-      update \oper_l__sign_extend 1'0
-      update \oper_l__ldst_mode 2'00
-    sync posedge \clk
+      update \oper_l__insn 32'00000000000000000000000000000000
+    sync posedge \coresync_clk
       update \oper_l__insn_type \oper_l__insn_type$next
+      update \oper_l__fn_unit \oper_l__fn_unit$next
       update \oper_l__imm_data__imm \oper_l__imm_data__imm$next
       update \oper_l__imm_data__imm_ok \oper_l__imm_data__imm_ok$next
-      update \oper_l__zero_a \oper_l__zero_a$next
       update \oper_l__rc__rc \oper_l__rc__rc$next
       update \oper_l__rc__rc_ok \oper_l__rc__rc_ok$next
       update \oper_l__oe__oe \oper_l__oe__oe$next
       update \oper_l__oe__oe_ok \oper_l__oe__oe_ok$next
+      update \oper_l__invert_a \oper_l__invert_a$next
+      update \oper_l__zero_a \oper_l__zero_a$next
+      update \oper_l__invert_out \oper_l__invert_out$next
+      update \oper_l__write_cr0 \oper_l__write_cr0$next
       update \oper_l__is_32bit \oper_l__is_32bit$next
       update \oper_l__is_signed \oper_l__is_signed$next
-      update \oper_l__data_len \oper_l__data_len$next
-      update \oper_l__byte_reverse \oper_l__byte_reverse$next
-      update \oper_l__sign_extend \oper_l__sign_extend$next
-      update \oper_l__ldst_mode \oper_l__ldst_mode$next
+      update \oper_l__insn \oper_l__insn$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:366"
-  wire width 64 \ldd_r
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:279"
-  wire width 64 \ldd_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
-  wire width 64 \ldo_r
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
-  wire width 64 \ldo_r$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+  wire width 64 \data_r0__o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+  wire width 1 \data_r0__o_ok
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+  wire width 64 \data_r0_l__o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+  wire width 64 \data_r0_l__o$next
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+  wire width 1 \data_r0_l__o_ok
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+  wire width 1 \data_r0_l__o_ok$next
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
-  wire width 64 $36
+  wire width 65 $72
+  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744"
+  wire width 1 $73
+  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744"
+  cell $reduce_bool $74
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 4
+    parameter \Y_WIDTH 1
+    connect \A \alu_pulsem
+    connect \Y $73
+  end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
-  cell $mux $37
-    parameter \WIDTH 64
-    connect \A \ldo_r
-    connect \B \ldd_o
-    connect \S \ld_ok
-    connect \Y $36
+  cell $mux $75
+    parameter \WIDTH 65
+    connect \A { \data_r0_l__o_ok \data_r0_l__o }
+    connect \B { \o_ok \alu_mul0_o }
+    connect \S $73
+    connect \Y $72
   end
-  process $group_56
-    assign \ldd_r 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \ldd_r $36
+  process $group_55
+    assign \data_r0__o 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \data_r0__o_ok 1'0
+    assign { \data_r0__o_ok \data_r0__o } $72
     sync init
   end
+  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
+  wire width 1 $76
+  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
+  cell $reduce_bool $77
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 4
+    parameter \Y_WIDTH 1
+    connect \A \alu_pulsem
+    connect \Y $76
+  end
   process $group_57
-    assign \ldo_r$next \ldo_r
+    assign \data_r0_l__o$next \data_r0_l__o
+    assign \data_r0_l__o_ok$next \data_r0_l__o_ok
     attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
-    switch { \ld_ok }
+    switch { $76 }
       attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
       case 1'1
-        assign \ldo_r$next \ldd_o
+        assign { \data_r0_l__o_ok$next \data_r0_l__o$next } { \o_ok \alu_mul0_o }
     end
-    sync init
-      update \ldo_r 64'0000000000000000000000000000000000000000000000000000000000000000
-    sync posedge \clk
-      update \ldo_r \ldo_r$next
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:373"
-  wire width 64 \src_r0
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
-  wire width 64 \src_r0_l
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
-  wire width 64 \src_r0_l$next
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
-  wire width 64 $38
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
-  cell $mux $39
-    parameter \WIDTH 64
-    connect \A \src_r0_l
-    connect \B \src1_i
-    connect \S \src_l_q_src [0]
-    connect \Y $38
-  end
-  process $group_58
-    assign \src_r0 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \src_r0 $38
-    sync init
-  end
-  process $group_59
-    assign \src_r0_l$next \src_r0_l
-    attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
-    switch { \src_l_q_src [0] }
-      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
       case 1'1
-        assign \src_r0_l$next \src1_i
+        assign \data_r0_l__o_ok$next 1'0
     end
     sync init
-      update \src_r0_l 64'0000000000000000000000000000000000000000000000000000000000000000
-    sync posedge \clk
-      update \src_r0_l \src_r0_l$next
+      update \data_r0_l__o 64'0000000000000000000000000000000000000000000000000000000000000000
+      update \data_r0_l__o_ok 1'0
+    sync posedge \coresync_clk
+      update \data_r0_l__o \data_r0_l__o$next
+      update \data_r0_l__o_ok \data_r0_l__o_ok$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:373"
-  wire width 64 \src_r1
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
-  wire width 64 \src_r1_l
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
-  wire width 64 \src_r1_l$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+  wire width 4 \data_r1__cr_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+  wire width 1 \data_r1__cr_a_ok
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+  wire width 4 \data_r1_l__cr_a
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+  wire width 4 \data_r1_l__cr_a$next
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+  wire width 1 \data_r1_l__cr_a_ok
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+  wire width 1 \data_r1_l__cr_a_ok$next
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
-  wire width 64 $40
+  wire width 5 $78
+  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744"
+  wire width 1 $79
+  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744"
+  cell $reduce_bool $80
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 4
+    parameter \Y_WIDTH 1
+    connect \A \alu_pulsem
+    connect \Y $79
+  end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
-  cell $mux $41
-    parameter \WIDTH 64
-    connect \A \src_r1_l
-    connect \B \src2_i
-    connect \S \src_l_q_src [1]
-    connect \Y $40
+  cell $mux $81
+    parameter \WIDTH 5
+    connect \A { \data_r1_l__cr_a_ok \data_r1_l__cr_a }
+    connect \B { \cr_a_ok \alu_mul0_cr_a }
+    connect \S $79
+    connect \Y $78
   end
-  process $group_60
-    assign \src_r1 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \src_r1 $40
+  process $group_59
+    assign \data_r1__cr_a 4'0000
+    assign \data_r1__cr_a_ok 1'0
+    assign { \data_r1__cr_a_ok \data_r1__cr_a } $78
     sync init
   end
+  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
+  wire width 1 $82
+  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
+  cell $reduce_bool $83
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 4
+    parameter \Y_WIDTH 1
+    connect \A \alu_pulsem
+    connect \Y $82
+  end
   process $group_61
-    assign \src_r1_l$next \src_r1_l
+    assign \data_r1_l__cr_a$next \data_r1_l__cr_a
+    assign \data_r1_l__cr_a_ok$next \data_r1_l__cr_a_ok
     attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
-    switch { \src_l_q_src [1] }
+    switch { $82 }
       attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
       case 1'1
-        assign \src_r1_l$next \src2_i
+        assign { \data_r1_l__cr_a_ok$next \data_r1_l__cr_a$next } { \cr_a_ok \alu_mul0_cr_a }
+    end
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
+      case 1'1
+        assign \data_r1_l__cr_a_ok$next 1'0
     end
     sync init
-      update \src_r1_l 64'0000000000000000000000000000000000000000000000000000000000000000
-    sync posedge \clk
-      update \src_r1_l \src_r1_l$next
+      update \data_r1_l__cr_a 4'0000
+      update \data_r1_l__cr_a_ok 1'0
+    sync posedge \coresync_clk
+      update \data_r1_l__cr_a \data_r1_l__cr_a$next
+      update \data_r1_l__cr_a_ok \data_r1_l__cr_a_ok$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:373"
-  wire width 64 \src_r2
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
-  wire width 64 \src_r2_l
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
-  wire width 64 \src_r2_l$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+  wire width 2 \data_r2__xer_ov
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+  wire width 1 \data_r2__xer_ov_ok
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+  wire width 2 \data_r2_l__xer_ov
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+  wire width 2 \data_r2_l__xer_ov$next
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+  wire width 1 \data_r2_l__xer_ov_ok
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+  wire width 1 \data_r2_l__xer_ov_ok$next
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
-  wire width 64 $42
+  wire width 3 $84
+  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744"
+  wire width 1 $85
+  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744"
+  cell $reduce_bool $86
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 4
+    parameter \Y_WIDTH 1
+    connect \A \alu_pulsem
+    connect \Y $85
+  end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
-  cell $mux $43
-    parameter \WIDTH 64
-    connect \A \src_r2_l
-    connect \B \src3_i
-    connect \S \src_l_q_src [2]
-    connect \Y $42
+  cell $mux $87
+    parameter \WIDTH 3
+    connect \A { \data_r2_l__xer_ov_ok \data_r2_l__xer_ov }
+    connect \B { \xer_ov_ok \alu_mul0_xer_ov }
+    connect \S $85
+    connect \Y $84
   end
-  process $group_62
-    assign \src_r2 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \src_r2 $42
+  process $group_63
+    assign \data_r2__xer_ov 2'00
+    assign \data_r2__xer_ov_ok 1'0
+    assign { \data_r2__xer_ov_ok \data_r2__xer_ov } $84
     sync init
   end
-  process $group_63
-    assign \src_r2_l$next \src_r2_l
+  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
+  wire width 1 $88
+  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
+  cell $reduce_bool $89
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 4
+    parameter \Y_WIDTH 1
+    connect \A \alu_pulsem
+    connect \Y $88
+  end
+  process $group_65
+    assign \data_r2_l__xer_ov$next \data_r2_l__xer_ov
+    assign \data_r2_l__xer_ov_ok$next \data_r2_l__xer_ov_ok
     attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
-    switch { \src_l_q_src [2] }
+    switch { $88 }
       attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
       case 1'1
-        assign \src_r2_l$next \src3_i
+        assign { \data_r2_l__xer_ov_ok$next \data_r2_l__xer_ov$next } { \xer_ov_ok \alu_mul0_xer_ov }
+    end
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
+      case 1'1
+        assign \data_r2_l__xer_ov_ok$next 1'0
     end
     sync init
-      update \src_r2_l 64'0000000000000000000000000000000000000000000000000000000000000000
-    sync posedge \clk
-      update \src_r2_l \src_r2_l$next
+      update \data_r2_l__xer_ov 2'00
+      update \data_r2_l__xer_ov_ok 1'0
+    sync posedge \coresync_clk
+      update \data_r2_l__xer_ov \data_r2_l__xer_ov$next
+      update \data_r2_l__xer_ov_ok \data_r2_l__xer_ov_ok$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:378"
-  wire width 64 \addr_r
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:278"
-  wire width 64 \alu_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:278"
-  wire width 64 \alu_o$next
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
-  wire width 64 \ea_r
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
-  wire width 64 \ea_r$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+  wire width 1 \data_r3__xer_so
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+  wire width 1 \data_r3__xer_so_ok
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+  wire width 1 \data_r3_l__xer_so
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+  wire width 1 \data_r3_l__xer_so$next
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+  wire width 1 \data_r3_l__xer_so_ok
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+  wire width 1 \data_r3_l__xer_so_ok$next
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
-  wire width 64 $44
+  wire width 2 $90
+  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744"
+  wire width 1 $91
+  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744"
+  cell $reduce_bool $92
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 4
+    parameter \Y_WIDTH 1
+    connect \A \alu_pulsem
+    connect \Y $91
+  end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
-  cell $mux $45
-    parameter \WIDTH 64
-    connect \A \ea_r
-    connect \B \alu_o
-    connect \S \alu_l_q_alu
-    connect \Y $44
+  cell $mux $93
+    parameter \WIDTH 2
+    connect \A { \data_r3_l__xer_so_ok \data_r3_l__xer_so }
+    connect \B { \xer_so_ok \alu_mul0_xer_so }
+    connect \S $91
+    connect \Y $90
   end
-  process $group_64
-    assign \addr_r 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \addr_r $44
+  process $group_67
+    assign \data_r3__xer_so 1'0
+    assign \data_r3__xer_so_ok 1'0
+    assign { \data_r3__xer_so_ok \data_r3__xer_so } $90
     sync init
   end
-  process $group_65
-    assign \ea_r$next \ea_r
+  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
+  wire width 1 $94
+  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
+  cell $reduce_bool $95
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 4
+    parameter \Y_WIDTH 1
+    connect \A \alu_pulsem
+    connect \Y $94
+  end
+  process $group_69
+    assign \data_r3_l__xer_so$next \data_r3_l__xer_so
+    assign \data_r3_l__xer_so_ok$next \data_r3_l__xer_so_ok
     attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
-    switch { \alu_l_q_alu }
+    switch { $94 }
       attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
       case 1'1
-        assign \ea_r$next \alu_o
+        assign { \data_r3_l__xer_so_ok$next \data_r3_l__xer_so$next } { \xer_so_ok \alu_mul0_xer_so }
+    end
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
+      case 1'1
+        assign \data_r3_l__xer_so_ok$next 1'0
     end
     sync init
-      update \ea_r 64'0000000000000000000000000000000000000000000000000000000000000000
-    sync posedge \clk
-      update \ea_r \ea_r$next
+      update \data_r3_l__xer_so 1'0
+      update \data_r3_l__xer_so_ok 1'0
+    sync posedge \coresync_clk
+      update \data_r3_l__xer_so \data_r3_l__xer_so$next
+      update \data_r3_l__xer_so_ok \data_r3_l__xer_so_ok$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:383"
-  wire width 64 \src1_or_z
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:384"
-  wire width 64 $46
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:384"
-  cell $mux $47
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278"
+  wire width 1 $96
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278"
+  cell $and $97
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \data_r0__o_ok
+    connect \B \cu_busy_o
+    connect \Y $96
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278"
+  wire width 1 $98
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278"
+  cell $and $99
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \data_r1__cr_a_ok
+    connect \B \cu_busy_o
+    connect \Y $98
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278"
+  wire width 1 $100
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278"
+  cell $and $101
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \data_r2__xer_ov_ok
+    connect \B \cu_busy_o
+    connect \Y $100
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278"
+  wire width 1 $102
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278"
+  cell $and $103
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \data_r3__xer_so_ok
+    connect \B \cu_busy_o
+    connect \Y $102
+  end
+  process $group_71
+    assign \cu_wrmask_o 4'0000
+    assign \cu_wrmask_o { $102 $100 $98 $96 }
+    sync init
+  end
+  process $group_72
+    assign \alu_mul0_mul_op__insn_type 7'0000000
+    assign \alu_mul0_mul_op__fn_unit 11'00000000000
+    assign \alu_mul0_mul_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \alu_mul0_mul_op__imm_data__imm_ok 1'0
+    assign \alu_mul0_mul_op__rc__rc 1'0
+    assign \alu_mul0_mul_op__rc__rc_ok 1'0
+    assign \alu_mul0_mul_op__oe__oe 1'0
+    assign \alu_mul0_mul_op__oe__oe_ok 1'0
+    assign \alu_mul0_mul_op__invert_a 1'0
+    assign \alu_mul0_mul_op__zero_a 1'0
+    assign \alu_mul0_mul_op__invert_out 1'0
+    assign \alu_mul0_mul_op__write_cr0 1'0
+    assign \alu_mul0_mul_op__is_32bit 1'0
+    assign \alu_mul0_mul_op__is_signed 1'0
+    assign \alu_mul0_mul_op__insn 32'00000000000000000000000000000000
+    assign { \alu_mul0_mul_op__insn \alu_mul0_mul_op__is_signed \alu_mul0_mul_op__is_32bit \alu_mul0_mul_op__write_cr0 \alu_mul0_mul_op__invert_out \alu_mul0_mul_op__zero_a \alu_mul0_mul_op__invert_a { \alu_mul0_mul_op__oe__oe_ok \alu_mul0_mul_op__oe__oe } { \alu_mul0_mul_op__rc__rc_ok \alu_mul0_mul_op__rc__rc } { \alu_mul0_mul_op__imm_data__imm_ok \alu_mul0_mul_op__imm_data__imm } \alu_mul0_mul_op__fn_unit \alu_mul0_mul_op__insn_type } { \oper_r__insn \oper_r__is_signed \oper_r__is_32bit \oper_r__write_cr0 \oper_r__invert_out \oper_r__zero_a \oper_r__invert_a { \oper_r__oe__oe_ok \oper_r__oe__oe } { \oper_r__rc__rc_ok \oper_r__rc__rc } { \oper_r__imm_data__imm_ok \oper_r__imm_data__imm } \oper_r__fn_unit \oper_r__insn_type }
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:166"
+  wire width 1 \src_sel
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:167"
+  wire width 1 $104
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:167"
+  cell $mux $105
+    parameter \WIDTH 1
+    connect \A \src_l_q_src [0]
+    connect \B \opc_l_q_opc
+    connect \S \oper_r__zero_a
+    connect \Y $104
+  end
+  process $group_87
+    assign \src_sel 1'0
+    assign \src_sel $104
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:165"
+  wire width 64 \src_or_imm
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168"
+  wire width 64 $106
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168"
+  cell $mux $107
     parameter \WIDTH 64
-    connect \A \src_r0
+    connect \A \src1_i
     connect \B 64'0000000000000000000000000000000000000000000000000000000000000000
     connect \S \oper_r__zero_a
-    connect \Y $46
+    connect \Y $106
   end
-  process $group_66
-    assign \src1_or_z 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \src1_or_z $46
+  process $group_88
+    assign \src_or_imm 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \src_or_imm $106
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:388"
-  wire width 64 \src2_or_imm
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:389"
-  wire width 64 $48
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:389"
-  cell $mux $49
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:166"
+  wire width 1 \src_sel$108
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:167"
+  wire width 1 $109
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:167"
+  cell $mux $110
+    parameter \WIDTH 1
+    connect \A \src_l_q_src [1]
+    connect \B \opc_l_q_opc
+    connect \S \oper_r__imm_data__imm_ok
+    connect \Y $109
+  end
+  process $group_89
+    assign \src_sel$108 1'0
+    assign \src_sel$108 $109
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:165"
+  wire width 64 \src_or_imm$111
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168"
+  wire width 64 $112
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168"
+  cell $mux $113
     parameter \WIDTH 64
-    connect \A \src_r1
+    connect \A \src2_i
     connect \B \oper_r__imm_data__imm
     connect \S \oper_r__imm_data__imm_ok
-    connect \Y $48
+    connect \Y $112
   end
-  process $group_67
-    assign \src2_or_imm 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \src2_or_imm $48
+  process $group_90
+    assign \src_or_imm$111 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \src_or_imm$111 $112
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:392"
-  wire width 65 $50
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:392"
-  wire width 65 $51
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:392"
-  cell $add $52
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 64
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 64
-    parameter \Y_WIDTH 65
-    connect \A \src1_or_z
-    connect \B \src2_or_imm
-    connect \Y $51
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
+  wire width 64 \src_r0
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
+  wire width 64 \src_r0$next
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
+  wire width 64 $114
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
+  cell $mux $115
+    parameter \WIDTH 64
+    connect \A \src_r0
+    connect \B \src_or_imm
+    connect \S \src_sel
+    connect \Y $114
   end
-  connect $50 $51
-  process $group_68
-    assign \alu_o$next \alu_o
-    assign \alu_o$next $50 [63:0]
+  process $group_91
+    assign \alu_mul0_ra 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \alu_mul0_ra $114
     sync init
-      update \alu_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    sync posedge \clk
-      update \alu_o \alu_o$next
   end
-  process $group_69
-    assign \alu_ok$next \alu_ok
-    assign \alu_ok$next \alu_valid
+  process $group_92
+    assign \src_r0$next \src_r0
+    attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
+    switch { \src_sel }
+      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
+      case 1'1
+        assign \src_r0$next \src_or_imm
+    end
     sync init
-      update \alu_ok 1'0
-    sync posedge \clk
-      update \alu_ok \alu_ok$next
+      update \src_r0 64'0000000000000000000000000000000000000000000000000000000000000000
+    sync posedge \coresync_clk
+      update \src_r0 \src_r0$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:396"
-  wire width 1 $53
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:396"
-  cell $eq $54
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 7
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 7
-    parameter \Y_WIDTH 1
-    connect \A \oper_r__insn_type
-    connect \B 7'0100110
-    connect \Y $53
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
+  wire width 64 \src_r1
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
+  wire width 64 \src_r1$next
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
+  wire width 64 $116
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
+  cell $mux $117
+    parameter \WIDTH 64
+    connect \A \src_r1
+    connect \B \src_or_imm$111
+    connect \S \src_sel$108
+    connect \Y $116
   end
-  process $group_70
-    assign \op_is_st 1'0
-    assign \op_is_st $53
+  process $group_93
+    assign \alu_mul0_rb 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \alu_mul0_rb $116
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:264"
-  wire width 1 \op_is_ld
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:397"
-  wire width 1 $55
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:397"
-  cell $eq $56
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 7
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 7
-    parameter \Y_WIDTH 1
-    connect \A \oper_r__insn_type
-    connect \B 7'0100101
-    connect \Y $55
+  process $group_94
+    assign \src_r1$next \src_r1
+    attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
+    switch { \src_sel$108 }
+      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
+      case 1'1
+        assign \src_r1$next \src_or_imm$111
+    end
+    sync init
+      update \src_r1 64'0000000000000000000000000000000000000000000000000000000000000000
+    sync posedge \coresync_clk
+      update \src_r1 \src_r1$next
   end
-  process $group_71
-    assign \op_is_ld 1'0
-    assign \op_is_ld $55
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
+  wire width 1 \src_r2
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
+  wire width 1 \src_r2$next
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
+  wire width 1 $118
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
+  cell $mux $119
+    parameter \WIDTH 1
+    connect \A \src_r2
+    connect \B \src3_i
+    connect \S \src_l_q_src [2]
+    connect \Y $118
+  end
+  process $group_95
+    assign \alu_mul0_xer_so$1 1'0
+    assign \alu_mul0_xer_so$1 $118
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:112"
-  wire width 1 \load_mem_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:400"
-  wire width 1 $57
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:400"
-  cell $and $58
+  process $group_96
+    assign \src_r2$next \src_r2
+    attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
+    switch { \src_l_q_src [2] }
+      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
+      case 1'1
+        assign \src_r2$next \src3_i
+    end
+    sync init
+      update \src_r2 1'0
+    sync posedge \coresync_clk
+      update \src_r2 \src_r2$next
+  end
+  process $group_97
+    assign \alu_mul0_p_valid_i 1'0
+    assign \alu_mul0_p_valid_i \alui_l_q_alui
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:329"
+  wire width 1 $120
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:329"
+  cell $and $121
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \op_is_ld
-    connect \B \cu_ad__go_i
-    connect \Y $57
+    connect \A \alu_mul0_p_ready_o
+    connect \B \alui_l_q_alui
+    connect \Y $120
   end
-  process $group_72
-    assign \load_mem_o 1'0
-    assign \load_mem_o $57
+  process $group_98
+    assign \alui_l_r_alui$next \alui_l_r_alui
+    assign \alui_l_r_alui$next $120
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
+      case 1'1
+        assign \alui_l_r_alui$next 1'1
+    end
+    sync init
+      update \alui_l_r_alui 1'1
+    sync posedge \coresync_clk
+      update \alui_l_r_alui \alui_l_r_alui$next
+  end
+  process $group_99
+    assign \alui_l_s_alui 1'0
+    assign \alui_l_s_alui \all_rd_pulse
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:113"
-  wire width 1 \stwd_mem_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:401"
-  wire width 1 $59
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:401"
-  cell $and $60
+  process $group_100
+    assign \alu_mul0_n_ready_i 1'0
+    assign \alu_mul0_n_ready_i \alu_l_q_alu
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:336"
+  wire width 1 $122
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:336"
+  cell $and $123
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \op_is_st
-    connect \B \cu_st__go_i
-    connect \Y $59
-  end
-  process $group_73
-    assign \stwd_mem_o 1'0
-    assign \stwd_mem_o $59
-    sync init
+    connect \A \alu_mul0_n_valid_o
+    connect \B \alu_l_q_alu
+    connect \Y $122
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:108"
-  wire width 1 \ld_o
-  process $group_74
-    assign \ld_o 1'0
-    assign \ld_o \op_is_ld
+  process $group_101
+    assign \alu_l_r_alu$next \alu_l_r_alu
+    assign \alu_l_r_alu$next $122
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
+      case 1'1
+        assign \alu_l_r_alu$next 1'1
+    end
     sync init
+      update \alu_l_r_alu 1'1
+    sync posedge \coresync_clk
+      update \alu_l_r_alu \alu_l_r_alu$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:109"
-  wire width 1 \st_o
-  process $group_75
-    assign \st_o 1'0
-    assign \st_o \op_is_st
+  process $group_102
+    assign \alu_l_s_alu 1'0
+    assign \alu_l_s_alu \all_rd_pulse
     sync init
   end
-  process $group_76
+  process $group_103
     assign \cu_busy_o 1'0
     assign \cu_busy_o \opc_l_q_opc
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:416"
-  wire width 3 $61
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:416"
-  cell $and $62
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+  wire width 3 $124
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+  cell $and $125
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
@@ -110511,872 +111418,366 @@ module \ldst0
     parameter \Y_WIDTH 3
     connect \A \src_l_q_src
     connect \B { \cu_busy_o \cu_busy_o \cu_busy_o }
-    connect \Y $61
+    connect \Y $124
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:416"
-  wire width 2 $63
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:416"
-  cell $not $64
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:172"
+  wire width 1 $126
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:172"
+  cell $not $127
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 2
-    parameter \Y_WIDTH 2
-    connect \A { \oper_r__imm_data__imm_ok \oper_r__zero_a }
-    connect \Y $63
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \oper_r__zero_a
+    connect \Y $126
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:416"
-  wire width 3 $65
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:416"
-  cell $and $66
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:172"
+  wire width 1 $128
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:172"
+  cell $not $129
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 3
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 2
-    parameter \Y_WIDTH 3
-    connect \A $61
-    connect \B $63
-    connect \Y $65
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \oper_r__imm_data__imm_ok
+    connect \Y $128
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:416"
-  wire width 3 $67
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:416"
-  cell $not $68
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+  wire width 3 $130
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+  cell $and $131
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 3
     parameter \Y_WIDTH 3
-    connect \A \cu_rdmaskn_i
-    connect \Y $67
+    connect \A $124
+    connect \B { 1'1 $128 $126 }
+    connect \Y $130
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:416"
-  wire width 3 $69
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:416"
-  cell $and $70
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+  wire width 3 $132
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+  cell $not $133
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 3
     parameter \Y_WIDTH 3
-    connect \A $65
-    connect \B $67
-    connect \Y $69
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:425"
-  wire width 1 $71
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:425"
-  cell $and $72
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \src_l_q_src [2]
-    connect \B \cu_busy_o
-    connect \Y $71
+    connect \A \cu_rdmaskn_i
+    connect \Y $132
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:425"
-  wire width 1 $73
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:425"
-  cell $and $74
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+  wire width 3 $134
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+  cell $and $135
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
+    parameter \A_WIDTH 3
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A $71
-    connect \B \op_is_st
-    connect \Y $73
+    parameter \B_WIDTH 3
+    parameter \Y_WIDTH 3
+    connect \A $130
+    connect \B $132
+    connect \Y $134
   end
-  process $group_77
+  process $group_104
     assign \cu_rd__rel_o 3'000
-    assign \cu_rd__rel_o $69
-    assign \cu_rd__rel_o [2] $73
+    assign \cu_rd__rel_o $134
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:419"
-  wire width 1 $75
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:419"
-  cell $or $76
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:101"
+  wire width 1 \cu_shadown_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352"
+  wire width 1 $136
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352"
+  cell $and $137
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \cu_rd__go_i [0]
-    connect \B \cu_rd__go_i [1]
-    connect \Y $75
-  end
-  process $group_78
-    assign \rda_any 1'0
-    assign \rda_any $75
-    sync init
+    connect \A \cu_busy_o
+    connect \B \cu_shadown_i
+    connect \Y $136
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:422"
-  wire width 1 $77
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:422"
-  wire width 1 $78
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:422"
-  cell $or $79
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352"
+  wire width 1 $138
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352"
+  cell $and $139
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \cu_rd__rel_o [0]
-    connect \B \cu_rd__rel_o [1]
-    connect \Y $78
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:422"
-  cell $not $80
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A $78
-    connect \Y $77
+    connect \A \cu_busy_o
+    connect \B \cu_shadown_i
+    connect \Y $138
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:422"
-  wire width 1 $81
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:422"
-  cell $and $82
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352"
+  wire width 1 $140
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352"
+  cell $and $141
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \cu_busy_o
-    connect \B $77
-    connect \Y $81
-  end
-  process $group_79
-    assign \alu_valid 1'0
-    assign \alu_valid $81
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:274"
-  wire width 1 \rd_done
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428"
-  wire width 1 $83
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428"
-  cell $not $84
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \cu_rd__rel_o [2]
-    connect \Y $83
+    connect \B \cu_shadown_i
+    connect \Y $140
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428"
-  wire width 1 $85
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428"
-  cell $and $86
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352"
+  wire width 1 $142
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352"
+  cell $and $143
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \alu_valid
-    connect \B $83
-    connect \Y $85
-  end
-  process $group_80
-    assign \rd_done 1'0
-    assign \rd_done $85
-    sync init
+    connect \A \cu_busy_o
+    connect \B \cu_shadown_i
+    connect \Y $142
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:431"
-  wire width 1 $87
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:431"
-  cell $and $88
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:353"
+  wire width 4 $144
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:353"
+  cell $and $145
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
+    parameter \A_WIDTH 4
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \alu_valid
-    connect \B \adr_l_q_adr
-    connect \Y $87
+    parameter \B_WIDTH 4
+    parameter \Y_WIDTH 4
+    connect \A \req_l_q_req
+    connect \B { $136 $138 $140 $142 }
+    connect \Y $144
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:431"
-  wire width 1 $89
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:431"
-  cell $and $90
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:353"
+  wire width 4 $146
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:353"
+  cell $and $147
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
+    parameter \A_WIDTH 4
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A $87
-    connect \B \cu_busy_o
-    connect \Y $89
+    parameter \B_WIDTH 4
+    parameter \Y_WIDTH 4
+    connect \A $144
+    connect \B \cu_wrmask_o
+    connect \Y $146
   end
-  process $group_81
-    assign \cu_ad__rel_o 1'0
-    assign \cu_ad__rel_o $89
+  process $group_105
+    assign \cu_wr__rel_o 4'0000
+    assign \cu_wr__rel_o $146
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434"
-  wire width 1 $91
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434"
-  cell $and $92
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
+  wire width 1 $148
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
+  cell $and $149
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \sto_l_q_sto
+    connect \A \cu_wr__go_i [0]
     connect \B \cu_busy_o
-    connect \Y $91
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434"
-  wire width 1 $93
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434"
-  cell $and $94
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A $91
-    connect \B \rd_done
-    connect \Y $93
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434"
-  wire width 1 $95
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434"
-  cell $and $96
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A $93
-    connect \B \op_is_st
-    connect \Y $95
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:101"
-  wire width 1 \cu_shadown_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:435"
-  wire width 1 $97
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:435"
-  cell $and $98
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A $95
-    connect \B \cu_shadown_i
-    connect \Y $97
+    connect \Y $148
   end
-  process $group_82
-    assign \cu_st__rel_o 1'0
-    assign \cu_st__rel_o $97
+  process $group_106
+    assign \dest1_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
+    switch { $148 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
+      case 1'1
+        assign \dest1_o { \data_r0__o_ok \data_r0__o } [63:0]
+    end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:439"
-  wire width 1 $99
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:439"
-  cell $and $100
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \rd_done
-    connect \B \wri_l_q_wri
-    connect \Y $99
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:439"
-  wire width 1 $101
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:439"
-  cell $and $102
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
+  wire width 1 $150
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
+  cell $and $151
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $99
+    connect \A \cu_wr__go_i [1]
     connect \B \cu_busy_o
-    connect \Y $101
+    connect \Y $150
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:439"
-  wire width 1 $103
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:439"
-  cell $and $104
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A $101
-    connect \B \lod_l_qn_lod
-    connect \Y $103
+  process $group_107
+    assign \dest2_o 4'0000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
+    switch { $150 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
+      case 1'1
+        assign \dest2_o { \data_r1__cr_a_ok \data_r1__cr_a } [3:0]
+    end
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:439"
-  wire width 1 $105
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:439"
-  cell $and $106
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
+  wire width 1 $152
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
+  cell $and $153
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $103
-    connect \B \op_is_ld
-    connect \Y $105
+    connect \A \cu_wr__go_i [2]
+    connect \B \cu_busy_o
+    connect \Y $152
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:439"
-  wire width 1 $107
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:439"
-  cell $and $108
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A $105
-    connect \B \cu_shadown_i
-    connect \Y $107
+  process $group_108
+    assign \dest3_o 2'00
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
+    switch { $152 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
+      case 1'1
+        assign \dest3_o { \data_r2__xer_ov_ok \data_r2__xer_ov } [1:0]
+    end
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:443"
-  wire width 1 $109
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:443"
-  cell $and $110
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
+  wire width 1 $154
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
+  cell $and $155
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \upd_l_q_upd
+    connect \A \cu_wr__go_i [3]
     connect \B \cu_busy_o
-    connect \Y $109
+    connect \Y $154
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:398"
-  wire width 1 $111
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:398"
-  cell $eq $112
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 2
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 2
-    parameter \Y_WIDTH 1
-    connect \A \oper_r__ldst_mode
-    connect \B 2'01
-    connect \Y $111
+  process $group_109
+    assign \dest4_o 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
+    switch { $154 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
+      case 1'1
+        assign \dest4_o { \data_r3__xer_so_ok \data_r3__xer_so } [0]
+    end
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:443"
-  wire width 1 $113
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:443"
-  cell $and $114
+  connect \cu_go_die_i 1'0
+  connect \cu_shadown_i 1'1
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.p"
+module \p$104
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153"
+  wire width 1 input 0 \p_valid_i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154"
+  wire width 1 input 1 \p_ready_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158"
+  wire width 1 \trigger
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205"
+  wire width 1 $1
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205"
+  cell $and $2
     parameter \A_SIGNED 0
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-          attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:14"
-          case 4'0001
-            assign \stdata_r [7:0] \src_r2 [7:0]
-          attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:14"
-          case 4'0010
-            assign \stdata_r [7:0] \src_r2 [15:8]
-            assign \stdata_r [15:8] \src_r2 [7:0]
-          attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:14"
-          case 4'0100
-            assign \stdata_r [7:0] \src_r2 [31:24]
-            assign \stdata_r [15:8] \src_r2 [23:16]
-            assign \stdata_r [23:16] \src_r2 [15:8]
-            assign \stdata_r [31:24] \src_r2 [7:0]
-          attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:14"
-          case 4'1000
-            assign \stdata_r [7:0] \src_r2 [63:56]
-            assign \stdata_r [15:8] \src_r2 [55:48]
-            assign \stdata_r [23:16] \src_r2 [47:40]
-            assign \stdata_r [31:24] \src_r2 [39:32]
-            assign \stdata_r [39:32] \src_r2 [31:24]
-            assign \stdata_r [47:40] \src_r2 [23:16]
-            assign \stdata_r [55:48] \src_r2 [15:8]
-            assign \stdata_r [63:56] \src_r2 [7:0]
-        end
-    end
-    sync init
-  end
-  process $group_104
-    assign \ldst_port0_st_data_i_ok 1'0
-    assign \ldst_port0_st_data_i_ok \cu_st__go_i
+  process $group_0
+    assign \trigger 1'0
+    assign \trigger $1
     sync init
   end
-  connect \cu_go_die_i 1'0
-  connect \cu_shadown_i 1'1
 end
 attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.fus"
-module \fus
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 1 input 0 \cu_ad__go_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 1 output 1 \cu_ad__rel_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 1 input 2 \cu_st__go_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 1 output 3 \cu_st__rel_o
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 4 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 5 \clk
+attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe.input"
+module \input$109
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
+  wire width 2 input 0 \muxid
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
   attribute \enum_value_0000001 "OP_NOP"
@@ -111451,7 +111852,7 @@ module \fus
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 7 input 6 \oper_i_alu_alu0__insn_type
+  wire width 7 input 1 \sr_op__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -111465,49 +111866,47 @@ module \fus
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 11 input 7 \oper_i_alu_alu0__fn_unit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 64 input 8 \oper_i_alu_alu0__imm_data__imm
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 9 \oper_i_alu_alu0__imm_data__imm_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 10 \oper_i_alu_alu0__rc__rc
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 11 \oper_i_alu_alu0__rc__rc_ok
+  wire width 11 input 2 \sr_op__fn_unit
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 12 \oper_i_alu_alu0__oe__oe
+  wire width 64 input 3 \sr_op__imm_data__imm
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 13 \oper_i_alu_alu0__oe__oe_ok
+  wire width 1 input 4 \sr_op__imm_data__imm_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 14 \oper_i_alu_alu0__invert_a
+  wire width 1 input 5 \sr_op__rc__rc
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 15 \oper_i_alu_alu0__zero_a
+  wire width 1 input 6 \sr_op__rc__rc_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 16 \oper_i_alu_alu0__invert_out
+  wire width 1 input 7 \sr_op__oe__oe
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 17 \oper_i_alu_alu0__write_cr0
+  wire width 1 input 8 \sr_op__oe__oe_ok
   attribute \enum_base_type "CryIn"
   attribute \enum_value_00 "ZERO"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "CA"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 2 input 18 \oper_i_alu_alu0__input_carry
+  wire width 2 input 10 \sr_op__input_carry
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 19 \oper_i_alu_alu0__output_carry
+  wire width 1 input 11 \sr_op__output_carry
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 20 \oper_i_alu_alu0__is_32bit
+  wire width 1 input 12 \sr_op__input_cr
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 21 \oper_i_alu_alu0__is_signed
+  wire width 1 input 13 \sr_op__output_cr
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 4 input 22 \oper_i_alu_alu0__data_len
+  wire width 1 input 14 \sr_op__is_32bit
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 32 input 23 \oper_i_alu_alu0__insn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
-  wire width 1 input 24 \cu_issue_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:106"
-  wire width 1 output 25 \cu_busy_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
-  wire width 4 input 26 \cu_rdmaskn_i
+  wire width 1 input 15 \sr_op__is_signed
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 input 16 \sr_op__insn
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
+  wire width 64 input 17 \ra
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
+  wire width 64 input 18 \rb
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
+  wire width 64 input 19 \rc
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
+  wire width 2 input 20 \xer_ca
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
+  wire width 2 output 21 \muxid$1
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
   attribute \enum_value_0000001 "OP_NOP"
@@ -111582,7 +111981,7 @@ module \fus
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 7 input 27 \oper_i_alu_cr0__insn_type
+  wire width 7 output 22 \sr_op__insn_type$2
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -111596,14100 +111995,28277 @@ module \fus
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 11 input 28 \oper_i_alu_cr0__fn_unit
+  wire width 11 output 23 \sr_op__fn_unit$3
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 32 input 29 \oper_i_alu_cr0__insn
+  wire width 64 output 24 \sr_op__imm_data__imm$4
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 30 \oper_i_alu_cr0__read_cr_whole
+  wire width 1 output 25 \sr_op__imm_data__imm_ok$5
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 31 \oper_i_alu_cr0__write_cr_whole
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
-  wire width 1 input 32 \cu_issue_i$1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:106"
-  wire width 1 output 33 \cu_busy_o$2
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
-  wire width 6 input 34 \cu_rdmaskn_i$3
+  wire width 1 output 26 \sr_op__rc__rc$6
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 64 input 35 \oper_i_alu_branch0__cia
-  attribute \enum_base_type "MicrOp"
-  attribute \enum_value_0000000 "OP_ILLEGAL"
-  attribute \enum_value_0000001 "OP_NOP"
-  attribute \enum_value_0000010 "OP_ADD"
-  attribute \enum_value_0000011 "OP_ADDPCIS"
-  attribute \enum_value_0000100 "OP_AND"
-  attribute \enum_value_0000101 "OP_ATTN"
-  attribute \enum_value_0000110 "OP_B"
-  attribute \enum_value_0000111 "OP_BC"
-  attribute \enum_value_0001000 "OP_BCREG"
-  attribute \enum_value_0001001 "OP_BPERM"
-  attribute \enum_value_0001010 "OP_CMP"
-  attribute \enum_value_0001011 "OP_CMPB"
-  attribute \enum_value_0001100 "OP_CMPEQB"
-  attribute \enum_value_0001101 "OP_CMPRB"
-  attribute \enum_value_0001110 "OP_CNTZ"
-  attribute \enum_value_0001111 "OP_CRAND"
-  attribute \enum_value_0010000 "OP_CRANDC"
-  attribute \enum_value_0010001 "OP_CREQV"
-  attribute \enum_value_0010010 "OP_CRNAND"
-  attribute \enum_value_0010011 "OP_CRNOR"
-  attribute \enum_value_0010100 "OP_CROR"
-  attribute \enum_value_0010101 "OP_CRORC"
-  attribute \enum_value_0010110 "OP_CRXOR"
-  attribute \enum_value_0010111 "OP_DARN"
-  attribute \enum_value_0011000 "OP_DCBF"
-  attribute \enum_value_0011001 "OP_DCBST"
-  attribute \enum_value_0011010 "OP_DCBT"
-  attribute \enum_value_0011011 "OP_DCBTST"
-  attribute \enum_value_0011100 "OP_DCBZ"
-  attribute \enum_value_0011101 "OP_DIV"
-  attribute \enum_value_0011110 "OP_DIVE"
-  attribute \enum_value_0011111 "OP_EXTS"
-  attribute \enum_value_0100000 "OP_EXTSWSLI"
-  attribute \enum_value_0100001 "OP_ICBI"
-  attribute \enum_value_0100010 "OP_ICBT"
-  attribute \enum_value_0100011 "OP_ISEL"
-  attribute \enum_value_0100100 "OP_ISYNC"
-  attribute \enum_value_0100101 "OP_LOAD"
-  attribute \enum_value_0100110 "OP_STORE"
-  attribute \enum_value_0100111 "OP_MADDHD"
-  attribute \enum_value_0101000 "OP_MADDHDU"
-  attribute \enum_value_0101001 "OP_MADDLD"
-  attribute \enum_value_0101010 "OP_MCRF"
-  attribute \enum_value_0101011 "OP_MCRXR"
-  attribute \enum_value_0101100 "OP_MCRXRX"
-  attribute \enum_value_0101101 "OP_MFCR"
-  attribute \enum_value_0101110 "OP_MFSPR"
-  attribute \enum_value_0101111 "OP_MOD"
-  attribute \enum_value_0110000 "OP_MTCRF"
-  attribute \enum_value_0110001 "OP_MTSPR"
-  attribute \enum_value_0110010 "OP_MUL_L64"
-  attribute \enum_value_0110011 "OP_MUL_H64"
-  attribute \enum_value_0110100 "OP_MUL_H32"
-  attribute \enum_value_0110101 "OP_OR"
-  attribute \enum_value_0110110 "OP_POPCNT"
-  attribute \enum_value_0110111 "OP_PRTY"
-  attribute \enum_value_0111000 "OP_RLC"
-  attribute \enum_value_0111001 "OP_RLCL"
-  attribute \enum_value_0111010 "OP_RLCR"
-  attribute \enum_value_0111011 "OP_SETB"
-  attribute \enum_value_0111100 "OP_SHL"
-  attribute \enum_value_0111101 "OP_SHR"
-  attribute \enum_value_0111110 "OP_SYNC"
-  attribute \enum_value_0111111 "OP_TRAP"
-  attribute \enum_value_1000011 "OP_XOR"
-  attribute \enum_value_1000100 "OP_SIM_CONFIG"
-  attribute \enum_value_1000101 "OP_CROP"
-  attribute \enum_value_1000110 "OP_RFID"
-  attribute \enum_value_1000111 "OP_MFMSR"
-  attribute \enum_value_1001000 "OP_MTMSRD"
-  attribute \enum_value_1001001 "OP_SC"
-  attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 7 input 36 \oper_i_alu_branch0__insn_type
-  attribute \enum_base_type "Function"
-  attribute \enum_value_00000000000 "NONE"
-  attribute \enum_value_00000000010 "ALU"
-  attribute \enum_value_00000000100 "LDST"
-  attribute \enum_value_00000001000 "SHIFT_ROT"
-  attribute \enum_value_00000010000 "LOGICAL"
-  attribute \enum_value_00000100000 "BRANCH"
-  attribute \enum_value_00001000000 "CR"
-  attribute \enum_value_00010000000 "TRAP"
-  attribute \enum_value_00100000000 "MUL"
-  attribute \enum_value_01000000000 "DIV"
-  attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 11 input 37 \oper_i_alu_branch0__fn_unit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 32 input 38 \oper_i_alu_branch0__insn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 64 input 39 \oper_i_alu_branch0__imm_data__imm
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 40 \oper_i_alu_branch0__imm_data__imm_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 41 \oper_i_alu_branch0__lk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 42 \oper_i_alu_branch0__is_32bit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
-  wire width 1 input 43 \cu_issue_i$4
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:106"
-  wire width 1 output 44 \cu_busy_o$5
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
-  wire width 3 input 45 \cu_rdmaskn_i$6
-  attribute \enum_base_type "MicrOp"
-  attribute \enum_value_0000000 "OP_ILLEGAL"
-  attribute \enum_value_0000001 "OP_NOP"
-  attribute \enum_value_0000010 "OP_ADD"
-  attribute \enum_value_0000011 "OP_ADDPCIS"
-  attribute \enum_value_0000100 "OP_AND"
-  attribute \enum_value_0000101 "OP_ATTN"
-  attribute \enum_value_0000110 "OP_B"
-  attribute \enum_value_0000111 "OP_BC"
-  attribute \enum_value_0001000 "OP_BCREG"
-  attribute \enum_value_0001001 "OP_BPERM"
-  attribute \enum_value_0001010 "OP_CMP"
-  attribute \enum_value_0001011 "OP_CMPB"
-  attribute \enum_value_0001100 "OP_CMPEQB"
-  attribute \enum_value_0001101 "OP_CMPRB"
-  attribute \enum_value_0001110 "OP_CNTZ"
-  attribute \enum_value_0001111 "OP_CRAND"
-  attribute \enum_value_0010000 "OP_CRANDC"
-  attribute \enum_value_0010001 "OP_CREQV"
-  attribute \enum_value_0010010 "OP_CRNAND"
-  attribute \enum_value_0010011 "OP_CRNOR"
-  attribute \enum_value_0010100 "OP_CROR"
-  attribute \enum_value_0010101 "OP_CRORC"
-  attribute \enum_value_0010110 "OP_CRXOR"
-  attribute \enum_value_0010111 "OP_DARN"
-  attribute \enum_value_0011000 "OP_DCBF"
-  attribute \enum_value_0011001 "OP_DCBST"
-  attribute \enum_value_0011010 "OP_DCBT"
-  attribute \enum_value_0011011 "OP_DCBTST"
-  attribute \enum_value_0011100 "OP_DCBZ"
-  attribute \enum_value_0011101 "OP_DIV"
-  attribute \enum_value_0011110 "OP_DIVE"
-  attribute \enum_value_0011111 "OP_EXTS"
-  attribute \enum_value_0100000 "OP_EXTSWSLI"
-  attribute \enum_value_0100001 "OP_ICBI"
-  attribute \enum_value_0100010 "OP_ICBT"
-  attribute \enum_value_0100011 "OP_ISEL"
-  attribute \enum_value_0100100 "OP_ISYNC"
-  attribute \enum_value_0100101 "OP_LOAD"
-  attribute \enum_value_0100110 "OP_STORE"
-  attribute \enum_value_0100111 "OP_MADDHD"
-  attribute \enum_value_0101000 "OP_MADDHDU"
-  attribute \enum_value_0101001 "OP_MADDLD"
-  attribute \enum_value_0101010 "OP_MCRF"
-  attribute \enum_value_0101011 "OP_MCRXR"
-  attribute \enum_value_0101100 "OP_MCRXRX"
-  attribute \enum_value_0101101 "OP_MFCR"
-  attribute \enum_value_0101110 "OP_MFSPR"
-  attribute \enum_value_0101111 "OP_MOD"
-  attribute \enum_value_0110000 "OP_MTCRF"
-  attribute \enum_value_0110001 "OP_MTSPR"
-  attribute \enum_value_0110010 "OP_MUL_L64"
-  attribute \enum_value_0110011 "OP_MUL_H64"
-  attribute \enum_value_0110100 "OP_MUL_H32"
-  attribute \enum_value_0110101 "OP_OR"
-  attribute \enum_value_0110110 "OP_POPCNT"
-  attribute \enum_value_0110111 "OP_PRTY"
-  attribute \enum_value_0111000 "OP_RLC"
-  attribute \enum_value_0111001 "OP_RLCL"
-  attribute \enum_value_0111010 "OP_RLCR"
-  attribute \enum_value_0111011 "OP_SETB"
-  attribute \enum_value_0111100 "OP_SHL"
-  attribute \enum_value_0111101 "OP_SHR"
-  attribute \enum_value_0111110 "OP_SYNC"
-  attribute \enum_value_0111111 "OP_TRAP"
-  attribute \enum_value_1000011 "OP_XOR"
-  attribute \enum_value_1000100 "OP_SIM_CONFIG"
-  attribute \enum_value_1000101 "OP_CROP"
-  attribute \enum_value_1000110 "OP_RFID"
-  attribute \enum_value_1000111 "OP_MFMSR"
-  attribute \enum_value_1001000 "OP_MTMSRD"
-  attribute \enum_value_1001001 "OP_SC"
-  attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 7 input 46 \oper_i_alu_trap0__insn_type
-  attribute \enum_base_type "Function"
-  attribute \enum_value_00000000000 "NONE"
-  attribute \enum_value_00000000010 "ALU"
-  attribute \enum_value_00000000100 "LDST"
-  attribute \enum_value_00000001000 "SHIFT_ROT"
-  attribute \enum_value_00000010000 "LOGICAL"
-  attribute \enum_value_00000100000 "BRANCH"
-  attribute \enum_value_00001000000 "CR"
-  attribute \enum_value_00010000000 "TRAP"
-  attribute \enum_value_00100000000 "MUL"
-  attribute \enum_value_01000000000 "DIV"
-  attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 11 input 47 \oper_i_alu_trap0__fn_unit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 32 input 48 \oper_i_alu_trap0__insn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 64 input 49 \oper_i_alu_trap0__msr
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 64 input 50 \oper_i_alu_trap0__cia
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 51 \oper_i_alu_trap0__is_32bit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 5 input 52 \oper_i_alu_trap0__traptype
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 13 input 53 \oper_i_alu_trap0__trapaddr
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
-  wire width 1 input 54 \cu_issue_i$7
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:106"
-  wire width 1 output 55 \cu_busy_o$8
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
-  wire width 4 input 56 \cu_rdmaskn_i$9
-  attribute \enum_base_type "MicrOp"
-  attribute \enum_value_0000000 "OP_ILLEGAL"
-  attribute \enum_value_0000001 "OP_NOP"
-  attribute \enum_value_0000010 "OP_ADD"
-  attribute \enum_value_0000011 "OP_ADDPCIS"
-  attribute \enum_value_0000100 "OP_AND"
-  attribute \enum_value_0000101 "OP_ATTN"
-  attribute \enum_value_0000110 "OP_B"
-  attribute \enum_value_0000111 "OP_BC"
-  attribute \enum_value_0001000 "OP_BCREG"
-  attribute \enum_value_0001001 "OP_BPERM"
-  attribute \enum_value_0001010 "OP_CMP"
-  attribute \enum_value_0001011 "OP_CMPB"
-  attribute \enum_value_0001100 "OP_CMPEQB"
-  attribute \enum_value_0001101 "OP_CMPRB"
-  attribute \enum_value_0001110 "OP_CNTZ"
-  attribute \enum_value_0001111 "OP_CRAND"
-  attribute \enum_value_0010000 "OP_CRANDC"
-  attribute \enum_value_0010001 "OP_CREQV"
-  attribute \enum_value_0010010 "OP_CRNAND"
-  attribute \enum_value_0010011 "OP_CRNOR"
-  attribute \enum_value_0010100 "OP_CROR"
-  attribute \enum_value_0010101 "OP_CRORC"
-  attribute \enum_value_0010110 "OP_CRXOR"
-  attribute \enum_value_0010111 "OP_DARN"
-  attribute \enum_value_0011000 "OP_DCBF"
-  attribute \enum_value_0011001 "OP_DCBST"
-  attribute \enum_value_0011010 "OP_DCBT"
-  attribute \enum_value_0011011 "OP_DCBTST"
-  attribute \enum_value_0011100 "OP_DCBZ"
-  attribute \enum_value_0011101 "OP_DIV"
-  attribute \enum_value_0011110 "OP_DIVE"
-  attribute \enum_value_0011111 "OP_EXTS"
-  attribute \enum_value_0100000 "OP_EXTSWSLI"
-  attribute \enum_value_0100001 "OP_ICBI"
-  attribute \enum_value_0100010 "OP_ICBT"
-  attribute \enum_value_0100011 "OP_ISEL"
-  attribute \enum_value_0100100 "OP_ISYNC"
-  attribute \enum_value_0100101 "OP_LOAD"
-  attribute \enum_value_0100110 "OP_STORE"
-  attribute \enum_value_0100111 "OP_MADDHD"
-  attribute \enum_value_0101000 "OP_MADDHDU"
-  attribute \enum_value_0101001 "OP_MADDLD"
-  attribute \enum_value_0101010 "OP_MCRF"
-  attribute \enum_value_0101011 "OP_MCRXR"
-  attribute \enum_value_0101100 "OP_MCRXRX"
-  attribute \enum_value_0101101 "OP_MFCR"
-  attribute \enum_value_0101110 "OP_MFSPR"
-  attribute \enum_value_0101111 "OP_MOD"
-  attribute \enum_value_0110000 "OP_MTCRF"
-  attribute \enum_value_0110001 "OP_MTSPR"
-  attribute \enum_value_0110010 "OP_MUL_L64"
-  attribute \enum_value_0110011 "OP_MUL_H64"
-  attribute \enum_value_0110100 "OP_MUL_H32"
-  attribute \enum_value_0110101 "OP_OR"
-  attribute \enum_value_0110110 "OP_POPCNT"
-  attribute \enum_value_0110111 "OP_PRTY"
-  attribute \enum_value_0111000 "OP_RLC"
-  attribute \enum_value_0111001 "OP_RLCL"
-  attribute \enum_value_0111010 "OP_RLCR"
-  attribute \enum_value_0111011 "OP_SETB"
-  attribute \enum_value_0111100 "OP_SHL"
-  attribute \enum_value_0111101 "OP_SHR"
-  attribute \enum_value_0111110 "OP_SYNC"
-  attribute \enum_value_0111111 "OP_TRAP"
-  attribute \enum_value_1000011 "OP_XOR"
-  attribute \enum_value_1000100 "OP_SIM_CONFIG"
-  attribute \enum_value_1000101 "OP_CROP"
-  attribute \enum_value_1000110 "OP_RFID"
-  attribute \enum_value_1000111 "OP_MFMSR"
-  attribute \enum_value_1001000 "OP_MTMSRD"
-  attribute \enum_value_1001001 "OP_SC"
-  attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 7 input 57 \oper_i_alu_logical0__insn_type
-  attribute \enum_base_type "Function"
-  attribute \enum_value_00000000000 "NONE"
-  attribute \enum_value_00000000010 "ALU"
-  attribute \enum_value_00000000100 "LDST"
-  attribute \enum_value_00000001000 "SHIFT_ROT"
-  attribute \enum_value_00000010000 "LOGICAL"
-  attribute \enum_value_00000100000 "BRANCH"
-  attribute \enum_value_00001000000 "CR"
-  attribute \enum_value_00010000000 "TRAP"
-  attribute \enum_value_00100000000 "MUL"
-  attribute \enum_value_01000000000 "DIV"
-  attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 11 input 58 \oper_i_alu_logical0__fn_unit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 64 input 59 \oper_i_alu_logical0__imm_data__imm
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 60 \oper_i_alu_logical0__imm_data__imm_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 61 \oper_i_alu_logical0__rc__rc
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 62 \oper_i_alu_logical0__rc__rc_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 63 \oper_i_alu_logical0__oe__oe
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 64 \oper_i_alu_logical0__oe__oe_ok
+  wire width 1 output 27 \sr_op__rc__rc_ok$7
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 65 \oper_i_alu_logical0__invert_a
+  wire width 1 output 28 \sr_op__oe__oe$8
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 66 \oper_i_alu_logical0__zero_a
+  wire width 1 output 29 \sr_op__oe__oe_ok$9
   attribute \enum_base_type "CryIn"
   attribute \enum_value_00 "ZERO"
   attribute \enum_value_01 "ONE"
   attribute \enum_value_10 "CA"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 2 input 67 \oper_i_alu_logical0__input_carry
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 68 \oper_i_alu_logical0__invert_out
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 69 \oper_i_alu_logical0__write_cr0
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 70 \oper_i_alu_logical0__output_carry
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 71 \oper_i_alu_logical0__is_32bit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 72 \oper_i_alu_logical0__is_signed
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 4 input 73 \oper_i_alu_logical0__data_len
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 32 input 74 \oper_i_alu_logical0__insn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
-  wire width 1 input 75 \cu_issue_i$10
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:106"
-  wire width 1 output 76 \cu_busy_o$11
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
-  wire width 2 input 77 \cu_rdmaskn_i$12
-  attribute \enum_base_type "MicrOp"
-  attribute \enum_value_0000000 "OP_ILLEGAL"
-  attribute \enum_value_0000001 "OP_NOP"
-  attribute \enum_value_0000010 "OP_ADD"
-  attribute \enum_value_0000011 "OP_ADDPCIS"
-  attribute \enum_value_0000100 "OP_AND"
-  attribute \enum_value_0000101 "OP_ATTN"
-  attribute \enum_value_0000110 "OP_B"
-  attribute \enum_value_0000111 "OP_BC"
-  attribute \enum_value_0001000 "OP_BCREG"
-  attribute \enum_value_0001001 "OP_BPERM"
-  attribute \enum_value_0001010 "OP_CMP"
-  attribute \enum_value_0001011 "OP_CMPB"
-  attribute \enum_value_0001100 "OP_CMPEQB"
-  attribute \enum_value_0001101 "OP_CMPRB"
-  attribute \enum_value_0001110 "OP_CNTZ"
-  attribute \enum_value_0001111 "OP_CRAND"
-  attribute \enum_value_0010000 "OP_CRANDC"
-  attribute \enum_value_0010001 "OP_CREQV"
-  attribute \enum_value_0010010 "OP_CRNAND"
-  attribute \enum_value_0010011 "OP_CRNOR"
-  attribute \enum_value_0010100 "OP_CROR"
-  attribute \enum_value_0010101 "OP_CRORC"
-  attribute \enum_value_0010110 "OP_CRXOR"
-  attribute \enum_value_0010111 "OP_DARN"
-  attribute \enum_value_0011000 "OP_DCBF"
-  attribute \enum_value_0011001 "OP_DCBST"
-  attribute \enum_value_0011010 "OP_DCBT"
-  attribute \enum_value_0011011 "OP_DCBTST"
-  attribute \enum_value_0011100 "OP_DCBZ"
-  attribute \enum_value_0011101 "OP_DIV"
-  attribute \enum_value_0011110 "OP_DIVE"
-  attribute \enum_value_0011111 "OP_EXTS"
-  attribute \enum_value_0100000 "OP_EXTSWSLI"
-  attribute \enum_value_0100001 "OP_ICBI"
-  attribute \enum_value_0100010 "OP_ICBT"
-  attribute \enum_value_0100011 "OP_ISEL"
-  attribute \enum_value_0100100 "OP_ISYNC"
-  attribute \enum_value_0100101 "OP_LOAD"
-  attribute \enum_value_0100110 "OP_STORE"
-  attribute \enum_value_0100111 "OP_MADDHD"
-  attribute \enum_value_0101000 "OP_MADDHDU"
-  attribute \enum_value_0101001 "OP_MADDLD"
-  attribute \enum_value_0101010 "OP_MCRF"
-  attribute \enum_value_0101011 "OP_MCRXR"
-  attribute \enum_value_0101100 "OP_MCRXRX"
-  attribute \enum_value_0101101 "OP_MFCR"
-  attribute \enum_value_0101110 "OP_MFSPR"
-  attribute \enum_value_0101111 "OP_MOD"
-  attribute \enum_value_0110000 "OP_MTCRF"
-  attribute \enum_value_0110001 "OP_MTSPR"
-  attribute \enum_value_0110010 "OP_MUL_L64"
-  attribute \enum_value_0110011 "OP_MUL_H64"
-  attribute \enum_value_0110100 "OP_MUL_H32"
-  attribute \enum_value_0110101 "OP_OR"
-  attribute \enum_value_0110110 "OP_POPCNT"
-  attribute \enum_value_0110111 "OP_PRTY"
-  attribute \enum_value_0111000 "OP_RLC"
-  attribute \enum_value_0111001 "OP_RLCL"
-  attribute \enum_value_0111010 "OP_RLCR"
-  attribute \enum_value_0111011 "OP_SETB"
-  attribute \enum_value_0111100 "OP_SHL"
-  attribute \enum_value_0111101 "OP_SHR"
-  attribute \enum_value_0111110 "OP_SYNC"
-  attribute \enum_value_0111111 "OP_TRAP"
-  attribute \enum_value_1000011 "OP_XOR"
-  attribute \enum_value_1000100 "OP_SIM_CONFIG"
-  attribute \enum_value_1000101 "OP_CROP"
-  attribute \enum_value_1000110 "OP_RFID"
-  attribute \enum_value_1000111 "OP_MFMSR"
-  attribute \enum_value_1001000 "OP_MTMSRD"
-  attribute \enum_value_1001001 "OP_SC"
-  attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 7 input 78 \oper_i_alu_spr0__insn_type
-  attribute \enum_base_type "Function"
-  attribute \enum_value_00000000000 "NONE"
-  attribute \enum_value_00000000010 "ALU"
-  attribute \enum_value_00000000100 "LDST"
-  attribute \enum_value_00000001000 "SHIFT_ROT"
-  attribute \enum_value_00000010000 "LOGICAL"
-  attribute \enum_value_00000100000 "BRANCH"
-  attribute \enum_value_00001000000 "CR"
-  attribute \enum_value_00010000000 "TRAP"
-  attribute \enum_value_00100000000 "MUL"
-  attribute \enum_value_01000000000 "DIV"
-  attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 11 input 79 \oper_i_alu_spr0__fn_unit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 32 input 80 \oper_i_alu_spr0__insn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 81 \oper_i_alu_spr0__is_32bit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
-  wire width 1 input 82 \cu_issue_i$13
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:106"
-  wire width 1 output 83 \cu_busy_o$14
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
-  wire width 6 input 84 \cu_rdmaskn_i$15
-  attribute \enum_base_type "MicrOp"
-  attribute \enum_value_0000000 "OP_ILLEGAL"
-  attribute \enum_value_0000001 "OP_NOP"
-  attribute \enum_value_0000010 "OP_ADD"
-  attribute \enum_value_0000011 "OP_ADDPCIS"
-  attribute \enum_value_0000100 "OP_AND"
-  attribute \enum_value_0000101 "OP_ATTN"
-  attribute \enum_value_0000110 "OP_B"
-  attribute \enum_value_0000111 "OP_BC"
-  attribute \enum_value_0001000 "OP_BCREG"
-  attribute \enum_value_0001001 "OP_BPERM"
-  attribute \enum_value_0001010 "OP_CMP"
-  attribute \enum_value_0001011 "OP_CMPB"
-  attribute \enum_value_0001100 "OP_CMPEQB"
-  attribute \enum_value_0001101 "OP_CMPRB"
-  attribute \enum_value_0001110 "OP_CNTZ"
-  attribute \enum_value_0001111 "OP_CRAND"
-  attribute \enum_value_0010000 "OP_CRANDC"
-  attribute \enum_value_0010001 "OP_CREQV"
-  attribute \enum_value_0010010 "OP_CRNAND"
-  attribute \enum_value_0010011 "OP_CRNOR"
-  attribute \enum_value_0010100 "OP_CROR"
-  attribute \enum_value_0010101 "OP_CRORC"
-  attribute \enum_value_0010110 "OP_CRXOR"
-  attribute \enum_value_0010111 "OP_DARN"
-  attribute \enum_value_0011000 "OP_DCBF"
-  attribute \enum_value_0011001 "OP_DCBST"
-  attribute \enum_value_0011010 "OP_DCBT"
-  attribute \enum_value_0011011 "OP_DCBTST"
-  attribute \enum_value_0011100 "OP_DCBZ"
-  attribute \enum_value_0011101 "OP_DIV"
-  attribute \enum_value_0011110 "OP_DIVE"
-  attribute \enum_value_0011111 "OP_EXTS"
-  attribute \enum_value_0100000 "OP_EXTSWSLI"
-  attribute \enum_value_0100001 "OP_ICBI"
-  attribute \enum_value_0100010 "OP_ICBT"
-  attribute \enum_value_0100011 "OP_ISEL"
-  attribute \enum_value_0100100 "OP_ISYNC"
-  attribute \enum_value_0100101 "OP_LOAD"
-  attribute \enum_value_0100110 "OP_STORE"
-  attribute \enum_value_0100111 "OP_MADDHD"
-  attribute \enum_value_0101000 "OP_MADDHDU"
-  attribute \enum_value_0101001 "OP_MADDLD"
-  attribute \enum_value_0101010 "OP_MCRF"
-  attribute \enum_value_0101011 "OP_MCRXR"
-  attribute \enum_value_0101100 "OP_MCRXRX"
-  attribute \enum_value_0101101 "OP_MFCR"
-  attribute \enum_value_0101110 "OP_MFSPR"
-  attribute \enum_value_0101111 "OP_MOD"
-  attribute \enum_value_0110000 "OP_MTCRF"
-  attribute \enum_value_0110001 "OP_MTSPR"
-  attribute \enum_value_0110010 "OP_MUL_L64"
-  attribute \enum_value_0110011 "OP_MUL_H64"
-  attribute \enum_value_0110100 "OP_MUL_H32"
-  attribute \enum_value_0110101 "OP_OR"
-  attribute \enum_value_0110110 "OP_POPCNT"
-  attribute \enum_value_0110111 "OP_PRTY"
-  attribute \enum_value_0111000 "OP_RLC"
-  attribute \enum_value_0111001 "OP_RLCL"
-  attribute \enum_value_0111010 "OP_RLCR"
-  attribute \enum_value_0111011 "OP_SETB"
-  attribute \enum_value_0111100 "OP_SHL"
-  attribute \enum_value_0111101 "OP_SHR"
-  attribute \enum_value_0111110 "OP_SYNC"
-  attribute \enum_value_0111111 "OP_TRAP"
-  attribute \enum_value_1000011 "OP_XOR"
-  attribute \enum_value_1000100 "OP_SIM_CONFIG"
-  attribute \enum_value_1000101 "OP_CROP"
-  attribute \enum_value_1000110 "OP_RFID"
-  attribute \enum_value_1000111 "OP_MFMSR"
-  attribute \enum_value_1001000 "OP_MTMSRD"
-  attribute \enum_value_1001001 "OP_SC"
-  attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 7 input 85 \oper_i_alu_mul0__insn_type
-  attribute \enum_base_type "Function"
-  attribute \enum_value_00000000000 "NONE"
-  attribute \enum_value_00000000010 "ALU"
-  attribute \enum_value_00000000100 "LDST"
-  attribute \enum_value_00000001000 "SHIFT_ROT"
-  attribute \enum_value_00000010000 "LOGICAL"
-  attribute \enum_value_00000100000 "BRANCH"
-  attribute \enum_value_00001000000 "CR"
-  attribute \enum_value_00010000000 "TRAP"
-  attribute \enum_value_00100000000 "MUL"
-  attribute \enum_value_01000000000 "DIV"
-  attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 11 input 86 \oper_i_alu_mul0__fn_unit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 64 input 87 \oper_i_alu_mul0__imm_data__imm
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 88 \oper_i_alu_mul0__imm_data__imm_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 89 \oper_i_alu_mul0__rc__rc
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 90 \oper_i_alu_mul0__rc__rc_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 91 \oper_i_alu_mul0__oe__oe
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 92 \oper_i_alu_mul0__oe__oe_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 93 \oper_i_alu_mul0__invert_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 94 \oper_i_alu_mul0__zero_a
+  wire width 2 output 31 \sr_op__input_carry$10
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 95 \oper_i_alu_mul0__invert_out
+  wire width 1 output 32 \sr_op__output_carry$11
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 96 \oper_i_alu_mul0__write_cr0
+  wire width 1 output 33 \sr_op__input_cr$12
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 97 \oper_i_alu_mul0__is_32bit
+  wire width 1 output 34 \sr_op__output_cr$13
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 98 \oper_i_alu_mul0__is_signed
+  wire width 1 output 35 \sr_op__is_32bit$14
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 32 input 99 \oper_i_alu_mul0__insn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
-  wire width 1 input 100 \cu_issue_i$16
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:106"
-  wire width 1 output 101 \cu_busy_o$17
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
-  wire width 3 input 102 \cu_rdmaskn_i$18
-  attribute \enum_base_type "MicrOp"
-  attribute \enum_value_0000000 "OP_ILLEGAL"
-  attribute \enum_value_0000001 "OP_NOP"
-  attribute \enum_value_0000010 "OP_ADD"
-  attribute \enum_value_0000011 "OP_ADDPCIS"
-  attribute \enum_value_0000100 "OP_AND"
-  attribute \enum_value_0000101 "OP_ATTN"
-  attribute \enum_value_0000110 "OP_B"
-  attribute \enum_value_0000111 "OP_BC"
-  attribute \enum_value_0001000 "OP_BCREG"
-  attribute \enum_value_0001001 "OP_BPERM"
-  attribute \enum_value_0001010 "OP_CMP"
-  attribute \enum_value_0001011 "OP_CMPB"
-  attribute \enum_value_0001100 "OP_CMPEQB"
-  attribute \enum_value_0001101 "OP_CMPRB"
-  attribute \enum_value_0001110 "OP_CNTZ"
-  attribute \enum_value_0001111 "OP_CRAND"
-  attribute \enum_value_0010000 "OP_CRANDC"
-  attribute \enum_value_0010001 "OP_CREQV"
-  attribute \enum_value_0010010 "OP_CRNAND"
-  attribute \enum_value_0010011 "OP_CRNOR"
-  attribute \enum_value_0010100 "OP_CROR"
-  attribute \enum_value_0010101 "OP_CRORC"
-  attribute \enum_value_0010110 "OP_CRXOR"
-  attribute \enum_value_0010111 "OP_DARN"
-  attribute \enum_value_0011000 "OP_DCBF"
-  attribute \enum_value_0011001 "OP_DCBST"
-  attribute \enum_value_0011010 "OP_DCBT"
-  attribute \enum_value_0011011 "OP_DCBTST"
-  attribute \enum_value_0011100 "OP_DCBZ"
-  attribute \enum_value_0011101 "OP_DIV"
-  attribute \enum_value_0011110 "OP_DIVE"
-  attribute \enum_value_0011111 "OP_EXTS"
-  attribute \enum_value_0100000 "OP_EXTSWSLI"
-  attribute \enum_value_0100001 "OP_ICBI"
-  attribute \enum_value_0100010 "OP_ICBT"
-  attribute \enum_value_0100011 "OP_ISEL"
-  attribute \enum_value_0100100 "OP_ISYNC"
-  attribute \enum_value_0100101 "OP_LOAD"
-  attribute \enum_value_0100110 "OP_STORE"
-  attribute \enum_value_0100111 "OP_MADDHD"
-  attribute \enum_value_0101000 "OP_MADDHDU"
-  attribute \enum_value_0101001 "OP_MADDLD"
-  attribute \enum_value_0101010 "OP_MCRF"
-  attribute \enum_value_0101011 "OP_MCRXR"
-  attribute \enum_value_0101100 "OP_MCRXRX"
-  attribute \enum_value_0101101 "OP_MFCR"
-  attribute \enum_value_0101110 "OP_MFSPR"
-  attribute \enum_value_0101111 "OP_MOD"
-  attribute \enum_value_0110000 "OP_MTCRF"
-  attribute \enum_value_0110001 "OP_MTSPR"
-  attribute \enum_value_0110010 "OP_MUL_L64"
-  attribute \enum_value_0110011 "OP_MUL_H64"
-  attribute \enum_value_0110100 "OP_MUL_H32"
-  attribute \enum_value_0110101 "OP_OR"
-  attribute \enum_value_0110110 "OP_POPCNT"
-  attribute \enum_value_0110111 "OP_PRTY"
-  attribute \enum_value_0111000 "OP_RLC"
-  attribute \enum_value_0111001 "OP_RLCL"
-  attribute \enum_value_0111010 "OP_RLCR"
-  attribute \enum_value_0111011 "OP_SETB"
-  attribute \enum_value_0111100 "OP_SHL"
-  attribute \enum_value_0111101 "OP_SHR"
-  attribute \enum_value_0111110 "OP_SYNC"
-  attribute \enum_value_0111111 "OP_TRAP"
-  attribute \enum_value_1000011 "OP_XOR"
-  attribute \enum_value_1000100 "OP_SIM_CONFIG"
-  attribute \enum_value_1000101 "OP_CROP"
-  attribute \enum_value_1000110 "OP_RFID"
-  attribute \enum_value_1000111 "OP_MFMSR"
-  attribute \enum_value_1001000 "OP_MTMSRD"
-  attribute \enum_value_1001001 "OP_SC"
-  attribute \enum_value_1001010 "OP_MTMSR"
+  wire width 1 output 36 \sr_op__is_signed$15
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 7 input 103 \oper_i_alu_shift_rot0__insn_type
-  attribute \enum_base_type "Function"
-  attribute \enum_value_00000000000 "NONE"
-  attribute \enum_value_00000000010 "ALU"
-  attribute \enum_value_00000000100 "LDST"
-  attribute \enum_value_00000001000 "SHIFT_ROT"
-  attribute \enum_value_00000010000 "LOGICAL"
-  attribute \enum_value_00000100000 "BRANCH"
-  attribute \enum_value_00001000000 "CR"
-  attribute \enum_value_00010000000 "TRAP"
-  attribute \enum_value_00100000000 "MUL"
-  attribute \enum_value_01000000000 "DIV"
-  attribute \enum_value_10000000000 "SPR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 11 input 104 \oper_i_alu_shift_rot0__fn_unit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 64 input 105 \oper_i_alu_shift_rot0__imm_data__imm
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 106 \oper_i_alu_shift_rot0__imm_data__imm_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 107 \oper_i_alu_shift_rot0__rc__rc
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 108 \oper_i_alu_shift_rot0__rc__rc_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 109 \oper_i_alu_shift_rot0__oe__oe
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 110 \oper_i_alu_shift_rot0__oe__oe_ok
-  attribute \enum_base_type "CryIn"
-  attribute \enum_value_00 "ZERO"
-  attribute \enum_value_01 "ONE"
-  attribute \enum_value_10 "CA"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 2 input 112 \oper_i_alu_shift_rot0__input_carry
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 113 \oper_i_alu_shift_rot0__output_carry
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 114 \oper_i_alu_shift_rot0__input_cr
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 115 \oper_i_alu_shift_rot0__output_cr
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 116 \oper_i_alu_shift_rot0__is_32bit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 117 \oper_i_alu_shift_rot0__is_signed
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 32 input 118 \oper_i_alu_shift_rot0__insn
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
-  wire width 1 input 119 \cu_issue_i$19
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:106"
-  wire width 1 output 120 \cu_busy_o$20
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
-  wire width 4 input 121 \cu_rdmaskn_i$21
-  attribute \enum_base_type "MicrOp"
-  attribute \enum_value_0000000 "OP_ILLEGAL"
-  attribute \enum_value_0000001 "OP_NOP"
-  attribute \enum_value_0000010 "OP_ADD"
-  attribute \enum_value_0000011 "OP_ADDPCIS"
-  attribute \enum_value_0000100 "OP_AND"
-  attribute \enum_value_0000101 "OP_ATTN"
-  attribute \enum_value_0000110 "OP_B"
-  attribute \enum_value_0000111 "OP_BC"
-  attribute \enum_value_0001000 "OP_BCREG"
-  attribute \enum_value_0001001 "OP_BPERM"
-  attribute \enum_value_0001010 "OP_CMP"
-  attribute \enum_value_0001011 "OP_CMPB"
-  attribute \enum_value_0001100 "OP_CMPEQB"
-  attribute \enum_value_0001101 "OP_CMPRB"
-  attribute \enum_value_0001110 "OP_CNTZ"
-  attribute \enum_value_0001111 "OP_CRAND"
-  attribute \enum_value_0010000 "OP_CRANDC"
-  attribute \enum_value_0010001 "OP_CREQV"
-  attribute \enum_value_0010010 "OP_CRNAND"
-  attribute \enum_value_0010011 "OP_CRNOR"
-  attribute \enum_value_0010100 "OP_CROR"
-  attribute \enum_value_0010101 "OP_CRORC"
-  attribute \enum_value_0010110 "OP_CRXOR"
-  attribute \enum_value_0010111 "OP_DARN"
-  attribute \enum_value_0011000 "OP_DCBF"
-  attribute \enum_value_0011001 "OP_DCBST"
-  attribute \enum_value_0011010 "OP_DCBT"
-  attribute \enum_value_0011011 "OP_DCBTST"
-  attribute \enum_value_0011100 "OP_DCBZ"
-  attribute \enum_value_0011101 "OP_DIV"
-  attribute \enum_value_0011110 "OP_DIVE"
-  attribute \enum_value_0011111 "OP_EXTS"
-  attribute \enum_value_0100000 "OP_EXTSWSLI"
-  attribute \enum_value_0100001 "OP_ICBI"
-  attribute \enum_value_0100010 "OP_ICBT"
-  attribute \enum_value_0100011 "OP_ISEL"
-  attribute \enum_value_0100100 "OP_ISYNC"
-  attribute \enum_value_0100101 "OP_LOAD"
-  attribute \enum_value_0100110 "OP_STORE"
-  attribute \enum_value_0100111 "OP_MADDHD"
-  attribute \enum_value_0101000 "OP_MADDHDU"
-  attribute \enum_value_0101001 "OP_MADDLD"
-  attribute \enum_value_0101010 "OP_MCRF"
-  attribute \enum_value_0101011 "OP_MCRXR"
-  attribute \enum_value_0101100 "OP_MCRXRX"
-  attribute \enum_value_0101101 "OP_MFCR"
-  attribute \enum_value_0101110 "OP_MFSPR"
-  attribute \enum_value_0101111 "OP_MOD"
-  attribute \enum_value_0110000 "OP_MTCRF"
-  attribute \enum_value_0110001 "OP_MTSPR"
-  attribute \enum_value_0110010 "OP_MUL_L64"
-  attribute \enum_value_0110011 "OP_MUL_H64"
-  attribute \enum_value_0110100 "OP_MUL_H32"
-  attribute \enum_value_0110101 "OP_OR"
-  attribute \enum_value_0110110 "OP_POPCNT"
-  attribute \enum_value_0110111 "OP_PRTY"
-  attribute \enum_value_0111000 "OP_RLC"
-  attribute \enum_value_0111001 "OP_RLCL"
-  attribute \enum_value_0111010 "OP_RLCR"
-  attribute \enum_value_0111011 "OP_SETB"
-  attribute \enum_value_0111100 "OP_SHL"
-  attribute \enum_value_0111101 "OP_SHR"
-  attribute \enum_value_0111110 "OP_SYNC"
-  attribute \enum_value_0111111 "OP_TRAP"
-  attribute \enum_value_1000011 "OP_XOR"
-  attribute \enum_value_1000100 "OP_SIM_CONFIG"
-  attribute \enum_value_1000101 "OP_CROP"
-  attribute \enum_value_1000110 "OP_RFID"
-  attribute \enum_value_1000111 "OP_MFMSR"
-  attribute \enum_value_1001000 "OP_MTMSRD"
-  attribute \enum_value_1001001 "OP_SC"
-  attribute \enum_value_1001010 "OP_MTMSR"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 7 input 122 \oper_i_ldst_ldst0__insn_type
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 64 input 123 \oper_i_ldst_ldst0__imm_data__imm
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 124 \oper_i_ldst_ldst0__imm_data__imm_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 125 \oper_i_ldst_ldst0__zero_a
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 126 \oper_i_ldst_ldst0__rc__rc
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 127 \oper_i_ldst_ldst0__rc__rc_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 128 \oper_i_ldst_ldst0__oe__oe
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 129 \oper_i_ldst_ldst0__oe__oe_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 130 \oper_i_ldst_ldst0__is_32bit
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 131 \oper_i_ldst_ldst0__is_signed
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 4 input 132 \oper_i_ldst_ldst0__data_len
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 133 \oper_i_ldst_ldst0__byte_reverse
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 input 134 \oper_i_ldst_ldst0__sign_extend
-  attribute \enum_base_type "LDSTMode"
-  attribute \enum_value_00 "NONE"
-  attribute \enum_value_01 "update"
-  attribute \enum_value_10 "cix"
-  attribute \enum_value_11 "cx"
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 2 input 135 \oper_i_ldst_ldst0__ldst_mode
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
-  wire width 1 input 136 \cu_issue_i$22
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:106"
-  wire width 1 output 137 \cu_busy_o$23
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
-  wire width 3 input 138 \cu_rdmaskn_i$24
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 4 output 139 \cu_rd__rel_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 4 input 140 \cu_rd__go_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
-  wire width 64 input 141 \src1_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 6 output 142 \cu_rd__rel_o$25
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 6 input 143 \cu_rd__go_i$26
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
-  wire width 64 input 144 \src1_i$27
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 4 output 145 \cu_rd__rel_o$28
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 4 input 146 \cu_rd__go_i$29
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
-  wire width 64 input 147 \src1_i$30
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 2 output 148 \cu_rd__rel_o$31
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 2 input 149 \cu_rd__go_i$32
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
-  wire width 64 input 150 \src1_i$33
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 6 output 151 \cu_rd__rel_o$34
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 6 input 152 \cu_rd__go_i$35
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
-  wire width 64 input 153 \src1_i$36
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 3 output 154 \cu_rd__rel_o$37
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 3 input 155 \cu_rd__go_i$38
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
-  wire width 64 input 156 \src1_i$39
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 4 output 157 \cu_rd__rel_o$40
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 4 input 158 \cu_rd__go_i$41
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
-  wire width 64 input 159 \src1_i$42
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 3 output 160 \cu_rd__rel_o$43
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 3 input 161 \cu_rd__go_i$44
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
-  wire width 64 input 162 \src1_i$45
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
-  wire width 64 input 163 \src2_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
-  wire width 64 input 164 \src2_i$46
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
-  wire width 64 input 165 \src2_i$47
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
-  wire width 64 input 166 \src2_i$48
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
-  wire width 64 input 167 \src2_i$49
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
-  wire width 64 input 168 \src2_i$50
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
-  wire width 64 input 169 \src2_i$51
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
-  wire width 64 input 170 \src3_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
-  wire width 64 input 171 \src3_i$52
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
-  wire width 1 input 172 \src3_i$53
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
-  wire width 1 input 173 \src4_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
-  wire width 1 input 174 \src3_i$54
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
-  wire width 2 input 175 \src4_i$55
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
-  wire width 2 input 176 \src6_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
-  wire width 2 input 177 \src4_i$56
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
-  wire width 2 input 178 \src5_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
-  wire width 32 input 179 \src3_i$57
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
-  wire width 4 input 180 \src4_i$58
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 3 output 181 \cu_rd__rel_o$59
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 3 input 182 \cu_rd__go_i$60
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
-  wire width 4 input 183 \src3_i$61
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
-  wire width 4 input 184 \src5_i$62
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
-  wire width 4 input 185 \src6_i$63
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
-  wire width 64 input 186 \src1_i$64
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
-  wire width 64 input 187 \src3_i$65
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
-  wire width 64 input 188 \src3_i$66
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
-  wire width 64 input 189 \src2_i$67
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
-  wire width 64 input 190 \src4_i$68
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
-  wire width 64 input 191 \src2_i$69
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 192 \o_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 5 output 193 \cu_wr__rel_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 5 input 194 \cu_wr__go_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 195 \o_ok$70
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 3 output 196 \cu_wr__rel_o$71
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 3 input 197 \cu_wr__go_i$72
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 198 \o_ok$73
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 5 output 199 \cu_wr__rel_o$74
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 5 input 200 \cu_wr__go_i$75
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 201 \o_ok$76
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 3 output 202 \cu_wr__rel_o$77
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 3 input 203 \cu_wr__go_i$78
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 204 \o_ok$79
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 6 output 205 \cu_wr__rel_o$80
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 6 input 206 \cu_wr__go_i$81
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 207 \o_ok$82
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 4 output 208 \cu_wr__rel_o$83
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 4 input 209 \cu_wr__go_i$84
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 210 \o_ok$85
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 3 output 211 \cu_wr__rel_o$86
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 3 input 212 \cu_wr__go_i$87
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 2 output 213 \cu_wr__rel_o$88
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 2 input 214 \cu_wr__go_i$89
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
-  wire width 64 output 215 \dest1_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
-  wire width 64 output 216 \dest1_o$90
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
-  wire width 64 output 217 \dest1_o$91
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
-  wire width 64 output 218 \dest1_o$92
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
-  wire width 64 output 219 \dest1_o$93
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
-  wire width 64 output 220 \dest1_o$94
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
-  wire width 64 output 221 \dest1_o$95
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 64 output 222 \o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 64 output 223 \ea
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 224 \full_cr_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
-  wire width 32 output 225 \dest2_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 226 \cr_a_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 227 \cr_a_ok$96
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 228 \cr_a_ok$97
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 229 \cr_a_ok$98
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 230 \cr_a_ok$99
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
-  wire width 4 output 231 \dest2_o$100
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
-  wire width 4 output 232 \dest3_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
-  wire width 4 output 233 \dest2_o$101
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
-  wire width 4 output 234 \dest2_o$102
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
-  wire width 4 output 235 \dest2_o$103
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 236 \xer_ca_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 237 \xer_ca_ok$104
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 238 \xer_ca_ok$105
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 239 \xer_ca_ok$106
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
-  wire width 2 output 240 \dest3_o$107
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
-  wire width 2 output 241 \dest3_o$108
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
-  wire width 2 output 242 \dest6_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
-  wire width 2 output 243 \dest3_o$109
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 244 \xer_ov_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 245 \xer_ov_ok$110
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 246 \xer_ov_ok$111
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
-  wire width 2 output 247 \dest4_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
-  wire width 2 output 248 \dest5_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
-  wire width 2 output 249 \dest3_o$112
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 250 \xer_so_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 251 \xer_so_ok$113
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 252 \xer_so_ok$114
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
-  wire width 1 output 253 \dest5_o$115
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
-  wire width 1 output 254 \dest4_o$116
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
-  wire width 1 output 255 \dest4_o$117
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 256 \fast1_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 3 output 257 \cu_wr__rel_o$118
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 3 input 258 \cu_wr__go_i$119
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 259 \fast1_ok$120
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 260 \fast1_ok$121
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
-  wire width 64 output 261 \dest1_o$122
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
-  wire width 64 output 262 \dest2_o$123
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
-  wire width 64 output 263 \dest3_o$124
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 264 \fast2_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 265 \fast2_ok$125
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
-  wire width 64 output 266 \dest2_o$126
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
-  wire width 64 output 267 \dest3_o$127
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 268 \nia_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 269 \nia_ok$128
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
-  wire width 64 output 270 \dest3_o$129
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
-  wire width 64 output 271 \dest4_o$130
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 272 \msr_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
-  wire width 64 output 273 \dest5_o$131
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 274 \spr1_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
-  wire width 64 output 275 \dest2_o$132
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:95"
-  wire width 1 output 276 \ldst_port0_is_ld_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:96"
-  wire width 1 output 277 \ldst_port0_is_st_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99"
-  wire width 4 output 278 \ldst_port0_data_len
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 96 output 279 \ldst_port0_addr_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 280 \ldst_port0_addr_i_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:107"
-  wire width 1 input 281 \ldst_port0_addr_exc_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:106"
-  wire width 1 input 282 \ldst_port0_addr_ok_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 64 input 283 \ldst_port0_ld_data_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 input 284 \ldst_port0_ld_data_o_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 64 output 285 \ldst_port0_st_data_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 286 \ldst_port0_st_data_i_ok
-  cell \alu0 \alu0
-    connect \rst \rst
-    connect \clk \clk
-    connect \oper_i_alu_alu0__insn_type \oper_i_alu_alu0__insn_type
-    connect \oper_i_alu_alu0__fn_unit \oper_i_alu_alu0__fn_unit
-    connect \oper_i_alu_alu0__imm_data__imm \oper_i_alu_alu0__imm_data__imm
-    connect \oper_i_alu_alu0__imm_data__imm_ok \oper_i_alu_alu0__imm_data__imm_ok
-    connect \oper_i_alu_alu0__rc__rc \oper_i_alu_alu0__rc__rc
-    connect \oper_i_alu_alu0__rc__rc_ok \oper_i_alu_alu0__rc__rc_ok
-    connect \oper_i_alu_alu0__oe__oe \oper_i_alu_alu0__oe__oe
-    connect \oper_i_alu_alu0__oe__oe_ok \oper_i_alu_alu0__oe__oe_ok
-    connect \oper_i_alu_alu0__invert_a \oper_i_alu_alu0__invert_a
-    connect \oper_i_alu_alu0__zero_a \oper_i_alu_alu0__zero_a
-    connect \oper_i_alu_alu0__invert_out \oper_i_alu_alu0__invert_out
-    connect \oper_i_alu_alu0__write_cr0 \oper_i_alu_alu0__write_cr0
-    connect \oper_i_alu_alu0__input_carry \oper_i_alu_alu0__input_carry
-    connect \oper_i_alu_alu0__output_carry \oper_i_alu_alu0__output_carry
-    connect \oper_i_alu_alu0__is_32bit \oper_i_alu_alu0__is_32bit
-    connect \oper_i_alu_alu0__is_signed \oper_i_alu_alu0__is_signed
-    connect \oper_i_alu_alu0__data_len \oper_i_alu_alu0__data_len
-    connect \oper_i_alu_alu0__insn \oper_i_alu_alu0__insn
-    connect \cu_issue_i \cu_issue_i
-    connect \cu_busy_o \cu_busy_o
-    connect \cu_rdmaskn_i \cu_rdmaskn_i
-    connect \cu_rd__rel_o \cu_rd__rel_o
-    connect \cu_rd__go_i \cu_rd__go_i
-    connect \src1_i \src1_i
-    connect \src2_i \src2_i
-    connect \src3_i \src3_i$53
-    connect \src4_i \src4_i$55
-    connect \o_ok \o_ok
-    connect \cu_wr__rel_o \cu_wr__rel_o
-    connect \cu_wr__go_i \cu_wr__go_i
-    connect \dest1_o \dest1_o
-    connect \cr_a_ok \cr_a_ok
-    connect \dest2_o \dest2_o$100
-    connect \xer_ca_ok \xer_ca_ok
-    connect \dest3_o \dest3_o$107
-    connect \xer_ov_ok \xer_ov_ok
-    connect \dest4_o \dest4_o
-    connect \xer_so_ok \xer_so_ok
-    connect \dest5_o \dest5_o$115
+  wire width 32 output 37 \sr_op__insn$16
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
+  wire width 64 output 38 \ra$17
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
+  wire width 64 output 39 \rb$18
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
+  wire width 64 output 40 \rc$19
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
+  wire width 2 output 41 \xer_ca$20
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20"
+  wire width 64 \a
+  process $group_0
+    assign \a 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \a \ra
+    sync init
   end
-  cell \cr0 \cr0
-    connect \rst \rst
-    connect \clk \clk
-    connect \oper_i_alu_cr0__insn_type \oper_i_alu_cr0__insn_type
-    connect \oper_i_alu_cr0__fn_unit \oper_i_alu_cr0__fn_unit
-    connect \oper_i_alu_cr0__insn \oper_i_alu_cr0__insn
-    connect \oper_i_alu_cr0__read_cr_whole \oper_i_alu_cr0__read_cr_whole
-    connect \oper_i_alu_cr0__write_cr_whole \oper_i_alu_cr0__write_cr_whole
-    connect \cu_issue_i \cu_issue_i$1
-    connect \cu_busy_o \cu_busy_o$2
-    connect \cu_rdmaskn_i \cu_rdmaskn_i$3
-    connect \cu_rd__rel_o \cu_rd__rel_o$25
-    connect \cu_rd__go_i \cu_rd__go_i$26
-    connect \src1_i \src1_i$27
-    connect \src2_i \src2_i$46
-    connect \src3_i \src3_i$57
-    connect \src4_i \src4_i$58
-    connect \src5_i \src5_i$62
-    connect \src6_i \src6_i$63
-    connect \o_ok \o_ok$70
-    connect \cu_wr__rel_o \cu_wr__rel_o$71
-    connect \cu_wr__go_i \cu_wr__go_i$72
-    connect \dest1_o \dest1_o$90
-    connect \full_cr_ok \full_cr_ok
-    connect \dest2_o \dest2_o
-    connect \cr_a_ok \cr_a_ok$96
-    connect \dest3_o \dest3_o
+  process $group_1
+    assign \ra$17 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \ra$17 \a
+    sync init
   end
-  cell \branch0 \branch0
-    connect \rst \rst
-    connect \clk \clk
-    connect \oper_i_alu_branch0__cia \oper_i_alu_branch0__cia
-    connect \oper_i_alu_branch0__insn_type \oper_i_alu_branch0__insn_type
-    connect \oper_i_alu_branch0__fn_unit \oper_i_alu_branch0__fn_unit
-    connect \oper_i_alu_branch0__insn \oper_i_alu_branch0__insn
-    connect \oper_i_alu_branch0__imm_data__imm \oper_i_alu_branch0__imm_data__imm
-    connect \oper_i_alu_branch0__imm_data__imm_ok \oper_i_alu_branch0__imm_data__imm_ok
-    connect \oper_i_alu_branch0__lk \oper_i_alu_branch0__lk
-    connect \oper_i_alu_branch0__is_32bit \oper_i_alu_branch0__is_32bit
-    connect \cu_issue_i \cu_issue_i$4
-    connect \cu_busy_o \cu_busy_o$5
-    connect \cu_rdmaskn_i \cu_rdmaskn_i$6
-    connect \cu_rd__rel_o \cu_rd__rel_o$59
-    connect \cu_rd__go_i \cu_rd__go_i$60
-    connect \src3_i \src3_i$61
-    connect \src1_i \src1_i$64
-    connect \src2_i \src2_i$67
-    connect \fast1_ok \fast1_ok
-    connect \cu_wr__rel_o \cu_wr__rel_o$118
-    connect \cu_wr__go_i \cu_wr__go_i$119
-    connect \dest1_o \dest1_o$122
-    connect \fast2_ok \fast2_ok
-    connect \dest2_o \dest2_o$126
-    connect \nia_ok \nia_ok
-    connect \dest3_o \dest3_o$129
+  process $group_2
+    assign \xer_ca$20 2'00
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:36"
+    switch \sr_op__input_carry
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:37"
+      attribute \nmigen.decoding "ZERO/0"
+      case 2'00
+        assign \xer_ca$20 2'00
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:39"
+      attribute \nmigen.decoding "ONE/1"
+      case 2'01
+        assign \xer_ca$20 2'11
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:41"
+      attribute \nmigen.decoding "CA/2"
+      case 2'10
+        assign \xer_ca$20 \xer_ca
+    end
+    sync init
   end
-  cell \trap0 \trap0
-    connect \rst \rst
-    connect \clk \clk
-    connect \oper_i_alu_trap0__insn_type \oper_i_alu_trap0__insn_type
-    connect \oper_i_alu_trap0__fn_unit \oper_i_alu_trap0__fn_unit
-    connect \oper_i_alu_trap0__insn \oper_i_alu_trap0__insn
-    connect \oper_i_alu_trap0__msr \oper_i_alu_trap0__msr
-    connect \oper_i_alu_trap0__cia \oper_i_alu_trap0__cia
-    connect \oper_i_alu_trap0__is_32bit \oper_i_alu_trap0__is_32bit
-    connect \oper_i_alu_trap0__traptype \oper_i_alu_trap0__traptype
-    connect \oper_i_alu_trap0__trapaddr \oper_i_alu_trap0__trapaddr
-    connect \cu_issue_i \cu_issue_i$7
-    connect \cu_busy_o \cu_busy_o$8
-    connect \cu_rdmaskn_i \cu_rdmaskn_i$9
-    connect \cu_rd__rel_o \cu_rd__rel_o$28
-    connect \cu_rd__go_i \cu_rd__go_i$29
-    connect \src1_i \src1_i$30
-    connect \src2_i \src2_i$47
-    connect \src3_i \src3_i$65
-    connect \src4_i \src4_i$68
-    connect \o_ok \o_ok$73
-    connect \cu_wr__rel_o \cu_wr__rel_o$74
-    connect \cu_wr__go_i \cu_wr__go_i$75
-    connect \dest1_o \dest1_o$91
-    connect \fast1_ok \fast1_ok$120
-    connect \dest2_o \dest2_o$123
-    connect \fast2_ok \fast2_ok$125
-    connect \dest3_o \dest3_o$127
-    connect \nia_ok \nia_ok$128
-    connect \dest4_o \dest4_o$130
-    connect \msr_ok \msr_ok
-    connect \dest5_o \dest5_o$131
+  process $group_3
+    assign \muxid$1 2'00
+    assign \muxid$1 \muxid
+    sync init
   end
-  cell \logical0 \logical0
-    connect \rst \rst
-    connect \clk \clk
-    connect \oper_i_alu_logical0__insn_type \oper_i_alu_logical0__insn_type
-    connect \oper_i_alu_logical0__fn_unit \oper_i_alu_logical0__fn_unit
-    connect \oper_i_alu_logical0__imm_data__imm \oper_i_alu_logical0__imm_data__imm
-    connect \oper_i_alu_logical0__imm_data__imm_ok \oper_i_alu_logical0__imm_data__imm_ok
-    connect \oper_i_alu_logical0__rc__rc \oper_i_alu_logical0__rc__rc
-    connect \oper_i_alu_logical0__rc__rc_ok \oper_i_alu_logical0__rc__rc_ok
-    connect \oper_i_alu_logical0__oe__oe \oper_i_alu_logical0__oe__oe
-    connect \oper_i_alu_logical0__oe__oe_ok \oper_i_alu_logical0__oe__oe_ok
-    connect \oper_i_alu_logical0__invert_a \oper_i_alu_logical0__invert_a
-    connect \oper_i_alu_logical0__zero_a \oper_i_alu_logical0__zero_a
-    connect \oper_i_alu_logical0__input_carry \oper_i_alu_logical0__input_carry
-    connect \oper_i_alu_logical0__invert_out \oper_i_alu_logical0__invert_out
-    connect \oper_i_alu_logical0__write_cr0 \oper_i_alu_logical0__write_cr0
-    connect \oper_i_alu_logical0__output_carry \oper_i_alu_logical0__output_carry
-    connect \oper_i_alu_logical0__is_32bit \oper_i_alu_logical0__is_32bit
-    connect \oper_i_alu_logical0__is_signed \oper_i_alu_logical0__is_signed
-    connect \oper_i_alu_logical0__data_len \oper_i_alu_logical0__data_len
-    connect \oper_i_alu_logical0__insn \oper_i_alu_logical0__insn
-    connect \cu_issue_i \cu_issue_i$10
-    connect \cu_busy_o \cu_busy_o$11
-    connect \cu_rdmaskn_i \cu_rdmaskn_i$12
-    connect \cu_rd__rel_o \cu_rd__rel_o$31
-    connect \cu_rd__go_i \cu_rd__go_i$32
-    connect \src1_i \src1_i$33
-    connect \src2_i \src2_i$48
-    connect \o_ok \o_ok$76
-    connect \cu_wr__rel_o \cu_wr__rel_o$77
-    connect \cu_wr__go_i \cu_wr__go_i$78
-    connect \dest1_o \dest1_o$92
-    connect \cr_a_ok \cr_a_ok$97
-    connect \dest2_o \dest2_o$101
-    connect \xer_ca_ok \xer_ca_ok$104
-    connect \dest3_o \dest3_o$108
+  process $group_4
+    assign \sr_op__insn_type$2 7'0000000
+    assign \sr_op__fn_unit$3 11'00000000000
+    assign \sr_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \sr_op__imm_data__imm_ok$5 1'0
+    assign \sr_op__rc__rc$6 1'0
+    assign \sr_op__rc__rc_ok$7 1'0
+    assign \sr_op__oe__oe$8 1'0
+    assign \sr_op__oe__oe_ok$9 1'0
+    assign { } 0'0
+    assign \sr_op__input_carry$10 2'00
+    assign \sr_op__output_carry$11 1'0
+    assign \sr_op__input_cr$12 1'0
+    assign \sr_op__output_cr$13 1'0
+    assign \sr_op__is_32bit$14 1'0
+    assign \sr_op__is_signed$15 1'0
+    assign \sr_op__insn$16 32'00000000000000000000000000000000
+    assign { \sr_op__insn$16 \sr_op__is_signed$15 \sr_op__is_32bit$14 \sr_op__output_cr$13 \sr_op__input_cr$12 \sr_op__output_carry$11 \sr_op__input_carry$10 { } { \sr_op__oe__oe_ok$9 \sr_op__oe__oe$8 } { \sr_op__rc__rc_ok$7 \sr_op__rc__rc$6 } { \sr_op__imm_data__imm_ok$5 \sr_op__imm_data__imm$4 } \sr_op__fn_unit$3 \sr_op__insn_type$2 } { \sr_op__insn \sr_op__is_signed \sr_op__is_32bit \sr_op__output_cr \sr_op__input_cr \sr_op__output_carry \sr_op__input_carry { } { \sr_op__oe__oe_ok \sr_op__oe__oe } { \sr_op__rc__rc_ok \sr_op__rc__rc } { \sr_op__imm_data__imm_ok \sr_op__imm_data__imm } \sr_op__fn_unit \sr_op__insn_type }
+    sync init
   end
-  cell \spr0 \spr0
-    connect \rst \rst
-    connect \clk \clk
-    connect \oper_i_alu_spr0__insn_type \oper_i_alu_spr0__insn_type
-    connect \oper_i_alu_spr0__fn_unit \oper_i_alu_spr0__fn_unit
-    connect \oper_i_alu_spr0__insn \oper_i_alu_spr0__insn
-    connect \oper_i_alu_spr0__is_32bit \oper_i_alu_spr0__is_32bit
-    connect \cu_issue_i \cu_issue_i$13
-    connect \cu_busy_o \cu_busy_o$14
-    connect \cu_rdmaskn_i \cu_rdmaskn_i$15
-    connect \cu_rd__rel_o \cu_rd__rel_o$34
-    connect \cu_rd__go_i \cu_rd__go_i$35
-    connect \src1_i \src1_i$36
-    connect \src4_i \src4_i
-    connect \src6_i \src6_i
-    connect \src5_i \src5_i
-    connect \src3_i \src3_i$66
-    connect \src2_i \src2_i$69
-    connect \o_ok \o_ok$79
-    connect \cu_wr__rel_o \cu_wr__rel_o$80
-    connect \cu_wr__go_i \cu_wr__go_i$81
-    connect \dest1_o \dest1_o$93
-    connect \xer_ca_ok \xer_ca_ok$105
-    connect \dest6_o \dest6_o
-    connect \xer_ov_ok \xer_ov_ok$110
-    connect \dest5_o \dest5_o
-    connect \xer_so_ok \xer_so_ok$113
-    connect \dest4_o \dest4_o$116
-    connect \fast1_ok \fast1_ok$121
-    connect \dest3_o \dest3_o$124
-    connect \spr1_ok \spr1_ok
-    connect \dest2_o \dest2_o$132
+  process $group_20
+    assign \rb$18 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \rb$18 \rb
+    sync init
   end
-  cell \mul0 \mul0
-    connect \rst \rst
-    connect \clk \clk
-    connect \oper_i_alu_mul0__insn_type \oper_i_alu_mul0__insn_type
-    connect \oper_i_alu_mul0__fn_unit \oper_i_alu_mul0__fn_unit
-    connect \oper_i_alu_mul0__imm_data__imm \oper_i_alu_mul0__imm_data__imm
-    connect \oper_i_alu_mul0__imm_data__imm_ok \oper_i_alu_mul0__imm_data__imm_ok
-    connect \oper_i_alu_mul0__rc__rc \oper_i_alu_mul0__rc__rc
-    connect \oper_i_alu_mul0__rc__rc_ok \oper_i_alu_mul0__rc__rc_ok
-    connect \oper_i_alu_mul0__oe__oe \oper_i_alu_mul0__oe__oe
-    connect \oper_i_alu_mul0__oe__oe_ok \oper_i_alu_mul0__oe__oe_ok
-    connect \oper_i_alu_mul0__invert_a \oper_i_alu_mul0__invert_a
-    connect \oper_i_alu_mul0__zero_a \oper_i_alu_mul0__zero_a
-    connect \oper_i_alu_mul0__invert_out \oper_i_alu_mul0__invert_out
-    connect \oper_i_alu_mul0__write_cr0 \oper_i_alu_mul0__write_cr0
-    connect \oper_i_alu_mul0__is_32bit \oper_i_alu_mul0__is_32bit
-    connect \oper_i_alu_mul0__is_signed \oper_i_alu_mul0__is_signed
-    connect \oper_i_alu_mul0__insn \oper_i_alu_mul0__insn
-    connect \cu_issue_i \cu_issue_i$16
-    connect \cu_busy_o \cu_busy_o$17
-    connect \cu_rdmaskn_i \cu_rdmaskn_i$18
-    connect \cu_rd__rel_o \cu_rd__rel_o$37
-    connect \cu_rd__go_i \cu_rd__go_i$38
-    connect \src1_i \src1_i$39
-    connect \src2_i \src2_i$49
-    connect \src3_i \src3_i$54
-    connect \o_ok \o_ok$82
-    connect \cu_wr__rel_o \cu_wr__rel_o$83
-    connect \cu_wr__go_i \cu_wr__go_i$84
-    connect \dest1_o \dest1_o$94
-    connect \cr_a_ok \cr_a_ok$98
-    connect \dest2_o \dest2_o$102
-    connect \xer_ov_ok \xer_ov_ok$111
-    connect \dest3_o \dest3_o$112
-    connect \xer_so_ok \xer_so_ok$114
-    connect \dest4_o \dest4_o$117
-  end
-  cell \shiftrot0 \shiftrot0
-    connect \rst \rst
-    connect \clk \clk
-    connect \oper_i_alu_shift_rot0__insn_type \oper_i_alu_shift_rot0__insn_type
-    connect \oper_i_alu_shift_rot0__fn_unit \oper_i_alu_shift_rot0__fn_unit
-    connect \oper_i_alu_shift_rot0__imm_data__imm \oper_i_alu_shift_rot0__imm_data__imm
-    connect \oper_i_alu_shift_rot0__imm_data__imm_ok \oper_i_alu_shift_rot0__imm_data__imm_ok
-    connect \oper_i_alu_shift_rot0__rc__rc \oper_i_alu_shift_rot0__rc__rc
-    connect \oper_i_alu_shift_rot0__rc__rc_ok \oper_i_alu_shift_rot0__rc__rc_ok
-    connect \oper_i_alu_shift_rot0__oe__oe \oper_i_alu_shift_rot0__oe__oe
-    connect \oper_i_alu_shift_rot0__oe__oe_ok \oper_i_alu_shift_rot0__oe__oe_ok
-    connect \oper_i_alu_shift_rot0__input_carry \oper_i_alu_shift_rot0__input_carry
-    connect \oper_i_alu_shift_rot0__output_carry \oper_i_alu_shift_rot0__output_carry
-    connect \oper_i_alu_shift_rot0__input_cr \oper_i_alu_shift_rot0__input_cr
-    connect \oper_i_alu_shift_rot0__output_cr \oper_i_alu_shift_rot0__output_cr
-    connect \oper_i_alu_shift_rot0__is_32bit \oper_i_alu_shift_rot0__is_32bit
-    connect \oper_i_alu_shift_rot0__is_signed \oper_i_alu_shift_rot0__is_signed
-    connect \oper_i_alu_shift_rot0__insn \oper_i_alu_shift_rot0__insn
-    connect \cu_issue_i \cu_issue_i$19
-    connect \cu_busy_o \cu_busy_o$20
-    connect \cu_rdmaskn_i \cu_rdmaskn_i$21
-    connect \cu_rd__rel_o \cu_rd__rel_o$40
-    connect \cu_rd__go_i \cu_rd__go_i$41
-    connect \src1_i \src1_i$42
-    connect \src2_i \src2_i$50
-    connect \src3_i \src3_i
-    connect \src4_i \src4_i$56
-    connect \o_ok \o_ok$85
-    connect \cu_wr__rel_o \cu_wr__rel_o$86
-    connect \cu_wr__go_i \cu_wr__go_i$87
-    connect \dest1_o \dest1_o$95
-    connect \cr_a_ok \cr_a_ok$99
-    connect \dest2_o \dest2_o$103
-    connect \xer_ca_ok \xer_ca_ok$106
-    connect \dest3_o \dest3_o$109
-  end
-  cell \ldst0 \ldst0
-    connect \cu_ad__go_i \cu_ad__go_i
-    connect \cu_ad__rel_o \cu_ad__rel_o
-    connect \cu_st__go_i \cu_st__go_i
-    connect \cu_st__rel_o \cu_st__rel_o
-    connect \rst \rst
-    connect \clk \clk
-    connect \oper_i_ldst_ldst0__insn_type \oper_i_ldst_ldst0__insn_type
-    connect \oper_i_ldst_ldst0__imm_data__imm \oper_i_ldst_ldst0__imm_data__imm
-    connect \oper_i_ldst_ldst0__imm_data__imm_ok \oper_i_ldst_ldst0__imm_data__imm_ok
-    connect \oper_i_ldst_ldst0__zero_a \oper_i_ldst_ldst0__zero_a
-    connect \oper_i_ldst_ldst0__rc__rc \oper_i_ldst_ldst0__rc__rc
-    connect \oper_i_ldst_ldst0__rc__rc_ok \oper_i_ldst_ldst0__rc__rc_ok
-    connect \oper_i_ldst_ldst0__oe__oe \oper_i_ldst_ldst0__oe__oe
-    connect \oper_i_ldst_ldst0__oe__oe_ok \oper_i_ldst_ldst0__oe__oe_ok
-    connect \oper_i_ldst_ldst0__is_32bit \oper_i_ldst_ldst0__is_32bit
-    connect \oper_i_ldst_ldst0__is_signed \oper_i_ldst_ldst0__is_signed
-    connect \oper_i_ldst_ldst0__data_len \oper_i_ldst_ldst0__data_len
-    connect \oper_i_ldst_ldst0__byte_reverse \oper_i_ldst_ldst0__byte_reverse
-    connect \oper_i_ldst_ldst0__sign_extend \oper_i_ldst_ldst0__sign_extend
-    connect \oper_i_ldst_ldst0__ldst_mode \oper_i_ldst_ldst0__ldst_mode
-    connect \cu_issue_i \cu_issue_i$22
-    connect \cu_busy_o \cu_busy_o$23
-    connect \cu_rdmaskn_i \cu_rdmaskn_i$24
-    connect \cu_rd__rel_o \cu_rd__rel_o$43
-    connect \cu_rd__go_i \cu_rd__go_i$44
-    connect \src1_i \src1_i$45
-    connect \src2_i \src2_i$51
-    connect \src3_i \src3_i$52
-    connect \cu_wr__rel_o \cu_wr__rel_o$88
-    connect \cu_wr__go_i \cu_wr__go_i$89
-    connect \o \o
-    connect \ea \ea
-    connect \ldst_port0_is_ld_i \ldst_port0_is_ld_i
-    connect \ldst_port0_is_st_i \ldst_port0_is_st_i
-    connect \ldst_port0_data_len \ldst_port0_data_len
-    connect \ldst_port0_addr_i \ldst_port0_addr_i
-    connect \ldst_port0_addr_i_ok \ldst_port0_addr_i_ok
-    connect \ldst_port0_addr_exc_o \ldst_port0_addr_exc_o
-    connect \ldst_port0_addr_ok_o \ldst_port0_addr_ok_o
-    connect \ldst_port0_ld_data_o \ldst_port0_ld_data_o
-    connect \ldst_port0_ld_data_o_ok \ldst_port0_ld_data_o_ok
-    connect \ldst_port0_st_data_i \ldst_port0_st_data_i
-    connect \ldst_port0_st_data_i_ok \ldst_port0_st_data_i_ok
+  process $group_21
+    assign \rc$19 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \rc$19 \rc
+    sync init
   end
 end
 attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.l0.pimem.st_active"
-module \st_active
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
-  wire width 1 input 2 \s_st_active
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
-  wire width 1 output 3 \q_st_active
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
-  wire width 1 input 4 \r_st_active
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
-  wire width 1 \q_int
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
-  wire width 1 \q_int$next
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
-  wire width 1 $1
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
-  cell $not $2
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \r_st_active
-    connect \Y $1
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
-  wire width 1 $3
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
-  cell $and $4
+attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe.main.rotator.rotl"
+module \rotl
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:8"
+  wire width 64 input 0 \a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:9"
+  wire width 6 input 1 \b
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:11"
+  wire width 64 output 2 \o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:19"
+  wire width 64 $1
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:18"
+  wire width 8 $2
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:18"
+  cell $sub $3
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
+    parameter \A_WIDTH 7
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \q_int
-    connect \B $1
-    connect \Y $3
+    parameter \B_WIDTH 6
+    parameter \Y_WIDTH 8
+    connect \A 7'1000000
+    connect \B \b
+    connect \Y $2
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
-  wire width 1 $5
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
-  cell $or $6
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:19"
+  cell $shift $4
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
+    parameter \A_WIDTH 128
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A $3
-    connect \B \s_st_active
-    connect \Y $5
+    parameter \B_WIDTH 8
+    parameter \Y_WIDTH 64
+    connect \A { \a \a }
+    connect \B $2
+    connect \Y $1
   end
   process $group_0
-    assign \q_int$next \q_int
-    assign \q_int$next $5
-    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    assign \o 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \o $1
+    sync init
+  end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe.main.rotator"
+module \rotator
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:47"
+  wire width 5 input 0 \me
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:48"
+  wire width 5 input 1 \mb
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:50"
+  wire width 1 input 2 \mb_extra
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:52"
+  wire width 64 input 3 \rs
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:51"
+  wire width 64 input 4 \ra
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:53"
+  wire width 7 input 5 \shift
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:54"
+  wire width 1 input 6 \is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:56"
+  wire width 1 input 7 \arith
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:55"
+  wire width 1 input 8 \right_shift
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:57"
+  wire width 1 input 9 \clear_left
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:58"
+  wire width 1 input 10 \clear_right
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:59"
+  wire width 1 input 11 \sign_ext_rs
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:61"
+  wire width 64 output 12 \result_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:62"
+  wire width 1 output 13 \carry_out_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:8"
+  wire width 64 \rotl_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:9"
+  wire width 6 \rotl_b
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:11"
+  wire width 64 \rotl_o
+  cell \rotl \rotl
+    connect \a \rotl_a
+    connect \b \rotl_b
+    connect \o \rotl_o
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:78"
+  wire width 32 \hi32
+  process $group_0
+    assign \hi32 32'00000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:82"
+    switch { \sign_ext_rs \is_32bit }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:82"
+      case 2'-1
+        assign \hi32 \rs [31:0]
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:84"
+      case 2'1-
+        assign \hi32 { \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:87"
+      case
+        assign \hi32 \rs [63:32]
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:79"
+  wire width 64 \repl32
+  process $group_1
+    assign \repl32 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \repl32 { \hi32 \rs [31:0] }
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:91"
+  wire width 6 \shift_signed
+  process $group_2
+    assign \shift_signed 6'000000
+    assign \shift_signed \shift [5:0]
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:70"
+  wire width 6 \rot_count
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:96"
+  wire width 7 $1
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:96"
+  wire width 7 $2
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:96"
+  cell $neg $3
+    parameter \A_SIGNED 1
+    parameter \A_WIDTH 6
+    parameter \Y_WIDTH 7
+    connect \A \shift_signed
+    connect \Y $2
+  end
+  connect $1 $2
+  process $group_3
+    assign \rot_count 6'000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:95"
+    switch { \right_shift }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:95"
       case 1'1
-        assign \q_int$next 1'0
+        assign \rot_count $1 [5:0]
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:97"
+      case
+        assign \rot_count \shift [5:0]
     end
     sync init
-      update \q_int 1'0
-    sync posedge \clk
-      update \q_int \q_int$next
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
-  wire width 1 $7
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
-  cell $not $8
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \r_st_active
-    connect \Y $7
+  process $group_4
+    assign \rotl_a 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \rotl_a \repl32
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
-  wire width 1 $9
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
-  cell $and $10
+  process $group_5
+    assign \rotl_b 6'000000
+    assign \rotl_b \rot_count
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:71"
+  wire width 64 \rot
+  process $group_6
+    assign \rot 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \rot \rotl_o
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:72"
+  wire width 7 \sh
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:107"
+  wire width 1 $4
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:107"
+  cell $not $5
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \q_int
-    connect \B $7
-    connect \Y $9
+    connect \A \is_32bit
+    connect \Y $4
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
-  wire width 1 $11
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
-  cell $or $12
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:107"
+  wire width 1 $6
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:107"
+  cell $and $7
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $9
-    connect \B \s_st_active
-    connect \Y $11
+    connect \A \shift [6]
+    connect \B $4
+    connect \Y $6
   end
-  process $group_1
-    assign \q_st_active 1'0
-    assign \q_st_active $11
+  process $group_7
+    assign \sh 7'0000000
+    assign \sh { $6 \shift [5:0] }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
-  wire width 1 \qn_st_active
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
-  wire width 1 $13
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
-  cell $not $14
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:73"
+  wire width 7 \mb$8
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:48"
+  wire width 7 $9
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:48"
+  cell $pos $10
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 5
+    parameter \Y_WIDTH 7
+    connect \A \mb
+    connect \Y $9
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:123"
+  wire width 1 $11
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:123"
+  cell $not $12
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \q_st_active
-    connect \Y $13
+    connect \A \sh [5]
+    connect \Y $11
   end
-  process $group_2
-    assign \qn_st_active 1'0
-    assign \qn_st_active $13
+  process $group_8
+    assign \mb$8 7'0000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:113"
+    switch { \right_shift \clear_left }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:113"
+      case 2'-1
+        assign \mb$8 $9
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:115"
+        switch { \is_32bit }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:115"
+          case 1'1
+            assign \mb$8 [6:5] 2'01
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:117"
+          case
+            assign \mb$8 [6:5] { 1'0 \mb_extra }
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:119"
+      case 2'1-
+        assign \mb$8 \sh
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:122"
+        switch { \is_32bit }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:122"
+          case 1'1
+            assign \mb$8 [6:5] { \sh [5] $11 }
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:124"
+      case
+        assign \mb$8 { 1'0 \is_32bit 5'00000 }
+    end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62"
-  wire width 1 \qlq_st_active
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
-  wire width 1 $15
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
-  cell $or $16
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:74"
+  wire width 7 \me$13
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:128"
+  wire width 1 $14
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:128"
+  cell $and $15
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \q_st_active
-    connect \B \q_int
-    connect \Y $15
-  end
-  process $group_3
-    assign \qlq_st_active 1'0
-    assign \qlq_st_active $15
-    sync init
+    connect \A \clear_right
+    connect \B \is_32bit
+    connect \Y $14
   end
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.l0.pimem.ld_active"
-module \ld_active
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
-  wire width 1 input 2 \s_ld_active
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
-  wire width 1 output 3 \q_ld_active
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
-  wire width 1 input 4 \r_ld_active
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
-  wire width 1 \q_int
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
-  wire width 1 \q_int$next
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
-  wire width 1 $1
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
-  cell $not $2
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:131"
+  wire width 1 $16
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:131"
+  cell $not $17
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \r_ld_active
-    connect \Y $1
+    connect \A \clear_left
+    connect \Y $16
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
-  wire width 1 $3
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
-  cell $and $4
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:131"
+  wire width 1 $18
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:131"
+  cell $and $19
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \q_int
-    connect \B $1
-    connect \Y $3
+    connect \A \clear_right
+    connect \B $16
+    connect \Y $18
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
-  wire width 1 $5
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
-  cell $or $6
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:136"
+  wire width 6 $20
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:136"
+  cell $not $21
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A $3
-    connect \B \s_ld_active
-    connect \Y $5
+    parameter \A_WIDTH 6
+    parameter \Y_WIDTH 6
+    connect \A \sh [5:0]
+    connect \Y $20
   end
-  process $group_0
-    assign \q_int$next \q_int
-    assign \q_int$next $5
-    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
-      case 1'1
-        assign \q_int$next 1'0
+  process $group_9
+    assign \me$13 7'0000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:128"
+    switch { $18 $14 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:128"
+      case 2'-1
+        assign \me$13 { 2'01 \me }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:131"
+      case 2'1-
+        assign \me$13 { 1'0 \mb_extra \mb }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:134"
+      case
+        assign \me$13 { \sh [6] $20 }
     end
     sync init
-      update \q_int 1'0
-    sync posedge \clk
-      update \q_int \q_int$next
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
-  wire width 1 $7
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
-  cell $not $8
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:14"
+  wire width 64 \right_mask
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:15"
+  wire width 1 $22
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:15"
+  cell $le $23
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
+    parameter \A_WIDTH 7
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 7
     parameter \Y_WIDTH 1
-    connect \A \r_ld_active
-    connect \Y $7
+    connect \A \mb$8
+    connect \B 7'1000000
+    connect \Y $22
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
-  wire width 1 $9
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
-  cell $and $10
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:16"
+  wire width 257 $24
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:16"
+  wire width 8 $25
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:16"
+  cell $sub $26
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
+    parameter \A_WIDTH 7
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \q_int
-    connect \B $7
-    connect \Y $9
+    parameter \B_WIDTH 7
+    parameter \Y_WIDTH 8
+    connect \A 7'1000000
+    connect \B \mb$8
+    connect \Y $25
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
-  wire width 1 $11
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
-  cell $or $12
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:16"
+  wire width 256 $27
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:16"
+  cell $sshl $28
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
+    parameter \B_WIDTH 8
+    parameter \Y_WIDTH 256
+    connect \A 1'1
+    connect \B $25
+    connect \Y $27
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:16"
+  wire width 257 $29
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:16"
+  cell $sub $30
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 256
+    parameter \B_SIGNED 0
     parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A $9
-    connect \B \s_ld_active
-    connect \Y $11
+    parameter \Y_WIDTH 257
+    connect \A $27
+    connect \B 1'1
+    connect \Y $29
   end
-  process $group_1
-    assign \q_ld_active 1'0
-    assign \q_ld_active $11
+  connect $24 $29
+  process $group_10
+    assign \right_mask 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:15"
+    switch { $22 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:15"
+      case 1'1
+        assign \right_mask $24 [63:0]
+    end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
-  wire width 1 \qn_ld_active
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
-  wire width 1 $13
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
-  cell $not $14
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \q_ld_active
-    connect \Y $13
-  end
-  process $group_2
-    assign \qn_ld_active 1'0
-    assign \qn_ld_active $13
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:75"
+  wire width 64 \mr
+  process $group_11
+    assign \mr 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \mr \right_mask
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62"
-  wire width 1 \qlq_ld_active
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
-  wire width 1 $15
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
-  cell $or $16
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:21"
+  wire width 64 \left_mask
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:22"
+  wire width 257 $31
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:22"
+  wire width 257 $32
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:22"
+  wire width 8 $33
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:22"
+  cell $sub $34
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
+    parameter \A_WIDTH 6
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \q_ld_active
-    connect \B \q_int
-    connect \Y $15
-  end
-  process $group_3
-    assign \qlq_ld_active 1'0
-    assign \qlq_ld_active $15
-    sync init
+    parameter \B_WIDTH 7
+    parameter \Y_WIDTH 8
+    connect \A 6'111111
+    connect \B \me$13
+    connect \Y $33
   end
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.l0.pimem.reset_l"
-module \reset_l
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
-  wire width 1 input 2 \s_reset
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
-  wire width 1 input 3 \r_reset
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
-  wire width 1 output 4 \q_reset
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
-  wire width 1 \q_int
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
-  wire width 1 \q_int$next
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
-  wire width 1 $1
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
-  cell $not $2
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:22"
+  wire width 256 $35
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:22"
+  cell $sshl $36
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \r_reset
-    connect \Y $1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 8
+    parameter \Y_WIDTH 256
+    connect \A 1'1
+    connect \B $33
+    connect \Y $35
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
-  wire width 1 $3
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
-  cell $and $4
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:22"
+  wire width 257 $37
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:22"
+  cell $sub $38
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
+    parameter \A_WIDTH 256
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \q_int
-    connect \B $1
-    connect \Y $3
+    parameter \Y_WIDTH 257
+    connect \A $35
+    connect \B 1'1
+    connect \Y $37
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
-  wire width 1 $5
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
-  cell $or $6
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:22"
+  cell $not $39
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A $3
-    connect \B \s_reset
-    connect \Y $5
+    parameter \A_WIDTH 257
+    parameter \Y_WIDTH 257
+    connect \A $37
+    connect \Y $32
   end
-  process $group_0
-    assign \q_int$next \q_int
-    assign \q_int$next $5
-    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
-      case 1'1
-        assign \q_int$next 1'0
-    end
+  connect $31 $32
+  process $group_12
+    assign \left_mask 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \left_mask $31 [63:0]
     sync init
-      update \q_int 1'0
-    sync posedge \clk
-      update \q_int \q_int$next
   end
-  process $group_1
-    assign \q_reset 1'0
-    assign \q_reset \q_int
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:76"
+  wire width 64 \ml
+  process $group_13
+    assign \ml 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \ml \left_mask
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
-  wire width 1 \qn_reset
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
-  wire width 1 $7
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
-  cell $not $8
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:77"
+  wire width 2 \output_mode
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:147"
+  wire width 1 $40
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:147"
+  cell $not $41
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \q_reset
-    connect \Y $7
-  end
-  process $group_2
-    assign \qn_reset 1'0
-    assign \qn_reset $7
-    sync init
+    connect \A \clear_right
+    connect \Y $40
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62"
-  wire width 1 \qlq_reset
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
-  wire width 1 $9
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
-  cell $or $10
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:147"
+  wire width 1 $42
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:147"
+  cell $and $43
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \q_reset
-    connect \B \q_int
-    connect \Y $9
-  end
-  process $group_3
-    assign \qlq_reset 1'0
-    assign \qlq_reset $9
-    sync init
+    connect \A \clear_left
+    connect \B $40
+    connect \Y $42
   end
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.l0.pimem.adrok_l"
-module \adrok_l
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
-  wire width 1 input 2 \s_addr_acked
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
-  wire width 1 input 3 \r_addr_acked
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
-  wire width 1 output 4 \qn_addr_acked
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
-  wire width 1 output 5 \q_addr_acked
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
-  wire width 1 \q_int
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
-  wire width 1 \q_int$next
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
-  wire width 1 $1
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
-  cell $not $2
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:147"
+  wire width 1 $44
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:147"
+  cell $or $45
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \r_addr_acked
-    connect \Y $1
+    connect \A $42
+    connect \B \right_shift
+    connect \Y $44
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
-  wire width 1 $3
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
-  cell $and $4
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:148"
+  wire width 1 $46
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:148"
+  cell $and $47
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \q_int
-    connect \B $1
-    connect \Y $3
+    connect \A \arith
+    connect \B \repl32 [63]
+    connect \Y $46
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
-  wire width 1 $5
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
-  cell $or $6
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:150"
+  wire width 1 $48
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:150"
+  cell $gt $49
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 6
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 6
+    parameter \Y_WIDTH 1
+    connect \A \mb$8 [5:0]
+    connect \B \me$13 [5:0]
+    connect \Y $48
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:150"
+  wire width 1 $50
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:150"
+  cell $and $51
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $3
-    connect \B \s_addr_acked
-    connect \Y $5
+    connect \A \clear_right
+    connect \B $48
+    connect \Y $50
   end
-  process $group_0
-    assign \q_int$next \q_int
-    assign \q_int$next $5
-    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+  process $group_14
+    assign \output_mode 2'00
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:147"
+    switch { $44 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:147"
       case 1'1
-        assign \q_int$next 1'0
+        assign \output_mode { 1'1 $46 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:149"
+      case
+        assign \output_mode { 1'0 $50 }
     end
     sync init
-      update \q_int 1'0
-    sync posedge \clk
-      update \q_int \q_int$next
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
-  wire width 1 $7
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
-  cell $not $8
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:156"
+  wire width 64 $52
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:156"
+  cell $and $53
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \r_addr_acked
-    connect \Y $7
+    parameter \A_WIDTH 64
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 64
+    parameter \Y_WIDTH 64
+    connect \A \mr
+    connect \B \ml
+    connect \Y $52
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
-  wire width 1 $9
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
-  cell $and $10
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:156"
+  wire width 64 $54
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:156"
+  cell $and $55
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
+    parameter \A_WIDTH 64
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \q_int
-    connect \B $7
-    connect \Y $9
+    parameter \B_WIDTH 64
+    parameter \Y_WIDTH 64
+    connect \A \rot
+    connect \B $52
+    connect \Y $54
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
-  wire width 1 $11
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
-  cell $or $12
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:156"
+  wire width 64 $56
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:156"
+  wire width 64 $57
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:156"
+  cell $and $58
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
+    parameter \A_WIDTH 64
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A $9
-    connect \B \s_addr_acked
-    connect \Y $11
-  end
-  process $group_1
-    assign \q_addr_acked 1'0
-    assign \q_addr_acked $11
-    sync init
+    parameter \B_WIDTH 64
+    parameter \Y_WIDTH 64
+    connect \A \mr
+    connect \B \ml
+    connect \Y $57
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
-  wire width 1 $13
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
-  cell $not $14
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:156"
+  cell $not $59
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \q_addr_acked
-    connect \Y $13
-  end
-  process $group_2
-    assign \qn_addr_acked 1'0
-    assign \qn_addr_acked $13
-    sync init
+    parameter \A_WIDTH 64
+    parameter \Y_WIDTH 64
+    connect \A $57
+    connect \Y $56
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62"
-  wire width 1 \qlq_addr_acked
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
-  wire width 1 $15
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
-  cell $or $16
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:156"
+  wire width 64 $60
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:156"
+  cell $and $61
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
+    parameter \A_WIDTH 64
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \q_addr_acked
-    connect \B \q_int
-    connect \Y $15
+    parameter \B_WIDTH 64
+    parameter \Y_WIDTH 64
+    connect \A \ra
+    connect \B $56
+    connect \Y $60
   end
-  process $group_3
-    assign \qlq_addr_acked 1'0
-    assign \qlq_addr_acked $15
-    sync init
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:156"
+  wire width 64 $62
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:156"
+  cell $or $63
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 64
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 64
+    parameter \Y_WIDTH 64
+    connect \A $54
+    connect \B $60
+    connect \Y $62
   end
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.l0.pimem.busy_l"
-module \busy_l
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
-  wire width 1 input 2 \s_busy
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
-  wire width 1 input 3 \r_busy
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
-  wire width 1 output 4 \q_busy
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
-  wire width 1 \q_int
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
-  wire width 1 \q_int$next
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
-  wire width 1 $1
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
-  cell $not $2
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:158"
+  wire width 64 $64
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:158"
+  cell $or $65
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \r_busy
-    connect \Y $1
+    parameter \A_WIDTH 64
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 64
+    parameter \Y_WIDTH 64
+    connect \A \mr
+    connect \B \ml
+    connect \Y $64
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
-  wire width 1 $3
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
-  cell $and $4
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:158"
+  wire width 64 $66
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:158"
+  cell $and $67
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
+    parameter \A_WIDTH 64
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \q_int
-    connect \B $1
-    connect \Y $3
+    parameter \B_WIDTH 64
+    parameter \Y_WIDTH 64
+    connect \A \rot
+    connect \B $64
+    connect \Y $66
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
-  wire width 1 $5
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
-  cell $or $6
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:158"
+  wire width 64 $68
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:158"
+  wire width 64 $69
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:158"
+  cell $or $70
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
+    parameter \A_WIDTH 64
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A $3
-    connect \B \s_busy
-    connect \Y $5
+    parameter \B_WIDTH 64
+    parameter \Y_WIDTH 64
+    connect \A \mr
+    connect \B \ml
+    connect \Y $69
   end
-  process $group_0
-    assign \q_int$next \q_int
-    assign \q_int$next $5
-    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
-      case 1'1
-        assign \q_int$next 1'0
-    end
-    sync init
-      update \q_int 1'0
-    sync posedge \clk
-      update \q_int \q_int$next
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
-  wire width 1 $7
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
-  cell $not $8
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:158"
+  cell $not $71
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \r_busy
-    connect \Y $7
+    parameter \A_WIDTH 64
+    parameter \Y_WIDTH 64
+    connect \A $69
+    connect \Y $68
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
-  wire width 1 $9
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
-  cell $and $10
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:158"
+  wire width 64 $72
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:158"
+  cell $and $73
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
+    parameter \A_WIDTH 64
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \q_int
-    connect \B $7
-    connect \Y $9
+    parameter \B_WIDTH 64
+    parameter \Y_WIDTH 64
+    connect \A \ra
+    connect \B $68
+    connect \Y $72
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
-  wire width 1 $11
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
-  cell $or $12
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:158"
+  wire width 64 $74
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:158"
+  cell $or $75
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
+    parameter \A_WIDTH 64
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A $9
-    connect \B \s_busy
-    connect \Y $11
-  end
-  process $group_1
-    assign \q_busy 1'0
-    assign \q_busy $11
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
-  wire width 1 \qn_busy
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
-  wire width 1 $13
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
-  cell $not $14
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \q_busy
-    connect \Y $13
-  end
-  process $group_2
-    assign \qn_busy 1'0
-    assign \qn_busy $13
-    sync init
+    parameter \B_WIDTH 64
+    parameter \Y_WIDTH 64
+    connect \A $66
+    connect \B $72
+    connect \Y $74
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62"
-  wire width 1 \qlq_busy
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
-  wire width 1 $15
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
-  cell $or $16
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:160"
+  wire width 64 $76
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:160"
+  cell $and $77
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
+    parameter \A_WIDTH 64
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \q_busy
-    connect \B \q_int
-    connect \Y $15
-  end
-  process $group_3
-    assign \qlq_busy 1'0
-    assign \qlq_busy $15
-    sync init
-  end
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.l0.pimem.cyc_l"
-module \cyc_l
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
-  wire width 1 input 2 \s_cyc
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
-  wire width 1 input 3 \r_cyc
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
-  wire width 1 output 4 \q_cyc
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
-  wire width 1 \q_int
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
-  wire width 1 \q_int$next
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
-  wire width 1 $1
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
-  cell $not $2
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \r_cyc
-    connect \Y $1
+    parameter \B_WIDTH 64
+    parameter \Y_WIDTH 64
+    connect \A \rot
+    connect \B \mr
+    connect \Y $76
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
-  wire width 1 $3
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
-  cell $and $4
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:162"
+  wire width 64 $78
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:162"
+  cell $not $79
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \q_int
-    connect \B $1
-    connect \Y $3
+    parameter \A_WIDTH 64
+    parameter \Y_WIDTH 64
+    connect \A \mr
+    connect \Y $78
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
-  wire width 1 $5
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
-  cell $or $6
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:162"
+  wire width 64 $80
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:162"
+  cell $or $81
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
+    parameter \A_WIDTH 64
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A $3
-    connect \B \s_cyc
-    connect \Y $5
+    parameter \B_WIDTH 64
+    parameter \Y_WIDTH 64
+    connect \A \rot
+    connect \B $78
+    connect \Y $80
   end
-  process $group_0
-    assign \q_int$next \q_int
-    assign \q_int$next $5
-    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
-      case 1'1
-        assign \q_int$next 1'0
+  process $group_15
+    assign \result_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:154"
+    switch \output_mode
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:155"
+      case 2'00
+        assign \result_o $62
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:157"
+      case 2'01
+        assign \result_o $74
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:159"
+      case 2'10
+        assign \result_o $76
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:161"
+      case 2'11
+        assign \result_o $80
     end
-    sync init
-      update \q_int 1'0
-    sync posedge \clk
-      update \q_int \q_int$next
-  end
-  process $group_1
-    assign \q_cyc 1'0
-    assign \q_cyc \q_int
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
-  wire width 1 \qn_cyc
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
-  wire width 1 $7
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
-  cell $not $8
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \q_cyc
-    connect \Y $7
-  end
-  process $group_2
-    assign \qn_cyc 1'0
-    assign \qn_cyc $7
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62"
-  wire width 1 \qlq_cyc
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
-  wire width 1 $9
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
-  cell $or $10
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \q_cyc
-    connect \B \q_int
-    connect \Y $9
-  end
-  process $group_3
-    assign \qlq_cyc 1'0
-    assign \qlq_cyc $9
-    sync init
-  end
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.l0.pimem.lenexp"
-module \lenexp
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:130"
-  wire width 4 input 0 \len_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:131"
-  wire width 4 input 1 \addr_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:132"
-  wire width 64 output 2 \lexp_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:134"
-  wire width 176 output 3 \rexp_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:148"
-  wire width 17 \binlen
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150"
-  wire width 21 $1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150"
-  wire width 20 $2
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150"
-  cell $sshl $3
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 5
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 4
-    parameter \Y_WIDTH 20
-    connect \A 5'00001
-    connect \B \len_i
-    connect \Y $2
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150"
-  wire width 21 $4
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150"
-  cell $sub $5
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 20
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 21
-    connect \A $2
-    connect \B 1'1
-    connect \Y $4
-  end
-  connect $1 $4
-  process $group_0
-    assign \binlen 17'00000000000000000
-    assign \binlen $1 [16:0]
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:151"
-  wire width 64 $6
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:151"
-  wire width 32 $7
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:151"
-  cell $sshl $8
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 17
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 4
-    parameter \Y_WIDTH 32
-    connect \A \binlen
-    connect \B \addr_i
-    connect \Y $7
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:151"
-  cell $pos $9
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:164"
+  wire width 1 $82
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:164"
+  wire width 64 $83
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:164"
+  cell $not $84
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 32
+    parameter \A_WIDTH 64
     parameter \Y_WIDTH 64
-    connect \A $7
-    connect \Y $6
-  end
-  process $group_1
-    assign \lexp_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \lexp_o $6
-    sync init
-  end
-  process $group_2
-    assign \rexp_o 176'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
-    assign \rexp_o { { \lexp_o [63] \lexp_o [63] \lexp_o [63] \lexp_o [63] \lexp_o [63] \lexp_o [63] \lexp_o [63] \lexp_o [63] } { \lexp_o [62] \lexp_o [62] \lexp_o [62] \lexp_o [62] \lexp_o [62] \lexp_o [62] \lexp_o [62] \lexp_o [62] } { \lexp_o [61] \lexp_o [61] \lexp_o [61] \lexp_o [61] \lexp_o [61] \lexp_o [61] \lexp_o [61] \lexp_o [61] } { \lexp_o [60] \lexp_o [60] \lexp_o [60] \lexp_o [60] \lexp_o [60] \lexp_o [60] \lexp_o [60] \lexp_o [60] } { \lexp_o [59] \lexp_o [59] \lexp_o [59] \lexp_o [59] \lexp_o [59] \lexp_o [59] \lexp_o [59] \lexp_o [59] } { \lexp_o [58] \lexp_o [58] \lexp_o [58] \lexp_o [58] \lexp_o [58] \lexp_o [58] \lexp_o [58] \lexp_o [58] } { \lexp_o [57] \lexp_o [57] \lexp_o [57] \lexp_o [57] \lexp_o [57] \lexp_o [57] \lexp_o [57] \lexp_o [57] } { \lexp_o [56] \lexp_o [56] \lexp_o [56] \lexp_o [56] \lexp_o [56] \lexp_o [56] \lexp_o [56] \lexp_o [56] } { \lexp_o [55] \lexp_o [55] \lexp_o [55] \lexp_o [55] \lexp_o [55] \lexp_o [55] \lexp_o [55] \lexp_o [55] } { \lexp_o [54] \lexp_o [54] \lexp_o [54] \lexp_o [54] \lexp_o [54] \lexp_o [54] \lexp_o [54] \lexp_o [54] } { \lexp_o [53] \lexp_o [53] \lexp_o [53] \lexp_o [53] \lexp_o [53] \lexp_o [53] \lexp_o [53] \lexp_o [53] } { \lexp_o [52] \lexp_o [52] \lexp_o [52] \lexp_o [52] \lexp_o [52] \lexp_o [52] \lexp_o [52] \lexp_o [52] } { \lexp_o [51] \lexp_o [51] \lexp_o [51] \lexp_o [51] \lexp_o [51] \lexp_o [51] \lexp_o [51] \lexp_o [51] } { \lexp_o [50] \lexp_o [50] \lexp_o [50] \lexp_o [50] \lexp_o [50] \lexp_o [50] \lexp_o [50] \lexp_o [50] } { \lexp_o [49] \lexp_o [49] \lexp_o [49] \lexp_o [49] \lexp_o [49] \lexp_o [49] \lexp_o [49] \lexp_o [49] } { \lexp_o [48] \lexp_o [48] \lexp_o [48] \lexp_o [48] \lexp_o [48] \lexp_o [48] \lexp_o [48] \lexp_o [48] } { \lexp_o [47] \lexp_o [47] \lexp_o [47] \lexp_o [47] \lexp_o [47] \lexp_o [47] \lexp_o [47] \lexp_o [47] } { \lexp_o [46] \lexp_o [46] \lexp_o [46] \lexp_o [46] \lexp_o [46] \lexp_o [46] \lexp_o [46] \lexp_o [46] } { \lexp_o [45] \lexp_o [45] \lexp_o [45] \lexp_o [45] \lexp_o [45] \lexp_o [45] \lexp_o [45] \lexp_o [45] } { \lexp_o [44] \lexp_o [44] \lexp_o [44] \lexp_o [44] \lexp_o [44] \lexp_o [44] \lexp_o [44] \lexp_o [44] } { \lexp_o [43] \lexp_o [43] \lexp_o [43] \lexp_o [43] \lexp_o [43] \lexp_o [43] \lexp_o [43] \lexp_o [43] } { \lexp_o [42] \lexp_o [42] \lexp_o [42] \lexp_o [42] \lexp_o [42] \lexp_o [42] \lexp_o [42] \lexp_o [42] } { \lexp_o [41] \lexp_o [41] \lexp_o [41] \lexp_o [41] \lexp_o [41] \lexp_o [41] \lexp_o [41] \lexp_o [41] } { \lexp_o [40] \lexp_o [40] \lexp_o [40] \lexp_o [40] \lexp_o [40] \lexp_o [40] \lexp_o [40] \lexp_o [40] } { \lexp_o [39] \lexp_o [39] \lexp_o [39] \lexp_o [39] \lexp_o [39] \lexp_o [39] \lexp_o [39] \lexp_o [39] } { \lexp_o [38] \lexp_o [38] \lexp_o [38] \lexp_o [38] \lexp_o [38] \lexp_o [38] \lexp_o [38] \lexp_o [38] } { \lexp_o [37] \lexp_o [37] \lexp_o [37] \lexp_o [37] \lexp_o [37] \lexp_o [37] \lexp_o [37] \lexp_o [37] } { \lexp_o [36] \lexp_o [36] \lexp_o [36] \lexp_o [36] \lexp_o [36] \lexp_o [36] \lexp_o [36] \lexp_o [36] } { \lexp_o [35] \lexp_o [35] \lexp_o [35] \lexp_o [35] \lexp_o [35] \lexp_o [35] \lexp_o [35] \lexp_o [35] } { \lexp_o [34] \lexp_o [34] \lexp_o [34] \lexp_o [34] \lexp_o [34] \lexp_o [34] \lexp_o [34] \lexp_o [34] } { \lexp_o [33] \lexp_o [33] \lexp_o [33] \lexp_o [33] \lexp_o [33] \lexp_o [33] \lexp_o [33] \lexp_o [33] } { \lexp_o [32] \lexp_o [32] \lexp_o [32] \lexp_o [32] \lexp_o [32] \lexp_o [32] \lexp_o [32] \lexp_o [32] } { \lexp_o [31] \lexp_o [31] \lexp_o [31] \lexp_o [31] \lexp_o [31] \lexp_o [31] \lexp_o [31] \lexp_o [31] } { \lexp_o [30] \lexp_o [30] \lexp_o [30] \lexp_o [30] \lexp_o [30] \lexp_o [30] \lexp_o [30] \lexp_o [30] } { \lexp_o [29] \lexp_o [29] \lexp_o [29] \lexp_o [29] \lexp_o [29] \lexp_o [29] \lexp_o [29] \lexp_o [29] } { \lexp_o [28] \lexp_o [28] \lexp_o [28] \lexp_o [28] \lexp_o [28] \lexp_o [28] \lexp_o [28] \lexp_o [28] } { \lexp_o [27] \lexp_o [27] \lexp_o [27] \lexp_o [27] \lexp_o [27] \lexp_o [27] \lexp_o [27] \lexp_o [27] } { \lexp_o [26] \lexp_o [26] \lexp_o [26] \lexp_o [26] \lexp_o [26] \lexp_o [26] \lexp_o [26] \lexp_o [26] } { \lexp_o [25] \lexp_o [25] \lexp_o [25] \lexp_o [25] \lexp_o [25] \lexp_o [25] \lexp_o [25] \lexp_o [25] } { \lexp_o [24] \lexp_o [24] \lexp_o [24] \lexp_o [24] \lexp_o [24] \lexp_o [24] \lexp_o [24] \lexp_o [24] } { \lexp_o [23] \lexp_o [23] \lexp_o [23] \lexp_o [23] \lexp_o [23] \lexp_o [23] \lexp_o [23] \lexp_o [23] } { \lexp_o [22] \lexp_o [22] \lexp_o [22] \lexp_o [22] \lexp_o [22] \lexp_o [22] \lexp_o [22] \lexp_o [22] } { \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21] } { \lexp_o [20] \lexp_o [20] \lexp_o [20] \lexp_o [20] \lexp_o [20] \lexp_o [20] \lexp_o [20] \lexp_o [20] } { \lexp_o [19] \lexp_o [19] \lexp_o [19] \lexp_o [19] \lexp_o [19] \lexp_o [19] \lexp_o [19] \lexp_o [19] } { \lexp_o [18] \lexp_o [18] \lexp_o [18] \lexp_o [18] \lexp_o [18] \lexp_o [18] \lexp_o [18] \lexp_o [18] } { \lexp_o [17] \lexp_o [17] \lexp_o [17] \lexp_o [17] \lexp_o [17] \lexp_o [17] \lexp_o [17] \lexp_o [17] } { \lexp_o [16] \lexp_o [16] \lexp_o [16] \lexp_o [16] \lexp_o [16] \lexp_o [16] \lexp_o [16] \lexp_o [16] } { \lexp_o [15] \lexp_o [15] \lexp_o [15] \lexp_o [15] \lexp_o [15] \lexp_o [15] \lexp_o [15] \lexp_o [15] } { \lexp_o [14] \lexp_o [14] \lexp_o [14] \lexp_o [14] \lexp_o [14] \lexp_o [14] \lexp_o [14] \lexp_o [14] } { \lexp_o [13] \lexp_o [13] \lexp_o [13] \lexp_o [13] \lexp_o [13] \lexp_o [13] \lexp_o [13] \lexp_o [13] } { \lexp_o [12] \lexp_o [12] \lexp_o [12] \lexp_o [12] \lexp_o [12] \lexp_o [12] \lexp_o [12] \lexp_o [12] } { \lexp_o [11] \lexp_o [11] \lexp_o [11] \lexp_o [11] \lexp_o [11] \lexp_o [11] \lexp_o [11] \lexp_o [11] } { \lexp_o [10] \lexp_o [10] \lexp_o [10] \lexp_o [10] \lexp_o [10] \lexp_o [10] \lexp_o [10] \lexp_o [10] } { \lexp_o [9] \lexp_o [9] \lexp_o [9] \lexp_o [9] \lexp_o [9] \lexp_o [9] \lexp_o [9] \lexp_o [9] } { \lexp_o [8] \lexp_o [8] \lexp_o [8] \lexp_o [8] \lexp_o [8] \lexp_o [8] \lexp_o [8] \lexp_o [8] } { \lexp_o [7] \lexp_o [7] \lexp_o [7] \lexp_o [7] \lexp_o [7] \lexp_o [7] \lexp_o [7] \lexp_o [7] } { \lexp_o [6] \lexp_o [6] \lexp_o [6] \lexp_o [6] \lexp_o [6] \lexp_o [6] \lexp_o [6] \lexp_o [6] } { \lexp_o [5] \lexp_o [5] \lexp_o [5] \lexp_o [5] \lexp_o [5] \lexp_o [5] \lexp_o [5] \lexp_o [5] } { \lexp_o [4] \lexp_o [4] \lexp_o [4] \lexp_o [4] \lexp_o [4] \lexp_o [4] \lexp_o [4] \lexp_o [4] } { \lexp_o [3] \lexp_o [3] \lexp_o [3] \lexp_o [3] \lexp_o [3] \lexp_o [3] \lexp_o [3] \lexp_o [3] } { \lexp_o [2] \lexp_o [2] \lexp_o [2] \lexp_o [2] \lexp_o [2] \lexp_o [2] \lexp_o [2] \lexp_o [2] } { \lexp_o [1] \lexp_o [1] \lexp_o [1] \lexp_o [1] \lexp_o [1] \lexp_o [1] \lexp_o [1] \lexp_o [1] } { \lexp_o [0] \lexp_o [0] \lexp_o [0] \lexp_o [0] \lexp_o [0] \lexp_o [0] \lexp_o [0] \lexp_o [0] } } [175:0]
-    sync init
-  end
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.l0.pimem.valid_l"
-module \valid_l
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
-  wire width 1 input 2 \s_valid
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
-  wire width 1 output 3 \q_valid
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
-  wire width 1 input 4 \r_valid
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
-  wire width 1 \q_int
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
-  wire width 1 \q_int$next
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
-  wire width 1 $1
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
-  cell $not $2
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \r_valid
-    connect \Y $1
+    connect \A \ml
+    connect \Y $83
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
-  wire width 1 $3
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
-  cell $and $4
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:164"
+  wire width 64 $85
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:164"
+  cell $and $86
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
+    parameter \A_WIDTH 64
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \q_int
-    connect \B $1
-    connect \Y $3
+    parameter \B_WIDTH 64
+    parameter \Y_WIDTH 64
+    connect \A \rs
+    connect \B $83
+    connect \Y $85
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
-  wire width 1 $5
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
-  cell $or $6
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:164"
+  cell $reduce_bool $87
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
+    parameter \A_WIDTH 64
     parameter \Y_WIDTH 1
-    connect \A $3
-    connect \B \s_valid
-    connect \Y $5
+    connect \A $85
+    connect \Y $82
   end
-  process $group_0
-    assign \q_int$next \q_int
-    assign \q_int$next $5
-    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
-      case 1'1
-        assign \q_int$next 1'0
+  process $group_16
+    assign \carry_out_o 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:154"
+    switch \output_mode
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:155"
+      case 2'00
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:157"
+      case 2'01
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:159"
+      case 2'10
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:161"
+      case 2'11
+        assign \carry_out_o $82
     end
-    sync init
-      update \q_int 1'0
-    sync posedge \clk
-      update \q_int \q_int$next
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
-  wire width 1 $7
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
-  cell $not $8
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \r_valid
-    connect \Y $7
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
-  wire width 1 $9
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
-  cell $and $10
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \q_int
-    connect \B $7
-    connect \Y $9
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
-  wire width 1 $11
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
-  cell $or $12
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A $9
-    connect \B \s_valid
-    connect \Y $11
-  end
-  process $group_1
-    assign \q_valid 1'0
-    assign \q_valid $11
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
-  wire width 1 \qn_valid
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
-  wire width 1 $13
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
-  cell $not $14
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \q_valid
-    connect \Y $13
-  end
-  process $group_2
-    assign \qn_valid 1'0
-    assign \qn_valid $13
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62"
-  wire width 1 \qlq_valid
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
-  wire width 1 $15
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
-  cell $or $16
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \q_valid
-    connect \B \q_int
-    connect \Y $15
-  end
-  process $group_3
-    assign \qlq_valid 1'0
-    assign \qlq_valid $15
     sync init
   end
 end
 attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.l0.pimem"
-module \pimem
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:95"
-  wire width 1 input 2 \ldst_port0_is_ld_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102"
-  wire width 1 output 3 \ldst_port0_busy_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:96"
-  wire width 1 input 4 \ldst_port0_is_st_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99"
-  wire width 4 input 5 \ldst_port0_data_len
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 48 input 6 \ldst_port0_addr_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 input 7 \ldst_port0_addr_i_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:27"
-  wire width 8 output 8 \x_mask_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:26"
-  wire width 48 output 9 \x_addr_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:106"
-  wire width 1 output 10 \ldst_port0_addr_ok_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:45"
-  wire width 64 input 11 \m_ld_data_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 64 output 12 \ldst_port0_ld_data_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 13 \ldst_port0_ld_data_o_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:42"
-  wire width 1 input 14 \x_busy_o
+attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe.main"
+module \main$110
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
+  wire width 2 input 0 \muxid
+  attribute \enum_base_type "MicrOp"
+  attribute \enum_value_0000000 "OP_ILLEGAL"
+  attribute \enum_value_0000001 "OP_NOP"
+  attribute \enum_value_0000010 "OP_ADD"
+  attribute \enum_value_0000011 "OP_ADDPCIS"
+  attribute \enum_value_0000100 "OP_AND"
+  attribute \enum_value_0000101 "OP_ATTN"
+  attribute \enum_value_0000110 "OP_B"
+  attribute \enum_value_0000111 "OP_BC"
+  attribute \enum_value_0001000 "OP_BCREG"
+  attribute \enum_value_0001001 "OP_BPERM"
+  attribute \enum_value_0001010 "OP_CMP"
+  attribute \enum_value_0001011 "OP_CMPB"
+  attribute \enum_value_0001100 "OP_CMPEQB"
+  attribute \enum_value_0001101 "OP_CMPRB"
+  attribute \enum_value_0001110 "OP_CNTZ"
+  attribute \enum_value_0001111 "OP_CRAND"
+  attribute \enum_value_0010000 "OP_CRANDC"
+  attribute \enum_value_0010001 "OP_CREQV"
+  attribute \enum_value_0010010 "OP_CRNAND"
+  attribute \enum_value_0010011 "OP_CRNOR"
+  attribute \enum_value_0010100 "OP_CROR"
+  attribute \enum_value_0010101 "OP_CRORC"
+  attribute \enum_value_0010110 "OP_CRXOR"
+  attribute \enum_value_0010111 "OP_DARN"
+  attribute \enum_value_0011000 "OP_DCBF"
+  attribute \enum_value_0011001 "OP_DCBST"
+  attribute \enum_value_0011010 "OP_DCBT"
+  attribute \enum_value_0011011 "OP_DCBTST"
+  attribute \enum_value_0011100 "OP_DCBZ"
+  attribute \enum_value_0011101 "OP_DIV"
+  attribute \enum_value_0011110 "OP_DIVE"
+  attribute \enum_value_0011111 "OP_EXTS"
+  attribute \enum_value_0100000 "OP_EXTSWSLI"
+  attribute \enum_value_0100001 "OP_ICBI"
+  attribute \enum_value_0100010 "OP_ICBT"
+  attribute \enum_value_0100011 "OP_ISEL"
+  attribute \enum_value_0100100 "OP_ISYNC"
+  attribute \enum_value_0100101 "OP_LOAD"
+  attribute \enum_value_0100110 "OP_STORE"
+  attribute \enum_value_0100111 "OP_MADDHD"
+  attribute \enum_value_0101000 "OP_MADDHDU"
+  attribute \enum_value_0101001 "OP_MADDLD"
+  attribute \enum_value_0101010 "OP_MCRF"
+  attribute \enum_value_0101011 "OP_MCRXR"
+  attribute \enum_value_0101100 "OP_MCRXRX"
+  attribute \enum_value_0101101 "OP_MFCR"
+  attribute \enum_value_0101110 "OP_MFSPR"
+  attribute \enum_value_0101111 "OP_MOD"
+  attribute \enum_value_0110000 "OP_MTCRF"
+  attribute \enum_value_0110001 "OP_MTSPR"
+  attribute \enum_value_0110010 "OP_MUL_L64"
+  attribute \enum_value_0110011 "OP_MUL_H64"
+  attribute \enum_value_0110100 "OP_MUL_H32"
+  attribute \enum_value_0110101 "OP_OR"
+  attribute \enum_value_0110110 "OP_POPCNT"
+  attribute \enum_value_0110111 "OP_PRTY"
+  attribute \enum_value_0111000 "OP_RLC"
+  attribute \enum_value_0111001 "OP_RLCL"
+  attribute \enum_value_0111010 "OP_RLCR"
+  attribute \enum_value_0111011 "OP_SETB"
+  attribute \enum_value_0111100 "OP_SHL"
+  attribute \enum_value_0111101 "OP_SHR"
+  attribute \enum_value_0111110 "OP_SYNC"
+  attribute \enum_value_0111111 "OP_TRAP"
+  attribute \enum_value_1000011 "OP_XOR"
+  attribute \enum_value_1000100 "OP_SIM_CONFIG"
+  attribute \enum_value_1000101 "OP_CROP"
+  attribute \enum_value_1000110 "OP_RFID"
+  attribute \enum_value_1000111 "OP_MFMSR"
+  attribute \enum_value_1001000 "OP_MTMSRD"
+  attribute \enum_value_1001001 "OP_SC"
+  attribute \enum_value_1001010 "OP_MTMSR"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 input 1 \sr_op__insn_type
+  attribute \enum_base_type "Function"
+  attribute \enum_value_00000000000 "NONE"
+  attribute \enum_value_00000000010 "ALU"
+  attribute \enum_value_00000000100 "LDST"
+  attribute \enum_value_00000001000 "SHIFT_ROT"
+  attribute \enum_value_00000010000 "LOGICAL"
+  attribute \enum_value_00000100000 "BRANCH"
+  attribute \enum_value_00001000000 "CR"
+  attribute \enum_value_00010000000 "TRAP"
+  attribute \enum_value_00100000000 "MUL"
+  attribute \enum_value_01000000000 "DIV"
+  attribute \enum_value_10000000000 "SPR"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 input 2 \sr_op__fn_unit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 input 3 \sr_op__imm_data__imm
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 4 \sr_op__imm_data__imm_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 5 \sr_op__rc__rc
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 6 \sr_op__rc__rc_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 7 \sr_op__oe__oe
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 8 \sr_op__oe__oe_ok
+  attribute \enum_base_type "CryIn"
+  attribute \enum_value_00 "ZERO"
+  attribute \enum_value_01 "ONE"
+  attribute \enum_value_10 "CA"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 2 input 10 \sr_op__input_carry
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 11 \sr_op__output_carry
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 12 \sr_op__input_cr
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 13 \sr_op__output_cr
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 14 \sr_op__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 15 \sr_op__is_signed
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 input 16 \sr_op__insn
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
+  wire width 64 input 17 \ra
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
+  wire width 64 input 18 \rb
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
+  wire width 64 input 19 \rc
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
+  wire width 2 output 20 \muxid$1
+  attribute \enum_base_type "MicrOp"
+  attribute \enum_value_0000000 "OP_ILLEGAL"
+  attribute \enum_value_0000001 "OP_NOP"
+  attribute \enum_value_0000010 "OP_ADD"
+  attribute \enum_value_0000011 "OP_ADDPCIS"
+  attribute \enum_value_0000100 "OP_AND"
+  attribute \enum_value_0000101 "OP_ATTN"
+  attribute \enum_value_0000110 "OP_B"
+  attribute \enum_value_0000111 "OP_BC"
+  attribute \enum_value_0001000 "OP_BCREG"
+  attribute \enum_value_0001001 "OP_BPERM"
+  attribute \enum_value_0001010 "OP_CMP"
+  attribute \enum_value_0001011 "OP_CMPB"
+  attribute \enum_value_0001100 "OP_CMPEQB"
+  attribute \enum_value_0001101 "OP_CMPRB"
+  attribute \enum_value_0001110 "OP_CNTZ"
+  attribute \enum_value_0001111 "OP_CRAND"
+  attribute \enum_value_0010000 "OP_CRANDC"
+  attribute \enum_value_0010001 "OP_CREQV"
+  attribute \enum_value_0010010 "OP_CRNAND"
+  attribute \enum_value_0010011 "OP_CRNOR"
+  attribute \enum_value_0010100 "OP_CROR"
+  attribute \enum_value_0010101 "OP_CRORC"
+  attribute \enum_value_0010110 "OP_CRXOR"
+  attribute \enum_value_0010111 "OP_DARN"
+  attribute \enum_value_0011000 "OP_DCBF"
+  attribute \enum_value_0011001 "OP_DCBST"
+  attribute \enum_value_0011010 "OP_DCBT"
+  attribute \enum_value_0011011 "OP_DCBTST"
+  attribute \enum_value_0011100 "OP_DCBZ"
+  attribute \enum_value_0011101 "OP_DIV"
+  attribute \enum_value_0011110 "OP_DIVE"
+  attribute \enum_value_0011111 "OP_EXTS"
+  attribute \enum_value_0100000 "OP_EXTSWSLI"
+  attribute \enum_value_0100001 "OP_ICBI"
+  attribute \enum_value_0100010 "OP_ICBT"
+  attribute \enum_value_0100011 "OP_ISEL"
+  attribute \enum_value_0100100 "OP_ISYNC"
+  attribute \enum_value_0100101 "OP_LOAD"
+  attribute \enum_value_0100110 "OP_STORE"
+  attribute \enum_value_0100111 "OP_MADDHD"
+  attribute \enum_value_0101000 "OP_MADDHDU"
+  attribute \enum_value_0101001 "OP_MADDLD"
+  attribute \enum_value_0101010 "OP_MCRF"
+  attribute \enum_value_0101011 "OP_MCRXR"
+  attribute \enum_value_0101100 "OP_MCRXRX"
+  attribute \enum_value_0101101 "OP_MFCR"
+  attribute \enum_value_0101110 "OP_MFSPR"
+  attribute \enum_value_0101111 "OP_MOD"
+  attribute \enum_value_0110000 "OP_MTCRF"
+  attribute \enum_value_0110001 "OP_MTSPR"
+  attribute \enum_value_0110010 "OP_MUL_L64"
+  attribute \enum_value_0110011 "OP_MUL_H64"
+  attribute \enum_value_0110100 "OP_MUL_H32"
+  attribute \enum_value_0110101 "OP_OR"
+  attribute \enum_value_0110110 "OP_POPCNT"
+  attribute \enum_value_0110111 "OP_PRTY"
+  attribute \enum_value_0111000 "OP_RLC"
+  attribute \enum_value_0111001 "OP_RLCL"
+  attribute \enum_value_0111010 "OP_RLCR"
+  attribute \enum_value_0111011 "OP_SETB"
+  attribute \enum_value_0111100 "OP_SHL"
+  attribute \enum_value_0111101 "OP_SHR"
+  attribute \enum_value_0111110 "OP_SYNC"
+  attribute \enum_value_0111111 "OP_TRAP"
+  attribute \enum_value_1000011 "OP_XOR"
+  attribute \enum_value_1000100 "OP_SIM_CONFIG"
+  attribute \enum_value_1000101 "OP_CROP"
+  attribute \enum_value_1000110 "OP_RFID"
+  attribute \enum_value_1000111 "OP_MFMSR"
+  attribute \enum_value_1001000 "OP_MTMSRD"
+  attribute \enum_value_1001001 "OP_SC"
+  attribute \enum_value_1001010 "OP_MTMSR"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 output 21 \sr_op__insn_type$2
+  attribute \enum_base_type "Function"
+  attribute \enum_value_00000000000 "NONE"
+  attribute \enum_value_00000000010 "ALU"
+  attribute \enum_value_00000000100 "LDST"
+  attribute \enum_value_00000001000 "SHIFT_ROT"
+  attribute \enum_value_00000010000 "LOGICAL"
+  attribute \enum_value_00000100000 "BRANCH"
+  attribute \enum_value_00001000000 "CR"
+  attribute \enum_value_00010000000 "TRAP"
+  attribute \enum_value_00100000000 "MUL"
+  attribute \enum_value_01000000000 "DIV"
+  attribute \enum_value_10000000000 "SPR"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 output 22 \sr_op__fn_unit$3
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 output 23 \sr_op__imm_data__imm$4
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 24 \sr_op__imm_data__imm_ok$5
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 25 \sr_op__rc__rc$6
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 26 \sr_op__rc__rc_ok$7
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 27 \sr_op__oe__oe$8
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 28 \sr_op__oe__oe_ok$9
+  attribute \enum_base_type "CryIn"
+  attribute \enum_value_00 "ZERO"
+  attribute \enum_value_01 "ONE"
+  attribute \enum_value_10 "CA"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 2 output 30 \sr_op__input_carry$10
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 31 \sr_op__output_carry$11
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 32 \sr_op__input_cr$12
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 33 \sr_op__output_cr$13
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 34 \sr_op__is_32bit$14
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 35 \sr_op__is_signed$15
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 output 36 \sr_op__insn$16
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 input 15 \ldst_port0_st_data_i_ok
+  wire width 64 output 37 \o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 64 input 16 \ldst_port0_st_data_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:30"
-  wire width 64 output 17 \x_st_data_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:107"
-  wire width 1 input 18 \ldst_port0_addr_exc_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:28"
-  wire width 1 output 19 \x_ld_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:29"
-  wire width 1 output 20 \x_st_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:37"
-  wire width 1 output 21 \m_valid_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:33"
-  wire width 1 output 22 \x_valid_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
-  wire width 1 \st_active_s_st_active
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
-  wire width 1 \st_active_q_st_active
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
-  wire width 1 \st_active_r_st_active
-  cell \st_active \st_active
-    connect \rst \rst
-    connect \clk \clk
-    connect \s_st_active \st_active_s_st_active
-    connect \q_st_active \st_active_q_st_active
-    connect \r_st_active \st_active_r_st_active
+  wire width 1 output 38 \o_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 2 output 39 \xer_ca
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:47"
+  wire width 5 \rotator_me
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:48"
+  wire width 5 \rotator_mb
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:50"
+  wire width 1 \rotator_mb_extra
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:52"
+  wire width 64 \rotator_rs
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:51"
+  wire width 64 \rotator_ra
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:53"
+  wire width 7 \rotator_shift
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:54"
+  wire width 1 \rotator_is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:56"
+  wire width 1 \rotator_arith
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:55"
+  wire width 1 \rotator_right_shift
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:57"
+  wire width 1 \rotator_clear_left
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:58"
+  wire width 1 \rotator_clear_right
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:59"
+  wire width 1 \rotator_sign_ext_rs
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:61"
+  wire width 64 \rotator_result_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:62"
+  wire width 1 \rotator_carry_out_o
+  cell \rotator \rotator
+    connect \me \rotator_me
+    connect \mb \rotator_mb
+    connect \mb_extra \rotator_mb_extra
+    connect \rs \rotator_rs
+    connect \ra \rotator_ra
+    connect \shift \rotator_shift
+    connect \is_32bit \rotator_is_32bit
+    connect \arith \rotator_arith
+    connect \right_shift \rotator_right_shift
+    connect \clear_left \rotator_clear_left
+    connect \clear_right \rotator_clear_right
+    connect \sign_ext_rs \rotator_sign_ext_rs
+    connect \result_o \rotator_result_o
+    connect \carry_out_o \rotator_carry_out_o
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
-  wire width 1 \ld_active_s_ld_active
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
-  wire width 1 \ld_active_q_ld_active
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
-  wire width 1 \ld_active_r_ld_active
-  cell \ld_active \ld_active
-    connect \rst \rst
-    connect \clk \clk
-    connect \s_ld_active \ld_active_s_ld_active
-    connect \q_ld_active \ld_active_q_ld_active
-    connect \r_ld_active \ld_active_r_ld_active
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:42"
+  wire width 5 \mb
+  process $group_0
+    assign \mb 5'00000
+    assign \mb { \sr_op__insn [10] \sr_op__insn [9] \sr_op__insn [8] \sr_op__insn [7] \sr_op__insn [6] }
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
-  wire width 1 \reset_l_s_reset
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
-  wire width 1 \reset_l_r_reset
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
-  wire width 1 \reset_l_q_reset
-  cell \reset_l \reset_l
-    connect \rst \rst
-    connect \clk \clk
-    connect \s_reset \reset_l_s_reset
-    connect \r_reset \reset_l_r_reset
-    connect \q_reset \reset_l_q_reset
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:43"
+  wire width 5 \me
+  process $group_1
+    assign \me 5'00000
+    assign \me { \sr_op__insn [5] \sr_op__insn [4] \sr_op__insn [3] \sr_op__insn [2] \sr_op__insn [1] }
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
-  wire width 1 \adrok_l_s_addr_acked
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
-  wire width 1 \adrok_l_s_addr_acked$next
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
-  wire width 1 \adrok_l_r_addr_acked
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
-  wire width 1 \adrok_l_qn_addr_acked
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
-  wire width 1 \adrok_l_q_addr_acked
-  cell \adrok_l \adrok_l
-    connect \rst \rst
-    connect \clk \clk
-    connect \s_addr_acked \adrok_l_s_addr_acked
-    connect \r_addr_acked \adrok_l_r_addr_acked
-    connect \qn_addr_acked \adrok_l_qn_addr_acked
-    connect \q_addr_acked \adrok_l_q_addr_acked
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:44"
+  wire width 1 \mb_extra
+  process $group_2
+    assign \mb_extra 1'0
+    assign \mb_extra { \sr_op__insn [10] \sr_op__insn [9] \sr_op__insn [8] \sr_op__insn [7] \sr_op__insn [6] \sr_op__insn [5] } [0]
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
-  wire width 1 \busy_l_s_busy
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
-  wire width 1 \busy_l_r_busy
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
-  wire width 1 \busy_l_q_busy
-  cell \busy_l \busy_l
-    connect \rst \rst
-    connect \clk \clk
-    connect \s_busy \busy_l_s_busy
-    connect \r_busy \busy_l_r_busy
-    connect \q_busy \busy_l_q_busy
+  process $group_3
+    assign \rotator_me 5'00000
+    assign \rotator_me \me
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
-  wire width 1 \cyc_l_s_cyc
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
-  wire width 1 \cyc_l_r_cyc
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
-  wire width 1 \cyc_l_q_cyc
-  cell \cyc_l \cyc_l
-    connect \rst \rst
-    connect \clk \clk
-    connect \s_cyc \cyc_l_s_cyc
-    connect \r_cyc \cyc_l_r_cyc
-    connect \q_cyc \cyc_l_q_cyc
+  process $group_4
+    assign \rotator_mb 5'00000
+    assign \rotator_mb \mb
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:130"
-  wire width 4 \lenexp_len_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:131"
-  wire width 4 \lenexp_addr_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:132"
-  wire width 64 \lenexp_lexp_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:134"
-  wire width 176 \lenexp_rexp_o
-  cell \lenexp \lenexp
-    connect \len_i \lenexp_len_i
-    connect \addr_i \lenexp_addr_i
-    connect \lexp_o \lenexp_lexp_o
-    connect \rexp_o \lenexp_rexp_o
+  process $group_5
+    assign \rotator_mb_extra 1'0
+    assign \rotator_mb_extra \mb_extra
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
-  wire width 1 \valid_l_s_valid
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
-  wire width 1 \valid_l_q_valid
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
-  wire width 1 \valid_l_r_valid
-  cell \valid_l \valid_l
-    connect \rst \rst
-    connect \clk \clk
-    connect \s_valid \valid_l_s_valid
-    connect \q_valid \valid_l_q_valid
-    connect \r_valid \valid_l_r_valid
+  process $group_6
+    assign \rotator_rs 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \rotator_rs \rc
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:261"
-  wire width 1 $1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:261"
-  cell $or $2
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \ldst_port0_st_data_i_ok
-    connect \B \ldst_port0_ld_data_o_ok
-    connect \Y $1
+  process $group_7
+    assign \rotator_ra 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \rotator_ra \ra
+    sync init
   end
-  process $group_0
-    assign \cyc_l_s_cyc 1'0
-    assign \cyc_l_s_cyc 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:261"
-    switch { $1 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:261"
-      case 1'1
-        assign \cyc_l_s_cyc 1'1
-    end
+  process $group_8
+    assign \rotator_shift 7'0000000
+    assign \rotator_shift \rb [6:0]
     sync init
   end
-  process $group_1
-    assign \cyc_l_r_cyc 1'1
-    assign \cyc_l_r_cyc 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:264"
-    switch { \cyc_l_q_cyc }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:264"
-      case 1'1
-        assign \cyc_l_r_cyc 1'1
-    end
+  process $group_9
+    assign \rotator_is_32bit 1'0
+    assign \rotator_is_32bit \sr_op__is_32bit
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:195"
-  wire width 1 $3
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:195"
-  cell $and $4
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \ldst_port0_addr_i_ok
-    connect \B \adrok_l_qn_addr_acked
-    connect \Y $3
+  process $group_10
+    assign \rotator_arith 1'0
+    assign \rotator_arith \sr_op__is_signed
+    sync init
   end
-  process $group_2
-    assign \adrok_l_s_addr_acked$next \adrok_l_s_addr_acked
-    assign \adrok_l_s_addr_acked$next 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:190"
-    switch { \ld_active_q_ld_active }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:190"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:195"
-        switch { $3 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:195"
-          case 1'1
-            assign \adrok_l_s_addr_acked$next 1'1
-        end
-    end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:202"
-    switch { \st_active_q_st_active }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:202"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:207"
-        switch { \ldst_port0_addr_i_ok }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:207"
-          case 1'1
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:209"
-            switch { \adrok_l_qn_addr_acked }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:209"
-              case 1'1
-                assign \adrok_l_s_addr_acked$next 1'1
-            end
-        end
+  process $group_11
+    assign \o_ok 1'0
+    assign \o_ok 1'1
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:66"
+    switch \sr_op__insn_type
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:67"
+      attribute \nmigen.decoding "OP_SHL/60"
+      case 7'0111100
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:68"
+      attribute \nmigen.decoding "OP_SHR/61"
+      case 7'0111101
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:69"
+      attribute \nmigen.decoding "OP_RLC/56"
+      case 7'0111000
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:70"
+      attribute \nmigen.decoding "OP_RLCL/57"
+      case 7'0111001
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:71"
+      attribute \nmigen.decoding "OP_RLCR/58"
+      case 7'0111010
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:72"
+      attribute \nmigen.decoding "OP_EXTSWSLI/32"
+      case 7'0100000
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:73"
+      attribute \nmigen.decoding ""
+      case
+        assign \o_ok 1'0
     end
-    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
-      case 1'1
-        assign \adrok_l_s_addr_acked$next 1'0
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:65"
+  wire width 4 \mode
+  process $group_12
+    assign \mode 4'0000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:66"
+    switch \sr_op__insn_type
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:67"
+      attribute \nmigen.decoding "OP_SHL/60"
+      case 7'0111100
+        assign \mode 4'0000
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:68"
+      attribute \nmigen.decoding "OP_SHR/61"
+      case 7'0111101
+        assign \mode 4'0001
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:69"
+      attribute \nmigen.decoding "OP_RLC/56"
+      case 7'0111000
+        assign \mode 4'0110
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:70"
+      attribute \nmigen.decoding "OP_RLCL/57"
+      case 7'0111001
+        assign \mode 4'0010
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:71"
+      attribute \nmigen.decoding "OP_RLCR/58"
+      case 7'0111010
+        assign \mode 4'0100
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:72"
+      attribute \nmigen.decoding "OP_EXTSWSLI/32"
+      case 7'0100000
+        assign \mode 4'1000
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:73"
+      attribute \nmigen.decoding ""
+      case
     end
     sync init
-      update \adrok_l_s_addr_acked 1'0
-    sync posedge \clk
-      update \adrok_l_s_addr_acked \adrok_l_s_addr_acked$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:240"
-  wire width 1 \reset_delay
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:240"
-  wire width 1 \reset_delay$next
+  process $group_13
+    assign \rotator_right_shift 1'0
+    assign \rotator_clear_left 1'0
+    assign \rotator_clear_right 1'0
+    assign \rotator_sign_ext_rs 1'0
+    assign { \rotator_sign_ext_rs \rotator_clear_right \rotator_clear_left \rotator_right_shift } \mode
+    sync init
+  end
+  process $group_17
+    assign \o 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \o \rotator_result_o
+    sync init
+  end
+  process $group_18
+    assign \xer_ca 2'00
+    assign \xer_ca { \rotator_carry_out_o \rotator_carry_out_o }
+    sync init
+  end
+  process $group_19
+    assign \muxid$1 2'00
+    assign \muxid$1 \muxid
+    sync init
+  end
+  process $group_20
+    assign \sr_op__insn_type$2 7'0000000
+    assign \sr_op__fn_unit$3 11'00000000000
+    assign \sr_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \sr_op__imm_data__imm_ok$5 1'0
+    assign \sr_op__rc__rc$6 1'0
+    assign \sr_op__rc__rc_ok$7 1'0
+    assign \sr_op__oe__oe$8 1'0
+    assign \sr_op__oe__oe_ok$9 1'0
+    assign { } 0'0
+    assign \sr_op__input_carry$10 2'00
+    assign \sr_op__output_carry$11 1'0
+    assign \sr_op__input_cr$12 1'0
+    assign \sr_op__output_cr$13 1'0
+    assign \sr_op__is_32bit$14 1'0
+    assign \sr_op__is_signed$15 1'0
+    assign \sr_op__insn$16 32'00000000000000000000000000000000
+    assign { \sr_op__insn$16 \sr_op__is_signed$15 \sr_op__is_32bit$14 \sr_op__output_cr$13 \sr_op__input_cr$12 \sr_op__output_carry$11 \sr_op__input_carry$10 { } { \sr_op__oe__oe_ok$9 \sr_op__oe__oe$8 } { \sr_op__rc__rc_ok$7 \sr_op__rc__rc$6 } { \sr_op__imm_data__imm_ok$5 \sr_op__imm_data__imm$4 } \sr_op__fn_unit$3 \sr_op__insn_type$2 } { \sr_op__insn \sr_op__is_signed \sr_op__is_32bit \sr_op__output_cr \sr_op__input_cr \sr_op__output_carry \sr_op__input_carry { } { \sr_op__oe__oe_ok \sr_op__oe__oe } { \sr_op__rc__rc_ok \sr_op__rc__rc } { \sr_op__imm_data__imm_ok \sr_op__imm_data__imm } \sr_op__fn_unit \sr_op__insn_type }
+    sync init
+  end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe.output"
+module \output$111
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
+  wire width 2 input 0 \muxid
+  attribute \enum_base_type "MicrOp"
+  attribute \enum_value_0000000 "OP_ILLEGAL"
+  attribute \enum_value_0000001 "OP_NOP"
+  attribute \enum_value_0000010 "OP_ADD"
+  attribute \enum_value_0000011 "OP_ADDPCIS"
+  attribute \enum_value_0000100 "OP_AND"
+  attribute \enum_value_0000101 "OP_ATTN"
+  attribute \enum_value_0000110 "OP_B"
+  attribute \enum_value_0000111 "OP_BC"
+  attribute \enum_value_0001000 "OP_BCREG"
+  attribute \enum_value_0001001 "OP_BPERM"
+  attribute \enum_value_0001010 "OP_CMP"
+  attribute \enum_value_0001011 "OP_CMPB"
+  attribute \enum_value_0001100 "OP_CMPEQB"
+  attribute \enum_value_0001101 "OP_CMPRB"
+  attribute \enum_value_0001110 "OP_CNTZ"
+  attribute \enum_value_0001111 "OP_CRAND"
+  attribute \enum_value_0010000 "OP_CRANDC"
+  attribute \enum_value_0010001 "OP_CREQV"
+  attribute \enum_value_0010010 "OP_CRNAND"
+  attribute \enum_value_0010011 "OP_CRNOR"
+  attribute \enum_value_0010100 "OP_CROR"
+  attribute \enum_value_0010101 "OP_CRORC"
+  attribute \enum_value_0010110 "OP_CRXOR"
+  attribute \enum_value_0010111 "OP_DARN"
+  attribute \enum_value_0011000 "OP_DCBF"
+  attribute \enum_value_0011001 "OP_DCBST"
+  attribute \enum_value_0011010 "OP_DCBT"
+  attribute \enum_value_0011011 "OP_DCBTST"
+  attribute \enum_value_0011100 "OP_DCBZ"
+  attribute \enum_value_0011101 "OP_DIV"
+  attribute \enum_value_0011110 "OP_DIVE"
+  attribute \enum_value_0011111 "OP_EXTS"
+  attribute \enum_value_0100000 "OP_EXTSWSLI"
+  attribute \enum_value_0100001 "OP_ICBI"
+  attribute \enum_value_0100010 "OP_ICBT"
+  attribute \enum_value_0100011 "OP_ISEL"
+  attribute \enum_value_0100100 "OP_ISYNC"
+  attribute \enum_value_0100101 "OP_LOAD"
+  attribute \enum_value_0100110 "OP_STORE"
+  attribute \enum_value_0100111 "OP_MADDHD"
+  attribute \enum_value_0101000 "OP_MADDHDU"
+  attribute \enum_value_0101001 "OP_MADDLD"
+  attribute \enum_value_0101010 "OP_MCRF"
+  attribute \enum_value_0101011 "OP_MCRXR"
+  attribute \enum_value_0101100 "OP_MCRXRX"
+  attribute \enum_value_0101101 "OP_MFCR"
+  attribute \enum_value_0101110 "OP_MFSPR"
+  attribute \enum_value_0101111 "OP_MOD"
+  attribute \enum_value_0110000 "OP_MTCRF"
+  attribute \enum_value_0110001 "OP_MTSPR"
+  attribute \enum_value_0110010 "OP_MUL_L64"
+  attribute \enum_value_0110011 "OP_MUL_H64"
+  attribute \enum_value_0110100 "OP_MUL_H32"
+  attribute \enum_value_0110101 "OP_OR"
+  attribute \enum_value_0110110 "OP_POPCNT"
+  attribute \enum_value_0110111 "OP_PRTY"
+  attribute \enum_value_0111000 "OP_RLC"
+  attribute \enum_value_0111001 "OP_RLCL"
+  attribute \enum_value_0111010 "OP_RLCR"
+  attribute \enum_value_0111011 "OP_SETB"
+  attribute \enum_value_0111100 "OP_SHL"
+  attribute \enum_value_0111101 "OP_SHR"
+  attribute \enum_value_0111110 "OP_SYNC"
+  attribute \enum_value_0111111 "OP_TRAP"
+  attribute \enum_value_1000011 "OP_XOR"
+  attribute \enum_value_1000100 "OP_SIM_CONFIG"
+  attribute \enum_value_1000101 "OP_CROP"
+  attribute \enum_value_1000110 "OP_RFID"
+  attribute \enum_value_1000111 "OP_MFMSR"
+  attribute \enum_value_1001000 "OP_MTMSRD"
+  attribute \enum_value_1001001 "OP_SC"
+  attribute \enum_value_1001010 "OP_MTMSR"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 input 1 \sr_op__insn_type
+  attribute \enum_base_type "Function"
+  attribute \enum_value_00000000000 "NONE"
+  attribute \enum_value_00000000010 "ALU"
+  attribute \enum_value_00000000100 "LDST"
+  attribute \enum_value_00000001000 "SHIFT_ROT"
+  attribute \enum_value_00000010000 "LOGICAL"
+  attribute \enum_value_00000100000 "BRANCH"
+  attribute \enum_value_00001000000 "CR"
+  attribute \enum_value_00010000000 "TRAP"
+  attribute \enum_value_00100000000 "MUL"
+  attribute \enum_value_01000000000 "DIV"
+  attribute \enum_value_10000000000 "SPR"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 input 2 \sr_op__fn_unit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 input 3 \sr_op__imm_data__imm
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 4 \sr_op__imm_data__imm_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 5 \sr_op__rc__rc
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 6 \sr_op__rc__rc_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 7 \sr_op__oe__oe
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 8 \sr_op__oe__oe_ok
+  attribute \enum_base_type "CryIn"
+  attribute \enum_value_00 "ZERO"
+  attribute \enum_value_01 "ONE"
+  attribute \enum_value_10 "CA"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 2 input 10 \sr_op__input_carry
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 11 \sr_op__output_carry
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 12 \sr_op__input_cr
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 13 \sr_op__output_cr
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 14 \sr_op__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 15 \sr_op__is_signed
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 input 16 \sr_op__insn
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 64 input 17 \o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 input 18 \o_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 4 input 19 \cr_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 2 input 20 \xer_ca
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
+  wire width 2 output 21 \muxid$1
+  attribute \enum_base_type "MicrOp"
+  attribute \enum_value_0000000 "OP_ILLEGAL"
+  attribute \enum_value_0000001 "OP_NOP"
+  attribute \enum_value_0000010 "OP_ADD"
+  attribute \enum_value_0000011 "OP_ADDPCIS"
+  attribute \enum_value_0000100 "OP_AND"
+  attribute \enum_value_0000101 "OP_ATTN"
+  attribute \enum_value_0000110 "OP_B"
+  attribute \enum_value_0000111 "OP_BC"
+  attribute \enum_value_0001000 "OP_BCREG"
+  attribute \enum_value_0001001 "OP_BPERM"
+  attribute \enum_value_0001010 "OP_CMP"
+  attribute \enum_value_0001011 "OP_CMPB"
+  attribute \enum_value_0001100 "OP_CMPEQB"
+  attribute \enum_value_0001101 "OP_CMPRB"
+  attribute \enum_value_0001110 "OP_CNTZ"
+  attribute \enum_value_0001111 "OP_CRAND"
+  attribute \enum_value_0010000 "OP_CRANDC"
+  attribute \enum_value_0010001 "OP_CREQV"
+  attribute \enum_value_0010010 "OP_CRNAND"
+  attribute \enum_value_0010011 "OP_CRNOR"
+  attribute \enum_value_0010100 "OP_CROR"
+  attribute \enum_value_0010101 "OP_CRORC"
+  attribute \enum_value_0010110 "OP_CRXOR"
+  attribute \enum_value_0010111 "OP_DARN"
+  attribute \enum_value_0011000 "OP_DCBF"
+  attribute \enum_value_0011001 "OP_DCBST"
+  attribute \enum_value_0011010 "OP_DCBT"
+  attribute \enum_value_0011011 "OP_DCBTST"
+  attribute \enum_value_0011100 "OP_DCBZ"
+  attribute \enum_value_0011101 "OP_DIV"
+  attribute \enum_value_0011110 "OP_DIVE"
+  attribute \enum_value_0011111 "OP_EXTS"
+  attribute \enum_value_0100000 "OP_EXTSWSLI"
+  attribute \enum_value_0100001 "OP_ICBI"
+  attribute \enum_value_0100010 "OP_ICBT"
+  attribute \enum_value_0100011 "OP_ISEL"
+  attribute \enum_value_0100100 "OP_ISYNC"
+  attribute \enum_value_0100101 "OP_LOAD"
+  attribute \enum_value_0100110 "OP_STORE"
+  attribute \enum_value_0100111 "OP_MADDHD"
+  attribute \enum_value_0101000 "OP_MADDHDU"
+  attribute \enum_value_0101001 "OP_MADDLD"
+  attribute \enum_value_0101010 "OP_MCRF"
+  attribute \enum_value_0101011 "OP_MCRXR"
+  attribute \enum_value_0101100 "OP_MCRXRX"
+  attribute \enum_value_0101101 "OP_MFCR"
+  attribute \enum_value_0101110 "OP_MFSPR"
+  attribute \enum_value_0101111 "OP_MOD"
+  attribute \enum_value_0110000 "OP_MTCRF"
+  attribute \enum_value_0110001 "OP_MTSPR"
+  attribute \enum_value_0110010 "OP_MUL_L64"
+  attribute \enum_value_0110011 "OP_MUL_H64"
+  attribute \enum_value_0110100 "OP_MUL_H32"
+  attribute \enum_value_0110101 "OP_OR"
+  attribute \enum_value_0110110 "OP_POPCNT"
+  attribute \enum_value_0110111 "OP_PRTY"
+  attribute \enum_value_0111000 "OP_RLC"
+  attribute \enum_value_0111001 "OP_RLCL"
+  attribute \enum_value_0111010 "OP_RLCR"
+  attribute \enum_value_0111011 "OP_SETB"
+  attribute \enum_value_0111100 "OP_SHL"
+  attribute \enum_value_0111101 "OP_SHR"
+  attribute \enum_value_0111110 "OP_SYNC"
+  attribute \enum_value_0111111 "OP_TRAP"
+  attribute \enum_value_1000011 "OP_XOR"
+  attribute \enum_value_1000100 "OP_SIM_CONFIG"
+  attribute \enum_value_1000101 "OP_CROP"
+  attribute \enum_value_1000110 "OP_RFID"
+  attribute \enum_value_1000111 "OP_MFMSR"
+  attribute \enum_value_1001000 "OP_MTMSRD"
+  attribute \enum_value_1001001 "OP_SC"
+  attribute \enum_value_1001010 "OP_MTMSR"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 output 22 \sr_op__insn_type$2
+  attribute \enum_base_type "Function"
+  attribute \enum_value_00000000000 "NONE"
+  attribute \enum_value_00000000010 "ALU"
+  attribute \enum_value_00000000100 "LDST"
+  attribute \enum_value_00000001000 "SHIFT_ROT"
+  attribute \enum_value_00000010000 "LOGICAL"
+  attribute \enum_value_00000100000 "BRANCH"
+  attribute \enum_value_00001000000 "CR"
+  attribute \enum_value_00010000000 "TRAP"
+  attribute \enum_value_00100000000 "MUL"
+  attribute \enum_value_01000000000 "DIV"
+  attribute \enum_value_10000000000 "SPR"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 output 23 \sr_op__fn_unit$3
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 output 24 \sr_op__imm_data__imm$4
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 25 \sr_op__imm_data__imm_ok$5
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 26 \sr_op__rc__rc$6
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 27 \sr_op__rc__rc_ok$7
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 28 \sr_op__oe__oe$8
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 29 \sr_op__oe__oe_ok$9
+  attribute \enum_base_type "CryIn"
+  attribute \enum_value_00 "ZERO"
+  attribute \enum_value_01 "ONE"
+  attribute \enum_value_10 "CA"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 2 output 31 \sr_op__input_carry$10
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 32 \sr_op__output_carry$11
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 33 \sr_op__input_cr$12
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 34 \sr_op__output_cr$13
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 35 \sr_op__is_32bit$14
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 36 \sr_op__is_signed$15
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 output 37 \sr_op__insn$16
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 64 output 38 \o$17
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 output 39 \o_ok$18
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 4 output 40 \cr_a$19
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 output 41 \cr_a_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 2 output 42 \xer_ca$20
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 output 43 \xer_ca_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:23"
+  wire width 65 \o$21
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 65 $22
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  cell $pos $23
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 64
+    parameter \Y_WIDTH 65
+    connect \A \o
+    connect \Y $22
+  end
+  process $group_0
+    assign \o$21 65'00000000000000000000000000000000000000000000000000000000000000000
+    assign \o$21 $22
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:35"
+  wire width 64 \target
+  process $group_1
+    assign \target 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \target \o$21 [63:0]
+    sync init
+  end
+  process $group_2
+    assign \xer_ca$20 2'00
+    assign \xer_ca$20 \xer_ca
+    sync init
+  end
   process $group_3
-    assign \adrok_l_r_addr_acked 1'1
-    assign \adrok_l_r_addr_acked 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:242"
-    switch { \reset_delay }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:242"
-      case 1'1
-        assign \adrok_l_r_addr_acked 1'1
-    end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:246"
-    switch { \reset_l_q_reset }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:246"
-      case 1'1
-        assign \adrok_l_r_addr_acked 1'1
-    end
+    assign \xer_ca_ok 1'0
+    assign \xer_ca_ok \sr_op__output_carry
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:176"
-  wire width 1 \lds
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:179"
-  wire width 1 $5
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:179"
-  cell $and $6
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:54"
+  wire width 1 \is_cmp
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:63"
+  wire width 1 $24
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:63"
+  cell $eq $25
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
+    parameter \A_WIDTH 7
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
+    parameter \B_WIDTH 7
     parameter \Y_WIDTH 1
-    connect \A \ldst_port0_is_ld_i
-    connect \B \ldst_port0_busy_o
-    connect \Y $5
+    connect \A \sr_op__insn_type
+    connect \B 7'0001010
+    connect \Y $24
   end
   process $group_4
-    assign \lds 1'0
-    assign \lds $5
+    assign \is_cmp 1'0
+    assign \is_cmp $24
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:177"
-  wire width 1 \sts
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:180"
-  wire width 1 $7
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:180"
-  cell $and $8
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:55"
+  wire width 1 \is_cmpeqb
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:64"
+  wire width 1 $26
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:64"
+  cell $eq $27
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
+    parameter \A_WIDTH 7
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
+    parameter \B_WIDTH 7
     parameter \Y_WIDTH 1
-    connect \A \ldst_port0_is_st_i
-    connect \B \ldst_port0_busy_o
-    connect \Y $7
+    connect \A \sr_op__insn_type
+    connect \B 7'0001100
+    connect \Y $26
   end
   process $group_5
-    assign \sts 1'0
-    assign \sts $7
+    assign \is_cmpeqb 1'0
+    assign \is_cmpeqb $26
     sync init
   end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:53"
+  wire width 1 \msb_test
   process $group_6
-    assign \ld_active_s_ld_active 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:183"
-    switch { \sts \lds }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:183"
-      case 2'-1
-        assign \ld_active_s_ld_active 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:185"
-      case 2'1-
-    end
-    sync init
-  end
-  process $group_7
-    assign \st_active_s_st_active 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:183"
-    switch { \sts \lds }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:183"
-      case 2'-1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:185"
-      case 2'1-
-        assign \st_active_s_st_active 1'1
-    end
-    sync init
-  end
-  process $group_8
-    assign \lenexp_len_i 4'0000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:190"
-    switch { \ld_active_q_ld_active }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:190"
-      case 1'1
-        assign \lenexp_len_i \ldst_port0_data_len
-    end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:202"
-    switch { \st_active_q_st_active }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:202"
-      case 1'1
-        assign \lenexp_len_i \ldst_port0_data_len
-    end
+    assign \msb_test 1'0
+    assign \msb_test \target [63]
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265"
-  wire width 4 $9
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265"
-  cell $pos $10
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 3
-    parameter \Y_WIDTH 4
-    connect \A \ldst_port0_addr_i [2:0]
-    connect \Y $9
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265"
-  wire width 4 $11
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265"
-  cell $pos $12
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:50"
+  wire width 1 \is_nzero
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71"
+  wire width 1 $28
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71"
+  cell $reduce_bool $29
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 3
-    parameter \Y_WIDTH 4
-    connect \A \ldst_port0_addr_i [2:0]
-    connect \Y $11
+    parameter \A_WIDTH 64
+    parameter \Y_WIDTH 1
+    connect \A \target
+    connect \Y $28
   end
-  process $group_9
-    assign \lenexp_addr_i 4'0000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:190"
-    switch { \ld_active_q_ld_active }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:190"
-      case 1'1
-        assign \lenexp_addr_i $9
-    end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:202"
-    switch { \st_active_q_st_active }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:202"
-      case 1'1
-        assign \lenexp_addr_i $11
-    end
+  process $group_7
+    assign \is_nzero 1'0
+    assign \is_nzero $28
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:195"
-  wire width 1 $13
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:195"
-  cell $and $14
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:51"
+  wire width 1 \is_positive
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77"
+  wire width 1 $30
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77"
+  cell $not $31
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \ldst_port0_addr_i_ok
-    connect \B \adrok_l_qn_addr_acked
-    connect \Y $13
-  end
-  process $group_10
-    assign \valid_l_s_valid 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:190"
-    switch { \ld_active_q_ld_active }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:190"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:195"
-        switch { $13 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:195"
-          case 1'1
-            assign \valid_l_s_valid 1'1
-        end
-    end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:202"
-    switch { \st_active_q_st_active }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:202"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:207"
-        switch { \ldst_port0_addr_i_ok }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:207"
-          case 1'1
-            assign \valid_l_s_valid 1'1
-        end
-    end
-    sync init
+    connect \A \msb_test
+    connect \Y $30
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:195"
-  wire width 1 $15
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:195"
-  cell $and $16
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77"
+  wire width 1 $32
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77"
+  cell $and $33
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \ldst_port0_addr_i_ok
-    connect \B \adrok_l_qn_addr_acked
-    connect \Y $15
+    connect \A \is_nzero
+    connect \B $30
+    connect \Y $32
   end
-  process $group_11
-    assign \x_mask_i 8'00000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:190"
-    switch { \ld_active_q_ld_active }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:190"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:195"
-        switch { $15 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:195"
-          case 1'1
-            assign \x_mask_i \lenexp_lexp_o [7:0]
-        end
-    end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:202"
-    switch { \st_active_q_st_active }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:202"
+  process $group_8
+    assign \is_positive 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:72"
+    switch { \is_cmp }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:72"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:207"
-        switch { \ldst_port0_addr_i_ok }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:207"
-          case 1'1
-            assign \x_mask_i \lenexp_lexp_o [7:0]
-        end
+        assign \is_positive \msb_test
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:75"
+      case
+        assign \is_positive $32
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:195"
-  wire width 1 $17
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:195"
-  cell $and $18
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:52"
+  wire width 1 \is_negative
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:74"
+  wire width 1 $34
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:74"
+  cell $not $35
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \ldst_port0_addr_i_ok
-    connect \B \adrok_l_qn_addr_acked
-    connect \Y $17
-  end
-  process $group_12
-    assign \x_addr_i 48'000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:190"
-    switch { \ld_active_q_ld_active }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:190"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:195"
-        switch { $17 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:195"
-          case 1'1
-            assign \x_addr_i \ldst_port0_addr_i
-        end
-    end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:202"
-    switch { \st_active_q_st_active }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:202"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:207"
-        switch { \ldst_port0_addr_i_ok }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:207"
-          case 1'1
-            assign \x_addr_i \ldst_port0_addr_i
-        end
-    end
-    sync init
+    connect \A \msb_test
+    connect \Y $34
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:195"
-  wire width 1 $19
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:195"
-  cell $and $20
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:74"
+  wire width 1 $36
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:74"
+  cell $and $37
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \ldst_port0_addr_i_ok
-    connect \B \adrok_l_qn_addr_acked
-    connect \Y $19
+    connect \A \is_nzero
+    connect \B $34
+    connect \Y $36
   end
-  process $group_13
-    assign \ldst_port0_addr_ok_o 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:190"
-    switch { \ld_active_q_ld_active }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:190"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:195"
-        switch { $19 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:195"
-          case 1'1
-            assign \ldst_port0_addr_ok_o 1'1
-        end
-    end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:202"
-    switch { \st_active_q_st_active }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:202"
+  process $group_9
+    assign \is_negative 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:72"
+    switch { \is_cmp }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:72"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:207"
-        switch { \ldst_port0_addr_i_ok }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:207"
-          case 1'1
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:209"
-            switch { \adrok_l_qn_addr_acked }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:209"
-              case 1'1
-                assign \ldst_port0_addr_ok_o 1'1
-            end
-        end
+        assign \is_negative $36
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:75"
+      case
+        assign \is_negative \msb_test
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:221"
-  wire width 1 $21
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:221"
-  cell $and $22
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \ld_active_q_ld_active
-    connect \B \adrok_l_q_addr_acked
-    connect \Y $21
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:61"
-  wire width 1 $23
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:61"
-  cell $not $24
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \x_busy_o
-    connect \Y $23
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:229"
-  wire width 1 $25
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:229"
-  cell $and $26
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \st_active_q_st_active
-    connect \B \ldst_port0_st_data_i_ok
-    connect \Y $25
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:58"
-  wire width 1 $27
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:58"
-  cell $not $28
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:57"
+  wire width 4 \cr0
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:82"
+  wire width 1 $38
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:82"
+  cell $not $39
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \x_busy_o
-    connect \Y $27
+    connect \A \is_nzero
+    connect \Y $38
   end
-  process $group_14
-    assign \reset_l_s_reset 1'0
-    assign \reset_l_s_reset 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:221"
-    switch { $21 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:221"
-      case 1'1
-        assign \reset_l_s_reset $23
-    end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:229"
-    switch { $25 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:229"
+  process $group_10
+    assign \cr0 4'0000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:79"
+    switch { \is_cmpeqb }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:79"
       case 1'1
-        assign \reset_l_s_reset $27
+        assign \cr0 \cr_a
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81"
+      case
+        assign \cr0 { \is_negative \is_positive $38 1'0 }
     end
     sync init
   end
-  process $group_15
-    assign \reset_l_r_reset 1'1
-    assign \reset_l_r_reset 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:246"
-    switch { \reset_l_q_reset }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:246"
-      case 1'1
-        assign \reset_l_r_reset 1'1
-    end
+  process $group_11
+    assign \o$17 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \o$17 \o$21 [63:0]
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:217"
-  wire width 64 \lddata
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:220"
-  wire width 176 $29
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:219"
-  wire width 176 $30
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:219"
-  cell $and $31
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 64
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 176
-    parameter \Y_WIDTH 176
-    connect \A \m_ld_data_o
-    connect \B \lenexp_rexp_o
-    connect \Y $30
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:220"
-  wire width 8 $32
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:220"
-  cell $mul $33
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 4
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 4
-    parameter \Y_WIDTH 8
-    connect \A \lenexp_addr_i
-    connect \B 4'1000
-    connect \Y $32
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:220"
-  wire width 176 $34
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:220"
-  cell $sshr $35
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 176
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 8
-    parameter \Y_WIDTH 176
-    connect \A $30
-    connect \B $32
-    connect \Y $34
-  end
-  connect $29 $34
-  process $group_16
-    assign \lddata 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \lddata $29 [63:0]
+  process $group_12
+    assign \o_ok$18 1'0
+    assign \o_ok$18 \o_ok
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:221"
-  wire width 1 $36
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:221"
-  cell $and $37
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \ld_active_q_ld_active
-    connect \B \adrok_l_q_addr_acked
-    connect \Y $36
-  end
-  process $group_17
-    assign \ldst_port0_ld_data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:221"
-    switch { $36 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:221"
-      case 1'1
-        assign \ldst_port0_ld_data_o \lddata
-    end
+  process $group_13
+    assign \cr_a$19 4'0000
+    assign \cr_a$19 \cr0
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:221"
-  wire width 1 $38
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:221"
-  cell $and $39
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \ld_active_q_ld_active
-    connect \B \adrok_l_q_addr_acked
-    connect \Y $38
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:61"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
   wire width 1 $40
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:61"
-  cell $not $41
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  cell $pos $41
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
+    parameter \A_WIDTH 0
     parameter \Y_WIDTH 1
-    connect \A \x_busy_o
+    connect \A { }
     connect \Y $40
   end
-  process $group_18
-    assign \ldst_port0_ld_data_o_ok 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:221"
-    switch { $38 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:221"
-      case 1'1
-        assign \ldst_port0_ld_data_o_ok $40
-    end
+  process $group_14
+    assign \cr_a_ok 1'0
+    assign \cr_a_ok $40
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:232"
-  wire width 64 \stdata
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:229"
-  wire width 1 $42
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:229"
-  cell $and $43
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \st_active_q_st_active
-    connect \B \ldst_port0_st_data_i_ok
-    connect \Y $42
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233"
-  wire width 319 $44
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233"
-  wire width 8 $45
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233"
-  cell $mul $46
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 4
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 4
-    parameter \Y_WIDTH 8
-    connect \A \lenexp_addr_i
-    connect \B 4'1000
-    connect \Y $45
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233"
-  wire width 319 $47
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233"
-  cell $sshl $48
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 64
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 8
-    parameter \Y_WIDTH 319
-    connect \A \ldst_port0_st_data_i
-    connect \B $45
-    connect \Y $47
-  end
-  connect $44 $47
-  process $group_19
-    assign \stdata 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:229"
-    switch { $42 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:229"
-      case 1'1
-        assign \stdata $44 [63:0]
-    end
+  process $group_15
+    assign \muxid$1 2'00
+    assign \muxid$1 \muxid
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:229"
-  wire width 1 $49
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:229"
-  cell $and $50
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \st_active_q_st_active
-    connect \B \ldst_port0_st_data_i_ok
-    connect \Y $49
-  end
-  process $group_20
-    assign \x_st_data_i 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:229"
-    switch { $49 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:229"
-      case 1'1
-        assign \x_st_data_i \stdata
-    end
-    sync init
-  end
-  process $group_21
-    assign \reset_delay$next \reset_delay
-    assign \reset_delay$next \reset_l_q_reset
-    sync init
-      update \reset_delay 1'0
-    sync posedge \clk
-      update \reset_delay \reset_delay$next
-  end
-  process $group_22
-    assign \ld_active_r_ld_active 1'1
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:246"
-    switch { \reset_l_q_reset }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:246"
-      case 1'1
-        assign \ld_active_r_ld_active 1'1
-    end
-    sync init
-  end
-  process $group_23
-    assign \st_active_r_st_active 1'1
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:246"
-    switch { \reset_l_q_reset }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:246"
-      case 1'1
-        assign \st_active_r_st_active 1'1
-    end
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:253"
-  wire width 1 $51
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:253"
-  cell $or $52
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \ldst_port0_is_ld_i
-    connect \B \ldst_port0_is_st_i
-    connect \Y $51
-  end
-  process $group_24
-    assign \busy_l_s_busy 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:253"
-    switch { $51 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:253"
-      case 1'1
-        assign \busy_l_s_busy 1'1
-    end
-    sync init
-  end
-  process $group_25
-    assign \busy_l_r_busy 1'1
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:257"
-    switch { \ldst_port0_addr_exc_o }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:257"
-      case 1'1
-        assign \busy_l_r_busy 1'1
-    end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:264"
-    switch { \cyc_l_q_cyc }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:264"
-      case 1'1
-        assign \busy_l_r_busy 1'1
-    end
-    sync init
-  end
-  process $group_26
-    assign \ldst_port0_busy_o 1'0
-    assign \ldst_port0_busy_o \busy_l_q_busy
-    sync init
-  end
-  process $group_27
-    assign \x_ld_i 1'0
-    assign \x_ld_i \ldst_port0_is_ld_i
-    sync init
-  end
-  process $group_28
-    assign \x_st_i 1'0
-    assign \x_st_i \ldst_port0_is_st_i
-    sync init
-  end
-  process $group_29
-    assign \m_valid_i 1'0
-    assign \m_valid_i \valid_l_q_valid
-    sync init
-  end
-  process $group_30
-    assign \x_valid_i 1'0
-    assign \x_valid_i \valid_l_q_valid
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:79"
-  wire width 1 $53
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:79"
-  cell $not $54
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \ldst_port0_busy_o
-    connect \Y $53
-  end
-  process $group_31
-    assign \valid_l_r_valid 1'1
-    assign \valid_l_r_valid $53
+  process $group_16
+    assign \sr_op__insn_type$2 7'0000000
+    assign \sr_op__fn_unit$3 11'00000000000
+    assign \sr_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \sr_op__imm_data__imm_ok$5 1'0
+    assign \sr_op__rc__rc$6 1'0
+    assign \sr_op__rc__rc_ok$7 1'0
+    assign \sr_op__oe__oe$8 1'0
+    assign \sr_op__oe__oe_ok$9 1'0
+    assign { } 0'0
+    assign \sr_op__input_carry$10 2'00
+    assign \sr_op__output_carry$11 1'0
+    assign \sr_op__input_cr$12 1'0
+    assign \sr_op__output_cr$13 1'0
+    assign \sr_op__is_32bit$14 1'0
+    assign \sr_op__is_signed$15 1'0
+    assign \sr_op__insn$16 32'00000000000000000000000000000000
+    assign { \sr_op__insn$16 \sr_op__is_signed$15 \sr_op__is_32bit$14 \sr_op__output_cr$13 \sr_op__input_cr$12 \sr_op__output_carry$11 \sr_op__input_carry$10 { } { \sr_op__oe__oe_ok$9 \sr_op__oe__oe$8 } { \sr_op__rc__rc_ok$7 \sr_op__rc__rc$6 } { \sr_op__imm_data__imm_ok$5 \sr_op__imm_data__imm$4 } \sr_op__fn_unit$3 \sr_op__insn_type$2 } { \sr_op__insn \sr_op__is_signed \sr_op__is_32bit \sr_op__output_cr \sr_op__input_cr \sr_op__output_carry \sr_op__input_carry { } { \sr_op__oe__oe_ok \sr_op__oe__oe } { \sr_op__rc__rc_ok \sr_op__rc__rc } { \sr_op__imm_data__imm_ok \sr_op__imm_data__imm } \sr_op__fn_unit \sr_op__insn_type }
     sync init
   end
 end
 attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.l0.l0.idx_l"
-module \idx_l
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
-  wire width 1 output 2 \q_idx_l
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
-  wire width 1 input 3 \s_idx_l
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
-  wire width 1 input 4 \r_idx_l
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
-  wire width 1 \q_int
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
-  wire width 1 \q_int$next
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
-  wire width 1 $1
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
-  cell $not $2
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \r_idx_l
-    connect \Y $1
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
-  wire width 1 $3
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
-  cell $and $4
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \q_int
-    connect \B $1
-    connect \Y $3
+attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe"
+module \pipe$106
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153"
+  wire width 1 input 2 \p_valid_i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154"
+  wire width 1 output 3 \p_ready_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
+  wire width 2 input 4 \muxid
+  attribute \enum_base_type "MicrOp"
+  attribute \enum_value_0000000 "OP_ILLEGAL"
+  attribute \enum_value_0000001 "OP_NOP"
+  attribute \enum_value_0000010 "OP_ADD"
+  attribute \enum_value_0000011 "OP_ADDPCIS"
+  attribute \enum_value_0000100 "OP_AND"
+  attribute \enum_value_0000101 "OP_ATTN"
+  attribute \enum_value_0000110 "OP_B"
+  attribute \enum_value_0000111 "OP_BC"
+  attribute \enum_value_0001000 "OP_BCREG"
+  attribute \enum_value_0001001 "OP_BPERM"
+  attribute \enum_value_0001010 "OP_CMP"
+  attribute \enum_value_0001011 "OP_CMPB"
+  attribute \enum_value_0001100 "OP_CMPEQB"
+  attribute \enum_value_0001101 "OP_CMPRB"
+  attribute \enum_value_0001110 "OP_CNTZ"
+  attribute \enum_value_0001111 "OP_CRAND"
+  attribute \enum_value_0010000 "OP_CRANDC"
+  attribute \enum_value_0010001 "OP_CREQV"
+  attribute \enum_value_0010010 "OP_CRNAND"
+  attribute \enum_value_0010011 "OP_CRNOR"
+  attribute \enum_value_0010100 "OP_CROR"
+  attribute \enum_value_0010101 "OP_CRORC"
+  attribute \enum_value_0010110 "OP_CRXOR"
+  attribute \enum_value_0010111 "OP_DARN"
+  attribute \enum_value_0011000 "OP_DCBF"
+  attribute \enum_value_0011001 "OP_DCBST"
+  attribute \enum_value_0011010 "OP_DCBT"
+  attribute \enum_value_0011011 "OP_DCBTST"
+  attribute \enum_value_0011100 "OP_DCBZ"
+  attribute \enum_value_0011101 "OP_DIV"
+  attribute \enum_value_0011110 "OP_DIVE"
+  attribute \enum_value_0011111 "OP_EXTS"
+  attribute \enum_value_0100000 "OP_EXTSWSLI"
+  attribute \enum_value_0100001 "OP_ICBI"
+  attribute \enum_value_0100010 "OP_ICBT"
+  attribute \enum_value_0100011 "OP_ISEL"
+  attribute \enum_value_0100100 "OP_ISYNC"
+  attribute \enum_value_0100101 "OP_LOAD"
+  attribute \enum_value_0100110 "OP_STORE"
+  attribute \enum_value_0100111 "OP_MADDHD"
+  attribute \enum_value_0101000 "OP_MADDHDU"
+  attribute \enum_value_0101001 "OP_MADDLD"
+  attribute \enum_value_0101010 "OP_MCRF"
+  attribute \enum_value_0101011 "OP_MCRXR"
+  attribute \enum_value_0101100 "OP_MCRXRX"
+  attribute \enum_value_0101101 "OP_MFCR"
+  attribute \enum_value_0101110 "OP_MFSPR"
+  attribute \enum_value_0101111 "OP_MOD"
+  attribute \enum_value_0110000 "OP_MTCRF"
+  attribute \enum_value_0110001 "OP_MTSPR"
+  attribute \enum_value_0110010 "OP_MUL_L64"
+  attribute \enum_value_0110011 "OP_MUL_H64"
+  attribute \enum_value_0110100 "OP_MUL_H32"
+  attribute \enum_value_0110101 "OP_OR"
+  attribute \enum_value_0110110 "OP_POPCNT"
+  attribute \enum_value_0110111 "OP_PRTY"
+  attribute \enum_value_0111000 "OP_RLC"
+  attribute \enum_value_0111001 "OP_RLCL"
+  attribute \enum_value_0111010 "OP_RLCR"
+  attribute \enum_value_0111011 "OP_SETB"
+  attribute \enum_value_0111100 "OP_SHL"
+  attribute \enum_value_0111101 "OP_SHR"
+  attribute \enum_value_0111110 "OP_SYNC"
+  attribute \enum_value_0111111 "OP_TRAP"
+  attribute \enum_value_1000011 "OP_XOR"
+  attribute \enum_value_1000100 "OP_SIM_CONFIG"
+  attribute \enum_value_1000101 "OP_CROP"
+  attribute \enum_value_1000110 "OP_RFID"
+  attribute \enum_value_1000111 "OP_MFMSR"
+  attribute \enum_value_1001000 "OP_MTMSRD"
+  attribute \enum_value_1001001 "OP_SC"
+  attribute \enum_value_1001010 "OP_MTMSR"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 input 5 \sr_op__insn_type
+  attribute \enum_base_type "Function"
+  attribute \enum_value_00000000000 "NONE"
+  attribute \enum_value_00000000010 "ALU"
+  attribute \enum_value_00000000100 "LDST"
+  attribute \enum_value_00000001000 "SHIFT_ROT"
+  attribute \enum_value_00000010000 "LOGICAL"
+  attribute \enum_value_00000100000 "BRANCH"
+  attribute \enum_value_00001000000 "CR"
+  attribute \enum_value_00010000000 "TRAP"
+  attribute \enum_value_00100000000 "MUL"
+  attribute \enum_value_01000000000 "DIV"
+  attribute \enum_value_10000000000 "SPR"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 input 6 \sr_op__fn_unit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 input 7 \sr_op__imm_data__imm
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 8 \sr_op__imm_data__imm_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 9 \sr_op__rc__rc
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 10 \sr_op__rc__rc_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 11 \sr_op__oe__oe
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 12 \sr_op__oe__oe_ok
+  attribute \enum_base_type "CryIn"
+  attribute \enum_value_00 "ZERO"
+  attribute \enum_value_01 "ONE"
+  attribute \enum_value_10 "CA"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 2 input 14 \sr_op__input_carry
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 15 \sr_op__output_carry
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 16 \sr_op__input_cr
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 17 \sr_op__output_cr
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 18 \sr_op__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 19 \sr_op__is_signed
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 input 20 \sr_op__insn
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
+  wire width 64 input 21 \ra
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
+  wire width 64 input 22 \rb
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
+  wire width 64 input 23 \rc
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
+  wire width 2 input 24 \xer_ca
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
+  wire width 1 output 25 \n_valid_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
+  wire width 1 input 26 \n_ready_i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
+  wire width 2 output 27 \muxid$1
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
+  wire width 2 \muxid$1$next
+  attribute \enum_base_type "MicrOp"
+  attribute \enum_value_0000000 "OP_ILLEGAL"
+  attribute \enum_value_0000001 "OP_NOP"
+  attribute \enum_value_0000010 "OP_ADD"
+  attribute \enum_value_0000011 "OP_ADDPCIS"
+  attribute \enum_value_0000100 "OP_AND"
+  attribute \enum_value_0000101 "OP_ATTN"
+  attribute \enum_value_0000110 "OP_B"
+  attribute \enum_value_0000111 "OP_BC"
+  attribute \enum_value_0001000 "OP_BCREG"
+  attribute \enum_value_0001001 "OP_BPERM"
+  attribute \enum_value_0001010 "OP_CMP"
+  attribute \enum_value_0001011 "OP_CMPB"
+  attribute \enum_value_0001100 "OP_CMPEQB"
+  attribute \enum_value_0001101 "OP_CMPRB"
+  attribute \enum_value_0001110 "OP_CNTZ"
+  attribute \enum_value_0001111 "OP_CRAND"
+  attribute \enum_value_0010000 "OP_CRANDC"
+  attribute \enum_value_0010001 "OP_CREQV"
+  attribute \enum_value_0010010 "OP_CRNAND"
+  attribute \enum_value_0010011 "OP_CRNOR"
+  attribute \enum_value_0010100 "OP_CROR"
+  attribute \enum_value_0010101 "OP_CRORC"
+  attribute \enum_value_0010110 "OP_CRXOR"
+  attribute \enum_value_0010111 "OP_DARN"
+  attribute \enum_value_0011000 "OP_DCBF"
+  attribute \enum_value_0011001 "OP_DCBST"
+  attribute \enum_value_0011010 "OP_DCBT"
+  attribute \enum_value_0011011 "OP_DCBTST"
+  attribute \enum_value_0011100 "OP_DCBZ"
+  attribute \enum_value_0011101 "OP_DIV"
+  attribute \enum_value_0011110 "OP_DIVE"
+  attribute \enum_value_0011111 "OP_EXTS"
+  attribute \enum_value_0100000 "OP_EXTSWSLI"
+  attribute \enum_value_0100001 "OP_ICBI"
+  attribute \enum_value_0100010 "OP_ICBT"
+  attribute \enum_value_0100011 "OP_ISEL"
+  attribute \enum_value_0100100 "OP_ISYNC"
+  attribute \enum_value_0100101 "OP_LOAD"
+  attribute \enum_value_0100110 "OP_STORE"
+  attribute \enum_value_0100111 "OP_MADDHD"
+  attribute \enum_value_0101000 "OP_MADDHDU"
+  attribute \enum_value_0101001 "OP_MADDLD"
+  attribute \enum_value_0101010 "OP_MCRF"
+  attribute \enum_value_0101011 "OP_MCRXR"
+  attribute \enum_value_0101100 "OP_MCRXRX"
+  attribute \enum_value_0101101 "OP_MFCR"
+  attribute \enum_value_0101110 "OP_MFSPR"
+  attribute \enum_value_0101111 "OP_MOD"
+  attribute \enum_value_0110000 "OP_MTCRF"
+  attribute \enum_value_0110001 "OP_MTSPR"
+  attribute \enum_value_0110010 "OP_MUL_L64"
+  attribute \enum_value_0110011 "OP_MUL_H64"
+  attribute \enum_value_0110100 "OP_MUL_H32"
+  attribute \enum_value_0110101 "OP_OR"
+  attribute \enum_value_0110110 "OP_POPCNT"
+  attribute \enum_value_0110111 "OP_PRTY"
+  attribute \enum_value_0111000 "OP_RLC"
+  attribute \enum_value_0111001 "OP_RLCL"
+  attribute \enum_value_0111010 "OP_RLCR"
+  attribute \enum_value_0111011 "OP_SETB"
+  attribute \enum_value_0111100 "OP_SHL"
+  attribute \enum_value_0111101 "OP_SHR"
+  attribute \enum_value_0111110 "OP_SYNC"
+  attribute \enum_value_0111111 "OP_TRAP"
+  attribute \enum_value_1000011 "OP_XOR"
+  attribute \enum_value_1000100 "OP_SIM_CONFIG"
+  attribute \enum_value_1000101 "OP_CROP"
+  attribute \enum_value_1000110 "OP_RFID"
+  attribute \enum_value_1000111 "OP_MFMSR"
+  attribute \enum_value_1001000 "OP_MTMSRD"
+  attribute \enum_value_1001001 "OP_SC"
+  attribute \enum_value_1001010 "OP_MTMSR"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 output 28 \sr_op__insn_type$2
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 \sr_op__insn_type$2$next
+  attribute \enum_base_type "Function"
+  attribute \enum_value_00000000000 "NONE"
+  attribute \enum_value_00000000010 "ALU"
+  attribute \enum_value_00000000100 "LDST"
+  attribute \enum_value_00000001000 "SHIFT_ROT"
+  attribute \enum_value_00000010000 "LOGICAL"
+  attribute \enum_value_00000100000 "BRANCH"
+  attribute \enum_value_00001000000 "CR"
+  attribute \enum_value_00010000000 "TRAP"
+  attribute \enum_value_00100000000 "MUL"
+  attribute \enum_value_01000000000 "DIV"
+  attribute \enum_value_10000000000 "SPR"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 output 29 \sr_op__fn_unit$3
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 \sr_op__fn_unit$3$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 output 30 \sr_op__imm_data__imm$4
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 \sr_op__imm_data__imm$4$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 31 \sr_op__imm_data__imm_ok$5
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \sr_op__imm_data__imm_ok$5$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 32 \sr_op__rc__rc$6
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \sr_op__rc__rc$6$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 33 \sr_op__rc__rc_ok$7
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \sr_op__rc__rc_ok$7$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 34 \sr_op__oe__oe$8
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \sr_op__oe__oe$8$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 35 \sr_op__oe__oe_ok$9
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \sr_op__oe__oe_ok$9$next
+  attribute \enum_base_type "CryIn"
+  attribute \enum_value_00 "ZERO"
+  attribute \enum_value_01 "ONE"
+  attribute \enum_value_10 "CA"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 2 output 37 \sr_op__input_carry$10
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 2 \sr_op__input_carry$10$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 38 \sr_op__output_carry$11
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \sr_op__output_carry$11$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 39 \sr_op__input_cr$12
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \sr_op__input_cr$12$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 40 \sr_op__output_cr$13
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \sr_op__output_cr$13$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 41 \sr_op__is_32bit$14
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \sr_op__is_32bit$14$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 output 42 \sr_op__is_signed$15
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \sr_op__is_signed$15$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 output 43 \sr_op__insn$16
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \sr_op__insn$16$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 64 output 44 \o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 64 \o$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 output 45 \o_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 \o_ok$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 4 output 46 \cr_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 4 \cr_a$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 output 47 \cr_a_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 \cr_a_ok$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 2 output 48 \xer_ca$17
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 2 \xer_ca$17$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 output 49 \xer_ca_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 \xer_ca_ok$next
+  cell \p$107 \p
+    connect \p_valid_i \p_valid_i
+    connect \p_ready_o \p_ready_o
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
-  wire width 1 $5
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
-  cell $or $6
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A $3
-    connect \B \s_idx_l
-    connect \Y $5
+  cell \n$108 \n
+    connect \n_valid_o \n_valid_o
+    connect \n_ready_i \n_ready_i
   end
-  process $group_0
-    assign \q_int$next \q_int
-    assign \q_int$next $5
-    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
-      case 1'1
-        assign \q_int$next 1'0
-    end
-    sync init
-      update \q_int 1'0
-    sync posedge \clk
-      update \q_int \q_int$next
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
-  wire width 1 $7
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
-  cell $not $8
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \r_idx_l
-    connect \Y $7
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
-  wire width 1 $9
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
-  cell $and $10
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \q_int
-    connect \B $7
-    connect \Y $9
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
-  wire width 1 $11
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
-  cell $or $12
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A $9
-    connect \B \s_idx_l
-    connect \Y $11
-  end
-  process $group_1
-    assign \q_idx_l 1'0
-    assign \q_idx_l $11
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
-  wire width 1 \qn_idx_l
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
-  wire width 1 $13
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
-  cell $not $14
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \q_idx_l
-    connect \Y $13
-  end
-  process $group_2
-    assign \qn_idx_l 1'0
-    assign \qn_idx_l $13
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62"
-  wire width 1 \qlq_idx_l
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
-  wire width 1 $15
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
-  cell $or $16
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \q_idx_l
-    connect \B \q_int
-    connect \Y $15
-  end
-  process $group_3
-    assign \qlq_idx_l 1'0
-    assign \qlq_idx_l $15
-    sync init
-  end
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.l0.l0.reset_l"
-module \reset_l$107
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
-  wire width 1 input 2 \s_reset
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
-  wire width 1 input 3 \r_reset
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
-  wire width 1 output 4 \q_reset
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
-  wire width 1 \q_int
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
-  wire width 1 \q_int$next
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
-  wire width 1 $1
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
-  cell $not $2
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \r_reset
-    connect \Y $1
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
-  wire width 1 $3
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
-  cell $and $4
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \q_int
-    connect \B $1
-    connect \Y $3
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
-  wire width 1 $5
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
-  cell $or $6
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A $3
-    connect \B \s_reset
-    connect \Y $5
-  end
-  process $group_0
-    assign \q_int$next \q_int
-    assign \q_int$next $5
-    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
-      case 1'1
-        assign \q_int$next 1'0
-    end
-    sync init
-      update \q_int 1'0
-    sync posedge \clk
-      update \q_int \q_int$next
-  end
-  process $group_1
-    assign \q_reset 1'0
-    assign \q_reset \q_int
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
-  wire width 1 \qn_reset
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
-  wire width 1 $7
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
-  cell $not $8
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \q_reset
-    connect \Y $7
-  end
-  process $group_2
-    assign \qn_reset 1'0
-    assign \qn_reset $7
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62"
-  wire width 1 \qlq_reset
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
-  wire width 1 $9
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
-  cell $or $10
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \q_reset
-    connect \B \q_int
-    connect \Y $9
-  end
-  process $group_3
-    assign \qlq_reset 1'0
-    assign \qlq_reset $9
-    sync init
-  end
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.l0.l0.pick"
-module \pick
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75"
-  wire width 1 input 0 \i
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76"
-  wire width 1 output 1 \o
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77"
-  wire width 1 output 2 \n
-  process $group_0
-    assign \o 1'0
-    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82"
-    switch { \i }
-      attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82"
-      case 1'1
-        assign \o 1'0
-    end
-    sync init
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
+  wire width 2 \input_muxid
+  attribute \enum_base_type "MicrOp"
+  attribute \enum_value_0000000 "OP_ILLEGAL"
+  attribute \enum_value_0000001 "OP_NOP"
+  attribute \enum_value_0000010 "OP_ADD"
+  attribute \enum_value_0000011 "OP_ADDPCIS"
+  attribute \enum_value_0000100 "OP_AND"
+  attribute \enum_value_0000101 "OP_ATTN"
+  attribute \enum_value_0000110 "OP_B"
+  attribute \enum_value_0000111 "OP_BC"
+  attribute \enum_value_0001000 "OP_BCREG"
+  attribute \enum_value_0001001 "OP_BPERM"
+  attribute \enum_value_0001010 "OP_CMP"
+  attribute \enum_value_0001011 "OP_CMPB"
+  attribute \enum_value_0001100 "OP_CMPEQB"
+  attribute \enum_value_0001101 "OP_CMPRB"
+  attribute \enum_value_0001110 "OP_CNTZ"
+  attribute \enum_value_0001111 "OP_CRAND"
+  attribute \enum_value_0010000 "OP_CRANDC"
+  attribute \enum_value_0010001 "OP_CREQV"
+  attribute \enum_value_0010010 "OP_CRNAND"
+  attribute \enum_value_0010011 "OP_CRNOR"
+  attribute \enum_value_0010100 "OP_CROR"
+  attribute \enum_value_0010101 "OP_CRORC"
+  attribute \enum_value_0010110 "OP_CRXOR"
+  attribute \enum_value_0010111 "OP_DARN"
+  attribute \enum_value_0011000 "OP_DCBF"
+  attribute \enum_value_0011001 "OP_DCBST"
+  attribute \enum_value_0011010 "OP_DCBT"
+  attribute \enum_value_0011011 "OP_DCBTST"
+  attribute \enum_value_0011100 "OP_DCBZ"
+  attribute \enum_value_0011101 "OP_DIV"
+  attribute \enum_value_0011110 "OP_DIVE"
+  attribute \enum_value_0011111 "OP_EXTS"
+  attribute \enum_value_0100000 "OP_EXTSWSLI"
+  attribute \enum_value_0100001 "OP_ICBI"
+  attribute \enum_value_0100010 "OP_ICBT"
+  attribute \enum_value_0100011 "OP_ISEL"
+  attribute \enum_value_0100100 "OP_ISYNC"
+  attribute \enum_value_0100101 "OP_LOAD"
+  attribute \enum_value_0100110 "OP_STORE"
+  attribute \enum_value_0100111 "OP_MADDHD"
+  attribute \enum_value_0101000 "OP_MADDHDU"
+  attribute \enum_value_0101001 "OP_MADDLD"
+  attribute \enum_value_0101010 "OP_MCRF"
+  attribute \enum_value_0101011 "OP_MCRXR"
+  attribute \enum_value_0101100 "OP_MCRXRX"
+  attribute \enum_value_0101101 "OP_MFCR"
+  attribute \enum_value_0101110 "OP_MFSPR"
+  attribute \enum_value_0101111 "OP_MOD"
+  attribute \enum_value_0110000 "OP_MTCRF"
+  attribute \enum_value_0110001 "OP_MTSPR"
+  attribute \enum_value_0110010 "OP_MUL_L64"
+  attribute \enum_value_0110011 "OP_MUL_H64"
+  attribute \enum_value_0110100 "OP_MUL_H32"
+  attribute \enum_value_0110101 "OP_OR"
+  attribute \enum_value_0110110 "OP_POPCNT"
+  attribute \enum_value_0110111 "OP_PRTY"
+  attribute \enum_value_0111000 "OP_RLC"
+  attribute \enum_value_0111001 "OP_RLCL"
+  attribute \enum_value_0111010 "OP_RLCR"
+  attribute \enum_value_0111011 "OP_SETB"
+  attribute \enum_value_0111100 "OP_SHL"
+  attribute \enum_value_0111101 "OP_SHR"
+  attribute \enum_value_0111110 "OP_SYNC"
+  attribute \enum_value_0111111 "OP_TRAP"
+  attribute \enum_value_1000011 "OP_XOR"
+  attribute \enum_value_1000100 "OP_SIM_CONFIG"
+  attribute \enum_value_1000101 "OP_CROP"
+  attribute \enum_value_1000110 "OP_RFID"
+  attribute \enum_value_1000111 "OP_MFMSR"
+  attribute \enum_value_1001000 "OP_MTMSRD"
+  attribute \enum_value_1001001 "OP_SC"
+  attribute \enum_value_1001010 "OP_MTMSR"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 \input_sr_op__insn_type
+  attribute \enum_base_type "Function"
+  attribute \enum_value_00000000000 "NONE"
+  attribute \enum_value_00000000010 "ALU"
+  attribute \enum_value_00000000100 "LDST"
+  attribute \enum_value_00000001000 "SHIFT_ROT"
+  attribute \enum_value_00000010000 "LOGICAL"
+  attribute \enum_value_00000100000 "BRANCH"
+  attribute \enum_value_00001000000 "CR"
+  attribute \enum_value_00010000000 "TRAP"
+  attribute \enum_value_00100000000 "MUL"
+  attribute \enum_value_01000000000 "DIV"
+  attribute \enum_value_10000000000 "SPR"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 \input_sr_op__fn_unit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 \input_sr_op__imm_data__imm
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \input_sr_op__imm_data__imm_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \input_sr_op__rc__rc
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \input_sr_op__rc__rc_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \input_sr_op__oe__oe
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \input_sr_op__oe__oe_ok
+  attribute \enum_base_type "CryIn"
+  attribute \enum_value_00 "ZERO"
+  attribute \enum_value_01 "ONE"
+  attribute \enum_value_10 "CA"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 2 \input_sr_op__input_carry
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \input_sr_op__output_carry
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \input_sr_op__input_cr
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \input_sr_op__output_cr
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \input_sr_op__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \input_sr_op__is_signed
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \input_sr_op__insn
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
+  wire width 64 \input_ra
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
+  wire width 64 \input_rb
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
+  wire width 64 \input_rc
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
+  wire width 2 \input_xer_ca
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
+  wire width 2 \input_muxid$18
+  attribute \enum_base_type "MicrOp"
+  attribute \enum_value_0000000 "OP_ILLEGAL"
+  attribute \enum_value_0000001 "OP_NOP"
+  attribute \enum_value_0000010 "OP_ADD"
+  attribute \enum_value_0000011 "OP_ADDPCIS"
+  attribute \enum_value_0000100 "OP_AND"
+  attribute \enum_value_0000101 "OP_ATTN"
+  attribute \enum_value_0000110 "OP_B"
+  attribute \enum_value_0000111 "OP_BC"
+  attribute \enum_value_0001000 "OP_BCREG"
+  attribute \enum_value_0001001 "OP_BPERM"
+  attribute \enum_value_0001010 "OP_CMP"
+  attribute \enum_value_0001011 "OP_CMPB"
+  attribute \enum_value_0001100 "OP_CMPEQB"
+  attribute \enum_value_0001101 "OP_CMPRB"
+  attribute \enum_value_0001110 "OP_CNTZ"
+  attribute \enum_value_0001111 "OP_CRAND"
+  attribute \enum_value_0010000 "OP_CRANDC"
+  attribute \enum_value_0010001 "OP_CREQV"
+  attribute \enum_value_0010010 "OP_CRNAND"
+  attribute \enum_value_0010011 "OP_CRNOR"
+  attribute \enum_value_0010100 "OP_CROR"
+  attribute \enum_value_0010101 "OP_CRORC"
+  attribute \enum_value_0010110 "OP_CRXOR"
+  attribute \enum_value_0010111 "OP_DARN"
+  attribute \enum_value_0011000 "OP_DCBF"
+  attribute \enum_value_0011001 "OP_DCBST"
+  attribute \enum_value_0011010 "OP_DCBT"
+  attribute \enum_value_0011011 "OP_DCBTST"
+  attribute \enum_value_0011100 "OP_DCBZ"
+  attribute \enum_value_0011101 "OP_DIV"
+  attribute \enum_value_0011110 "OP_DIVE"
+  attribute \enum_value_0011111 "OP_EXTS"
+  attribute \enum_value_0100000 "OP_EXTSWSLI"
+  attribute \enum_value_0100001 "OP_ICBI"
+  attribute \enum_value_0100010 "OP_ICBT"
+  attribute \enum_value_0100011 "OP_ISEL"
+  attribute \enum_value_0100100 "OP_ISYNC"
+  attribute \enum_value_0100101 "OP_LOAD"
+  attribute \enum_value_0100110 "OP_STORE"
+  attribute \enum_value_0100111 "OP_MADDHD"
+  attribute \enum_value_0101000 "OP_MADDHDU"
+  attribute \enum_value_0101001 "OP_MADDLD"
+  attribute \enum_value_0101010 "OP_MCRF"
+  attribute \enum_value_0101011 "OP_MCRXR"
+  attribute \enum_value_0101100 "OP_MCRXRX"
+  attribute \enum_value_0101101 "OP_MFCR"
+  attribute \enum_value_0101110 "OP_MFSPR"
+  attribute \enum_value_0101111 "OP_MOD"
+  attribute \enum_value_0110000 "OP_MTCRF"
+  attribute \enum_value_0110001 "OP_MTSPR"
+  attribute \enum_value_0110010 "OP_MUL_L64"
+  attribute \enum_value_0110011 "OP_MUL_H64"
+  attribute \enum_value_0110100 "OP_MUL_H32"
+  attribute \enum_value_0110101 "OP_OR"
+  attribute \enum_value_0110110 "OP_POPCNT"
+  attribute \enum_value_0110111 "OP_PRTY"
+  attribute \enum_value_0111000 "OP_RLC"
+  attribute \enum_value_0111001 "OP_RLCL"
+  attribute \enum_value_0111010 "OP_RLCR"
+  attribute \enum_value_0111011 "OP_SETB"
+  attribute \enum_value_0111100 "OP_SHL"
+  attribute \enum_value_0111101 "OP_SHR"
+  attribute \enum_value_0111110 "OP_SYNC"
+  attribute \enum_value_0111111 "OP_TRAP"
+  attribute \enum_value_1000011 "OP_XOR"
+  attribute \enum_value_1000100 "OP_SIM_CONFIG"
+  attribute \enum_value_1000101 "OP_CROP"
+  attribute \enum_value_1000110 "OP_RFID"
+  attribute \enum_value_1000111 "OP_MFMSR"
+  attribute \enum_value_1001000 "OP_MTMSRD"
+  attribute \enum_value_1001001 "OP_SC"
+  attribute \enum_value_1001010 "OP_MTMSR"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 \input_sr_op__insn_type$19
+  attribute \enum_base_type "Function"
+  attribute \enum_value_00000000000 "NONE"
+  attribute \enum_value_00000000010 "ALU"
+  attribute \enum_value_00000000100 "LDST"
+  attribute \enum_value_00000001000 "SHIFT_ROT"
+  attribute \enum_value_00000010000 "LOGICAL"
+  attribute \enum_value_00000100000 "BRANCH"
+  attribute \enum_value_00001000000 "CR"
+  attribute \enum_value_00010000000 "TRAP"
+  attribute \enum_value_00100000000 "MUL"
+  attribute \enum_value_01000000000 "DIV"
+  attribute \enum_value_10000000000 "SPR"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 \input_sr_op__fn_unit$20
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 \input_sr_op__imm_data__imm$21
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \input_sr_op__imm_data__imm_ok$22
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \input_sr_op__rc__rc$23
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \input_sr_op__rc__rc_ok$24
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \input_sr_op__oe__oe$25
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \input_sr_op__oe__oe_ok$26
+  attribute \enum_base_type "CryIn"
+  attribute \enum_value_00 "ZERO"
+  attribute \enum_value_01 "ONE"
+  attribute \enum_value_10 "CA"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 2 \input_sr_op__input_carry$27
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \input_sr_op__output_carry$28
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \input_sr_op__input_cr$29
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \input_sr_op__output_cr$30
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \input_sr_op__is_32bit$31
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \input_sr_op__is_signed$32
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \input_sr_op__insn$33
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
+  wire width 64 \input_ra$34
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
+  wire width 64 \input_rb$35
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
+  wire width 64 \input_rc$36
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
+  wire width 2 \input_xer_ca$37
+  cell \input$109 \input
+    connect \muxid \input_muxid
+    connect \sr_op__insn_type \input_sr_op__insn_type
+    connect \sr_op__fn_unit \input_sr_op__fn_unit
+    connect \sr_op__imm_data__imm \input_sr_op__imm_data__imm
+    connect \sr_op__imm_data__imm_ok \input_sr_op__imm_data__imm_ok
+    connect \sr_op__rc__rc \input_sr_op__rc__rc
+    connect \sr_op__rc__rc_ok \input_sr_op__rc__rc_ok
+    connect \sr_op__oe__oe \input_sr_op__oe__oe
+    connect \sr_op__oe__oe_ok \input_sr_op__oe__oe_ok
+    connect \sr_op__input_carry \input_sr_op__input_carry
+    connect \sr_op__output_carry \input_sr_op__output_carry
+    connect \sr_op__input_cr \input_sr_op__input_cr
+    connect \sr_op__output_cr \input_sr_op__output_cr
+    connect \sr_op__is_32bit \input_sr_op__is_32bit
+    connect \sr_op__is_signed \input_sr_op__is_signed
+    connect \sr_op__insn \input_sr_op__insn
+    connect \ra \input_ra
+    connect \rb \input_rb
+    connect \rc \input_rc
+    connect \xer_ca \input_xer_ca
+    connect \muxid$1 \input_muxid$18
+    connect \sr_op__insn_type$2 \input_sr_op__insn_type$19
+    connect \sr_op__fn_unit$3 \input_sr_op__fn_unit$20
+    connect \sr_op__imm_data__imm$4 \input_sr_op__imm_data__imm$21
+    connect \sr_op__imm_data__imm_ok$5 \input_sr_op__imm_data__imm_ok$22
+    connect \sr_op__rc__rc$6 \input_sr_op__rc__rc$23
+    connect \sr_op__rc__rc_ok$7 \input_sr_op__rc__rc_ok$24
+    connect \sr_op__oe__oe$8 \input_sr_op__oe__oe$25
+    connect \sr_op__oe__oe_ok$9 \input_sr_op__oe__oe_ok$26
+    connect \sr_op__input_carry$10 \input_sr_op__input_carry$27
+    connect \sr_op__output_carry$11 \input_sr_op__output_carry$28
+    connect \sr_op__input_cr$12 \input_sr_op__input_cr$29
+    connect \sr_op__output_cr$13 \input_sr_op__output_cr$30
+    connect \sr_op__is_32bit$14 \input_sr_op__is_32bit$31
+    connect \sr_op__is_signed$15 \input_sr_op__is_signed$32
+    connect \sr_op__insn$16 \input_sr_op__insn$33
+    connect \ra$17 \input_ra$34
+    connect \rb$18 \input_rb$35
+    connect \rc$19 \input_rc$36
+    connect \xer_ca$20 \input_xer_ca$37
   end
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84"
-  wire width 1 $1
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84"
-  cell $eq $2
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \i
-    connect \B 1'0
-    connect \Y $1
-  end
-  process $group_1
-    assign \n 1'0
-    assign \n $1
-    sync init
-  end
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.l0.l0"
-module \l0$106
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:95"
-  wire width 1 input 2 \ldst_port0_is_ld_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:96"
-  wire width 1 input 3 \ldst_port0_is_st_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99"
-  wire width 4 input 4 \ldst_port0_data_len
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 96 input 5 \ldst_port0_addr_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 input 6 \ldst_port0_addr_i_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:107"
-  wire width 1 output 7 \ldst_port0_addr_exc_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:106"
-  wire width 1 output 8 \ldst_port0_addr_ok_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 64 output 9 \ldst_port0_ld_data_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 10 \ldst_port0_ld_data_o_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 64 input 11 \ldst_port0_st_data_i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
+  wire width 2 \main_muxid
+  attribute \enum_base_type "MicrOp"
+  attribute \enum_value_0000000 "OP_ILLEGAL"
+  attribute \enum_value_0000001 "OP_NOP"
+  attribute \enum_value_0000010 "OP_ADD"
+  attribute \enum_value_0000011 "OP_ADDPCIS"
+  attribute \enum_value_0000100 "OP_AND"
+  attribute \enum_value_0000101 "OP_ATTN"
+  attribute \enum_value_0000110 "OP_B"
+  attribute \enum_value_0000111 "OP_BC"
+  attribute \enum_value_0001000 "OP_BCREG"
+  attribute \enum_value_0001001 "OP_BPERM"
+  attribute \enum_value_0001010 "OP_CMP"
+  attribute \enum_value_0001011 "OP_CMPB"
+  attribute \enum_value_0001100 "OP_CMPEQB"
+  attribute \enum_value_0001101 "OP_CMPRB"
+  attribute \enum_value_0001110 "OP_CNTZ"
+  attribute \enum_value_0001111 "OP_CRAND"
+  attribute \enum_value_0010000 "OP_CRANDC"
+  attribute \enum_value_0010001 "OP_CREQV"
+  attribute \enum_value_0010010 "OP_CRNAND"
+  attribute \enum_value_0010011 "OP_CRNOR"
+  attribute \enum_value_0010100 "OP_CROR"
+  attribute \enum_value_0010101 "OP_CRORC"
+  attribute \enum_value_0010110 "OP_CRXOR"
+  attribute \enum_value_0010111 "OP_DARN"
+  attribute \enum_value_0011000 "OP_DCBF"
+  attribute \enum_value_0011001 "OP_DCBST"
+  attribute \enum_value_0011010 "OP_DCBT"
+  attribute \enum_value_0011011 "OP_DCBTST"
+  attribute \enum_value_0011100 "OP_DCBZ"
+  attribute \enum_value_0011101 "OP_DIV"
+  attribute \enum_value_0011110 "OP_DIVE"
+  attribute \enum_value_0011111 "OP_EXTS"
+  attribute \enum_value_0100000 "OP_EXTSWSLI"
+  attribute \enum_value_0100001 "OP_ICBI"
+  attribute \enum_value_0100010 "OP_ICBT"
+  attribute \enum_value_0100011 "OP_ISEL"
+  attribute \enum_value_0100100 "OP_ISYNC"
+  attribute \enum_value_0100101 "OP_LOAD"
+  attribute \enum_value_0100110 "OP_STORE"
+  attribute \enum_value_0100111 "OP_MADDHD"
+  attribute \enum_value_0101000 "OP_MADDHDU"
+  attribute \enum_value_0101001 "OP_MADDLD"
+  attribute \enum_value_0101010 "OP_MCRF"
+  attribute \enum_value_0101011 "OP_MCRXR"
+  attribute \enum_value_0101100 "OP_MCRXRX"
+  attribute \enum_value_0101101 "OP_MFCR"
+  attribute \enum_value_0101110 "OP_MFSPR"
+  attribute \enum_value_0101111 "OP_MOD"
+  attribute \enum_value_0110000 "OP_MTCRF"
+  attribute \enum_value_0110001 "OP_MTSPR"
+  attribute \enum_value_0110010 "OP_MUL_L64"
+  attribute \enum_value_0110011 "OP_MUL_H64"
+  attribute \enum_value_0110100 "OP_MUL_H32"
+  attribute \enum_value_0110101 "OP_OR"
+  attribute \enum_value_0110110 "OP_POPCNT"
+  attribute \enum_value_0110111 "OP_PRTY"
+  attribute \enum_value_0111000 "OP_RLC"
+  attribute \enum_value_0111001 "OP_RLCL"
+  attribute \enum_value_0111010 "OP_RLCR"
+  attribute \enum_value_0111011 "OP_SETB"
+  attribute \enum_value_0111100 "OP_SHL"
+  attribute \enum_value_0111101 "OP_SHR"
+  attribute \enum_value_0111110 "OP_SYNC"
+  attribute \enum_value_0111111 "OP_TRAP"
+  attribute \enum_value_1000011 "OP_XOR"
+  attribute \enum_value_1000100 "OP_SIM_CONFIG"
+  attribute \enum_value_1000101 "OP_CROP"
+  attribute \enum_value_1000110 "OP_RFID"
+  attribute \enum_value_1000111 "OP_MFMSR"
+  attribute \enum_value_1001000 "OP_MTMSRD"
+  attribute \enum_value_1001001 "OP_SC"
+  attribute \enum_value_1001010 "OP_MTMSR"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 \main_sr_op__insn_type
+  attribute \enum_base_type "Function"
+  attribute \enum_value_00000000000 "NONE"
+  attribute \enum_value_00000000010 "ALU"
+  attribute \enum_value_00000000100 "LDST"
+  attribute \enum_value_00000001000 "SHIFT_ROT"
+  attribute \enum_value_00000010000 "LOGICAL"
+  attribute \enum_value_00000100000 "BRANCH"
+  attribute \enum_value_00001000000 "CR"
+  attribute \enum_value_00010000000 "TRAP"
+  attribute \enum_value_00100000000 "MUL"
+  attribute \enum_value_01000000000 "DIV"
+  attribute \enum_value_10000000000 "SPR"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 \main_sr_op__fn_unit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 \main_sr_op__imm_data__imm
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \main_sr_op__imm_data__imm_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \main_sr_op__rc__rc
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \main_sr_op__rc__rc_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \main_sr_op__oe__oe
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \main_sr_op__oe__oe_ok
+  attribute \enum_base_type "CryIn"
+  attribute \enum_value_00 "ZERO"
+  attribute \enum_value_01 "ONE"
+  attribute \enum_value_10 "CA"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 2 \main_sr_op__input_carry
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \main_sr_op__output_carry
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \main_sr_op__input_cr
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \main_sr_op__output_cr
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \main_sr_op__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \main_sr_op__is_signed
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \main_sr_op__insn
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
+  wire width 64 \main_ra
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
+  wire width 64 \main_rb
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
+  wire width 64 \main_rc
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
+  wire width 2 \main_muxid$38
+  attribute \enum_base_type "MicrOp"
+  attribute \enum_value_0000000 "OP_ILLEGAL"
+  attribute \enum_value_0000001 "OP_NOP"
+  attribute \enum_value_0000010 "OP_ADD"
+  attribute \enum_value_0000011 "OP_ADDPCIS"
+  attribute \enum_value_0000100 "OP_AND"
+  attribute \enum_value_0000101 "OP_ATTN"
+  attribute \enum_value_0000110 "OP_B"
+  attribute \enum_value_0000111 "OP_BC"
+  attribute \enum_value_0001000 "OP_BCREG"
+  attribute \enum_value_0001001 "OP_BPERM"
+  attribute \enum_value_0001010 "OP_CMP"
+  attribute \enum_value_0001011 "OP_CMPB"
+  attribute \enum_value_0001100 "OP_CMPEQB"
+  attribute \enum_value_0001101 "OP_CMPRB"
+  attribute \enum_value_0001110 "OP_CNTZ"
+  attribute \enum_value_0001111 "OP_CRAND"
+  attribute \enum_value_0010000 "OP_CRANDC"
+  attribute \enum_value_0010001 "OP_CREQV"
+  attribute \enum_value_0010010 "OP_CRNAND"
+  attribute \enum_value_0010011 "OP_CRNOR"
+  attribute \enum_value_0010100 "OP_CROR"
+  attribute \enum_value_0010101 "OP_CRORC"
+  attribute \enum_value_0010110 "OP_CRXOR"
+  attribute \enum_value_0010111 "OP_DARN"
+  attribute \enum_value_0011000 "OP_DCBF"
+  attribute \enum_value_0011001 "OP_DCBST"
+  attribute \enum_value_0011010 "OP_DCBT"
+  attribute \enum_value_0011011 "OP_DCBTST"
+  attribute \enum_value_0011100 "OP_DCBZ"
+  attribute \enum_value_0011101 "OP_DIV"
+  attribute \enum_value_0011110 "OP_DIVE"
+  attribute \enum_value_0011111 "OP_EXTS"
+  attribute \enum_value_0100000 "OP_EXTSWSLI"
+  attribute \enum_value_0100001 "OP_ICBI"
+  attribute \enum_value_0100010 "OP_ICBT"
+  attribute \enum_value_0100011 "OP_ISEL"
+  attribute \enum_value_0100100 "OP_ISYNC"
+  attribute \enum_value_0100101 "OP_LOAD"
+  attribute \enum_value_0100110 "OP_STORE"
+  attribute \enum_value_0100111 "OP_MADDHD"
+  attribute \enum_value_0101000 "OP_MADDHDU"
+  attribute \enum_value_0101001 "OP_MADDLD"
+  attribute \enum_value_0101010 "OP_MCRF"
+  attribute \enum_value_0101011 "OP_MCRXR"
+  attribute \enum_value_0101100 "OP_MCRXRX"
+  attribute \enum_value_0101101 "OP_MFCR"
+  attribute \enum_value_0101110 "OP_MFSPR"
+  attribute \enum_value_0101111 "OP_MOD"
+  attribute \enum_value_0110000 "OP_MTCRF"
+  attribute \enum_value_0110001 "OP_MTSPR"
+  attribute \enum_value_0110010 "OP_MUL_L64"
+  attribute \enum_value_0110011 "OP_MUL_H64"
+  attribute \enum_value_0110100 "OP_MUL_H32"
+  attribute \enum_value_0110101 "OP_OR"
+  attribute \enum_value_0110110 "OP_POPCNT"
+  attribute \enum_value_0110111 "OP_PRTY"
+  attribute \enum_value_0111000 "OP_RLC"
+  attribute \enum_value_0111001 "OP_RLCL"
+  attribute \enum_value_0111010 "OP_RLCR"
+  attribute \enum_value_0111011 "OP_SETB"
+  attribute \enum_value_0111100 "OP_SHL"
+  attribute \enum_value_0111101 "OP_SHR"
+  attribute \enum_value_0111110 "OP_SYNC"
+  attribute \enum_value_0111111 "OP_TRAP"
+  attribute \enum_value_1000011 "OP_XOR"
+  attribute \enum_value_1000100 "OP_SIM_CONFIG"
+  attribute \enum_value_1000101 "OP_CROP"
+  attribute \enum_value_1000110 "OP_RFID"
+  attribute \enum_value_1000111 "OP_MFMSR"
+  attribute \enum_value_1001000 "OP_MTMSRD"
+  attribute \enum_value_1001001 "OP_SC"
+  attribute \enum_value_1001010 "OP_MTMSR"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 \main_sr_op__insn_type$39
+  attribute \enum_base_type "Function"
+  attribute \enum_value_00000000000 "NONE"
+  attribute \enum_value_00000000010 "ALU"
+  attribute \enum_value_00000000100 "LDST"
+  attribute \enum_value_00000001000 "SHIFT_ROT"
+  attribute \enum_value_00000010000 "LOGICAL"
+  attribute \enum_value_00000100000 "BRANCH"
+  attribute \enum_value_00001000000 "CR"
+  attribute \enum_value_00010000000 "TRAP"
+  attribute \enum_value_00100000000 "MUL"
+  attribute \enum_value_01000000000 "DIV"
+  attribute \enum_value_10000000000 "SPR"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 \main_sr_op__fn_unit$40
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 \main_sr_op__imm_data__imm$41
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \main_sr_op__imm_data__imm_ok$42
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \main_sr_op__rc__rc$43
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \main_sr_op__rc__rc_ok$44
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \main_sr_op__oe__oe$45
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \main_sr_op__oe__oe_ok$46
+  attribute \enum_base_type "CryIn"
+  attribute \enum_value_00 "ZERO"
+  attribute \enum_value_01 "ONE"
+  attribute \enum_value_10 "CA"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 2 \main_sr_op__input_carry$47
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \main_sr_op__output_carry$48
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \main_sr_op__input_cr$49
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \main_sr_op__output_cr$50
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \main_sr_op__is_32bit$51
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \main_sr_op__is_signed$52
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \main_sr_op__insn$53
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 input 12 \ldst_port0_st_data_i_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:95"
-  wire width 1 output 13 \ldst_port0_is_ld_i$1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102"
-  wire width 1 input 14 \ldst_port0_busy_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:96"
-  wire width 1 output 15 \ldst_port0_is_st_i$2
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99"
-  wire width 4 output 16 \ldst_port0_data_len$3
+  wire width 64 \main_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 48 output 17 \ldst_port0_addr_i$4
+  wire width 1 \main_o_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 18 \ldst_port0_addr_i_ok$5
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:106"
-  wire width 1 input 19 \ldst_port0_addr_ok_o$6
+  wire width 2 \main_xer_ca
+  cell \main$110 \main
+    connect \muxid \main_muxid
+    connect \sr_op__insn_type \main_sr_op__insn_type
+    connect \sr_op__fn_unit \main_sr_op__fn_unit
+    connect \sr_op__imm_data__imm \main_sr_op__imm_data__imm
+    connect \sr_op__imm_data__imm_ok \main_sr_op__imm_data__imm_ok
+    connect \sr_op__rc__rc \main_sr_op__rc__rc
+    connect \sr_op__rc__rc_ok \main_sr_op__rc__rc_ok
+    connect \sr_op__oe__oe \main_sr_op__oe__oe
+    connect \sr_op__oe__oe_ok \main_sr_op__oe__oe_ok
+    connect \sr_op__input_carry \main_sr_op__input_carry
+    connect \sr_op__output_carry \main_sr_op__output_carry
+    connect \sr_op__input_cr \main_sr_op__input_cr
+    connect \sr_op__output_cr \main_sr_op__output_cr
+    connect \sr_op__is_32bit \main_sr_op__is_32bit
+    connect \sr_op__is_signed \main_sr_op__is_signed
+    connect \sr_op__insn \main_sr_op__insn
+    connect \ra \main_ra
+    connect \rb \main_rb
+    connect \rc \main_rc
+    connect \muxid$1 \main_muxid$38
+    connect \sr_op__insn_type$2 \main_sr_op__insn_type$39
+    connect \sr_op__fn_unit$3 \main_sr_op__fn_unit$40
+    connect \sr_op__imm_data__imm$4 \main_sr_op__imm_data__imm$41
+    connect \sr_op__imm_data__imm_ok$5 \main_sr_op__imm_data__imm_ok$42
+    connect \sr_op__rc__rc$6 \main_sr_op__rc__rc$43
+    connect \sr_op__rc__rc_ok$7 \main_sr_op__rc__rc_ok$44
+    connect \sr_op__oe__oe$8 \main_sr_op__oe__oe$45
+    connect \sr_op__oe__oe_ok$9 \main_sr_op__oe__oe_ok$46
+    connect \sr_op__input_carry$10 \main_sr_op__input_carry$47
+    connect \sr_op__output_carry$11 \main_sr_op__output_carry$48
+    connect \sr_op__input_cr$12 \main_sr_op__input_cr$49
+    connect \sr_op__output_cr$13 \main_sr_op__output_cr$50
+    connect \sr_op__is_32bit$14 \main_sr_op__is_32bit$51
+    connect \sr_op__is_signed$15 \main_sr_op__is_signed$52
+    connect \sr_op__insn$16 \main_sr_op__insn$53
+    connect \o \main_o
+    connect \o_ok \main_o_ok
+    connect \xer_ca \main_xer_ca
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
+  wire width 2 \output_muxid
+  attribute \enum_base_type "MicrOp"
+  attribute \enum_value_0000000 "OP_ILLEGAL"
+  attribute \enum_value_0000001 "OP_NOP"
+  attribute \enum_value_0000010 "OP_ADD"
+  attribute \enum_value_0000011 "OP_ADDPCIS"
+  attribute \enum_value_0000100 "OP_AND"
+  attribute \enum_value_0000101 "OP_ATTN"
+  attribute \enum_value_0000110 "OP_B"
+  attribute \enum_value_0000111 "OP_BC"
+  attribute \enum_value_0001000 "OP_BCREG"
+  attribute \enum_value_0001001 "OP_BPERM"
+  attribute \enum_value_0001010 "OP_CMP"
+  attribute \enum_value_0001011 "OP_CMPB"
+  attribute \enum_value_0001100 "OP_CMPEQB"
+  attribute \enum_value_0001101 "OP_CMPRB"
+  attribute \enum_value_0001110 "OP_CNTZ"
+  attribute \enum_value_0001111 "OP_CRAND"
+  attribute \enum_value_0010000 "OP_CRANDC"
+  attribute \enum_value_0010001 "OP_CREQV"
+  attribute \enum_value_0010010 "OP_CRNAND"
+  attribute \enum_value_0010011 "OP_CRNOR"
+  attribute \enum_value_0010100 "OP_CROR"
+  attribute \enum_value_0010101 "OP_CRORC"
+  attribute \enum_value_0010110 "OP_CRXOR"
+  attribute \enum_value_0010111 "OP_DARN"
+  attribute \enum_value_0011000 "OP_DCBF"
+  attribute \enum_value_0011001 "OP_DCBST"
+  attribute \enum_value_0011010 "OP_DCBT"
+  attribute \enum_value_0011011 "OP_DCBTST"
+  attribute \enum_value_0011100 "OP_DCBZ"
+  attribute \enum_value_0011101 "OP_DIV"
+  attribute \enum_value_0011110 "OP_DIVE"
+  attribute \enum_value_0011111 "OP_EXTS"
+  attribute \enum_value_0100000 "OP_EXTSWSLI"
+  attribute \enum_value_0100001 "OP_ICBI"
+  attribute \enum_value_0100010 "OP_ICBT"
+  attribute \enum_value_0100011 "OP_ISEL"
+  attribute \enum_value_0100100 "OP_ISYNC"
+  attribute \enum_value_0100101 "OP_LOAD"
+  attribute \enum_value_0100110 "OP_STORE"
+  attribute \enum_value_0100111 "OP_MADDHD"
+  attribute \enum_value_0101000 "OP_MADDHDU"
+  attribute \enum_value_0101001 "OP_MADDLD"
+  attribute \enum_value_0101010 "OP_MCRF"
+  attribute \enum_value_0101011 "OP_MCRXR"
+  attribute \enum_value_0101100 "OP_MCRXRX"
+  attribute \enum_value_0101101 "OP_MFCR"
+  attribute \enum_value_0101110 "OP_MFSPR"
+  attribute \enum_value_0101111 "OP_MOD"
+  attribute \enum_value_0110000 "OP_MTCRF"
+  attribute \enum_value_0110001 "OP_MTSPR"
+  attribute \enum_value_0110010 "OP_MUL_L64"
+  attribute \enum_value_0110011 "OP_MUL_H64"
+  attribute \enum_value_0110100 "OP_MUL_H32"
+  attribute \enum_value_0110101 "OP_OR"
+  attribute \enum_value_0110110 "OP_POPCNT"
+  attribute \enum_value_0110111 "OP_PRTY"
+  attribute \enum_value_0111000 "OP_RLC"
+  attribute \enum_value_0111001 "OP_RLCL"
+  attribute \enum_value_0111010 "OP_RLCR"
+  attribute \enum_value_0111011 "OP_SETB"
+  attribute \enum_value_0111100 "OP_SHL"
+  attribute \enum_value_0111101 "OP_SHR"
+  attribute \enum_value_0111110 "OP_SYNC"
+  attribute \enum_value_0111111 "OP_TRAP"
+  attribute \enum_value_1000011 "OP_XOR"
+  attribute \enum_value_1000100 "OP_SIM_CONFIG"
+  attribute \enum_value_1000101 "OP_CROP"
+  attribute \enum_value_1000110 "OP_RFID"
+  attribute \enum_value_1000111 "OP_MFMSR"
+  attribute \enum_value_1001000 "OP_MTMSRD"
+  attribute \enum_value_1001001 "OP_SC"
+  attribute \enum_value_1001010 "OP_MTMSR"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 \output_sr_op__insn_type
+  attribute \enum_base_type "Function"
+  attribute \enum_value_00000000000 "NONE"
+  attribute \enum_value_00000000010 "ALU"
+  attribute \enum_value_00000000100 "LDST"
+  attribute \enum_value_00000001000 "SHIFT_ROT"
+  attribute \enum_value_00000010000 "LOGICAL"
+  attribute \enum_value_00000100000 "BRANCH"
+  attribute \enum_value_00001000000 "CR"
+  attribute \enum_value_00010000000 "TRAP"
+  attribute \enum_value_00100000000 "MUL"
+  attribute \enum_value_01000000000 "DIV"
+  attribute \enum_value_10000000000 "SPR"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 \output_sr_op__fn_unit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 \output_sr_op__imm_data__imm
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_sr_op__imm_data__imm_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_sr_op__rc__rc
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_sr_op__rc__rc_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_sr_op__oe__oe
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_sr_op__oe__oe_ok
+  attribute \enum_base_type "CryIn"
+  attribute \enum_value_00 "ZERO"
+  attribute \enum_value_01 "ONE"
+  attribute \enum_value_10 "CA"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 2 \output_sr_op__input_carry
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_sr_op__output_carry
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_sr_op__input_cr
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_sr_op__output_cr
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_sr_op__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_sr_op__is_signed
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \output_sr_op__insn
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 64 input 20 \ldst_port0_ld_data_o$7
+  wire width 64 \output_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 input 21 \ldst_port0_ld_data_o_ok$8
+  wire width 1 \output_o_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 22 \ldst_port0_st_data_i_ok$9
+  wire width 4 \output_cr_a
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 64 output 23 \ldst_port0_st_data_i$10
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:107"
-  wire width 1 input 24 \ldst_port0_addr_exc_o$11
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
-  wire width 1 \idx_l_q_idx_l
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
-  wire width 1 \idx_l_s_idx_l
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
-  wire width 1 \idx_l_r_idx_l
-  cell \idx_l \idx_l
-    connect \rst \rst
-    connect \clk \clk
-    connect \q_idx_l \idx_l_q_idx_l
-    connect \s_idx_l \idx_l_s_idx_l
-    connect \r_idx_l \idx_l_r_idx_l
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
-  wire width 1 \reset_l_s_reset
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
-  wire width 1 \reset_l_r_reset
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
-  wire width 1 \reset_l_q_reset
-  cell \reset_l$107 \reset_l
-    connect \rst \rst
-    connect \clk \clk
-    connect \s_reset \reset_l_s_reset
-    connect \r_reset \reset_l_r_reset
-    connect \q_reset \reset_l_q_reset
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75"
-  wire width 1 \pick_i
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76"
-  wire width 1 \pick_o
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77"
-  wire width 1 \pick_n
-  cell \pick \pick
-    connect \i \pick_i
-    connect \o \pick_o
-    connect \n \pick_n
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:222"
-  wire width 1 $12
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:222"
-  cell $or $13
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \ldst_port0_is_ld_i
-    connect \B \ldst_port0_is_st_i
-    connect \Y $12
-  end
-  process $group_0
-    assign \pick_i 1'0
-    assign \pick_i { $12 }
-    sync init
+  wire width 2 \output_xer_ca
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
+  wire width 2 \output_muxid$54
+  attribute \enum_base_type "MicrOp"
+  attribute \enum_value_0000000 "OP_ILLEGAL"
+  attribute \enum_value_0000001 "OP_NOP"
+  attribute \enum_value_0000010 "OP_ADD"
+  attribute \enum_value_0000011 "OP_ADDPCIS"
+  attribute \enum_value_0000100 "OP_AND"
+  attribute \enum_value_0000101 "OP_ATTN"
+  attribute \enum_value_0000110 "OP_B"
+  attribute \enum_value_0000111 "OP_BC"
+  attribute \enum_value_0001000 "OP_BCREG"
+  attribute \enum_value_0001001 "OP_BPERM"
+  attribute \enum_value_0001010 "OP_CMP"
+  attribute \enum_value_0001011 "OP_CMPB"
+  attribute \enum_value_0001100 "OP_CMPEQB"
+  attribute \enum_value_0001101 "OP_CMPRB"
+  attribute \enum_value_0001110 "OP_CNTZ"
+  attribute \enum_value_0001111 "OP_CRAND"
+  attribute \enum_value_0010000 "OP_CRANDC"
+  attribute \enum_value_0010001 "OP_CREQV"
+  attribute \enum_value_0010010 "OP_CRNAND"
+  attribute \enum_value_0010011 "OP_CRNOR"
+  attribute \enum_value_0010100 "OP_CROR"
+  attribute \enum_value_0010101 "OP_CRORC"
+  attribute \enum_value_0010110 "OP_CRXOR"
+  attribute \enum_value_0010111 "OP_DARN"
+  attribute \enum_value_0011000 "OP_DCBF"
+  attribute \enum_value_0011001 "OP_DCBST"
+  attribute \enum_value_0011010 "OP_DCBT"
+  attribute \enum_value_0011011 "OP_DCBTST"
+  attribute \enum_value_0011100 "OP_DCBZ"
+  attribute \enum_value_0011101 "OP_DIV"
+  attribute \enum_value_0011110 "OP_DIVE"
+  attribute \enum_value_0011111 "OP_EXTS"
+  attribute \enum_value_0100000 "OP_EXTSWSLI"
+  attribute \enum_value_0100001 "OP_ICBI"
+  attribute \enum_value_0100010 "OP_ICBT"
+  attribute \enum_value_0100011 "OP_ISEL"
+  attribute \enum_value_0100100 "OP_ISYNC"
+  attribute \enum_value_0100101 "OP_LOAD"
+  attribute \enum_value_0100110 "OP_STORE"
+  attribute \enum_value_0100111 "OP_MADDHD"
+  attribute \enum_value_0101000 "OP_MADDHDU"
+  attribute \enum_value_0101001 "OP_MADDLD"
+  attribute \enum_value_0101010 "OP_MCRF"
+  attribute \enum_value_0101011 "OP_MCRXR"
+  attribute \enum_value_0101100 "OP_MCRXRX"
+  attribute \enum_value_0101101 "OP_MFCR"
+  attribute \enum_value_0101110 "OP_MFSPR"
+  attribute \enum_value_0101111 "OP_MOD"
+  attribute \enum_value_0110000 "OP_MTCRF"
+  attribute \enum_value_0110001 "OP_MTSPR"
+  attribute \enum_value_0110010 "OP_MUL_L64"
+  attribute \enum_value_0110011 "OP_MUL_H64"
+  attribute \enum_value_0110100 "OP_MUL_H32"
+  attribute \enum_value_0110101 "OP_OR"
+  attribute \enum_value_0110110 "OP_POPCNT"
+  attribute \enum_value_0110111 "OP_PRTY"
+  attribute \enum_value_0111000 "OP_RLC"
+  attribute \enum_value_0111001 "OP_RLCL"
+  attribute \enum_value_0111010 "OP_RLCR"
+  attribute \enum_value_0111011 "OP_SETB"
+  attribute \enum_value_0111100 "OP_SHL"
+  attribute \enum_value_0111101 "OP_SHR"
+  attribute \enum_value_0111110 "OP_SYNC"
+  attribute \enum_value_0111111 "OP_TRAP"
+  attribute \enum_value_1000011 "OP_XOR"
+  attribute \enum_value_1000100 "OP_SIM_CONFIG"
+  attribute \enum_value_1000101 "OP_CROP"
+  attribute \enum_value_1000110 "OP_RFID"
+  attribute \enum_value_1000111 "OP_MFMSR"
+  attribute \enum_value_1001000 "OP_MTMSRD"
+  attribute \enum_value_1001001 "OP_SC"
+  attribute \enum_value_1001010 "OP_MTMSR"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 \output_sr_op__insn_type$55
+  attribute \enum_base_type "Function"
+  attribute \enum_value_00000000000 "NONE"
+  attribute \enum_value_00000000010 "ALU"
+  attribute \enum_value_00000000100 "LDST"
+  attribute \enum_value_00000001000 "SHIFT_ROT"
+  attribute \enum_value_00000010000 "LOGICAL"
+  attribute \enum_value_00000100000 "BRANCH"
+  attribute \enum_value_00001000000 "CR"
+  attribute \enum_value_00010000000 "TRAP"
+  attribute \enum_value_00100000000 "MUL"
+  attribute \enum_value_01000000000 "DIV"
+  attribute \enum_value_10000000000 "SPR"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 \output_sr_op__fn_unit$56
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 \output_sr_op__imm_data__imm$57
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_sr_op__imm_data__imm_ok$58
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_sr_op__rc__rc$59
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_sr_op__rc__rc_ok$60
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_sr_op__oe__oe$61
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_sr_op__oe__oe_ok$62
+  attribute \enum_base_type "CryIn"
+  attribute \enum_value_00 "ZERO"
+  attribute \enum_value_01 "ONE"
+  attribute \enum_value_10 "CA"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 2 \output_sr_op__input_carry$63
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_sr_op__output_carry$64
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_sr_op__input_cr$65
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_sr_op__output_cr$66
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_sr_op__is_32bit$67
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \output_sr_op__is_signed$68
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \output_sr_op__insn$69
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 64 \output_o$70
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 \output_o_ok$71
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 4 \output_cr_a$72
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 \output_cr_a_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 2 \output_xer_ca$73
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 \output_xer_ca_ok
+  cell \output$111 \output
+    connect \muxid \output_muxid
+    connect \sr_op__insn_type \output_sr_op__insn_type
+    connect \sr_op__fn_unit \output_sr_op__fn_unit
+    connect \sr_op__imm_data__imm \output_sr_op__imm_data__imm
+    connect \sr_op__imm_data__imm_ok \output_sr_op__imm_data__imm_ok
+    connect \sr_op__rc__rc \output_sr_op__rc__rc
+    connect \sr_op__rc__rc_ok \output_sr_op__rc__rc_ok
+    connect \sr_op__oe__oe \output_sr_op__oe__oe
+    connect \sr_op__oe__oe_ok \output_sr_op__oe__oe_ok
+    connect \sr_op__input_carry \output_sr_op__input_carry
+    connect \sr_op__output_carry \output_sr_op__output_carry
+    connect \sr_op__input_cr \output_sr_op__input_cr
+    connect \sr_op__output_cr \output_sr_op__output_cr
+    connect \sr_op__is_32bit \output_sr_op__is_32bit
+    connect \sr_op__is_signed \output_sr_op__is_signed
+    connect \sr_op__insn \output_sr_op__insn
+    connect \o \output_o
+    connect \o_ok \output_o_ok
+    connect \cr_a \output_cr_a
+    connect \xer_ca \output_xer_ca
+    connect \muxid$1 \output_muxid$54
+    connect \sr_op__insn_type$2 \output_sr_op__insn_type$55
+    connect \sr_op__fn_unit$3 \output_sr_op__fn_unit$56
+    connect \sr_op__imm_data__imm$4 \output_sr_op__imm_data__imm$57
+    connect \sr_op__imm_data__imm_ok$5 \output_sr_op__imm_data__imm_ok$58
+    connect \sr_op__rc__rc$6 \output_sr_op__rc__rc$59
+    connect \sr_op__rc__rc_ok$7 \output_sr_op__rc__rc_ok$60
+    connect \sr_op__oe__oe$8 \output_sr_op__oe__oe$61
+    connect \sr_op__oe__oe_ok$9 \output_sr_op__oe__oe_ok$62
+    connect \sr_op__input_carry$10 \output_sr_op__input_carry$63
+    connect \sr_op__output_carry$11 \output_sr_op__output_carry$64
+    connect \sr_op__input_cr$12 \output_sr_op__input_cr$65
+    connect \sr_op__output_cr$13 \output_sr_op__output_cr$66
+    connect \sr_op__is_32bit$14 \output_sr_op__is_32bit$67
+    connect \sr_op__is_signed$15 \output_sr_op__is_signed$68
+    connect \sr_op__insn$16 \output_sr_op__insn$69
+    connect \o$17 \output_o$70
+    connect \o_ok$18 \output_o_ok$71
+    connect \cr_a$19 \output_cr_a$72
+    connect \cr_a_ok \output_cr_a_ok
+    connect \xer_ca$20 \output_xer_ca$73
+    connect \xer_ca_ok \output_xer_ca_ok
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
-  wire width 1 $14
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
-  wire width 1 \idx_l$15
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
-  wire width 1 \idx_l$15$next
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
-  wire width 1 $16
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
-  cell $mux $17
-    parameter \WIDTH 1
-    connect \A \idx_l$15
-    connect \B \pick_o
-    connect \S \idx_l_q_idx_l
-    connect \Y $16
+  process $group_0
+    assign \input_muxid 2'00
+    assign \input_muxid \muxid
+    sync init
   end
-  connect $14 $16
   process $group_1
+    assign \input_sr_op__insn_type 7'0000000
+    assign \input_sr_op__fn_unit 11'00000000000
+    assign \input_sr_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \input_sr_op__imm_data__imm_ok 1'0
+    assign \input_sr_op__rc__rc 1'0
+    assign \input_sr_op__rc__rc_ok 1'0
+    assign \input_sr_op__oe__oe 1'0
+    assign \input_sr_op__oe__oe_ok 1'0
     assign { } 0'0
-    assign { } {}
+    assign \input_sr_op__input_carry 2'00
+    assign \input_sr_op__output_carry 1'0
+    assign \input_sr_op__input_cr 1'0
+    assign \input_sr_op__output_cr 1'0
+    assign \input_sr_op__is_32bit 1'0
+    assign \input_sr_op__is_signed 1'0
+    assign \input_sr_op__insn 32'00000000000000000000000000000000
+    assign { \input_sr_op__insn \input_sr_op__is_signed \input_sr_op__is_32bit \input_sr_op__output_cr \input_sr_op__input_cr \input_sr_op__output_carry \input_sr_op__input_carry { } { \input_sr_op__oe__oe_ok \input_sr_op__oe__oe } { \input_sr_op__rc__rc_ok \input_sr_op__rc__rc } { \input_sr_op__imm_data__imm_ok \input_sr_op__imm_data__imm } \input_sr_op__fn_unit \input_sr_op__insn_type } { \sr_op__insn \sr_op__is_signed \sr_op__is_32bit \sr_op__output_cr \sr_op__input_cr \sr_op__output_carry \sr_op__input_carry { } { \sr_op__oe__oe_ok \sr_op__oe__oe } { \sr_op__rc__rc_ok \sr_op__rc__rc } { \sr_op__imm_data__imm_ok \sr_op__imm_data__imm } \sr_op__fn_unit \sr_op__insn_type }
     sync init
   end
-  process $group_2
-    assign \idx_l$15$next \idx_l$15
-    attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
-    switch { \idx_l_q_idx_l }
-      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
-      case 1'1
-        assign \idx_l$15$next \pick_o
-    end
-    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
-      case 1'1
-        assign \idx_l$15$next 1'0
-    end
+  process $group_17
+    assign \input_ra 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \input_ra \ra
     sync init
-      update \idx_l$15 1'0
-    sync posedge \clk
-      update \idx_l$15 \idx_l$15$next
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:238"
-  wire width 1 $18
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:238"
-  cell $not $19
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \pick_n
-    connect \Y $18
   end
-  process $group_3
-    assign \idx_l_s_idx_l 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:238"
-    switch { $18 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:238"
-      case 1'1
-        assign \idx_l_s_idx_l 1'1
-    end
+  process $group_18
+    assign \input_rb 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \input_rb \rb
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:248"
-  wire width 1 $20
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:248"
-  cell $not $21
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \ldst_port0_busy_o
-    connect \Y $20
-  end
-  process $group_4
-    assign \reset_l_s_reset 1'0
-    assign \reset_l_s_reset 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:246"
-    switch { \idx_l_q_idx_l }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:246"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:248"
-        switch { $20 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:248"
-          case 1'1
-            assign \reset_l_s_reset 1'1
-        end
-    end
+  process $group_19
+    assign \input_rc 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \input_rc \rc
     sync init
   end
-  process $group_5
-    assign \reset_l_r_reset 1'1
-    assign \reset_l_r_reset 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:256"
-    switch { \reset_l_q_reset }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:256"
-      case 1'1
-        assign \reset_l_r_reset 1'1
-    end
+  process $group_20
+    assign \input_xer_ca 2'00
+    assign \input_xer_ca \xer_ca
     sync init
   end
-  process $group_6
-    assign \ldst_port0_is_ld_i$1 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:246"
-    switch { \idx_l_q_idx_l }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:246"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:115"
-        switch { }
-          case 0'
-            assign \ldst_port0_is_ld_i$1 \ldst_port0_is_ld_i
-        end
-    end
+  process $group_21
+    assign \main_muxid 2'00
+    assign \main_muxid \input_muxid$18
     sync init
   end
-  process $group_7
-    assign \ldst_port0_is_st_i$2 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:246"
-    switch { \idx_l_q_idx_l }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:246"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:116"
-        switch { }
-          case 0'
-            assign \ldst_port0_is_st_i$2 \ldst_port0_is_st_i
-        end
-    end
+  process $group_22
+    assign \main_sr_op__insn_type 7'0000000
+    assign \main_sr_op__fn_unit 11'00000000000
+    assign \main_sr_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \main_sr_op__imm_data__imm_ok 1'0
+    assign \main_sr_op__rc__rc 1'0
+    assign \main_sr_op__rc__rc_ok 1'0
+    assign \main_sr_op__oe__oe 1'0
+    assign \main_sr_op__oe__oe_ok 1'0
+    assign { } 0'0
+    assign \main_sr_op__input_carry 2'00
+    assign \main_sr_op__output_carry 1'0
+    assign \main_sr_op__input_cr 1'0
+    assign \main_sr_op__output_cr 1'0
+    assign \main_sr_op__is_32bit 1'0
+    assign \main_sr_op__is_signed 1'0
+    assign \main_sr_op__insn 32'00000000000000000000000000000000
+    assign { \main_sr_op__insn \main_sr_op__is_signed \main_sr_op__is_32bit \main_sr_op__output_cr \main_sr_op__input_cr \main_sr_op__output_carry \main_sr_op__input_carry { } { \main_sr_op__oe__oe_ok \main_sr_op__oe__oe } { \main_sr_op__rc__rc_ok \main_sr_op__rc__rc } { \main_sr_op__imm_data__imm_ok \main_sr_op__imm_data__imm } \main_sr_op__fn_unit \main_sr_op__insn_type } { \input_sr_op__insn$33 \input_sr_op__is_signed$32 \input_sr_op__is_32bit$31 \input_sr_op__output_cr$30 \input_sr_op__input_cr$29 \input_sr_op__output_carry$28 \input_sr_op__input_carry$27 { } { \input_sr_op__oe__oe_ok$26 \input_sr_op__oe__oe$25 } { \input_sr_op__rc__rc_ok$24 \input_sr_op__rc__rc$23 } { \input_sr_op__imm_data__imm_ok$22 \input_sr_op__imm_data__imm$21 } \input_sr_op__fn_unit$20 \input_sr_op__insn_type$19 }
     sync init
   end
-  process $group_8
-    assign \ldst_port0_data_len$3 4'0000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:246"
-    switch { \idx_l_q_idx_l }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:246"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:117"
-        switch { }
-          case 0'
-            assign \ldst_port0_data_len$3 \ldst_port0_data_len
-        end
-    end
+  process $group_38
+    assign \main_ra 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \main_ra \input_ra$34
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:103"
-  wire width 1 \ldst_port0_go_die_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:103"
-  wire width 1 \ldst_port0_go_die_i$22
-  process $group_9
-    assign \ldst_port0_go_die_i 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:246"
-    switch { \idx_l_q_idx_l }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:246"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:118"
-        switch { }
-          case 0'
-            assign \ldst_port0_go_die_i \ldst_port0_go_die_i$22
-        end
-    end
+  process $group_39
+    assign \main_rb 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \main_rb \input_rb$35
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:119"
-  wire width 96 $23
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:119"
-  wire width 96 $24
-  connect $24 \ldst_port0_addr_i
-  process $group_10
-    assign \ldst_port0_addr_i$4 48'000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:246"
-    switch { \idx_l_q_idx_l }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:246"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:119"
-        switch { }
-          case 0'
-            assign \ldst_port0_addr_i$4 $24 [47:0]
-        end
-    end
+  process $group_40
+    assign \main_rc 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \main_rc \input_rc$36
     sync init
   end
-  process $group_11
-    assign \ldst_port0_addr_i_ok$5 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:246"
-    switch { \idx_l_q_idx_l }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:246"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:120"
-        switch { }
-          case 0'
-            assign \ldst_port0_addr_i_ok$5 \ldst_port0_addr_i_ok
-        end
-    end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
+  wire width 2 \xer_ca$74
+  process $group_41
+    assign \xer_ca$74 2'00
+    assign \xer_ca$74 \input_xer_ca$37
     sync init
   end
-  process $group_12
-    assign \ldst_port0_st_data_i$10 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \ldst_port0_st_data_i_ok$9 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:246"
-    switch { \idx_l_q_idx_l }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:246"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:121"
-        switch { }
-          case 0'
-            assign { \ldst_port0_st_data_i_ok$9 \ldst_port0_st_data_i$10 } { \ldst_port0_st_data_i_ok \ldst_port0_st_data_i }
-        end
-    end
+  process $group_42
+    assign \output_muxid 2'00
+    assign \output_muxid \main_muxid$38
     sync init
   end
-  process $group_14
-    assign \ldst_port0_ld_data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \ldst_port0_ld_data_o_ok 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:246"
-    switch { \idx_l_q_idx_l }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:246"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:122"
-        switch { }
-          case 0'
-            assign { \ldst_port0_ld_data_o_ok \ldst_port0_ld_data_o } { \ldst_port0_ld_data_o_ok$8 \ldst_port0_ld_data_o$7 }
-        end
-    end
+  process $group_43
+    assign \output_sr_op__insn_type 7'0000000
+    assign \output_sr_op__fn_unit 11'00000000000
+    assign \output_sr_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \output_sr_op__imm_data__imm_ok 1'0
+    assign \output_sr_op__rc__rc 1'0
+    assign \output_sr_op__rc__rc_ok 1'0
+    assign \output_sr_op__oe__oe 1'0
+    assign \output_sr_op__oe__oe_ok 1'0
+    assign { } 0'0
+    assign \output_sr_op__input_carry 2'00
+    assign \output_sr_op__output_carry 1'0
+    assign \output_sr_op__input_cr 1'0
+    assign \output_sr_op__output_cr 1'0
+    assign \output_sr_op__is_32bit 1'0
+    assign \output_sr_op__is_signed 1'0
+    assign \output_sr_op__insn 32'00000000000000000000000000000000
+    assign { \output_sr_op__insn \output_sr_op__is_signed \output_sr_op__is_32bit \output_sr_op__output_cr \output_sr_op__input_cr \output_sr_op__output_carry \output_sr_op__input_carry { } { \output_sr_op__oe__oe_ok \output_sr_op__oe__oe } { \output_sr_op__rc__rc_ok \output_sr_op__rc__rc } { \output_sr_op__imm_data__imm_ok \output_sr_op__imm_data__imm } \output_sr_op__fn_unit \output_sr_op__insn_type } { \main_sr_op__insn$53 \main_sr_op__is_signed$52 \main_sr_op__is_32bit$51 \main_sr_op__output_cr$50 \main_sr_op__input_cr$49 \main_sr_op__output_carry$48 \main_sr_op__input_carry$47 { } { \main_sr_op__oe__oe_ok$46 \main_sr_op__oe__oe$45 } { \main_sr_op__rc__rc_ok$44 \main_sr_op__rc__rc$43 } { \main_sr_op__imm_data__imm_ok$42 \main_sr_op__imm_data__imm$41 } \main_sr_op__fn_unit$40 \main_sr_op__insn_type$39 }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102"
-  wire width 1 \ldst_port0_busy_o$25
-  process $group_16
-    assign \ldst_port0_busy_o$25 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:246"
-    switch { \idx_l_q_idx_l }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:246"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:123"
-        switch { }
-          case 0'
-            assign \ldst_port0_busy_o$25 \ldst_port0_busy_o
-        end
-    end
+  process $group_59
+    assign \output_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \output_o_ok 1'0
+    assign { \output_o_ok \output_o } { \main_o_ok \main_o }
     sync init
   end
-  process $group_17
-    assign \ldst_port0_addr_ok_o 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:246"
-    switch { \idx_l_q_idx_l }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:246"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:124"
-        switch { }
-          case 0'
-            assign \ldst_port0_addr_ok_o \ldst_port0_addr_ok_o$6
-        end
-    end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 \cr_a_ok$75
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 4 \cr_a$76
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 \cr_a_ok$77
+  process $group_61
+    assign \output_cr_a 4'0000
+    assign \cr_a_ok$75 1'0
+    assign { \cr_a_ok$75 \output_cr_a } { \cr_a_ok$77 \cr_a$76 }
     sync init
   end
-  process $group_18
-    assign \ldst_port0_addr_exc_o 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:246"
-    switch { \idx_l_q_idx_l }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:246"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:125"
-        switch { }
-          case 0'
-            assign \ldst_port0_addr_exc_o \ldst_port0_addr_exc_o$11
-        end
-    end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 \xer_ca_ok$78
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 \xer_ca_ok$79
+  process $group_63
+    assign \output_xer_ca 2'00
+    assign \xer_ca_ok$78 1'0
+    assign { \xer_ca_ok$78 \output_xer_ca } { \xer_ca_ok$79 \main_xer_ca }
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:252"
-  wire width 1 \reset_delay
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:252"
-  wire width 1 \reset_delay$next
-  process $group_19
-    assign \reset_delay$next \reset_delay
-    assign \reset_delay$next \reset_l_q_reset
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621"
+  wire width 1 \p_valid_i$80
+  process $group_65
+    assign \p_valid_i$80 1'0
+    assign \p_valid_i$80 \p_valid_i
     sync init
-      update \reset_delay 1'0
-    sync posedge \clk
-      update \reset_delay \reset_delay$next
   end
-  process $group_20
-    assign \idx_l_r_idx_l 1'1
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:256"
-    switch { \reset_l_q_reset }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:256"
-      case 1'1
-        assign \idx_l_r_idx_l 1'1
-    end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619"
+  wire width 1 \n_i_rdy_data
+  process $group_66
+    assign \n_i_rdy_data 1'0
+    assign \n_i_rdy_data \n_ready_i
     sync init
   end
-  connect \ldst_port0_go_die_i$22 1'0
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.l0.lsmem"
-module \lsmem
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:27"
-  wire width 8 input 2 \x_mask_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:26"
-  wire width 48 input 3 \x_addr_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:45"
-  wire width 64 output 4 \m_ld_data_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:45"
-  wire width 64 \m_ld_data_o$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:42"
-  wire width 1 output 5 \x_busy_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:30"
-  wire width 64 input 6 \x_st_data_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:28"
-  wire width 1 input 7 \x_ld_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:29"
-  wire width 1 input 8 \x_st_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:37"
-  wire width 1 input 9 \m_valid_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:33"
-  wire width 1 input 10 \x_valid_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
-  wire width 1 output 11 \dbus__cyc
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
-  wire width 1 \dbus__cyc$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
-  wire width 1 input 12 \dbus__ack
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
-  wire width 1 input 13 \dbus__err
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
-  wire width 1 output 14 \dbus__stb
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
-  wire width 1 \dbus__stb$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
-  wire width 64 input 15 \dbus__dat_r
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
-  wire width 45 output 16 \dbus__adr
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
-  wire width 45 \dbus__adr$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
-  wire width 8 output 17 \dbus__sel
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
-  wire width 8 \dbus__sel$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
-  wire width 1 output 18 \dbus__we
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
-  wire width 1 \dbus__we$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
-  wire width 64 output 19 \dbus__dat_w
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
-  wire width 64 \dbus__dat_w$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
-  wire width 1 $1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
-  cell $or $2
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620"
+  wire width 1 \p_valid_i_p_ready_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624"
+  wire width 1 $81
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624"
+  cell $and $82
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \x_ld_i
-    connect \B \x_st_i
-    connect \Y $1
+    connect \A \p_valid_i$80
+    connect \B \p_ready_o
+    connect \Y $81
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
-  wire width 1 $3
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
-  cell $and $4
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A $1
-    connect \B \x_valid_i
-    connect \Y $3
+  process $group_67
+    assign \p_valid_i_p_ready_o 1'0
+    assign \p_valid_i_p_ready_o $81
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
-  wire width 1 $5
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32"
-  wire width 1 \x_stall_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
-  cell $not $6
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \x_stall_i
-    connect \Y $5
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
+  wire width 2 \muxid$83
+  process $group_68
+    assign \muxid$83 2'00
+    assign \muxid$83 \output_muxid$54
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
-  wire width 1 $7
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
-  cell $and $8
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A $3
-    connect \B $5
-    connect \Y $7
+  attribute \enum_base_type "MicrOp"
+  attribute \enum_value_0000000 "OP_ILLEGAL"
+  attribute \enum_value_0000001 "OP_NOP"
+  attribute \enum_value_0000010 "OP_ADD"
+  attribute \enum_value_0000011 "OP_ADDPCIS"
+  attribute \enum_value_0000100 "OP_AND"
+  attribute \enum_value_0000101 "OP_ATTN"
+  attribute \enum_value_0000110 "OP_B"
+  attribute \enum_value_0000111 "OP_BC"
+  attribute \enum_value_0001000 "OP_BCREG"
+  attribute \enum_value_0001001 "OP_BPERM"
+  attribute \enum_value_0001010 "OP_CMP"
+  attribute \enum_value_0001011 "OP_CMPB"
+  attribute \enum_value_0001100 "OP_CMPEQB"
+  attribute \enum_value_0001101 "OP_CMPRB"
+  attribute \enum_value_0001110 "OP_CNTZ"
+  attribute \enum_value_0001111 "OP_CRAND"
+  attribute \enum_value_0010000 "OP_CRANDC"
+  attribute \enum_value_0010001 "OP_CREQV"
+  attribute \enum_value_0010010 "OP_CRNAND"
+  attribute \enum_value_0010011 "OP_CRNOR"
+  attribute \enum_value_0010100 "OP_CROR"
+  attribute \enum_value_0010101 "OP_CRORC"
+  attribute \enum_value_0010110 "OP_CRXOR"
+  attribute \enum_value_0010111 "OP_DARN"
+  attribute \enum_value_0011000 "OP_DCBF"
+  attribute \enum_value_0011001 "OP_DCBST"
+  attribute \enum_value_0011010 "OP_DCBT"
+  attribute \enum_value_0011011 "OP_DCBTST"
+  attribute \enum_value_0011100 "OP_DCBZ"
+  attribute \enum_value_0011101 "OP_DIV"
+  attribute \enum_value_0011110 "OP_DIVE"
+  attribute \enum_value_0011111 "OP_EXTS"
+  attribute \enum_value_0100000 "OP_EXTSWSLI"
+  attribute \enum_value_0100001 "OP_ICBI"
+  attribute \enum_value_0100010 "OP_ICBT"
+  attribute \enum_value_0100011 "OP_ISEL"
+  attribute \enum_value_0100100 "OP_ISYNC"
+  attribute \enum_value_0100101 "OP_LOAD"
+  attribute \enum_value_0100110 "OP_STORE"
+  attribute \enum_value_0100111 "OP_MADDHD"
+  attribute \enum_value_0101000 "OP_MADDHDU"
+  attribute \enum_value_0101001 "OP_MADDLD"
+  attribute \enum_value_0101010 "OP_MCRF"
+  attribute \enum_value_0101011 "OP_MCRXR"
+  attribute \enum_value_0101100 "OP_MCRXRX"
+  attribute \enum_value_0101101 "OP_MFCR"
+  attribute \enum_value_0101110 "OP_MFSPR"
+  attribute \enum_value_0101111 "OP_MOD"
+  attribute \enum_value_0110000 "OP_MTCRF"
+  attribute \enum_value_0110001 "OP_MTSPR"
+  attribute \enum_value_0110010 "OP_MUL_L64"
+  attribute \enum_value_0110011 "OP_MUL_H64"
+  attribute \enum_value_0110100 "OP_MUL_H32"
+  attribute \enum_value_0110101 "OP_OR"
+  attribute \enum_value_0110110 "OP_POPCNT"
+  attribute \enum_value_0110111 "OP_PRTY"
+  attribute \enum_value_0111000 "OP_RLC"
+  attribute \enum_value_0111001 "OP_RLCL"
+  attribute \enum_value_0111010 "OP_RLCR"
+  attribute \enum_value_0111011 "OP_SETB"
+  attribute \enum_value_0111100 "OP_SHL"
+  attribute \enum_value_0111101 "OP_SHR"
+  attribute \enum_value_0111110 "OP_SYNC"
+  attribute \enum_value_0111111 "OP_TRAP"
+  attribute \enum_value_1000011 "OP_XOR"
+  attribute \enum_value_1000100 "OP_SIM_CONFIG"
+  attribute \enum_value_1000101 "OP_CROP"
+  attribute \enum_value_1000110 "OP_RFID"
+  attribute \enum_value_1000111 "OP_MFMSR"
+  attribute \enum_value_1001000 "OP_MTMSRD"
+  attribute \enum_value_1001001 "OP_SC"
+  attribute \enum_value_1001010 "OP_MTMSR"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 \sr_op__insn_type$84
+  attribute \enum_base_type "Function"
+  attribute \enum_value_00000000000 "NONE"
+  attribute \enum_value_00000000010 "ALU"
+  attribute \enum_value_00000000100 "LDST"
+  attribute \enum_value_00000001000 "SHIFT_ROT"
+  attribute \enum_value_00000010000 "LOGICAL"
+  attribute \enum_value_00000100000 "BRANCH"
+  attribute \enum_value_00001000000 "CR"
+  attribute \enum_value_00010000000 "TRAP"
+  attribute \enum_value_00100000000 "MUL"
+  attribute \enum_value_01000000000 "DIV"
+  attribute \enum_value_10000000000 "SPR"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 \sr_op__fn_unit$85
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 \sr_op__imm_data__imm$86
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \sr_op__imm_data__imm_ok$87
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \sr_op__rc__rc$88
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \sr_op__rc__rc_ok$89
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \sr_op__oe__oe$90
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \sr_op__oe__oe_ok$91
+  attribute \enum_base_type "CryIn"
+  attribute \enum_value_00 "ZERO"
+  attribute \enum_value_01 "ONE"
+  attribute \enum_value_10 "CA"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 2 \sr_op__input_carry$92
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \sr_op__output_carry$93
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \sr_op__input_cr$94
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \sr_op__output_cr$95
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \sr_op__is_32bit$96
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \sr_op__is_signed$97
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \sr_op__insn$98
+  process $group_69
+    assign \sr_op__insn_type$84 7'0000000
+    assign \sr_op__fn_unit$85 11'00000000000
+    assign \sr_op__imm_data__imm$86 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \sr_op__imm_data__imm_ok$87 1'0
+    assign \sr_op__rc__rc$88 1'0
+    assign \sr_op__rc__rc_ok$89 1'0
+    assign \sr_op__oe__oe$90 1'0
+    assign \sr_op__oe__oe_ok$91 1'0
+    assign { } 0'0
+    assign \sr_op__input_carry$92 2'00
+    assign \sr_op__output_carry$93 1'0
+    assign \sr_op__input_cr$94 1'0
+    assign \sr_op__output_cr$95 1'0
+    assign \sr_op__is_32bit$96 1'0
+    assign \sr_op__is_signed$97 1'0
+    assign \sr_op__insn$98 32'00000000000000000000000000000000
+    assign { \sr_op__insn$98 \sr_op__is_signed$97 \sr_op__is_32bit$96 \sr_op__output_cr$95 \sr_op__input_cr$94 \sr_op__output_carry$93 \sr_op__input_carry$92 { } { \sr_op__oe__oe_ok$91 \sr_op__oe__oe$90 } { \sr_op__rc__rc_ok$89 \sr_op__rc__rc$88 } { \sr_op__imm_data__imm_ok$87 \sr_op__imm_data__imm$86 } \sr_op__fn_unit$85 \sr_op__insn_type$84 } { \output_sr_op__insn$69 \output_sr_op__is_signed$68 \output_sr_op__is_32bit$67 \output_sr_op__output_cr$66 \output_sr_op__input_cr$65 \output_sr_op__output_carry$64 \output_sr_op__input_carry$63 { } { \output_sr_op__oe__oe_ok$62 \output_sr_op__oe__oe$61 } { \output_sr_op__rc__rc_ok$60 \output_sr_op__rc__rc$59 } { \output_sr_op__imm_data__imm_ok$58 \output_sr_op__imm_data__imm$57 } \output_sr_op__fn_unit$56 \output_sr_op__insn_type$55 }
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:84"
-  wire width 1 $9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:84"
-  cell $or $10
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \dbus__ack
-    connect \B \dbus__err
-    connect \Y $9
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 64 \o$99
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 \o_ok$100
+  process $group_85
+    assign \o$99 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \o_ok$100 1'0
+    assign { \o_ok$100 \o$99 } { \output_o_ok$71 \output_o$70 }
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:84"
-  wire width 1 $11
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:84"
-  cell $not $12
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \m_valid_i
-    connect \Y $11
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 4 \cr_a$101
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 \cr_a_ok$102
+  process $group_87
+    assign \cr_a$101 4'0000
+    assign \cr_a_ok$102 1'0
+    assign { \cr_a_ok$102 \cr_a$101 } { \output_cr_a_ok \output_cr_a$72 }
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:84"
-  wire width 1 $13
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:84"
-  cell $or $14
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A $9
-    connect \B $11
-    connect \Y $13
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 2 \xer_ca$103
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 \xer_ca_ok$104
+  process $group_89
+    assign \xer_ca$103 2'00
+    assign \xer_ca_ok$104 1'0
+    assign { \xer_ca_ok$104 \xer_ca$103 } { \output_xer_ca_ok \output_xer_ca$73 }
+    sync init
   end
-  process $group_0
-    assign \dbus__cyc$next \dbus__cyc
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:83"
-    switch { $7 \dbus__cyc }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:83"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615"
+  wire width 1 \r_busy
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615"
+  wire width 1 \r_busy$next
+  process $group_91
+    assign \r_busy$next \r_busy
+    attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+    switch { \n_i_rdy_data \p_valid_i_p_ready_o }
+      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
       case 2'-1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:84"
-        switch { $13 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:84"
-          case 1'1
-            assign \dbus__cyc$next 1'0
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
+        assign \r_busy$next 1'1
+      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
       case 2'1-
-        assign \dbus__cyc$next 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:100"
-      case
+        assign \r_busy$next 1'0
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
-        assign \dbus__cyc$next 1'0
+        assign \r_busy$next 1'0
     end
     sync init
-      update \dbus__cyc 1'0
-    sync posedge \clk
-      update \dbus__cyc \dbus__cyc$next
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
-  wire width 1 $15
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
-  cell $or $16
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \x_ld_i
-    connect \B \x_st_i
-    connect \Y $15
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
-  wire width 1 $17
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
-  cell $and $18
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A $15
-    connect \B \x_valid_i
-    connect \Y $17
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
-  wire width 1 $19
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
-  cell $not $20
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \x_stall_i
-    connect \Y $19
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
-  wire width 1 $21
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
-  cell $and $22
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A $17
-    connect \B $19
-    connect \Y $21
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:84"
-  wire width 1 $23
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:84"
-  cell $or $24
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \dbus__ack
-    connect \B \dbus__err
-    connect \Y $23
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:84"
-  wire width 1 $25
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:84"
-  cell $not $26
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \m_valid_i
-    connect \Y $25
+      update \r_busy 1'0
+    sync posedge \coresync_clk
+      update \r_busy \r_busy$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:84"
-  wire width 1 $27
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:84"
-  cell $or $28
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A $23
-    connect \B $25
-    connect \Y $27
+  process $group_92
+    assign \muxid$1$next \muxid$1
+    attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+    switch { \n_i_rdy_data \p_valid_i_p_ready_o }
+      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+      case 2'-1
+        assign \muxid$1$next \muxid$83
+      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
+      case 2'1-
+        assign \muxid$1$next \muxid$83
+    end
+    sync init
+      update \muxid$1 2'00
+    sync posedge \coresync_clk
+      update \muxid$1 \muxid$1$next
   end
-  process $group_1
-    assign \dbus__stb$next \dbus__stb
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:83"
-    switch { $21 \dbus__cyc }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:83"
+  process $group_93
+    assign \sr_op__insn_type$2$next \sr_op__insn_type$2
+    assign \sr_op__fn_unit$3$next \sr_op__fn_unit$3
+    assign \sr_op__imm_data__imm$4$next \sr_op__imm_data__imm$4
+    assign \sr_op__imm_data__imm_ok$5$next \sr_op__imm_data__imm_ok$5
+    assign \sr_op__rc__rc$6$next \sr_op__rc__rc$6
+    assign \sr_op__rc__rc_ok$7$next \sr_op__rc__rc_ok$7
+    assign \sr_op__oe__oe$8$next \sr_op__oe__oe$8
+    assign \sr_op__oe__oe_ok$9$next \sr_op__oe__oe_ok$9
+    assign { } { }
+    assign \sr_op__input_carry$10$next \sr_op__input_carry$10
+    assign \sr_op__output_carry$11$next \sr_op__output_carry$11
+    assign \sr_op__input_cr$12$next \sr_op__input_cr$12
+    assign \sr_op__output_cr$13$next \sr_op__output_cr$13
+    assign \sr_op__is_32bit$14$next \sr_op__is_32bit$14
+    assign \sr_op__is_signed$15$next \sr_op__is_signed$15
+    assign \sr_op__insn$16$next \sr_op__insn$16
+    attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+    switch { \n_i_rdy_data \p_valid_i_p_ready_o }
+      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
       case 2'-1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:84"
-        switch { $27 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:84"
-          case 1'1
-            assign \dbus__stb$next 1'0
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
+        assign { \sr_op__insn$16$next \sr_op__is_signed$15$next \sr_op__is_32bit$14$next \sr_op__output_cr$13$next \sr_op__input_cr$12$next \sr_op__output_carry$11$next \sr_op__input_carry$10$next { } { \sr_op__oe__oe_ok$9$next \sr_op__oe__oe$8$next } { \sr_op__rc__rc_ok$7$next \sr_op__rc__rc$6$next } { \sr_op__imm_data__imm_ok$5$next \sr_op__imm_data__imm$4$next } \sr_op__fn_unit$3$next \sr_op__insn_type$2$next } { \sr_op__insn$98 \sr_op__is_signed$97 \sr_op__is_32bit$96 \sr_op__output_cr$95 \sr_op__input_cr$94 \sr_op__output_carry$93 \sr_op__input_carry$92 { } { \sr_op__oe__oe_ok$91 \sr_op__oe__oe$90 } { \sr_op__rc__rc_ok$89 \sr_op__rc__rc$88 } { \sr_op__imm_data__imm_ok$87 \sr_op__imm_data__imm$86 } \sr_op__fn_unit$85 \sr_op__insn_type$84 }
+      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
       case 2'1-
-        assign \dbus__stb$next 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:100"
-      case
+        assign { \sr_op__insn$16$next \sr_op__is_signed$15$next \sr_op__is_32bit$14$next \sr_op__output_cr$13$next \sr_op__input_cr$12$next \sr_op__output_carry$11$next \sr_op__input_carry$10$next { } { \sr_op__oe__oe_ok$9$next \sr_op__oe__oe$8$next } { \sr_op__rc__rc_ok$7$next \sr_op__rc__rc$6$next } { \sr_op__imm_data__imm_ok$5$next \sr_op__imm_data__imm$4$next } \sr_op__fn_unit$3$next \sr_op__insn_type$2$next } { \sr_op__insn$98 \sr_op__is_signed$97 \sr_op__is_32bit$96 \sr_op__output_cr$95 \sr_op__input_cr$94 \sr_op__output_carry$93 \sr_op__input_carry$92 { } { \sr_op__oe__oe_ok$91 \sr_op__oe__oe$90 } { \sr_op__rc__rc_ok$89 \sr_op__rc__rc$88 } { \sr_op__imm_data__imm_ok$87 \sr_op__imm_data__imm$86 } \sr_op__fn_unit$85 \sr_op__insn_type$84 }
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
-        assign \dbus__stb$next 1'0
+        assign \sr_op__imm_data__imm$4$next 64'0000000000000000000000000000000000000000000000000000000000000000
+        assign \sr_op__imm_data__imm_ok$5$next 1'0
+        assign \sr_op__rc__rc$6$next 1'0
+        assign \sr_op__rc__rc_ok$7$next 1'0
+        assign \sr_op__oe__oe$8$next 1'0
+        assign \sr_op__oe__oe_ok$9$next 1'0
     end
     sync init
-      update \dbus__stb 1'0
-    sync posedge \clk
-      update \dbus__stb \dbus__stb$next
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
-  wire width 1 $29
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
-  cell $or $30
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \x_ld_i
-    connect \B \x_st_i
-    connect \Y $29
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
-  wire width 1 $31
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
-  cell $and $32
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A $29
-    connect \B \x_valid_i
-    connect \Y $31
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
-  wire width 1 $33
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
-  cell $not $34
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \x_stall_i
-    connect \Y $33
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
-  wire width 1 $35
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
-  cell $and $36
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A $31
-    connect \B $33
-    connect \Y $35
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:84"
-  wire width 1 $37
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:84"
-  cell $or $38
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \dbus__ack
-    connect \B \dbus__err
-    connect \Y $37
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:84"
-  wire width 1 $39
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:84"
-  cell $not $40
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \m_valid_i
-    connect \Y $39
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:84"
-  wire width 1 $41
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:84"
-  cell $or $42
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A $37
-    connect \B $39
-    connect \Y $41
-  end
-  process $group_2
-    assign \m_ld_data_o$next \m_ld_data_o
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:83"
-    switch { $35 \dbus__cyc }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:83"
-      case 2'-1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:84"
-        switch { $41 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:84"
-          case 1'1
-            assign \m_ld_data_o$next \dbus__dat_r
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
-      case 2'1-
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:100"
-      case
-    end
-    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
-      case 1'1
-        assign \m_ld_data_o$next 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
-    sync init
-      update \m_ld_data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    sync posedge \clk
-      update \m_ld_data_o \m_ld_data_o$next
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
-  wire width 1 $43
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
-  cell $or $44
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \x_ld_i
-    connect \B \x_st_i
-    connect \Y $43
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
-  wire width 1 $45
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
-  cell $and $46
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A $43
-    connect \B \x_valid_i
-    connect \Y $45
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
-  wire width 1 $47
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
-  cell $not $48
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \x_stall_i
-    connect \Y $47
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
-  wire width 1 $49
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
-  cell $and $50
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A $45
-    connect \B $47
-    connect \Y $49
+      update \sr_op__insn_type$2 7'0000000
+      update \sr_op__fn_unit$3 11'00000000000
+      update \sr_op__imm_data__imm$4 64'0000000000000000000000000000000000000000000000000000000000000000
+      update \sr_op__imm_data__imm_ok$5 1'0
+      update \sr_op__rc__rc$6 1'0
+      update \sr_op__rc__rc_ok$7 1'0
+      update \sr_op__oe__oe$8 1'0
+      update \sr_op__oe__oe_ok$9 1'0
+      update { } 0'0
+      update \sr_op__input_carry$10 2'00
+      update \sr_op__output_carry$11 1'0
+      update \sr_op__input_cr$12 1'0
+      update \sr_op__output_cr$13 1'0
+      update \sr_op__is_32bit$14 1'0
+      update \sr_op__is_signed$15 1'0
+      update \sr_op__insn$16 32'00000000000000000000000000000000
+    sync posedge \coresync_clk
+      update \sr_op__insn_type$2 \sr_op__insn_type$2$next
+      update \sr_op__fn_unit$3 \sr_op__fn_unit$3$next
+      update \sr_op__imm_data__imm$4 \sr_op__imm_data__imm$4$next
+      update \sr_op__imm_data__imm_ok$5 \sr_op__imm_data__imm_ok$5$next
+      update \sr_op__rc__rc$6 \sr_op__rc__rc$6$next
+      update \sr_op__rc__rc_ok$7 \sr_op__rc__rc_ok$7$next
+      update \sr_op__oe__oe$8 \sr_op__oe__oe$8$next
+      update \sr_op__oe__oe_ok$9 \sr_op__oe__oe_ok$9$next
+      update { } { }
+      update \sr_op__input_carry$10 \sr_op__input_carry$10$next
+      update \sr_op__output_carry$11 \sr_op__output_carry$11$next
+      update \sr_op__input_cr$12 \sr_op__input_cr$12$next
+      update \sr_op__output_cr$13 \sr_op__output_cr$13$next
+      update \sr_op__is_32bit$14 \sr_op__is_32bit$14$next
+      update \sr_op__is_signed$15 \sr_op__is_signed$15$next
+      update \sr_op__insn$16 \sr_op__insn$16$next
   end
-  process $group_3
-    assign \dbus__adr$next \dbus__adr
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:83"
-    switch { $49 \dbus__cyc }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:83"
+  process $group_109
+    assign \o$next \o
+    assign \o_ok$next \o_ok
+    attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+    switch { \n_i_rdy_data \p_valid_i_p_ready_o }
+      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
       case 2'-1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
+        assign { \o_ok$next \o$next } { \o_ok$100 \o$99 }
+      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
       case 2'1-
-        assign \dbus__adr$next \x_addr_i [47:3]
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:100"
-      case
-        assign \dbus__adr$next 45'000000000000000000000000000000000000000000000
+        assign { \o_ok$next \o$next } { \o_ok$100 \o$99 }
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
-        assign \dbus__adr$next 45'000000000000000000000000000000000000000000000
+        assign \o_ok$next 1'0
     end
     sync init
-      update \dbus__adr 45'000000000000000000000000000000000000000000000
-    sync posedge \clk
-      update \dbus__adr \dbus__adr$next
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
-  wire width 1 $51
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
-  cell $or $52
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \x_ld_i
-    connect \B \x_st_i
-    connect \Y $51
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
-  wire width 1 $53
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
-  cell $and $54
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A $51
-    connect \B \x_valid_i
-    connect \Y $53
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
-  wire width 1 $55
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
-  cell $not $56
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \x_stall_i
-    connect \Y $55
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
-  wire width 1 $57
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
-  cell $and $58
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A $53
-    connect \B $55
-    connect \Y $57
+      update \o 64'0000000000000000000000000000000000000000000000000000000000000000
+      update \o_ok 1'0
+    sync posedge \coresync_clk
+      update \o \o$next
+      update \o_ok \o_ok$next
   end
-  process $group_4
-    assign \dbus__sel$next \dbus__sel
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:83"
-    switch { $57 \dbus__cyc }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:83"
+  process $group_111
+    assign \cr_a$next \cr_a
+    assign \cr_a_ok$next \cr_a_ok
+    attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+    switch { \n_i_rdy_data \p_valid_i_p_ready_o }
+      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
       case 2'-1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
+        assign { \cr_a_ok$next \cr_a$next } { \cr_a_ok$102 \cr_a$101 }
+      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
       case 2'1-
-        assign \dbus__sel$next \x_mask_i
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:100"
-      case
-        assign \dbus__sel$next 8'00000000
-        assign \dbus__sel$next 8'00000000
+        assign { \cr_a_ok$next \cr_a$next } { \cr_a_ok$102 \cr_a$101 }
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
-        assign \dbus__sel$next 8'00000000
+        assign \cr_a_ok$next 1'0
     end
     sync init
-      update \dbus__sel 8'00000000
-    sync posedge \clk
-      update \dbus__sel \dbus__sel$next
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
-  wire width 1 $59
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
-  cell $or $60
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \x_ld_i
-    connect \B \x_st_i
-    connect \Y $59
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
-  wire width 1 $61
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
-  cell $and $62
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A $59
-    connect \B \x_valid_i
-    connect \Y $61
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
-  wire width 1 $63
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
-  cell $not $64
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \x_stall_i
-    connect \Y $63
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
-  wire width 1 $65
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
-  cell $and $66
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A $61
-    connect \B $63
-    connect \Y $65
+      update \cr_a 4'0000
+      update \cr_a_ok 1'0
+    sync posedge \coresync_clk
+      update \cr_a \cr_a$next
+      update \cr_a_ok \cr_a_ok$next
   end
-  process $group_5
-    assign \dbus__we$next \dbus__we
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:83"
-    switch { $65 \dbus__cyc }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:83"
+  process $group_113
+    assign \xer_ca$17$next \xer_ca$17
+    assign \xer_ca_ok$next \xer_ca_ok
+    attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
+    switch { \n_i_rdy_data \p_valid_i_p_ready_o }
+      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631"
       case 2'-1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
+        assign { \xer_ca_ok$next \xer_ca$17$next } { \xer_ca_ok$104 \xer_ca$103 }
+      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637"
       case 2'1-
-        assign \dbus__we$next \x_st_i
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:100"
-      case
-        assign \dbus__we$next 1'0
+        assign { \xer_ca_ok$next \xer_ca$17$next } { \xer_ca_ok$104 \xer_ca$103 }
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
-        assign \dbus__we$next 1'0
+        assign \xer_ca_ok$next 1'0
     end
     sync init
-      update \dbus__we 1'0
-    sync posedge \clk
-      update \dbus__we \dbus__we$next
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
-  wire width 1 $67
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
-  cell $or $68
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \x_ld_i
-    connect \B \x_st_i
-    connect \Y $67
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
-  wire width 1 $69
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
-  cell $and $70
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A $67
-    connect \B \x_valid_i
-    connect \Y $69
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
-  wire width 1 $71
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
-  cell $not $72
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \x_stall_i
-    connect \Y $71
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
-  wire width 1 $73
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
-  cell $and $74
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A $69
-    connect \B $71
-    connect \Y $73
+      update \xer_ca$17 2'00
+      update \xer_ca_ok 1'0
+    sync posedge \coresync_clk
+      update \xer_ca$17 \xer_ca$17$next
+      update \xer_ca_ok \xer_ca_ok$next
   end
-  process $group_6
-    assign \dbus__dat_w$next \dbus__dat_w
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:83"
-    switch { $73 \dbus__cyc }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:83"
-      case 2'-1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
-      case 2'1-
-        assign \dbus__dat_w$next \x_st_data_i
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:100"
-      case
-        assign \dbus__dat_w$next 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
-    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
-      case 1'1
-        assign \dbus__dat_w$next 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
+  process $group_115
+    assign \n_valid_o 1'0
+    assign \n_valid_o \r_busy
     sync init
-      update \dbus__dat_w 64'0000000000000000000000000000000000000000000000000000000000000000
-    sync posedge \clk
-      update \dbus__dat_w \dbus__dat_w$next
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:50"
-  wire width 1 \m_load_err_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:50"
-  wire width 1 \m_load_err_o$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:109"
-  wire width 1 $75
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:109"
-  cell $and $76
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \dbus__cyc
-    connect \B \dbus__err
-    connect \Y $75
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:115"
-  wire width 1 $77
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:36"
-  wire width 1 \m_stall_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:115"
-  cell $not $78
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \m_stall_i
-    connect \Y $77
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111"
-  wire width 1 $79
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111"
-  cell $not $80
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \dbus__we
-    connect \Y $79
-  end
-  process $group_7
-    assign \m_load_err_o$next \m_load_err_o
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:109"
-    switch { $77 $75 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:109"
-      case 2'-1
-        assign \m_load_err_o$next $79
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:115"
-      case 2'1-
-        assign \m_load_err_o$next 1'0
-    end
-    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
-      case 1'1
-        assign \m_load_err_o$next 1'0
-    end
+  process $group_116
+    assign \p_ready_o 1'0
+    assign \p_ready_o \n_i_rdy_data
     sync init
-      update \m_load_err_o 1'0
-    sync posedge \clk
-      update \m_load_err_o \m_load_err_o$next
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:51"
-  wire width 1 \m_store_err_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:51"
-  wire width 1 \m_store_err_o$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:109"
-  wire width 1 $81
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:109"
-  cell $and $82
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \dbus__cyc
-    connect \B \dbus__err
-    connect \Y $81
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:115"
-  wire width 1 $83
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:115"
-  cell $not $84
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \m_stall_i
-    connect \Y $83
-  end
-  process $group_8
-    assign \m_store_err_o$next \m_store_err_o
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:109"
-    switch { $83 $81 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:109"
-      case 2'-1
-        assign \m_store_err_o$next \dbus__we
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:115"
-      case 2'1-
-        assign \m_store_err_o$next 1'0
-    end
-    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
-      case 1'1
-        assign \m_store_err_o$next 1'0
-    end
-    sync init
-      update \m_store_err_o 1'0
-    sync posedge \clk
-      update \m_store_err_o \m_store_err_o$next
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:53"
-  wire width 45 \m_badaddr_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:53"
-  wire width 45 \m_badaddr_o$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:109"
-  wire width 1 $85
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:109"
-  cell $and $86
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \dbus__cyc
-    connect \B \dbus__err
-    connect \Y $85
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:115"
-  wire width 1 $87
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:115"
-  cell $not $88
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \m_stall_i
-    connect \Y $87
-  end
-  process $group_9
-    assign \m_badaddr_o$next \m_badaddr_o
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:109"
-    switch { $87 $85 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:109"
-      case 2'-1
-        assign \m_badaddr_o$next \dbus__adr
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:115"
-      case 2'1-
-    end
-    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
-      case 1'1
-        assign \m_badaddr_o$next 45'000000000000000000000000000000000000000000000
-    end
-    sync init
-      update \m_badaddr_o 45'000000000000000000000000000000000000000000000
-    sync posedge \clk
-      update \m_badaddr_o \m_badaddr_o$next
-  end
-  process $group_10
-    assign \x_busy_o 1'0
-    assign \x_busy_o \dbus__cyc
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:43"
-  wire width 1 \m_busy_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:123"
-  wire width 1 $89
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:123"
-  cell $or $90
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \m_load_err_o
-    connect \B \m_store_err_o
-    connect \Y $89
-  end
-  process $group_11
-    assign \m_busy_o 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:123"
-    switch { $89 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:123"
-      case 1'1
-        assign \m_busy_o 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:125"
-      case
-        assign \m_busy_o \dbus__cyc
-    end
-    sync init
-  end
-  connect \x_stall_i 1'0
-  connect \m_stall_i 1'0
+  connect \cr_a$76 4'0000
+  connect \cr_a_ok$77 1'0
+  connect \xer_ca_ok$79 1'0
 end
 attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.l0"
-module \l0
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:95"
-  wire width 1 input 2 \ldst_port0_is_ld_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:96"
-  wire width 1 input 3 \ldst_port0_is_st_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99"
-  wire width 4 input 4 \ldst_port0_data_len
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 96 input 5 \ldst_port0_addr_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 input 6 \ldst_port0_addr_i_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:107"
-  wire width 1 output 7 \ldst_port0_addr_exc_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:106"
-  wire width 1 output 8 \ldst_port0_addr_ok_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 64 output 9 \ldst_port0_ld_data_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 output 10 \ldst_port0_ld_data_o_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 64 input 11 \ldst_port0_st_data_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 input 12 \ldst_port0_st_data_i_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
-  wire width 1 output 13 \dbus__cyc
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
-  wire width 1 input 14 \dbus__ack
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
-  wire width 1 input 15 \dbus__err
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
-  wire width 1 output 16 \dbus__stb
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
-  wire width 64 input 17 \dbus__dat_r
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
-  wire width 45 output 18 \dbus__adr
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
-  wire width 8 output 19 \dbus__sel
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
-  wire width 1 output 20 \dbus__we
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
-  wire width 64 output 21 \dbus__dat_w
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:95"
-  wire width 1 \pimem_ldst_port0_is_ld_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102"
-  wire width 1 \pimem_ldst_port0_busy_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:96"
-  wire width 1 \pimem_ldst_port0_is_st_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99"
-  wire width 4 \pimem_ldst_port0_data_len
+attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0"
+module \alu_shift_rot0
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 48 \pimem_ldst_port0_addr_i
+  wire width 1 output 1 \o_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 \pimem_ldst_port0_addr_i_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:27"
-  wire width 8 \pimem_x_mask_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:26"
-  wire width 48 \pimem_x_addr_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:106"
-  wire width 1 \pimem_ldst_port0_addr_ok_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:45"
-  wire width 64 \pimem_m_ld_data_o
+  wire width 1 output 2 \cr_a_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 64 \pimem_ldst_port0_ld_data_o
+  wire width 1 output 3 \xer_ca_ok
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 4 \coresync_rst
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
+  wire width 1 output 5 \n_valid_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
+  wire width 1 input 6 \n_ready_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 \pimem_ldst_port0_ld_data_o_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:42"
-  wire width 1 \pimem_x_busy_o
+  wire width 64 output 7 \o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 \pimem_ldst_port0_st_data_i_ok
+  wire width 4 output 8 \cr_a
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 64 \pimem_ldst_port0_st_data_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:30"
-  wire width 64 \pimem_x_st_data_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:107"
-  wire width 1 \pimem_ldst_port0_addr_exc_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:28"
-  wire width 1 \pimem_x_ld_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:29"
-  wire width 1 \pimem_x_st_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:37"
-  wire width 1 \pimem_m_valid_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:33"
-  wire width 1 \pimem_x_valid_i
-  cell \pimem \pimem
-    connect \rst \rst
-    connect \clk \clk
-    connect \ldst_port0_is_ld_i \pimem_ldst_port0_is_ld_i
-    connect \ldst_port0_busy_o \pimem_ldst_port0_busy_o
-    connect \ldst_port0_is_st_i \pimem_ldst_port0_is_st_i
-    connect \ldst_port0_data_len \pimem_ldst_port0_data_len
-    connect \ldst_port0_addr_i \pimem_ldst_port0_addr_i
-    connect \ldst_port0_addr_i_ok \pimem_ldst_port0_addr_i_ok
-    connect \x_mask_i \pimem_x_mask_i
-    connect \x_addr_i \pimem_x_addr_i
-    connect \ldst_port0_addr_ok_o \pimem_ldst_port0_addr_ok_o
-    connect \m_ld_data_o \pimem_m_ld_data_o
-    connect \ldst_port0_ld_data_o \pimem_ldst_port0_ld_data_o
-    connect \ldst_port0_ld_data_o_ok \pimem_ldst_port0_ld_data_o_ok
-    connect \x_busy_o \pimem_x_busy_o
-    connect \ldst_port0_st_data_i_ok \pimem_ldst_port0_st_data_i_ok
-    connect \ldst_port0_st_data_i \pimem_ldst_port0_st_data_i
-    connect \x_st_data_i \pimem_x_st_data_i
-    connect \ldst_port0_addr_exc_o \pimem_ldst_port0_addr_exc_o
-    connect \x_ld_i \pimem_x_ld_i
-    connect \x_st_i \pimem_x_st_i
-    connect \m_valid_i \pimem_m_valid_i
-    connect \x_valid_i \pimem_x_valid_i
-  end
-  cell \l0$106 \l0
-    connect \rst \rst
-    connect \clk \clk
-    connect \ldst_port0_is_ld_i \ldst_port0_is_ld_i
-    connect \ldst_port0_is_st_i \ldst_port0_is_st_i
-    connect \ldst_port0_data_len \ldst_port0_data_len
-    connect \ldst_port0_addr_i \ldst_port0_addr_i
-    connect \ldst_port0_addr_i_ok \ldst_port0_addr_i_ok
-    connect \ldst_port0_addr_exc_o \ldst_port0_addr_exc_o
-    connect \ldst_port0_addr_ok_o \ldst_port0_addr_ok_o
-    connect \ldst_port0_ld_data_o \ldst_port0_ld_data_o
-    connect \ldst_port0_ld_data_o_ok \ldst_port0_ld_data_o_ok
-    connect \ldst_port0_st_data_i \ldst_port0_st_data_i
-    connect \ldst_port0_st_data_i_ok \ldst_port0_st_data_i_ok
-    connect \ldst_port0_is_ld_i$1 \pimem_ldst_port0_is_ld_i
-    connect \ldst_port0_busy_o \pimem_ldst_port0_busy_o
-    connect \ldst_port0_is_st_i$2 \pimem_ldst_port0_is_st_i
-    connect \ldst_port0_data_len$3 \pimem_ldst_port0_data_len
-    connect \ldst_port0_addr_i$4 \pimem_ldst_port0_addr_i
-    connect \ldst_port0_addr_i_ok$5 \pimem_ldst_port0_addr_i_ok
-    connect \ldst_port0_addr_ok_o$6 \pimem_ldst_port0_addr_ok_o
-    connect \ldst_port0_ld_data_o$7 \pimem_ldst_port0_ld_data_o
-    connect \ldst_port0_ld_data_o_ok$8 \pimem_ldst_port0_ld_data_o_ok
-    connect \ldst_port0_st_data_i_ok$9 \pimem_ldst_port0_st_data_i_ok
-    connect \ldst_port0_st_data_i$10 \pimem_ldst_port0_st_data_i
-    connect \ldst_port0_addr_exc_o$11 \pimem_ldst_port0_addr_exc_o
-  end
-  cell \lsmem \lsmem
-    connect \rst \rst
-    connect \clk \clk
-    connect \x_mask_i \pimem_x_mask_i
-    connect \x_addr_i \pimem_x_addr_i
-    connect \m_ld_data_o \pimem_m_ld_data_o
-    connect \x_busy_o \pimem_x_busy_o
-    connect \x_st_data_i \pimem_x_st_data_i
-    connect \x_ld_i \pimem_x_ld_i
-    connect \x_st_i \pimem_x_st_i
-    connect \m_valid_i \pimem_m_valid_i
-    connect \x_valid_i \pimem_x_valid_i
-    connect \dbus__cyc \dbus__cyc
-    connect \dbus__ack \dbus__ack
-    connect \dbus__err \dbus__err
-    connect \dbus__stb \dbus__stb
-    connect \dbus__dat_r \dbus__dat_r
-    connect \dbus__adr \dbus__adr
-    connect \dbus__sel \dbus__sel
-    connect \dbus__we \dbus__we
-    connect \dbus__dat_w \dbus__dat_w
-  end
-  connect \pimem_ldst_port0_addr_exc_o 1'0
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.int.reg_0"
-module \reg_0
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 2 \src10__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 3 \src10__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 4 \src20__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 5 \src20__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 6 \src30__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 7 \src30__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 8 \dest10__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 9 \dest10__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 10 \dest20__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 11 \dest20__data_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $2
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \src10__ren
-    connect \B 1'1
-    connect \Y $1
-  end
-  process $group_0
-    assign \wr_detect 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $1 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        assign \wr_detect 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest10__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest20__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-    end
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $3
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $4
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \src10__ren
-    connect \B 1'1
-    connect \Y $3
+  wire width 2 output 9 \xer_ca
+  attribute \enum_base_type "MicrOp"
+  attribute \enum_value_0000000 "OP_ILLEGAL"
+  attribute \enum_value_0000001 "OP_NOP"
+  attribute \enum_value_0000010 "OP_ADD"
+  attribute \enum_value_0000011 "OP_ADDPCIS"
+  attribute \enum_value_0000100 "OP_AND"
+  attribute \enum_value_0000101 "OP_ATTN"
+  attribute \enum_value_0000110 "OP_B"
+  attribute \enum_value_0000111 "OP_BC"
+  attribute \enum_value_0001000 "OP_BCREG"
+  attribute \enum_value_0001001 "OP_BPERM"
+  attribute \enum_value_0001010 "OP_CMP"
+  attribute \enum_value_0001011 "OP_CMPB"
+  attribute \enum_value_0001100 "OP_CMPEQB"
+  attribute \enum_value_0001101 "OP_CMPRB"
+  attribute \enum_value_0001110 "OP_CNTZ"
+  attribute \enum_value_0001111 "OP_CRAND"
+  attribute \enum_value_0010000 "OP_CRANDC"
+  attribute \enum_value_0010001 "OP_CREQV"
+  attribute \enum_value_0010010 "OP_CRNAND"
+  attribute \enum_value_0010011 "OP_CRNOR"
+  attribute \enum_value_0010100 "OP_CROR"
+  attribute \enum_value_0010101 "OP_CRORC"
+  attribute \enum_value_0010110 "OP_CRXOR"
+  attribute \enum_value_0010111 "OP_DARN"
+  attribute \enum_value_0011000 "OP_DCBF"
+  attribute \enum_value_0011001 "OP_DCBST"
+  attribute \enum_value_0011010 "OP_DCBT"
+  attribute \enum_value_0011011 "OP_DCBTST"
+  attribute \enum_value_0011100 "OP_DCBZ"
+  attribute \enum_value_0011101 "OP_DIV"
+  attribute \enum_value_0011110 "OP_DIVE"
+  attribute \enum_value_0011111 "OP_EXTS"
+  attribute \enum_value_0100000 "OP_EXTSWSLI"
+  attribute \enum_value_0100001 "OP_ICBI"
+  attribute \enum_value_0100010 "OP_ICBT"
+  attribute \enum_value_0100011 "OP_ISEL"
+  attribute \enum_value_0100100 "OP_ISYNC"
+  attribute \enum_value_0100101 "OP_LOAD"
+  attribute \enum_value_0100110 "OP_STORE"
+  attribute \enum_value_0100111 "OP_MADDHD"
+  attribute \enum_value_0101000 "OP_MADDHDU"
+  attribute \enum_value_0101001 "OP_MADDLD"
+  attribute \enum_value_0101010 "OP_MCRF"
+  attribute \enum_value_0101011 "OP_MCRXR"
+  attribute \enum_value_0101100 "OP_MCRXRX"
+  attribute \enum_value_0101101 "OP_MFCR"
+  attribute \enum_value_0101110 "OP_MFSPR"
+  attribute \enum_value_0101111 "OP_MOD"
+  attribute \enum_value_0110000 "OP_MTCRF"
+  attribute \enum_value_0110001 "OP_MTSPR"
+  attribute \enum_value_0110010 "OP_MUL_L64"
+  attribute \enum_value_0110011 "OP_MUL_H64"
+  attribute \enum_value_0110100 "OP_MUL_H32"
+  attribute \enum_value_0110101 "OP_OR"
+  attribute \enum_value_0110110 "OP_POPCNT"
+  attribute \enum_value_0110111 "OP_PRTY"
+  attribute \enum_value_0111000 "OP_RLC"
+  attribute \enum_value_0111001 "OP_RLCL"
+  attribute \enum_value_0111010 "OP_RLCR"
+  attribute \enum_value_0111011 "OP_SETB"
+  attribute \enum_value_0111100 "OP_SHL"
+  attribute \enum_value_0111101 "OP_SHR"
+  attribute \enum_value_0111110 "OP_SYNC"
+  attribute \enum_value_0111111 "OP_TRAP"
+  attribute \enum_value_1000011 "OP_XOR"
+  attribute \enum_value_1000100 "OP_SIM_CONFIG"
+  attribute \enum_value_1000101 "OP_CROP"
+  attribute \enum_value_1000110 "OP_RFID"
+  attribute \enum_value_1000111 "OP_MFMSR"
+  attribute \enum_value_1001000 "OP_MTMSRD"
+  attribute \enum_value_1001001 "OP_SC"
+  attribute \enum_value_1001010 "OP_MTMSR"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 input 10 \sr_op__insn_type
+  attribute \enum_base_type "Function"
+  attribute \enum_value_00000000000 "NONE"
+  attribute \enum_value_00000000010 "ALU"
+  attribute \enum_value_00000000100 "LDST"
+  attribute \enum_value_00000001000 "SHIFT_ROT"
+  attribute \enum_value_00000010000 "LOGICAL"
+  attribute \enum_value_00000100000 "BRANCH"
+  attribute \enum_value_00001000000 "CR"
+  attribute \enum_value_00010000000 "TRAP"
+  attribute \enum_value_00100000000 "MUL"
+  attribute \enum_value_01000000000 "DIV"
+  attribute \enum_value_10000000000 "SPR"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 input 11 \sr_op__fn_unit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 input 12 \sr_op__imm_data__imm
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 13 \sr_op__imm_data__imm_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 14 \sr_op__rc__rc
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 15 \sr_op__rc__rc_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 16 \sr_op__oe__oe
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 17 \sr_op__oe__oe_ok
+  attribute \enum_base_type "CryIn"
+  attribute \enum_value_00 "ZERO"
+  attribute \enum_value_01 "ONE"
+  attribute \enum_value_10 "CA"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 2 input 19 \sr_op__input_carry
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 20 \sr_op__output_carry
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 21 \sr_op__input_cr
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 22 \sr_op__output_cr
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 23 \sr_op__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 24 \sr_op__is_signed
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 input 25 \sr_op__insn
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
+  wire width 64 input 26 \ra
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
+  wire width 64 input 27 \rb
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
+  wire width 64 input 28 \rc
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
+  wire width 2 input 29 \xer_ca$1
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153"
+  wire width 1 input 30 \p_valid_i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154"
+  wire width 1 output 31 \p_ready_o
+  cell \p$104 \p
+    connect \p_valid_i \p_valid_i
+    connect \p_ready_o \p_ready_o
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  wire width 1 $5
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $6
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \wr_detect
-    connect \Y $5
+  cell \n$105 \n
+    connect \n_valid_o \n_valid_o
+    connect \n_ready_i \n_ready_i
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
-  wire width 64 \reg
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
-  wire width 64 \reg$next
-  process $group_1
-    assign \src10__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $3 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest10__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src10__data_o \dest10__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest20__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src10__data_o \dest20__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $5 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \src10__data_o \reg
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \src10__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153"
+  wire width 1 \pipe_p_valid_i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154"
+  wire width 1 \pipe_p_ready_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
+  wire width 2 \pipe_muxid
+  attribute \enum_base_type "MicrOp"
+  attribute \enum_value_0000000 "OP_ILLEGAL"
+  attribute \enum_value_0000001 "OP_NOP"
+  attribute \enum_value_0000010 "OP_ADD"
+  attribute \enum_value_0000011 "OP_ADDPCIS"
+  attribute \enum_value_0000100 "OP_AND"
+  attribute \enum_value_0000101 "OP_ATTN"
+  attribute \enum_value_0000110 "OP_B"
+  attribute \enum_value_0000111 "OP_BC"
+  attribute \enum_value_0001000 "OP_BCREG"
+  attribute \enum_value_0001001 "OP_BPERM"
+  attribute \enum_value_0001010 "OP_CMP"
+  attribute \enum_value_0001011 "OP_CMPB"
+  attribute \enum_value_0001100 "OP_CMPEQB"
+  attribute \enum_value_0001101 "OP_CMPRB"
+  attribute \enum_value_0001110 "OP_CNTZ"
+  attribute \enum_value_0001111 "OP_CRAND"
+  attribute \enum_value_0010000 "OP_CRANDC"
+  attribute \enum_value_0010001 "OP_CREQV"
+  attribute \enum_value_0010010 "OP_CRNAND"
+  attribute \enum_value_0010011 "OP_CRNOR"
+  attribute \enum_value_0010100 "OP_CROR"
+  attribute \enum_value_0010101 "OP_CRORC"
+  attribute \enum_value_0010110 "OP_CRXOR"
+  attribute \enum_value_0010111 "OP_DARN"
+  attribute \enum_value_0011000 "OP_DCBF"
+  attribute \enum_value_0011001 "OP_DCBST"
+  attribute \enum_value_0011010 "OP_DCBT"
+  attribute \enum_value_0011011 "OP_DCBTST"
+  attribute \enum_value_0011100 "OP_DCBZ"
+  attribute \enum_value_0011101 "OP_DIV"
+  attribute \enum_value_0011110 "OP_DIVE"
+  attribute \enum_value_0011111 "OP_EXTS"
+  attribute \enum_value_0100000 "OP_EXTSWSLI"
+  attribute \enum_value_0100001 "OP_ICBI"
+  attribute \enum_value_0100010 "OP_ICBT"
+  attribute \enum_value_0100011 "OP_ISEL"
+  attribute \enum_value_0100100 "OP_ISYNC"
+  attribute \enum_value_0100101 "OP_LOAD"
+  attribute \enum_value_0100110 "OP_STORE"
+  attribute \enum_value_0100111 "OP_MADDHD"
+  attribute \enum_value_0101000 "OP_MADDHDU"
+  attribute \enum_value_0101001 "OP_MADDLD"
+  attribute \enum_value_0101010 "OP_MCRF"
+  attribute \enum_value_0101011 "OP_MCRXR"
+  attribute \enum_value_0101100 "OP_MCRXRX"
+  attribute \enum_value_0101101 "OP_MFCR"
+  attribute \enum_value_0101110 "OP_MFSPR"
+  attribute \enum_value_0101111 "OP_MOD"
+  attribute \enum_value_0110000 "OP_MTCRF"
+  attribute \enum_value_0110001 "OP_MTSPR"
+  attribute \enum_value_0110010 "OP_MUL_L64"
+  attribute \enum_value_0110011 "OP_MUL_H64"
+  attribute \enum_value_0110100 "OP_MUL_H32"
+  attribute \enum_value_0110101 "OP_OR"
+  attribute \enum_value_0110110 "OP_POPCNT"
+  attribute \enum_value_0110111 "OP_PRTY"
+  attribute \enum_value_0111000 "OP_RLC"
+  attribute \enum_value_0111001 "OP_RLCL"
+  attribute \enum_value_0111010 "OP_RLCR"
+  attribute \enum_value_0111011 "OP_SETB"
+  attribute \enum_value_0111100 "OP_SHL"
+  attribute \enum_value_0111101 "OP_SHR"
+  attribute \enum_value_0111110 "OP_SYNC"
+  attribute \enum_value_0111111 "OP_TRAP"
+  attribute \enum_value_1000011 "OP_XOR"
+  attribute \enum_value_1000100 "OP_SIM_CONFIG"
+  attribute \enum_value_1000101 "OP_CROP"
+  attribute \enum_value_1000110 "OP_RFID"
+  attribute \enum_value_1000111 "OP_MFMSR"
+  attribute \enum_value_1001000 "OP_MTMSRD"
+  attribute \enum_value_1001001 "OP_SC"
+  attribute \enum_value_1001010 "OP_MTMSR"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 \pipe_sr_op__insn_type
+  attribute \enum_base_type "Function"
+  attribute \enum_value_00000000000 "NONE"
+  attribute \enum_value_00000000010 "ALU"
+  attribute \enum_value_00000000100 "LDST"
+  attribute \enum_value_00000001000 "SHIFT_ROT"
+  attribute \enum_value_00000010000 "LOGICAL"
+  attribute \enum_value_00000100000 "BRANCH"
+  attribute \enum_value_00001000000 "CR"
+  attribute \enum_value_00010000000 "TRAP"
+  attribute \enum_value_00100000000 "MUL"
+  attribute \enum_value_01000000000 "DIV"
+  attribute \enum_value_10000000000 "SPR"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 \pipe_sr_op__fn_unit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 \pipe_sr_op__imm_data__imm
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \pipe_sr_op__imm_data__imm_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \pipe_sr_op__rc__rc
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \pipe_sr_op__rc__rc_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \pipe_sr_op__oe__oe
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \pipe_sr_op__oe__oe_ok
+  attribute \enum_base_type "CryIn"
+  attribute \enum_value_00 "ZERO"
+  attribute \enum_value_01 "ONE"
+  attribute \enum_value_10 "CA"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 2 \pipe_sr_op__input_carry
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \pipe_sr_op__output_carry
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \pipe_sr_op__input_cr
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \pipe_sr_op__output_cr
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \pipe_sr_op__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \pipe_sr_op__is_signed
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \pipe_sr_op__insn
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
+  wire width 64 \pipe_ra
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
+  wire width 64 \pipe_rb
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
+  wire width 64 \pipe_rc
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
+  wire width 2 \pipe_xer_ca
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
+  wire width 1 \pipe_n_valid_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
+  wire width 1 \pipe_n_ready_i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
+  wire width 2 \pipe_muxid$2
+  attribute \enum_base_type "MicrOp"
+  attribute \enum_value_0000000 "OP_ILLEGAL"
+  attribute \enum_value_0000001 "OP_NOP"
+  attribute \enum_value_0000010 "OP_ADD"
+  attribute \enum_value_0000011 "OP_ADDPCIS"
+  attribute \enum_value_0000100 "OP_AND"
+  attribute \enum_value_0000101 "OP_ATTN"
+  attribute \enum_value_0000110 "OP_B"
+  attribute \enum_value_0000111 "OP_BC"
+  attribute \enum_value_0001000 "OP_BCREG"
+  attribute \enum_value_0001001 "OP_BPERM"
+  attribute \enum_value_0001010 "OP_CMP"
+  attribute \enum_value_0001011 "OP_CMPB"
+  attribute \enum_value_0001100 "OP_CMPEQB"
+  attribute \enum_value_0001101 "OP_CMPRB"
+  attribute \enum_value_0001110 "OP_CNTZ"
+  attribute \enum_value_0001111 "OP_CRAND"
+  attribute \enum_value_0010000 "OP_CRANDC"
+  attribute \enum_value_0010001 "OP_CREQV"
+  attribute \enum_value_0010010 "OP_CRNAND"
+  attribute \enum_value_0010011 "OP_CRNOR"
+  attribute \enum_value_0010100 "OP_CROR"
+  attribute \enum_value_0010101 "OP_CRORC"
+  attribute \enum_value_0010110 "OP_CRXOR"
+  attribute \enum_value_0010111 "OP_DARN"
+  attribute \enum_value_0011000 "OP_DCBF"
+  attribute \enum_value_0011001 "OP_DCBST"
+  attribute \enum_value_0011010 "OP_DCBT"
+  attribute \enum_value_0011011 "OP_DCBTST"
+  attribute \enum_value_0011100 "OP_DCBZ"
+  attribute \enum_value_0011101 "OP_DIV"
+  attribute \enum_value_0011110 "OP_DIVE"
+  attribute \enum_value_0011111 "OP_EXTS"
+  attribute \enum_value_0100000 "OP_EXTSWSLI"
+  attribute \enum_value_0100001 "OP_ICBI"
+  attribute \enum_value_0100010 "OP_ICBT"
+  attribute \enum_value_0100011 "OP_ISEL"
+  attribute \enum_value_0100100 "OP_ISYNC"
+  attribute \enum_value_0100101 "OP_LOAD"
+  attribute \enum_value_0100110 "OP_STORE"
+  attribute \enum_value_0100111 "OP_MADDHD"
+  attribute \enum_value_0101000 "OP_MADDHDU"
+  attribute \enum_value_0101001 "OP_MADDLD"
+  attribute \enum_value_0101010 "OP_MCRF"
+  attribute \enum_value_0101011 "OP_MCRXR"
+  attribute \enum_value_0101100 "OP_MCRXRX"
+  attribute \enum_value_0101101 "OP_MFCR"
+  attribute \enum_value_0101110 "OP_MFSPR"
+  attribute \enum_value_0101111 "OP_MOD"
+  attribute \enum_value_0110000 "OP_MTCRF"
+  attribute \enum_value_0110001 "OP_MTSPR"
+  attribute \enum_value_0110010 "OP_MUL_L64"
+  attribute \enum_value_0110011 "OP_MUL_H64"
+  attribute \enum_value_0110100 "OP_MUL_H32"
+  attribute \enum_value_0110101 "OP_OR"
+  attribute \enum_value_0110110 "OP_POPCNT"
+  attribute \enum_value_0110111 "OP_PRTY"
+  attribute \enum_value_0111000 "OP_RLC"
+  attribute \enum_value_0111001 "OP_RLCL"
+  attribute \enum_value_0111010 "OP_RLCR"
+  attribute \enum_value_0111011 "OP_SETB"
+  attribute \enum_value_0111100 "OP_SHL"
+  attribute \enum_value_0111101 "OP_SHR"
+  attribute \enum_value_0111110 "OP_SYNC"
+  attribute \enum_value_0111111 "OP_TRAP"
+  attribute \enum_value_1000011 "OP_XOR"
+  attribute \enum_value_1000100 "OP_SIM_CONFIG"
+  attribute \enum_value_1000101 "OP_CROP"
+  attribute \enum_value_1000110 "OP_RFID"
+  attribute \enum_value_1000111 "OP_MFMSR"
+  attribute \enum_value_1001000 "OP_MTMSRD"
+  attribute \enum_value_1001001 "OP_SC"
+  attribute \enum_value_1001010 "OP_MTMSR"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 \pipe_sr_op__insn_type$3
+  attribute \enum_base_type "Function"
+  attribute \enum_value_00000000000 "NONE"
+  attribute \enum_value_00000000010 "ALU"
+  attribute \enum_value_00000000100 "LDST"
+  attribute \enum_value_00000001000 "SHIFT_ROT"
+  attribute \enum_value_00000010000 "LOGICAL"
+  attribute \enum_value_00000100000 "BRANCH"
+  attribute \enum_value_00001000000 "CR"
+  attribute \enum_value_00010000000 "TRAP"
+  attribute \enum_value_00100000000 "MUL"
+  attribute \enum_value_01000000000 "DIV"
+  attribute \enum_value_10000000000 "SPR"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 \pipe_sr_op__fn_unit$4
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 \pipe_sr_op__imm_data__imm$5
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \pipe_sr_op__imm_data__imm_ok$6
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \pipe_sr_op__rc__rc$7
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \pipe_sr_op__rc__rc_ok$8
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \pipe_sr_op__oe__oe$9
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \pipe_sr_op__oe__oe_ok$10
+  attribute \enum_base_type "CryIn"
+  attribute \enum_value_00 "ZERO"
+  attribute \enum_value_01 "ONE"
+  attribute \enum_value_10 "CA"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 2 \pipe_sr_op__input_carry$11
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \pipe_sr_op__output_carry$12
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \pipe_sr_op__input_cr$13
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \pipe_sr_op__output_cr$14
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \pipe_sr_op__is_32bit$15
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \pipe_sr_op__is_signed$16
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \pipe_sr_op__insn$17
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 64 \pipe_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 \pipe_o_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 4 \pipe_cr_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 \pipe_cr_a_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 2 \pipe_xer_ca$18
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 \pipe_xer_ca_ok
+  cell \pipe$106 \pipe
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
+    connect \p_valid_i \pipe_p_valid_i
+    connect \p_ready_o \pipe_p_ready_o
+    connect \muxid \pipe_muxid
+    connect \sr_op__insn_type \pipe_sr_op__insn_type
+    connect \sr_op__fn_unit \pipe_sr_op__fn_unit
+    connect \sr_op__imm_data__imm \pipe_sr_op__imm_data__imm
+    connect \sr_op__imm_data__imm_ok \pipe_sr_op__imm_data__imm_ok
+    connect \sr_op__rc__rc \pipe_sr_op__rc__rc
+    connect \sr_op__rc__rc_ok \pipe_sr_op__rc__rc_ok
+    connect \sr_op__oe__oe \pipe_sr_op__oe__oe
+    connect \sr_op__oe__oe_ok \pipe_sr_op__oe__oe_ok
+    connect \sr_op__input_carry \pipe_sr_op__input_carry
+    connect \sr_op__output_carry \pipe_sr_op__output_carry
+    connect \sr_op__input_cr \pipe_sr_op__input_cr
+    connect \sr_op__output_cr \pipe_sr_op__output_cr
+    connect \sr_op__is_32bit \pipe_sr_op__is_32bit
+    connect \sr_op__is_signed \pipe_sr_op__is_signed
+    connect \sr_op__insn \pipe_sr_op__insn
+    connect \ra \pipe_ra
+    connect \rb \pipe_rb
+    connect \rc \pipe_rc
+    connect \xer_ca \pipe_xer_ca
+    connect \n_valid_o \pipe_n_valid_o
+    connect \n_ready_i \pipe_n_ready_i
+    connect \muxid$1 \pipe_muxid$2
+    connect \sr_op__insn_type$2 \pipe_sr_op__insn_type$3
+    connect \sr_op__fn_unit$3 \pipe_sr_op__fn_unit$4
+    connect \sr_op__imm_data__imm$4 \pipe_sr_op__imm_data__imm$5
+    connect \sr_op__imm_data__imm_ok$5 \pipe_sr_op__imm_data__imm_ok$6
+    connect \sr_op__rc__rc$6 \pipe_sr_op__rc__rc$7
+    connect \sr_op__rc__rc_ok$7 \pipe_sr_op__rc__rc_ok$8
+    connect \sr_op__oe__oe$8 \pipe_sr_op__oe__oe$9
+    connect \sr_op__oe__oe_ok$9 \pipe_sr_op__oe__oe_ok$10
+    connect \sr_op__input_carry$10 \pipe_sr_op__input_carry$11
+    connect \sr_op__output_carry$11 \pipe_sr_op__output_carry$12
+    connect \sr_op__input_cr$12 \pipe_sr_op__input_cr$13
+    connect \sr_op__output_cr$13 \pipe_sr_op__output_cr$14
+    connect \sr_op__is_32bit$14 \pipe_sr_op__is_32bit$15
+    connect \sr_op__is_signed$15 \pipe_sr_op__is_signed$16
+    connect \sr_op__insn$16 \pipe_sr_op__insn$17
+    connect \o \pipe_o
+    connect \o_ok \pipe_o_ok
+    connect \cr_a \pipe_cr_a
+    connect \cr_a_ok \pipe_cr_a_ok
+    connect \xer_ca$17 \pipe_xer_ca$18
+    connect \xer_ca_ok \pipe_xer_ca_ok
+  end
+  process $group_0
+    assign \pipe_p_valid_i 1'0
+    assign \pipe_p_valid_i \p_valid_i
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect$7
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $8
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $9
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \src20__ren
-    connect \B 1'1
-    connect \Y $8
+  process $group_1
+    assign \p_ready_o 1'0
+    assign \p_ready_o \pipe_p_ready_o
+    sync init
   end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
+  wire width 2 \muxid
   process $group_2
-    assign \wr_detect$7 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $8 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        assign \wr_detect$7 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest10__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$7 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest20__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$7 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-    end
+    assign \pipe_muxid 2'00
+    assign \pipe_muxid \muxid
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $10
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $11
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \src20__ren
-    connect \B 1'1
-    connect \Y $10
+  process $group_3
+    assign \pipe_sr_op__insn_type 7'0000000
+    assign \pipe_sr_op__fn_unit 11'00000000000
+    assign \pipe_sr_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \pipe_sr_op__imm_data__imm_ok 1'0
+    assign \pipe_sr_op__rc__rc 1'0
+    assign \pipe_sr_op__rc__rc_ok 1'0
+    assign \pipe_sr_op__oe__oe 1'0
+    assign \pipe_sr_op__oe__oe_ok 1'0
+    assign { } 0'0
+    assign \pipe_sr_op__input_carry 2'00
+    assign \pipe_sr_op__output_carry 1'0
+    assign \pipe_sr_op__input_cr 1'0
+    assign \pipe_sr_op__output_cr 1'0
+    assign \pipe_sr_op__is_32bit 1'0
+    assign \pipe_sr_op__is_signed 1'0
+    assign \pipe_sr_op__insn 32'00000000000000000000000000000000
+    assign { \pipe_sr_op__insn \pipe_sr_op__is_signed \pipe_sr_op__is_32bit \pipe_sr_op__output_cr \pipe_sr_op__input_cr \pipe_sr_op__output_carry \pipe_sr_op__input_carry { } { \pipe_sr_op__oe__oe_ok \pipe_sr_op__oe__oe } { \pipe_sr_op__rc__rc_ok \pipe_sr_op__rc__rc } { \pipe_sr_op__imm_data__imm_ok \pipe_sr_op__imm_data__imm } \pipe_sr_op__fn_unit \pipe_sr_op__insn_type } { \sr_op__insn \sr_op__is_signed \sr_op__is_32bit \sr_op__output_cr \sr_op__input_cr \sr_op__output_carry \sr_op__input_carry { } { \sr_op__oe__oe_ok \sr_op__oe__oe } { \sr_op__rc__rc_ok \sr_op__rc__rc } { \sr_op__imm_data__imm_ok \sr_op__imm_data__imm } \sr_op__fn_unit \sr_op__insn_type }
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  wire width 1 $12
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $13
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \wr_detect$7
-    connect \Y $12
+  process $group_19
+    assign \pipe_ra 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \pipe_ra \ra
+    sync init
   end
-  process $group_3
-    assign \src20__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $10 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest10__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src20__data_o \dest10__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest20__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src20__data_o \dest20__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $12 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \src20__data_o \reg
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \src20__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
+  process $group_20
+    assign \pipe_rb 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \pipe_rb \rb
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect$14
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $15
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $16
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \src30__ren
-    connect \B 1'1
-    connect \Y $15
+  process $group_21
+    assign \pipe_rc 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \pipe_rc \rc
+    sync init
   end
-  process $group_4
-    assign \wr_detect$14 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $15 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        assign \wr_detect$14 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest10__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$14 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest20__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$14 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-    end
+  process $group_22
+    assign \pipe_xer_ca 2'00
+    assign \pipe_xer_ca \xer_ca$1
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $17
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $18
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \src30__ren
-    connect \B 1'1
-    connect \Y $17
+  process $group_23
+    assign \n_valid_o 1'0
+    assign \n_valid_o \pipe_n_valid_o
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  wire width 1 $19
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $20
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \wr_detect$14
-    connect \Y $19
+  process $group_24
+    assign \pipe_n_ready_i 1'0
+    assign \pipe_n_ready_i \n_ready_i
+    sync init
   end
-  process $group_5
-    assign \src30__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $17 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest10__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src30__data_o \dest10__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest20__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src30__data_o \dest20__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $19 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \src30__data_o \reg
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \src30__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35"
+  wire width 2 \muxid$19
+  process $group_25
+    assign \muxid$19 2'00
+    assign \muxid$19 \pipe_muxid$2
     sync init
   end
-  process $group_6
-    assign \reg$next \reg
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-    switch { \dest10__wen }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-      case 1'1
-        assign \reg$next \dest10__data_i
-    end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-    switch { \dest20__wen }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-      case 1'1
-        assign \reg$next \dest20__data_i
-    end
+  attribute \enum_base_type "MicrOp"
+  attribute \enum_value_0000000 "OP_ILLEGAL"
+  attribute \enum_value_0000001 "OP_NOP"
+  attribute \enum_value_0000010 "OP_ADD"
+  attribute \enum_value_0000011 "OP_ADDPCIS"
+  attribute \enum_value_0000100 "OP_AND"
+  attribute \enum_value_0000101 "OP_ATTN"
+  attribute \enum_value_0000110 "OP_B"
+  attribute \enum_value_0000111 "OP_BC"
+  attribute \enum_value_0001000 "OP_BCREG"
+  attribute \enum_value_0001001 "OP_BPERM"
+  attribute \enum_value_0001010 "OP_CMP"
+  attribute \enum_value_0001011 "OP_CMPB"
+  attribute \enum_value_0001100 "OP_CMPEQB"
+  attribute \enum_value_0001101 "OP_CMPRB"
+  attribute \enum_value_0001110 "OP_CNTZ"
+  attribute \enum_value_0001111 "OP_CRAND"
+  attribute \enum_value_0010000 "OP_CRANDC"
+  attribute \enum_value_0010001 "OP_CREQV"
+  attribute \enum_value_0010010 "OP_CRNAND"
+  attribute \enum_value_0010011 "OP_CRNOR"
+  attribute \enum_value_0010100 "OP_CROR"
+  attribute \enum_value_0010101 "OP_CRORC"
+  attribute \enum_value_0010110 "OP_CRXOR"
+  attribute \enum_value_0010111 "OP_DARN"
+  attribute \enum_value_0011000 "OP_DCBF"
+  attribute \enum_value_0011001 "OP_DCBST"
+  attribute \enum_value_0011010 "OP_DCBT"
+  attribute \enum_value_0011011 "OP_DCBTST"
+  attribute \enum_value_0011100 "OP_DCBZ"
+  attribute \enum_value_0011101 "OP_DIV"
+  attribute \enum_value_0011110 "OP_DIVE"
+  attribute \enum_value_0011111 "OP_EXTS"
+  attribute \enum_value_0100000 "OP_EXTSWSLI"
+  attribute \enum_value_0100001 "OP_ICBI"
+  attribute \enum_value_0100010 "OP_ICBT"
+  attribute \enum_value_0100011 "OP_ISEL"
+  attribute \enum_value_0100100 "OP_ISYNC"
+  attribute \enum_value_0100101 "OP_LOAD"
+  attribute \enum_value_0100110 "OP_STORE"
+  attribute \enum_value_0100111 "OP_MADDHD"
+  attribute \enum_value_0101000 "OP_MADDHDU"
+  attribute \enum_value_0101001 "OP_MADDLD"
+  attribute \enum_value_0101010 "OP_MCRF"
+  attribute \enum_value_0101011 "OP_MCRXR"
+  attribute \enum_value_0101100 "OP_MCRXRX"
+  attribute \enum_value_0101101 "OP_MFCR"
+  attribute \enum_value_0101110 "OP_MFSPR"
+  attribute \enum_value_0101111 "OP_MOD"
+  attribute \enum_value_0110000 "OP_MTCRF"
+  attribute \enum_value_0110001 "OP_MTSPR"
+  attribute \enum_value_0110010 "OP_MUL_L64"
+  attribute \enum_value_0110011 "OP_MUL_H64"
+  attribute \enum_value_0110100 "OP_MUL_H32"
+  attribute \enum_value_0110101 "OP_OR"
+  attribute \enum_value_0110110 "OP_POPCNT"
+  attribute \enum_value_0110111 "OP_PRTY"
+  attribute \enum_value_0111000 "OP_RLC"
+  attribute \enum_value_0111001 "OP_RLCL"
+  attribute \enum_value_0111010 "OP_RLCR"
+  attribute \enum_value_0111011 "OP_SETB"
+  attribute \enum_value_0111100 "OP_SHL"
+  attribute \enum_value_0111101 "OP_SHR"
+  attribute \enum_value_0111110 "OP_SYNC"
+  attribute \enum_value_0111111 "OP_TRAP"
+  attribute \enum_value_1000011 "OP_XOR"
+  attribute \enum_value_1000100 "OP_SIM_CONFIG"
+  attribute \enum_value_1000101 "OP_CROP"
+  attribute \enum_value_1000110 "OP_RFID"
+  attribute \enum_value_1000111 "OP_MFMSR"
+  attribute \enum_value_1001000 "OP_MTMSRD"
+  attribute \enum_value_1001001 "OP_SC"
+  attribute \enum_value_1001010 "OP_MTMSR"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 \sr_op__insn_type$20
+  attribute \enum_base_type "Function"
+  attribute \enum_value_00000000000 "NONE"
+  attribute \enum_value_00000000010 "ALU"
+  attribute \enum_value_00000000100 "LDST"
+  attribute \enum_value_00000001000 "SHIFT_ROT"
+  attribute \enum_value_00000010000 "LOGICAL"
+  attribute \enum_value_00000100000 "BRANCH"
+  attribute \enum_value_00001000000 "CR"
+  attribute \enum_value_00010000000 "TRAP"
+  attribute \enum_value_00100000000 "MUL"
+  attribute \enum_value_01000000000 "DIV"
+  attribute \enum_value_10000000000 "SPR"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 \sr_op__fn_unit$21
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 \sr_op__imm_data__imm$22
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \sr_op__imm_data__imm_ok$23
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \sr_op__rc__rc$24
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \sr_op__rc__rc_ok$25
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \sr_op__oe__oe$26
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \sr_op__oe__oe_ok$27
+  attribute \enum_base_type "CryIn"
+  attribute \enum_value_00 "ZERO"
+  attribute \enum_value_01 "ONE"
+  attribute \enum_value_10 "CA"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 2 \sr_op__input_carry$28
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \sr_op__output_carry$29
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \sr_op__input_cr$30
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \sr_op__output_cr$31
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \sr_op__is_32bit$32
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \sr_op__is_signed$33
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \sr_op__insn$34
+  process $group_26
+    assign \sr_op__insn_type$20 7'0000000
+    assign \sr_op__fn_unit$21 11'00000000000
+    assign \sr_op__imm_data__imm$22 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \sr_op__imm_data__imm_ok$23 1'0
+    assign \sr_op__rc__rc$24 1'0
+    assign \sr_op__rc__rc_ok$25 1'0
+    assign \sr_op__oe__oe$26 1'0
+    assign \sr_op__oe__oe_ok$27 1'0
+    assign { } 0'0
+    assign \sr_op__input_carry$28 2'00
+    assign \sr_op__output_carry$29 1'0
+    assign \sr_op__input_cr$30 1'0
+    assign \sr_op__output_cr$31 1'0
+    assign \sr_op__is_32bit$32 1'0
+    assign \sr_op__is_signed$33 1'0
+    assign \sr_op__insn$34 32'00000000000000000000000000000000
+    assign { \sr_op__insn$34 \sr_op__is_signed$33 \sr_op__is_32bit$32 \sr_op__output_cr$31 \sr_op__input_cr$30 \sr_op__output_carry$29 \sr_op__input_carry$28 { } { \sr_op__oe__oe_ok$27 \sr_op__oe__oe$26 } { \sr_op__rc__rc_ok$25 \sr_op__rc__rc$24 } { \sr_op__imm_data__imm_ok$23 \sr_op__imm_data__imm$22 } \sr_op__fn_unit$21 \sr_op__insn_type$20 } { \pipe_sr_op__insn$17 \pipe_sr_op__is_signed$16 \pipe_sr_op__is_32bit$15 \pipe_sr_op__output_cr$14 \pipe_sr_op__input_cr$13 \pipe_sr_op__output_carry$12 \pipe_sr_op__input_carry$11 { } { \pipe_sr_op__oe__oe_ok$10 \pipe_sr_op__oe__oe$9 } { \pipe_sr_op__rc__rc_ok$8 \pipe_sr_op__rc__rc$7 } { \pipe_sr_op__imm_data__imm_ok$6 \pipe_sr_op__imm_data__imm$5 } \pipe_sr_op__fn_unit$4 \pipe_sr_op__insn_type$3 }
+    sync init
+  end
+  process $group_42
+    assign \o 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \o_ok 1'0
+    assign { \o_ok \o } { \pipe_o_ok \pipe_o }
+    sync init
+  end
+  process $group_44
+    assign \cr_a 4'0000
+    assign \cr_a_ok 1'0
+    assign { \cr_a_ok \cr_a } { \pipe_cr_a_ok \pipe_cr_a }
+    sync init
+  end
+  process $group_46
+    assign \xer_ca 2'00
+    assign \xer_ca_ok 1'0
+    assign { \xer_ca_ok \xer_ca } { \pipe_xer_ca_ok \pipe_xer_ca$18 }
+    sync init
+  end
+  connect \muxid 2'00
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.src_l"
+module \src_l$112
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+  wire width 4 input 2 \s_src
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+  wire width 4 input 3 \r_src
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
+  wire width 4 output 4 \q_src
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
+  wire width 4 \q_int
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
+  wire width 4 \q_int$next
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  wire width 4 $1
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  cell $not $2
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 4
+    parameter \Y_WIDTH 4
+    connect \A \r_src
+    connect \Y $1
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  wire width 4 $3
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  cell $and $4
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 4
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 4
+    parameter \Y_WIDTH 4
+    connect \A \q_int
+    connect \B $1
+    connect \Y $3
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  wire width 4 $5
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  cell $or $6
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 4
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 4
+    parameter \Y_WIDTH 4
+    connect \A $3
+    connect \B \s_src
+    connect \Y $5
+  end
+  process $group_0
+    assign \q_int$next \q_int
+    assign \q_int$next $5
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
-        assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
+        assign \q_int$next 4'0000
     end
     sync init
-      update \reg 64'0000000000000000000000000000000000000000000000000000000000000000
-    sync posedge \clk
-      update \reg \reg$next
+      update \q_int 4'0000
+    sync posedge \coresync_clk
+      update \q_int \q_int$next
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  wire width 4 $7
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  cell $not $8
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 4
+    parameter \Y_WIDTH 4
+    connect \A \r_src
+    connect \Y $7
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  wire width 4 $9
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  cell $and $10
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 4
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 4
+    parameter \Y_WIDTH 4
+    connect \A \q_int
+    connect \B $7
+    connect \Y $9
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  wire width 4 $11
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  cell $or $12
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 4
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 4
+    parameter \Y_WIDTH 4
+    connect \A $9
+    connect \B \s_src
+    connect \Y $11
+  end
+  process $group_1
+    assign \q_src 4'0000
+    assign \q_src $11
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
+  wire width 4 \qn_src
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
+  wire width 4 $13
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
+  cell $not $14
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 4
+    parameter \Y_WIDTH 4
+    connect \A \q_src
+    connect \Y $13
+  end
+  process $group_2
+    assign \qn_src 4'0000
+    assign \qn_src $13
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62"
+  wire width 4 \qlq_src
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
+  wire width 4 $15
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
+  cell $or $16
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 4
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 4
+    parameter \Y_WIDTH 4
+    connect \A \q_src
+    connect \B \q_int
+    connect \Y $15
+  end
+  process $group_3
+    assign \qlq_src 4'0000
+    assign \qlq_src $15
+    sync init
   end
 end
 attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.int.reg_1"
-module \reg_1
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 2 \src11__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 3 \src11__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 4 \src21__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 5 \src21__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 6 \src31__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 7 \src31__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 8 \dest11__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 9 \dest11__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 10 \dest21__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 11 \dest21__data_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.opc_l"
+module \opc_l$113
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+  wire width 1 input 2 \s_opc
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+  wire width 1 input 3 \r_opc
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
+  wire width 1 output 4 \q_opc
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
+  wire width 1 \q_int
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
+  wire width 1 \q_int$next
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
   wire width 1 $1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $2
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  cell $not $2
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src11__ren
-    connect \B 1'1
+    connect \A \r_opc
     connect \Y $1
   end
-  process $group_0
-    assign \wr_detect 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $1 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        assign \wr_detect 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest11__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest21__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-    end
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
   wire width 1 $3
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $4
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  cell $and $4
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src11__ren
-    connect \B 1'1
+    connect \A \q_int
+    connect \B $1
     connect \Y $3
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
   wire width 1 $5
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $6
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  cell $or $6
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr_detect
+    connect \A $3
+    connect \B \s_opc
     connect \Y $5
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
-  wire width 64 \reg
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
-  wire width 64 \reg$next
-  process $group_1
-    assign \src11__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $3 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  process $group_0
+    assign \q_int$next \q_int
+    assign \q_int$next $5
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest11__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src11__data_o \dest11__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest21__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src11__data_o \dest21__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $5 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \src11__data_o \reg
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \src11__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+        assign \q_int$next 1'0
     end
     sync init
+      update \q_int 1'0
+    sync posedge \coresync_clk
+      update \q_int \q_int$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect$7
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $8
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $9
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  wire width 1 $7
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  cell $not $8
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \r_opc
+    connect \Y $7
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  wire width 1 $9
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  cell $and $10
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src21__ren
-    connect \B 1'1
-    connect \Y $8
+    connect \A \q_int
+    connect \B $7
+    connect \Y $9
   end
-  process $group_2
-    assign \wr_detect$7 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $8 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        assign \wr_detect$7 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest11__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$7 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest21__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$7 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-    end
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $10
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $11
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  wire width 1 $11
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  cell $or $12
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src21__ren
-    connect \B 1'1
-    connect \Y $10
+    connect \A $9
+    connect \B \s_opc
+    connect \Y $11
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  wire width 1 $12
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $13
+  process $group_1
+    assign \q_opc 1'0
+    assign \q_opc $11
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
+  wire width 1 \qn_opc
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
+  wire width 1 $13
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
+  cell $not $14
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr_detect$7
-    connect \Y $12
+    connect \A \q_opc
+    connect \Y $13
   end
-  process $group_3
-    assign \src21__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $10 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest11__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src21__data_o \dest11__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest21__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src21__data_o \dest21__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $12 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \src21__data_o \reg
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \src21__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
+  process $group_2
+    assign \qn_opc 1'0
+    assign \qn_opc $13
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect$14
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62"
+  wire width 1 \qlq_opc
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
   wire width 1 $15
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $16
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
+  cell $or $16
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src31__ren
-    connect \B 1'1
+    connect \A \q_opc
+    connect \B \q_int
     connect \Y $15
   end
-  process $group_4
-    assign \wr_detect$14 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $15 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        assign \wr_detect$14 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest11__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$14 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest21__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$14 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-    end
+  process $group_3
+    assign \qlq_opc 1'0
+    assign \qlq_opc $15
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $17
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $18
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.req_l"
+module \req_l$114
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
+  wire width 3 output 2 \q_req
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+  wire width 3 input 3 \s_req
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+  wire width 3 input 4 \r_req
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
+  wire width 3 \q_int
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
+  wire width 3 \q_int$next
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  wire width 3 $1
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  cell $not $2
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
+    parameter \A_WIDTH 3
+    parameter \Y_WIDTH 3
+    connect \A \r_req
+    connect \Y $1
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  wire width 3 $3
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  cell $and $4
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 3
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \src31__ren
-    connect \B 1'1
-    connect \Y $17
+    parameter \B_WIDTH 3
+    parameter \Y_WIDTH 3
+    connect \A \q_int
+    connect \B $1
+    connect \Y $3
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  wire width 1 $19
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $20
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  wire width 3 $5
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  cell $or $6
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \wr_detect$14
-    connect \Y $19
+    parameter \A_WIDTH 3
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 3
+    parameter \Y_WIDTH 3
+    connect \A $3
+    connect \B \s_req
+    connect \Y $5
   end
-  process $group_5
-    assign \src31__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $17 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  process $group_0
+    assign \q_int$next \q_int
+    assign \q_int$next $5
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest11__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src31__data_o \dest11__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest21__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src31__data_o \dest21__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $19 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \src31__data_o \reg
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \src31__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+        assign \q_int$next 3'000
     end
     sync init
+      update \q_int 3'000
+    sync posedge \coresync_clk
+      update \q_int \q_int$next
   end
-  process $group_6
-    assign \reg$next \reg
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-    switch { \dest11__wen }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-      case 1'1
-        assign \reg$next \dest11__data_i
-    end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-    switch { \dest21__wen }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-      case 1'1
-        assign \reg$next \dest21__data_i
-    end
-    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
-      case 1'1
-        assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  wire width 3 $7
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  cell $not $8
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 3
+    parameter \Y_WIDTH 3
+    connect \A \r_req
+    connect \Y $7
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  wire width 3 $9
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  cell $and $10
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 3
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 3
+    parameter \Y_WIDTH 3
+    connect \A \q_int
+    connect \B $7
+    connect \Y $9
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  wire width 3 $11
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  cell $or $12
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 3
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 3
+    parameter \Y_WIDTH 3
+    connect \A $9
+    connect \B \s_req
+    connect \Y $11
+  end
+  process $group_1
+    assign \q_req 3'000
+    assign \q_req $11
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
+  wire width 3 \qn_req
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
+  wire width 3 $13
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
+  cell $not $14
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 3
+    parameter \Y_WIDTH 3
+    connect \A \q_req
+    connect \Y $13
+  end
+  process $group_2
+    assign \qn_req 3'000
+    assign \qn_req $13
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62"
+  wire width 3 \qlq_req
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
+  wire width 3 $15
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
+  cell $or $16
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 3
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 3
+    parameter \Y_WIDTH 3
+    connect \A \q_req
+    connect \B \q_int
+    connect \Y $15
+  end
+  process $group_3
+    assign \qlq_req 3'000
+    assign \qlq_req $15
     sync init
-      update \reg 64'0000000000000000000000000000000000000000000000000000000000000000
-    sync posedge \clk
-      update \reg \reg$next
   end
 end
 attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.int.reg_2"
-module \reg_2
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 2 \src12__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 3 \src12__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 4 \src22__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 5 \src22__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 6 \src32__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 7 \src32__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 8 \dest12__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 9 \dest12__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 10 \dest22__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 11 \dest22__data_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.rst_l"
+module \rst_l$115
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+  wire width 1 input 2 \s_rst
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+  wire width 1 input 3 \r_rst
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
+  wire width 1 \q_int
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
+  wire width 1 \q_int$next
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
   wire width 1 $1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $2
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  cell $not $2
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src12__ren
-    connect \B 1'1
+    connect \A \r_rst
     connect \Y $1
   end
-  process $group_0
-    assign \wr_detect 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $1 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        assign \wr_detect 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest12__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest22__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-    end
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
   wire width 1 $3
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $4
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  cell $and $4
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src12__ren
-    connect \B 1'1
+    connect \A \q_int
+    connect \B $1
     connect \Y $3
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
   wire width 1 $5
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $6
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  cell $or $6
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr_detect
+    connect \A $3
+    connect \B \s_rst
     connect \Y $5
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
-  wire width 64 \reg
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
-  wire width 64 \reg$next
-  process $group_1
-    assign \src12__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $3 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  process $group_0
+    assign \q_int$next \q_int
+    assign \q_int$next $5
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest12__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src12__data_o \dest12__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest22__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src12__data_o \dest22__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $5 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \src12__data_o \reg
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \src12__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+        assign \q_int$next 1'0
     end
     sync init
+      update \q_int 1'0
+    sync posedge \coresync_clk
+      update \q_int \q_int$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect$7
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $8
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $9
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
+  wire width 1 \q_rst
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  wire width 1 $7
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  cell $not $8
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src22__ren
-    connect \B 1'1
-    connect \Y $8
-  end
-  process $group_2
-    assign \wr_detect$7 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $8 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        assign \wr_detect$7 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest12__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$7 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest22__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$7 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-    end
-    sync init
+    connect \A \r_rst
+    connect \Y $7
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $10
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $11
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  wire width 1 $9
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  cell $and $10
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src22__ren
-    connect \B 1'1
-    connect \Y $10
+    connect \A \q_int
+    connect \B $7
+    connect \Y $9
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  wire width 1 $12
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $13
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  wire width 1 $11
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  cell $or $12
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr_detect$7
-    connect \Y $12
+    connect \A $9
+    connect \B \s_rst
+    connect \Y $11
   end
-  process $group_3
-    assign \src22__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $10 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest12__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src22__data_o \dest12__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest22__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src22__data_o \dest22__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $12 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \src22__data_o \reg
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \src22__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
+  process $group_1
+    assign \q_rst 1'0
+    assign \q_rst $11
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect$14
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $15
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $16
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
+  wire width 1 \qn_rst
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
+  wire width 1 $13
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
+  cell $not $14
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src32__ren
-    connect \B 1'1
-    connect \Y $15
+    connect \A \q_rst
+    connect \Y $13
   end
-  process $group_4
-    assign \wr_detect$14 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $15 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        assign \wr_detect$14 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest12__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$14 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest22__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$14 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-    end
+  process $group_2
+    assign \qn_rst 1'0
+    assign \qn_rst $13
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $17
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $18
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62"
+  wire width 1 \qlq_rst
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
+  wire width 1 $15
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
+  cell $or $16
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src32__ren
-    connect \B 1'1
-    connect \Y $17
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  wire width 1 $19
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $20
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \wr_detect$14
-    connect \Y $19
-  end
-  process $group_5
-    assign \src32__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $17 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest12__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src32__data_o \dest12__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest22__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src32__data_o \dest22__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $19 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \src32__data_o \reg
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \src32__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
-    sync init
+    connect \A \q_rst
+    connect \B \q_int
+    connect \Y $15
   end
-  process $group_6
-    assign \reg$next \reg
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-    switch { \dest12__wen }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-      case 1'1
-        assign \reg$next \dest12__data_i
-    end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-    switch { \dest22__wen }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-      case 1'1
-        assign \reg$next \dest22__data_i
-    end
-    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
-      case 1'1
-        assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
+  process $group_3
+    assign \qlq_rst 1'0
+    assign \qlq_rst $15
     sync init
-      update \reg 64'0000000000000000000000000000000000000000000000000000000000000000
-    sync posedge \clk
-      update \reg \reg$next
   end
 end
 attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.int.reg_3"
-module \reg_3
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 2 \src13__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 3 \src13__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 4 \src23__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 5 \src23__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 6 \src33__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 7 \src33__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 8 \dest13__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 9 \dest13__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 10 \dest23__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 11 \dest23__data_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.rok_l"
+module \rok_l$116
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
+  wire width 1 output 2 \q_rdok
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+  wire width 1 input 3 \s_rdok
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+  wire width 1 input 4 \r_rdok
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
+  wire width 1 \q_int
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
+  wire width 1 \q_int$next
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
   wire width 1 $1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $2
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  cell $not $2
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src13__ren
-    connect \B 1'1
+    connect \A \r_rdok
     connect \Y $1
   end
-  process $group_0
-    assign \wr_detect 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $1 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        assign \wr_detect 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest13__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest23__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-    end
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
   wire width 1 $3
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $4
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  cell $and $4
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src13__ren
-    connect \B 1'1
+    connect \A \q_int
+    connect \B $1
     connect \Y $3
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
   wire width 1 $5
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $6
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  cell $or $6
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr_detect
+    connect \A $3
+    connect \B \s_rdok
     connect \Y $5
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
-  wire width 64 \reg
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
-  wire width 64 \reg$next
-  process $group_1
-    assign \src13__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $3 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  process $group_0
+    assign \q_int$next \q_int
+    assign \q_int$next $5
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest13__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src13__data_o \dest13__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest23__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src13__data_o \dest23__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $5 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \src13__data_o \reg
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \src13__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+        assign \q_int$next 1'0
     end
     sync init
+      update \q_int 1'0
+    sync posedge \coresync_clk
+      update \q_int \q_int$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect$7
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $8
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $9
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  wire width 1 $7
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  cell $not $8
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \r_rdok
+    connect \Y $7
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  wire width 1 $9
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  cell $and $10
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src23__ren
-    connect \B 1'1
-    connect \Y $8
-  end
-  process $group_2
-    assign \wr_detect$7 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $8 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        assign \wr_detect$7 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest13__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$7 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest23__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$7 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-    end
-    sync init
+    connect \A \q_int
+    connect \B $7
+    connect \Y $9
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $10
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $11
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  wire width 1 $11
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  cell $or $12
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src23__ren
-    connect \B 1'1
-    connect \Y $10
+    connect \A $9
+    connect \B \s_rdok
+    connect \Y $11
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  wire width 1 $12
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $13
+  process $group_1
+    assign \q_rdok 1'0
+    assign \q_rdok $11
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
+  wire width 1 \qn_rdok
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
+  wire width 1 $13
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
+  cell $not $14
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr_detect$7
-    connect \Y $12
+    connect \A \q_rdok
+    connect \Y $13
   end
-  process $group_3
-    assign \src23__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $10 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest13__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src23__data_o \dest13__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest23__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src23__data_o \dest23__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $12 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \src23__data_o \reg
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \src23__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
+  process $group_2
+    assign \qn_rdok 1'0
+    assign \qn_rdok $13
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect$14
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62"
+  wire width 1 \qlq_rdok
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
   wire width 1 $15
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $16
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
+  cell $or $16
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src33__ren
-    connect \B 1'1
+    connect \A \q_rdok
+    connect \B \q_int
     connect \Y $15
   end
-  process $group_4
-    assign \wr_detect$14 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $15 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        assign \wr_detect$14 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest13__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$14 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest23__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$14 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-    end
+  process $group_3
+    assign \qlq_rdok 1'0
+    assign \qlq_rdok $15
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $17
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $18
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alui_l"
+module \alui_l$117
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
+  wire width 1 output 2 \q_alui
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+  wire width 1 input 3 \r_alui
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+  wire width 1 input 4 \s_alui
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
+  wire width 1 \q_int
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
+  wire width 1 \q_int$next
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  wire width 1 $1
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  cell $not $2
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \r_alui
+    connect \Y $1
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  wire width 1 $3
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  cell $and $4
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src33__ren
-    connect \B 1'1
-    connect \Y $17
+    connect \A \q_int
+    connect \B $1
+    connect \Y $3
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  wire width 1 $19
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $20
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  wire width 1 $5
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  cell $or $6
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr_detect$14
-    connect \Y $19
+    connect \A $3
+    connect \B \s_alui
+    connect \Y $5
   end
-  process $group_5
-    assign \src33__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $17 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  process $group_0
+    assign \q_int$next \q_int
+    assign \q_int$next $5
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest13__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src33__data_o \dest13__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest23__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src33__data_o \dest23__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $19 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \src33__data_o \reg
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \src33__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
-    sync init
-  end
-  process $group_6
-    assign \reg$next \reg
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-    switch { \dest13__wen }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-      case 1'1
-        assign \reg$next \dest13__data_i
-    end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-    switch { \dest23__wen }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-      case 1'1
-        assign \reg$next \dest23__data_i
-    end
-    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
-      case 1'1
-        assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
+        assign \q_int$next 1'0
     end
     sync init
-      update \reg 64'0000000000000000000000000000000000000000000000000000000000000000
-    sync posedge \clk
-      update \reg \reg$next
+      update \q_int 1'0
+    sync posedge \coresync_clk
+      update \q_int \q_int$next
   end
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.int.reg_4"
-module \reg_4
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 2 \src14__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 3 \src14__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 4 \src24__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 5 \src24__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 6 \src34__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 7 \src34__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 8 \dest14__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 9 \dest14__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 10 \dest24__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 11 \dest24__data_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $2
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  wire width 1 $7
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  cell $not $8
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src14__ren
-    connect \B 1'1
-    connect \Y $1
-  end
-  process $group_0
-    assign \wr_detect 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $1 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        assign \wr_detect 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest14__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest24__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-    end
-    sync init
+    connect \A \r_alui
+    connect \Y $7
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $3
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $4
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  wire width 1 $9
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  cell $and $10
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src14__ren
-    connect \B 1'1
-    connect \Y $3
+    connect \A \q_int
+    connect \B $7
+    connect \Y $9
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  wire width 1 $5
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $6
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  wire width 1 $11
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  cell $or $12
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr_detect
-    connect \Y $5
+    connect \A $9
+    connect \B \s_alui
+    connect \Y $11
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
-  wire width 64 \reg
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
-  wire width 64 \reg$next
   process $group_1
-    assign \src14__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $3 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest14__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src14__data_o \dest14__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest24__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src14__data_o \dest24__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $5 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \src14__data_o \reg
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \src14__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
+    assign \q_alui 1'0
+    assign \q_alui $11
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect$7
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $8
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $9
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
+  wire width 1 \qn_alui
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
+  wire width 1 $13
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
+  cell $not $14
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src24__ren
-    connect \B 1'1
-    connect \Y $8
+    connect \A \q_alui
+    connect \Y $13
   end
   process $group_2
-    assign \wr_detect$7 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $8 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        assign \wr_detect$7 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest14__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$7 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest24__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$7 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-    end
+    assign \qn_alui 1'0
+    assign \qn_alui $13
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $10
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $11
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62"
+  wire width 1 \qlq_alui
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
+  wire width 1 $15
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
+  cell $or $16
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src24__ren
-    connect \B 1'1
-    connect \Y $10
+    connect \A \q_alui
+    connect \B \q_int
+    connect \Y $15
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  wire width 1 $12
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $13
+  process $group_3
+    assign \qlq_alui 1'0
+    assign \qlq_alui $15
+    sync init
+  end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_l"
+module \alu_l$118
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
+  wire width 1 output 2 \q_alu
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+  wire width 1 input 3 \r_alu
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+  wire width 1 input 4 \s_alu
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
+  wire width 1 \q_int
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
+  wire width 1 \q_int$next
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  wire width 1 $1
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  cell $not $2
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr_detect$7
-    connect \Y $12
+    connect \A \r_alu
+    connect \Y $1
   end
-  process $group_3
-    assign \src24__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $10 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest14__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src24__data_o \dest14__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest24__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src24__data_o \dest24__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $12 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \src24__data_o \reg
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \src24__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
-    sync init
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  wire width 1 $3
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  cell $and $4
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \q_int
+    connect \B $1
+    connect \Y $3
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect$14
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $15
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $16
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  wire width 1 $5
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  cell $or $6
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src34__ren
-    connect \B 1'1
-    connect \Y $15
+    connect \A $3
+    connect \B \s_alu
+    connect \Y $5
   end
-  process $group_4
-    assign \wr_detect$14 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $15 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  process $group_0
+    assign \q_int$next \q_int
+    assign \q_int$next $5
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
       case 1'1
-        assign \wr_detect$14 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest14__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$14 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest24__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$14 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
+        assign \q_int$next 1'0
     end
     sync init
+      update \q_int 1'0
+    sync posedge \coresync_clk
+      update \q_int \q_int$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $17
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $18
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  wire width 1 $7
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  cell $not $8
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src34__ren
-    connect \B 1'1
-    connect \Y $17
+    connect \A \r_alu
+    connect \Y $7
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  wire width 1 $19
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $20
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  wire width 1 $9
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  cell $and $10
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr_detect$14
-    connect \Y $19
-  end
-  process $group_5
-    assign \src34__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $17 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest14__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src34__data_o \dest14__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest24__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src34__data_o \dest24__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $19 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \src34__data_o \reg
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \src34__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
-    sync init
-  end
-  process $group_6
-    assign \reg$next \reg
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-    switch { \dest14__wen }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-      case 1'1
-        assign \reg$next \dest14__data_i
-    end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-    switch { \dest24__wen }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-      case 1'1
-        assign \reg$next \dest24__data_i
-    end
-    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
-      case 1'1
-        assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
-    sync init
-      update \reg 64'0000000000000000000000000000000000000000000000000000000000000000
-    sync posedge \clk
-      update \reg \reg$next
+    connect \A \q_int
+    connect \B $7
+    connect \Y $9
   end
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.int.reg_5"
-module \reg_5
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 2 \src15__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 3 \src15__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 4 \src25__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 5 \src25__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 6 \src35__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 7 \src35__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 8 \dest15__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 9 \dest15__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 10 \dest25__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 11 \dest25__data_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $2
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  wire width 1 $11
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  cell $or $12
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src15__ren
-    connect \B 1'1
-    connect \Y $1
+    connect \A $9
+    connect \B \s_alu
+    connect \Y $11
   end
-  process $group_0
-    assign \wr_detect 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $1 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        assign \wr_detect 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest15__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest25__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-    end
+  process $group_1
+    assign \q_alu 1'0
+    assign \q_alu $11
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $3
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $4
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
+  wire width 1 \qn_alu
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
+  wire width 1 $13
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
+  cell $not $14
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src15__ren
-    connect \B 1'1
-    connect \Y $3
+    connect \A \q_alu
+    connect \Y $13
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  wire width 1 $5
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $6
+  process $group_2
+    assign \qn_alu 1'0
+    assign \qn_alu $13
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62"
+  wire width 1 \qlq_alu
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
+  wire width 1 $15
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
+  cell $or $16
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr_detect
-    connect \Y $5
+    connect \A \q_alu
+    connect \B \q_int
+    connect \Y $15
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
-  wire width 64 \reg
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
-  wire width 64 \reg$next
-  process $group_1
-    assign \src15__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $3 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest15__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src15__data_o \dest15__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest25__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src15__data_o \dest25__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $5 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \src15__data_o \reg
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \src15__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
+  process $group_3
+    assign \qlq_alu 1'0
+    assign \qlq_alu $15
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect$7
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $8
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $9
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0"
+module \shiftrot0
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \enum_base_type "MicrOp"
+  attribute \enum_value_0000000 "OP_ILLEGAL"
+  attribute \enum_value_0000001 "OP_NOP"
+  attribute \enum_value_0000010 "OP_ADD"
+  attribute \enum_value_0000011 "OP_ADDPCIS"
+  attribute \enum_value_0000100 "OP_AND"
+  attribute \enum_value_0000101 "OP_ATTN"
+  attribute \enum_value_0000110 "OP_B"
+  attribute \enum_value_0000111 "OP_BC"
+  attribute \enum_value_0001000 "OP_BCREG"
+  attribute \enum_value_0001001 "OP_BPERM"
+  attribute \enum_value_0001010 "OP_CMP"
+  attribute \enum_value_0001011 "OP_CMPB"
+  attribute \enum_value_0001100 "OP_CMPEQB"
+  attribute \enum_value_0001101 "OP_CMPRB"
+  attribute \enum_value_0001110 "OP_CNTZ"
+  attribute \enum_value_0001111 "OP_CRAND"
+  attribute \enum_value_0010000 "OP_CRANDC"
+  attribute \enum_value_0010001 "OP_CREQV"
+  attribute \enum_value_0010010 "OP_CRNAND"
+  attribute \enum_value_0010011 "OP_CRNOR"
+  attribute \enum_value_0010100 "OP_CROR"
+  attribute \enum_value_0010101 "OP_CRORC"
+  attribute \enum_value_0010110 "OP_CRXOR"
+  attribute \enum_value_0010111 "OP_DARN"
+  attribute \enum_value_0011000 "OP_DCBF"
+  attribute \enum_value_0011001 "OP_DCBST"
+  attribute \enum_value_0011010 "OP_DCBT"
+  attribute \enum_value_0011011 "OP_DCBTST"
+  attribute \enum_value_0011100 "OP_DCBZ"
+  attribute \enum_value_0011101 "OP_DIV"
+  attribute \enum_value_0011110 "OP_DIVE"
+  attribute \enum_value_0011111 "OP_EXTS"
+  attribute \enum_value_0100000 "OP_EXTSWSLI"
+  attribute \enum_value_0100001 "OP_ICBI"
+  attribute \enum_value_0100010 "OP_ICBT"
+  attribute \enum_value_0100011 "OP_ISEL"
+  attribute \enum_value_0100100 "OP_ISYNC"
+  attribute \enum_value_0100101 "OP_LOAD"
+  attribute \enum_value_0100110 "OP_STORE"
+  attribute \enum_value_0100111 "OP_MADDHD"
+  attribute \enum_value_0101000 "OP_MADDHDU"
+  attribute \enum_value_0101001 "OP_MADDLD"
+  attribute \enum_value_0101010 "OP_MCRF"
+  attribute \enum_value_0101011 "OP_MCRXR"
+  attribute \enum_value_0101100 "OP_MCRXRX"
+  attribute \enum_value_0101101 "OP_MFCR"
+  attribute \enum_value_0101110 "OP_MFSPR"
+  attribute \enum_value_0101111 "OP_MOD"
+  attribute \enum_value_0110000 "OP_MTCRF"
+  attribute \enum_value_0110001 "OP_MTSPR"
+  attribute \enum_value_0110010 "OP_MUL_L64"
+  attribute \enum_value_0110011 "OP_MUL_H64"
+  attribute \enum_value_0110100 "OP_MUL_H32"
+  attribute \enum_value_0110101 "OP_OR"
+  attribute \enum_value_0110110 "OP_POPCNT"
+  attribute \enum_value_0110111 "OP_PRTY"
+  attribute \enum_value_0111000 "OP_RLC"
+  attribute \enum_value_0111001 "OP_RLCL"
+  attribute \enum_value_0111010 "OP_RLCR"
+  attribute \enum_value_0111011 "OP_SETB"
+  attribute \enum_value_0111100 "OP_SHL"
+  attribute \enum_value_0111101 "OP_SHR"
+  attribute \enum_value_0111110 "OP_SYNC"
+  attribute \enum_value_0111111 "OP_TRAP"
+  attribute \enum_value_1000011 "OP_XOR"
+  attribute \enum_value_1000100 "OP_SIM_CONFIG"
+  attribute \enum_value_1000101 "OP_CROP"
+  attribute \enum_value_1000110 "OP_RFID"
+  attribute \enum_value_1000111 "OP_MFMSR"
+  attribute \enum_value_1001000 "OP_MTMSRD"
+  attribute \enum_value_1001001 "OP_SC"
+  attribute \enum_value_1001010 "OP_MTMSR"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 input 1 \oper_i_alu_shift_rot0__insn_type
+  attribute \enum_base_type "Function"
+  attribute \enum_value_00000000000 "NONE"
+  attribute \enum_value_00000000010 "ALU"
+  attribute \enum_value_00000000100 "LDST"
+  attribute \enum_value_00000001000 "SHIFT_ROT"
+  attribute \enum_value_00000010000 "LOGICAL"
+  attribute \enum_value_00000100000 "BRANCH"
+  attribute \enum_value_00001000000 "CR"
+  attribute \enum_value_00010000000 "TRAP"
+  attribute \enum_value_00100000000 "MUL"
+  attribute \enum_value_01000000000 "DIV"
+  attribute \enum_value_10000000000 "SPR"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 input 2 \oper_i_alu_shift_rot0__fn_unit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 input 3 \oper_i_alu_shift_rot0__imm_data__imm
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 4 \oper_i_alu_shift_rot0__imm_data__imm_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 5 \oper_i_alu_shift_rot0__rc__rc
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 6 \oper_i_alu_shift_rot0__rc__rc_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 7 \oper_i_alu_shift_rot0__oe__oe
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 8 \oper_i_alu_shift_rot0__oe__oe_ok
+  attribute \enum_base_type "CryIn"
+  attribute \enum_value_00 "ZERO"
+  attribute \enum_value_01 "ONE"
+  attribute \enum_value_10 "CA"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 2 input 10 \oper_i_alu_shift_rot0__input_carry
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 11 \oper_i_alu_shift_rot0__output_carry
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 12 \oper_i_alu_shift_rot0__input_cr
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 13 \oper_i_alu_shift_rot0__output_cr
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 14 \oper_i_alu_shift_rot0__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 15 \oper_i_alu_shift_rot0__is_signed
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 input 16 \oper_i_alu_shift_rot0__insn
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
+  wire width 1 input 17 \cu_issue_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:106"
+  wire width 1 output 18 \cu_busy_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
+  wire width 4 input 19 \cu_rdmaskn_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+  wire width 4 output 20 \cu_rd__rel_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+  wire width 4 input 21 \cu_rd__go_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
+  wire width 64 input 22 \src1_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
+  wire width 64 input 23 \src2_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
+  wire width 64 input 24 \src3_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
+  wire width 2 input 25 \src4_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 output 26 \o_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+  wire width 3 output 27 \cu_wr__rel_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+  wire width 3 input 28 \cu_wr__go_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
+  wire width 64 output 29 \dest1_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 output 30 \cr_a_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
+  wire width 4 output 31 \dest2_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 output 32 \xer_ca_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
+  wire width 2 output 33 \dest3_o
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 34 \coresync_rst
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246"
+  wire width 1 \alu_shift_rot0_n_valid_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247"
+  wire width 1 \alu_shift_rot0_n_ready_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 64 \alu_shift_rot0_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 4 \alu_shift_rot0_cr_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 2 \alu_shift_rot0_xer_ca
+  attribute \enum_base_type "MicrOp"
+  attribute \enum_value_0000000 "OP_ILLEGAL"
+  attribute \enum_value_0000001 "OP_NOP"
+  attribute \enum_value_0000010 "OP_ADD"
+  attribute \enum_value_0000011 "OP_ADDPCIS"
+  attribute \enum_value_0000100 "OP_AND"
+  attribute \enum_value_0000101 "OP_ATTN"
+  attribute \enum_value_0000110 "OP_B"
+  attribute \enum_value_0000111 "OP_BC"
+  attribute \enum_value_0001000 "OP_BCREG"
+  attribute \enum_value_0001001 "OP_BPERM"
+  attribute \enum_value_0001010 "OP_CMP"
+  attribute \enum_value_0001011 "OP_CMPB"
+  attribute \enum_value_0001100 "OP_CMPEQB"
+  attribute \enum_value_0001101 "OP_CMPRB"
+  attribute \enum_value_0001110 "OP_CNTZ"
+  attribute \enum_value_0001111 "OP_CRAND"
+  attribute \enum_value_0010000 "OP_CRANDC"
+  attribute \enum_value_0010001 "OP_CREQV"
+  attribute \enum_value_0010010 "OP_CRNAND"
+  attribute \enum_value_0010011 "OP_CRNOR"
+  attribute \enum_value_0010100 "OP_CROR"
+  attribute \enum_value_0010101 "OP_CRORC"
+  attribute \enum_value_0010110 "OP_CRXOR"
+  attribute \enum_value_0010111 "OP_DARN"
+  attribute \enum_value_0011000 "OP_DCBF"
+  attribute \enum_value_0011001 "OP_DCBST"
+  attribute \enum_value_0011010 "OP_DCBT"
+  attribute \enum_value_0011011 "OP_DCBTST"
+  attribute \enum_value_0011100 "OP_DCBZ"
+  attribute \enum_value_0011101 "OP_DIV"
+  attribute \enum_value_0011110 "OP_DIVE"
+  attribute \enum_value_0011111 "OP_EXTS"
+  attribute \enum_value_0100000 "OP_EXTSWSLI"
+  attribute \enum_value_0100001 "OP_ICBI"
+  attribute \enum_value_0100010 "OP_ICBT"
+  attribute \enum_value_0100011 "OP_ISEL"
+  attribute \enum_value_0100100 "OP_ISYNC"
+  attribute \enum_value_0100101 "OP_LOAD"
+  attribute \enum_value_0100110 "OP_STORE"
+  attribute \enum_value_0100111 "OP_MADDHD"
+  attribute \enum_value_0101000 "OP_MADDHDU"
+  attribute \enum_value_0101001 "OP_MADDLD"
+  attribute \enum_value_0101010 "OP_MCRF"
+  attribute \enum_value_0101011 "OP_MCRXR"
+  attribute \enum_value_0101100 "OP_MCRXRX"
+  attribute \enum_value_0101101 "OP_MFCR"
+  attribute \enum_value_0101110 "OP_MFSPR"
+  attribute \enum_value_0101111 "OP_MOD"
+  attribute \enum_value_0110000 "OP_MTCRF"
+  attribute \enum_value_0110001 "OP_MTSPR"
+  attribute \enum_value_0110010 "OP_MUL_L64"
+  attribute \enum_value_0110011 "OP_MUL_H64"
+  attribute \enum_value_0110100 "OP_MUL_H32"
+  attribute \enum_value_0110101 "OP_OR"
+  attribute \enum_value_0110110 "OP_POPCNT"
+  attribute \enum_value_0110111 "OP_PRTY"
+  attribute \enum_value_0111000 "OP_RLC"
+  attribute \enum_value_0111001 "OP_RLCL"
+  attribute \enum_value_0111010 "OP_RLCR"
+  attribute \enum_value_0111011 "OP_SETB"
+  attribute \enum_value_0111100 "OP_SHL"
+  attribute \enum_value_0111101 "OP_SHR"
+  attribute \enum_value_0111110 "OP_SYNC"
+  attribute \enum_value_0111111 "OP_TRAP"
+  attribute \enum_value_1000011 "OP_XOR"
+  attribute \enum_value_1000100 "OP_SIM_CONFIG"
+  attribute \enum_value_1000101 "OP_CROP"
+  attribute \enum_value_1000110 "OP_RFID"
+  attribute \enum_value_1000111 "OP_MFMSR"
+  attribute \enum_value_1001000 "OP_MTMSRD"
+  attribute \enum_value_1001001 "OP_SC"
+  attribute \enum_value_1001010 "OP_MTMSR"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 \alu_shift_rot0_sr_op__insn_type
+  attribute \enum_base_type "Function"
+  attribute \enum_value_00000000000 "NONE"
+  attribute \enum_value_00000000010 "ALU"
+  attribute \enum_value_00000000100 "LDST"
+  attribute \enum_value_00000001000 "SHIFT_ROT"
+  attribute \enum_value_00000010000 "LOGICAL"
+  attribute \enum_value_00000100000 "BRANCH"
+  attribute \enum_value_00001000000 "CR"
+  attribute \enum_value_00010000000 "TRAP"
+  attribute \enum_value_00100000000 "MUL"
+  attribute \enum_value_01000000000 "DIV"
+  attribute \enum_value_10000000000 "SPR"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 \alu_shift_rot0_sr_op__fn_unit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 \alu_shift_rot0_sr_op__imm_data__imm
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \alu_shift_rot0_sr_op__imm_data__imm_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \alu_shift_rot0_sr_op__rc__rc
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \alu_shift_rot0_sr_op__rc__rc_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \alu_shift_rot0_sr_op__oe__oe
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \alu_shift_rot0_sr_op__oe__oe_ok
+  attribute \enum_base_type "CryIn"
+  attribute \enum_value_00 "ZERO"
+  attribute \enum_value_01 "ONE"
+  attribute \enum_value_10 "CA"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 2 \alu_shift_rot0_sr_op__input_carry
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \alu_shift_rot0_sr_op__output_carry
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \alu_shift_rot0_sr_op__input_cr
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \alu_shift_rot0_sr_op__output_cr
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \alu_shift_rot0_sr_op__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \alu_shift_rot0_sr_op__is_signed
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \alu_shift_rot0_sr_op__insn
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
+  wire width 64 \alu_shift_rot0_ra
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
+  wire width 64 \alu_shift_rot0_rb
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
+  wire width 64 \alu_shift_rot0_rc
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29"
+  wire width 2 \alu_shift_rot0_xer_ca$1
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153"
+  wire width 1 \alu_shift_rot0_p_valid_i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154"
+  wire width 1 \alu_shift_rot0_p_ready_o
+  cell \alu_shift_rot0 \alu_shift_rot0
+    connect \coresync_clk \coresync_clk
+    connect \o_ok \o_ok
+    connect \cr_a_ok \cr_a_ok
+    connect \xer_ca_ok \xer_ca_ok
+    connect \coresync_rst \coresync_rst
+    connect \n_valid_o \alu_shift_rot0_n_valid_o
+    connect \n_ready_i \alu_shift_rot0_n_ready_i
+    connect \o \alu_shift_rot0_o
+    connect \cr_a \alu_shift_rot0_cr_a
+    connect \xer_ca \alu_shift_rot0_xer_ca
+    connect \sr_op__insn_type \alu_shift_rot0_sr_op__insn_type
+    connect \sr_op__fn_unit \alu_shift_rot0_sr_op__fn_unit
+    connect \sr_op__imm_data__imm \alu_shift_rot0_sr_op__imm_data__imm
+    connect \sr_op__imm_data__imm_ok \alu_shift_rot0_sr_op__imm_data__imm_ok
+    connect \sr_op__rc__rc \alu_shift_rot0_sr_op__rc__rc
+    connect \sr_op__rc__rc_ok \alu_shift_rot0_sr_op__rc__rc_ok
+    connect \sr_op__oe__oe \alu_shift_rot0_sr_op__oe__oe
+    connect \sr_op__oe__oe_ok \alu_shift_rot0_sr_op__oe__oe_ok
+    connect \sr_op__input_carry \alu_shift_rot0_sr_op__input_carry
+    connect \sr_op__output_carry \alu_shift_rot0_sr_op__output_carry
+    connect \sr_op__input_cr \alu_shift_rot0_sr_op__input_cr
+    connect \sr_op__output_cr \alu_shift_rot0_sr_op__output_cr
+    connect \sr_op__is_32bit \alu_shift_rot0_sr_op__is_32bit
+    connect \sr_op__is_signed \alu_shift_rot0_sr_op__is_signed
+    connect \sr_op__insn \alu_shift_rot0_sr_op__insn
+    connect \ra \alu_shift_rot0_ra
+    connect \rb \alu_shift_rot0_rb
+    connect \rc \alu_shift_rot0_rc
+    connect \xer_ca$1 \alu_shift_rot0_xer_ca$1
+    connect \p_valid_i \alu_shift_rot0_p_valid_i
+    connect \p_ready_o \alu_shift_rot0_p_ready_o
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+  wire width 4 \src_l_s_src
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+  wire width 4 \src_l_s_src$next
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+  wire width 4 \src_l_r_src
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+  wire width 4 \src_l_r_src$next
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
+  wire width 4 \src_l_q_src
+  cell \src_l$112 \src_l
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
+    connect \s_src \src_l_s_src
+    connect \r_src \src_l_r_src
+    connect \q_src \src_l_q_src
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+  wire width 1 \opc_l_s_opc
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+  wire width 1 \opc_l_s_opc$next
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+  wire width 1 \opc_l_r_opc
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+  wire width 1 \opc_l_r_opc$next
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
+  wire width 1 \opc_l_q_opc
+  cell \opc_l$113 \opc_l
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
+    connect \s_opc \opc_l_s_opc
+    connect \r_opc \opc_l_r_opc
+    connect \q_opc \opc_l_q_opc
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
+  wire width 3 \req_l_q_req
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+  wire width 3 \req_l_s_req
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+  wire width 3 \req_l_r_req
+  cell \req_l$114 \req_l
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
+    connect \q_req \req_l_q_req
+    connect \s_req \req_l_s_req
+    connect \r_req \req_l_r_req
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+  wire width 1 \rst_l_s_rst
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+  wire width 1 \rst_l_r_rst
+  cell \rst_l$115 \rst_l
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
+    connect \s_rst \rst_l_s_rst
+    connect \r_rst \rst_l_r_rst
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
+  wire width 1 \rok_l_q_rdok
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+  wire width 1 \rok_l_s_rdok
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+  wire width 1 \rok_l_r_rdok
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+  wire width 1 \rok_l_r_rdok$next
+  cell \rok_l$116 \rok_l
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
+    connect \q_rdok \rok_l_q_rdok
+    connect \s_rdok \rok_l_s_rdok
+    connect \r_rdok \rok_l_r_rdok
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
+  wire width 1 \alui_l_q_alui
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+  wire width 1 \alui_l_r_alui
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+  wire width 1 \alui_l_r_alui$next
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+  wire width 1 \alui_l_s_alui
+  cell \alui_l$117 \alui_l
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
+    connect \q_alui \alui_l_q_alui
+    connect \r_alui \alui_l_r_alui
+    connect \s_alui \alui_l_s_alui
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
+  wire width 1 \alu_l_q_alu
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+  wire width 1 \alu_l_r_alu
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+  wire width 1 \alu_l_r_alu$next
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+  wire width 1 \alu_l_s_alu
+  cell \alu_l$118 \alu_l
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
+    connect \q_alu \alu_l_q_alu
+    connect \r_alu \alu_l_r_alu
+    connect \s_alu \alu_l_s_alu
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:186"
+  wire width 1 \all_rd
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:187"
+  wire width 1 $2
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:187"
+  cell $and $3
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src25__ren
-    connect \B 1'1
-    connect \Y $8
+    connect \A \cu_busy_o
+    connect \B \rok_l_q_rdok
+    connect \Y $2
   end
-  process $group_2
-    assign \wr_detect$7 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $8 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        assign \wr_detect$7 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest15__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$7 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest25__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$7 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-    end
-    sync init
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188"
+  wire width 1 $4
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188"
+  wire width 4 $5
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188"
+  cell $not $6
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 4
+    parameter \Y_WIDTH 4
+    connect \A \cu_rd__rel_o
+    connect \Y $5
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $10
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $11
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188"
+  wire width 4 $7
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188"
+  cell $or $8
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
+    parameter \A_WIDTH 4
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
+    parameter \B_WIDTH 4
+    parameter \Y_WIDTH 4
+    connect \A $5
+    connect \B \cu_rd__go_i
+    connect \Y $7
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188"
+  cell $reduce_and $9
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 4
     parameter \Y_WIDTH 1
-    connect \A \src25__ren
-    connect \B 1'1
-    connect \Y $10
+    connect \A $7
+    connect \Y $4
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  wire width 1 $12
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $13
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188"
+  wire width 1 $10
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188"
+  cell $and $11
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr_detect$7
-    connect \Y $12
+    connect \A $2
+    connect \B $4
+    connect \Y $10
   end
-  process $group_3
-    assign \src25__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $10 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest15__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src25__data_o \dest15__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest25__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src25__data_o \dest25__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $12 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \src25__data_o \reg
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \src25__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
+  process $group_0
+    assign \all_rd 1'0
+    assign \all_rd $10
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect$14
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $15
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $16
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:191"
+  wire width 1 \all_rd_dly
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:191"
+  wire width 1 \all_rd_dly$next
+  process $group_1
+    assign \all_rd_dly$next \all_rd_dly
+    assign \all_rd_dly$next \all_rd
+    sync init
+      update \all_rd_dly 1'0
+    sync posedge \coresync_clk
+      update \all_rd_dly \all_rd_dly$next
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:192"
+  wire width 1 \all_rd_pulse
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:194"
+  wire width 1 $12
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:194"
+  cell $not $13
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \all_rd_dly
+    connect \Y $12
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:194"
+  wire width 1 $14
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:194"
+  cell $and $15
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src35__ren
-    connect \B 1'1
-    connect \Y $15
+    connect \A \all_rd
+    connect \B $12
+    connect \Y $14
+  end
+  process $group_2
+    assign \all_rd_pulse 1'0
+    assign \all_rd_pulse $14
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:197"
+  wire width 1 \alu_done
+  process $group_3
+    assign \alu_done 1'0
+    assign \alu_done \alu_shift_rot0_n_valid_o
+    sync init
   end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198"
+  wire width 1 \alu_done_dly
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198"
+  wire width 1 \alu_done_dly$next
   process $group_4
-    assign \wr_detect$14 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $15 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        assign \wr_detect$14 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest15__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$14 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest25__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$14 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-    end
+    assign \alu_done_dly$next \alu_done_dly
+    assign \alu_done_dly$next \alu_done
     sync init
+      update \alu_done_dly 1'0
+    sync posedge \coresync_clk
+      update \alu_done_dly \alu_done_dly$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $17
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $18
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:199"
+  wire width 1 \alu_pulse
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:203"
+  wire width 1 $16
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:203"
+  cell $not $17
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src35__ren
-    connect \B 1'1
-    connect \Y $17
+    connect \A \alu_done_dly
+    connect \Y $16
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  wire width 1 $19
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $20
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:203"
+  wire width 1 $18
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:203"
+  cell $and $19
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr_detect$14
-    connect \Y $19
+    connect \A \alu_done
+    connect \B $16
+    connect \Y $18
   end
   process $group_5
-    assign \src35__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $17 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest15__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src35__data_o \dest15__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest25__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src35__data_o \dest25__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $19 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \src35__data_o \reg
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \src35__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
+    assign \alu_pulse 1'0
+    assign \alu_pulse $18
     sync init
   end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:200"
+  wire width 3 \alu_pulsem
   process $group_6
-    assign \reg$next \reg
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-    switch { \dest15__wen }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-      case 1'1
-        assign \reg$next \dest15__data_i
-    end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-    switch { \dest25__wen }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-      case 1'1
-        assign \reg$next \dest25__data_i
-    end
-    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
-      case 1'1
-        assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
+    assign \alu_pulsem 3'000
+    assign \alu_pulsem { \alu_pulse \alu_pulse \alu_pulse }
     sync init
-      update \reg 64'0000000000000000000000000000000000000000000000000000000000000000
-    sync posedge \clk
-      update \reg \reg$next
   end
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.int.reg_6"
-module \reg_6
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 2 \src16__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 3 \src16__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 4 \src26__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 5 \src26__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 6 \src36__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 7 \src36__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 8 \dest16__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 9 \dest16__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 10 \dest26__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 11 \dest26__data_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $2
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:207"
+  wire width 3 \prev_wr_go
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:207"
+  wire width 3 \prev_wr_go$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
+  wire width 3 $20
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:209"
+  cell $and $21
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
+    parameter \A_WIDTH 3
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \src16__ren
-    connect \B 1'1
-    connect \Y $1
+    parameter \B_WIDTH 3
+    parameter \Y_WIDTH 3
+    connect \A \cu_wr__go_i
+    connect \B { \cu_busy_o \cu_busy_o \cu_busy_o }
+    connect \Y $20
   end
-  process $group_0
-    assign \wr_detect 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $1 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  process $group_7
+    assign \prev_wr_go$next \prev_wr_go
+    assign \prev_wr_go$next $20
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
       case 1'1
-        assign \wr_detect 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest16__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest26__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
+        assign \prev_wr_go$next 3'000
     end
     sync init
+      update \prev_wr_go 3'000
+    sync posedge \coresync_clk
+      update \prev_wr_go \prev_wr_go$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $3
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $4
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107"
+  wire width 1 \cu_done_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
+  wire width 1 $22
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
+  wire width 1 $23
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
+  wire width 3 $24
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96"
+  wire width 3 \cu_wrmask_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
+  cell $not $25
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
+    parameter \A_WIDTH 3
+    parameter \Y_WIDTH 3
+    connect \A \cu_wrmask_o
+    connect \Y $24
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
+  wire width 3 $26
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
+  cell $and $27
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 3
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
+    parameter \B_WIDTH 3
+    parameter \Y_WIDTH 3
+    connect \A \cu_wr__rel_o
+    connect \B $24
+    connect \Y $26
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
+  cell $reduce_bool $28
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 3
     parameter \Y_WIDTH 1
-    connect \A \src16__ren
-    connect \B 1'1
-    connect \Y $3
+    connect \A $26
+    connect \Y $23
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  wire width 1 $5
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $6
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
+  cell $not $29
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr_detect
-    connect \Y $5
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
-  wire width 64 \reg
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
-  wire width 64 \reg$next
-  process $group_1
-    assign \src16__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $3 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest16__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src16__data_o \dest16__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest26__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src16__data_o \dest26__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $5 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \src16__data_o \reg
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \src16__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
-    sync init
+    connect \A $23
+    connect \Y $22
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect$7
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $8
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $9
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
+  wire width 1 $30
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217"
+  cell $and $31
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src26__ren
-    connect \B 1'1
-    connect \Y $8
+    connect \A \cu_busy_o
+    connect \B $22
+    connect \Y $30
   end
-  process $group_2
-    assign \wr_detect$7 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $8 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        assign \wr_detect$7 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest16__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$7 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest26__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$7 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-    end
+  process $group_8
+    assign \cu_done_o 1'0
+    assign \cu_done_o $30
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $10
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $11
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214"
+  wire width 1 \wr_any
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:218"
+  wire width 1 $32
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:218"
+  cell $reduce_bool $33
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 3
+    parameter \Y_WIDTH 1
+    connect \A \cu_wr__go_i
+    connect \Y $32
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:218"
+  wire width 1 $34
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:218"
+  cell $reduce_bool $35
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 3
+    parameter \Y_WIDTH 1
+    connect \A \prev_wr_go
+    connect \Y $34
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:218"
+  wire width 1 $36
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:218"
+  cell $or $37
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src26__ren
-    connect \B 1'1
-    connect \Y $10
+    connect \A $32
+    connect \B $34
+    connect \Y $36
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  wire width 1 $12
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $13
+  process $group_9
+    assign \wr_any 1'0
+    assign \wr_any $36
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215"
+  wire width 1 \req_done
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:219"
+  wire width 1 $38
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:219"
+  cell $not $39
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr_detect$7
-    connect \Y $12
-  end
-  process $group_3
-    assign \src26__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $10 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest16__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src26__data_o \dest16__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest26__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src26__data_o \dest26__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $12 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \src26__data_o \reg
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \src26__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
-    sync init
+    connect \A \alu_shift_rot0_n_ready_i
+    connect \Y $38
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect$14
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $15
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $16
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:219"
+  wire width 1 $40
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:219"
+  cell $and $41
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src36__ren
-    connect \B 1'1
-    connect \Y $15
+    connect \A \wr_any
+    connect \B $38
+    connect \Y $40
   end
-  process $group_4
-    assign \wr_detect$14 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $15 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        assign \wr_detect$14 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest16__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$14 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest26__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$14 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-    end
-    sync init
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:220"
+  wire width 3 $42
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:220"
+  cell $and $43
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 3
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 3
+    parameter \Y_WIDTH 3
+    connect \A \req_l_q_req
+    connect \B \cu_wrmask_o
+    connect \Y $42
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $17
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $18
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:220"
+  wire width 1 $44
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:220"
+  cell $eq $45
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
+    parameter \A_WIDTH 3
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src36__ren
-    connect \B 1'1
-    connect \Y $17
+    connect \A $42
+    connect \B 1'0
+    connect \Y $44
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  wire width 1 $19
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $20
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:220"
+  wire width 1 $46
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:220"
+  cell $and $47
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr_detect$14
-    connect \Y $19
-  end
-  process $group_5
-    assign \src36__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $17 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest16__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src36__data_o \dest16__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest26__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src36__data_o \dest26__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $19 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \src36__data_o \reg
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \src36__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
-    sync init
+    connect \A $40
+    connect \B $44
+    connect \Y $46
   end
-  process $group_6
-    assign \reg$next \reg
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-    switch { \dest16__wen }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-      case 1'1
-        assign \reg$next \dest16__data_i
-    end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-    switch { \dest26__wen }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-      case 1'1
-        assign \reg$next \dest26__data_i
-    end
-    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
-      case 1'1
-        assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
-    sync init
-      update \reg 64'0000000000000000000000000000000000000000000000000000000000000000
-    sync posedge \clk
-      update \reg \reg$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
+  wire width 1 $48
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
+  cell $eq $49
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 3
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \cu_wrmask_o
+    connect \B 1'0
+    connect \Y $48
   end
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.int.reg_7"
-module \reg_7
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 2 \src17__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 3 \src17__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 4 \src27__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 5 \src27__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 6 \src37__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 7 \src37__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 8 \dest17__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 9 \dest17__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 10 \dest27__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 11 \dest27__data_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $2
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
+  wire width 1 $50
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
+  cell $and $51
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src17__ren
-    connect \B 1'1
-    connect \Y $1
-  end
-  process $group_0
-    assign \wr_detect 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $1 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        assign \wr_detect 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest17__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest27__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-    end
-    sync init
+    connect \A $48
+    connect \B \alu_shift_rot0_n_ready_i
+    connect \Y $50
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $3
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $4
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
+  wire width 1 $52
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
+  cell $and $53
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src17__ren
-    connect \B 1'1
-    connect \Y $3
+    connect \A $50
+    connect \B \alu_shift_rot0_n_valid_o
+    connect \Y $52
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  wire width 1 $5
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $6
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
+  wire width 1 $54
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
+  cell $and $55
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr_detect
-    connect \Y $5
+    connect \A $52
+    connect \B \cu_busy_o
+    connect \Y $54
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
-  wire width 64 \reg
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
-  wire width 64 \reg$next
-  process $group_1
-    assign \src17__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $3 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  process $group_10
+    assign \req_done 1'0
+    assign \req_done $46
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
+    switch { $54 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:225"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest17__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src17__data_o \dest17__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest27__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src17__data_o \dest27__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $5 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \src17__data_o \reg
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \src17__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+        assign \req_done 1'1
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect$7
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $8
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $9
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:229"
+  wire width 1 \reset
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:103"
+  wire width 1 \cu_go_die_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233"
+  wire width 1 $56
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233"
+  cell $or $57
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src27__ren
-    connect \B 1'1
-    connect \Y $8
+    connect \A \req_done
+    connect \B \cu_go_die_i
+    connect \Y $56
   end
-  process $group_2
-    assign \wr_detect$7 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $8 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        assign \wr_detect$7 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest17__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$7 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest27__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$7 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-    end
+  process $group_11
+    assign \reset 1'0
+    assign \reset $56
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $10
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $11
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230"
+  wire width 1 \rst_r
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:234"
+  wire width 1 $58
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:234"
+  cell $or $59
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src27__ren
-    connect \B 1'1
-    connect \Y $10
+    connect \A \cu_issue_i
+    connect \B \cu_go_die_i
+    connect \Y $58
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  wire width 1 $12
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $13
+  process $group_12
+    assign \rst_r 1'0
+    assign \rst_r $58
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231"
+  wire width 3 \reset_w
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:235"
+  wire width 3 $60
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:235"
+  cell $or $61
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \wr_detect$7
-    connect \Y $12
+    parameter \A_WIDTH 3
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 3
+    parameter \Y_WIDTH 3
+    connect \A \cu_wr__go_i
+    connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i }
+    connect \Y $60
   end
-  process $group_3
-    assign \src27__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $10 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest17__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src27__data_o \dest17__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest27__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src27__data_o \dest27__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $12 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \src27__data_o \reg
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \src27__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
+  process $group_13
+    assign \reset_w 3'000
+    assign \reset_w $60
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect$14
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $15
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $16
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232"
+  wire width 4 \reset_r
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:236"
+  wire width 4 $62
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:236"
+  cell $or $63
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
+    parameter \A_WIDTH 4
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \src37__ren
-    connect \B 1'1
-    connect \Y $15
+    parameter \B_WIDTH 4
+    parameter \Y_WIDTH 4
+    connect \A \cu_rd__go_i
+    connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i }
+    connect \Y $62
   end
-  process $group_4
-    assign \wr_detect$14 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $15 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        assign \wr_detect$14 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest17__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$14 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest27__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$14 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-    end
+  process $group_14
+    assign \reset_r 4'0000
+    assign \reset_r $62
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $17
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $18
+  process $group_15
+    assign \rok_l_s_rdok 1'0
+    assign \rok_l_s_rdok \cu_issue_i
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:240"
+  wire width 1 $64
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:240"
+  cell $and $65
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src37__ren
-    connect \B 1'1
-    connect \Y $17
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  wire width 1 $19
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $20
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \wr_detect$14
-    connect \Y $19
+    connect \A \alu_shift_rot0_n_valid_o
+    connect \B \cu_busy_o
+    connect \Y $64
   end
-  process $group_5
-    assign \src37__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $17 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  process $group_16
+    assign \rok_l_r_rdok$next \rok_l_r_rdok
+    assign \rok_l_r_rdok$next $64
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest17__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src37__data_o \dest17__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest27__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src37__data_o \dest27__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $19 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \src37__data_o \reg
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \src37__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+        assign \rok_l_r_rdok$next 1'1
     end
     sync init
+      update \rok_l_r_rdok 1'1
+    sync posedge \coresync_clk
+      update \rok_l_r_rdok \rok_l_r_rdok$next
   end
-  process $group_6
-    assign \reg$next \reg
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-    switch { \dest17__wen }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-      case 1'1
-        assign \reg$next \dest17__data_i
-    end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-    switch { \dest27__wen }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-      case 1'1
-        assign \reg$next \dest27__data_i
-    end
+  process $group_17
+    assign \rst_l_s_rst 1'0
+    assign \rst_l_s_rst \all_rd
+    sync init
+  end
+  process $group_18
+    assign \rst_l_r_rst 1'1
+    assign \rst_l_r_rst \rst_r
+    sync init
+  end
+  process $group_19
+    assign \opc_l_s_opc$next \opc_l_s_opc
+    assign \opc_l_s_opc$next \cu_issue_i
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
-        assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
+        assign \opc_l_s_opc$next 1'0
     end
     sync init
-      update \reg 64'0000000000000000000000000000000000000000000000000000000000000000
-    sync posedge \clk
-      update \reg \reg$next
+      update \opc_l_s_opc 1'0
+    sync posedge \coresync_clk
+      update \opc_l_s_opc \opc_l_s_opc$next
   end
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.int.reg_8"
-module \reg_8
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 2 \src18__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 3 \src18__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 4 \src28__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 5 \src28__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 6 \src38__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 7 \src38__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 8 \dest18__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 9 \dest18__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 10 \dest28__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 11 \dest28__data_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $2
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \src18__ren
-    connect \B 1'1
-    connect \Y $1
-  end
-  process $group_0
-    assign \wr_detect 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $1 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  process $group_20
+    assign \opc_l_r_opc$next \opc_l_r_opc
+    assign \opc_l_r_opc$next \req_done
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
       case 1'1
-        assign \wr_detect 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest18__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest28__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
+        assign \opc_l_r_opc$next 1'1
     end
     sync init
+      update \opc_l_r_opc 1'1
+    sync posedge \coresync_clk
+      update \opc_l_r_opc \opc_l_r_opc$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $3
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $4
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \src18__ren
-    connect \B 1'1
-    connect \Y $3
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  wire width 1 $5
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $6
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \wr_detect
-    connect \Y $5
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
-  wire width 64 \reg
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
-  wire width 64 \reg$next
-  process $group_1
-    assign \src18__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $3 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  process $group_21
+    assign \src_l_s_src$next \src_l_s_src
+    assign \src_l_s_src$next { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i }
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest18__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src18__data_o \dest18__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest28__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src18__data_o \dest28__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $5 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \src18__data_o \reg
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \src18__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+        assign \src_l_s_src$next 4'0000
     end
     sync init
+      update \src_l_s_src 4'0000
+    sync posedge \coresync_clk
+      update \src_l_s_src \src_l_s_src$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect$7
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $8
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $9
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \src28__ren
-    connect \B 1'1
-    connect \Y $8
-  end
-  process $group_2
-    assign \wr_detect$7 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $8 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  process $group_22
+    assign \src_l_r_src$next \src_l_r_src
+    assign \src_l_r_src$next \reset_r
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
       case 1'1
-        assign \wr_detect$7 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest18__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$7 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest28__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$7 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
+        assign \src_l_r_src$next 4'1111
     end
     sync init
+      update \src_l_r_src 4'1111
+    sync posedge \coresync_clk
+      update \src_l_r_src \src_l_r_src$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $10
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $11
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:255"
+  wire width 3 $66
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:255"
+  cell $and $67
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
+    parameter \A_WIDTH 3
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \src28__ren
-    connect \B 1'1
-    connect \Y $10
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  wire width 1 $12
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $13
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \wr_detect$7
-    connect \Y $12
+    parameter \B_WIDTH 3
+    parameter \Y_WIDTH 3
+    connect \A \alu_pulsem
+    connect \B \cu_wrmask_o
+    connect \Y $66
   end
-  process $group_3
-    assign \src28__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $10 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest18__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src28__data_o \dest18__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest28__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src28__data_o \dest28__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $12 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \src28__data_o \reg
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \src28__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
+  process $group_23
+    assign \req_l_s_req 3'000
+    assign \req_l_s_req $66
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect$14
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $15
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $16
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:256"
+  wire width 3 $68
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:256"
+  cell $or $69
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
+    parameter \A_WIDTH 3
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \src38__ren
-    connect \B 1'1
-    connect \Y $15
+    parameter \B_WIDTH 3
+    parameter \Y_WIDTH 3
+    connect \A \reset_w
+    connect \B \prev_wr_go
+    connect \Y $68
   end
-  process $group_4
-    assign \wr_detect$14 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $15 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        assign \wr_detect$14 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest18__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$14 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest28__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$14 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-    end
+  process $group_24
+    assign \req_l_r_req 3'111
+    assign \req_l_r_req $68
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $17
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $18
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \src38__ren
-    connect \B 1'1
-    connect \Y $17
+  attribute \enum_base_type "MicrOp"
+  attribute \enum_value_0000000 "OP_ILLEGAL"
+  attribute \enum_value_0000001 "OP_NOP"
+  attribute \enum_value_0000010 "OP_ADD"
+  attribute \enum_value_0000011 "OP_ADDPCIS"
+  attribute \enum_value_0000100 "OP_AND"
+  attribute \enum_value_0000101 "OP_ATTN"
+  attribute \enum_value_0000110 "OP_B"
+  attribute \enum_value_0000111 "OP_BC"
+  attribute \enum_value_0001000 "OP_BCREG"
+  attribute \enum_value_0001001 "OP_BPERM"
+  attribute \enum_value_0001010 "OP_CMP"
+  attribute \enum_value_0001011 "OP_CMPB"
+  attribute \enum_value_0001100 "OP_CMPEQB"
+  attribute \enum_value_0001101 "OP_CMPRB"
+  attribute \enum_value_0001110 "OP_CNTZ"
+  attribute \enum_value_0001111 "OP_CRAND"
+  attribute \enum_value_0010000 "OP_CRANDC"
+  attribute \enum_value_0010001 "OP_CREQV"
+  attribute \enum_value_0010010 "OP_CRNAND"
+  attribute \enum_value_0010011 "OP_CRNOR"
+  attribute \enum_value_0010100 "OP_CROR"
+  attribute \enum_value_0010101 "OP_CRORC"
+  attribute \enum_value_0010110 "OP_CRXOR"
+  attribute \enum_value_0010111 "OP_DARN"
+  attribute \enum_value_0011000 "OP_DCBF"
+  attribute \enum_value_0011001 "OP_DCBST"
+  attribute \enum_value_0011010 "OP_DCBT"
+  attribute \enum_value_0011011 "OP_DCBTST"
+  attribute \enum_value_0011100 "OP_DCBZ"
+  attribute \enum_value_0011101 "OP_DIV"
+  attribute \enum_value_0011110 "OP_DIVE"
+  attribute \enum_value_0011111 "OP_EXTS"
+  attribute \enum_value_0100000 "OP_EXTSWSLI"
+  attribute \enum_value_0100001 "OP_ICBI"
+  attribute \enum_value_0100010 "OP_ICBT"
+  attribute \enum_value_0100011 "OP_ISEL"
+  attribute \enum_value_0100100 "OP_ISYNC"
+  attribute \enum_value_0100101 "OP_LOAD"
+  attribute \enum_value_0100110 "OP_STORE"
+  attribute \enum_value_0100111 "OP_MADDHD"
+  attribute \enum_value_0101000 "OP_MADDHDU"
+  attribute \enum_value_0101001 "OP_MADDLD"
+  attribute \enum_value_0101010 "OP_MCRF"
+  attribute \enum_value_0101011 "OP_MCRXR"
+  attribute \enum_value_0101100 "OP_MCRXRX"
+  attribute \enum_value_0101101 "OP_MFCR"
+  attribute \enum_value_0101110 "OP_MFSPR"
+  attribute \enum_value_0101111 "OP_MOD"
+  attribute \enum_value_0110000 "OP_MTCRF"
+  attribute \enum_value_0110001 "OP_MTSPR"
+  attribute \enum_value_0110010 "OP_MUL_L64"
+  attribute \enum_value_0110011 "OP_MUL_H64"
+  attribute \enum_value_0110100 "OP_MUL_H32"
+  attribute \enum_value_0110101 "OP_OR"
+  attribute \enum_value_0110110 "OP_POPCNT"
+  attribute \enum_value_0110111 "OP_PRTY"
+  attribute \enum_value_0111000 "OP_RLC"
+  attribute \enum_value_0111001 "OP_RLCL"
+  attribute \enum_value_0111010 "OP_RLCR"
+  attribute \enum_value_0111011 "OP_SETB"
+  attribute \enum_value_0111100 "OP_SHL"
+  attribute \enum_value_0111101 "OP_SHR"
+  attribute \enum_value_0111110 "OP_SYNC"
+  attribute \enum_value_0111111 "OP_TRAP"
+  attribute \enum_value_1000011 "OP_XOR"
+  attribute \enum_value_1000100 "OP_SIM_CONFIG"
+  attribute \enum_value_1000101 "OP_CROP"
+  attribute \enum_value_1000110 "OP_RFID"
+  attribute \enum_value_1000111 "OP_MFMSR"
+  attribute \enum_value_1001000 "OP_MTMSRD"
+  attribute \enum_value_1001001 "OP_SC"
+  attribute \enum_value_1001010 "OP_MTMSR"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 \oper_r__insn_type
+  attribute \enum_base_type "Function"
+  attribute \enum_value_00000000000 "NONE"
+  attribute \enum_value_00000000010 "ALU"
+  attribute \enum_value_00000000100 "LDST"
+  attribute \enum_value_00000001000 "SHIFT_ROT"
+  attribute \enum_value_00000010000 "LOGICAL"
+  attribute \enum_value_00000100000 "BRANCH"
+  attribute \enum_value_00001000000 "CR"
+  attribute \enum_value_00010000000 "TRAP"
+  attribute \enum_value_00100000000 "MUL"
+  attribute \enum_value_01000000000 "DIV"
+  attribute \enum_value_10000000000 "SPR"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 \oper_r__fn_unit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 \oper_r__imm_data__imm
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \oper_r__imm_data__imm_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \oper_r__rc__rc
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \oper_r__rc__rc_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \oper_r__oe__oe
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \oper_r__oe__oe_ok
+  attribute \enum_base_type "CryIn"
+  attribute \enum_value_00 "ZERO"
+  attribute \enum_value_01 "ONE"
+  attribute \enum_value_10 "CA"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 2 \oper_r__input_carry
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \oper_r__output_carry
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \oper_r__input_cr
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \oper_r__output_cr
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \oper_r__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \oper_r__is_signed
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \oper_r__insn
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+  wire width 7 \oper_l__insn_type
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+  wire width 7 \oper_l__insn_type$next
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+  wire width 11 \oper_l__fn_unit
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+  wire width 11 \oper_l__fn_unit$next
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+  wire width 64 \oper_l__imm_data__imm
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+  wire width 64 \oper_l__imm_data__imm$next
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+  wire width 1 \oper_l__imm_data__imm_ok
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+  wire width 1 \oper_l__imm_data__imm_ok$next
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+  wire width 1 \oper_l__rc__rc
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+  wire width 1 \oper_l__rc__rc$next
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+  wire width 1 \oper_l__rc__rc_ok
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+  wire width 1 \oper_l__rc__rc_ok$next
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+  wire width 1 \oper_l__oe__oe
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+  wire width 1 \oper_l__oe__oe$next
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+  wire width 1 \oper_l__oe__oe_ok
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+  wire width 1 \oper_l__oe__oe_ok$next
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+  wire width 2 \oper_l__input_carry
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+  wire width 2 \oper_l__input_carry$next
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+  wire width 1 \oper_l__output_carry
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+  wire width 1 \oper_l__output_carry$next
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+  wire width 1 \oper_l__input_cr
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+  wire width 1 \oper_l__input_cr$next
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+  wire width 1 \oper_l__output_cr
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+  wire width 1 \oper_l__output_cr$next
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+  wire width 1 \oper_l__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+  wire width 1 \oper_l__is_32bit$next
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+  wire width 1 \oper_l__is_signed
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+  wire width 1 \oper_l__is_signed$next
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+  wire width 32 \oper_l__insn
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+  wire width 32 \oper_l__insn$next
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
+  wire width 126 $70
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
+  cell $mux $71
+    parameter \WIDTH 126
+    connect \A { \oper_l__insn \oper_l__is_signed \oper_l__is_32bit \oper_l__output_cr \oper_l__input_cr \oper_l__output_carry \oper_l__input_carry { } { \oper_l__oe__oe_ok \oper_l__oe__oe } { \oper_l__rc__rc_ok \oper_l__rc__rc } { \oper_l__imm_data__imm_ok \oper_l__imm_data__imm } \oper_l__fn_unit \oper_l__insn_type }
+    connect \B { \oper_i_alu_shift_rot0__insn \oper_i_alu_shift_rot0__is_signed \oper_i_alu_shift_rot0__is_32bit \oper_i_alu_shift_rot0__output_cr \oper_i_alu_shift_rot0__input_cr \oper_i_alu_shift_rot0__output_carry \oper_i_alu_shift_rot0__input_carry { } { \oper_i_alu_shift_rot0__oe__oe_ok \oper_i_alu_shift_rot0__oe__oe } { \oper_i_alu_shift_rot0__rc__rc_ok \oper_i_alu_shift_rot0__rc__rc } { \oper_i_alu_shift_rot0__imm_data__imm_ok \oper_i_alu_shift_rot0__imm_data__imm } \oper_i_alu_shift_rot0__fn_unit \oper_i_alu_shift_rot0__insn_type }
+    connect \S \cu_issue_i
+    connect \Y $70
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  wire width 1 $19
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $20
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \wr_detect$14
-    connect \Y $19
+  process $group_25
+    assign \oper_r__insn_type 7'0000000
+    assign \oper_r__fn_unit 11'00000000000
+    assign \oper_r__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \oper_r__imm_data__imm_ok 1'0
+    assign \oper_r__rc__rc 1'0
+    assign \oper_r__rc__rc_ok 1'0
+    assign \oper_r__oe__oe 1'0
+    assign \oper_r__oe__oe_ok 1'0
+    assign { } 0'0
+    assign \oper_r__input_carry 2'00
+    assign \oper_r__output_carry 1'0
+    assign \oper_r__input_cr 1'0
+    assign \oper_r__output_cr 1'0
+    assign \oper_r__is_32bit 1'0
+    assign \oper_r__is_signed 1'0
+    assign \oper_r__insn 32'00000000000000000000000000000000
+    assign { \oper_r__insn \oper_r__is_signed \oper_r__is_32bit \oper_r__output_cr \oper_r__input_cr \oper_r__output_carry \oper_r__input_carry { } { \oper_r__oe__oe_ok \oper_r__oe__oe } { \oper_r__rc__rc_ok \oper_r__rc__rc } { \oper_r__imm_data__imm_ok \oper_r__imm_data__imm } \oper_r__fn_unit \oper_r__insn_type } $70
+    sync init
   end
-  process $group_5
-    assign \src38__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $17 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest18__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src38__data_o \dest18__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest28__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src38__data_o \dest28__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $19 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \src38__data_o \reg
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \src38__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
-    sync init
-  end
-  process $group_6
-    assign \reg$next \reg
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-    switch { \dest18__wen }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-      case 1'1
-        assign \reg$next \dest18__data_i
-    end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-    switch { \dest28__wen }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+  process $group_41
+    assign \oper_l__insn_type$next \oper_l__insn_type
+    assign \oper_l__fn_unit$next \oper_l__fn_unit
+    assign \oper_l__imm_data__imm$next \oper_l__imm_data__imm
+    assign \oper_l__imm_data__imm_ok$next \oper_l__imm_data__imm_ok
+    assign \oper_l__rc__rc$next \oper_l__rc__rc
+    assign \oper_l__rc__rc_ok$next \oper_l__rc__rc_ok
+    assign \oper_l__oe__oe$next \oper_l__oe__oe
+    assign \oper_l__oe__oe_ok$next \oper_l__oe__oe_ok
+    assign { } { }
+    assign \oper_l__input_carry$next \oper_l__input_carry
+    assign \oper_l__output_carry$next \oper_l__output_carry
+    assign \oper_l__input_cr$next \oper_l__input_cr
+    assign \oper_l__output_cr$next \oper_l__output_cr
+    assign \oper_l__is_32bit$next \oper_l__is_32bit
+    assign \oper_l__is_signed$next \oper_l__is_signed
+    assign \oper_l__insn$next \oper_l__insn
+    attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
+    switch { \cu_issue_i }
+      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
       case 1'1
-        assign \reg$next \dest28__data_i
+        assign { \oper_l__insn$next \oper_l__is_signed$next \oper_l__is_32bit$next \oper_l__output_cr$next \oper_l__input_cr$next \oper_l__output_carry$next \oper_l__input_carry$next { } { \oper_l__oe__oe_ok$next \oper_l__oe__oe$next } { \oper_l__rc__rc_ok$next \oper_l__rc__rc$next } { \oper_l__imm_data__imm_ok$next \oper_l__imm_data__imm$next } \oper_l__fn_unit$next \oper_l__insn_type$next } { \oper_i_alu_shift_rot0__insn \oper_i_alu_shift_rot0__is_signed \oper_i_alu_shift_rot0__is_32bit \oper_i_alu_shift_rot0__output_cr \oper_i_alu_shift_rot0__input_cr \oper_i_alu_shift_rot0__output_carry \oper_i_alu_shift_rot0__input_carry { } { \oper_i_alu_shift_rot0__oe__oe_ok \oper_i_alu_shift_rot0__oe__oe } { \oper_i_alu_shift_rot0__rc__rc_ok \oper_i_alu_shift_rot0__rc__rc } { \oper_i_alu_shift_rot0__imm_data__imm_ok \oper_i_alu_shift_rot0__imm_data__imm } \oper_i_alu_shift_rot0__fn_unit \oper_i_alu_shift_rot0__insn_type }
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
-        assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
+        assign \oper_l__imm_data__imm$next 64'0000000000000000000000000000000000000000000000000000000000000000
+        assign \oper_l__imm_data__imm_ok$next 1'0
+        assign \oper_l__rc__rc$next 1'0
+        assign \oper_l__rc__rc_ok$next 1'0
+        assign \oper_l__oe__oe$next 1'0
+        assign \oper_l__oe__oe_ok$next 1'0
     end
     sync init
-      update \reg 64'0000000000000000000000000000000000000000000000000000000000000000
-    sync posedge \clk
-      update \reg \reg$next
+      update \oper_l__insn_type 7'0000000
+      update \oper_l__fn_unit 11'00000000000
+      update \oper_l__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
+      update \oper_l__imm_data__imm_ok 1'0
+      update \oper_l__rc__rc 1'0
+      update \oper_l__rc__rc_ok 1'0
+      update \oper_l__oe__oe 1'0
+      update \oper_l__oe__oe_ok 1'0
+      update { } 0'0
+      update \oper_l__input_carry 2'00
+      update \oper_l__output_carry 1'0
+      update \oper_l__input_cr 1'0
+      update \oper_l__output_cr 1'0
+      update \oper_l__is_32bit 1'0
+      update \oper_l__is_signed 1'0
+      update \oper_l__insn 32'00000000000000000000000000000000
+    sync posedge \coresync_clk
+      update \oper_l__insn_type \oper_l__insn_type$next
+      update \oper_l__fn_unit \oper_l__fn_unit$next
+      update \oper_l__imm_data__imm \oper_l__imm_data__imm$next
+      update \oper_l__imm_data__imm_ok \oper_l__imm_data__imm_ok$next
+      update \oper_l__rc__rc \oper_l__rc__rc$next
+      update \oper_l__rc__rc_ok \oper_l__rc__rc_ok$next
+      update \oper_l__oe__oe \oper_l__oe__oe$next
+      update \oper_l__oe__oe_ok \oper_l__oe__oe_ok$next
+      update { } { }
+      update \oper_l__input_carry \oper_l__input_carry$next
+      update \oper_l__output_carry \oper_l__output_carry$next
+      update \oper_l__input_cr \oper_l__input_cr$next
+      update \oper_l__output_cr \oper_l__output_cr$next
+      update \oper_l__is_32bit \oper_l__is_32bit$next
+      update \oper_l__is_signed \oper_l__is_signed$next
+      update \oper_l__insn \oper_l__insn$next
   end
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.int.reg_9"
-module \reg_9
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 2 \src19__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 3 \src19__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 4 \src29__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 5 \src29__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 6 \src39__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 7 \src39__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 8 \dest19__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 9 \dest19__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 10 \dest29__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 11 \dest29__data_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $2
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+  wire width 64 \data_r0__o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+  wire width 1 \data_r0__o_ok
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+  wire width 64 \data_r0_l__o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+  wire width 64 \data_r0_l__o$next
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+  wire width 1 \data_r0_l__o_ok
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+  wire width 1 \data_r0_l__o_ok$next
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
+  wire width 65 $72
+  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744"
+  wire width 1 $73
+  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744"
+  cell $reduce_bool $74
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
+    parameter \A_WIDTH 3
     parameter \Y_WIDTH 1
-    connect \A \src19__ren
-    connect \B 1'1
-    connect \Y $1
+    connect \A \alu_pulsem
+    connect \Y $73
   end
-  process $group_0
-    assign \wr_detect 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $1 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        assign \wr_detect 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest19__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest29__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-    end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
+  cell $mux $75
+    parameter \WIDTH 65
+    connect \A { \data_r0_l__o_ok \data_r0_l__o }
+    connect \B { \o_ok \alu_shift_rot0_o }
+    connect \S $73
+    connect \Y $72
+  end
+  process $group_57
+    assign \data_r0__o 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \data_r0__o_ok 1'0
+    assign { \data_r0__o_ok \data_r0__o } $72
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $3
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $4
+  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
+  wire width 1 $76
+  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
+  cell $reduce_bool $77
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
+    parameter \A_WIDTH 3
     parameter \Y_WIDTH 1
-    connect \A \src19__ren
-    connect \B 1'1
-    connect \Y $3
+    connect \A \alu_pulsem
+    connect \Y $76
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  wire width 1 $5
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $6
+  process $group_59
+    assign \data_r0_l__o$next \data_r0_l__o
+    assign \data_r0_l__o_ok$next \data_r0_l__o_ok
+    attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
+    switch { $76 }
+      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
+      case 1'1
+        assign { \data_r0_l__o_ok$next \data_r0_l__o$next } { \o_ok \alu_shift_rot0_o }
+    end
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
+      case 1'1
+        assign \data_r0_l__o_ok$next 1'0
+    end
+    sync init
+      update \data_r0_l__o 64'0000000000000000000000000000000000000000000000000000000000000000
+      update \data_r0_l__o_ok 1'0
+    sync posedge \coresync_clk
+      update \data_r0_l__o \data_r0_l__o$next
+      update \data_r0_l__o_ok \data_r0_l__o_ok$next
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+  wire width 4 \data_r1__cr_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+  wire width 1 \data_r1__cr_a_ok
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+  wire width 4 \data_r1_l__cr_a
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+  wire width 4 \data_r1_l__cr_a$next
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+  wire width 1 \data_r1_l__cr_a_ok
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+  wire width 1 \data_r1_l__cr_a_ok$next
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
+  wire width 5 $78
+  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744"
+  wire width 1 $79
+  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744"
+  cell $reduce_bool $80
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
+    parameter \A_WIDTH 3
     parameter \Y_WIDTH 1
-    connect \A \wr_detect
-    connect \Y $5
+    connect \A \alu_pulsem
+    connect \Y $79
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
-  wire width 64 \reg
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
-  wire width 64 \reg$next
-  process $group_1
-    assign \src19__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $3 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest19__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src19__data_o \dest19__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest29__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src19__data_o \dest29__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $5 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \src19__data_o \reg
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \src19__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
+  cell $mux $81
+    parameter \WIDTH 5
+    connect \A { \data_r1_l__cr_a_ok \data_r1_l__cr_a }
+    connect \B { \cr_a_ok \alu_shift_rot0_cr_a }
+    connect \S $79
+    connect \Y $78
+  end
+  process $group_61
+    assign \data_r1__cr_a 4'0000
+    assign \data_r1__cr_a_ok 1'0
+    assign { \data_r1__cr_a_ok \data_r1__cr_a } $78
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect$7
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $8
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $9
+  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
+  wire width 1 $82
+  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
+  cell $reduce_bool $83
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
+    parameter \A_WIDTH 3
     parameter \Y_WIDTH 1
-    connect \A \src29__ren
-    connect \B 1'1
-    connect \Y $8
+    connect \A \alu_pulsem
+    connect \Y $82
   end
-  process $group_2
-    assign \wr_detect$7 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $8 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  process $group_63
+    assign \data_r1_l__cr_a$next \data_r1_l__cr_a
+    assign \data_r1_l__cr_a_ok$next \data_r1_l__cr_a_ok
+    attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
+    switch { $82 }
+      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
       case 1'1
-        assign \wr_detect$7 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest19__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$7 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest29__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$7 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
+        assign { \data_r1_l__cr_a_ok$next \data_r1_l__cr_a$next } { \cr_a_ok \alu_shift_rot0_cr_a }
+    end
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
+      case 1'1
+        assign \data_r1_l__cr_a_ok$next 1'0
     end
     sync init
+      update \data_r1_l__cr_a 4'0000
+      update \data_r1_l__cr_a_ok 1'0
+    sync posedge \coresync_clk
+      update \data_r1_l__cr_a \data_r1_l__cr_a$next
+      update \data_r1_l__cr_a_ok \data_r1_l__cr_a_ok$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $10
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $11
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+  wire width 2 \data_r2__xer_ca
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:270"
+  wire width 1 \data_r2__xer_ca_ok
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+  wire width 2 \data_r2_l__xer_ca
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+  wire width 2 \data_r2_l__xer_ca$next
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+  wire width 1 \data_r2_l__xer_ca_ok
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+  wire width 1 \data_r2_l__xer_ca_ok$next
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
+  wire width 3 $84
+  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744"
+  wire width 1 $85
+  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:744"
+  cell $reduce_bool $86
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
+    parameter \A_WIDTH 3
     parameter \Y_WIDTH 1
-    connect \A \src29__ren
-    connect \B 1'1
-    connect \Y $10
+    connect \A \alu_pulsem
+    connect \Y $85
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  wire width 1 $12
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $13
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
+  cell $mux $87
+    parameter \WIDTH 3
+    connect \A { \data_r2_l__xer_ca_ok \data_r2_l__xer_ca }
+    connect \B { \xer_ca_ok \alu_shift_rot0_xer_ca }
+    connect \S $85
+    connect \Y $84
+  end
+  process $group_65
+    assign \data_r2__xer_ca 2'00
+    assign \data_r2__xer_ca_ok 1'0
+    assign { \data_r2__xer_ca_ok \data_r2__xer_ca } $84
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
+  wire width 1 $88
+  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
+  cell $reduce_bool $89
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
+    parameter \A_WIDTH 3
     parameter \Y_WIDTH 1
-    connect \A \wr_detect$7
-    connect \Y $12
+    connect \A \alu_pulsem
+    connect \Y $88
   end
-  process $group_3
-    assign \src29__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $10 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  process $group_67
+    assign \data_r2_l__xer_ca$next \data_r2_l__xer_ca
+    assign \data_r2_l__xer_ca_ok$next \data_r2_l__xer_ca_ok
+    attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
+    switch { $88 }
+      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest19__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src29__data_o \dest19__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest29__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src29__data_o \dest29__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $12 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \src29__data_o \reg
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \src29__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+        assign { \data_r2_l__xer_ca_ok$next \data_r2_l__xer_ca$next } { \xer_ca_ok \alu_shift_rot0_xer_ca }
+    end
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
+      case 1'1
+        assign \data_r2_l__xer_ca_ok$next 1'0
     end
     sync init
+      update \data_r2_l__xer_ca 2'00
+      update \data_r2_l__xer_ca_ok 1'0
+    sync posedge \coresync_clk
+      update \data_r2_l__xer_ca \data_r2_l__xer_ca$next
+      update \data_r2_l__xer_ca_ok \data_r2_l__xer_ca_ok$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect$14
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $15
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $16
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278"
+  wire width 1 $90
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278"
+  cell $and $91
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src39__ren
-    connect \B 1'1
-    connect \Y $15
-  end
-  process $group_4
-    assign \wr_detect$14 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $15 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        assign \wr_detect$14 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest19__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$14 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest29__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$14 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-    end
-    sync init
+    connect \A \data_r0__o_ok
+    connect \B \cu_busy_o
+    connect \Y $90
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $17
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $18
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278"
+  wire width 1 $92
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278"
+  cell $and $93
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src39__ren
-    connect \B 1'1
-    connect \Y $17
+    connect \A \data_r1__cr_a_ok
+    connect \B \cu_busy_o
+    connect \Y $92
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  wire width 1 $19
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $20
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278"
+  wire width 1 $94
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:278"
+  cell $and $95
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr_detect$14
-    connect \Y $19
+    connect \A \data_r2__xer_ca_ok
+    connect \B \cu_busy_o
+    connect \Y $94
   end
-  process $group_5
-    assign \src39__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $17 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest19__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src39__data_o \dest19__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest29__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src39__data_o \dest29__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $19 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \src39__data_o \reg
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \src39__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
+  process $group_69
+    assign \cu_wrmask_o 3'000
+    assign \cu_wrmask_o { $94 $92 $90 }
     sync init
   end
-  process $group_6
-    assign \reg$next \reg
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-    switch { \dest19__wen }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+  process $group_70
+    assign \alu_shift_rot0_sr_op__insn_type 7'0000000
+    assign \alu_shift_rot0_sr_op__fn_unit 11'00000000000
+    assign \alu_shift_rot0_sr_op__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \alu_shift_rot0_sr_op__imm_data__imm_ok 1'0
+    assign \alu_shift_rot0_sr_op__rc__rc 1'0
+    assign \alu_shift_rot0_sr_op__rc__rc_ok 1'0
+    assign \alu_shift_rot0_sr_op__oe__oe 1'0
+    assign \alu_shift_rot0_sr_op__oe__oe_ok 1'0
+    assign { } 0'0
+    assign \alu_shift_rot0_sr_op__input_carry 2'00
+    assign \alu_shift_rot0_sr_op__output_carry 1'0
+    assign \alu_shift_rot0_sr_op__input_cr 1'0
+    assign \alu_shift_rot0_sr_op__output_cr 1'0
+    assign \alu_shift_rot0_sr_op__is_32bit 1'0
+    assign \alu_shift_rot0_sr_op__is_signed 1'0
+    assign \alu_shift_rot0_sr_op__insn 32'00000000000000000000000000000000
+    assign { \alu_shift_rot0_sr_op__insn \alu_shift_rot0_sr_op__is_signed \alu_shift_rot0_sr_op__is_32bit \alu_shift_rot0_sr_op__output_cr \alu_shift_rot0_sr_op__input_cr \alu_shift_rot0_sr_op__output_carry \alu_shift_rot0_sr_op__input_carry { } { \alu_shift_rot0_sr_op__oe__oe_ok \alu_shift_rot0_sr_op__oe__oe } { \alu_shift_rot0_sr_op__rc__rc_ok \alu_shift_rot0_sr_op__rc__rc } { \alu_shift_rot0_sr_op__imm_data__imm_ok \alu_shift_rot0_sr_op__imm_data__imm } \alu_shift_rot0_sr_op__fn_unit \alu_shift_rot0_sr_op__insn_type } { \oper_r__insn \oper_r__is_signed \oper_r__is_32bit \oper_r__output_cr \oper_r__input_cr \oper_r__output_carry \oper_r__input_carry { } { \oper_r__oe__oe_ok \oper_r__oe__oe } { \oper_r__rc__rc_ok \oper_r__rc__rc } { \oper_r__imm_data__imm_ok \oper_r__imm_data__imm } \oper_r__fn_unit \oper_r__insn_type }
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:166"
+  wire width 1 \src_sel
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:167"
+  wire width 1 $96
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:167"
+  cell $mux $97
+    parameter \WIDTH 1
+    connect \A \src_l_q_src [1]
+    connect \B \opc_l_q_opc
+    connect \S \oper_r__imm_data__imm_ok
+    connect \Y $96
+  end
+  process $group_86
+    assign \src_sel 1'0
+    assign \src_sel $96
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:165"
+  wire width 64 \src_or_imm
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168"
+  wire width 64 $98
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168"
+  cell $mux $99
+    parameter \WIDTH 64
+    connect \A \src2_i
+    connect \B \oper_r__imm_data__imm
+    connect \S \oper_r__imm_data__imm_ok
+    connect \Y $98
+  end
+  process $group_87
+    assign \src_or_imm 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \src_or_imm $98
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
+  wire width 64 \src_r0
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
+  wire width 64 \src_r0$next
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
+  wire width 64 $100
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
+  cell $mux $101
+    parameter \WIDTH 64
+    connect \A \src_r0
+    connect \B \src1_i
+    connect \S \src_l_q_src [0]
+    connect \Y $100
+  end
+  process $group_88
+    assign \alu_shift_rot0_ra 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \alu_shift_rot0_ra $100
+    sync init
+  end
+  process $group_89
+    assign \src_r0$next \src_r0
+    attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
+    switch { \src_l_q_src [0] }
+      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
       case 1'1
-        assign \reg$next \dest19__data_i
+        assign \src_r0$next \src1_i
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-    switch { \dest29__wen }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+    sync init
+      update \src_r0 64'0000000000000000000000000000000000000000000000000000000000000000
+    sync posedge \coresync_clk
+      update \src_r0 \src_r0$next
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
+  wire width 64 \src_r1
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
+  wire width 64 \src_r1$next
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
+  wire width 64 $102
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
+  cell $mux $103
+    parameter \WIDTH 64
+    connect \A \src_r1
+    connect \B \src_or_imm
+    connect \S \src_sel
+    connect \Y $102
+  end
+  process $group_90
+    assign \alu_shift_rot0_rb 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \alu_shift_rot0_rb $102
+    sync init
+  end
+  process $group_91
+    assign \src_r1$next \src_r1
+    attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
+    switch { \src_sel }
+      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
       case 1'1
-        assign \reg$next \dest29__data_i
+        assign \src_r1$next \src_or_imm
     end
-    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    sync init
+      update \src_r1 64'0000000000000000000000000000000000000000000000000000000000000000
+    sync posedge \coresync_clk
+      update \src_r1 \src_r1$next
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
+  wire width 64 \src_r2
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
+  wire width 64 \src_r2$next
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
+  wire width 64 $104
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
+  cell $mux $105
+    parameter \WIDTH 64
+    connect \A \src_r2
+    connect \B \src3_i
+    connect \S \src_l_q_src [2]
+    connect \Y $104
+  end
+  process $group_92
+    assign \alu_shift_rot0_rc 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \alu_shift_rot0_rc $104
+    sync init
+  end
+  process $group_93
+    assign \src_r2$next \src_r2
+    attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
+    switch { \src_l_q_src [2] }
+      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
       case 1'1
-        assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
+        assign \src_r2$next \src3_i
     end
     sync init
-      update \reg 64'0000000000000000000000000000000000000000000000000000000000000000
-    sync posedge \clk
-      update \reg \reg$next
+      update \src_r2 64'0000000000000000000000000000000000000000000000000000000000000000
+    sync posedge \coresync_clk
+      update \src_r2 \src_r2$next
   end
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.int.reg_10"
-module \reg_10
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 2 \src110__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 3 \src110__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 4 \src210__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 5 \src210__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 6 \src310__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 7 \src310__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 8 \dest110__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 9 \dest110__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 10 \dest210__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 11 \dest210__data_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $2
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \src110__ren
-    connect \B 1'1
-    connect \Y $1
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
+  wire width 2 \src_r3
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
+  wire width 2 \src_r3$next
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
+  wire width 2 $106
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
+  cell $mux $107
+    parameter \WIDTH 2
+    connect \A \src_r3
+    connect \B \src4_i
+    connect \S \src_l_q_src [3]
+    connect \Y $106
   end
-  process $group_0
-    assign \wr_detect 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $1 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  process $group_94
+    assign \alu_shift_rot0_xer_ca$1 2'00
+    assign \alu_shift_rot0_xer_ca$1 $106
+    sync init
+  end
+  process $group_95
+    assign \src_r3$next \src_r3
+    attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
+    switch { \src_l_q_src [3] }
+      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
       case 1'1
-        assign \wr_detect 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest110__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest210__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
+        assign \src_r3$next \src4_i
     end
     sync init
+      update \src_r3 2'00
+    sync posedge \coresync_clk
+      update \src_r3 \src_r3$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $3
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $4
+  process $group_96
+    assign \alu_shift_rot0_p_valid_i 1'0
+    assign \alu_shift_rot0_p_valid_i \alui_l_q_alui
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:329"
+  wire width 1 $108
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:329"
+  cell $and $109
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src110__ren
-    connect \B 1'1
-    connect \Y $3
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  wire width 1 $5
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $6
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \wr_detect
-    connect \Y $5
+    connect \A \alu_shift_rot0_p_ready_o
+    connect \B \alui_l_q_alui
+    connect \Y $108
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
-  wire width 64 \reg
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
-  wire width 64 \reg$next
-  process $group_1
-    assign \src110__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $3 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  process $group_97
+    assign \alui_l_r_alui$next \alui_l_r_alui
+    assign \alui_l_r_alui$next $108
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest110__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src110__data_o \dest110__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest210__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src110__data_o \dest210__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $5 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \src110__data_o \reg
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \src110__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+        assign \alui_l_r_alui$next 1'1
     end
     sync init
+      update \alui_l_r_alui 1'1
+    sync posedge \coresync_clk
+      update \alui_l_r_alui \alui_l_r_alui$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect$7
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $8
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $9
+  process $group_98
+    assign \alui_l_s_alui 1'0
+    assign \alui_l_s_alui \all_rd_pulse
+    sync init
+  end
+  process $group_99
+    assign \alu_shift_rot0_n_ready_i 1'0
+    assign \alu_shift_rot0_n_ready_i \alu_l_q_alu
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:336"
+  wire width 1 $110
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:336"
+  cell $and $111
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src210__ren
-    connect \B 1'1
-    connect \Y $8
+    connect \A \alu_shift_rot0_n_valid_o
+    connect \B \alu_l_q_alu
+    connect \Y $110
   end
-  process $group_2
-    assign \wr_detect$7 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $8 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  process $group_100
+    assign \alu_l_r_alu$next \alu_l_r_alu
+    assign \alu_l_r_alu$next $110
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
       case 1'1
-        assign \wr_detect$7 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest110__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$7 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest210__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$7 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
+        assign \alu_l_r_alu$next 1'1
     end
+    sync init
+      update \alu_l_r_alu 1'1
+    sync posedge \coresync_clk
+      update \alu_l_r_alu \alu_l_r_alu$next
+  end
+  process $group_101
+    assign \alu_l_s_alu 1'0
+    assign \alu_l_s_alu \all_rd_pulse
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $10
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $11
+  process $group_102
+    assign \cu_busy_o 1'0
+    assign \cu_busy_o \opc_l_q_opc
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+  wire width 4 $112
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+  cell $and $113
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
+    parameter \A_WIDTH 4
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \src210__ren
-    connect \B 1'1
-    connect \Y $10
+    parameter \B_WIDTH 4
+    parameter \Y_WIDTH 4
+    connect \A \src_l_q_src
+    connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o }
+    connect \Y $112
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  wire width 1 $12
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $13
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:172"
+  wire width 1 $114
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:172"
+  cell $not $115
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr_detect$7
-    connect \Y $12
+    connect \A \oper_r__imm_data__imm_ok
+    connect \Y $114
   end
-  process $group_3
-    assign \src210__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $10 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest110__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src210__data_o \dest110__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest210__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src210__data_o \dest210__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $12 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \src210__data_o \reg
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \src210__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+  wire width 4 $116
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+  cell $and $117
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 4
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 4
+    parameter \Y_WIDTH 4
+    connect \A $112
+    connect \B { 1'1 1'1 $114 1'1 }
+    connect \Y $116
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+  wire width 4 $118
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+  cell $not $119
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 4
+    parameter \Y_WIDTH 4
+    connect \A \cu_rdmaskn_i
+    connect \Y $118
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+  wire width 4 $120
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:349"
+  cell $and $121
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 4
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 4
+    parameter \Y_WIDTH 4
+    connect \A $116
+    connect \B $118
+    connect \Y $120
+  end
+  process $group_103
+    assign \cu_rd__rel_o 4'0000
+    assign \cu_rd__rel_o $120
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect$14
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $15
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $16
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:101"
+  wire width 1 \cu_shadown_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352"
+  wire width 1 $122
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352"
+  cell $and $123
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src310__ren
-    connect \B 1'1
-    connect \Y $15
+    connect \A \cu_busy_o
+    connect \B \cu_shadown_i
+    connect \Y $122
   end
-  process $group_4
-    assign \wr_detect$14 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $15 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        assign \wr_detect$14 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest110__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$14 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest210__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$14 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-    end
-    sync init
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352"
+  wire width 1 $124
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352"
+  cell $and $125
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \cu_busy_o
+    connect \B \cu_shadown_i
+    connect \Y $124
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $17
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $18
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352"
+  wire width 1 $126
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:352"
+  cell $and $127
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src310__ren
-    connect \B 1'1
-    connect \Y $17
+    connect \A \cu_busy_o
+    connect \B \cu_shadown_i
+    connect \Y $126
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  wire width 1 $19
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $20
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:353"
+  wire width 3 $128
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:353"
+  cell $and $129
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 3
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 3
+    parameter \Y_WIDTH 3
+    connect \A \req_l_q_req
+    connect \B { $122 $124 $126 }
+    connect \Y $128
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:353"
+  wire width 3 $130
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:353"
+  cell $and $131
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 3
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 3
+    parameter \Y_WIDTH 3
+    connect \A $128
+    connect \B \cu_wrmask_o
+    connect \Y $130
+  end
+  process $group_104
+    assign \cu_wr__rel_o 3'000
+    assign \cu_wr__rel_o $130
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
+  wire width 1 $132
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
+  cell $and $133
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr_detect$14
-    connect \Y $19
+    connect \A \cu_wr__go_i [0]
+    connect \B \cu_busy_o
+    connect \Y $132
   end
-  process $group_5
-    assign \src310__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $17 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  process $group_105
+    assign \dest1_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
+    switch { $132 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest110__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src310__data_o \dest110__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest210__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src310__data_o \dest210__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $19 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \src310__data_o \reg
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \src310__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+        assign \dest1_o { \data_r0__o_ok \data_r0__o } [63:0]
     end
     sync init
   end
-  process $group_6
-    assign \reg$next \reg
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-    switch { \dest110__wen }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-      case 1'1
-        assign \reg$next \dest110__data_i
-    end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-    switch { \dest210__wen }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-      case 1'1
-        assign \reg$next \dest210__data_i
-    end
-    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
+  wire width 1 $134
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
+  cell $and $135
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \cu_wr__go_i [1]
+    connect \B \cu_busy_o
+    connect \Y $134
+  end
+  process $group_106
+    assign \dest2_o 4'0000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
+    switch { $134 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
       case 1'1
-        assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
+        assign \dest2_o { \data_r1__cr_a_ok \data_r1__cr_a } [3:0]
     end
     sync init
-      update \reg 64'0000000000000000000000000000000000000000000000000000000000000000
-    sync posedge \clk
-      update \reg \reg$next
   end
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.int.reg_11"
-module \reg_11
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 2 \src111__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 3 \src111__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 4 \src211__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 5 \src211__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 6 \src311__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 7 \src311__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 8 \dest111__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 9 \dest111__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 10 \dest211__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 11 \dest211__data_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $2
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
+  wire width 1 $136
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
+  cell $and $137
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src111__ren
-    connect \B 1'1
-    connect \Y $1
+    connect \A \cu_wr__go_i [2]
+    connect \B \cu_busy_o
+    connect \Y $136
   end
-  process $group_0
-    assign \wr_detect 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $1 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  process $group_107
+    assign \dest3_o 2'00
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
+    switch { $136 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:357"
       case 1'1
-        assign \wr_detect 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest111__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest211__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
+        assign \dest3_o { \data_r2__xer_ca_ok \data_r2__xer_ca } [1:0]
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  connect \cu_go_die_i 1'0
+  connect \cu_shadown_i 1'1
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.opc_l"
+module \opc_l$119
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+  wire width 1 input 2 \s_opc
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+  wire width 1 input 3 \r_opc
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
+  wire width 1 output 4 \q_opc
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
+  wire width 1 \q_int
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
+  wire width 1 \q_int$next
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  wire width 1 $1
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  cell $not $2
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \r_opc
+    connect \Y $1
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
   wire width 1 $3
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $4
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  cell $and $4
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src111__ren
-    connect \B 1'1
+    connect \A \q_int
+    connect \B $1
     connect \Y $3
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
   wire width 1 $5
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $6
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  cell $or $6
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr_detect
+    connect \A $3
+    connect \B \s_opc
     connect \Y $5
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
-  wire width 64 \reg
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
-  wire width 64 \reg$next
-  process $group_1
-    assign \src111__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $3 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  process $group_0
+    assign \q_int$next \q_int
+    assign \q_int$next $5
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest111__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src111__data_o \dest111__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest211__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src111__data_o \dest211__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $5 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \src111__data_o \reg
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \src111__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+        assign \q_int$next 1'0
     end
     sync init
+      update \q_int 1'0
+    sync posedge \coresync_clk
+      update \q_int \q_int$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect$7
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $8
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $9
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  wire width 1 $7
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  cell $not $8
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \r_opc
+    connect \Y $7
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  wire width 1 $9
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  cell $and $10
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src211__ren
-    connect \B 1'1
-    connect \Y $8
-  end
-  process $group_2
-    assign \wr_detect$7 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $8 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        assign \wr_detect$7 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest111__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$7 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest211__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$7 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-    end
-    sync init
+    connect \A \q_int
+    connect \B $7
+    connect \Y $9
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $10
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $11
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  wire width 1 $11
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  cell $or $12
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src211__ren
-    connect \B 1'1
-    connect \Y $10
+    connect \A $9
+    connect \B \s_opc
+    connect \Y $11
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  wire width 1 $12
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $13
+  process $group_1
+    assign \q_opc 1'0
+    assign \q_opc $11
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
+  wire width 1 \qn_opc
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
+  wire width 1 $13
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
+  cell $not $14
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr_detect$7
-    connect \Y $12
+    connect \A \q_opc
+    connect \Y $13
   end
-  process $group_3
-    assign \src211__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $10 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest111__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src211__data_o \dest111__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest211__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src211__data_o \dest211__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $12 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \src211__data_o \reg
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \src211__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
+  process $group_2
+    assign \qn_opc 1'0
+    assign \qn_opc $13
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect$14
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62"
+  wire width 1 \qlq_opc
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
   wire width 1 $15
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $16
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
+  cell $or $16
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src311__ren
-    connect \B 1'1
+    connect \A \q_opc
+    connect \B \q_int
     connect \Y $15
   end
-  process $group_4
-    assign \wr_detect$14 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $15 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        assign \wr_detect$14 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest111__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$14 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest211__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$14 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-    end
+  process $group_3
+    assign \qlq_opc 1'0
+    assign \qlq_opc $15
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $17
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $18
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.src_l"
+module \src_l$120
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+  wire width 3 input 2 \s_src
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+  wire width 3 input 3 \r_src
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
+  wire width 3 output 4 \q_src
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
+  wire width 3 \q_int
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
+  wire width 3 \q_int$next
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  wire width 3 $1
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  cell $not $2
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \src311__ren
-    connect \B 1'1
-    connect \Y $17
+    parameter \A_WIDTH 3
+    parameter \Y_WIDTH 3
+    connect \A \r_src
+    connect \Y $1
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  wire width 1 $19
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $20
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  wire width 3 $3
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  cell $and $4
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \wr_detect$14
-    connect \Y $19
-  end
-  process $group_5
-    assign \src311__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $17 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest111__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src311__data_o \dest111__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest211__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src311__data_o \dest211__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $19 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \src311__data_o \reg
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \src311__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
-    sync init
+    parameter \A_WIDTH 3
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 3
+    parameter \Y_WIDTH 3
+    connect \A \q_int
+    connect \B $1
+    connect \Y $3
   end
-  process $group_6
-    assign \reg$next \reg
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-    switch { \dest111__wen }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-      case 1'1
-        assign \reg$next \dest111__data_i
-    end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-    switch { \dest211__wen }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-      case 1'1
-        assign \reg$next \dest211__data_i
-    end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  wire width 3 $5
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  cell $or $6
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 3
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 3
+    parameter \Y_WIDTH 3
+    connect \A $3
+    connect \B \s_src
+    connect \Y $5
+  end
+  process $group_0
+    assign \q_int$next \q_int
+    assign \q_int$next $5
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
-        assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
+        assign \q_int$next 3'000
     end
     sync init
-      update \reg 64'0000000000000000000000000000000000000000000000000000000000000000
-    sync posedge \clk
-      update \reg \reg$next
+      update \q_int 3'000
+    sync posedge \coresync_clk
+      update \q_int \q_int$next
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  wire width 3 $7
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  cell $not $8
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 3
+    parameter \Y_WIDTH 3
+    connect \A \r_src
+    connect \Y $7
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  wire width 3 $9
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  cell $and $10
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 3
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 3
+    parameter \Y_WIDTH 3
+    connect \A \q_int
+    connect \B $7
+    connect \Y $9
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  wire width 3 $11
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  cell $or $12
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 3
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 3
+    parameter \Y_WIDTH 3
+    connect \A $9
+    connect \B \s_src
+    connect \Y $11
+  end
+  process $group_1
+    assign \q_src 3'000
+    assign \q_src $11
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
+  wire width 3 \qn_src
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
+  wire width 3 $13
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
+  cell $not $14
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 3
+    parameter \Y_WIDTH 3
+    connect \A \q_src
+    connect \Y $13
+  end
+  process $group_2
+    assign \qn_src 3'000
+    assign \qn_src $13
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62"
+  wire width 3 \qlq_src
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
+  wire width 3 $15
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
+  cell $or $16
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 3
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 3
+    parameter \Y_WIDTH 3
+    connect \A \q_src
+    connect \B \q_int
+    connect \Y $15
+  end
+  process $group_3
+    assign \qlq_src 3'000
+    assign \qlq_src $15
+    sync init
   end
 end
 attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.int.reg_12"
-module \reg_12
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 2 \src112__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 3 \src112__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 4 \src212__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 5 \src212__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 6 \src312__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 7 \src312__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 8 \dest112__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 9 \dest112__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 10 \dest212__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 11 \dest212__data_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.alu_l"
+module \alu_l$121
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+  wire width 1 input 2 \s_alu
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+  wire width 1 input 3 \r_alu
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
+  wire width 1 output 4 \q_alu
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
+  wire width 1 \q_int
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
+  wire width 1 \q_int$next
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
   wire width 1 $1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $2
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  cell $not $2
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src112__ren
-    connect \B 1'1
+    connect \A \r_alu
     connect \Y $1
   end
-  process $group_0
-    assign \wr_detect 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $1 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        assign \wr_detect 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest112__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest212__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-    end
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
   wire width 1 $3
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $4
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  cell $and $4
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src112__ren
-    connect \B 1'1
+    connect \A \q_int
+    connect \B $1
     connect \Y $3
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
   wire width 1 $5
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $6
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  cell $or $6
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr_detect
+    connect \A $3
+    connect \B \s_alu
     connect \Y $5
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
-  wire width 64 \reg
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
-  wire width 64 \reg$next
-  process $group_1
-    assign \src112__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $3 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  process $group_0
+    assign \q_int$next \q_int
+    assign \q_int$next $5
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest112__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src112__data_o \dest112__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest212__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src112__data_o \dest212__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $5 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \src112__data_o \reg
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \src112__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+        assign \q_int$next 1'0
     end
     sync init
+      update \q_int 1'0
+    sync posedge \coresync_clk
+      update \q_int \q_int$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect$7
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $8
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $9
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  wire width 1 $7
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  cell $not $8
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \r_alu
+    connect \Y $7
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  wire width 1 $9
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  cell $and $10
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src212__ren
-    connect \B 1'1
-    connect \Y $8
-  end
-  process $group_2
-    assign \wr_detect$7 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $8 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        assign \wr_detect$7 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest112__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$7 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest212__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$7 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-    end
-    sync init
+    connect \A \q_int
+    connect \B $7
+    connect \Y $9
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $10
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $11
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  wire width 1 $11
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  cell $or $12
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src212__ren
-    connect \B 1'1
-    connect \Y $10
+    connect \A $9
+    connect \B \s_alu
+    connect \Y $11
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  wire width 1 $12
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $13
+  process $group_1
+    assign \q_alu 1'0
+    assign \q_alu $11
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
+  wire width 1 \qn_alu
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
+  wire width 1 $13
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
+  cell $not $14
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr_detect$7
-    connect \Y $12
+    connect \A \q_alu
+    connect \Y $13
   end
-  process $group_3
-    assign \src212__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $10 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest112__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src212__data_o \dest112__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest212__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src212__data_o \dest212__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $12 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \src212__data_o \reg
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \src212__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
+  process $group_2
+    assign \qn_alu 1'0
+    assign \qn_alu $13
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect$14
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62"
+  wire width 1 \qlq_alu
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
   wire width 1 $15
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $16
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
+  cell $or $16
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src312__ren
-    connect \B 1'1
+    connect \A \q_alu
+    connect \B \q_int
     connect \Y $15
   end
-  process $group_4
-    assign \wr_detect$14 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $15 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        assign \wr_detect$14 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest112__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$14 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest212__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$14 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-    end
+  process $group_3
+    assign \qlq_alu 1'0
+    assign \qlq_alu $15
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $17
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $18
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.adr_l"
+module \adr_l
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+  wire width 1 input 2 \s_adr
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+  wire width 1 input 3 \r_adr
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
+  wire width 1 output 4 \q_adr
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
+  wire width 1 \q_int
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
+  wire width 1 \q_int$next
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  wire width 1 $1
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  cell $not $2
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \r_adr
+    connect \Y $1
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  wire width 1 $3
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  cell $and $4
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src312__ren
-    connect \B 1'1
-    connect \Y $17
+    connect \A \q_int
+    connect \B $1
+    connect \Y $3
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  wire width 1 $19
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $20
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  wire width 1 $5
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  cell $or $6
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr_detect$14
-    connect \Y $19
+    connect \A $3
+    connect \B \s_adr
+    connect \Y $5
   end
-  process $group_5
-    assign \src312__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $17 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  process $group_0
+    assign \q_int$next \q_int
+    assign \q_int$next $5
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest112__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src312__data_o \dest112__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest212__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src312__data_o \dest212__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $19 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \src312__data_o \reg
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \src312__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+        assign \q_int$next 1'0
     end
     sync init
+      update \q_int 1'0
+    sync posedge \coresync_clk
+      update \q_int \q_int$next
   end
-  process $group_6
-    assign \reg$next \reg
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-    switch { \dest112__wen }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-      case 1'1
-        assign \reg$next \dest112__data_i
-    end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-    switch { \dest212__wen }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-      case 1'1
-        assign \reg$next \dest212__data_i
-    end
-    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
-      case 1'1
-        assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
-    sync init
-      update \reg 64'0000000000000000000000000000000000000000000000000000000000000000
-    sync posedge \clk
-      update \reg \reg$next
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  wire width 1 $7
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  cell $not $8
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \r_adr
+    connect \Y $7
   end
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.int.reg_13"
-module \reg_13
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 2 \src113__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 3 \src113__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 4 \src213__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 5 \src213__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 6 \src313__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 7 \src313__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 8 \dest113__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 9 \dest113__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 10 \dest213__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 11 \dest213__data_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $2
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  wire width 1 $9
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  cell $and $10
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src113__ren
-    connect \B 1'1
-    connect \Y $1
-  end
-  process $group_0
-    assign \wr_detect 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $1 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        assign \wr_detect 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest113__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest213__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-    end
-    sync init
+    connect \A \q_int
+    connect \B $7
+    connect \Y $9
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $3
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $4
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  wire width 1 $11
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  cell $or $12
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src113__ren
-    connect \B 1'1
-    connect \Y $3
+    connect \A $9
+    connect \B \s_adr
+    connect \Y $11
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  wire width 1 $5
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $6
+  process $group_1
+    assign \q_adr 1'0
+    assign \q_adr $11
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
+  wire width 1 \qn_adr
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
+  wire width 1 $13
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
+  cell $not $14
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr_detect
-    connect \Y $5
+    connect \A \q_adr
+    connect \Y $13
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
-  wire width 64 \reg
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
-  wire width 64 \reg$next
-  process $group_1
-    assign \src113__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $3 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest113__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src113__data_o \dest113__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest213__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src113__data_o \dest213__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $5 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \src113__data_o \reg
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \src113__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
+  process $group_2
+    assign \qn_adr 1'0
+    assign \qn_adr $13
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect$7
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $8
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $9
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62"
+  wire width 1 \qlq_adr
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
+  wire width 1 $15
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
+  cell $or $16
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src213__ren
-    connect \B 1'1
-    connect \Y $8
+    connect \A \q_adr
+    connect \B \q_int
+    connect \Y $15
   end
-  process $group_2
-    assign \wr_detect$7 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $8 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        assign \wr_detect$7 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest113__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$7 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest213__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$7 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-    end
+  process $group_3
+    assign \qlq_adr 1'0
+    assign \qlq_adr $15
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $10
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $11
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.lod_l"
+module \lod_l
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+  wire width 1 input 2 \s_lod
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+  wire width 1 input 3 \r_lod
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
+  wire width 1 output 4 \qn_lod
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
+  wire width 1 \q_int
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
+  wire width 1 \q_int$next
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  wire width 1 $1
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  cell $not $2
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \r_lod
+    connect \Y $1
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  wire width 1 $3
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  cell $and $4
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src213__ren
-    connect \B 1'1
-    connect \Y $10
+    connect \A \q_int
+    connect \B $1
+    connect \Y $3
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  wire width 1 $12
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $13
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  wire width 1 $5
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  cell $or $6
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr_detect$7
-    connect \Y $12
+    connect \A $3
+    connect \B \s_lod
+    connect \Y $5
   end
-  process $group_3
-    assign \src213__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $10 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  process $group_0
+    assign \q_int$next \q_int
+    assign \q_int$next $5
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest113__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src213__data_o \dest113__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest213__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src213__data_o \dest213__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $12 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \src213__data_o \reg
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \src213__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+        assign \q_int$next 1'0
     end
     sync init
+      update \q_int 1'0
+    sync posedge \coresync_clk
+      update \q_int \q_int$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect$14
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $15
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $16
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
+  wire width 1 \q_lod
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  wire width 1 $7
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  cell $not $8
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \r_lod
+    connect \Y $7
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  wire width 1 $9
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  cell $and $10
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src313__ren
-    connect \B 1'1
-    connect \Y $15
-  end
-  process $group_4
-    assign \wr_detect$14 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $15 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        assign \wr_detect$14 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest113__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$14 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest213__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$14 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-    end
-    sync init
+    connect \A \q_int
+    connect \B $7
+    connect \Y $9
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $17
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $18
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  wire width 1 $11
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  cell $or $12
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src313__ren
-    connect \B 1'1
-    connect \Y $17
+    connect \A $9
+    connect \B \s_lod
+    connect \Y $11
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  wire width 1 $19
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $20
+  process $group_1
+    assign \q_lod 1'0
+    assign \q_lod $11
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
+  wire width 1 $13
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
+  cell $not $14
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr_detect$14
-    connect \Y $19
+    connect \A \q_lod
+    connect \Y $13
   end
-  process $group_5
-    assign \src313__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $17 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest113__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src313__data_o \dest113__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest213__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src313__data_o \dest213__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $19 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \src313__data_o \reg
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \src313__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
+  process $group_2
+    assign \qn_lod 1'0
+    assign \qn_lod $13
     sync init
   end
-  process $group_6
-    assign \reg$next \reg
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-    switch { \dest113__wen }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-      case 1'1
-        assign \reg$next \dest113__data_i
-    end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-    switch { \dest213__wen }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-      case 1'1
-        assign \reg$next \dest213__data_i
-    end
-    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
-      case 1'1
-        assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62"
+  wire width 1 \qlq_lod
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
+  wire width 1 $15
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
+  cell $or $16
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \q_lod
+    connect \B \q_int
+    connect \Y $15
+  end
+  process $group_3
+    assign \qlq_lod 1'0
+    assign \qlq_lod $15
     sync init
-      update \reg 64'0000000000000000000000000000000000000000000000000000000000000000
-    sync posedge \clk
-      update \reg \reg$next
   end
 end
 attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.int.reg_14"
-module \reg_14
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 2 \src114__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 3 \src114__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 4 \src214__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 5 \src214__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 6 \src314__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 7 \src314__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 8 \dest114__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 9 \dest114__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 10 \dest214__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 11 \dest214__data_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.sto_l"
+module \sto_l
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+  wire width 1 input 2 \s_sto
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+  wire width 1 input 3 \r_sto
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
+  wire width 1 output 4 \q_sto
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
+  wire width 1 \q_int
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
+  wire width 1 \q_int$next
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
   wire width 1 $1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $2
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  cell $not $2
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \r_sto
+    connect \Y $1
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  wire width 1 $3
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  cell $and $4
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src114__ren
-    connect \B 1'1
-    connect \Y $1
+    connect \A \q_int
+    connect \B $1
+    connect \Y $3
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  wire width 1 $5
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  cell $or $6
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $3
+    connect \B \s_sto
+    connect \Y $5
   end
   process $group_0
-    assign \wr_detect 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $1 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    assign \q_int$next \q_int
+    assign \q_int$next $5
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
       case 1'1
-        assign \wr_detect 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest114__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest214__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
+        assign \q_int$next 1'0
     end
     sync init
+      update \q_int 1'0
+    sync posedge \coresync_clk
+      update \q_int \q_int$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $3
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $4
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  wire width 1 $7
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  cell $not $8
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \r_sto
+    connect \Y $7
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  wire width 1 $9
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  cell $and $10
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src114__ren
-    connect \B 1'1
-    connect \Y $3
+    connect \A \q_int
+    connect \B $7
+    connect \Y $9
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  wire width 1 $5
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $6
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  wire width 1 $11
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  cell $or $12
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr_detect
-    connect \Y $5
+    connect \A $9
+    connect \B \s_sto
+    connect \Y $11
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
-  wire width 64 \reg
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
-  wire width 64 \reg$next
   process $group_1
-    assign \src114__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $3 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest114__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src114__data_o \dest114__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest214__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src114__data_o \dest214__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $5 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \src114__data_o \reg
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \src114__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
+    assign \q_sto 1'0
+    assign \q_sto $11
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect$7
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $8
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $9
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
+  wire width 1 \qn_sto
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
+  wire width 1 $13
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
+  cell $not $14
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src214__ren
-    connect \B 1'1
-    connect \Y $8
+    connect \A \q_sto
+    connect \Y $13
   end
   process $group_2
-    assign \wr_detect$7 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $8 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        assign \wr_detect$7 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest114__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$7 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest214__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$7 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-    end
+    assign \qn_sto 1'0
+    assign \qn_sto $13
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $10
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $11
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62"
+  wire width 1 \qlq_sto
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
+  wire width 1 $15
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
+  cell $or $16
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src214__ren
-    connect \B 1'1
-    connect \Y $10
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  wire width 1 $12
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $13
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \wr_detect$7
-    connect \Y $12
+    connect \A \q_sto
+    connect \B \q_int
+    connect \Y $15
   end
   process $group_3
-    assign \src214__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $10 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest114__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src214__data_o \dest114__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest214__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src214__data_o \dest214__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $12 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \src214__data_o \reg
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \src214__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
+    assign \qlq_sto 1'0
+    assign \qlq_sto $15
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect$14
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $15
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $16
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.wri_l"
+module \wri_l
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+  wire width 1 input 2 \s_wri
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+  wire width 1 input 3 \r_wri
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
+  wire width 1 output 4 \q_wri
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
+  wire width 1 \q_int
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
+  wire width 1 \q_int$next
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  wire width 1 $1
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  cell $not $2
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src314__ren
-    connect \B 1'1
-    connect \Y $15
-  end
-  process $group_4
-    assign \wr_detect$14 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $15 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        assign \wr_detect$14 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest114__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$14 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest214__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$14 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-    end
-    sync init
+    connect \A \r_wri
+    connect \Y $1
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $17
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $18
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  wire width 1 $3
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  cell $and $4
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src314__ren
-    connect \B 1'1
-    connect \Y $17
+    connect \A \q_int
+    connect \B $1
+    connect \Y $3
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  wire width 1 $19
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $20
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  wire width 1 $5
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  cell $or $6
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr_detect$14
-    connect \Y $19
-  end
-  process $group_5
-    assign \src314__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $17 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest114__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src314__data_o \dest114__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest214__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src314__data_o \dest214__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $19 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \src314__data_o \reg
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \src314__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
-    sync init
+    connect \A $3
+    connect \B \s_wri
+    connect \Y $5
   end
-  process $group_6
-    assign \reg$next \reg
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-    switch { \dest114__wen }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-      case 1'1
-        assign \reg$next \dest114__data_i
-    end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-    switch { \dest214__wen }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-      case 1'1
-        assign \reg$next \dest214__data_i
-    end
+  process $group_0
+    assign \q_int$next \q_int
+    assign \q_int$next $5
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
-        assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
+        assign \q_int$next 1'0
     end
     sync init
-      update \reg 64'0000000000000000000000000000000000000000000000000000000000000000
-    sync posedge \clk
-      update \reg \reg$next
+      update \q_int 1'0
+    sync posedge \coresync_clk
+      update \q_int \q_int$next
   end
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.int.reg_15"
-module \reg_15
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 2 \src115__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 3 \src115__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 4 \src215__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 5 \src215__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 6 \src315__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 7 \src315__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 8 \dest115__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 9 \dest115__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 10 \dest215__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 11 \dest215__data_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $2
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  wire width 1 $7
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  cell $not $8
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src115__ren
-    connect \B 1'1
-    connect \Y $1
-  end
-  process $group_0
-    assign \wr_detect 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $1 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        assign \wr_detect 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest115__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest215__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-    end
-    sync init
+    connect \A \r_wri
+    connect \Y $7
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $3
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $4
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  wire width 1 $9
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  cell $and $10
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src115__ren
-    connect \B 1'1
-    connect \Y $3
+    connect \A \q_int
+    connect \B $7
+    connect \Y $9
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  wire width 1 $5
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $6
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  wire width 1 $11
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  cell $or $12
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr_detect
-    connect \Y $5
+    connect \A $9
+    connect \B \s_wri
+    connect \Y $11
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
-  wire width 64 \reg
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
-  wire width 64 \reg$next
   process $group_1
-    assign \src115__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $3 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest115__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src115__data_o \dest115__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest215__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src115__data_o \dest215__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $5 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \src115__data_o \reg
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \src115__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
+    assign \q_wri 1'0
+    assign \q_wri $11
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect$7
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $8
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $9
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
+  wire width 1 \qn_wri
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
+  wire width 1 $13
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
+  cell $not $14
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src215__ren
-    connect \B 1'1
-    connect \Y $8
+    connect \A \q_wri
+    connect \Y $13
   end
   process $group_2
-    assign \wr_detect$7 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $8 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        assign \wr_detect$7 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest115__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$7 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest215__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$7 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-    end
+    assign \qn_wri 1'0
+    assign \qn_wri $13
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $10
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $11
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62"
+  wire width 1 \qlq_wri
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
+  wire width 1 $15
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
+  cell $or $16
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src215__ren
-    connect \B 1'1
-    connect \Y $10
+    connect \A \q_wri
+    connect \B \q_int
+    connect \Y $15
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  wire width 1 $12
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $13
+  process $group_3
+    assign \qlq_wri 1'0
+    assign \qlq_wri $15
+    sync init
+  end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.upd_l"
+module \upd_l
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+  wire width 1 input 2 \s_upd
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+  wire width 1 input 3 \r_upd
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
+  wire width 1 output 4 \q_upd
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
+  wire width 1 \q_int
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
+  wire width 1 \q_int$next
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  wire width 1 $1
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  cell $not $2
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr_detect$7
-    connect \Y $12
+    connect \A \r_upd
+    connect \Y $1
   end
-  process $group_3
-    assign \src215__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $10 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest115__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src215__data_o \dest115__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest215__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src215__data_o \dest215__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $12 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \src215__data_o \reg
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \src215__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
-    sync init
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  wire width 1 $3
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  cell $and $4
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \q_int
+    connect \B $1
+    connect \Y $3
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect$14
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $15
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $16
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  wire width 1 $5
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  cell $or $6
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src315__ren
-    connect \B 1'1
-    connect \Y $15
+    connect \A $3
+    connect \B \s_upd
+    connect \Y $5
   end
-  process $group_4
-    assign \wr_detect$14 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $15 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  process $group_0
+    assign \q_int$next \q_int
+    assign \q_int$next $5
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
       case 1'1
-        assign \wr_detect$14 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest115__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$14 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest215__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$14 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
+        assign \q_int$next 1'0
     end
     sync init
+      update \q_int 1'0
+    sync posedge \coresync_clk
+      update \q_int \q_int$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $17
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $18
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  wire width 1 $7
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  cell $not $8
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \r_upd
+    connect \Y $7
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  wire width 1 $9
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  cell $and $10
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src315__ren
-    connect \B 1'1
-    connect \Y $17
+    connect \A \q_int
+    connect \B $7
+    connect \Y $9
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  wire width 1 $19
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $20
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  wire width 1 $11
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  cell $or $12
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr_detect$14
-    connect \Y $19
+    connect \A $9
+    connect \B \s_upd
+    connect \Y $11
   end
-  process $group_5
-    assign \src315__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $17 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest115__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src315__data_o \dest115__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest215__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src315__data_o \dest215__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $19 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \src315__data_o \reg
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \src315__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
+  process $group_1
+    assign \q_upd 1'0
+    assign \q_upd $11
     sync init
   end
-  process $group_6
-    assign \reg$next \reg
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-    switch { \dest115__wen }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-      case 1'1
-        assign \reg$next \dest115__data_i
-    end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-    switch { \dest215__wen }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-      case 1'1
-        assign \reg$next \dest215__data_i
-    end
-    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
-      case 1'1
-        assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
+  wire width 1 \qn_upd
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
+  wire width 1 $13
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
+  cell $not $14
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \q_upd
+    connect \Y $13
+  end
+  process $group_2
+    assign \qn_upd 1'0
+    assign \qn_upd $13
     sync init
-      update \reg 64'0000000000000000000000000000000000000000000000000000000000000000
-    sync posedge \clk
-      update \reg \reg$next
   end
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.int.reg_16"
-module \reg_16
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 2 \src116__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 3 \src116__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 4 \src216__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 5 \src216__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 6 \src316__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 7 \src316__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 8 \dest116__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 9 \dest116__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 10 \dest216__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 11 \dest216__data_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $2
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62"
+  wire width 1 \qlq_upd
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
+  wire width 1 $15
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
+  cell $or $16
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src116__ren
-    connect \B 1'1
-    connect \Y $1
+    connect \A \q_upd
+    connect \B \q_int
+    connect \Y $15
   end
-  process $group_0
-    assign \wr_detect 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $1 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        assign \wr_detect 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest116__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest216__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-    end
+  process $group_3
+    assign \qlq_upd 1'0
+    assign \qlq_upd $15
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.rst_l"
+module \rst_l$122
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+  wire width 1 input 2 \s_rst
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+  wire width 1 input 3 \r_rst
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
+  wire width 1 output 4 \q_rst
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
+  wire width 1 \q_int
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
+  wire width 1 \q_int$next
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  wire width 1 $1
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  cell $not $2
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \r_rst
+    connect \Y $1
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
   wire width 1 $3
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $4
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  cell $and $4
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src116__ren
-    connect \B 1'1
+    connect \A \q_int
+    connect \B $1
     connect \Y $3
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
   wire width 1 $5
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $6
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  cell $or $6
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr_detect
+    connect \A $3
+    connect \B \s_rst
     connect \Y $5
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
-  wire width 64 \reg
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
-  wire width 64 \reg$next
-  process $group_1
-    assign \src116__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $3 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  process $group_0
+    assign \q_int$next \q_int
+    assign \q_int$next $5
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest116__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src116__data_o \dest116__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest216__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src116__data_o \dest216__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $5 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \src116__data_o \reg
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \src116__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+        assign \q_int$next 1'0
     end
     sync init
+      update \q_int 1'0
+    sync posedge \coresync_clk
+      update \q_int \q_int$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect$7
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $8
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $9
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  wire width 1 $7
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  cell $not $8
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \r_rst
+    connect \Y $7
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  wire width 1 $9
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  cell $and $10
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src216__ren
-    connect \B 1'1
-    connect \Y $8
-  end
-  process $group_2
-    assign \wr_detect$7 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $8 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        assign \wr_detect$7 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest116__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$7 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest216__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$7 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-    end
-    sync init
+    connect \A \q_int
+    connect \B $7
+    connect \Y $9
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $10
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $11
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  wire width 1 $11
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  cell $or $12
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src216__ren
-    connect \B 1'1
-    connect \Y $10
+    connect \A $9
+    connect \B \s_rst
+    connect \Y $11
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  wire width 1 $12
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $13
+  process $group_1
+    assign \q_rst 1'0
+    assign \q_rst $11
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
+  wire width 1 \qn_rst
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
+  wire width 1 $13
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
+  cell $not $14
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr_detect$7
-    connect \Y $12
+    connect \A \q_rst
+    connect \Y $13
   end
-  process $group_3
-    assign \src216__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $10 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest116__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src216__data_o \dest116__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest216__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src216__data_o \dest216__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $12 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \src216__data_o \reg
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \src216__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
+  process $group_2
+    assign \qn_rst 1'0
+    assign \qn_rst $13
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect$14
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62"
+  wire width 1 \qlq_rst
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
   wire width 1 $15
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $16
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
+  cell $or $16
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src316__ren
-    connect \B 1'1
+    connect \A \q_rst
+    connect \B \q_int
     connect \Y $15
   end
-  process $group_4
-    assign \wr_detect$14 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $15 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        assign \wr_detect$14 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest116__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$14 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest216__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$14 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-    end
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $17
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $18
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \src316__ren
-    connect \B 1'1
-    connect \Y $17
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  wire width 1 $19
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $20
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \wr_detect$14
-    connect \Y $19
-  end
-  process $group_5
-    assign \src316__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $17 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest116__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src316__data_o \dest116__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest216__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src316__data_o \dest216__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $19 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \src316__data_o \reg
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \src316__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
-    sync init
-  end
-  process $group_6
-    assign \reg$next \reg
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-    switch { \dest116__wen }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-      case 1'1
-        assign \reg$next \dest116__data_i
-    end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-    switch { \dest216__wen }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-      case 1'1
-        assign \reg$next \dest216__data_i
-    end
-    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
-      case 1'1
-        assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
+  process $group_3
+    assign \qlq_rst 1'0
+    assign \qlq_rst $15
     sync init
-      update \reg 64'0000000000000000000000000000000000000000000000000000000000000000
-    sync posedge \clk
-      update \reg \reg$next
   end
 end
 attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.int.reg_17"
-module \reg_17
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 2 \src117__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 3 \src117__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 4 \src217__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 5 \src217__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 6 \src317__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 7 \src317__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 8 \dest117__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 9 \dest117__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 10 \dest217__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 11 \dest217__data_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.lsd_l"
+module \lsd_l
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+  wire width 1 input 2 \s_lsd
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+  wire width 1 input 3 \r_lsd
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
+  wire width 1 output 4 \q_lsd
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
+  wire width 1 \q_int
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
+  wire width 1 \q_int$next
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
   wire width 1 $1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $2
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  cell $not $2
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src117__ren
-    connect \B 1'1
+    connect \A \r_lsd
     connect \Y $1
   end
-  process $group_0
-    assign \wr_detect 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $1 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        assign \wr_detect 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest117__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest217__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-    end
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
   wire width 1 $3
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $4
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  cell $and $4
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src117__ren
-    connect \B 1'1
+    connect \A \q_int
+    connect \B $1
     connect \Y $3
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
   wire width 1 $5
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $6
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \wr_detect
-    connect \Y $5
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
-  wire width 64 \reg
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
-  wire width 64 \reg$next
-  process $group_1
-    assign \src117__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $3 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest117__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src117__data_o \dest117__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest217__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src117__data_o \dest217__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $5 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \src117__data_o \reg
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \src117__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect$7
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $8
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $9
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  cell $or $6
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src217__ren
-    connect \B 1'1
-    connect \Y $8
+    connect \A $3
+    connect \B \s_lsd
+    connect \Y $5
   end
-  process $group_2
-    assign \wr_detect$7 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $8 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  process $group_0
+    assign \q_int$next \q_int
+    assign \q_int$next $5
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
       case 1'1
-        assign \wr_detect$7 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest117__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$7 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest217__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$7 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
+        assign \q_int$next 1'0
     end
     sync init
+      update \q_int 1'0
+    sync posedge \coresync_clk
+      update \q_int \q_int$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $10
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $11
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \src217__ren
-    connect \B 1'1
-    connect \Y $10
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  wire width 1 $12
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $13
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  wire width 1 $7
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  cell $not $8
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr_detect$7
-    connect \Y $12
-  end
-  process $group_3
-    assign \src217__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $10 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest117__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src217__data_o \dest117__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest217__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src217__data_o \dest217__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $12 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \src217__data_o \reg
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \src217__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
-    sync init
+    connect \A \r_lsd
+    connect \Y $7
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect$14
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $15
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $16
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  wire width 1 $9
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  cell $and $10
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src317__ren
-    connect \B 1'1
-    connect \Y $15
-  end
-  process $group_4
-    assign \wr_detect$14 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $15 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        assign \wr_detect$14 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest117__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$14 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest217__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$14 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-    end
-    sync init
+    connect \A \q_int
+    connect \B $7
+    connect \Y $9
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $17
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $18
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  wire width 1 $11
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  cell $or $12
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src317__ren
-    connect \B 1'1
-    connect \Y $17
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  wire width 1 $19
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $20
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \wr_detect$14
-    connect \Y $19
-  end
-  process $group_5
-    assign \src317__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $17 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest117__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src317__data_o \dest117__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest217__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src317__data_o \dest217__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $19 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \src317__data_o \reg
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \src317__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
-    sync init
+    connect \A $9
+    connect \B \s_lsd
+    connect \Y $11
   end
-  process $group_6
-    assign \reg$next \reg
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-    switch { \dest117__wen }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-      case 1'1
-        assign \reg$next \dest117__data_i
-    end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-    switch { \dest217__wen }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-      case 1'1
-        assign \reg$next \dest217__data_i
-    end
-    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
-      case 1'1
-        assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
+  process $group_1
+    assign \q_lsd 1'0
+    assign \q_lsd $11
     sync init
-      update \reg 64'0000000000000000000000000000000000000000000000000000000000000000
-    sync posedge \clk
-      update \reg \reg$next
   end
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.int.reg_18"
-module \reg_18
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 2 \src118__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 3 \src118__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 4 \src218__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 5 \src218__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 6 \src318__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 7 \src318__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 8 \dest118__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 9 \dest118__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 10 \dest218__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 11 \dest218__data_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $2
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
+  wire width 1 \qn_lsd
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
+  wire width 1 $13
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
+  cell $not $14
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src118__ren
-    connect \B 1'1
-    connect \Y $1
+    connect \A \q_lsd
+    connect \Y $13
   end
-  process $group_0
-    assign \wr_detect 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $1 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        assign \wr_detect 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest118__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest218__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-    end
+  process $group_2
+    assign \qn_lsd 1'0
+    assign \qn_lsd $13
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $3
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $4
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62"
+  wire width 1 \qlq_lsd
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
+  wire width 1 $15
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
+  cell $or $16
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src118__ren
-    connect \B 1'1
-    connect \Y $3
+    connect \A \q_lsd
+    connect \B \q_int
+    connect \Y $15
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  wire width 1 $5
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $6
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \wr_detect
-    connect \Y $5
+  process $group_3
+    assign \qlq_lsd 1'0
+    assign \qlq_lsd $15
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
-  wire width 64 \reg
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
-  wire width 64 \reg$next
-  process $group_1
-    assign \src118__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $3 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest118__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src118__data_o \dest118__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest218__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src118__data_o \dest218__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $5 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \src118__data_o \reg
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \src118__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
-    sync init
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0"
+module \ldst0
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+  wire width 1 input 1 \cu_ad__go_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+  wire width 1 output 2 \cu_ad__rel_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+  wire width 1 input 3 \cu_st__go_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+  wire width 1 output 4 \cu_st__rel_o
+  attribute \enum_base_type "MicrOp"
+  attribute \enum_value_0000000 "OP_ILLEGAL"
+  attribute \enum_value_0000001 "OP_NOP"
+  attribute \enum_value_0000010 "OP_ADD"
+  attribute \enum_value_0000011 "OP_ADDPCIS"
+  attribute \enum_value_0000100 "OP_AND"
+  attribute \enum_value_0000101 "OP_ATTN"
+  attribute \enum_value_0000110 "OP_B"
+  attribute \enum_value_0000111 "OP_BC"
+  attribute \enum_value_0001000 "OP_BCREG"
+  attribute \enum_value_0001001 "OP_BPERM"
+  attribute \enum_value_0001010 "OP_CMP"
+  attribute \enum_value_0001011 "OP_CMPB"
+  attribute \enum_value_0001100 "OP_CMPEQB"
+  attribute \enum_value_0001101 "OP_CMPRB"
+  attribute \enum_value_0001110 "OP_CNTZ"
+  attribute \enum_value_0001111 "OP_CRAND"
+  attribute \enum_value_0010000 "OP_CRANDC"
+  attribute \enum_value_0010001 "OP_CREQV"
+  attribute \enum_value_0010010 "OP_CRNAND"
+  attribute \enum_value_0010011 "OP_CRNOR"
+  attribute \enum_value_0010100 "OP_CROR"
+  attribute \enum_value_0010101 "OP_CRORC"
+  attribute \enum_value_0010110 "OP_CRXOR"
+  attribute \enum_value_0010111 "OP_DARN"
+  attribute \enum_value_0011000 "OP_DCBF"
+  attribute \enum_value_0011001 "OP_DCBST"
+  attribute \enum_value_0011010 "OP_DCBT"
+  attribute \enum_value_0011011 "OP_DCBTST"
+  attribute \enum_value_0011100 "OP_DCBZ"
+  attribute \enum_value_0011101 "OP_DIV"
+  attribute \enum_value_0011110 "OP_DIVE"
+  attribute \enum_value_0011111 "OP_EXTS"
+  attribute \enum_value_0100000 "OP_EXTSWSLI"
+  attribute \enum_value_0100001 "OP_ICBI"
+  attribute \enum_value_0100010 "OP_ICBT"
+  attribute \enum_value_0100011 "OP_ISEL"
+  attribute \enum_value_0100100 "OP_ISYNC"
+  attribute \enum_value_0100101 "OP_LOAD"
+  attribute \enum_value_0100110 "OP_STORE"
+  attribute \enum_value_0100111 "OP_MADDHD"
+  attribute \enum_value_0101000 "OP_MADDHDU"
+  attribute \enum_value_0101001 "OP_MADDLD"
+  attribute \enum_value_0101010 "OP_MCRF"
+  attribute \enum_value_0101011 "OP_MCRXR"
+  attribute \enum_value_0101100 "OP_MCRXRX"
+  attribute \enum_value_0101101 "OP_MFCR"
+  attribute \enum_value_0101110 "OP_MFSPR"
+  attribute \enum_value_0101111 "OP_MOD"
+  attribute \enum_value_0110000 "OP_MTCRF"
+  attribute \enum_value_0110001 "OP_MTSPR"
+  attribute \enum_value_0110010 "OP_MUL_L64"
+  attribute \enum_value_0110011 "OP_MUL_H64"
+  attribute \enum_value_0110100 "OP_MUL_H32"
+  attribute \enum_value_0110101 "OP_OR"
+  attribute \enum_value_0110110 "OP_POPCNT"
+  attribute \enum_value_0110111 "OP_PRTY"
+  attribute \enum_value_0111000 "OP_RLC"
+  attribute \enum_value_0111001 "OP_RLCL"
+  attribute \enum_value_0111010 "OP_RLCR"
+  attribute \enum_value_0111011 "OP_SETB"
+  attribute \enum_value_0111100 "OP_SHL"
+  attribute \enum_value_0111101 "OP_SHR"
+  attribute \enum_value_0111110 "OP_SYNC"
+  attribute \enum_value_0111111 "OP_TRAP"
+  attribute \enum_value_1000011 "OP_XOR"
+  attribute \enum_value_1000100 "OP_SIM_CONFIG"
+  attribute \enum_value_1000101 "OP_CROP"
+  attribute \enum_value_1000110 "OP_RFID"
+  attribute \enum_value_1000111 "OP_MFMSR"
+  attribute \enum_value_1001000 "OP_MTMSRD"
+  attribute \enum_value_1001001 "OP_SC"
+  attribute \enum_value_1001010 "OP_MTMSR"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 input 5 \oper_i_ldst_ldst0__insn_type
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 input 6 \oper_i_ldst_ldst0__imm_data__imm
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 7 \oper_i_ldst_ldst0__imm_data__imm_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 8 \oper_i_ldst_ldst0__zero_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 9 \oper_i_ldst_ldst0__rc__rc
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 10 \oper_i_ldst_ldst0__rc__rc_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 11 \oper_i_ldst_ldst0__oe__oe
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 12 \oper_i_ldst_ldst0__oe__oe_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 13 \oper_i_ldst_ldst0__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 14 \oper_i_ldst_ldst0__is_signed
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 4 input 15 \oper_i_ldst_ldst0__data_len
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 16 \oper_i_ldst_ldst0__byte_reverse
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 17 \oper_i_ldst_ldst0__sign_extend
+  attribute \enum_base_type "LDSTMode"
+  attribute \enum_value_00 "NONE"
+  attribute \enum_value_01 "update"
+  attribute \enum_value_10 "cix"
+  attribute \enum_value_11 "cx"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 2 input 18 \oper_i_ldst_ldst0__ldst_mode
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
+  wire width 1 input 19 \cu_issue_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:106"
+  wire width 1 output 20 \cu_busy_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
+  wire width 3 input 21 \cu_rdmaskn_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+  wire width 3 output 22 \cu_rd__rel_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+  wire width 3 input 23 \cu_rd__go_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
+  wire width 64 input 24 \src1_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
+  wire width 64 input 25 \src2_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
+  wire width 64 input 26 \src3_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+  wire width 2 output 27 \cu_wr__rel_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+  wire width 2 input 28 \cu_wr__go_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 64 output 29 \o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 64 output 30 \ea
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 31 \coresync_rst
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:95"
+  wire width 1 output 32 \ldst_port0_is_ld_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:96"
+  wire width 1 output 33 \ldst_port0_is_st_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99"
+  wire width 4 output 34 \ldst_port0_data_len
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 96 output 35 \ldst_port0_addr_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 output 36 \ldst_port0_addr_i_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:107"
+  wire width 1 input 37 \ldst_port0_addr_exc_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:106"
+  wire width 1 input 38 \ldst_port0_addr_ok_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 64 input 39 \ldst_port0_ld_data_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 input 40 \ldst_port0_ld_data_o_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 64 output 41 \ldst_port0_st_data_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 output 42 \ldst_port0_st_data_i_ok
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+  wire width 1 \opc_l_s_opc
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+  wire width 1 \opc_l_s_opc$next
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+  wire width 1 \opc_l_r_opc
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+  wire width 1 \opc_l_r_opc$next
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
+  wire width 1 \opc_l_q_opc
+  cell \opc_l$119 \opc_l
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
+    connect \s_opc \opc_l_s_opc
+    connect \r_opc \opc_l_r_opc
+    connect \q_opc \opc_l_q_opc
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect$7
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $8
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $9
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+  wire width 3 \src_l_s_src
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+  wire width 3 \src_l_s_src$next
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+  wire width 3 \src_l_r_src
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+  wire width 3 \src_l_r_src$next
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
+  wire width 3 \src_l_q_src
+  cell \src_l$120 \src_l
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
+    connect \s_src \src_l_s_src
+    connect \r_src \src_l_r_src
+    connect \q_src \src_l_q_src
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+  wire width 1 \alu_l_s_alu
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+  wire width 1 \alu_l_r_alu
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
+  wire width 1 \alu_l_q_alu
+  cell \alu_l$121 \alu_l
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
+    connect \s_alu \alu_l_s_alu
+    connect \r_alu \alu_l_r_alu
+    connect \q_alu \alu_l_q_alu
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+  wire width 1 \adr_l_s_adr
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+  wire width 1 \adr_l_r_adr
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+  wire width 1 \adr_l_r_adr$next
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
+  wire width 1 \adr_l_q_adr
+  cell \adr_l \adr_l
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
+    connect \s_adr \adr_l_s_adr
+    connect \r_adr \adr_l_r_adr
+    connect \q_adr \adr_l_q_adr
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+  wire width 1 \lod_l_s_lod
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+  wire width 1 \lod_l_r_lod
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
+  wire width 1 \lod_l_qn_lod
+  cell \lod_l \lod_l
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
+    connect \s_lod \lod_l_s_lod
+    connect \r_lod \lod_l_r_lod
+    connect \qn_lod \lod_l_qn_lod
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+  wire width 1 \sto_l_s_sto
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+  wire width 1 \sto_l_r_sto
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
+  wire width 1 \sto_l_q_sto
+  cell \sto_l \sto_l
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
+    connect \s_sto \sto_l_s_sto
+    connect \r_sto \sto_l_r_sto
+    connect \q_sto \sto_l_q_sto
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+  wire width 1 \wri_l_s_wri
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+  wire width 1 \wri_l_r_wri
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+  wire width 1 \wri_l_r_wri$next
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
+  wire width 1 \wri_l_q_wri
+  cell \wri_l \wri_l
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
+    connect \s_wri \wri_l_s_wri
+    connect \r_wri \wri_l_r_wri
+    connect \q_wri \wri_l_q_wri
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+  wire width 1 \upd_l_s_upd
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+  wire width 1 \upd_l_s_upd$next
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+  wire width 1 \upd_l_r_upd
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+  wire width 1 \upd_l_r_upd$next
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
+  wire width 1 \upd_l_q_upd
+  cell \upd_l \upd_l
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
+    connect \s_upd \upd_l_s_upd
+    connect \r_upd \upd_l_r_upd
+    connect \q_upd \upd_l_q_upd
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+  wire width 1 \rst_l_s_rst
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+  wire width 1 \rst_l_r_rst
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
+  wire width 1 \rst_l_q_rst
+  cell \rst_l$122 \rst_l
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
+    connect \s_rst \rst_l_s_rst
+    connect \r_rst \rst_l_r_rst
+    connect \q_rst \rst_l_q_rst
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+  wire width 1 \lsd_l_s_lsd
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+  wire width 1 \lsd_l_r_lsd
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+  wire width 1 \lsd_l_r_lsd$next
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
+  wire width 1 \lsd_l_q_lsd
+  cell \lsd_l \lsd_l
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
+    connect \s_lsd \lsd_l_s_lsd
+    connect \r_lsd \lsd_l_r_lsd
+    connect \q_lsd \lsd_l_q_lsd
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:289"
+  wire width 1 \reset_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:103"
+  wire width 1 \cu_go_die_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:293"
+  wire width 1 $1
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:293"
+  cell $or $2
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src218__ren
-    connect \B 1'1
-    connect \Y $8
+    connect \A \cu_issue_i
+    connect \B \cu_go_die_i
+    connect \Y $1
   end
-  process $group_2
-    assign \wr_detect$7 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $8 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        assign \wr_detect$7 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest118__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$7 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest218__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$7 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-    end
+  process $group_0
+    assign \reset_i 1'0
+    assign \reset_i $1
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $10
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $11
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:285"
+  wire width 1 \reset_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:275"
+  wire width 1 \wr_reset
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:294"
+  wire width 1 $3
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:294"
+  cell $or $4
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src218__ren
-    connect \B 1'1
-    connect \Y $10
+    connect \A \wr_reset
+    connect \B \cu_go_die_i
+    connect \Y $3
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  wire width 1 $12
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $13
+  process $group_1
+    assign \reset_o 1'0
+    assign \reset_o $3
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:286"
+  wire width 1 \reset_w
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:295"
+  wire width 1 $5
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:295"
+  cell $or $6
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr_detect$7
-    connect \Y $12
+    connect \A \cu_wr__go_i [0]
+    connect \B \cu_go_die_i
+    connect \Y $5
   end
-  process $group_3
-    assign \src218__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $10 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest118__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src218__data_o \dest118__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest218__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src218__data_o \dest218__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $12 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \src218__data_o \reg
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \src218__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
+  process $group_2
+    assign \reset_w 1'0
+    assign \reset_w $5
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect$14
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $15
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $16
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:287"
+  wire width 1 \reset_u
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:296"
+  wire width 1 $7
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:296"
+  cell $or $8
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src318__ren
-    connect \B 1'1
-    connect \Y $15
+    connect \A \cu_wr__go_i [1]
+    connect \B \cu_go_die_i
+    connect \Y $7
   end
-  process $group_4
-    assign \wr_detect$14 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $15 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        assign \wr_detect$14 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest118__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$14 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest218__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$14 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-    end
+  process $group_3
+    assign \reset_u 1'0
+    assign \reset_u $7
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $17
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $18
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:291"
+  wire width 1 \reset_s
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:297"
+  wire width 1 $9
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:297"
+  cell $or $10
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src318__ren
-    connect \B 1'1
-    connect \Y $17
+    connect \A \cu_st__go_i
+    connect \B \cu_go_die_i
+    connect \Y $9
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  wire width 1 $19
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $20
+  process $group_4
+    assign \reset_s 1'0
+    assign \reset_s $9
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:290"
+  wire width 3 \reset_r
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:298"
+  wire width 3 $11
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:298"
+  cell $or $12
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 3
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 3
+    parameter \Y_WIDTH 3
+    connect \A \cu_rd__go_i
+    connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i }
+    connect \Y $11
+  end
+  process $group_5
+    assign \reset_r 3'000
+    assign \reset_r $11
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:288"
+  wire width 1 \reset_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:299"
+  wire width 1 $13
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:299"
+  cell $or $14
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr_detect$14
-    connect \Y $19
+    connect \A \cu_ad__go_i
+    connect \B \cu_go_die_i
+    connect \Y $13
   end
-  process $group_5
-    assign \src318__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $17 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  process $group_6
+    assign \reset_a 1'0
+    assign \reset_a $13
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:301"
+  wire width 1 \p_st_go
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:301"
+  wire width 1 \p_st_go$next
+  process $group_7
+    assign \p_st_go$next \p_st_go
+    assign \p_st_go$next \cu_st__go_i
+    sync init
+      update \p_st_go 1'0
+    sync posedge \coresync_clk
+      update \p_st_go \p_st_go$next
+  end
+  process $group_8
+    assign \opc_l_s_opc$next \opc_l_s_opc
+    assign \opc_l_s_opc$next \cu_issue_i
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest118__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src318__data_o \dest118__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest218__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src318__data_o \dest218__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $19 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \src318__data_o \reg
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \src318__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+        assign \opc_l_s_opc$next 1'0
     end
     sync init
+      update \opc_l_s_opc 1'0
+    sync posedge \coresync_clk
+      update \opc_l_s_opc \opc_l_s_opc$next
   end
-  process $group_6
-    assign \reg$next \reg
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-    switch { \dest118__wen }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+  process $group_9
+    assign \opc_l_r_opc$next \opc_l_r_opc
+    assign \opc_l_r_opc$next \reset_o
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
       case 1'1
-        assign \reg$next \dest118__data_i
+        assign \opc_l_r_opc$next 1'1
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-    switch { \dest218__wen }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+    sync init
+      update \opc_l_r_opc 1'1
+    sync posedge \coresync_clk
+      update \opc_l_r_opc \opc_l_r_opc$next
+  end
+  process $group_10
+    assign \src_l_s_src$next \src_l_s_src
+    assign \src_l_s_src$next { \cu_issue_i \cu_issue_i \cu_issue_i }
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
       case 1'1
-        assign \reg$next \dest218__data_i
+        assign \src_l_s_src$next 3'000
     end
+    sync init
+      update \src_l_s_src 3'000
+    sync posedge \coresync_clk
+      update \src_l_s_src \src_l_s_src$next
+  end
+  process $group_11
+    assign \src_l_r_src$next \src_l_r_src
+    assign \src_l_r_src$next \reset_r
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
-        assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
+        assign \src_l_r_src$next 3'111
     end
     sync init
-      update \reg 64'0000000000000000000000000000000000000000000000000000000000000000
-    sync posedge \clk
-      update \reg \reg$next
+      update \src_l_r_src 3'111
+    sync posedge \coresync_clk
+      update \src_l_r_src \src_l_r_src$next
   end
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.int.reg_19"
-module \reg_19
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 2 \src119__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 3 \src119__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 4 \src219__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 5 \src219__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 6 \src319__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 7 \src319__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 8 \dest119__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 9 \dest119__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 10 \dest219__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 11 \dest219__data_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $2
+  process $group_12
+    assign \alu_l_s_alu 1'0
+    assign \alu_l_s_alu \reset_i
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:269"
+  wire width 1 \alu_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:269"
+  wire width 1 \alu_ok$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:331"
+  wire width 1 $15
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:268"
+  wire width 1 \alu_valid
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:331"
+  cell $not $16
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src119__ren
-    connect \B 1'1
-    connect \Y $1
-  end
-  process $group_0
-    assign \wr_detect 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $1 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        assign \wr_detect 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest119__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest219__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-    end
-    sync init
+    connect \A \alu_valid
+    connect \Y $15
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $3
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $4
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:331"
+  wire width 1 $17
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:331"
+  cell $and $18
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src119__ren
-    connect \B 1'1
-    connect \Y $3
+    connect \A \alu_ok
+    connect \B $15
+    connect \Y $17
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  wire width 1 $5
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $6
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:331"
+  wire width 1 $19
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:273"
+  wire width 1 \rda_any
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:331"
+  cell $not $20
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr_detect
-    connect \Y $5
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
-  wire width 64 \reg
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
-  wire width 64 \reg$next
-  process $group_1
-    assign \src119__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $3 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest119__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src119__data_o \dest119__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest219__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src119__data_o \dest219__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $5 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \src119__data_o \reg
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \src119__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
-    sync init
+    connect \A \rda_any
+    connect \Y $19
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect$7
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $8
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $9
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:331"
+  wire width 1 $21
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:331"
+  cell $and $22
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src219__ren
-    connect \B 1'1
-    connect \Y $8
+    connect \A $17
+    connect \B $19
+    connect \Y $21
   end
-  process $group_2
-    assign \wr_detect$7 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $8 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  process $group_13
+    assign \alu_l_r_alu 1'1
+    assign \alu_l_r_alu $21
+    sync init
+  end
+  process $group_14
+    assign \adr_l_s_adr 1'0
+    assign \adr_l_s_adr \reset_i
+    sync init
+  end
+  process $group_15
+    assign \adr_l_r_adr$next \adr_l_r_adr
+    assign \adr_l_r_adr$next \reset_a
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
       case 1'1
-        assign \wr_detect$7 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest119__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$7 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest219__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$7 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
+        assign \adr_l_r_adr$next 1'1
     end
     sync init
+      update \adr_l_r_adr 1'1
+    sync posedge \coresync_clk
+      update \adr_l_r_adr \adr_l_r_adr$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $10
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $11
+  process $group_16
+    assign \lod_l_s_lod 1'0
+    assign \lod_l_s_lod \reset_i
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:271"
+  wire width 1 \ld_ok
+  process $group_17
+    assign \lod_l_r_lod 1'1
+    assign \lod_l_r_lod \ld_ok
+    sync init
+  end
+  process $group_18
+    assign \wri_l_s_wri 1'0
+    assign \wri_l_s_wri \cu_issue_i
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:343"
+  wire width 2 $23
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107"
+  wire width 1 \cu_done_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:343"
+  wire width 2 $24
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:343"
+  cell $or $25
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \src219__ren
-    connect \B 1'1
-    connect \Y $10
+    parameter \B_WIDTH 2
+    parameter \Y_WIDTH 2
+    connect \A \reset_w
+    connect \B { \cu_done_o \cu_done_o }
+    connect \Y $24
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  wire width 1 $12
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $13
+  connect $23 $24
+  process $group_19
+    assign \wri_l_r_wri$next \wri_l_r_wri
+    assign \wri_l_r_wri$next $23 [0]
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
+      case 1'1
+        assign \wri_l_r_wri$next 1'1
+    end
+    sync init
+      update \wri_l_r_wri 1'1
+    sync posedge \coresync_clk
+      update \wri_l_r_wri \wri_l_r_wri$next
+  end
+  process $group_20
+    assign \upd_l_s_upd$next \upd_l_s_upd
+    assign \upd_l_s_upd$next \reset_i
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
+      case 1'1
+        assign \upd_l_s_upd$next 1'0
+    end
+    sync init
+      update \upd_l_s_upd 1'0
+    sync posedge \coresync_clk
+      update \upd_l_s_upd \upd_l_s_upd$next
+  end
+  process $group_21
+    assign \upd_l_r_upd$next \upd_l_r_upd
+    assign \upd_l_r_upd$next \reset_u
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
+      case 1'1
+        assign \upd_l_r_upd$next 1'1
+    end
+    sync init
+      update \upd_l_r_upd 1'1
+    sync posedge \coresync_clk
+      update \upd_l_r_upd \upd_l_r_upd$next
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:270"
+  wire width 1 \addr_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:265"
+  wire width 1 \op_is_st
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:350"
+  wire width 1 $26
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:350"
+  cell $and $27
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr_detect$7
-    connect \Y $12
+    connect \A \addr_ok
+    connect \B \op_is_st
+    connect \Y $26
   end
-  process $group_3
-    assign \src219__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $10 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest119__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src219__data_o \dest119__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest219__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src219__data_o \dest219__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $12 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \src219__data_o \reg
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \src219__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
+  process $group_22
+    assign \sto_l_s_sto 1'0
+    assign \sto_l_s_sto $26
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect$14
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $15
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $16
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:351"
+  wire width 1 $28
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:351"
+  cell $or $29
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src319__ren
-    connect \B 1'1
-    connect \Y $15
+    connect \A \reset_s
+    connect \B \p_st_go
+    connect \Y $28
   end
-  process $group_4
-    assign \wr_detect$14 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $15 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        assign \wr_detect$14 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest119__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$14 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest219__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$14 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-    end
+  process $group_23
+    assign \sto_l_r_sto 1'1
+    assign \sto_l_r_sto $28
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $17
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $18
+  process $group_24
+    assign \lsd_l_s_lsd 1'0
+    assign \lsd_l_s_lsd \cu_issue_i
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:355"
+  wire width 1 $30
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:355"
+  cell $or $31
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src319__ren
-    connect \B 1'1
-    connect \Y $17
+    connect \A \reset_s
+    connect \B \p_st_go
+    connect \Y $30
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  wire width 1 $19
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $20
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:355"
+  wire width 1 $32
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:355"
+  cell $or $33
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr_detect$14
-    connect \Y $19
+    connect \A $30
+    connect \B \ld_ok
+    connect \Y $32
   end
-  process $group_5
-    assign \src319__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $17 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  process $group_25
+    assign \lsd_l_r_lsd$next \lsd_l_r_lsd
+    assign \lsd_l_r_lsd$next $32
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest119__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src319__data_o \dest119__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest219__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src319__data_o \dest219__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $19 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \src319__data_o \reg
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \src319__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+        assign \lsd_l_r_lsd$next 1'1
     end
     sync init
+      update \lsd_l_r_lsd 1'1
+    sync posedge \coresync_clk
+      update \lsd_l_r_lsd \lsd_l_r_lsd$next
   end
-  process $group_6
-    assign \reg$next \reg
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-    switch { \dest119__wen }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-      case 1'1
-        assign \reg$next \dest119__data_i
-    end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-    switch { \dest219__wen }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+  process $group_26
+    assign \rst_l_s_rst 1'0
+    assign \rst_l_s_rst \addr_ok
+    sync init
+  end
+  process $group_27
+    assign \rst_l_r_rst 1'1
+    assign \rst_l_r_rst \cu_issue_i
+    sync init
+  end
+  attribute \enum_base_type "MicrOp"
+  attribute \enum_value_0000000 "OP_ILLEGAL"
+  attribute \enum_value_0000001 "OP_NOP"
+  attribute \enum_value_0000010 "OP_ADD"
+  attribute \enum_value_0000011 "OP_ADDPCIS"
+  attribute \enum_value_0000100 "OP_AND"
+  attribute \enum_value_0000101 "OP_ATTN"
+  attribute \enum_value_0000110 "OP_B"
+  attribute \enum_value_0000111 "OP_BC"
+  attribute \enum_value_0001000 "OP_BCREG"
+  attribute \enum_value_0001001 "OP_BPERM"
+  attribute \enum_value_0001010 "OP_CMP"
+  attribute \enum_value_0001011 "OP_CMPB"
+  attribute \enum_value_0001100 "OP_CMPEQB"
+  attribute \enum_value_0001101 "OP_CMPRB"
+  attribute \enum_value_0001110 "OP_CNTZ"
+  attribute \enum_value_0001111 "OP_CRAND"
+  attribute \enum_value_0010000 "OP_CRANDC"
+  attribute \enum_value_0010001 "OP_CREQV"
+  attribute \enum_value_0010010 "OP_CRNAND"
+  attribute \enum_value_0010011 "OP_CRNOR"
+  attribute \enum_value_0010100 "OP_CROR"
+  attribute \enum_value_0010101 "OP_CRORC"
+  attribute \enum_value_0010110 "OP_CRXOR"
+  attribute \enum_value_0010111 "OP_DARN"
+  attribute \enum_value_0011000 "OP_DCBF"
+  attribute \enum_value_0011001 "OP_DCBST"
+  attribute \enum_value_0011010 "OP_DCBT"
+  attribute \enum_value_0011011 "OP_DCBTST"
+  attribute \enum_value_0011100 "OP_DCBZ"
+  attribute \enum_value_0011101 "OP_DIV"
+  attribute \enum_value_0011110 "OP_DIVE"
+  attribute \enum_value_0011111 "OP_EXTS"
+  attribute \enum_value_0100000 "OP_EXTSWSLI"
+  attribute \enum_value_0100001 "OP_ICBI"
+  attribute \enum_value_0100010 "OP_ICBT"
+  attribute \enum_value_0100011 "OP_ISEL"
+  attribute \enum_value_0100100 "OP_ISYNC"
+  attribute \enum_value_0100101 "OP_LOAD"
+  attribute \enum_value_0100110 "OP_STORE"
+  attribute \enum_value_0100111 "OP_MADDHD"
+  attribute \enum_value_0101000 "OP_MADDHDU"
+  attribute \enum_value_0101001 "OP_MADDLD"
+  attribute \enum_value_0101010 "OP_MCRF"
+  attribute \enum_value_0101011 "OP_MCRXR"
+  attribute \enum_value_0101100 "OP_MCRXRX"
+  attribute \enum_value_0101101 "OP_MFCR"
+  attribute \enum_value_0101110 "OP_MFSPR"
+  attribute \enum_value_0101111 "OP_MOD"
+  attribute \enum_value_0110000 "OP_MTCRF"
+  attribute \enum_value_0110001 "OP_MTSPR"
+  attribute \enum_value_0110010 "OP_MUL_L64"
+  attribute \enum_value_0110011 "OP_MUL_H64"
+  attribute \enum_value_0110100 "OP_MUL_H32"
+  attribute \enum_value_0110101 "OP_OR"
+  attribute \enum_value_0110110 "OP_POPCNT"
+  attribute \enum_value_0110111 "OP_PRTY"
+  attribute \enum_value_0111000 "OP_RLC"
+  attribute \enum_value_0111001 "OP_RLCL"
+  attribute \enum_value_0111010 "OP_RLCR"
+  attribute \enum_value_0111011 "OP_SETB"
+  attribute \enum_value_0111100 "OP_SHL"
+  attribute \enum_value_0111101 "OP_SHR"
+  attribute \enum_value_0111110 "OP_SYNC"
+  attribute \enum_value_0111111 "OP_TRAP"
+  attribute \enum_value_1000011 "OP_XOR"
+  attribute \enum_value_1000100 "OP_SIM_CONFIG"
+  attribute \enum_value_1000101 "OP_CROP"
+  attribute \enum_value_1000110 "OP_RFID"
+  attribute \enum_value_1000111 "OP_MFMSR"
+  attribute \enum_value_1001000 "OP_MTMSRD"
+  attribute \enum_value_1001001 "OP_SC"
+  attribute \enum_value_1001010 "OP_MTMSR"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 \oper_r__insn_type
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 \oper_r__imm_data__imm
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \oper_r__imm_data__imm_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \oper_r__zero_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \oper_r__rc__rc
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \oper_r__rc__rc_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \oper_r__oe__oe
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \oper_r__oe__oe_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \oper_r__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \oper_r__is_signed
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 4 \oper_r__data_len
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \oper_r__byte_reverse
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \oper_r__sign_extend
+  attribute \enum_base_type "LDSTMode"
+  attribute \enum_value_00 "NONE"
+  attribute \enum_value_01 "update"
+  attribute \enum_value_10 "cix"
+  attribute \enum_value_11 "cx"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 2 \oper_r__ldst_mode
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+  wire width 7 \oper_l__insn_type
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+  wire width 7 \oper_l__insn_type$next
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+  wire width 64 \oper_l__imm_data__imm
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+  wire width 64 \oper_l__imm_data__imm$next
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+  wire width 1 \oper_l__imm_data__imm_ok
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+  wire width 1 \oper_l__imm_data__imm_ok$next
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+  wire width 1 \oper_l__zero_a
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+  wire width 1 \oper_l__zero_a$next
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+  wire width 1 \oper_l__rc__rc
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+  wire width 1 \oper_l__rc__rc$next
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+  wire width 1 \oper_l__rc__rc_ok
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+  wire width 1 \oper_l__rc__rc_ok$next
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+  wire width 1 \oper_l__oe__oe
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+  wire width 1 \oper_l__oe__oe$next
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+  wire width 1 \oper_l__oe__oe_ok
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+  wire width 1 \oper_l__oe__oe_ok$next
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+  wire width 1 \oper_l__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+  wire width 1 \oper_l__is_32bit$next
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+  wire width 1 \oper_l__is_signed
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+  wire width 1 \oper_l__is_signed$next
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+  wire width 4 \oper_l__data_len
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+  wire width 4 \oper_l__data_len$next
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+  wire width 1 \oper_l__byte_reverse
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+  wire width 1 \oper_l__byte_reverse$next
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+  wire width 1 \oper_l__sign_extend
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+  wire width 1 \oper_l__sign_extend$next
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+  wire width 2 \oper_l__ldst_mode
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:37"
+  wire width 2 \oper_l__ldst_mode$next
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
+  wire width 87 $34
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
+  cell $mux $35
+    parameter \WIDTH 87
+    connect \A { \oper_l__ldst_mode \oper_l__sign_extend \oper_l__byte_reverse \oper_l__data_len \oper_l__is_signed \oper_l__is_32bit { \oper_l__oe__oe_ok \oper_l__oe__oe } { \oper_l__rc__rc_ok \oper_l__rc__rc } \oper_l__zero_a { \oper_l__imm_data__imm_ok \oper_l__imm_data__imm } \oper_l__insn_type }
+    connect \B { \oper_i_ldst_ldst0__ldst_mode \oper_i_ldst_ldst0__sign_extend \oper_i_ldst_ldst0__byte_reverse \oper_i_ldst_ldst0__data_len \oper_i_ldst_ldst0__is_signed \oper_i_ldst_ldst0__is_32bit { \oper_i_ldst_ldst0__oe__oe_ok \oper_i_ldst_ldst0__oe__oe } { \oper_i_ldst_ldst0__rc__rc_ok \oper_i_ldst_ldst0__rc__rc } \oper_i_ldst_ldst0__zero_a { \oper_i_ldst_ldst0__imm_data__imm_ok \oper_i_ldst_ldst0__imm_data__imm } \oper_i_ldst_ldst0__insn_type }
+    connect \S \cu_issue_i
+    connect \Y $34
+  end
+  process $group_28
+    assign \oper_r__insn_type 7'0000000
+    assign \oper_r__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \oper_r__imm_data__imm_ok 1'0
+    assign \oper_r__zero_a 1'0
+    assign \oper_r__rc__rc 1'0
+    assign \oper_r__rc__rc_ok 1'0
+    assign \oper_r__oe__oe 1'0
+    assign \oper_r__oe__oe_ok 1'0
+    assign \oper_r__is_32bit 1'0
+    assign \oper_r__is_signed 1'0
+    assign \oper_r__data_len 4'0000
+    assign \oper_r__byte_reverse 1'0
+    assign \oper_r__sign_extend 1'0
+    assign \oper_r__ldst_mode 2'00
+    assign { \oper_r__ldst_mode \oper_r__sign_extend \oper_r__byte_reverse \oper_r__data_len \oper_r__is_signed \oper_r__is_32bit { \oper_r__oe__oe_ok \oper_r__oe__oe } { \oper_r__rc__rc_ok \oper_r__rc__rc } \oper_r__zero_a { \oper_r__imm_data__imm_ok \oper_r__imm_data__imm } \oper_r__insn_type } $34
+    sync init
+  end
+  process $group_42
+    assign \oper_l__insn_type$next \oper_l__insn_type
+    assign \oper_l__imm_data__imm$next \oper_l__imm_data__imm
+    assign \oper_l__imm_data__imm_ok$next \oper_l__imm_data__imm_ok
+    assign \oper_l__zero_a$next \oper_l__zero_a
+    assign \oper_l__rc__rc$next \oper_l__rc__rc
+    assign \oper_l__rc__rc_ok$next \oper_l__rc__rc_ok
+    assign \oper_l__oe__oe$next \oper_l__oe__oe
+    assign \oper_l__oe__oe_ok$next \oper_l__oe__oe_ok
+    assign \oper_l__is_32bit$next \oper_l__is_32bit
+    assign \oper_l__is_signed$next \oper_l__is_signed
+    assign \oper_l__data_len$next \oper_l__data_len
+    assign \oper_l__byte_reverse$next \oper_l__byte_reverse
+    assign \oper_l__sign_extend$next \oper_l__sign_extend
+    assign \oper_l__ldst_mode$next \oper_l__ldst_mode
+    attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
+    switch { \cu_issue_i }
+      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
       case 1'1
-        assign \reg$next \dest219__data_i
+        assign { \oper_l__ldst_mode$next \oper_l__sign_extend$next \oper_l__byte_reverse$next \oper_l__data_len$next \oper_l__is_signed$next \oper_l__is_32bit$next { \oper_l__oe__oe_ok$next \oper_l__oe__oe$next } { \oper_l__rc__rc_ok$next \oper_l__rc__rc$next } \oper_l__zero_a$next { \oper_l__imm_data__imm_ok$next \oper_l__imm_data__imm$next } \oper_l__insn_type$next } { \oper_i_ldst_ldst0__ldst_mode \oper_i_ldst_ldst0__sign_extend \oper_i_ldst_ldst0__byte_reverse \oper_i_ldst_ldst0__data_len \oper_i_ldst_ldst0__is_signed \oper_i_ldst_ldst0__is_32bit { \oper_i_ldst_ldst0__oe__oe_ok \oper_i_ldst_ldst0__oe__oe } { \oper_i_ldst_ldst0__rc__rc_ok \oper_i_ldst_ldst0__rc__rc } \oper_i_ldst_ldst0__zero_a { \oper_i_ldst_ldst0__imm_data__imm_ok \oper_i_ldst_ldst0__imm_data__imm } \oper_i_ldst_ldst0__insn_type }
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
-        assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
+        assign \oper_l__imm_data__imm$next 64'0000000000000000000000000000000000000000000000000000000000000000
+        assign \oper_l__imm_data__imm_ok$next 1'0
+        assign \oper_l__rc__rc$next 1'0
+        assign \oper_l__rc__rc_ok$next 1'0
+        assign \oper_l__oe__oe$next 1'0
+        assign \oper_l__oe__oe_ok$next 1'0
     end
     sync init
-      update \reg 64'0000000000000000000000000000000000000000000000000000000000000000
-    sync posedge \clk
-      update \reg \reg$next
+      update \oper_l__insn_type 7'0000000
+      update \oper_l__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
+      update \oper_l__imm_data__imm_ok 1'0
+      update \oper_l__zero_a 1'0
+      update \oper_l__rc__rc 1'0
+      update \oper_l__rc__rc_ok 1'0
+      update \oper_l__oe__oe 1'0
+      update \oper_l__oe__oe_ok 1'0
+      update \oper_l__is_32bit 1'0
+      update \oper_l__is_signed 1'0
+      update \oper_l__data_len 4'0000
+      update \oper_l__byte_reverse 1'0
+      update \oper_l__sign_extend 1'0
+      update \oper_l__ldst_mode 2'00
+    sync posedge \coresync_clk
+      update \oper_l__insn_type \oper_l__insn_type$next
+      update \oper_l__imm_data__imm \oper_l__imm_data__imm$next
+      update \oper_l__imm_data__imm_ok \oper_l__imm_data__imm_ok$next
+      update \oper_l__zero_a \oper_l__zero_a$next
+      update \oper_l__rc__rc \oper_l__rc__rc$next
+      update \oper_l__rc__rc_ok \oper_l__rc__rc_ok$next
+      update \oper_l__oe__oe \oper_l__oe__oe$next
+      update \oper_l__oe__oe_ok \oper_l__oe__oe_ok$next
+      update \oper_l__is_32bit \oper_l__is_32bit$next
+      update \oper_l__is_signed \oper_l__is_signed$next
+      update \oper_l__data_len \oper_l__data_len$next
+      update \oper_l__byte_reverse \oper_l__byte_reverse$next
+      update \oper_l__sign_extend \oper_l__sign_extend$next
+      update \oper_l__ldst_mode \oper_l__ldst_mode$next
   end
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.int.reg_20"
-module \reg_20
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 2 \src120__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 3 \src120__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 4 \src220__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 5 \src220__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 6 \src320__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 7 \src320__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 8 \dest120__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 9 \dest120__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 10 \dest220__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 11 \dest220__data_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $2
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \src120__ren
-    connect \B 1'1
-    connect \Y $1
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:366"
+  wire width 64 \ldd_r
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:279"
+  wire width 64 \ldd_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
+  wire width 64 \ldo_r
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
+  wire width 64 \ldo_r$next
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
+  wire width 64 $36
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
+  cell $mux $37
+    parameter \WIDTH 64
+    connect \A \ldo_r
+    connect \B \ldd_o
+    connect \S \ld_ok
+    connect \Y $36
   end
-  process $group_0
-    assign \wr_detect 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $1 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  process $group_56
+    assign \ldd_r 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \ldd_r $36
+    sync init
+  end
+  process $group_57
+    assign \ldo_r$next \ldo_r
+    attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
+    switch { \ld_ok }
+      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
       case 1'1
-        assign \wr_detect 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest120__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest220__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
+        assign \ldo_r$next \ldd_o
     end
     sync init
+      update \ldo_r 64'0000000000000000000000000000000000000000000000000000000000000000
+    sync posedge \coresync_clk
+      update \ldo_r \ldo_r$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $3
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $4
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \src120__ren
-    connect \B 1'1
-    connect \Y $3
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:373"
+  wire width 64 \src_r0
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
+  wire width 64 \src_r0_l
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
+  wire width 64 \src_r0_l$next
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
+  wire width 64 $38
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
+  cell $mux $39
+    parameter \WIDTH 64
+    connect \A \src_r0_l
+    connect \B \src1_i
+    connect \S \src_l_q_src [0]
+    connect \Y $38
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  wire width 1 $5
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $6
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \wr_detect
-    connect \Y $5
+  process $group_58
+    assign \src_r0 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \src_r0 $38
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
-  wire width 64 \reg
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
-  wire width 64 \reg$next
-  process $group_1
-    assign \src120__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $3 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  process $group_59
+    assign \src_r0_l$next \src_r0_l
+    attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
+    switch { \src_l_q_src [0] }
+      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest120__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src120__data_o \dest120__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest220__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src120__data_o \dest220__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $5 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \src120__data_o \reg
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \src120__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+        assign \src_r0_l$next \src1_i
     end
     sync init
+      update \src_r0_l 64'0000000000000000000000000000000000000000000000000000000000000000
+    sync posedge \coresync_clk
+      update \src_r0_l \src_r0_l$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect$7
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $8
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $9
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \src220__ren
-    connect \B 1'1
-    connect \Y $8
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:373"
+  wire width 64 \src_r1
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
+  wire width 64 \src_r1_l
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
+  wire width 64 \src_r1_l$next
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
+  wire width 64 $40
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
+  cell $mux $41
+    parameter \WIDTH 64
+    connect \A \src_r1_l
+    connect \B \src2_i
+    connect \S \src_l_q_src [1]
+    connect \Y $40
   end
-  process $group_2
-    assign \wr_detect$7 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $8 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  process $group_60
+    assign \src_r1 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \src_r1 $40
+    sync init
+  end
+  process $group_61
+    assign \src_r1_l$next \src_r1_l
+    attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
+    switch { \src_l_q_src [1] }
+      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
       case 1'1
-        assign \wr_detect$7 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest120__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$7 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest220__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$7 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
+        assign \src_r1_l$next \src2_i
     end
     sync init
+      update \src_r1_l 64'0000000000000000000000000000000000000000000000000000000000000000
+    sync posedge \coresync_clk
+      update \src_r1_l \src_r1_l$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $10
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $11
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \src220__ren
-    connect \B 1'1
-    connect \Y $10
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:373"
+  wire width 64 \src_r2
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
+  wire width 64 \src_r2_l
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
+  wire width 64 \src_r2_l$next
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
+  wire width 64 $42
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
+  cell $mux $43
+    parameter \WIDTH 64
+    connect \A \src_r2_l
+    connect \B \src3_i
+    connect \S \src_l_q_src [2]
+    connect \Y $42
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  wire width 1 $12
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $13
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \wr_detect$7
-    connect \Y $12
-  end
-  process $group_3
-    assign \src220__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $10 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest120__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src220__data_o \dest120__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest220__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src220__data_o \dest220__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $12 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \src220__data_o \reg
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \src220__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
+  process $group_62
+    assign \src_r2 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \src_r2 $42
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect$14
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $15
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $16
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \src320__ren
-    connect \B 1'1
-    connect \Y $15
-  end
-  process $group_4
-    assign \wr_detect$14 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $15 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  process $group_63
+    assign \src_r2_l$next \src_r2_l
+    attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
+    switch { \src_l_q_src [2] }
+      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
       case 1'1
-        assign \wr_detect$14 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest120__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$14 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest220__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$14 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
+        assign \src_r2_l$next \src3_i
     end
     sync init
+      update \src_r2_l 64'0000000000000000000000000000000000000000000000000000000000000000
+    sync posedge \coresync_clk
+      update \src_r2_l \src_r2_l$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $17
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $18
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \src320__ren
-    connect \B 1'1
-    connect \Y $17
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:378"
+  wire width 64 \addr_r
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:278"
+  wire width 64 \alu_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:278"
+  wire width 64 \alu_o$next
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
+  wire width 64 \ea_r
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
+  wire width 64 \ea_r$next
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
+  wire width 64 $44
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
+  cell $mux $45
+    parameter \WIDTH 64
+    connect \A \ea_r
+    connect \B \alu_o
+    connect \S \alu_l_q_alu
+    connect \Y $44
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  wire width 1 $19
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $20
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \wr_detect$14
-    connect \Y $19
+  process $group_64
+    assign \addr_r 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \addr_r $44
+    sync init
   end
-  process $group_5
-    assign \src320__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $17 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  process $group_65
+    assign \ea_r$next \ea_r
+    attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
+    switch { \alu_l_q_alu }
+      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest120__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src320__data_o \dest120__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest220__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src320__data_o \dest220__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $19 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \src320__data_o \reg
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \src320__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+        assign \ea_r$next \alu_o
     end
     sync init
+      update \ea_r 64'0000000000000000000000000000000000000000000000000000000000000000
+    sync posedge \coresync_clk
+      update \ea_r \ea_r$next
   end
-  process $group_6
-    assign \reg$next \reg
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-    switch { \dest120__wen }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-      case 1'1
-        assign \reg$next \dest120__data_i
-    end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-    switch { \dest220__wen }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-      case 1'1
-        assign \reg$next \dest220__data_i
-    end
-    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
-      case 1'1
-        assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:383"
+  wire width 64 \src1_or_z
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:384"
+  wire width 64 $46
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:384"
+  cell $mux $47
+    parameter \WIDTH 64
+    connect \A \src_r0
+    connect \B 64'0000000000000000000000000000000000000000000000000000000000000000
+    connect \S \oper_r__zero_a
+    connect \Y $46
+  end
+  process $group_66
+    assign \src1_or_z 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \src1_or_z $46
     sync init
-      update \reg 64'0000000000000000000000000000000000000000000000000000000000000000
-    sync posedge \clk
-      update \reg \reg$next
   end
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.int.reg_21"
-module \reg_21
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 2 \src121__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 3 \src121__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 4 \src221__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 5 \src221__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 6 \src321__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 7 \src321__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 8 \dest121__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 9 \dest121__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 10 \dest221__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 11 \dest221__data_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $2
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \src121__ren
-    connect \B 1'1
-    connect \Y $1
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:388"
+  wire width 64 \src2_or_imm
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:389"
+  wire width 64 $48
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:389"
+  cell $mux $49
+    parameter \WIDTH 64
+    connect \A \src_r1
+    connect \B \oper_r__imm_data__imm
+    connect \S \oper_r__imm_data__imm_ok
+    connect \Y $48
   end
-  process $group_0
-    assign \wr_detect 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $1 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        assign \wr_detect 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest121__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest221__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-    end
+  process $group_67
+    assign \src2_or_imm 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \src2_or_imm $48
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $3
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $4
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:392"
+  wire width 65 $50
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:392"
+  wire width 65 $51
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:392"
+  cell $add $52
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
+    parameter \A_WIDTH 64
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \src121__ren
-    connect \B 1'1
-    connect \Y $3
+    parameter \B_WIDTH 64
+    parameter \Y_WIDTH 65
+    connect \A \src1_or_z
+    connect \B \src2_or_imm
+    connect \Y $51
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  wire width 1 $5
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $6
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \wr_detect
-    connect \Y $5
+  connect $50 $51
+  process $group_68
+    assign \alu_o$next \alu_o
+    assign \alu_o$next $50 [63:0]
+    sync init
+      update \alu_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    sync posedge \coresync_clk
+      update \alu_o \alu_o$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
-  wire width 64 \reg
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
-  wire width 64 \reg$next
-  process $group_1
-    assign \src121__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $3 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest121__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src121__data_o \dest121__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest221__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src121__data_o \dest221__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $5 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \src121__data_o \reg
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \src121__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
+  process $group_69
+    assign \alu_ok$next \alu_ok
+    assign \alu_ok$next \alu_valid
     sync init
+      update \alu_ok 1'0
+    sync posedge \coresync_clk
+      update \alu_ok \alu_ok$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect$7
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $8
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $9
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:396"
+  wire width 1 $53
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:396"
+  cell $eq $54
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
+    parameter \A_WIDTH 7
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
+    parameter \B_WIDTH 7
     parameter \Y_WIDTH 1
-    connect \A \src221__ren
-    connect \B 1'1
-    connect \Y $8
+    connect \A \oper_r__insn_type
+    connect \B 7'0100110
+    connect \Y $53
   end
-  process $group_2
-    assign \wr_detect$7 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $8 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        assign \wr_detect$7 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest121__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$7 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest221__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$7 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-    end
+  process $group_70
+    assign \op_is_st 1'0
+    assign \op_is_st $53
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $10
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $11
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:264"
+  wire width 1 \op_is_ld
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:397"
+  wire width 1 $55
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:397"
+  cell $eq $56
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
+    parameter \A_WIDTH 7
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \src221__ren
-    connect \B 1'1
-    connect \Y $10
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  wire width 1 $12
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $13
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
+    parameter \B_WIDTH 7
     parameter \Y_WIDTH 1
-    connect \A \wr_detect$7
-    connect \Y $12
+    connect \A \oper_r__insn_type
+    connect \B 7'0100101
+    connect \Y $55
   end
-  process $group_3
-    assign \src221__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $10 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest121__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src221__data_o \dest121__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest221__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src221__data_o \dest221__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $12 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \src221__data_o \reg
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \src221__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
+  process $group_71
+    assign \op_is_ld 1'0
+    assign \op_is_ld $55
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect$14
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $15
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $16
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:112"
+  wire width 1 \load_mem_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:400"
+  wire width 1 $57
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:400"
+  cell $and $58
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src321__ren
-    connect \B 1'1
-    connect \Y $15
+    connect \A \op_is_ld
+    connect \B \cu_ad__go_i
+    connect \Y $57
   end
-  process $group_4
-    assign \wr_detect$14 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $15 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        assign \wr_detect$14 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest121__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$14 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest221__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$14 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-    end
+  process $group_72
+    assign \load_mem_o 1'0
+    assign \load_mem_o $57
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $17
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $18
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:113"
+  wire width 1 \stwd_mem_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:401"
+  wire width 1 $59
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:401"
+  cell $and $60
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src321__ren
-    connect \B 1'1
-    connect \Y $17
+    connect \A \op_is_st
+    connect \B \cu_st__go_i
+    connect \Y $59
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  wire width 1 $19
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $20
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \wr_detect$14
-    connect \Y $19
+  process $group_73
+    assign \stwd_mem_o 1'0
+    assign \stwd_mem_o $59
+    sync init
   end
-  process $group_5
-    assign \src321__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $17 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest121__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src321__data_o \dest121__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest221__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src321__data_o \dest221__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $19 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \src321__data_o \reg
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \src321__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:108"
+  wire width 1 \ld_o
+  process $group_74
+    assign \ld_o 1'0
+    assign \ld_o \op_is_ld
     sync init
   end
-  process $group_6
-    assign \reg$next \reg
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-    switch { \dest121__wen }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-      case 1'1
-        assign \reg$next \dest121__data_i
-    end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-    switch { \dest221__wen }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-      case 1'1
-        assign \reg$next \dest221__data_i
-    end
-    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
-      case 1'1
-        assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:109"
+  wire width 1 \st_o
+  process $group_75
+    assign \st_o 1'0
+    assign \st_o \op_is_st
     sync init
-      update \reg 64'0000000000000000000000000000000000000000000000000000000000000000
-    sync posedge \clk
-      update \reg \reg$next
   end
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.int.reg_22"
-module \reg_22
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 2 \src122__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 3 \src122__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 4 \src222__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 5 \src222__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 6 \src322__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 7 \src322__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 8 \dest122__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 9 \dest122__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 10 \dest222__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 11 \dest222__data_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $2
+  process $group_76
+    assign \cu_busy_o 1'0
+    assign \cu_busy_o \opc_l_q_opc
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:416"
+  wire width 3 $61
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:416"
+  cell $and $62
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
+    parameter \A_WIDTH 3
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \src122__ren
-    connect \B 1'1
-    connect \Y $1
+    parameter \B_WIDTH 3
+    parameter \Y_WIDTH 3
+    connect \A \src_l_q_src
+    connect \B { \cu_busy_o \cu_busy_o \cu_busy_o }
+    connect \Y $61
   end
-  process $group_0
-    assign \wr_detect 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $1 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        assign \wr_detect 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest122__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest222__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-    end
-    sync init
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:416"
+  wire width 2 $63
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:416"
+  cell $not $64
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 2
+    parameter \Y_WIDTH 2
+    connect \A { \oper_r__imm_data__imm_ok \oper_r__zero_a }
+    connect \Y $63
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $3
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $4
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:416"
+  wire width 3 $65
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:416"
+  cell $and $66
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 3
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 2
+    parameter \Y_WIDTH 3
+    connect \A $61
+    connect \B $63
+    connect \Y $65
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:416"
+  wire width 3 $67
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:416"
+  cell $not $68
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 3
+    parameter \Y_WIDTH 3
+    connect \A \cu_rdmaskn_i
+    connect \Y $67
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:416"
+  wire width 3 $69
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:416"
+  cell $and $70
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 3
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 3
+    parameter \Y_WIDTH 3
+    connect \A $65
+    connect \B $67
+    connect \Y $69
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:425"
+  wire width 1 $71
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:425"
+  cell $and $72
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src122__ren
-    connect \B 1'1
-    connect \Y $3
+    connect \A \src_l_q_src [2]
+    connect \B \cu_busy_o
+    connect \Y $71
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  wire width 1 $5
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $6
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:425"
+  wire width 1 $73
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:425"
+  cell $and $74
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr_detect
-    connect \Y $5
+    connect \A $71
+    connect \B \op_is_st
+    connect \Y $73
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
-  wire width 64 \reg
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
-  wire width 64 \reg$next
-  process $group_1
-    assign \src122__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $3 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest122__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src122__data_o \dest122__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest222__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src122__data_o \dest222__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $5 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \src122__data_o \reg
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \src122__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
+  process $group_77
+    assign \cu_rd__rel_o 3'000
+    assign \cu_rd__rel_o $69
+    assign \cu_rd__rel_o [2] $73
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect$7
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $8
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $9
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:419"
+  wire width 1 $75
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:419"
+  cell $or $76
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src222__ren
-    connect \B 1'1
-    connect \Y $8
+    connect \A \cu_rd__go_i [0]
+    connect \B \cu_rd__go_i [1]
+    connect \Y $75
   end
-  process $group_2
-    assign \wr_detect$7 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $8 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        assign \wr_detect$7 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest122__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$7 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest222__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$7 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-    end
+  process $group_78
+    assign \rda_any 1'0
+    assign \rda_any $75
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $10
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $11
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:422"
+  wire width 1 $77
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:422"
+  wire width 1 $78
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:422"
+  cell $or $79
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src222__ren
-    connect \B 1'1
-    connect \Y $10
+    connect \A \cu_rd__rel_o [0]
+    connect \B \cu_rd__rel_o [1]
+    connect \Y $78
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  wire width 1 $12
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $13
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:422"
+  cell $not $80
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr_detect$7
-    connect \Y $12
-  end
-  process $group_3
-    assign \src222__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $10 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest122__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src222__data_o \dest122__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest222__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src222__data_o \dest222__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $12 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \src222__data_o \reg
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \src222__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
-    sync init
+    connect \A $78
+    connect \Y $77
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect$14
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $15
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $16
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:422"
+  wire width 1 $81
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:422"
+  cell $and $82
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src322__ren
-    connect \B 1'1
-    connect \Y $15
+    connect \A \cu_busy_o
+    connect \B $77
+    connect \Y $81
   end
-  process $group_4
-    assign \wr_detect$14 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $15 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        assign \wr_detect$14 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest122__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$14 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest222__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$14 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-    end
+  process $group_79
+    assign \alu_valid 1'0
+    assign \alu_valid $81
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $17
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $18
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:274"
+  wire width 1 \rd_done
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428"
+  wire width 1 $83
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428"
+  cell $not $84
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src322__ren
-    connect \B 1'1
-    connect \Y $17
+    connect \A \cu_rd__rel_o [2]
+    connect \Y $83
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  wire width 1 $19
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $20
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428"
+  wire width 1 $85
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:428"
+  cell $and $86
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr_detect$14
-    connect \Y $19
-  end
-  process $group_5
-    assign \src322__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $17 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest122__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src322__data_o \dest122__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest222__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src322__data_o \dest222__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $19 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \src322__data_o \reg
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \src322__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
-    sync init
+    connect \A \alu_valid
+    connect \B $83
+    connect \Y $85
   end
-  process $group_6
-    assign \reg$next \reg
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-    switch { \dest122__wen }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-      case 1'1
-        assign \reg$next \dest122__data_i
-    end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-    switch { \dest222__wen }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-      case 1'1
-        assign \reg$next \dest222__data_i
-    end
-    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
-      case 1'1
-        assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
+  process $group_80
+    assign \rd_done 1'0
+    assign \rd_done $85
     sync init
-      update \reg 64'0000000000000000000000000000000000000000000000000000000000000000
-    sync posedge \clk
-      update \reg \reg$next
   end
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.int.reg_23"
-module \reg_23
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 2 \src123__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 3 \src123__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 4 \src223__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 5 \src223__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 6 \src323__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 7 \src323__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 8 \dest123__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 9 \dest123__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 10 \dest223__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 11 \dest223__data_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $2
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:431"
+  wire width 1 $87
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:431"
+  cell $and $88
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src123__ren
-    connect \B 1'1
-    connect \Y $1
+    connect \A \alu_valid
+    connect \B \adr_l_q_adr
+    connect \Y $87
   end
-  process $group_0
-    assign \wr_detect 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $1 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        assign \wr_detect 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest123__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest223__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-    end
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $3
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $4
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:431"
+  wire width 1 $89
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:431"
+  cell $and $90
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src123__ren
-    connect \B 1'1
-    connect \Y $3
+    connect \A $87
+    connect \B \cu_busy_o
+    connect \Y $89
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  wire width 1 $5
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $6
+  process $group_81
+    assign \cu_ad__rel_o 1'0
+    assign \cu_ad__rel_o $89
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434"
+  wire width 1 $91
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434"
+  cell $and $92
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr_detect
-    connect \Y $5
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
-  wire width 64 \reg
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
-  wire width 64 \reg$next
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-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $3 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest123__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src123__data_o \dest123__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest223__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src123__data_o \dest223__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $5 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \src123__data_o \reg
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \src123__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
-    sync init
+    connect \A \sto_l_q_sto
+    connect \B \cu_busy_o
+    connect \Y $91
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect$7
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $8
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $9
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434"
+  wire width 1 $93
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434"
+  cell $and $94
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src223__ren
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-    connect \Y $8
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-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $8 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
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-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest123__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
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-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest223__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
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-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-    end
-    sync init
+    connect \A $91
+    connect \B \rd_done
+    connect \Y $93
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $10
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $11
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434"
+  wire width 1 $95
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:434"
+  cell $and $96
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src223__ren
-    connect \B 1'1
-    connect \Y $10
+    connect \A $93
+    connect \B \op_is_st
+    connect \Y $95
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  wire width 1 $12
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $13
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:101"
+  wire width 1 \cu_shadown_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:435"
+  wire width 1 $97
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:435"
+  cell $and $98
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr_detect$7
-    connect \Y $12
+    connect \A $95
+    connect \B \cu_shadown_i
+    connect \Y $97
   end
-  process $group_3
-    assign \src223__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $10 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest123__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src223__data_o \dest123__data_i
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-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest223__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src223__data_o \dest223__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $12 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \src223__data_o \reg
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \src223__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
+  process $group_82
+    assign \cu_st__rel_o 1'0
+    assign \cu_st__rel_o $97
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect$14
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $15
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $16
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:439"
+  wire width 1 $99
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:439"
+  cell $and $100
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src323__ren
-    connect \B 1'1
-    connect \Y $15
-  end
-  process $group_4
-    assign \wr_detect$14 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $15 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        assign \wr_detect$14 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest123__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$14 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest223__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$14 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-    end
-    sync init
+    connect \A \rd_done
+    connect \B \wri_l_q_wri
+    connect \Y $99
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $17
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $18
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:439"
+  wire width 1 $101
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:439"
+  cell $and $102
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src323__ren
-    connect \B 1'1
-    connect \Y $17
+    connect \A $99
+    connect \B \cu_busy_o
+    connect \Y $101
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  wire width 1 $19
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $20
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:439"
+  wire width 1 $103
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:439"
+  cell $and $104
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr_detect$14
-    connect \Y $19
-  end
-  process $group_5
-    assign \src323__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $17 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest123__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src323__data_o \dest123__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest223__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src323__data_o \dest223__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $19 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \src323__data_o \reg
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-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \src323__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
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-    sync init
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-  process $group_6
-    assign \reg$next \reg
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-    switch { \dest123__wen }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-      case 1'1
-        assign \reg$next \dest123__data_i
-    end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-    switch { \dest223__wen }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-      case 1'1
-        assign \reg$next \dest223__data_i
-    end
-    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
-      case 1'1
-        assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
-    sync init
-      update \reg 64'0000000000000000000000000000000000000000000000000000000000000000
-    sync posedge \clk
-      update \reg \reg$next
+    connect \A $101
+    connect \B \lod_l_qn_lod
+    connect \Y $103
   end
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.int.reg_24"
-module \reg_24
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 2 \src124__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 3 \src124__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 4 \src224__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 5 \src224__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 6 \src324__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 7 \src324__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 8 \dest124__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 9 \dest124__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 10 \dest224__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 11 \dest224__data_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $2
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:439"
+  wire width 1 $105
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:439"
+  cell $and $106
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src124__ren
-    connect \B 1'1
-    connect \Y $1
-  end
-  process $group_0
-    assign \wr_detect 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $1 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        assign \wr_detect 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest124__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest224__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-    end
-    sync init
+    connect \A $103
+    connect \B \op_is_ld
+    connect \Y $105
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $3
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $4
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:439"
+  wire width 1 $107
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:439"
+  cell $and $108
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src124__ren
-    connect \B 1'1
-    connect \Y $3
+    connect \A $105
+    connect \B \cu_shadown_i
+    connect \Y $107
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  wire width 1 $5
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $6
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:443"
+  wire width 1 $109
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:443"
+  cell $and $110
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr_detect
-    connect \Y $5
+    connect \A \upd_l_q_upd
+    connect \B \cu_busy_o
+    connect \Y $109
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
-  wire width 64 \reg
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
-  wire width 64 \reg$next
-  process $group_1
-    assign \src124__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $3 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest124__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src124__data_o \dest124__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest224__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src124__data_o \dest224__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $5 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \src124__data_o \reg
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \src124__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
-    sync init
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:398"
+  wire width 1 $111
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:398"
+  cell $eq $112
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 2
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 2
+    parameter \Y_WIDTH 1
+    connect \A \oper_r__ldst_mode
+    connect \B 2'01
+    connect \Y $111
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect$7
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $8
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $9
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:443"
+  wire width 1 $113
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:443"
+  cell $and $114
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src224__ren
-    connect \B 1'1
-    connect \Y $8
-  end
-  process $group_2
-    assign \wr_detect$7 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $8 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        assign \wr_detect$7 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest124__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$7 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest224__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$7 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-    end
-    sync init
+    connect \A $109
+    connect \B $111
+    connect \Y $113
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $10
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $11
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:443"
+  wire width 1 $115
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:443"
+  cell $and $116
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src224__ren
-    connect \B 1'1
-    connect \Y $10
+    connect \A $113
+    connect \B \alu_valid
+    connect \Y $115
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  wire width 1 $12
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $13
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:443"
+  wire width 1 $117
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:443"
+  cell $and $118
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr_detect$7
-    connect \Y $12
+    connect \A $115
+    connect \B \cu_shadown_i
+    connect \Y $117
   end
-  process $group_3
-    assign \src224__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $10 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest124__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src224__data_o \dest124__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest224__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src224__data_o \dest224__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $12 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \src224__data_o \reg
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \src224__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
+  process $group_83
+    assign \cu_wr__rel_o 2'00
+    assign \cu_wr__rel_o [0] $107
+    assign \cu_wr__rel_o [1] $117
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect$14
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $15
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $16
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:272"
+  wire width 1 \wr_any
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:447"
+  wire width 1 $119
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:447"
+  cell $or $120
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src324__ren
-    connect \B 1'1
-    connect \Y $15
-  end
-  process $group_4
-    assign \wr_detect$14 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $15 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        assign \wr_detect$14 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest124__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$14 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest224__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$14 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-    end
-    sync init
+    connect \A \cu_st__go_i
+    connect \B \p_st_go
+    connect \Y $119
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $17
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $18
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:447"
+  wire width 1 $121
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:447"
+  cell $or $122
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src324__ren
-    connect \B 1'1
-    connect \Y $17
+    connect \A $119
+    connect \B \cu_wr__go_i [0]
+    connect \Y $121
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  wire width 1 $19
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $20
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:447"
+  wire width 1 $123
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:447"
+  cell $or $124
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr_detect$14
-    connect \Y $19
-  end
-  process $group_5
-    assign \src324__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $17 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest124__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src324__data_o \dest124__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest224__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src324__data_o \dest224__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $19 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \src324__data_o \reg
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \src324__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
-    sync init
+    connect \A $121
+    connect \B \cu_wr__go_i [1]
+    connect \Y $123
   end
-  process $group_6
-    assign \reg$next \reg
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-    switch { \dest124__wen }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-      case 1'1
-        assign \reg$next \dest124__data_i
-    end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-    switch { \dest224__wen }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-      case 1'1
-        assign \reg$next \dest224__data_i
-    end
-    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
-      case 1'1
-        assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
+  process $group_84
+    assign \wr_any 1'0
+    assign \wr_any $123
     sync init
-      update \reg 64'0000000000000000000000000000000000000000000000000000000000000000
-    sync posedge \clk
-      update \reg \reg$next
   end
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.int.reg_25"
-module \reg_25
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 2 \src125__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 3 \src125__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 4 \src225__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 5 \src225__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 6 \src325__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 7 \src325__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 8 \dest125__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 9 \dest125__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 10 \dest225__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 11 \dest225__data_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $2
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:450"
+  wire width 1 $125
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:450"
+  cell $and $126
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src125__ren
-    connect \B 1'1
-    connect \Y $1
-  end
-  process $group_0
-    assign \wr_detect 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $1 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        assign \wr_detect 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest125__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest225__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-    end
-    sync init
+    connect \A \rst_l_q_rst
+    connect \B \cu_busy_o
+    connect \Y $125
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $3
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $4
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:450"
+  wire width 1 $127
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:450"
+  cell $and $128
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src125__ren
-    connect \B 1'1
-    connect \Y $3
+    connect \A $125
+    connect \B \cu_shadown_i
+    connect \Y $127
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  wire width 1 $5
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $6
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:450"
+  wire width 1 $129
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:450"
+  wire width 1 $130
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:450"
+  cell $or $131
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr_detect
-    connect \Y $5
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
-  wire width 64 \reg
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
-  wire width 64 \reg$next
-  process $group_1
-    assign \src125__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $3 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest125__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src125__data_o \dest125__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest225__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src125__data_o \dest225__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $5 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \src125__data_o \reg
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \src125__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
-    sync init
+    connect \A \cu_st__rel_o
+    connect \B \cu_wr__rel_o [0]
+    connect \Y $130
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect$7
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $8
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $9
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:450"
+  wire width 1 $132
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:450"
+  cell $or $133
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src225__ren
-    connect \B 1'1
-    connect \Y $8
+    connect \A $130
+    connect \B \cu_wr__rel_o [1]
+    connect \Y $132
   end
-  process $group_2
-    assign \wr_detect$7 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $8 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        assign \wr_detect$7 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest125__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$7 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest225__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$7 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-    end
-    sync init
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:450"
+  cell $not $134
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $132
+    connect \Y $129
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $10
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $11
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:450"
+  wire width 1 $135
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:450"
+  cell $and $136
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src225__ren
-    connect \B 1'1
-    connect \Y $10
+    connect \A $127
+    connect \B $129
+    connect \Y $135
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  wire width 1 $12
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $13
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:451"
+  wire width 1 $137
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:451"
+  cell $or $138
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr_detect$7
-    connect \Y $12
-  end
-  process $group_3
-    assign \src225__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $10 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest125__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src225__data_o \dest125__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest225__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src225__data_o \dest225__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $12 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \src225__data_o \reg
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \src225__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
-    sync init
+    connect \A \lod_l_qn_lod
+    connect \B \op_is_st
+    connect \Y $137
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect$14
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $15
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $16
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:451"
+  wire width 1 $139
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:451"
+  cell $and $140
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src325__ren
-    connect \B 1'1
-    connect \Y $15
+    connect \A $135
+    connect \B $137
+    connect \Y $139
   end
-  process $group_4
-    assign \wr_detect$14 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $15 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  process $group_85
+    assign \wr_reset 1'0
+    assign \wr_reset $139
+    sync init
+  end
+  process $group_86
+    assign \cu_done_o 1'0
+    assign \cu_done_o \wr_reset
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
+  wire width 64 \dest1_o
+  process $group_87
+    assign \o 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \o \dest1_o
+    sync init
+  end
+  process $group_88
+    assign \dest1_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:459"
+    switch { \cu_wr__go_i [0] }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:459"
       case 1'1
-        assign \wr_detect$14 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest125__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$14 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest225__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$14 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
+        assign \dest1_o \ldd_r
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $17
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $18
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
+  wire width 64 \dest2_o
+  process $group_89
+    assign \ea 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \ea \dest2_o
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:398"
+  wire width 1 $141
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:398"
+  cell $eq $142
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
+    parameter \A_WIDTH 2
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
+    parameter \B_WIDTH 2
     parameter \Y_WIDTH 1
-    connect \A \src325__ren
-    connect \B 1'1
-    connect \Y $17
+    connect \A \oper_r__ldst_mode
+    connect \B 2'01
+    connect \Y $141
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  wire width 1 $19
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $20
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:464"
+  wire width 1 $143
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:464"
+  cell $and $144
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wr_detect$14
-    connect \Y $19
+    connect \A $141
+    connect \B \cu_wr__go_i [1]
+    connect \Y $143
   end
-  process $group_5
-    assign \src325__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $17 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  process $group_90
+    assign \dest2_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:464"
+    switch { $143 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:464"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest125__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src325__data_o \dest125__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest225__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src325__data_o \dest225__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $19 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \src325__data_o \reg
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \src325__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+        assign \dest2_o \addr_r
     end
     sync init
   end
-  process $group_6
-    assign \reg$next \reg
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-    switch { \dest125__wen }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-      case 1'1
-        assign \reg$next \dest125__data_i
-    end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-    switch { \dest225__wen }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-      case 1'1
-        assign \reg$next \dest225__data_i
-    end
-    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
-      case 1'1
-        assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96"
+  wire width 2 \cu_wrmask_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:469"
+  wire width 3 $145
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:398"
+  wire width 1 $146
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:398"
+  cell $eq $147
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 2
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 2
+    parameter \Y_WIDTH 1
+    connect \A \oper_r__ldst_mode
+    connect \B 2'01
+    connect \Y $146
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:469"
+  wire width 3 $148
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:469"
+  cell $and $149
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 3
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 2
+    parameter \Y_WIDTH 3
+    connect \A { \cu_busy_o \cu_busy_o \cu_busy_o }
+    connect \B { $146 \op_is_ld }
+    connect \Y $148
+  end
+  connect $145 $148
+  process $group_91
+    assign \cu_wrmask_o 2'00
+    assign \cu_wrmask_o $145 [1:0]
     sync init
-      update \reg 64'0000000000000000000000000000000000000000000000000000000000000000
-    sync posedge \clk
-      update \reg \reg$next
   end
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.int.reg_26"
-module \reg_26
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 2 \src126__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 3 \src126__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 4 \src226__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 5 \src226__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 6 \src326__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 7 \src326__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 8 \dest126__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 9 \dest126__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 10 \dest226__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 11 \dest226__data_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $2
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:476"
+  wire width 1 $150
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:476"
+  cell $and $151
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src126__ren
-    connect \B 1'1
-    connect \Y $1
+    connect \A \op_is_ld
+    connect \B \cu_busy_o
+    connect \Y $150
   end
-  process $group_0
-    assign \wr_detect 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $1 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        assign \wr_detect 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest126__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest226__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-    end
+  process $group_92
+    assign \ldst_port0_is_ld_i 1'0
+    assign \ldst_port0_is_ld_i $150
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $3
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $4
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:477"
+  wire width 1 $152
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:477"
+  cell $and $153
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src126__ren
-    connect \B 1'1
-    connect \Y $3
+    connect \A \op_is_st
+    connect \B \cu_busy_o
+    connect \Y $152
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  wire width 1 $5
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $6
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \wr_detect
-    connect \Y $5
+  process $group_93
+    assign \ldst_port0_is_st_i 1'0
+    assign \ldst_port0_is_st_i $152
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
-  wire width 64 \reg
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
-  wire width 64 \reg$next
-  process $group_1
-    assign \src126__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $3 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest126__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src126__data_o \dest126__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest226__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src126__data_o \dest226__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $5 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \src126__data_o \reg
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-        assign \src126__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
+  process $group_94
+    assign \ldst_port0_data_len 4'0000
+    assign \ldst_port0_data_len \oper_i_ldst_ldst0__data_len
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect$7
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $8
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $9
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:378"
+  wire width 96 $154
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:378"
+  cell $pos $155
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \src226__ren
-    connect \B 1'1
-    connect \Y $8
+    parameter \A_WIDTH 64
+    parameter \Y_WIDTH 96
+    connect \A \addr_r
+    connect \Y $154
   end
-  process $group_2
-    assign \wr_detect$7 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $8 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-      case 1'1
-        assign \wr_detect$7 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest126__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$7 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest226__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$7 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
-      case
-    end
+  process $group_95
+    assign \ldst_port0_addr_i 96'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
+    assign \ldst_port0_addr_i $154
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $10
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $11
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:481"
+  wire width 1 $156
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:481"
+  cell $and $157
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \src226__ren
-    connect \B 1'1
-    connect \Y $10
+    connect \A \alu_ok
+    connect \B \lsd_l_q_lsd
+    connect \Y $156
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  wire width 1 $12
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $13
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \wr_detect$7
-    connect \Y $12
+  process $group_96
+    assign \ldst_port0_addr_i_ok 1'0
+    assign \ldst_port0_addr_i_ok $156
+    sync init
   end
-  process $group_3
-    assign \src226__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $10 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:106"
+  wire width 1 \addr_exc_o
+  process $group_97
+    assign \addr_exc_o 1'0
+    assign \addr_exc_o \ldst_port0_addr_exc_o
+    sync init
+  end
+  process $group_98
+    assign \addr_ok 1'0
+    assign \addr_ok \ldst_port0_addr_ok_o
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:11"
+  wire width 64 \lddata_r
+  process $group_99
+    assign \lddata_r 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:486"
+    switch { \oper_i_ldst_ldst0__byte_reverse }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:486"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest126__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src226__data_o \dest126__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest226__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src226__data_o \dest226__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $12 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \src226__data_o \reg
+        attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:12"
+        switch \oper_i_ldst_ldst0__data_len
+          attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:14"
+          case 4'0001
+            assign \lddata_r [7:0] \ldst_port0_ld_data_o [7:0]
+          attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:14"
+          case 4'0010
+            assign \lddata_r [7:0] \ldst_port0_ld_data_o [15:8]
+            assign \lddata_r [15:8] \ldst_port0_ld_data_o [7:0]
+          attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:14"
+          case 4'0100
+            assign \lddata_r [7:0] \ldst_port0_ld_data_o [31:24]
+            assign \lddata_r [15:8] \ldst_port0_ld_data_o [23:16]
+            assign \lddata_r [23:16] \ldst_port0_ld_data_o [15:8]
+            assign \lddata_r [31:24] \ldst_port0_ld_data_o [7:0]
+          attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:14"
+          case 4'1000
+            assign \lddata_r [7:0] \ldst_port0_ld_data_o [63:56]
+            assign \lddata_r [15:8] \ldst_port0_ld_data_o [55:48]
+            assign \lddata_r [23:16] \ldst_port0_ld_data_o [47:40]
+            assign \lddata_r [31:24] \ldst_port0_ld_data_o [39:32]
+            assign \lddata_r [39:32] \ldst_port0_ld_data_o [31:24]
+            assign \lddata_r [47:40] \ldst_port0_ld_data_o [23:16]
+            assign \lddata_r [55:48] \ldst_port0_ld_data_o [15:8]
+            assign \lddata_r [63:56] \ldst_port0_ld_data_o [7:0]
         end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:491"
       case
-        assign \src226__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect$14
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $15
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $16
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \src326__ren
-    connect \B 1'1
-    connect \Y $15
-  end
-  process $group_4
-    assign \wr_detect$14 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $15 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  process $group_100
+    assign \ldd_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:486"
+    switch { \oper_i_ldst_ldst0__byte_reverse }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:486"
       case 1'1
-        assign \wr_detect$14 1'0
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest126__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$14 1'1
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest226__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \wr_detect$14 1'1
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+        assign \ldd_o \lddata_r
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:491"
       case
+        assign \ldd_o \ldst_port0_ld_data_o
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $17
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $18
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \src326__ren
-    connect \B 1'1
-    connect \Y $17
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  wire width 1 $19
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-  cell $not $20
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \wr_detect$14
-    connect \Y $19
+  process $group_101
+    assign \ld_ok 1'0
+    assign \ld_ok \ldst_port0_ld_data_o_ok
+    sync init
   end
-  process $group_5
-    assign \src326__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-    switch { $17 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:11"
+  wire width 64 \stdata_r
+  process $group_102
+    assign \stdata_r 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:498"
+    switch { \oper_i_ldst_ldst0__byte_reverse }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:498"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest126__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src326__data_o \dest126__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-        switch { \dest226__wen }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
-          case 1'1
-            assign \src326__data_o \dest226__data_i
-        end
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-        switch { $19 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
-          case 1'1
-            assign \src326__data_o \reg
+        attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:12"
+        switch \oper_i_ldst_ldst0__data_len
+          attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:14"
+          case 4'0001
+            assign \stdata_r [7:0] \src_r2 [7:0]
+          attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:14"
+          case 4'0010
+            assign \stdata_r [7:0] \src_r2 [15:8]
+            assign \stdata_r [15:8] \src_r2 [7:0]
+          attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:14"
+          case 4'0100
+            assign \stdata_r [7:0] \src_r2 [31:24]
+            assign \stdata_r [15:8] \src_r2 [23:16]
+            assign \stdata_r [23:16] \src_r2 [15:8]
+            assign \stdata_r [31:24] \src_r2 [7:0]
+          attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:14"
+          case 4'1000
+            assign \stdata_r [7:0] \src_r2 [63:56]
+            assign \stdata_r [15:8] \src_r2 [55:48]
+            assign \stdata_r [23:16] \src_r2 [47:40]
+            assign \stdata_r [31:24] \src_r2 [39:32]
+            assign \stdata_r [39:32] \src_r2 [31:24]
+            assign \stdata_r [47:40] \src_r2 [23:16]
+            assign \stdata_r [55:48] \src_r2 [15:8]
+            assign \stdata_r [63:56] \src_r2 [7:0]
         end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:503"
       case
-        assign \src326__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
     end
     sync init
   end
-  process $group_6
-    assign \reg$next \reg
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-    switch { \dest126__wen }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-      case 1'1
-        assign \reg$next \dest126__data_i
-    end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-    switch { \dest226__wen }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
-      case 1'1
-        assign \reg$next \dest226__data_i
-    end
-    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+  process $group_103
+    assign \ldst_port0_st_data_i 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:498"
+    switch { \oper_i_ldst_ldst0__byte_reverse }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:498"
       case 1'1
-        assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
+        assign \ldst_port0_st_data_i \stdata_r
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:503"
+      case
+        assign \ldst_port0_st_data_i \src_r2
     end
     sync init
-      update \reg 64'0000000000000000000000000000000000000000000000000000000000000000
-    sync posedge \clk
-      update \reg \reg$next
   end
+  process $group_104
+    assign \ldst_port0_st_data_i_ok 1'0
+    assign \ldst_port0_st_data_i_ok \cu_st__go_i
+    sync init
+  end
+  connect \cu_go_die_i 1'0
+  connect \cu_shadown_i 1'1
 end
 attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.core.int.reg_27"
-module \reg_27
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 2 \src127__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 3 \src127__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 4 \src227__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 5 \src227__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 6 \src327__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 7 \src327__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 8 \dest127__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 9 \dest127__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 10 \dest227__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 11 \dest227__data_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
-  wire width 1 \wr_detect
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  wire width 1 $1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
-  cell $eq $2
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
+attribute \nmigen.hierarchy "test_issuer.core.fus"
+module \fus
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+  wire width 1 input 1 \cu_ad__go_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+  wire width 1 output 2 \cu_ad__rel_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+  wire width 1 input 3 \cu_st__go_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+  wire width 1 output 4 \cu_st__rel_o
+  attribute \enum_base_type "MicrOp"
+  attribute \enum_value_0000000 "OP_ILLEGAL"
+  attribute \enum_value_0000001 "OP_NOP"
+  attribute \enum_value_0000010 "OP_ADD"
+  attribute \enum_value_0000011 "OP_ADDPCIS"
+  attribute \enum_value_0000100 "OP_AND"
+  attribute \enum_value_0000101 "OP_ATTN"
+  attribute \enum_value_0000110 "OP_B"
+  attribute \enum_value_0000111 "OP_BC"
+  attribute \enum_value_0001000 "OP_BCREG"
+  attribute \enum_value_0001001 "OP_BPERM"
+  attribute \enum_value_0001010 "OP_CMP"
+  attribute \enum_value_0001011 "OP_CMPB"
+  attribute \enum_value_0001100 "OP_CMPEQB"
+  attribute \enum_value_0001101 "OP_CMPRB"
+  attribute \enum_value_0001110 "OP_CNTZ"
+  attribute \enum_value_0001111 "OP_CRAND"
+  attribute \enum_value_0010000 "OP_CRANDC"
+  attribute \enum_value_0010001 "OP_CREQV"
+  attribute \enum_value_0010010 "OP_CRNAND"
+  attribute \enum_value_0010011 "OP_CRNOR"
+  attribute \enum_value_0010100 "OP_CROR"
+  attribute \enum_value_0010101 "OP_CRORC"
+  attribute \enum_value_0010110 "OP_CRXOR"
+  attribute \enum_value_0010111 "OP_DARN"
+  attribute \enum_value_0011000 "OP_DCBF"
+  attribute \enum_value_0011001 "OP_DCBST"
+  attribute \enum_value_0011010 "OP_DCBT"
+  attribute \enum_value_0011011 "OP_DCBTST"
+  attribute \enum_value_0011100 "OP_DCBZ"
+  attribute \enum_value_0011101 "OP_DIV"
+  attribute \enum_value_0011110 "OP_DIVE"
+  attribute \enum_value_0011111 "OP_EXTS"
+  attribute \enum_value_0100000 "OP_EXTSWSLI"
+  attribute \enum_value_0100001 "OP_ICBI"
+  attribute \enum_value_0100010 "OP_ICBT"
+  attribute \enum_value_0100011 "OP_ISEL"
+  attribute \enum_value_0100100 "OP_ISYNC"
+  attribute \enum_value_0100101 "OP_LOAD"
+  attribute \enum_value_0100110 "OP_STORE"
+  attribute \enum_value_0100111 "OP_MADDHD"
+  attribute \enum_value_0101000 "OP_MADDHDU"
+  attribute \enum_value_0101001 "OP_MADDLD"
+  attribute \enum_value_0101010 "OP_MCRF"
+  attribute \enum_value_0101011 "OP_MCRXR"
+  attribute \enum_value_0101100 "OP_MCRXRX"
+  attribute \enum_value_0101101 "OP_MFCR"
+  attribute \enum_value_0101110 "OP_MFSPR"
+  attribute \enum_value_0101111 "OP_MOD"
+  attribute \enum_value_0110000 "OP_MTCRF"
+  attribute \enum_value_0110001 "OP_MTSPR"
+  attribute \enum_value_0110010 "OP_MUL_L64"
+  attribute \enum_value_0110011 "OP_MUL_H64"
+  attribute \enum_value_0110100 "OP_MUL_H32"
+  attribute \enum_value_0110101 "OP_OR"
+  attribute \enum_value_0110110 "OP_POPCNT"
+  attribute \enum_value_0110111 "OP_PRTY"
+  attribute \enum_value_0111000 "OP_RLC"
+  attribute \enum_value_0111001 "OP_RLCL"
+  attribute \enum_value_0111010 "OP_RLCR"
+  attribute \enum_value_0111011 "OP_SETB"
+  attribute \enum_value_0111100 "OP_SHL"
+  attribute \enum_value_0111101 "OP_SHR"
+  attribute \enum_value_0111110 "OP_SYNC"
+  attribute \enum_value_0111111 "OP_TRAP"
+  attribute \enum_value_1000011 "OP_XOR"
+  attribute \enum_value_1000100 "OP_SIM_CONFIG"
+  attribute \enum_value_1000101 "OP_CROP"
+  attribute \enum_value_1000110 "OP_RFID"
+  attribute \enum_value_1000111 "OP_MFMSR"
+  attribute \enum_value_1001000 "OP_MTMSRD"
+  attribute \enum_value_1001001 "OP_SC"
+  attribute \enum_value_1001010 "OP_MTMSR"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 input 5 \oper_i_alu_alu0__insn_type
+  attribute \enum_base_type "Function"
+  attribute \enum_value_00000000000 "NONE"
+  attribute \enum_value_00000000010 "ALU"
+  attribute \enum_value_00000000100 "LDST"
+  attribute \enum_value_00000001000 "SHIFT_ROT"
+  attribute \enum_value_00000010000 "LOGICAL"
+  attribute \enum_value_00000100000 "BRANCH"
+  attribute \enum_value_00001000000 "CR"
+  attribute \enum_value_00010000000 "TRAP"
+  attribute \enum_value_00100000000 "MUL"
+  attribute \enum_value_01000000000 "DIV"
+  attribute \enum_value_10000000000 "SPR"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 input 6 \oper_i_alu_alu0__fn_unit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 input 7 \oper_i_alu_alu0__imm_data__imm
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 8 \oper_i_alu_alu0__imm_data__imm_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 9 \oper_i_alu_alu0__rc__rc
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 10 \oper_i_alu_alu0__rc__rc_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 11 \oper_i_alu_alu0__oe__oe
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 12 \oper_i_alu_alu0__oe__oe_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 13 \oper_i_alu_alu0__invert_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 14 \oper_i_alu_alu0__zero_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 15 \oper_i_alu_alu0__invert_out
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 16 \oper_i_alu_alu0__write_cr0
+  attribute \enum_base_type "CryIn"
+  attribute \enum_value_00 "ZERO"
+  attribute \enum_value_01 "ONE"
+  attribute \enum_value_10 "CA"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 2 input 17 \oper_i_alu_alu0__input_carry
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 18 \oper_i_alu_alu0__output_carry
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 19 \oper_i_alu_alu0__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 20 \oper_i_alu_alu0__is_signed
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 4 input 21 \oper_i_alu_alu0__data_len
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 input 22 \oper_i_alu_alu0__insn
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
+  wire width 1 input 23 \cu_issue_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:106"
+  wire width 1 output 24 \cu_busy_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
+  wire width 4 input 25 \cu_rdmaskn_i
+  attribute \enum_base_type "MicrOp"
+  attribute \enum_value_0000000 "OP_ILLEGAL"
+  attribute \enum_value_0000001 "OP_NOP"
+  attribute \enum_value_0000010 "OP_ADD"
+  attribute \enum_value_0000011 "OP_ADDPCIS"
+  attribute \enum_value_0000100 "OP_AND"
+  attribute \enum_value_0000101 "OP_ATTN"
+  attribute \enum_value_0000110 "OP_B"
+  attribute \enum_value_0000111 "OP_BC"
+  attribute \enum_value_0001000 "OP_BCREG"
+  attribute \enum_value_0001001 "OP_BPERM"
+  attribute \enum_value_0001010 "OP_CMP"
+  attribute \enum_value_0001011 "OP_CMPB"
+  attribute \enum_value_0001100 "OP_CMPEQB"
+  attribute \enum_value_0001101 "OP_CMPRB"
+  attribute \enum_value_0001110 "OP_CNTZ"
+  attribute \enum_value_0001111 "OP_CRAND"
+  attribute \enum_value_0010000 "OP_CRANDC"
+  attribute \enum_value_0010001 "OP_CREQV"
+  attribute \enum_value_0010010 "OP_CRNAND"
+  attribute \enum_value_0010011 "OP_CRNOR"
+  attribute \enum_value_0010100 "OP_CROR"
+  attribute \enum_value_0010101 "OP_CRORC"
+  attribute \enum_value_0010110 "OP_CRXOR"
+  attribute \enum_value_0010111 "OP_DARN"
+  attribute \enum_value_0011000 "OP_DCBF"
+  attribute \enum_value_0011001 "OP_DCBST"
+  attribute \enum_value_0011010 "OP_DCBT"
+  attribute \enum_value_0011011 "OP_DCBTST"
+  attribute \enum_value_0011100 "OP_DCBZ"
+  attribute \enum_value_0011101 "OP_DIV"
+  attribute \enum_value_0011110 "OP_DIVE"
+  attribute \enum_value_0011111 "OP_EXTS"
+  attribute \enum_value_0100000 "OP_EXTSWSLI"
+  attribute \enum_value_0100001 "OP_ICBI"
+  attribute \enum_value_0100010 "OP_ICBT"
+  attribute \enum_value_0100011 "OP_ISEL"
+  attribute \enum_value_0100100 "OP_ISYNC"
+  attribute \enum_value_0100101 "OP_LOAD"
+  attribute \enum_value_0100110 "OP_STORE"
+  attribute \enum_value_0100111 "OP_MADDHD"
+  attribute \enum_value_0101000 "OP_MADDHDU"
+  attribute \enum_value_0101001 "OP_MADDLD"
+  attribute \enum_value_0101010 "OP_MCRF"
+  attribute \enum_value_0101011 "OP_MCRXR"
+  attribute \enum_value_0101100 "OP_MCRXRX"
+  attribute \enum_value_0101101 "OP_MFCR"
+  attribute \enum_value_0101110 "OP_MFSPR"
+  attribute \enum_value_0101111 "OP_MOD"
+  attribute \enum_value_0110000 "OP_MTCRF"
+  attribute \enum_value_0110001 "OP_MTSPR"
+  attribute \enum_value_0110010 "OP_MUL_L64"
+  attribute \enum_value_0110011 "OP_MUL_H64"
+  attribute \enum_value_0110100 "OP_MUL_H32"
+  attribute \enum_value_0110101 "OP_OR"
+  attribute \enum_value_0110110 "OP_POPCNT"
+  attribute \enum_value_0110111 "OP_PRTY"
+  attribute \enum_value_0111000 "OP_RLC"
+  attribute \enum_value_0111001 "OP_RLCL"
+  attribute \enum_value_0111010 "OP_RLCR"
+  attribute \enum_value_0111011 "OP_SETB"
+  attribute \enum_value_0111100 "OP_SHL"
+  attribute \enum_value_0111101 "OP_SHR"
+  attribute \enum_value_0111110 "OP_SYNC"
+  attribute \enum_value_0111111 "OP_TRAP"
+  attribute \enum_value_1000011 "OP_XOR"
+  attribute \enum_value_1000100 "OP_SIM_CONFIG"
+  attribute \enum_value_1000101 "OP_CROP"
+  attribute \enum_value_1000110 "OP_RFID"
+  attribute \enum_value_1000111 "OP_MFMSR"
+  attribute \enum_value_1001000 "OP_MTMSRD"
+  attribute \enum_value_1001001 "OP_SC"
+  attribute \enum_value_1001010 "OP_MTMSR"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 input 26 \oper_i_alu_cr0__insn_type
+  attribute \enum_base_type "Function"
+  attribute \enum_value_00000000000 "NONE"
+  attribute \enum_value_00000000010 "ALU"
+  attribute \enum_value_00000000100 "LDST"
+  attribute \enum_value_00000001000 "SHIFT_ROT"
+  attribute \enum_value_00000010000 "LOGICAL"
+  attribute \enum_value_00000100000 "BRANCH"
+  attribute \enum_value_00001000000 "CR"
+  attribute \enum_value_00010000000 "TRAP"
+  attribute \enum_value_00100000000 "MUL"
+  attribute \enum_value_01000000000 "DIV"
+  attribute \enum_value_10000000000 "SPR"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 input 27 \oper_i_alu_cr0__fn_unit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 input 28 \oper_i_alu_cr0__insn
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 29 \oper_i_alu_cr0__read_cr_whole
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 30 \oper_i_alu_cr0__write_cr_whole
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
+  wire width 1 input 31 \cu_issue_i$1
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:106"
+  wire width 1 output 32 \cu_busy_o$2
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
+  wire width 6 input 33 \cu_rdmaskn_i$3
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 input 34 \oper_i_alu_branch0__cia
+  attribute \enum_base_type "MicrOp"
+  attribute \enum_value_0000000 "OP_ILLEGAL"
+  attribute \enum_value_0000001 "OP_NOP"
+  attribute \enum_value_0000010 "OP_ADD"
+  attribute \enum_value_0000011 "OP_ADDPCIS"
+  attribute \enum_value_0000100 "OP_AND"
+  attribute \enum_value_0000101 "OP_ATTN"
+  attribute \enum_value_0000110 "OP_B"
+  attribute \enum_value_0000111 "OP_BC"
+  attribute \enum_value_0001000 "OP_BCREG"
+  attribute \enum_value_0001001 "OP_BPERM"
+  attribute \enum_value_0001010 "OP_CMP"
+  attribute \enum_value_0001011 "OP_CMPB"
+  attribute \enum_value_0001100 "OP_CMPEQB"
+  attribute \enum_value_0001101 "OP_CMPRB"
+  attribute \enum_value_0001110 "OP_CNTZ"
+  attribute \enum_value_0001111 "OP_CRAND"
+  attribute \enum_value_0010000 "OP_CRANDC"
+  attribute \enum_value_0010001 "OP_CREQV"
+  attribute \enum_value_0010010 "OP_CRNAND"
+  attribute \enum_value_0010011 "OP_CRNOR"
+  attribute \enum_value_0010100 "OP_CROR"
+  attribute \enum_value_0010101 "OP_CRORC"
+  attribute \enum_value_0010110 "OP_CRXOR"
+  attribute \enum_value_0010111 "OP_DARN"
+  attribute \enum_value_0011000 "OP_DCBF"
+  attribute \enum_value_0011001 "OP_DCBST"
+  attribute \enum_value_0011010 "OP_DCBT"
+  attribute \enum_value_0011011 "OP_DCBTST"
+  attribute \enum_value_0011100 "OP_DCBZ"
+  attribute \enum_value_0011101 "OP_DIV"
+  attribute \enum_value_0011110 "OP_DIVE"
+  attribute \enum_value_0011111 "OP_EXTS"
+  attribute \enum_value_0100000 "OP_EXTSWSLI"
+  attribute \enum_value_0100001 "OP_ICBI"
+  attribute \enum_value_0100010 "OP_ICBT"
+  attribute \enum_value_0100011 "OP_ISEL"
+  attribute \enum_value_0100100 "OP_ISYNC"
+  attribute \enum_value_0100101 "OP_LOAD"
+  attribute \enum_value_0100110 "OP_STORE"
+  attribute \enum_value_0100111 "OP_MADDHD"
+  attribute \enum_value_0101000 "OP_MADDHDU"
+  attribute \enum_value_0101001 "OP_MADDLD"
+  attribute \enum_value_0101010 "OP_MCRF"
+  attribute \enum_value_0101011 "OP_MCRXR"
+  attribute \enum_value_0101100 "OP_MCRXRX"
+  attribute \enum_value_0101101 "OP_MFCR"
+  attribute \enum_value_0101110 "OP_MFSPR"
+  attribute \enum_value_0101111 "OP_MOD"
+  attribute \enum_value_0110000 "OP_MTCRF"
+  attribute \enum_value_0110001 "OP_MTSPR"
+  attribute \enum_value_0110010 "OP_MUL_L64"
+  attribute \enum_value_0110011 "OP_MUL_H64"
+  attribute \enum_value_0110100 "OP_MUL_H32"
+  attribute \enum_value_0110101 "OP_OR"
+  attribute \enum_value_0110110 "OP_POPCNT"
+  attribute \enum_value_0110111 "OP_PRTY"
+  attribute \enum_value_0111000 "OP_RLC"
+  attribute \enum_value_0111001 "OP_RLCL"
+  attribute \enum_value_0111010 "OP_RLCR"
+  attribute \enum_value_0111011 "OP_SETB"
+  attribute \enum_value_0111100 "OP_SHL"
+  attribute \enum_value_0111101 "OP_SHR"
+  attribute \enum_value_0111110 "OP_SYNC"
+  attribute \enum_value_0111111 "OP_TRAP"
+  attribute \enum_value_1000011 "OP_XOR"
+  attribute \enum_value_1000100 "OP_SIM_CONFIG"
+  attribute \enum_value_1000101 "OP_CROP"
+  attribute \enum_value_1000110 "OP_RFID"
+  attribute \enum_value_1000111 "OP_MFMSR"
+  attribute \enum_value_1001000 "OP_MTMSRD"
+  attribute \enum_value_1001001 "OP_SC"
+  attribute \enum_value_1001010 "OP_MTMSR"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 input 35 \oper_i_alu_branch0__insn_type
+  attribute \enum_base_type "Function"
+  attribute \enum_value_00000000000 "NONE"
+  attribute \enum_value_00000000010 "ALU"
+  attribute \enum_value_00000000100 "LDST"
+  attribute \enum_value_00000001000 "SHIFT_ROT"
+  attribute \enum_value_00000010000 "LOGICAL"
+  attribute \enum_value_00000100000 "BRANCH"
+  attribute \enum_value_00001000000 "CR"
+  attribute \enum_value_00010000000 "TRAP"
+  attribute \enum_value_00100000000 "MUL"
+  attribute \enum_value_01000000000 "DIV"
+  attribute \enum_value_10000000000 "SPR"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 input 36 \oper_i_alu_branch0__fn_unit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 input 37 \oper_i_alu_branch0__insn
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 input 38 \oper_i_alu_branch0__imm_data__imm
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 39 \oper_i_alu_branch0__imm_data__imm_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 40 \oper_i_alu_branch0__lk
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 41 \oper_i_alu_branch0__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
+  wire width 1 input 42 \cu_issue_i$4
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:106"
+  wire width 1 output 43 \cu_busy_o$5
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
+  wire width 3 input 44 \cu_rdmaskn_i$6
+  attribute \enum_base_type "MicrOp"
+  attribute \enum_value_0000000 "OP_ILLEGAL"
+  attribute \enum_value_0000001 "OP_NOP"
+  attribute \enum_value_0000010 "OP_ADD"
+  attribute \enum_value_0000011 "OP_ADDPCIS"
+  attribute \enum_value_0000100 "OP_AND"
+  attribute \enum_value_0000101 "OP_ATTN"
+  attribute \enum_value_0000110 "OP_B"
+  attribute \enum_value_0000111 "OP_BC"
+  attribute \enum_value_0001000 "OP_BCREG"
+  attribute \enum_value_0001001 "OP_BPERM"
+  attribute \enum_value_0001010 "OP_CMP"
+  attribute \enum_value_0001011 "OP_CMPB"
+  attribute \enum_value_0001100 "OP_CMPEQB"
+  attribute \enum_value_0001101 "OP_CMPRB"
+  attribute \enum_value_0001110 "OP_CNTZ"
+  attribute \enum_value_0001111 "OP_CRAND"
+  attribute \enum_value_0010000 "OP_CRANDC"
+  attribute \enum_value_0010001 "OP_CREQV"
+  attribute \enum_value_0010010 "OP_CRNAND"
+  attribute \enum_value_0010011 "OP_CRNOR"
+  attribute \enum_value_0010100 "OP_CROR"
+  attribute \enum_value_0010101 "OP_CRORC"
+  attribute \enum_value_0010110 "OP_CRXOR"
+  attribute \enum_value_0010111 "OP_DARN"
+  attribute \enum_value_0011000 "OP_DCBF"
+  attribute \enum_value_0011001 "OP_DCBST"
+  attribute \enum_value_0011010 "OP_DCBT"
+  attribute \enum_value_0011011 "OP_DCBTST"
+  attribute \enum_value_0011100 "OP_DCBZ"
+  attribute \enum_value_0011101 "OP_DIV"
+  attribute \enum_value_0011110 "OP_DIVE"
+  attribute \enum_value_0011111 "OP_EXTS"
+  attribute \enum_value_0100000 "OP_EXTSWSLI"
+  attribute \enum_value_0100001 "OP_ICBI"
+  attribute \enum_value_0100010 "OP_ICBT"
+  attribute \enum_value_0100011 "OP_ISEL"
+  attribute \enum_value_0100100 "OP_ISYNC"
+  attribute \enum_value_0100101 "OP_LOAD"
+  attribute \enum_value_0100110 "OP_STORE"
+  attribute \enum_value_0100111 "OP_MADDHD"
+  attribute \enum_value_0101000 "OP_MADDHDU"
+  attribute \enum_value_0101001 "OP_MADDLD"
+  attribute \enum_value_0101010 "OP_MCRF"
+  attribute \enum_value_0101011 "OP_MCRXR"
+  attribute \enum_value_0101100 "OP_MCRXRX"
+  attribute \enum_value_0101101 "OP_MFCR"
+  attribute \enum_value_0101110 "OP_MFSPR"
+  attribute \enum_value_0101111 "OP_MOD"
+  attribute \enum_value_0110000 "OP_MTCRF"
+  attribute \enum_value_0110001 "OP_MTSPR"
+  attribute \enum_value_0110010 "OP_MUL_L64"
+  attribute \enum_value_0110011 "OP_MUL_H64"
+  attribute \enum_value_0110100 "OP_MUL_H32"
+  attribute \enum_value_0110101 "OP_OR"
+  attribute \enum_value_0110110 "OP_POPCNT"
+  attribute \enum_value_0110111 "OP_PRTY"
+  attribute \enum_value_0111000 "OP_RLC"
+  attribute \enum_value_0111001 "OP_RLCL"
+  attribute \enum_value_0111010 "OP_RLCR"
+  attribute \enum_value_0111011 "OP_SETB"
+  attribute \enum_value_0111100 "OP_SHL"
+  attribute \enum_value_0111101 "OP_SHR"
+  attribute \enum_value_0111110 "OP_SYNC"
+  attribute \enum_value_0111111 "OP_TRAP"
+  attribute \enum_value_1000011 "OP_XOR"
+  attribute \enum_value_1000100 "OP_SIM_CONFIG"
+  attribute \enum_value_1000101 "OP_CROP"
+  attribute \enum_value_1000110 "OP_RFID"
+  attribute \enum_value_1000111 "OP_MFMSR"
+  attribute \enum_value_1001000 "OP_MTMSRD"
+  attribute \enum_value_1001001 "OP_SC"
+  attribute \enum_value_1001010 "OP_MTMSR"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 input 45 \oper_i_alu_trap0__insn_type
+  attribute \enum_base_type "Function"
+  attribute \enum_value_00000000000 "NONE"
+  attribute \enum_value_00000000010 "ALU"
+  attribute \enum_value_00000000100 "LDST"
+  attribute \enum_value_00000001000 "SHIFT_ROT"
+  attribute \enum_value_00000010000 "LOGICAL"
+  attribute \enum_value_00000100000 "BRANCH"
+  attribute \enum_value_00001000000 "CR"
+  attribute \enum_value_00010000000 "TRAP"
+  attribute \enum_value_00100000000 "MUL"
+  attribute \enum_value_01000000000 "DIV"
+  attribute \enum_value_10000000000 "SPR"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 input 46 \oper_i_alu_trap0__fn_unit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 input 47 \oper_i_alu_trap0__insn
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 input 48 \oper_i_alu_trap0__msr
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 input 49 \oper_i_alu_trap0__cia
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 50 \oper_i_alu_trap0__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 5 input 51 \oper_i_alu_trap0__traptype
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 13 input 52 \oper_i_alu_trap0__trapaddr
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
+  wire width 1 input 53 \cu_issue_i$7
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:106"
+  wire width 1 output 54 \cu_busy_o$8
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
+  wire width 4 input 55 \cu_rdmaskn_i$9
+  attribute \enum_base_type "MicrOp"
+  attribute \enum_value_0000000 "OP_ILLEGAL"
+  attribute \enum_value_0000001 "OP_NOP"
+  attribute \enum_value_0000010 "OP_ADD"
+  attribute \enum_value_0000011 "OP_ADDPCIS"
+  attribute \enum_value_0000100 "OP_AND"
+  attribute \enum_value_0000101 "OP_ATTN"
+  attribute \enum_value_0000110 "OP_B"
+  attribute \enum_value_0000111 "OP_BC"
+  attribute \enum_value_0001000 "OP_BCREG"
+  attribute \enum_value_0001001 "OP_BPERM"
+  attribute \enum_value_0001010 "OP_CMP"
+  attribute \enum_value_0001011 "OP_CMPB"
+  attribute \enum_value_0001100 "OP_CMPEQB"
+  attribute \enum_value_0001101 "OP_CMPRB"
+  attribute \enum_value_0001110 "OP_CNTZ"
+  attribute \enum_value_0001111 "OP_CRAND"
+  attribute \enum_value_0010000 "OP_CRANDC"
+  attribute \enum_value_0010001 "OP_CREQV"
+  attribute \enum_value_0010010 "OP_CRNAND"
+  attribute \enum_value_0010011 "OP_CRNOR"
+  attribute \enum_value_0010100 "OP_CROR"
+  attribute \enum_value_0010101 "OP_CRORC"
+  attribute \enum_value_0010110 "OP_CRXOR"
+  attribute \enum_value_0010111 "OP_DARN"
+  attribute \enum_value_0011000 "OP_DCBF"
+  attribute \enum_value_0011001 "OP_DCBST"
+  attribute \enum_value_0011010 "OP_DCBT"
+  attribute \enum_value_0011011 "OP_DCBTST"
+  attribute \enum_value_0011100 "OP_DCBZ"
+  attribute \enum_value_0011101 "OP_DIV"
+  attribute \enum_value_0011110 "OP_DIVE"
+  attribute \enum_value_0011111 "OP_EXTS"
+  attribute \enum_value_0100000 "OP_EXTSWSLI"
+  attribute \enum_value_0100001 "OP_ICBI"
+  attribute \enum_value_0100010 "OP_ICBT"
+  attribute \enum_value_0100011 "OP_ISEL"
+  attribute \enum_value_0100100 "OP_ISYNC"
+  attribute \enum_value_0100101 "OP_LOAD"
+  attribute \enum_value_0100110 "OP_STORE"
+  attribute \enum_value_0100111 "OP_MADDHD"
+  attribute \enum_value_0101000 "OP_MADDHDU"
+  attribute \enum_value_0101001 "OP_MADDLD"
+  attribute \enum_value_0101010 "OP_MCRF"
+  attribute \enum_value_0101011 "OP_MCRXR"
+  attribute \enum_value_0101100 "OP_MCRXRX"
+  attribute \enum_value_0101101 "OP_MFCR"
+  attribute \enum_value_0101110 "OP_MFSPR"
+  attribute \enum_value_0101111 "OP_MOD"
+  attribute \enum_value_0110000 "OP_MTCRF"
+  attribute \enum_value_0110001 "OP_MTSPR"
+  attribute \enum_value_0110010 "OP_MUL_L64"
+  attribute \enum_value_0110011 "OP_MUL_H64"
+  attribute \enum_value_0110100 "OP_MUL_H32"
+  attribute \enum_value_0110101 "OP_OR"
+  attribute \enum_value_0110110 "OP_POPCNT"
+  attribute \enum_value_0110111 "OP_PRTY"
+  attribute \enum_value_0111000 "OP_RLC"
+  attribute \enum_value_0111001 "OP_RLCL"
+  attribute \enum_value_0111010 "OP_RLCR"
+  attribute \enum_value_0111011 "OP_SETB"
+  attribute \enum_value_0111100 "OP_SHL"
+  attribute \enum_value_0111101 "OP_SHR"
+  attribute \enum_value_0111110 "OP_SYNC"
+  attribute \enum_value_0111111 "OP_TRAP"
+  attribute \enum_value_1000011 "OP_XOR"
+  attribute \enum_value_1000100 "OP_SIM_CONFIG"
+  attribute \enum_value_1000101 "OP_CROP"
+  attribute \enum_value_1000110 "OP_RFID"
+  attribute \enum_value_1000111 "OP_MFMSR"
+  attribute \enum_value_1001000 "OP_MTMSRD"
+  attribute \enum_value_1001001 "OP_SC"
+  attribute \enum_value_1001010 "OP_MTMSR"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 input 56 \oper_i_alu_logical0__insn_type
+  attribute \enum_base_type "Function"
+  attribute \enum_value_00000000000 "NONE"
+  attribute \enum_value_00000000010 "ALU"
+  attribute \enum_value_00000000100 "LDST"
+  attribute \enum_value_00000001000 "SHIFT_ROT"
+  attribute \enum_value_00000010000 "LOGICAL"
+  attribute \enum_value_00000100000 "BRANCH"
+  attribute \enum_value_00001000000 "CR"
+  attribute \enum_value_00010000000 "TRAP"
+  attribute \enum_value_00100000000 "MUL"
+  attribute \enum_value_01000000000 "DIV"
+  attribute \enum_value_10000000000 "SPR"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 input 57 \oper_i_alu_logical0__fn_unit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 input 58 \oper_i_alu_logical0__imm_data__imm
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 59 \oper_i_alu_logical0__imm_data__imm_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 60 \oper_i_alu_logical0__rc__rc
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 61 \oper_i_alu_logical0__rc__rc_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 62 \oper_i_alu_logical0__oe__oe
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 63 \oper_i_alu_logical0__oe__oe_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 64 \oper_i_alu_logical0__invert_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 65 \oper_i_alu_logical0__zero_a
+  attribute \enum_base_type "CryIn"
+  attribute \enum_value_00 "ZERO"
+  attribute \enum_value_01 "ONE"
+  attribute \enum_value_10 "CA"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 2 input 66 \oper_i_alu_logical0__input_carry
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 67 \oper_i_alu_logical0__invert_out
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 68 \oper_i_alu_logical0__write_cr0
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 69 \oper_i_alu_logical0__output_carry
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 70 \oper_i_alu_logical0__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 71 \oper_i_alu_logical0__is_signed
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 4 input 72 \oper_i_alu_logical0__data_len
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 input 73 \oper_i_alu_logical0__insn
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
+  wire width 1 input 74 \cu_issue_i$10
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:106"
+  wire width 1 output 75 \cu_busy_o$11
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
+  wire width 2 input 76 \cu_rdmaskn_i$12
+  attribute \enum_base_type "MicrOp"
+  attribute \enum_value_0000000 "OP_ILLEGAL"
+  attribute \enum_value_0000001 "OP_NOP"
+  attribute \enum_value_0000010 "OP_ADD"
+  attribute \enum_value_0000011 "OP_ADDPCIS"
+  attribute \enum_value_0000100 "OP_AND"
+  attribute \enum_value_0000101 "OP_ATTN"
+  attribute \enum_value_0000110 "OP_B"
+  attribute \enum_value_0000111 "OP_BC"
+  attribute \enum_value_0001000 "OP_BCREG"
+  attribute \enum_value_0001001 "OP_BPERM"
+  attribute \enum_value_0001010 "OP_CMP"
+  attribute \enum_value_0001011 "OP_CMPB"
+  attribute \enum_value_0001100 "OP_CMPEQB"
+  attribute \enum_value_0001101 "OP_CMPRB"
+  attribute \enum_value_0001110 "OP_CNTZ"
+  attribute \enum_value_0001111 "OP_CRAND"
+  attribute \enum_value_0010000 "OP_CRANDC"
+  attribute \enum_value_0010001 "OP_CREQV"
+  attribute \enum_value_0010010 "OP_CRNAND"
+  attribute \enum_value_0010011 "OP_CRNOR"
+  attribute \enum_value_0010100 "OP_CROR"
+  attribute \enum_value_0010101 "OP_CRORC"
+  attribute \enum_value_0010110 "OP_CRXOR"
+  attribute \enum_value_0010111 "OP_DARN"
+  attribute \enum_value_0011000 "OP_DCBF"
+  attribute \enum_value_0011001 "OP_DCBST"
+  attribute \enum_value_0011010 "OP_DCBT"
+  attribute \enum_value_0011011 "OP_DCBTST"
+  attribute \enum_value_0011100 "OP_DCBZ"
+  attribute \enum_value_0011101 "OP_DIV"
+  attribute \enum_value_0011110 "OP_DIVE"
+  attribute \enum_value_0011111 "OP_EXTS"
+  attribute \enum_value_0100000 "OP_EXTSWSLI"
+  attribute \enum_value_0100001 "OP_ICBI"
+  attribute \enum_value_0100010 "OP_ICBT"
+  attribute \enum_value_0100011 "OP_ISEL"
+  attribute \enum_value_0100100 "OP_ISYNC"
+  attribute \enum_value_0100101 "OP_LOAD"
+  attribute \enum_value_0100110 "OP_STORE"
+  attribute \enum_value_0100111 "OP_MADDHD"
+  attribute \enum_value_0101000 "OP_MADDHDU"
+  attribute \enum_value_0101001 "OP_MADDLD"
+  attribute \enum_value_0101010 "OP_MCRF"
+  attribute \enum_value_0101011 "OP_MCRXR"
+  attribute \enum_value_0101100 "OP_MCRXRX"
+  attribute \enum_value_0101101 "OP_MFCR"
+  attribute \enum_value_0101110 "OP_MFSPR"
+  attribute \enum_value_0101111 "OP_MOD"
+  attribute \enum_value_0110000 "OP_MTCRF"
+  attribute \enum_value_0110001 "OP_MTSPR"
+  attribute \enum_value_0110010 "OP_MUL_L64"
+  attribute \enum_value_0110011 "OP_MUL_H64"
+  attribute \enum_value_0110100 "OP_MUL_H32"
+  attribute \enum_value_0110101 "OP_OR"
+  attribute \enum_value_0110110 "OP_POPCNT"
+  attribute \enum_value_0110111 "OP_PRTY"
+  attribute \enum_value_0111000 "OP_RLC"
+  attribute \enum_value_0111001 "OP_RLCL"
+  attribute \enum_value_0111010 "OP_RLCR"
+  attribute \enum_value_0111011 "OP_SETB"
+  attribute \enum_value_0111100 "OP_SHL"
+  attribute \enum_value_0111101 "OP_SHR"
+  attribute \enum_value_0111110 "OP_SYNC"
+  attribute \enum_value_0111111 "OP_TRAP"
+  attribute \enum_value_1000011 "OP_XOR"
+  attribute \enum_value_1000100 "OP_SIM_CONFIG"
+  attribute \enum_value_1000101 "OP_CROP"
+  attribute \enum_value_1000110 "OP_RFID"
+  attribute \enum_value_1000111 "OP_MFMSR"
+  attribute \enum_value_1001000 "OP_MTMSRD"
+  attribute \enum_value_1001001 "OP_SC"
+  attribute \enum_value_1001010 "OP_MTMSR"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 input 77 \oper_i_alu_spr0__insn_type
+  attribute \enum_base_type "Function"
+  attribute \enum_value_00000000000 "NONE"
+  attribute \enum_value_00000000010 "ALU"
+  attribute \enum_value_00000000100 "LDST"
+  attribute \enum_value_00000001000 "SHIFT_ROT"
+  attribute \enum_value_00000010000 "LOGICAL"
+  attribute \enum_value_00000100000 "BRANCH"
+  attribute \enum_value_00001000000 "CR"
+  attribute \enum_value_00010000000 "TRAP"
+  attribute \enum_value_00100000000 "MUL"
+  attribute \enum_value_01000000000 "DIV"
+  attribute \enum_value_10000000000 "SPR"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 input 78 \oper_i_alu_spr0__fn_unit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 input 79 \oper_i_alu_spr0__insn
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 80 \oper_i_alu_spr0__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
+  wire width 1 input 81 \cu_issue_i$13
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:106"
+  wire width 1 output 82 \cu_busy_o$14
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
+  wire width 6 input 83 \cu_rdmaskn_i$15
+  attribute \enum_base_type "MicrOp"
+  attribute \enum_value_0000000 "OP_ILLEGAL"
+  attribute \enum_value_0000001 "OP_NOP"
+  attribute \enum_value_0000010 "OP_ADD"
+  attribute \enum_value_0000011 "OP_ADDPCIS"
+  attribute \enum_value_0000100 "OP_AND"
+  attribute \enum_value_0000101 "OP_ATTN"
+  attribute \enum_value_0000110 "OP_B"
+  attribute \enum_value_0000111 "OP_BC"
+  attribute \enum_value_0001000 "OP_BCREG"
+  attribute \enum_value_0001001 "OP_BPERM"
+  attribute \enum_value_0001010 "OP_CMP"
+  attribute \enum_value_0001011 "OP_CMPB"
+  attribute \enum_value_0001100 "OP_CMPEQB"
+  attribute \enum_value_0001101 "OP_CMPRB"
+  attribute \enum_value_0001110 "OP_CNTZ"
+  attribute \enum_value_0001111 "OP_CRAND"
+  attribute \enum_value_0010000 "OP_CRANDC"
+  attribute \enum_value_0010001 "OP_CREQV"
+  attribute \enum_value_0010010 "OP_CRNAND"
+  attribute \enum_value_0010011 "OP_CRNOR"
+  attribute \enum_value_0010100 "OP_CROR"
+  attribute \enum_value_0010101 "OP_CRORC"
+  attribute \enum_value_0010110 "OP_CRXOR"
+  attribute \enum_value_0010111 "OP_DARN"
+  attribute \enum_value_0011000 "OP_DCBF"
+  attribute \enum_value_0011001 "OP_DCBST"
+  attribute \enum_value_0011010 "OP_DCBT"
+  attribute \enum_value_0011011 "OP_DCBTST"
+  attribute \enum_value_0011100 "OP_DCBZ"
+  attribute \enum_value_0011101 "OP_DIV"
+  attribute \enum_value_0011110 "OP_DIVE"
+  attribute \enum_value_0011111 "OP_EXTS"
+  attribute \enum_value_0100000 "OP_EXTSWSLI"
+  attribute \enum_value_0100001 "OP_ICBI"
+  attribute \enum_value_0100010 "OP_ICBT"
+  attribute \enum_value_0100011 "OP_ISEL"
+  attribute \enum_value_0100100 "OP_ISYNC"
+  attribute \enum_value_0100101 "OP_LOAD"
+  attribute \enum_value_0100110 "OP_STORE"
+  attribute \enum_value_0100111 "OP_MADDHD"
+  attribute \enum_value_0101000 "OP_MADDHDU"
+  attribute \enum_value_0101001 "OP_MADDLD"
+  attribute \enum_value_0101010 "OP_MCRF"
+  attribute \enum_value_0101011 "OP_MCRXR"
+  attribute \enum_value_0101100 "OP_MCRXRX"
+  attribute \enum_value_0101101 "OP_MFCR"
+  attribute \enum_value_0101110 "OP_MFSPR"
+  attribute \enum_value_0101111 "OP_MOD"
+  attribute \enum_value_0110000 "OP_MTCRF"
+  attribute \enum_value_0110001 "OP_MTSPR"
+  attribute \enum_value_0110010 "OP_MUL_L64"
+  attribute \enum_value_0110011 "OP_MUL_H64"
+  attribute \enum_value_0110100 "OP_MUL_H32"
+  attribute \enum_value_0110101 "OP_OR"
+  attribute \enum_value_0110110 "OP_POPCNT"
+  attribute \enum_value_0110111 "OP_PRTY"
+  attribute \enum_value_0111000 "OP_RLC"
+  attribute \enum_value_0111001 "OP_RLCL"
+  attribute \enum_value_0111010 "OP_RLCR"
+  attribute \enum_value_0111011 "OP_SETB"
+  attribute \enum_value_0111100 "OP_SHL"
+  attribute \enum_value_0111101 "OP_SHR"
+  attribute \enum_value_0111110 "OP_SYNC"
+  attribute \enum_value_0111111 "OP_TRAP"
+  attribute \enum_value_1000011 "OP_XOR"
+  attribute \enum_value_1000100 "OP_SIM_CONFIG"
+  attribute \enum_value_1000101 "OP_CROP"
+  attribute \enum_value_1000110 "OP_RFID"
+  attribute \enum_value_1000111 "OP_MFMSR"
+  attribute \enum_value_1001000 "OP_MTMSRD"
+  attribute \enum_value_1001001 "OP_SC"
+  attribute \enum_value_1001010 "OP_MTMSR"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 input 84 \oper_i_alu_div0__insn_type
+  attribute \enum_base_type "Function"
+  attribute \enum_value_00000000000 "NONE"
+  attribute \enum_value_00000000010 "ALU"
+  attribute \enum_value_00000000100 "LDST"
+  attribute \enum_value_00000001000 "SHIFT_ROT"
+  attribute \enum_value_00000010000 "LOGICAL"
+  attribute \enum_value_00000100000 "BRANCH"
+  attribute \enum_value_00001000000 "CR"
+  attribute \enum_value_00010000000 "TRAP"
+  attribute \enum_value_00100000000 "MUL"
+  attribute \enum_value_01000000000 "DIV"
+  attribute \enum_value_10000000000 "SPR"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 input 85 \oper_i_alu_div0__fn_unit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 input 86 \oper_i_alu_div0__imm_data__imm
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 87 \oper_i_alu_div0__imm_data__imm_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 88 \oper_i_alu_div0__rc__rc
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 89 \oper_i_alu_div0__rc__rc_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 90 \oper_i_alu_div0__oe__oe
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 91 \oper_i_alu_div0__oe__oe_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 92 \oper_i_alu_div0__invert_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 93 \oper_i_alu_div0__zero_a
+  attribute \enum_base_type "CryIn"
+  attribute \enum_value_00 "ZERO"
+  attribute \enum_value_01 "ONE"
+  attribute \enum_value_10 "CA"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 2 input 94 \oper_i_alu_div0__input_carry
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 95 \oper_i_alu_div0__invert_out
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 96 \oper_i_alu_div0__write_cr0
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 97 \oper_i_alu_div0__output_carry
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 98 \oper_i_alu_div0__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 99 \oper_i_alu_div0__is_signed
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 4 input 100 \oper_i_alu_div0__data_len
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 input 101 \oper_i_alu_div0__insn
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
+  wire width 1 input 102 \cu_issue_i$16
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:106"
+  wire width 1 output 103 \cu_busy_o$17
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
+  wire width 3 input 104 \cu_rdmaskn_i$18
+  attribute \enum_base_type "MicrOp"
+  attribute \enum_value_0000000 "OP_ILLEGAL"
+  attribute \enum_value_0000001 "OP_NOP"
+  attribute \enum_value_0000010 "OP_ADD"
+  attribute \enum_value_0000011 "OP_ADDPCIS"
+  attribute \enum_value_0000100 "OP_AND"
+  attribute \enum_value_0000101 "OP_ATTN"
+  attribute \enum_value_0000110 "OP_B"
+  attribute \enum_value_0000111 "OP_BC"
+  attribute \enum_value_0001000 "OP_BCREG"
+  attribute \enum_value_0001001 "OP_BPERM"
+  attribute \enum_value_0001010 "OP_CMP"
+  attribute \enum_value_0001011 "OP_CMPB"
+  attribute \enum_value_0001100 "OP_CMPEQB"
+  attribute \enum_value_0001101 "OP_CMPRB"
+  attribute \enum_value_0001110 "OP_CNTZ"
+  attribute \enum_value_0001111 "OP_CRAND"
+  attribute \enum_value_0010000 "OP_CRANDC"
+  attribute \enum_value_0010001 "OP_CREQV"
+  attribute \enum_value_0010010 "OP_CRNAND"
+  attribute \enum_value_0010011 "OP_CRNOR"
+  attribute \enum_value_0010100 "OP_CROR"
+  attribute \enum_value_0010101 "OP_CRORC"
+  attribute \enum_value_0010110 "OP_CRXOR"
+  attribute \enum_value_0010111 "OP_DARN"
+  attribute \enum_value_0011000 "OP_DCBF"
+  attribute \enum_value_0011001 "OP_DCBST"
+  attribute \enum_value_0011010 "OP_DCBT"
+  attribute \enum_value_0011011 "OP_DCBTST"
+  attribute \enum_value_0011100 "OP_DCBZ"
+  attribute \enum_value_0011101 "OP_DIV"
+  attribute \enum_value_0011110 "OP_DIVE"
+  attribute \enum_value_0011111 "OP_EXTS"
+  attribute \enum_value_0100000 "OP_EXTSWSLI"
+  attribute \enum_value_0100001 "OP_ICBI"
+  attribute \enum_value_0100010 "OP_ICBT"
+  attribute \enum_value_0100011 "OP_ISEL"
+  attribute \enum_value_0100100 "OP_ISYNC"
+  attribute \enum_value_0100101 "OP_LOAD"
+  attribute \enum_value_0100110 "OP_STORE"
+  attribute \enum_value_0100111 "OP_MADDHD"
+  attribute \enum_value_0101000 "OP_MADDHDU"
+  attribute \enum_value_0101001 "OP_MADDLD"
+  attribute \enum_value_0101010 "OP_MCRF"
+  attribute \enum_value_0101011 "OP_MCRXR"
+  attribute \enum_value_0101100 "OP_MCRXRX"
+  attribute \enum_value_0101101 "OP_MFCR"
+  attribute \enum_value_0101110 "OP_MFSPR"
+  attribute \enum_value_0101111 "OP_MOD"
+  attribute \enum_value_0110000 "OP_MTCRF"
+  attribute \enum_value_0110001 "OP_MTSPR"
+  attribute \enum_value_0110010 "OP_MUL_L64"
+  attribute \enum_value_0110011 "OP_MUL_H64"
+  attribute \enum_value_0110100 "OP_MUL_H32"
+  attribute \enum_value_0110101 "OP_OR"
+  attribute \enum_value_0110110 "OP_POPCNT"
+  attribute \enum_value_0110111 "OP_PRTY"
+  attribute \enum_value_0111000 "OP_RLC"
+  attribute \enum_value_0111001 "OP_RLCL"
+  attribute \enum_value_0111010 "OP_RLCR"
+  attribute \enum_value_0111011 "OP_SETB"
+  attribute \enum_value_0111100 "OP_SHL"
+  attribute \enum_value_0111101 "OP_SHR"
+  attribute \enum_value_0111110 "OP_SYNC"
+  attribute \enum_value_0111111 "OP_TRAP"
+  attribute \enum_value_1000011 "OP_XOR"
+  attribute \enum_value_1000100 "OP_SIM_CONFIG"
+  attribute \enum_value_1000101 "OP_CROP"
+  attribute \enum_value_1000110 "OP_RFID"
+  attribute \enum_value_1000111 "OP_MFMSR"
+  attribute \enum_value_1001000 "OP_MTMSRD"
+  attribute \enum_value_1001001 "OP_SC"
+  attribute \enum_value_1001010 "OP_MTMSR"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 input 105 \oper_i_alu_mul0__insn_type
+  attribute \enum_base_type "Function"
+  attribute \enum_value_00000000000 "NONE"
+  attribute \enum_value_00000000010 "ALU"
+  attribute \enum_value_00000000100 "LDST"
+  attribute \enum_value_00000001000 "SHIFT_ROT"
+  attribute \enum_value_00000010000 "LOGICAL"
+  attribute \enum_value_00000100000 "BRANCH"
+  attribute \enum_value_00001000000 "CR"
+  attribute \enum_value_00010000000 "TRAP"
+  attribute \enum_value_00100000000 "MUL"
+  attribute \enum_value_01000000000 "DIV"
+  attribute \enum_value_10000000000 "SPR"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 input 106 \oper_i_alu_mul0__fn_unit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 input 107 \oper_i_alu_mul0__imm_data__imm
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 108 \oper_i_alu_mul0__imm_data__imm_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 109 \oper_i_alu_mul0__rc__rc
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 110 \oper_i_alu_mul0__rc__rc_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 111 \oper_i_alu_mul0__oe__oe
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 112 \oper_i_alu_mul0__oe__oe_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 113 \oper_i_alu_mul0__invert_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 114 \oper_i_alu_mul0__zero_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 115 \oper_i_alu_mul0__invert_out
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 116 \oper_i_alu_mul0__write_cr0
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 117 \oper_i_alu_mul0__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 118 \oper_i_alu_mul0__is_signed
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 input 119 \oper_i_alu_mul0__insn
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
+  wire width 1 input 120 \cu_issue_i$19
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:106"
+  wire width 1 output 121 \cu_busy_o$20
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
+  wire width 3 input 122 \cu_rdmaskn_i$21
+  attribute \enum_base_type "MicrOp"
+  attribute \enum_value_0000000 "OP_ILLEGAL"
+  attribute \enum_value_0000001 "OP_NOP"
+  attribute \enum_value_0000010 "OP_ADD"
+  attribute \enum_value_0000011 "OP_ADDPCIS"
+  attribute \enum_value_0000100 "OP_AND"
+  attribute \enum_value_0000101 "OP_ATTN"
+  attribute \enum_value_0000110 "OP_B"
+  attribute \enum_value_0000111 "OP_BC"
+  attribute \enum_value_0001000 "OP_BCREG"
+  attribute \enum_value_0001001 "OP_BPERM"
+  attribute \enum_value_0001010 "OP_CMP"
+  attribute \enum_value_0001011 "OP_CMPB"
+  attribute \enum_value_0001100 "OP_CMPEQB"
+  attribute \enum_value_0001101 "OP_CMPRB"
+  attribute \enum_value_0001110 "OP_CNTZ"
+  attribute \enum_value_0001111 "OP_CRAND"
+  attribute \enum_value_0010000 "OP_CRANDC"
+  attribute \enum_value_0010001 "OP_CREQV"
+  attribute \enum_value_0010010 "OP_CRNAND"
+  attribute \enum_value_0010011 "OP_CRNOR"
+  attribute \enum_value_0010100 "OP_CROR"
+  attribute \enum_value_0010101 "OP_CRORC"
+  attribute \enum_value_0010110 "OP_CRXOR"
+  attribute \enum_value_0010111 "OP_DARN"
+  attribute \enum_value_0011000 "OP_DCBF"
+  attribute \enum_value_0011001 "OP_DCBST"
+  attribute \enum_value_0011010 "OP_DCBT"
+  attribute \enum_value_0011011 "OP_DCBTST"
+  attribute \enum_value_0011100 "OP_DCBZ"
+  attribute \enum_value_0011101 "OP_DIV"
+  attribute \enum_value_0011110 "OP_DIVE"
+  attribute \enum_value_0011111 "OP_EXTS"
+  attribute \enum_value_0100000 "OP_EXTSWSLI"
+  attribute \enum_value_0100001 "OP_ICBI"
+  attribute \enum_value_0100010 "OP_ICBT"
+  attribute \enum_value_0100011 "OP_ISEL"
+  attribute \enum_value_0100100 "OP_ISYNC"
+  attribute \enum_value_0100101 "OP_LOAD"
+  attribute \enum_value_0100110 "OP_STORE"
+  attribute \enum_value_0100111 "OP_MADDHD"
+  attribute \enum_value_0101000 "OP_MADDHDU"
+  attribute \enum_value_0101001 "OP_MADDLD"
+  attribute \enum_value_0101010 "OP_MCRF"
+  attribute \enum_value_0101011 "OP_MCRXR"
+  attribute \enum_value_0101100 "OP_MCRXRX"
+  attribute \enum_value_0101101 "OP_MFCR"
+  attribute \enum_value_0101110 "OP_MFSPR"
+  attribute \enum_value_0101111 "OP_MOD"
+  attribute \enum_value_0110000 "OP_MTCRF"
+  attribute \enum_value_0110001 "OP_MTSPR"
+  attribute \enum_value_0110010 "OP_MUL_L64"
+  attribute \enum_value_0110011 "OP_MUL_H64"
+  attribute \enum_value_0110100 "OP_MUL_H32"
+  attribute \enum_value_0110101 "OP_OR"
+  attribute \enum_value_0110110 "OP_POPCNT"
+  attribute \enum_value_0110111 "OP_PRTY"
+  attribute \enum_value_0111000 "OP_RLC"
+  attribute \enum_value_0111001 "OP_RLCL"
+  attribute \enum_value_0111010 "OP_RLCR"
+  attribute \enum_value_0111011 "OP_SETB"
+  attribute \enum_value_0111100 "OP_SHL"
+  attribute \enum_value_0111101 "OP_SHR"
+  attribute \enum_value_0111110 "OP_SYNC"
+  attribute \enum_value_0111111 "OP_TRAP"
+  attribute \enum_value_1000011 "OP_XOR"
+  attribute \enum_value_1000100 "OP_SIM_CONFIG"
+  attribute \enum_value_1000101 "OP_CROP"
+  attribute \enum_value_1000110 "OP_RFID"
+  attribute \enum_value_1000111 "OP_MFMSR"
+  attribute \enum_value_1001000 "OP_MTMSRD"
+  attribute \enum_value_1001001 "OP_SC"
+  attribute \enum_value_1001010 "OP_MTMSR"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 input 123 \oper_i_alu_shift_rot0__insn_type
+  attribute \enum_base_type "Function"
+  attribute \enum_value_00000000000 "NONE"
+  attribute \enum_value_00000000010 "ALU"
+  attribute \enum_value_00000000100 "LDST"
+  attribute \enum_value_00000001000 "SHIFT_ROT"
+  attribute \enum_value_00000010000 "LOGICAL"
+  attribute \enum_value_00000100000 "BRANCH"
+  attribute \enum_value_00001000000 "CR"
+  attribute \enum_value_00010000000 "TRAP"
+  attribute \enum_value_00100000000 "MUL"
+  attribute \enum_value_01000000000 "DIV"
+  attribute \enum_value_10000000000 "SPR"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 input 124 \oper_i_alu_shift_rot0__fn_unit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 input 125 \oper_i_alu_shift_rot0__imm_data__imm
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 126 \oper_i_alu_shift_rot0__imm_data__imm_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 127 \oper_i_alu_shift_rot0__rc__rc
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 128 \oper_i_alu_shift_rot0__rc__rc_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 129 \oper_i_alu_shift_rot0__oe__oe
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 130 \oper_i_alu_shift_rot0__oe__oe_ok
+  attribute \enum_base_type "CryIn"
+  attribute \enum_value_00 "ZERO"
+  attribute \enum_value_01 "ONE"
+  attribute \enum_value_10 "CA"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 2 input 132 \oper_i_alu_shift_rot0__input_carry
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 133 \oper_i_alu_shift_rot0__output_carry
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 134 \oper_i_alu_shift_rot0__input_cr
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 135 \oper_i_alu_shift_rot0__output_cr
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 136 \oper_i_alu_shift_rot0__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 137 \oper_i_alu_shift_rot0__is_signed
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 input 138 \oper_i_alu_shift_rot0__insn
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
+  wire width 1 input 139 \cu_issue_i$22
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:106"
+  wire width 1 output 140 \cu_busy_o$23
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
+  wire width 4 input 141 \cu_rdmaskn_i$24
+  attribute \enum_base_type "MicrOp"
+  attribute \enum_value_0000000 "OP_ILLEGAL"
+  attribute \enum_value_0000001 "OP_NOP"
+  attribute \enum_value_0000010 "OP_ADD"
+  attribute \enum_value_0000011 "OP_ADDPCIS"
+  attribute \enum_value_0000100 "OP_AND"
+  attribute \enum_value_0000101 "OP_ATTN"
+  attribute \enum_value_0000110 "OP_B"
+  attribute \enum_value_0000111 "OP_BC"
+  attribute \enum_value_0001000 "OP_BCREG"
+  attribute \enum_value_0001001 "OP_BPERM"
+  attribute \enum_value_0001010 "OP_CMP"
+  attribute \enum_value_0001011 "OP_CMPB"
+  attribute \enum_value_0001100 "OP_CMPEQB"
+  attribute \enum_value_0001101 "OP_CMPRB"
+  attribute \enum_value_0001110 "OP_CNTZ"
+  attribute \enum_value_0001111 "OP_CRAND"
+  attribute \enum_value_0010000 "OP_CRANDC"
+  attribute \enum_value_0010001 "OP_CREQV"
+  attribute \enum_value_0010010 "OP_CRNAND"
+  attribute \enum_value_0010011 "OP_CRNOR"
+  attribute \enum_value_0010100 "OP_CROR"
+  attribute \enum_value_0010101 "OP_CRORC"
+  attribute \enum_value_0010110 "OP_CRXOR"
+  attribute \enum_value_0010111 "OP_DARN"
+  attribute \enum_value_0011000 "OP_DCBF"
+  attribute \enum_value_0011001 "OP_DCBST"
+  attribute \enum_value_0011010 "OP_DCBT"
+  attribute \enum_value_0011011 "OP_DCBTST"
+  attribute \enum_value_0011100 "OP_DCBZ"
+  attribute \enum_value_0011101 "OP_DIV"
+  attribute \enum_value_0011110 "OP_DIVE"
+  attribute \enum_value_0011111 "OP_EXTS"
+  attribute \enum_value_0100000 "OP_EXTSWSLI"
+  attribute \enum_value_0100001 "OP_ICBI"
+  attribute \enum_value_0100010 "OP_ICBT"
+  attribute \enum_value_0100011 "OP_ISEL"
+  attribute \enum_value_0100100 "OP_ISYNC"
+  attribute \enum_value_0100101 "OP_LOAD"
+  attribute \enum_value_0100110 "OP_STORE"
+  attribute \enum_value_0100111 "OP_MADDHD"
+  attribute \enum_value_0101000 "OP_MADDHDU"
+  attribute \enum_value_0101001 "OP_MADDLD"
+  attribute \enum_value_0101010 "OP_MCRF"
+  attribute \enum_value_0101011 "OP_MCRXR"
+  attribute \enum_value_0101100 "OP_MCRXRX"
+  attribute \enum_value_0101101 "OP_MFCR"
+  attribute \enum_value_0101110 "OP_MFSPR"
+  attribute \enum_value_0101111 "OP_MOD"
+  attribute \enum_value_0110000 "OP_MTCRF"
+  attribute \enum_value_0110001 "OP_MTSPR"
+  attribute \enum_value_0110010 "OP_MUL_L64"
+  attribute \enum_value_0110011 "OP_MUL_H64"
+  attribute \enum_value_0110100 "OP_MUL_H32"
+  attribute \enum_value_0110101 "OP_OR"
+  attribute \enum_value_0110110 "OP_POPCNT"
+  attribute \enum_value_0110111 "OP_PRTY"
+  attribute \enum_value_0111000 "OP_RLC"
+  attribute \enum_value_0111001 "OP_RLCL"
+  attribute \enum_value_0111010 "OP_RLCR"
+  attribute \enum_value_0111011 "OP_SETB"
+  attribute \enum_value_0111100 "OP_SHL"
+  attribute \enum_value_0111101 "OP_SHR"
+  attribute \enum_value_0111110 "OP_SYNC"
+  attribute \enum_value_0111111 "OP_TRAP"
+  attribute \enum_value_1000011 "OP_XOR"
+  attribute \enum_value_1000100 "OP_SIM_CONFIG"
+  attribute \enum_value_1000101 "OP_CROP"
+  attribute \enum_value_1000110 "OP_RFID"
+  attribute \enum_value_1000111 "OP_MFMSR"
+  attribute \enum_value_1001000 "OP_MTMSRD"
+  attribute \enum_value_1001001 "OP_SC"
+  attribute \enum_value_1001010 "OP_MTMSR"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 input 142 \oper_i_ldst_ldst0__insn_type
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 64 input 143 \oper_i_ldst_ldst0__imm_data__imm
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 144 \oper_i_ldst_ldst0__imm_data__imm_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 145 \oper_i_ldst_ldst0__zero_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 146 \oper_i_ldst_ldst0__rc__rc
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 147 \oper_i_ldst_ldst0__rc__rc_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 148 \oper_i_ldst_ldst0__oe__oe
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 149 \oper_i_ldst_ldst0__oe__oe_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 150 \oper_i_ldst_ldst0__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 151 \oper_i_ldst_ldst0__is_signed
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 4 input 152 \oper_i_ldst_ldst0__data_len
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 153 \oper_i_ldst_ldst0__byte_reverse
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 input 154 \oper_i_ldst_ldst0__sign_extend
+  attribute \enum_base_type "LDSTMode"
+  attribute \enum_value_00 "NONE"
+  attribute \enum_value_01 "update"
+  attribute \enum_value_10 "cix"
+  attribute \enum_value_11 "cx"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 2 input 155 \oper_i_ldst_ldst0__ldst_mode
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
+  wire width 1 input 156 \cu_issue_i$25
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:106"
+  wire width 1 output 157 \cu_busy_o$26
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
+  wire width 3 input 158 \cu_rdmaskn_i$27
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+  wire width 4 output 159 \cu_rd__rel_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+  wire width 4 input 160 \cu_rd__go_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
+  wire width 64 input 161 \src1_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+  wire width 6 output 162 \cu_rd__rel_o$28
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+  wire width 6 input 163 \cu_rd__go_i$29
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
+  wire width 64 input 164 \src1_i$30
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+  wire width 4 output 165 \cu_rd__rel_o$31
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+  wire width 4 input 166 \cu_rd__go_i$32
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
+  wire width 64 input 167 \src1_i$33
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+  wire width 2 output 168 \cu_rd__rel_o$34
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+  wire width 2 input 169 \cu_rd__go_i$35
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
+  wire width 64 input 170 \src1_i$36
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+  wire width 6 output 171 \cu_rd__rel_o$37
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+  wire width 6 input 172 \cu_rd__go_i$38
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
+  wire width 64 input 173 \src1_i$39
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+  wire width 3 output 174 \cu_rd__rel_o$40
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+  wire width 3 input 175 \cu_rd__go_i$41
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
+  wire width 64 input 176 \src1_i$42
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+  wire width 3 output 177 \cu_rd__rel_o$43
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+  wire width 3 input 178 \cu_rd__go_i$44
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
+  wire width 64 input 179 \src1_i$45
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+  wire width 4 output 180 \cu_rd__rel_o$46
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+  wire width 4 input 181 \cu_rd__go_i$47
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
+  wire width 64 input 182 \src1_i$48
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+  wire width 3 output 183 \cu_rd__rel_o$49
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+  wire width 3 input 184 \cu_rd__go_i$50
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
+  wire width 64 input 185 \src1_i$51
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
+  wire width 64 input 186 \src2_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
+  wire width 64 input 187 \src2_i$52
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
+  wire width 64 input 188 \src2_i$53
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
+  wire width 64 input 189 \src2_i$54
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
+  wire width 64 input 190 \src2_i$55
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
+  wire width 64 input 191 \src2_i$56
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
+  wire width 64 input 192 \src2_i$57
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
+  wire width 64 input 193 \src2_i$58
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
+  wire width 64 input 194 \src3_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
+  wire width 64 input 195 \src3_i$59
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
+  wire width 1 input 196 \src3_i$60
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
+  wire width 1 input 197 \src4_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
+  wire width 1 input 198 \src3_i$61
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
+  wire width 1 input 199 \src3_i$62
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
+  wire width 2 input 200 \src4_i$63
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
+  wire width 2 input 201 \src6_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
+  wire width 2 input 202 \src4_i$64
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
+  wire width 2 input 203 \src5_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
+  wire width 32 input 204 \src3_i$65
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
+  wire width 4 input 205 \src4_i$66
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+  wire width 3 output 206 \cu_rd__rel_o$67
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+  wire width 3 input 207 \cu_rd__go_i$68
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
+  wire width 4 input 208 \src3_i$69
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
+  wire width 4 input 209 \src5_i$70
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
+  wire width 4 input 210 \src6_i$71
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
+  wire width 64 input 211 \src1_i$72
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
+  wire width 64 input 212 \src3_i$73
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
+  wire width 64 input 213 \src3_i$74
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
+  wire width 64 input 214 \src2_i$75
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
+  wire width 64 input 215 \src4_i$76
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
+  wire width 64 input 216 \src2_i$77
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 output 217 \o_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+  wire width 5 output 218 \cu_wr__rel_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+  wire width 5 input 219 \cu_wr__go_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 output 220 \o_ok$78
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+  wire width 3 output 221 \cu_wr__rel_o$79
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+  wire width 3 input 222 \cu_wr__go_i$80
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 output 223 \o_ok$81
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+  wire width 5 output 224 \cu_wr__rel_o$82
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+  wire width 5 input 225 \cu_wr__go_i$83
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 output 226 \o_ok$84
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+  wire width 3 output 227 \cu_wr__rel_o$85
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+  wire width 3 input 228 \cu_wr__go_i$86
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 output 229 \o_ok$87
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+  wire width 6 output 230 \cu_wr__rel_o$88
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+  wire width 6 input 231 \cu_wr__go_i$89
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 output 232 \o_ok$90
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+  wire width 4 output 233 \cu_wr__rel_o$91
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+  wire width 4 input 234 \cu_wr__go_i$92
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 output 235 \o_ok$93
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+  wire width 4 output 236 \cu_wr__rel_o$94
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+  wire width 4 input 237 \cu_wr__go_i$95
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 output 238 \o_ok$96
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+  wire width 3 output 239 \cu_wr__rel_o$97
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+  wire width 3 input 240 \cu_wr__go_i$98
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+  wire width 2 output 241 \cu_wr__rel_o$99
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+  wire width 2 input 242 \cu_wr__go_i$100
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
+  wire width 64 output 243 \dest1_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
+  wire width 64 output 244 \dest1_o$101
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
+  wire width 64 output 245 \dest1_o$102
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
+  wire width 64 output 246 \dest1_o$103
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
+  wire width 64 output 247 \dest1_o$104
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
+  wire width 64 output 248 \dest1_o$105
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
+  wire width 64 output 249 \dest1_o$106
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
+  wire width 64 output 250 \dest1_o$107
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 64 output 251 \o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 64 output 252 \ea
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 output 253 \full_cr_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
+  wire width 32 output 254 \dest2_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 output 255 \cr_a_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 output 256 \cr_a_ok$108
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 output 257 \cr_a_ok$109
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 output 258 \cr_a_ok$110
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 output 259 \cr_a_ok$111
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 output 260 \cr_a_ok$112
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
+  wire width 4 output 261 \dest2_o$113
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
+  wire width 4 output 262 \dest3_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
+  wire width 4 output 263 \dest2_o$114
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
+  wire width 4 output 264 \dest2_o$115
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
+  wire width 4 output 265 \dest2_o$116
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
+  wire width 4 output 266 \dest2_o$117
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 output 267 \xer_ca_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 output 268 \xer_ca_ok$118
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 output 269 \xer_ca_ok$119
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 output 270 \xer_ca_ok$120
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
+  wire width 2 output 271 \dest3_o$121
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
+  wire width 2 output 272 \dest3_o$122
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
+  wire width 2 output 273 \dest6_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
+  wire width 2 output 274 \dest3_o$123
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 output 275 \xer_ov_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 output 276 \xer_ov_ok$124
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 output 277 \xer_ov_ok$125
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 output 278 \xer_ov_ok$126
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
+  wire width 2 output 279 \dest4_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
+  wire width 2 output 280 \dest5_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
+  wire width 2 output 281 \dest3_o$127
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
+  wire width 2 output 282 \dest3_o$128
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 output 283 \xer_so_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 output 284 \xer_so_ok$129
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 output 285 \xer_so_ok$130
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 output 286 \xer_so_ok$131
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
+  wire width 1 output 287 \dest5_o$132
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
+  wire width 1 output 288 \dest4_o$133
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
+  wire width 1 output 289 \dest4_o$134
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
+  wire width 1 output 290 \dest4_o$135
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 output 291 \fast1_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+  wire width 3 output 292 \cu_wr__rel_o$136
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+  wire width 3 input 293 \cu_wr__go_i$137
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 output 294 \fast1_ok$138
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 output 295 \fast1_ok$139
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
+  wire width 64 output 296 \dest1_o$140
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
+  wire width 64 output 297 \dest2_o$141
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
+  wire width 64 output 298 \dest3_o$142
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 output 299 \fast2_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 output 300 \fast2_ok$143
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
+  wire width 64 output 301 \dest2_o$144
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
+  wire width 64 output 302 \dest3_o$145
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 output 303 \nia_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 output 304 \nia_ok$146
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
+  wire width 64 output 305 \dest3_o$147
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
+  wire width 64 output 306 \dest4_o$148
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 output 307 \msr_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
+  wire width 64 output 308 \dest5_o$149
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 output 309 \spr1_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
+  wire width 64 output 310 \dest2_o$150
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 311 \coresync_rst
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:95"
+  wire width 1 output 312 \ldst_port0_is_ld_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:96"
+  wire width 1 output 313 \ldst_port0_is_st_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99"
+  wire width 4 output 314 \ldst_port0_data_len
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 96 output 315 \ldst_port0_addr_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 output 316 \ldst_port0_addr_i_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:107"
+  wire width 1 input 317 \ldst_port0_addr_exc_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:106"
+  wire width 1 input 318 \ldst_port0_addr_ok_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 64 input 319 \ldst_port0_ld_data_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 input 320 \ldst_port0_ld_data_o_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 64 output 321 \ldst_port0_st_data_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 output 322 \ldst_port0_st_data_i_ok
+  cell \alu0 \alu0
+    connect \coresync_clk \coresync_clk
+    connect \oper_i_alu_alu0__insn_type \oper_i_alu_alu0__insn_type
+    connect \oper_i_alu_alu0__fn_unit \oper_i_alu_alu0__fn_unit
+    connect \oper_i_alu_alu0__imm_data__imm \oper_i_alu_alu0__imm_data__imm
+    connect \oper_i_alu_alu0__imm_data__imm_ok \oper_i_alu_alu0__imm_data__imm_ok
+    connect \oper_i_alu_alu0__rc__rc \oper_i_alu_alu0__rc__rc
+    connect \oper_i_alu_alu0__rc__rc_ok \oper_i_alu_alu0__rc__rc_ok
+    connect \oper_i_alu_alu0__oe__oe \oper_i_alu_alu0__oe__oe
+    connect \oper_i_alu_alu0__oe__oe_ok \oper_i_alu_alu0__oe__oe_ok
+    connect \oper_i_alu_alu0__invert_a \oper_i_alu_alu0__invert_a
+    connect \oper_i_alu_alu0__zero_a \oper_i_alu_alu0__zero_a
+    connect \oper_i_alu_alu0__invert_out \oper_i_alu_alu0__invert_out
+    connect \oper_i_alu_alu0__write_cr0 \oper_i_alu_alu0__write_cr0
+    connect \oper_i_alu_alu0__input_carry \oper_i_alu_alu0__input_carry
+    connect \oper_i_alu_alu0__output_carry \oper_i_alu_alu0__output_carry
+    connect \oper_i_alu_alu0__is_32bit \oper_i_alu_alu0__is_32bit
+    connect \oper_i_alu_alu0__is_signed \oper_i_alu_alu0__is_signed
+    connect \oper_i_alu_alu0__data_len \oper_i_alu_alu0__data_len
+    connect \oper_i_alu_alu0__insn \oper_i_alu_alu0__insn
+    connect \cu_issue_i \cu_issue_i
+    connect \cu_busy_o \cu_busy_o
+    connect \cu_rdmaskn_i \cu_rdmaskn_i
+    connect \cu_rd__rel_o \cu_rd__rel_o
+    connect \cu_rd__go_i \cu_rd__go_i
+    connect \src1_i \src1_i
+    connect \src2_i \src2_i
+    connect \src3_i \src3_i$60
+    connect \src4_i \src4_i$63
+    connect \o_ok \o_ok
+    connect \cu_wr__rel_o \cu_wr__rel_o
+    connect \cu_wr__go_i \cu_wr__go_i
+    connect \dest1_o \dest1_o
+    connect \cr_a_ok \cr_a_ok
+    connect \dest2_o \dest2_o$113
+    connect \xer_ca_ok \xer_ca_ok
+    connect \dest3_o \dest3_o$121
+    connect \xer_ov_ok \xer_ov_ok
+    connect \dest4_o \dest4_o
+    connect \xer_so_ok \xer_so_ok
+    connect \dest5_o \dest5_o$132
+    connect \coresync_rst \coresync_rst
+  end
+  cell \cr0 \cr0
+    connect \coresync_clk \coresync_clk
+    connect \oper_i_alu_cr0__insn_type \oper_i_alu_cr0__insn_type
+    connect \oper_i_alu_cr0__fn_unit \oper_i_alu_cr0__fn_unit
+    connect \oper_i_alu_cr0__insn \oper_i_alu_cr0__insn
+    connect \oper_i_alu_cr0__read_cr_whole \oper_i_alu_cr0__read_cr_whole
+    connect \oper_i_alu_cr0__write_cr_whole \oper_i_alu_cr0__write_cr_whole
+    connect \cu_issue_i \cu_issue_i$1
+    connect \cu_busy_o \cu_busy_o$2
+    connect \cu_rdmaskn_i \cu_rdmaskn_i$3
+    connect \cu_rd__rel_o \cu_rd__rel_o$28
+    connect \cu_rd__go_i \cu_rd__go_i$29
+    connect \src1_i \src1_i$30
+    connect \src2_i \src2_i$52
+    connect \src3_i \src3_i$65
+    connect \src4_i \src4_i$66
+    connect \src5_i \src5_i$70
+    connect \src6_i \src6_i$71
+    connect \o_ok \o_ok$78
+    connect \cu_wr__rel_o \cu_wr__rel_o$79
+    connect \cu_wr__go_i \cu_wr__go_i$80
+    connect \dest1_o \dest1_o$101
+    connect \full_cr_ok \full_cr_ok
+    connect \dest2_o \dest2_o
+    connect \cr_a_ok \cr_a_ok$108
+    connect \dest3_o \dest3_o
+    connect \coresync_rst \coresync_rst
+  end
+  cell \branch0 \branch0
+    connect \coresync_clk \coresync_clk
+    connect \oper_i_alu_branch0__cia \oper_i_alu_branch0__cia
+    connect \oper_i_alu_branch0__insn_type \oper_i_alu_branch0__insn_type
+    connect \oper_i_alu_branch0__fn_unit \oper_i_alu_branch0__fn_unit
+    connect \oper_i_alu_branch0__insn \oper_i_alu_branch0__insn
+    connect \oper_i_alu_branch0__imm_data__imm \oper_i_alu_branch0__imm_data__imm
+    connect \oper_i_alu_branch0__imm_data__imm_ok \oper_i_alu_branch0__imm_data__imm_ok
+    connect \oper_i_alu_branch0__lk \oper_i_alu_branch0__lk
+    connect \oper_i_alu_branch0__is_32bit \oper_i_alu_branch0__is_32bit
+    connect \cu_issue_i \cu_issue_i$4
+    connect \cu_busy_o \cu_busy_o$5
+    connect \cu_rdmaskn_i \cu_rdmaskn_i$6
+    connect \cu_rd__rel_o \cu_rd__rel_o$67
+    connect \cu_rd__go_i \cu_rd__go_i$68
+    connect \src3_i \src3_i$69
+    connect \src1_i \src1_i$72
+    connect \src2_i \src2_i$75
+    connect \fast1_ok \fast1_ok
+    connect \cu_wr__rel_o \cu_wr__rel_o$136
+    connect \cu_wr__go_i \cu_wr__go_i$137
+    connect \dest1_o \dest1_o$140
+    connect \fast2_ok \fast2_ok
+    connect \dest2_o \dest2_o$144
+    connect \nia_ok \nia_ok
+    connect \dest3_o \dest3_o$147
+    connect \coresync_rst \coresync_rst
+  end
+  cell \trap0 \trap0
+    connect \coresync_clk \coresync_clk
+    connect \oper_i_alu_trap0__insn_type \oper_i_alu_trap0__insn_type
+    connect \oper_i_alu_trap0__fn_unit \oper_i_alu_trap0__fn_unit
+    connect \oper_i_alu_trap0__insn \oper_i_alu_trap0__insn
+    connect \oper_i_alu_trap0__msr \oper_i_alu_trap0__msr
+    connect \oper_i_alu_trap0__cia \oper_i_alu_trap0__cia
+    connect \oper_i_alu_trap0__is_32bit \oper_i_alu_trap0__is_32bit
+    connect \oper_i_alu_trap0__traptype \oper_i_alu_trap0__traptype
+    connect \oper_i_alu_trap0__trapaddr \oper_i_alu_trap0__trapaddr
+    connect \cu_issue_i \cu_issue_i$7
+    connect \cu_busy_o \cu_busy_o$8
+    connect \cu_rdmaskn_i \cu_rdmaskn_i$9
+    connect \cu_rd__rel_o \cu_rd__rel_o$31
+    connect \cu_rd__go_i \cu_rd__go_i$32
+    connect \src1_i \src1_i$33
+    connect \src2_i \src2_i$53
+    connect \src3_i \src3_i$73
+    connect \src4_i \src4_i$76
+    connect \o_ok \o_ok$81
+    connect \cu_wr__rel_o \cu_wr__rel_o$82
+    connect \cu_wr__go_i \cu_wr__go_i$83
+    connect \dest1_o \dest1_o$102
+    connect \fast1_ok \fast1_ok$138
+    connect \dest2_o \dest2_o$141
+    connect \fast2_ok \fast2_ok$143
+    connect \dest3_o \dest3_o$145
+    connect \nia_ok \nia_ok$146
+    connect \dest4_o \dest4_o$148
+    connect \msr_ok \msr_ok
+    connect \dest5_o \dest5_o$149
+    connect \coresync_rst \coresync_rst
+  end
+  cell \logical0 \logical0
+    connect \coresync_clk \coresync_clk
+    connect \oper_i_alu_logical0__insn_type \oper_i_alu_logical0__insn_type
+    connect \oper_i_alu_logical0__fn_unit \oper_i_alu_logical0__fn_unit
+    connect \oper_i_alu_logical0__imm_data__imm \oper_i_alu_logical0__imm_data__imm
+    connect \oper_i_alu_logical0__imm_data__imm_ok \oper_i_alu_logical0__imm_data__imm_ok
+    connect \oper_i_alu_logical0__rc__rc \oper_i_alu_logical0__rc__rc
+    connect \oper_i_alu_logical0__rc__rc_ok \oper_i_alu_logical0__rc__rc_ok
+    connect \oper_i_alu_logical0__oe__oe \oper_i_alu_logical0__oe__oe
+    connect \oper_i_alu_logical0__oe__oe_ok \oper_i_alu_logical0__oe__oe_ok
+    connect \oper_i_alu_logical0__invert_a \oper_i_alu_logical0__invert_a
+    connect \oper_i_alu_logical0__zero_a \oper_i_alu_logical0__zero_a
+    connect \oper_i_alu_logical0__input_carry \oper_i_alu_logical0__input_carry
+    connect \oper_i_alu_logical0__invert_out \oper_i_alu_logical0__invert_out
+    connect \oper_i_alu_logical0__write_cr0 \oper_i_alu_logical0__write_cr0
+    connect \oper_i_alu_logical0__output_carry \oper_i_alu_logical0__output_carry
+    connect \oper_i_alu_logical0__is_32bit \oper_i_alu_logical0__is_32bit
+    connect \oper_i_alu_logical0__is_signed \oper_i_alu_logical0__is_signed
+    connect \oper_i_alu_logical0__data_len \oper_i_alu_logical0__data_len
+    connect \oper_i_alu_logical0__insn \oper_i_alu_logical0__insn
+    connect \cu_issue_i \cu_issue_i$10
+    connect \cu_busy_o \cu_busy_o$11
+    connect \cu_rdmaskn_i \cu_rdmaskn_i$12
+    connect \cu_rd__rel_o \cu_rd__rel_o$34
+    connect \cu_rd__go_i \cu_rd__go_i$35
+    connect \src1_i \src1_i$36
+    connect \src2_i \src2_i$54
+    connect \o_ok \o_ok$84
+    connect \cu_wr__rel_o \cu_wr__rel_o$85
+    connect \cu_wr__go_i \cu_wr__go_i$86
+    connect \dest1_o \dest1_o$103
+    connect \cr_a_ok \cr_a_ok$109
+    connect \dest2_o \dest2_o$114
+    connect \xer_ca_ok \xer_ca_ok$118
+    connect \dest3_o \dest3_o$122
+    connect \coresync_rst \coresync_rst
+  end
+  cell \spr0 \spr0
+    connect \coresync_clk \coresync_clk
+    connect \oper_i_alu_spr0__insn_type \oper_i_alu_spr0__insn_type
+    connect \oper_i_alu_spr0__fn_unit \oper_i_alu_spr0__fn_unit
+    connect \oper_i_alu_spr0__insn \oper_i_alu_spr0__insn
+    connect \oper_i_alu_spr0__is_32bit \oper_i_alu_spr0__is_32bit
+    connect \cu_issue_i \cu_issue_i$13
+    connect \cu_busy_o \cu_busy_o$14
+    connect \cu_rdmaskn_i \cu_rdmaskn_i$15
+    connect \cu_rd__rel_o \cu_rd__rel_o$37
+    connect \cu_rd__go_i \cu_rd__go_i$38
+    connect \src1_i \src1_i$39
+    connect \src4_i \src4_i
+    connect \src6_i \src6_i
+    connect \src5_i \src5_i
+    connect \src3_i \src3_i$74
+    connect \src2_i \src2_i$77
+    connect \o_ok \o_ok$87
+    connect \cu_wr__rel_o \cu_wr__rel_o$88
+    connect \cu_wr__go_i \cu_wr__go_i$89
+    connect \dest1_o \dest1_o$104
+    connect \xer_ca_ok \xer_ca_ok$119
+    connect \dest6_o \dest6_o
+    connect \xer_ov_ok \xer_ov_ok$124
+    connect \dest5_o \dest5_o
+    connect \xer_so_ok \xer_so_ok$129
+    connect \dest4_o \dest4_o$133
+    connect \fast1_ok \fast1_ok$139
+    connect \dest3_o \dest3_o$142
+    connect \spr1_ok \spr1_ok
+    connect \dest2_o \dest2_o$150
+    connect \coresync_rst \coresync_rst
+  end
+  cell \div0 \div0
+    connect \coresync_clk \coresync_clk
+    connect \oper_i_alu_div0__insn_type \oper_i_alu_div0__insn_type
+    connect \oper_i_alu_div0__fn_unit \oper_i_alu_div0__fn_unit
+    connect \oper_i_alu_div0__imm_data__imm \oper_i_alu_div0__imm_data__imm
+    connect \oper_i_alu_div0__imm_data__imm_ok \oper_i_alu_div0__imm_data__imm_ok
+    connect \oper_i_alu_div0__rc__rc \oper_i_alu_div0__rc__rc
+    connect \oper_i_alu_div0__rc__rc_ok \oper_i_alu_div0__rc__rc_ok
+    connect \oper_i_alu_div0__oe__oe \oper_i_alu_div0__oe__oe
+    connect \oper_i_alu_div0__oe__oe_ok \oper_i_alu_div0__oe__oe_ok
+    connect \oper_i_alu_div0__invert_a \oper_i_alu_div0__invert_a
+    connect \oper_i_alu_div0__zero_a \oper_i_alu_div0__zero_a
+    connect \oper_i_alu_div0__input_carry \oper_i_alu_div0__input_carry
+    connect \oper_i_alu_div0__invert_out \oper_i_alu_div0__invert_out
+    connect \oper_i_alu_div0__write_cr0 \oper_i_alu_div0__write_cr0
+    connect \oper_i_alu_div0__output_carry \oper_i_alu_div0__output_carry
+    connect \oper_i_alu_div0__is_32bit \oper_i_alu_div0__is_32bit
+    connect \oper_i_alu_div0__is_signed \oper_i_alu_div0__is_signed
+    connect \oper_i_alu_div0__data_len \oper_i_alu_div0__data_len
+    connect \oper_i_alu_div0__insn \oper_i_alu_div0__insn
+    connect \cu_issue_i \cu_issue_i$16
+    connect \cu_busy_o \cu_busy_o$17
+    connect \cu_rdmaskn_i \cu_rdmaskn_i$18
+    connect \cu_rd__rel_o \cu_rd__rel_o$40
+    connect \cu_rd__go_i \cu_rd__go_i$41
+    connect \src1_i \src1_i$42
+    connect \src2_i \src2_i$55
+    connect \src3_i \src3_i$61
+    connect \o_ok \o_ok$90
+    connect \cu_wr__rel_o \cu_wr__rel_o$91
+    connect \cu_wr__go_i \cu_wr__go_i$92
+    connect \dest1_o \dest1_o$105
+    connect \cr_a_ok \cr_a_ok$110
+    connect \dest2_o \dest2_o$115
+    connect \xer_ov_ok \xer_ov_ok$125
+    connect \dest3_o \dest3_o$127
+    connect \xer_so_ok \xer_so_ok$130
+    connect \dest4_o \dest4_o$134
+    connect \coresync_rst \coresync_rst
+  end
+  cell \mul0 \mul0
+    connect \coresync_clk \coresync_clk
+    connect \oper_i_alu_mul0__insn_type \oper_i_alu_mul0__insn_type
+    connect \oper_i_alu_mul0__fn_unit \oper_i_alu_mul0__fn_unit
+    connect \oper_i_alu_mul0__imm_data__imm \oper_i_alu_mul0__imm_data__imm
+    connect \oper_i_alu_mul0__imm_data__imm_ok \oper_i_alu_mul0__imm_data__imm_ok
+    connect \oper_i_alu_mul0__rc__rc \oper_i_alu_mul0__rc__rc
+    connect \oper_i_alu_mul0__rc__rc_ok \oper_i_alu_mul0__rc__rc_ok
+    connect \oper_i_alu_mul0__oe__oe \oper_i_alu_mul0__oe__oe
+    connect \oper_i_alu_mul0__oe__oe_ok \oper_i_alu_mul0__oe__oe_ok
+    connect \oper_i_alu_mul0__invert_a \oper_i_alu_mul0__invert_a
+    connect \oper_i_alu_mul0__zero_a \oper_i_alu_mul0__zero_a
+    connect \oper_i_alu_mul0__invert_out \oper_i_alu_mul0__invert_out
+    connect \oper_i_alu_mul0__write_cr0 \oper_i_alu_mul0__write_cr0
+    connect \oper_i_alu_mul0__is_32bit \oper_i_alu_mul0__is_32bit
+    connect \oper_i_alu_mul0__is_signed \oper_i_alu_mul0__is_signed
+    connect \oper_i_alu_mul0__insn \oper_i_alu_mul0__insn
+    connect \cu_issue_i \cu_issue_i$19
+    connect \cu_busy_o \cu_busy_o$20
+    connect \cu_rdmaskn_i \cu_rdmaskn_i$21
+    connect \cu_rd__rel_o \cu_rd__rel_o$43
+    connect \cu_rd__go_i \cu_rd__go_i$44
+    connect \src1_i \src1_i$45
+    connect \src2_i \src2_i$56
+    connect \src3_i \src3_i$62
+    connect \o_ok \o_ok$93
+    connect \cu_wr__rel_o \cu_wr__rel_o$94
+    connect \cu_wr__go_i \cu_wr__go_i$95
+    connect \dest1_o \dest1_o$106
+    connect \cr_a_ok \cr_a_ok$111
+    connect \dest2_o \dest2_o$116
+    connect \xer_ov_ok \xer_ov_ok$126
+    connect \dest3_o \dest3_o$128
+    connect \xer_so_ok \xer_so_ok$131
+    connect \dest4_o \dest4_o$135
+    connect \coresync_rst \coresync_rst
+  end
+  cell \shiftrot0 \shiftrot0
+    connect \coresync_clk \coresync_clk
+    connect \oper_i_alu_shift_rot0__insn_type \oper_i_alu_shift_rot0__insn_type
+    connect \oper_i_alu_shift_rot0__fn_unit \oper_i_alu_shift_rot0__fn_unit
+    connect \oper_i_alu_shift_rot0__imm_data__imm \oper_i_alu_shift_rot0__imm_data__imm
+    connect \oper_i_alu_shift_rot0__imm_data__imm_ok \oper_i_alu_shift_rot0__imm_data__imm_ok
+    connect \oper_i_alu_shift_rot0__rc__rc \oper_i_alu_shift_rot0__rc__rc
+    connect \oper_i_alu_shift_rot0__rc__rc_ok \oper_i_alu_shift_rot0__rc__rc_ok
+    connect \oper_i_alu_shift_rot0__oe__oe \oper_i_alu_shift_rot0__oe__oe
+    connect \oper_i_alu_shift_rot0__oe__oe_ok \oper_i_alu_shift_rot0__oe__oe_ok
+    connect \oper_i_alu_shift_rot0__input_carry \oper_i_alu_shift_rot0__input_carry
+    connect \oper_i_alu_shift_rot0__output_carry \oper_i_alu_shift_rot0__output_carry
+    connect \oper_i_alu_shift_rot0__input_cr \oper_i_alu_shift_rot0__input_cr
+    connect \oper_i_alu_shift_rot0__output_cr \oper_i_alu_shift_rot0__output_cr
+    connect \oper_i_alu_shift_rot0__is_32bit \oper_i_alu_shift_rot0__is_32bit
+    connect \oper_i_alu_shift_rot0__is_signed \oper_i_alu_shift_rot0__is_signed
+    connect \oper_i_alu_shift_rot0__insn \oper_i_alu_shift_rot0__insn
+    connect \cu_issue_i \cu_issue_i$22
+    connect \cu_busy_o \cu_busy_o$23
+    connect \cu_rdmaskn_i \cu_rdmaskn_i$24
+    connect \cu_rd__rel_o \cu_rd__rel_o$46
+    connect \cu_rd__go_i \cu_rd__go_i$47
+    connect \src1_i \src1_i$48
+    connect \src2_i \src2_i$57
+    connect \src3_i \src3_i
+    connect \src4_i \src4_i$64
+    connect \o_ok \o_ok$96
+    connect \cu_wr__rel_o \cu_wr__rel_o$97
+    connect \cu_wr__go_i \cu_wr__go_i$98
+    connect \dest1_o \dest1_o$107
+    connect \cr_a_ok \cr_a_ok$112
+    connect \dest2_o \dest2_o$117
+    connect \xer_ca_ok \xer_ca_ok$120
+    connect \dest3_o \dest3_o$123
+    connect \coresync_rst \coresync_rst
+  end
+  cell \ldst0 \ldst0
+    connect \coresync_clk \coresync_clk
+    connect \cu_ad__go_i \cu_ad__go_i
+    connect \cu_ad__rel_o \cu_ad__rel_o
+    connect \cu_st__go_i \cu_st__go_i
+    connect \cu_st__rel_o \cu_st__rel_o
+    connect \oper_i_ldst_ldst0__insn_type \oper_i_ldst_ldst0__insn_type
+    connect \oper_i_ldst_ldst0__imm_data__imm \oper_i_ldst_ldst0__imm_data__imm
+    connect \oper_i_ldst_ldst0__imm_data__imm_ok \oper_i_ldst_ldst0__imm_data__imm_ok
+    connect \oper_i_ldst_ldst0__zero_a \oper_i_ldst_ldst0__zero_a
+    connect \oper_i_ldst_ldst0__rc__rc \oper_i_ldst_ldst0__rc__rc
+    connect \oper_i_ldst_ldst0__rc__rc_ok \oper_i_ldst_ldst0__rc__rc_ok
+    connect \oper_i_ldst_ldst0__oe__oe \oper_i_ldst_ldst0__oe__oe
+    connect \oper_i_ldst_ldst0__oe__oe_ok \oper_i_ldst_ldst0__oe__oe_ok
+    connect \oper_i_ldst_ldst0__is_32bit \oper_i_ldst_ldst0__is_32bit
+    connect \oper_i_ldst_ldst0__is_signed \oper_i_ldst_ldst0__is_signed
+    connect \oper_i_ldst_ldst0__data_len \oper_i_ldst_ldst0__data_len
+    connect \oper_i_ldst_ldst0__byte_reverse \oper_i_ldst_ldst0__byte_reverse
+    connect \oper_i_ldst_ldst0__sign_extend \oper_i_ldst_ldst0__sign_extend
+    connect \oper_i_ldst_ldst0__ldst_mode \oper_i_ldst_ldst0__ldst_mode
+    connect \cu_issue_i \cu_issue_i$25
+    connect \cu_busy_o \cu_busy_o$26
+    connect \cu_rdmaskn_i \cu_rdmaskn_i$27
+    connect \cu_rd__rel_o \cu_rd__rel_o$49
+    connect \cu_rd__go_i \cu_rd__go_i$50
+    connect \src1_i \src1_i$51
+    connect \src2_i \src2_i$58
+    connect \src3_i \src3_i$59
+    connect \cu_wr__rel_o \cu_wr__rel_o$99
+    connect \cu_wr__go_i \cu_wr__go_i$100
+    connect \o \o
+    connect \ea \ea
+    connect \coresync_rst \coresync_rst
+    connect \ldst_port0_is_ld_i \ldst_port0_is_ld_i
+    connect \ldst_port0_is_st_i \ldst_port0_is_st_i
+    connect \ldst_port0_data_len \ldst_port0_data_len
+    connect \ldst_port0_addr_i \ldst_port0_addr_i
+    connect \ldst_port0_addr_i_ok \ldst_port0_addr_i_ok
+    connect \ldst_port0_addr_exc_o \ldst_port0_addr_exc_o
+    connect \ldst_port0_addr_ok_o \ldst_port0_addr_ok_o
+    connect \ldst_port0_ld_data_o \ldst_port0_ld_data_o
+    connect \ldst_port0_ld_data_o_ok \ldst_port0_ld_data_o_ok
+    connect \ldst_port0_st_data_i \ldst_port0_st_data_i
+    connect \ldst_port0_st_data_i_ok \ldst_port0_st_data_i_ok
+  end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.l0.pimem.st_active"
+module \st_active
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+  wire width 1 input 2 \s_st_active
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
+  wire width 1 output 3 \q_st_active
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+  wire width 1 input 4 \r_st_active
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
+  wire width 1 \q_int
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
+  wire width 1 \q_int$next
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  wire width 1 $1
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  cell $not $2
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \r_st_active
+    connect \Y $1
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  wire width 1 $3
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  cell $and $4
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \q_int
+    connect \B $1
+    connect \Y $3
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  wire width 1 $5
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  cell $or $6
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $3
+    connect \B \s_st_active
+    connect \Y $5
+  end
+  process $group_0
+    assign \q_int$next \q_int
+    assign \q_int$next $5
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
+      case 1'1
+        assign \q_int$next 1'0
+    end
+    sync init
+      update \q_int 1'0
+    sync posedge \coresync_clk
+      update \q_int \q_int$next
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  wire width 1 $7
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  cell $not $8
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \r_st_active
+    connect \Y $7
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  wire width 1 $9
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  cell $and $10
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \q_int
+    connect \B $7
+    connect \Y $9
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  wire width 1 $11
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  cell $or $12
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $9
+    connect \B \s_st_active
+    connect \Y $11
+  end
+  process $group_1
+    assign \q_st_active 1'0
+    assign \q_st_active $11
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
+  wire width 1 \qn_st_active
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
+  wire width 1 $13
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
+  cell $not $14
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \q_st_active
+    connect \Y $13
+  end
+  process $group_2
+    assign \qn_st_active 1'0
+    assign \qn_st_active $13
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62"
+  wire width 1 \qlq_st_active
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
+  wire width 1 $15
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
+  cell $or $16
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \q_st_active
+    connect \B \q_int
+    connect \Y $15
+  end
+  process $group_3
+    assign \qlq_st_active 1'0
+    assign \qlq_st_active $15
+    sync init
+  end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.l0.pimem.ld_active"
+module \ld_active
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+  wire width 1 input 2 \s_ld_active
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
+  wire width 1 output 3 \q_ld_active
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+  wire width 1 input 4 \r_ld_active
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
+  wire width 1 \q_int
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
+  wire width 1 \q_int$next
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  wire width 1 $1
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  cell $not $2
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \r_ld_active
+    connect \Y $1
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  wire width 1 $3
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  cell $and $4
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \q_int
+    connect \B $1
+    connect \Y $3
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  wire width 1 $5
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  cell $or $6
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $3
+    connect \B \s_ld_active
+    connect \Y $5
+  end
+  process $group_0
+    assign \q_int$next \q_int
+    assign \q_int$next $5
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
+      case 1'1
+        assign \q_int$next 1'0
+    end
+    sync init
+      update \q_int 1'0
+    sync posedge \coresync_clk
+      update \q_int \q_int$next
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  wire width 1 $7
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  cell $not $8
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \r_ld_active
+    connect \Y $7
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  wire width 1 $9
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  cell $and $10
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \q_int
+    connect \B $7
+    connect \Y $9
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  wire width 1 $11
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  cell $or $12
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $9
+    connect \B \s_ld_active
+    connect \Y $11
+  end
+  process $group_1
+    assign \q_ld_active 1'0
+    assign \q_ld_active $11
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
+  wire width 1 \qn_ld_active
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
+  wire width 1 $13
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
+  cell $not $14
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \q_ld_active
+    connect \Y $13
+  end
+  process $group_2
+    assign \qn_ld_active 1'0
+    assign \qn_ld_active $13
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62"
+  wire width 1 \qlq_ld_active
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
+  wire width 1 $15
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
+  cell $or $16
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \q_ld_active
+    connect \B \q_int
+    connect \Y $15
+  end
+  process $group_3
+    assign \qlq_ld_active 1'0
+    assign \qlq_ld_active $15
+    sync init
+  end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.l0.pimem.reset_l"
+module \reset_l
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+  wire width 1 input 2 \s_reset
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+  wire width 1 input 3 \r_reset
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
+  wire width 1 output 4 \q_reset
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
+  wire width 1 \q_int
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
+  wire width 1 \q_int$next
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  wire width 1 $1
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  cell $not $2
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \r_reset
+    connect \Y $1
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  wire width 1 $3
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  cell $and $4
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \q_int
+    connect \B $1
+    connect \Y $3
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  wire width 1 $5
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  cell $or $6
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $3
+    connect \B \s_reset
+    connect \Y $5
+  end
+  process $group_0
+    assign \q_int$next \q_int
+    assign \q_int$next $5
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
+      case 1'1
+        assign \q_int$next 1'0
+    end
+    sync init
+      update \q_int 1'0
+    sync posedge \coresync_clk
+      update \q_int \q_int$next
+  end
+  process $group_1
+    assign \q_reset 1'0
+    assign \q_reset \q_int
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
+  wire width 1 \qn_reset
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
+  wire width 1 $7
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
+  cell $not $8
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \q_reset
+    connect \Y $7
+  end
+  process $group_2
+    assign \qn_reset 1'0
+    assign \qn_reset $7
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62"
+  wire width 1 \qlq_reset
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
+  wire width 1 $9
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
+  cell $or $10
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \q_reset
+    connect \B \q_int
+    connect \Y $9
+  end
+  process $group_3
+    assign \qlq_reset 1'0
+    assign \qlq_reset $9
+    sync init
+  end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.l0.pimem.adrok_l"
+module \adrok_l
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+  wire width 1 input 2 \s_addr_acked
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+  wire width 1 input 3 \r_addr_acked
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
+  wire width 1 output 4 \qn_addr_acked
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
+  wire width 1 output 5 \q_addr_acked
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
+  wire width 1 \q_int
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
+  wire width 1 \q_int$next
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  wire width 1 $1
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  cell $not $2
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \r_addr_acked
+    connect \Y $1
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  wire width 1 $3
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  cell $and $4
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \q_int
+    connect \B $1
+    connect \Y $3
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  wire width 1 $5
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  cell $or $6
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $3
+    connect \B \s_addr_acked
+    connect \Y $5
+  end
+  process $group_0
+    assign \q_int$next \q_int
+    assign \q_int$next $5
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
+      case 1'1
+        assign \q_int$next 1'0
+    end
+    sync init
+      update \q_int 1'0
+    sync posedge \coresync_clk
+      update \q_int \q_int$next
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  wire width 1 $7
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  cell $not $8
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \r_addr_acked
+    connect \Y $7
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  wire width 1 $9
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  cell $and $10
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \q_int
+    connect \B $7
+    connect \Y $9
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  wire width 1 $11
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  cell $or $12
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $9
+    connect \B \s_addr_acked
+    connect \Y $11
+  end
+  process $group_1
+    assign \q_addr_acked 1'0
+    assign \q_addr_acked $11
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
+  wire width 1 $13
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
+  cell $not $14
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \q_addr_acked
+    connect \Y $13
+  end
+  process $group_2
+    assign \qn_addr_acked 1'0
+    assign \qn_addr_acked $13
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62"
+  wire width 1 \qlq_addr_acked
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
+  wire width 1 $15
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
+  cell $or $16
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \q_addr_acked
+    connect \B \q_int
+    connect \Y $15
+  end
+  process $group_3
+    assign \qlq_addr_acked 1'0
+    assign \qlq_addr_acked $15
+    sync init
+  end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.l0.pimem.busy_l"
+module \busy_l
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+  wire width 1 input 2 \s_busy
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+  wire width 1 input 3 \r_busy
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
+  wire width 1 output 4 \q_busy
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
+  wire width 1 \q_int
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
+  wire width 1 \q_int$next
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  wire width 1 $1
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  cell $not $2
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \r_busy
+    connect \Y $1
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  wire width 1 $3
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  cell $and $4
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \q_int
+    connect \B $1
+    connect \Y $3
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  wire width 1 $5
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  cell $or $6
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $3
+    connect \B \s_busy
+    connect \Y $5
+  end
+  process $group_0
+    assign \q_int$next \q_int
+    assign \q_int$next $5
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
+      case 1'1
+        assign \q_int$next 1'0
+    end
+    sync init
+      update \q_int 1'0
+    sync posedge \coresync_clk
+      update \q_int \q_int$next
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  wire width 1 $7
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  cell $not $8
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \r_busy
+    connect \Y $7
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  wire width 1 $9
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  cell $and $10
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \q_int
+    connect \B $7
+    connect \Y $9
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  wire width 1 $11
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  cell $or $12
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $9
+    connect \B \s_busy
+    connect \Y $11
+  end
+  process $group_1
+    assign \q_busy 1'0
+    assign \q_busy $11
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
+  wire width 1 \qn_busy
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
+  wire width 1 $13
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
+  cell $not $14
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \q_busy
+    connect \Y $13
+  end
+  process $group_2
+    assign \qn_busy 1'0
+    assign \qn_busy $13
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62"
+  wire width 1 \qlq_busy
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
+  wire width 1 $15
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
+  cell $or $16
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \q_busy
+    connect \B \q_int
+    connect \Y $15
+  end
+  process $group_3
+    assign \qlq_busy 1'0
+    assign \qlq_busy $15
+    sync init
+  end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.l0.pimem.cyc_l"
+module \cyc_l
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+  wire width 1 input 2 \s_cyc
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+  wire width 1 input 3 \r_cyc
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
+  wire width 1 output 4 \q_cyc
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
+  wire width 1 \q_int
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
+  wire width 1 \q_int$next
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  wire width 1 $1
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  cell $not $2
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \r_cyc
+    connect \Y $1
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  wire width 1 $3
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  cell $and $4
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \q_int
+    connect \B $1
+    connect \Y $3
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  wire width 1 $5
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  cell $or $6
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $3
+    connect \B \s_cyc
+    connect \Y $5
+  end
+  process $group_0
+    assign \q_int$next \q_int
+    assign \q_int$next $5
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
+      case 1'1
+        assign \q_int$next 1'0
+    end
+    sync init
+      update \q_int 1'0
+    sync posedge \coresync_clk
+      update \q_int \q_int$next
+  end
+  process $group_1
+    assign \q_cyc 1'0
+    assign \q_cyc \q_int
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
+  wire width 1 \qn_cyc
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
+  wire width 1 $7
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
+  cell $not $8
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \q_cyc
+    connect \Y $7
+  end
+  process $group_2
+    assign \qn_cyc 1'0
+    assign \qn_cyc $7
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62"
+  wire width 1 \qlq_cyc
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
+  wire width 1 $9
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
+  cell $or $10
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \q_cyc
+    connect \B \q_int
+    connect \Y $9
+  end
+  process $group_3
+    assign \qlq_cyc 1'0
+    assign \qlq_cyc $9
+    sync init
+  end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.l0.pimem.lenexp"
+module \lenexp
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:130"
+  wire width 4 input 0 \len_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:131"
+  wire width 4 input 1 \addr_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:132"
+  wire width 64 output 2 \lexp_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:134"
+  wire width 176 output 3 \rexp_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:148"
+  wire width 17 \binlen
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150"
+  wire width 21 $1
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150"
+  wire width 20 $2
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150"
+  cell $sshl $3
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 5
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 4
+    parameter \Y_WIDTH 20
+    connect \A 5'00001
+    connect \B \len_i
+    connect \Y $2
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150"
+  wire width 21 $4
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150"
+  cell $sub $5
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 20
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 21
+    connect \A $2
+    connect \B 1'1
+    connect \Y $4
+  end
+  connect $1 $4
+  process $group_0
+    assign \binlen 17'00000000000000000
+    assign \binlen $1 [16:0]
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:151"
+  wire width 64 $6
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:151"
+  wire width 32 $7
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:151"
+  cell $sshl $8
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 17
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 4
+    parameter \Y_WIDTH 32
+    connect \A \binlen
+    connect \B \addr_i
+    connect \Y $7
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:151"
+  cell $pos $9
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 32
+    parameter \Y_WIDTH 64
+    connect \A $7
+    connect \Y $6
+  end
+  process $group_1
+    assign \lexp_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \lexp_o $6
+    sync init
+  end
+  process $group_2
+    assign \rexp_o 176'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
+    assign \rexp_o { { \lexp_o [63] \lexp_o [63] \lexp_o [63] \lexp_o [63] \lexp_o [63] \lexp_o [63] \lexp_o [63] \lexp_o [63] } { \lexp_o [62] \lexp_o [62] \lexp_o [62] \lexp_o [62] \lexp_o [62] \lexp_o [62] \lexp_o [62] \lexp_o [62] } { \lexp_o [61] \lexp_o [61] \lexp_o [61] \lexp_o [61] \lexp_o [61] \lexp_o [61] \lexp_o [61] \lexp_o [61] } { \lexp_o [60] \lexp_o [60] \lexp_o [60] \lexp_o [60] \lexp_o [60] \lexp_o [60] \lexp_o [60] \lexp_o [60] } { \lexp_o [59] \lexp_o [59] \lexp_o [59] \lexp_o [59] \lexp_o [59] \lexp_o [59] \lexp_o [59] \lexp_o [59] } { \lexp_o [58] \lexp_o [58] \lexp_o [58] \lexp_o [58] \lexp_o [58] \lexp_o [58] \lexp_o [58] \lexp_o [58] } { \lexp_o [57] \lexp_o [57] \lexp_o [57] \lexp_o [57] \lexp_o [57] \lexp_o [57] \lexp_o [57] \lexp_o [57] } { \lexp_o [56] \lexp_o [56] \lexp_o [56] \lexp_o [56] \lexp_o [56] \lexp_o [56] \lexp_o [56] \lexp_o [56] } { \lexp_o [55] \lexp_o [55] \lexp_o [55] \lexp_o [55] \lexp_o [55] \lexp_o [55] \lexp_o [55] \lexp_o [55] } { \lexp_o [54] \lexp_o [54] \lexp_o [54] \lexp_o [54] \lexp_o [54] \lexp_o [54] \lexp_o [54] \lexp_o [54] } { \lexp_o [53] \lexp_o [53] \lexp_o [53] \lexp_o [53] \lexp_o [53] \lexp_o [53] \lexp_o [53] \lexp_o [53] } { \lexp_o [52] \lexp_o [52] \lexp_o [52] \lexp_o [52] \lexp_o [52] \lexp_o [52] \lexp_o [52] \lexp_o [52] } { \lexp_o [51] \lexp_o [51] \lexp_o [51] \lexp_o [51] \lexp_o [51] \lexp_o [51] \lexp_o [51] \lexp_o [51] } { \lexp_o [50] \lexp_o [50] \lexp_o [50] \lexp_o [50] \lexp_o [50] \lexp_o [50] \lexp_o [50] \lexp_o [50] } { \lexp_o [49] \lexp_o [49] \lexp_o [49] \lexp_o [49] \lexp_o [49] \lexp_o [49] \lexp_o [49] \lexp_o [49] } { \lexp_o [48] \lexp_o [48] \lexp_o [48] \lexp_o [48] \lexp_o [48] \lexp_o [48] \lexp_o [48] \lexp_o [48] } { \lexp_o [47] \lexp_o [47] \lexp_o [47] \lexp_o [47] \lexp_o [47] \lexp_o [47] \lexp_o [47] \lexp_o [47] } { \lexp_o [46] \lexp_o [46] \lexp_o [46] \lexp_o [46] \lexp_o [46] \lexp_o [46] \lexp_o [46] \lexp_o [46] } { \lexp_o [45] \lexp_o [45] \lexp_o [45] \lexp_o [45] \lexp_o [45] \lexp_o [45] \lexp_o [45] \lexp_o [45] } { \lexp_o [44] \lexp_o [44] \lexp_o [44] \lexp_o [44] \lexp_o [44] \lexp_o [44] \lexp_o [44] \lexp_o [44] } { \lexp_o [43] \lexp_o [43] \lexp_o [43] \lexp_o [43] \lexp_o [43] \lexp_o [43] \lexp_o [43] \lexp_o [43] } { \lexp_o [42] \lexp_o [42] \lexp_o [42] \lexp_o [42] \lexp_o [42] \lexp_o [42] \lexp_o [42] \lexp_o [42] } { \lexp_o [41] \lexp_o [41] \lexp_o [41] \lexp_o [41] \lexp_o [41] \lexp_o [41] \lexp_o [41] \lexp_o [41] } { \lexp_o [40] \lexp_o [40] \lexp_o [40] \lexp_o [40] \lexp_o [40] \lexp_o [40] \lexp_o [40] \lexp_o [40] } { \lexp_o [39] \lexp_o [39] \lexp_o [39] \lexp_o [39] \lexp_o [39] \lexp_o [39] \lexp_o [39] \lexp_o [39] } { \lexp_o [38] \lexp_o [38] \lexp_o [38] \lexp_o [38] \lexp_o [38] \lexp_o [38] \lexp_o [38] \lexp_o [38] } { \lexp_o [37] \lexp_o [37] \lexp_o [37] \lexp_o [37] \lexp_o [37] \lexp_o [37] \lexp_o [37] \lexp_o [37] } { \lexp_o [36] \lexp_o [36] \lexp_o [36] \lexp_o [36] \lexp_o [36] \lexp_o [36] \lexp_o [36] \lexp_o [36] } { \lexp_o [35] \lexp_o [35] \lexp_o [35] \lexp_o [35] \lexp_o [35] \lexp_o [35] \lexp_o [35] \lexp_o [35] } { \lexp_o [34] \lexp_o [34] \lexp_o [34] \lexp_o [34] \lexp_o [34] \lexp_o [34] \lexp_o [34] \lexp_o [34] } { \lexp_o [33] \lexp_o [33] \lexp_o [33] \lexp_o [33] \lexp_o [33] \lexp_o [33] \lexp_o [33] \lexp_o [33] } { \lexp_o [32] \lexp_o [32] \lexp_o [32] \lexp_o [32] \lexp_o [32] \lexp_o [32] \lexp_o [32] \lexp_o [32] } { \lexp_o [31] \lexp_o [31] \lexp_o [31] \lexp_o [31] \lexp_o [31] \lexp_o [31] \lexp_o [31] \lexp_o [31] } { \lexp_o [30] \lexp_o [30] \lexp_o [30] \lexp_o [30] \lexp_o [30] \lexp_o [30] \lexp_o [30] \lexp_o [30] } { \lexp_o [29] \lexp_o [29] \lexp_o [29] \lexp_o [29] \lexp_o [29] \lexp_o [29] \lexp_o [29] \lexp_o [29] } { \lexp_o [28] \lexp_o [28] \lexp_o [28] \lexp_o [28] \lexp_o [28] \lexp_o [28] \lexp_o [28] \lexp_o [28] } { \lexp_o [27] \lexp_o [27] \lexp_o [27] \lexp_o [27] \lexp_o [27] \lexp_o [27] \lexp_o [27] \lexp_o [27] } { \lexp_o [26] \lexp_o [26] \lexp_o [26] \lexp_o [26] \lexp_o [26] \lexp_o [26] \lexp_o [26] \lexp_o [26] } { \lexp_o [25] \lexp_o [25] \lexp_o [25] \lexp_o [25] \lexp_o [25] \lexp_o [25] \lexp_o [25] \lexp_o [25] } { \lexp_o [24] \lexp_o [24] \lexp_o [24] \lexp_o [24] \lexp_o [24] \lexp_o [24] \lexp_o [24] \lexp_o [24] } { \lexp_o [23] \lexp_o [23] \lexp_o [23] \lexp_o [23] \lexp_o [23] \lexp_o [23] \lexp_o [23] \lexp_o [23] } { \lexp_o [22] \lexp_o [22] \lexp_o [22] \lexp_o [22] \lexp_o [22] \lexp_o [22] \lexp_o [22] \lexp_o [22] } { \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21] } { \lexp_o [20] \lexp_o [20] \lexp_o [20] \lexp_o [20] \lexp_o [20] \lexp_o [20] \lexp_o [20] \lexp_o [20] } { \lexp_o [19] \lexp_o [19] \lexp_o [19] \lexp_o [19] \lexp_o [19] \lexp_o [19] \lexp_o [19] \lexp_o [19] } { \lexp_o [18] \lexp_o [18] \lexp_o [18] \lexp_o [18] \lexp_o [18] \lexp_o [18] \lexp_o [18] \lexp_o [18] } { \lexp_o [17] \lexp_o [17] \lexp_o [17] \lexp_o [17] \lexp_o [17] \lexp_o [17] \lexp_o [17] \lexp_o [17] } { \lexp_o [16] \lexp_o [16] \lexp_o [16] \lexp_o [16] \lexp_o [16] \lexp_o [16] \lexp_o [16] \lexp_o [16] } { \lexp_o [15] \lexp_o [15] \lexp_o [15] \lexp_o [15] \lexp_o [15] \lexp_o [15] \lexp_o [15] \lexp_o [15] } { \lexp_o [14] \lexp_o [14] \lexp_o [14] \lexp_o [14] \lexp_o [14] \lexp_o [14] \lexp_o [14] \lexp_o [14] } { \lexp_o [13] \lexp_o [13] \lexp_o [13] \lexp_o [13] \lexp_o [13] \lexp_o [13] \lexp_o [13] \lexp_o [13] } { \lexp_o [12] \lexp_o [12] \lexp_o [12] \lexp_o [12] \lexp_o [12] \lexp_o [12] \lexp_o [12] \lexp_o [12] } { \lexp_o [11] \lexp_o [11] \lexp_o [11] \lexp_o [11] \lexp_o [11] \lexp_o [11] \lexp_o [11] \lexp_o [11] } { \lexp_o [10] \lexp_o [10] \lexp_o [10] \lexp_o [10] \lexp_o [10] \lexp_o [10] \lexp_o [10] \lexp_o [10] } { \lexp_o [9] \lexp_o [9] \lexp_o [9] \lexp_o [9] \lexp_o [9] \lexp_o [9] \lexp_o [9] \lexp_o [9] } { \lexp_o [8] \lexp_o [8] \lexp_o [8] \lexp_o [8] \lexp_o [8] \lexp_o [8] \lexp_o [8] \lexp_o [8] } { \lexp_o [7] \lexp_o [7] \lexp_o [7] \lexp_o [7] \lexp_o [7] \lexp_o [7] \lexp_o [7] \lexp_o [7] } { \lexp_o [6] \lexp_o [6] \lexp_o [6] \lexp_o [6] \lexp_o [6] \lexp_o [6] \lexp_o [6] \lexp_o [6] } { \lexp_o [5] \lexp_o [5] \lexp_o [5] \lexp_o [5] \lexp_o [5] \lexp_o [5] \lexp_o [5] \lexp_o [5] } { \lexp_o [4] \lexp_o [4] \lexp_o [4] \lexp_o [4] \lexp_o [4] \lexp_o [4] \lexp_o [4] \lexp_o [4] } { \lexp_o [3] \lexp_o [3] \lexp_o [3] \lexp_o [3] \lexp_o [3] \lexp_o [3] \lexp_o [3] \lexp_o [3] } { \lexp_o [2] \lexp_o [2] \lexp_o [2] \lexp_o [2] \lexp_o [2] \lexp_o [2] \lexp_o [2] \lexp_o [2] } { \lexp_o [1] \lexp_o [1] \lexp_o [1] \lexp_o [1] \lexp_o [1] \lexp_o [1] \lexp_o [1] \lexp_o [1] } { \lexp_o [0] \lexp_o [0] \lexp_o [0] \lexp_o [0] \lexp_o [0] \lexp_o [0] \lexp_o [0] \lexp_o [0] } } [175:0]
+    sync init
+  end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.l0.pimem.valid_l"
+module \valid_l
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+  wire width 1 input 2 \s_valid
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
+  wire width 1 output 3 \q_valid
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+  wire width 1 input 4 \r_valid
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
+  wire width 1 \q_int
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
+  wire width 1 \q_int$next
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  wire width 1 $1
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  cell $not $2
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \r_valid
+    connect \Y $1
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  wire width 1 $3
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  cell $and $4
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \q_int
+    connect \B $1
+    connect \Y $3
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  wire width 1 $5
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  cell $or $6
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $3
+    connect \B \s_valid
+    connect \Y $5
+  end
+  process $group_0
+    assign \q_int$next \q_int
+    assign \q_int$next $5
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
+      case 1'1
+        assign \q_int$next 1'0
+    end
+    sync init
+      update \q_int 1'0
+    sync posedge \coresync_clk
+      update \q_int \q_int$next
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  wire width 1 $7
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  cell $not $8
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \r_valid
+    connect \Y $7
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  wire width 1 $9
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  cell $and $10
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \q_int
+    connect \B $7
+    connect \Y $9
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  wire width 1 $11
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  cell $or $12
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $9
+    connect \B \s_valid
+    connect \Y $11
+  end
+  process $group_1
+    assign \q_valid 1'0
+    assign \q_valid $11
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
+  wire width 1 \qn_valid
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
+  wire width 1 $13
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
+  cell $not $14
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \q_valid
+    connect \Y $13
+  end
+  process $group_2
+    assign \qn_valid 1'0
+    assign \qn_valid $13
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62"
+  wire width 1 \qlq_valid
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
+  wire width 1 $15
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
+  cell $or $16
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \q_valid
+    connect \B \q_int
+    connect \Y $15
+  end
+  process $group_3
+    assign \qlq_valid 1'0
+    assign \qlq_valid $15
+    sync init
+  end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.l0.pimem"
+module \pimem
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:95"
+  wire width 1 input 2 \ldst_port0_is_ld_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102"
+  wire width 1 output 3 \ldst_port0_busy_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:96"
+  wire width 1 input 4 \ldst_port0_is_st_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99"
+  wire width 4 input 5 \ldst_port0_data_len
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 48 input 6 \ldst_port0_addr_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 input 7 \ldst_port0_addr_i_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:27"
+  wire width 8 output 8 \x_mask_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:26"
+  wire width 48 output 9 \x_addr_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:106"
+  wire width 1 output 10 \ldst_port0_addr_ok_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:45"
+  wire width 64 input 11 \m_ld_data_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 64 output 12 \ldst_port0_ld_data_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 output 13 \ldst_port0_ld_data_o_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:42"
+  wire width 1 input 14 \x_busy_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 input 15 \ldst_port0_st_data_i_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 64 input 16 \ldst_port0_st_data_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:30"
+  wire width 64 output 17 \x_st_data_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:107"
+  wire width 1 input 18 \ldst_port0_addr_exc_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:28"
+  wire width 1 output 19 \x_ld_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:29"
+  wire width 1 output 20 \x_st_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:37"
+  wire width 1 output 21 \m_valid_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:33"
+  wire width 1 output 22 \x_valid_i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+  wire width 1 \st_active_s_st_active
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
+  wire width 1 \st_active_q_st_active
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+  wire width 1 \st_active_r_st_active
+  cell \st_active \st_active
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
+    connect \s_st_active \st_active_s_st_active
+    connect \q_st_active \st_active_q_st_active
+    connect \r_st_active \st_active_r_st_active
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+  wire width 1 \ld_active_s_ld_active
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
+  wire width 1 \ld_active_q_ld_active
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+  wire width 1 \ld_active_r_ld_active
+  cell \ld_active \ld_active
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
+    connect \s_ld_active \ld_active_s_ld_active
+    connect \q_ld_active \ld_active_q_ld_active
+    connect \r_ld_active \ld_active_r_ld_active
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+  wire width 1 \reset_l_s_reset
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+  wire width 1 \reset_l_r_reset
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
+  wire width 1 \reset_l_q_reset
+  cell \reset_l \reset_l
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
+    connect \s_reset \reset_l_s_reset
+    connect \r_reset \reset_l_r_reset
+    connect \q_reset \reset_l_q_reset
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+  wire width 1 \adrok_l_s_addr_acked
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+  wire width 1 \adrok_l_s_addr_acked$next
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+  wire width 1 \adrok_l_r_addr_acked
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
+  wire width 1 \adrok_l_qn_addr_acked
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
+  wire width 1 \adrok_l_q_addr_acked
+  cell \adrok_l \adrok_l
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
+    connect \s_addr_acked \adrok_l_s_addr_acked
+    connect \r_addr_acked \adrok_l_r_addr_acked
+    connect \qn_addr_acked \adrok_l_qn_addr_acked
+    connect \q_addr_acked \adrok_l_q_addr_acked
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+  wire width 1 \busy_l_s_busy
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+  wire width 1 \busy_l_r_busy
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
+  wire width 1 \busy_l_q_busy
+  cell \busy_l \busy_l
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
+    connect \s_busy \busy_l_s_busy
+    connect \r_busy \busy_l_r_busy
+    connect \q_busy \busy_l_q_busy
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+  wire width 1 \cyc_l_s_cyc
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+  wire width 1 \cyc_l_r_cyc
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
+  wire width 1 \cyc_l_q_cyc
+  cell \cyc_l \cyc_l
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
+    connect \s_cyc \cyc_l_s_cyc
+    connect \r_cyc \cyc_l_r_cyc
+    connect \q_cyc \cyc_l_q_cyc
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:130"
+  wire width 4 \lenexp_len_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:131"
+  wire width 4 \lenexp_addr_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:132"
+  wire width 64 \lenexp_lexp_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:134"
+  wire width 176 \lenexp_rexp_o
+  cell \lenexp \lenexp
+    connect \len_i \lenexp_len_i
+    connect \addr_i \lenexp_addr_i
+    connect \lexp_o \lenexp_lexp_o
+    connect \rexp_o \lenexp_rexp_o
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+  wire width 1 \valid_l_s_valid
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
+  wire width 1 \valid_l_q_valid
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+  wire width 1 \valid_l_r_valid
+  cell \valid_l \valid_l
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
+    connect \s_valid \valid_l_s_valid
+    connect \q_valid \valid_l_q_valid
+    connect \r_valid \valid_l_r_valid
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:261"
+  wire width 1 $1
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:261"
+  cell $or $2
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \ldst_port0_st_data_i_ok
+    connect \B \ldst_port0_ld_data_o_ok
+    connect \Y $1
+  end
+  process $group_0
+    assign \cyc_l_s_cyc 1'0
+    assign \cyc_l_s_cyc 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:261"
+    switch { $1 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:261"
+      case 1'1
+        assign \cyc_l_s_cyc 1'1
+    end
+    sync init
+  end
+  process $group_1
+    assign \cyc_l_r_cyc 1'1
+    assign \cyc_l_r_cyc 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:264"
+    switch { \cyc_l_q_cyc }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:264"
+      case 1'1
+        assign \cyc_l_r_cyc 1'1
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:195"
+  wire width 1 $3
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:195"
+  cell $and $4
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \ldst_port0_addr_i_ok
+    connect \B \adrok_l_qn_addr_acked
+    connect \Y $3
+  end
+  process $group_2
+    assign \adrok_l_s_addr_acked$next \adrok_l_s_addr_acked
+    assign \adrok_l_s_addr_acked$next 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:190"
+    switch { \ld_active_q_ld_active }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:190"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:195"
+        switch { $3 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:195"
+          case 1'1
+            assign \adrok_l_s_addr_acked$next 1'1
+        end
+    end
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:202"
+    switch { \st_active_q_st_active }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:202"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:207"
+        switch { \ldst_port0_addr_i_ok }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:207"
+          case 1'1
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:209"
+            switch { \adrok_l_qn_addr_acked }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:209"
+              case 1'1
+                assign \adrok_l_s_addr_acked$next 1'1
+            end
+        end
+    end
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
+      case 1'1
+        assign \adrok_l_s_addr_acked$next 1'0
+    end
+    sync init
+      update \adrok_l_s_addr_acked 1'0
+    sync posedge \coresync_clk
+      update \adrok_l_s_addr_acked \adrok_l_s_addr_acked$next
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:240"
+  wire width 1 \reset_delay
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:240"
+  wire width 1 \reset_delay$next
+  process $group_3
+    assign \adrok_l_r_addr_acked 1'1
+    assign \adrok_l_r_addr_acked 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:242"
+    switch { \reset_delay }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:242"
+      case 1'1
+        assign \adrok_l_r_addr_acked 1'1
+    end
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:246"
+    switch { \reset_l_q_reset }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:246"
+      case 1'1
+        assign \adrok_l_r_addr_acked 1'1
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:176"
+  wire width 1 \lds
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:179"
+  wire width 1 $5
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:179"
+  cell $and $6
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \ldst_port0_is_ld_i
+    connect \B \ldst_port0_busy_o
+    connect \Y $5
+  end
+  process $group_4
+    assign \lds 1'0
+    assign \lds $5
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:177"
+  wire width 1 \sts
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:180"
+  wire width 1 $7
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:180"
+  cell $and $8
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \ldst_port0_is_st_i
+    connect \B \ldst_port0_busy_o
+    connect \Y $7
+  end
+  process $group_5
+    assign \sts 1'0
+    assign \sts $7
+    sync init
+  end
+  process $group_6
+    assign \ld_active_s_ld_active 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:183"
+    switch { \sts \lds }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:183"
+      case 2'-1
+        assign \ld_active_s_ld_active 1'1
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:185"
+      case 2'1-
+    end
+    sync init
+  end
+  process $group_7
+    assign \st_active_s_st_active 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:183"
+    switch { \sts \lds }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:183"
+      case 2'-1
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:185"
+      case 2'1-
+        assign \st_active_s_st_active 1'1
+    end
+    sync init
+  end
+  process $group_8
+    assign \lenexp_len_i 4'0000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:190"
+    switch { \ld_active_q_ld_active }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:190"
+      case 1'1
+        assign \lenexp_len_i \ldst_port0_data_len
+    end
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:202"
+    switch { \st_active_q_st_active }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:202"
+      case 1'1
+        assign \lenexp_len_i \ldst_port0_data_len
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265"
+  wire width 4 $9
+  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265"
+  cell $pos $10
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 3
+    parameter \Y_WIDTH 4
+    connect \A \ldst_port0_addr_i [2:0]
+    connect \Y $9
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265"
+  wire width 4 $11
+  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265"
+  cell $pos $12
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 3
+    parameter \Y_WIDTH 4
+    connect \A \ldst_port0_addr_i [2:0]
+    connect \Y $11
+  end
+  process $group_9
+    assign \lenexp_addr_i 4'0000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:190"
+    switch { \ld_active_q_ld_active }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:190"
+      case 1'1
+        assign \lenexp_addr_i $9
+    end
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:202"
+    switch { \st_active_q_st_active }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:202"
+      case 1'1
+        assign \lenexp_addr_i $11
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:195"
+  wire width 1 $13
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:195"
+  cell $and $14
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \ldst_port0_addr_i_ok
+    connect \B \adrok_l_qn_addr_acked
+    connect \Y $13
+  end
+  process $group_10
+    assign \valid_l_s_valid 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:190"
+    switch { \ld_active_q_ld_active }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:190"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:195"
+        switch { $13 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:195"
+          case 1'1
+            assign \valid_l_s_valid 1'1
+        end
+    end
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:202"
+    switch { \st_active_q_st_active }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:202"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:207"
+        switch { \ldst_port0_addr_i_ok }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:207"
+          case 1'1
+            assign \valid_l_s_valid 1'1
+        end
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:195"
+  wire width 1 $15
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:195"
+  cell $and $16
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \ldst_port0_addr_i_ok
+    connect \B \adrok_l_qn_addr_acked
+    connect \Y $15
+  end
+  process $group_11
+    assign \x_mask_i 8'00000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:190"
+    switch { \ld_active_q_ld_active }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:190"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:195"
+        switch { $15 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:195"
+          case 1'1
+            assign \x_mask_i \lenexp_lexp_o [7:0]
+        end
+    end
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:202"
+    switch { \st_active_q_st_active }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:202"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:207"
+        switch { \ldst_port0_addr_i_ok }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:207"
+          case 1'1
+            assign \x_mask_i \lenexp_lexp_o [7:0]
+        end
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:195"
+  wire width 1 $17
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:195"
+  cell $and $18
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \ldst_port0_addr_i_ok
+    connect \B \adrok_l_qn_addr_acked
+    connect \Y $17
+  end
+  process $group_12
+    assign \x_addr_i 48'000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:190"
+    switch { \ld_active_q_ld_active }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:190"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:195"
+        switch { $17 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:195"
+          case 1'1
+            assign \x_addr_i \ldst_port0_addr_i
+        end
+    end
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:202"
+    switch { \st_active_q_st_active }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:202"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:207"
+        switch { \ldst_port0_addr_i_ok }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:207"
+          case 1'1
+            assign \x_addr_i \ldst_port0_addr_i
+        end
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:195"
+  wire width 1 $19
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:195"
+  cell $and $20
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \ldst_port0_addr_i_ok
+    connect \B \adrok_l_qn_addr_acked
+    connect \Y $19
+  end
+  process $group_13
+    assign \ldst_port0_addr_ok_o 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:190"
+    switch { \ld_active_q_ld_active }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:190"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:195"
+        switch { $19 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:195"
+          case 1'1
+            assign \ldst_port0_addr_ok_o 1'1
+        end
+    end
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:202"
+    switch { \st_active_q_st_active }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:202"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:207"
+        switch { \ldst_port0_addr_i_ok }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:207"
+          case 1'1
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:209"
+            switch { \adrok_l_qn_addr_acked }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:209"
+              case 1'1
+                assign \ldst_port0_addr_ok_o 1'1
+            end
+        end
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:221"
+  wire width 1 $21
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:221"
+  cell $and $22
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \ld_active_q_ld_active
+    connect \B \adrok_l_q_addr_acked
+    connect \Y $21
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:61"
+  wire width 1 $23
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:61"
+  cell $not $24
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \x_busy_o
+    connect \Y $23
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:229"
+  wire width 1 $25
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:229"
+  cell $and $26
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \st_active_q_st_active
+    connect \B \ldst_port0_st_data_i_ok
+    connect \Y $25
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:58"
+  wire width 1 $27
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:58"
+  cell $not $28
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \x_busy_o
+    connect \Y $27
+  end
+  process $group_14
+    assign \reset_l_s_reset 1'0
+    assign \reset_l_s_reset 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:221"
+    switch { $21 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:221"
+      case 1'1
+        assign \reset_l_s_reset $23
+    end
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:229"
+    switch { $25 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:229"
+      case 1'1
+        assign \reset_l_s_reset $27
+    end
+    sync init
+  end
+  process $group_15
+    assign \reset_l_r_reset 1'1
+    assign \reset_l_r_reset 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:246"
+    switch { \reset_l_q_reset }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:246"
+      case 1'1
+        assign \reset_l_r_reset 1'1
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:217"
+  wire width 64 \lddata
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:220"
+  wire width 176 $29
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:219"
+  wire width 176 $30
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:219"
+  cell $and $31
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 64
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 176
+    parameter \Y_WIDTH 176
+    connect \A \m_ld_data_o
+    connect \B \lenexp_rexp_o
+    connect \Y $30
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:220"
+  wire width 8 $32
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:220"
+  cell $mul $33
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 4
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 4
+    parameter \Y_WIDTH 8
+    connect \A \lenexp_addr_i
+    connect \B 4'1000
+    connect \Y $32
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:220"
+  wire width 176 $34
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:220"
+  cell $sshr $35
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 176
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 8
+    parameter \Y_WIDTH 176
+    connect \A $30
+    connect \B $32
+    connect \Y $34
+  end
+  connect $29 $34
+  process $group_16
+    assign \lddata 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \lddata $29 [63:0]
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:221"
+  wire width 1 $36
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:221"
+  cell $and $37
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \ld_active_q_ld_active
+    connect \B \adrok_l_q_addr_acked
+    connect \Y $36
+  end
+  process $group_17
+    assign \ldst_port0_ld_data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:221"
+    switch { $36 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:221"
+      case 1'1
+        assign \ldst_port0_ld_data_o \lddata
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:221"
+  wire width 1 $38
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:221"
+  cell $and $39
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \ld_active_q_ld_active
+    connect \B \adrok_l_q_addr_acked
+    connect \Y $38
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:61"
+  wire width 1 $40
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:61"
+  cell $not $41
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \x_busy_o
+    connect \Y $40
+  end
+  process $group_18
+    assign \ldst_port0_ld_data_o_ok 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:221"
+    switch { $38 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:221"
+      case 1'1
+        assign \ldst_port0_ld_data_o_ok $40
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:232"
+  wire width 64 \stdata
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:229"
+  wire width 1 $42
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:229"
+  cell $and $43
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \st_active_q_st_active
+    connect \B \ldst_port0_st_data_i_ok
+    connect \Y $42
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233"
+  wire width 319 $44
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233"
+  wire width 8 $45
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233"
+  cell $mul $46
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 4
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 4
+    parameter \Y_WIDTH 8
+    connect \A \lenexp_addr_i
+    connect \B 4'1000
+    connect \Y $45
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233"
+  wire width 319 $47
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:233"
+  cell $sshl $48
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 64
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 8
+    parameter \Y_WIDTH 319
+    connect \A \ldst_port0_st_data_i
+    connect \B $45
+    connect \Y $47
+  end
+  connect $44 $47
+  process $group_19
+    assign \stdata 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:229"
+    switch { $42 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:229"
+      case 1'1
+        assign \stdata $44 [63:0]
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:229"
+  wire width 1 $49
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:229"
+  cell $and $50
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \st_active_q_st_active
+    connect \B \ldst_port0_st_data_i_ok
+    connect \Y $49
+  end
+  process $group_20
+    assign \x_st_data_i 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:229"
+    switch { $49 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:229"
+      case 1'1
+        assign \x_st_data_i \stdata
+    end
+    sync init
+  end
+  process $group_21
+    assign \reset_delay$next \reset_delay
+    assign \reset_delay$next \reset_l_q_reset
+    sync init
+      update \reset_delay 1'0
+    sync posedge \coresync_clk
+      update \reset_delay \reset_delay$next
+  end
+  process $group_22
+    assign \ld_active_r_ld_active 1'1
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:246"
+    switch { \reset_l_q_reset }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:246"
+      case 1'1
+        assign \ld_active_r_ld_active 1'1
+    end
+    sync init
+  end
+  process $group_23
+    assign \st_active_r_st_active 1'1
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:246"
+    switch { \reset_l_q_reset }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:246"
+      case 1'1
+        assign \st_active_r_st_active 1'1
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:253"
+  wire width 1 $51
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:253"
+  cell $or $52
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \ldst_port0_is_ld_i
+    connect \B \ldst_port0_is_st_i
+    connect \Y $51
+  end
+  process $group_24
+    assign \busy_l_s_busy 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:253"
+    switch { $51 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:253"
+      case 1'1
+        assign \busy_l_s_busy 1'1
+    end
+    sync init
+  end
+  process $group_25
+    assign \busy_l_r_busy 1'1
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:257"
+    switch { \ldst_port0_addr_exc_o }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:257"
+      case 1'1
+        assign \busy_l_r_busy 1'1
+    end
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:264"
+    switch { \cyc_l_q_cyc }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:264"
+      case 1'1
+        assign \busy_l_r_busy 1'1
+    end
+    sync init
+  end
+  process $group_26
+    assign \ldst_port0_busy_o 1'0
+    assign \ldst_port0_busy_o \busy_l_q_busy
+    sync init
+  end
+  process $group_27
+    assign \x_ld_i 1'0
+    assign \x_ld_i \ldst_port0_is_ld_i
+    sync init
+  end
+  process $group_28
+    assign \x_st_i 1'0
+    assign \x_st_i \ldst_port0_is_st_i
+    sync init
+  end
+  process $group_29
+    assign \m_valid_i 1'0
+    assign \m_valid_i \valid_l_q_valid
+    sync init
+  end
+  process $group_30
+    assign \x_valid_i 1'0
+    assign \x_valid_i \valid_l_q_valid
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:79"
+  wire width 1 $53
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:79"
+  cell $not $54
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \ldst_port0_busy_o
+    connect \Y $53
+  end
+  process $group_31
+    assign \valid_l_r_valid 1'1
+    assign \valid_l_r_valid $53
+    sync init
+  end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.l0.l0.idx_l"
+module \idx_l
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
+  wire width 1 output 2 \q_idx_l
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+  wire width 1 input 3 \s_idx_l
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+  wire width 1 input 4 \r_idx_l
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
+  wire width 1 \q_int
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
+  wire width 1 \q_int$next
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  wire width 1 $1
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  cell $not $2
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \r_idx_l
+    connect \Y $1
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  wire width 1 $3
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  cell $and $4
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \q_int
+    connect \B $1
+    connect \Y $3
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  wire width 1 $5
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  cell $or $6
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $3
+    connect \B \s_idx_l
+    connect \Y $5
+  end
+  process $group_0
+    assign \q_int$next \q_int
+    assign \q_int$next $5
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
+      case 1'1
+        assign \q_int$next 1'0
+    end
+    sync init
+      update \q_int 1'0
+    sync posedge \coresync_clk
+      update \q_int \q_int$next
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  wire width 1 $7
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  cell $not $8
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \r_idx_l
+    connect \Y $7
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  wire width 1 $9
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  cell $and $10
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \q_int
+    connect \B $7
+    connect \Y $9
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  wire width 1 $11
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72"
+  cell $or $12
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $9
+    connect \B \s_idx_l
+    connect \Y $11
+  end
+  process $group_1
+    assign \q_idx_l 1'0
+    assign \q_idx_l $11
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
+  wire width 1 \qn_idx_l
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
+  wire width 1 $13
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
+  cell $not $14
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \q_idx_l
+    connect \Y $13
+  end
+  process $group_2
+    assign \qn_idx_l 1'0
+    assign \qn_idx_l $13
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62"
+  wire width 1 \qlq_idx_l
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
+  wire width 1 $15
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
+  cell $or $16
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \q_idx_l
+    connect \B \q_int
+    connect \Y $15
+  end
+  process $group_3
+    assign \qlq_idx_l 1'0
+    assign \qlq_idx_l $15
+    sync init
+  end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.l0.l0.reset_l"
+module \reset_l$124
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+  wire width 1 input 2 \s_reset
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+  wire width 1 input 3 \r_reset
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
+  wire width 1 output 4 \q_reset
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
+  wire width 1 \q_int
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66"
+  wire width 1 \q_int$next
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  wire width 1 $1
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  cell $not $2
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \r_reset
+    connect \Y $1
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  wire width 1 $3
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  cell $and $4
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \q_int
+    connect \B $1
+    connect \Y $3
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  wire width 1 $5
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68"
+  cell $or $6
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $3
+    connect \B \s_reset
+    connect \Y $5
+  end
+  process $group_0
+    assign \q_int$next \q_int
+    assign \q_int$next $5
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
+      case 1'1
+        assign \q_int$next 1'0
+    end
+    sync init
+      update \q_int 1'0
+    sync posedge \coresync_clk
+      update \q_int \q_int$next
+  end
+  process $group_1
+    assign \q_reset 1'0
+    assign \q_reset \q_int
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61"
+  wire width 1 \qn_reset
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
+  wire width 1 $7
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73"
+  cell $not $8
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \q_reset
+    connect \Y $7
+  end
+  process $group_2
+    assign \qn_reset 1'0
+    assign \qn_reset $7
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62"
+  wire width 1 \qlq_reset
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
+  wire width 1 $9
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74"
+  cell $or $10
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \q_reset
+    connect \B \q_int
+    connect \Y $9
+  end
+  process $group_3
+    assign \qlq_reset 1'0
+    assign \qlq_reset $9
+    sync init
+  end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.l0.l0.pick"
+module \pick
+  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75"
+  wire width 1 input 0 \i
+  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76"
+  wire width 1 output 1 \o
+  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77"
+  wire width 1 output 2 \n
+  process $group_0
+    assign \o 1'0
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82"
+    switch { \i }
+      attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82"
+      case 1'1
+        assign \o 1'0
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84"
+  wire width 1 $1
+  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84"
+  cell $eq $2
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \i
+    connect \B 1'0
+    connect \Y $1
+  end
+  process $group_1
+    assign \n 1'0
+    assign \n $1
+    sync init
+  end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.l0.l0"
+module \l0$123
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:95"
+  wire width 1 input 2 \ldst_port0_is_ld_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:96"
+  wire width 1 input 3 \ldst_port0_is_st_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99"
+  wire width 4 input 4 \ldst_port0_data_len
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 96 input 5 \ldst_port0_addr_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 input 6 \ldst_port0_addr_i_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:107"
+  wire width 1 output 7 \ldst_port0_addr_exc_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:106"
+  wire width 1 output 8 \ldst_port0_addr_ok_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 64 output 9 \ldst_port0_ld_data_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 output 10 \ldst_port0_ld_data_o_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 64 input 11 \ldst_port0_st_data_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 input 12 \ldst_port0_st_data_i_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:95"
+  wire width 1 output 13 \ldst_port0_is_ld_i$1
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102"
+  wire width 1 input 14 \ldst_port0_busy_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:96"
+  wire width 1 output 15 \ldst_port0_is_st_i$2
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99"
+  wire width 4 output 16 \ldst_port0_data_len$3
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 48 output 17 \ldst_port0_addr_i$4
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 output 18 \ldst_port0_addr_i_ok$5
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:106"
+  wire width 1 input 19 \ldst_port0_addr_ok_o$6
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 64 input 20 \ldst_port0_ld_data_o$7
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 input 21 \ldst_port0_ld_data_o_ok$8
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 output 22 \ldst_port0_st_data_i_ok$9
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 64 output 23 \ldst_port0_st_data_i$10
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:107"
+  wire width 1 input 24 \ldst_port0_addr_exc_o$11
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
+  wire width 1 \idx_l_q_idx_l
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+  wire width 1 \idx_l_s_idx_l
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+  wire width 1 \idx_l_r_idx_l
+  cell \idx_l \idx_l
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
+    connect \q_idx_l \idx_l_q_idx_l
+    connect \s_idx_l \idx_l_s_idx_l
+    connect \r_idx_l \idx_l_r_idx_l
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58"
+  wire width 1 \reset_l_s_reset
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59"
+  wire width 1 \reset_l_r_reset
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60"
+  wire width 1 \reset_l_q_reset
+  cell \reset_l$124 \reset_l
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
+    connect \s_reset \reset_l_s_reset
+    connect \r_reset \reset_l_r_reset
+    connect \q_reset \reset_l_q_reset
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75"
+  wire width 1 \pick_i
+  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76"
+  wire width 1 \pick_o
+  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77"
+  wire width 1 \pick_n
+  cell \pick \pick
+    connect \i \pick_i
+    connect \o \pick_o
+    connect \n \pick_n
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:283"
+  wire width 1 $12
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:283"
+  cell $or $13
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \ldst_port0_is_ld_i
+    connect \B \ldst_port0_is_st_i
+    connect \Y $12
+  end
+  process $group_0
+    assign \pick_i 1'0
+    assign \pick_i { $12 }
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
+  wire width 1 $14
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
+  wire width 1 \idx_l$15
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39"
+  wire width 1 \idx_l$15$next
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
+  wire width 1 $16
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40"
+  cell $mux $17
+    parameter \WIDTH 1
+    connect \A \idx_l$15
+    connect \B \pick_o
+    connect \S \idx_l_q_idx_l
+    connect \Y $16
+  end
+  connect $14 $16
+  process $group_1
+    assign { } 0'0
+    assign { } {}
+    sync init
+  end
+  process $group_2
+    assign \idx_l$15$next \idx_l$15
+    attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
+    switch { \idx_l_q_idx_l }
+      attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41"
+      case 1'1
+        assign \idx_l$15$next \pick_o
+    end
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
+      case 1'1
+        assign \idx_l$15$next 1'0
+    end
+    sync init
+      update \idx_l$15 1'0
+    sync posedge \coresync_clk
+      update \idx_l$15 \idx_l$15$next
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:299"
+  wire width 1 $18
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:299"
+  cell $not $19
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \pick_n
+    connect \Y $18
+  end
+  process $group_3
+    assign \idx_l_s_idx_l 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:299"
+    switch { $18 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:299"
+      case 1'1
+        assign \idx_l_s_idx_l 1'1
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:309"
+  wire width 1 $20
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:309"
+  cell $not $21
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \ldst_port0_busy_o
+    connect \Y $20
+  end
+  process $group_4
+    assign \reset_l_s_reset 1'0
+    assign \reset_l_s_reset 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:307"
+    switch { \idx_l_q_idx_l }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:307"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:309"
+        switch { $20 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:309"
+          case 1'1
+            assign \reset_l_s_reset 1'1
+        end
+    end
+    sync init
+  end
+  process $group_5
+    assign \reset_l_r_reset 1'1
+    assign \reset_l_r_reset 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:317"
+    switch { \reset_l_q_reset }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:317"
+      case 1'1
+        assign \reset_l_r_reset 1'1
+    end
+    sync init
+  end
+  process $group_6
+    assign \ldst_port0_is_ld_i$1 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:307"
+    switch { \idx_l_q_idx_l }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:307"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:115"
+        switch { }
+          case 0'
+            assign \ldst_port0_is_ld_i$1 \ldst_port0_is_ld_i
+        end
+    end
+    sync init
+  end
+  process $group_7
+    assign \ldst_port0_is_st_i$2 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:307"
+    switch { \idx_l_q_idx_l }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:307"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:116"
+        switch { }
+          case 0'
+            assign \ldst_port0_is_st_i$2 \ldst_port0_is_st_i
+        end
+    end
+    sync init
+  end
+  process $group_8
+    assign \ldst_port0_data_len$3 4'0000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:307"
+    switch { \idx_l_q_idx_l }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:307"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:117"
+        switch { }
+          case 0'
+            assign \ldst_port0_data_len$3 \ldst_port0_data_len
+        end
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:103"
+  wire width 1 \ldst_port0_go_die_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:103"
+  wire width 1 \ldst_port0_go_die_i$22
+  process $group_9
+    assign \ldst_port0_go_die_i 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:307"
+    switch { \idx_l_q_idx_l }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:307"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:118"
+        switch { }
+          case 0'
+            assign \ldst_port0_go_die_i \ldst_port0_go_die_i$22
+        end
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:119"
+  wire width 96 $23
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:119"
+  wire width 96 $24
+  connect $24 \ldst_port0_addr_i
+  process $group_10
+    assign \ldst_port0_addr_i$4 48'000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:307"
+    switch { \idx_l_q_idx_l }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:307"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:119"
+        switch { }
+          case 0'
+            assign \ldst_port0_addr_i$4 $24 [47:0]
+        end
+    end
+    sync init
+  end
+  process $group_11
+    assign \ldst_port0_addr_i_ok$5 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:307"
+    switch { \idx_l_q_idx_l }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:307"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:120"
+        switch { }
+          case 0'
+            assign \ldst_port0_addr_i_ok$5 \ldst_port0_addr_i_ok
+        end
+    end
+    sync init
+  end
+  process $group_12
+    assign \ldst_port0_st_data_i$10 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \ldst_port0_st_data_i_ok$9 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:307"
+    switch { \idx_l_q_idx_l }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:307"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:121"
+        switch { }
+          case 0'
+            assign { \ldst_port0_st_data_i_ok$9 \ldst_port0_st_data_i$10 } { \ldst_port0_st_data_i_ok \ldst_port0_st_data_i }
+        end
+    end
+    sync init
+  end
+  process $group_14
+    assign \ldst_port0_ld_data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \ldst_port0_ld_data_o_ok 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:307"
+    switch { \idx_l_q_idx_l }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:307"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:122"
+        switch { }
+          case 0'
+            assign { \ldst_port0_ld_data_o_ok \ldst_port0_ld_data_o } { \ldst_port0_ld_data_o_ok$8 \ldst_port0_ld_data_o$7 }
+        end
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102"
+  wire width 1 \ldst_port0_busy_o$25
+  process $group_16
+    assign \ldst_port0_busy_o$25 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:307"
+    switch { \idx_l_q_idx_l }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:307"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:123"
+        switch { }
+          case 0'
+            assign \ldst_port0_busy_o$25 \ldst_port0_busy_o
+        end
+    end
+    sync init
+  end
+  process $group_17
+    assign \ldst_port0_addr_ok_o 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:307"
+    switch { \idx_l_q_idx_l }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:307"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:124"
+        switch { }
+          case 0'
+            assign \ldst_port0_addr_ok_o \ldst_port0_addr_ok_o$6
+        end
+    end
+    sync init
+  end
+  process $group_18
+    assign \ldst_port0_addr_exc_o 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:307"
+    switch { \idx_l_q_idx_l }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:307"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:125"
+        switch { }
+          case 0'
+            assign \ldst_port0_addr_exc_o \ldst_port0_addr_exc_o$11
+        end
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:313"
+  wire width 1 \reset_delay
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:313"
+  wire width 1 \reset_delay$next
+  process $group_19
+    assign \reset_delay$next \reset_delay
+    assign \reset_delay$next \reset_l_q_reset
+    sync init
+      update \reset_delay 1'0
+    sync posedge \coresync_clk
+      update \reset_delay \reset_delay$next
+  end
+  process $group_20
+    assign \idx_l_r_idx_l 1'1
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:317"
+    switch { \reset_l_q_reset }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:317"
+      case 1'1
+        assign \idx_l_r_idx_l 1'1
+    end
+    sync init
+  end
+  connect \ldst_port0_go_die_i$22 1'0
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.l0.lsmem"
+module \lsmem
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:27"
+  wire width 8 input 2 \x_mask_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:26"
+  wire width 48 input 3 \x_addr_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:45"
+  wire width 64 output 4 \m_ld_data_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:45"
+  wire width 64 \m_ld_data_o$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:42"
+  wire width 1 output 5 \x_busy_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:30"
+  wire width 64 input 6 \x_st_data_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:28"
+  wire width 1 input 7 \x_ld_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:29"
+  wire width 1 input 8 \x_st_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:37"
+  wire width 1 input 9 \m_valid_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:33"
+  wire width 1 input 10 \x_valid_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
+  wire width 1 output 11 \dbus__cyc
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
+  wire width 1 \dbus__cyc$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
+  wire width 1 input 12 \dbus__ack
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
+  wire width 1 input 13 \dbus__err
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
+  wire width 1 output 14 \dbus__stb
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
+  wire width 1 \dbus__stb$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
+  wire width 64 input 15 \dbus__dat_r
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
+  wire width 45 output 16 \dbus__adr
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
+  wire width 45 \dbus__adr$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
+  wire width 8 output 17 \dbus__sel
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
+  wire width 8 \dbus__sel$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
+  wire width 1 output 18 \dbus__we
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
+  wire width 1 \dbus__we$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
+  wire width 64 output 19 \dbus__dat_w
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
+  wire width 64 \dbus__dat_w$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
+  wire width 1 $1
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
+  cell $or $2
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \x_ld_i
+    connect \B \x_st_i
+    connect \Y $1
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
+  wire width 1 $3
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
+  cell $and $4
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $1
+    connect \B \x_valid_i
+    connect \Y $3
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
+  wire width 1 $5
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32"
+  wire width 1 \x_stall_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
+  cell $not $6
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \x_stall_i
+    connect \Y $5
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
+  wire width 1 $7
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
+  cell $and $8
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $3
+    connect \B $5
+    connect \Y $7
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:84"
+  wire width 1 $9
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:84"
+  cell $or $10
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \dbus__ack
+    connect \B \dbus__err
+    connect \Y $9
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:84"
+  wire width 1 $11
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:84"
+  cell $not $12
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \m_valid_i
+    connect \Y $11
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:84"
+  wire width 1 $13
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:84"
+  cell $or $14
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $9
+    connect \B $11
+    connect \Y $13
+  end
+  process $group_0
+    assign \dbus__cyc$next \dbus__cyc
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:83"
+    switch { $7 \dbus__cyc }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:83"
+      case 2'-1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:84"
+        switch { $13 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:84"
+          case 1'1
+            assign \dbus__cyc$next 1'0
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
+      case 2'1-
+        assign \dbus__cyc$next 1'1
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:100"
+      case
+    end
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
+      case 1'1
+        assign \dbus__cyc$next 1'0
+    end
+    sync init
+      update \dbus__cyc 1'0
+    sync posedge \coresync_clk
+      update \dbus__cyc \dbus__cyc$next
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
+  wire width 1 $15
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
+  cell $or $16
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \x_ld_i
+    connect \B \x_st_i
+    connect \Y $15
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
+  wire width 1 $17
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
+  cell $and $18
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $15
+    connect \B \x_valid_i
+    connect \Y $17
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
+  wire width 1 $19
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
+  cell $not $20
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \x_stall_i
+    connect \Y $19
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
+  wire width 1 $21
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
+  cell $and $22
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $17
+    connect \B $19
+    connect \Y $21
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:84"
+  wire width 1 $23
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:84"
+  cell $or $24
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \dbus__ack
+    connect \B \dbus__err
+    connect \Y $23
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:84"
+  wire width 1 $25
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:84"
+  cell $not $26
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \m_valid_i
+    connect \Y $25
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:84"
+  wire width 1 $27
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:84"
+  cell $or $28
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $23
+    connect \B $25
+    connect \Y $27
+  end
+  process $group_1
+    assign \dbus__stb$next \dbus__stb
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:83"
+    switch { $21 \dbus__cyc }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:83"
+      case 2'-1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:84"
+        switch { $27 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:84"
+          case 1'1
+            assign \dbus__stb$next 1'0
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
+      case 2'1-
+        assign \dbus__stb$next 1'1
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:100"
+      case
+    end
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
+      case 1'1
+        assign \dbus__stb$next 1'0
+    end
+    sync init
+      update \dbus__stb 1'0
+    sync posedge \coresync_clk
+      update \dbus__stb \dbus__stb$next
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
+  wire width 1 $29
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
+  cell $or $30
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \x_ld_i
+    connect \B \x_st_i
+    connect \Y $29
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
+  wire width 1 $31
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
+  cell $and $32
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $29
+    connect \B \x_valid_i
+    connect \Y $31
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
+  wire width 1 $33
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
+  cell $not $34
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \x_stall_i
+    connect \Y $33
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
+  wire width 1 $35
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
+  cell $and $36
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $31
+    connect \B $33
+    connect \Y $35
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:84"
+  wire width 1 $37
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:84"
+  cell $or $38
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \dbus__ack
+    connect \B \dbus__err
+    connect \Y $37
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:84"
+  wire width 1 $39
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:84"
+  cell $not $40
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \m_valid_i
+    connect \Y $39
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:84"
+  wire width 1 $41
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:84"
+  cell $or $42
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $37
+    connect \B $39
+    connect \Y $41
+  end
+  process $group_2
+    assign \m_ld_data_o$next \m_ld_data_o
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:83"
+    switch { $35 \dbus__cyc }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:83"
+      case 2'-1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:84"
+        switch { $41 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:84"
+          case 1'1
+            assign \m_ld_data_o$next \dbus__dat_r
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
+      case 2'1-
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:100"
+      case
+    end
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
+      case 1'1
+        assign \m_ld_data_o$next 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+      update \m_ld_data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    sync posedge \coresync_clk
+      update \m_ld_data_o \m_ld_data_o$next
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
+  wire width 1 $43
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
+  cell $or $44
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \x_ld_i
+    connect \B \x_st_i
+    connect \Y $43
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
+  wire width 1 $45
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
+  cell $and $46
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $43
+    connect \B \x_valid_i
+    connect \Y $45
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
+  wire width 1 $47
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
+  cell $not $48
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \x_stall_i
+    connect \Y $47
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
+  wire width 1 $49
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
+  cell $and $50
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $45
+    connect \B $47
+    connect \Y $49
+  end
+  process $group_3
+    assign \dbus__adr$next \dbus__adr
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:83"
+    switch { $49 \dbus__cyc }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:83"
+      case 2'-1
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
+      case 2'1-
+        assign \dbus__adr$next \x_addr_i [47:3]
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:100"
+      case
+        assign \dbus__adr$next 45'000000000000000000000000000000000000000000000
+    end
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
+      case 1'1
+        assign \dbus__adr$next 45'000000000000000000000000000000000000000000000
+    end
+    sync init
+      update \dbus__adr 45'000000000000000000000000000000000000000000000
+    sync posedge \coresync_clk
+      update \dbus__adr \dbus__adr$next
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
+  wire width 1 $51
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
+  cell $or $52
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \x_ld_i
+    connect \B \x_st_i
+    connect \Y $51
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
+  wire width 1 $53
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
+  cell $and $54
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $51
+    connect \B \x_valid_i
+    connect \Y $53
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
+  wire width 1 $55
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
+  cell $not $56
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \x_stall_i
+    connect \Y $55
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
+  wire width 1 $57
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
+  cell $and $58
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $53
+    connect \B $55
+    connect \Y $57
+  end
+  process $group_4
+    assign \dbus__sel$next \dbus__sel
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:83"
+    switch { $57 \dbus__cyc }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:83"
+      case 2'-1
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
+      case 2'1-
+        assign \dbus__sel$next \x_mask_i
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:100"
+      case
+        assign \dbus__sel$next 8'00000000
+        assign \dbus__sel$next 8'00000000
+    end
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
+      case 1'1
+        assign \dbus__sel$next 8'00000000
+    end
+    sync init
+      update \dbus__sel 8'00000000
+    sync posedge \coresync_clk
+      update \dbus__sel \dbus__sel$next
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
+  wire width 1 $59
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
+  cell $or $60
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \x_ld_i
+    connect \B \x_st_i
+    connect \Y $59
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
+  wire width 1 $61
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
+  cell $and $62
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $59
+    connect \B \x_valid_i
+    connect \Y $61
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
+  wire width 1 $63
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
+  cell $not $64
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \x_stall_i
+    connect \Y $63
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
+  wire width 1 $65
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
+  cell $and $66
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $61
+    connect \B $63
+    connect \Y $65
+  end
+  process $group_5
+    assign \dbus__we$next \dbus__we
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:83"
+    switch { $65 \dbus__cyc }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:83"
+      case 2'-1
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
+      case 2'1-
+        assign \dbus__we$next \x_st_i
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:100"
+      case
+        assign \dbus__we$next 1'0
+    end
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
+      case 1'1
+        assign \dbus__we$next 1'0
+    end
+    sync init
+      update \dbus__we 1'0
+    sync posedge \coresync_clk
+      update \dbus__we \dbus__we$next
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
+  wire width 1 $67
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
+  cell $or $68
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \x_ld_i
+    connect \B \x_st_i
+    connect \Y $67
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
+  wire width 1 $69
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
+  cell $and $70
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $67
+    connect \B \x_valid_i
+    connect \Y $69
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
+  wire width 1 $71
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
+  cell $not $72
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \x_stall_i
+    connect \Y $71
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
+  wire width 1 $73
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
+  cell $and $74
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $69
+    connect \B $71
+    connect \Y $73
+  end
+  process $group_6
+    assign \dbus__dat_w$next \dbus__dat_w
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:83"
+    switch { $73 \dbus__cyc }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:83"
+      case 2'-1
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:91"
+      case 2'1-
+        assign \dbus__dat_w$next \x_st_data_i
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:100"
+      case
+        assign \dbus__dat_w$next 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
+      case 1'1
+        assign \dbus__dat_w$next 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+      update \dbus__dat_w 64'0000000000000000000000000000000000000000000000000000000000000000
+    sync posedge \coresync_clk
+      update \dbus__dat_w \dbus__dat_w$next
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:50"
+  wire width 1 \m_load_err_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:50"
+  wire width 1 \m_load_err_o$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:109"
+  wire width 1 $75
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:109"
+  cell $and $76
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \dbus__cyc
+    connect \B \dbus__err
+    connect \Y $75
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:115"
+  wire width 1 $77
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:36"
+  wire width 1 \m_stall_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:115"
+  cell $not $78
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \m_stall_i
+    connect \Y $77
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111"
+  wire width 1 $79
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:111"
+  cell $not $80
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \dbus__we
+    connect \Y $79
+  end
+  process $group_7
+    assign \m_load_err_o$next \m_load_err_o
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:109"
+    switch { $77 $75 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:109"
+      case 2'-1
+        assign \m_load_err_o$next $79
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:115"
+      case 2'1-
+        assign \m_load_err_o$next 1'0
+    end
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
+      case 1'1
+        assign \m_load_err_o$next 1'0
+    end
+    sync init
+      update \m_load_err_o 1'0
+    sync posedge \coresync_clk
+      update \m_load_err_o \m_load_err_o$next
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:51"
+  wire width 1 \m_store_err_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:51"
+  wire width 1 \m_store_err_o$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:109"
+  wire width 1 $81
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:109"
+  cell $and $82
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \dbus__cyc
+    connect \B \dbus__err
+    connect \Y $81
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:115"
+  wire width 1 $83
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:115"
+  cell $not $84
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \m_stall_i
+    connect \Y $83
+  end
+  process $group_8
+    assign \m_store_err_o$next \m_store_err_o
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:109"
+    switch { $83 $81 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:109"
+      case 2'-1
+        assign \m_store_err_o$next \dbus__we
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:115"
+      case 2'1-
+        assign \m_store_err_o$next 1'0
+    end
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
+      case 1'1
+        assign \m_store_err_o$next 1'0
+    end
+    sync init
+      update \m_store_err_o 1'0
+    sync posedge \coresync_clk
+      update \m_store_err_o \m_store_err_o$next
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:53"
+  wire width 45 \m_badaddr_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:53"
+  wire width 45 \m_badaddr_o$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:109"
+  wire width 1 $85
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:109"
+  cell $and $86
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \dbus__cyc
+    connect \B \dbus__err
+    connect \Y $85
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:115"
+  wire width 1 $87
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:115"
+  cell $not $88
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \m_stall_i
+    connect \Y $87
+  end
+  process $group_9
+    assign \m_badaddr_o$next \m_badaddr_o
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:109"
+    switch { $87 $85 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:109"
+      case 2'-1
+        assign \m_badaddr_o$next \dbus__adr
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:115"
+      case 2'1-
+    end
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
+      case 1'1
+        assign \m_badaddr_o$next 45'000000000000000000000000000000000000000000000
+    end
+    sync init
+      update \m_badaddr_o 45'000000000000000000000000000000000000000000000
+    sync posedge \coresync_clk
+      update \m_badaddr_o \m_badaddr_o$next
+  end
+  process $group_10
+    assign \x_busy_o 1'0
+    assign \x_busy_o \dbus__cyc
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:43"
+  wire width 1 \m_busy_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:123"
+  wire width 1 $89
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:123"
+  cell $or $90
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \m_load_err_o
+    connect \B \m_store_err_o
+    connect \Y $89
+  end
+  process $group_11
+    assign \m_busy_o 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:123"
+    switch { $89 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:123"
+      case 1'1
+        assign \m_busy_o 1'0
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:125"
+      case
+        assign \m_busy_o \dbus__cyc
+    end
+    sync init
+  end
+  connect \x_stall_i 1'0
+  connect \m_stall_i 1'0
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.l0"
+module \l0
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:95"
+  wire width 1 input 2 \ldst_port0_is_ld_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:96"
+  wire width 1 input 3 \ldst_port0_is_st_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99"
+  wire width 4 input 4 \ldst_port0_data_len
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 96 input 5 \ldst_port0_addr_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 input 6 \ldst_port0_addr_i_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:107"
+  wire width 1 output 7 \ldst_port0_addr_exc_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:106"
+  wire width 1 output 8 \ldst_port0_addr_ok_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 64 output 9 \ldst_port0_ld_data_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 output 10 \ldst_port0_ld_data_o_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 64 input 11 \ldst_port0_st_data_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 input 12 \ldst_port0_st_data_i_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
+  wire width 1 output 13 \dbus__cyc
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
+  wire width 1 input 14 \dbus__ack
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
+  wire width 1 input 15 \dbus__err
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
+  wire width 1 output 16 \dbus__stb
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
+  wire width 64 input 17 \dbus__dat_r
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
+  wire width 45 output 18 \dbus__adr
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
+  wire width 8 output 19 \dbus__sel
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
+  wire width 1 output 20 \dbus__we
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
+  wire width 64 output 21 \dbus__dat_w
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:95"
+  wire width 1 \pimem_ldst_port0_is_ld_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102"
+  wire width 1 \pimem_ldst_port0_busy_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:96"
+  wire width 1 \pimem_ldst_port0_is_st_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99"
+  wire width 4 \pimem_ldst_port0_data_len
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 48 \pimem_ldst_port0_addr_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 \pimem_ldst_port0_addr_i_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:27"
+  wire width 8 \pimem_x_mask_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:26"
+  wire width 48 \pimem_x_addr_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:106"
+  wire width 1 \pimem_ldst_port0_addr_ok_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:45"
+  wire width 64 \pimem_m_ld_data_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 64 \pimem_ldst_port0_ld_data_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 \pimem_ldst_port0_ld_data_o_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:42"
+  wire width 1 \pimem_x_busy_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 \pimem_ldst_port0_st_data_i_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 64 \pimem_ldst_port0_st_data_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:30"
+  wire width 64 \pimem_x_st_data_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:107"
+  wire width 1 \pimem_ldst_port0_addr_exc_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:28"
+  wire width 1 \pimem_x_ld_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:29"
+  wire width 1 \pimem_x_st_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:37"
+  wire width 1 \pimem_m_valid_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:33"
+  wire width 1 \pimem_x_valid_i
+  cell \pimem \pimem
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
+    connect \ldst_port0_is_ld_i \pimem_ldst_port0_is_ld_i
+    connect \ldst_port0_busy_o \pimem_ldst_port0_busy_o
+    connect \ldst_port0_is_st_i \pimem_ldst_port0_is_st_i
+    connect \ldst_port0_data_len \pimem_ldst_port0_data_len
+    connect \ldst_port0_addr_i \pimem_ldst_port0_addr_i
+    connect \ldst_port0_addr_i_ok \pimem_ldst_port0_addr_i_ok
+    connect \x_mask_i \pimem_x_mask_i
+    connect \x_addr_i \pimem_x_addr_i
+    connect \ldst_port0_addr_ok_o \pimem_ldst_port0_addr_ok_o
+    connect \m_ld_data_o \pimem_m_ld_data_o
+    connect \ldst_port0_ld_data_o \pimem_ldst_port0_ld_data_o
+    connect \ldst_port0_ld_data_o_ok \pimem_ldst_port0_ld_data_o_ok
+    connect \x_busy_o \pimem_x_busy_o
+    connect \ldst_port0_st_data_i_ok \pimem_ldst_port0_st_data_i_ok
+    connect \ldst_port0_st_data_i \pimem_ldst_port0_st_data_i
+    connect \x_st_data_i \pimem_x_st_data_i
+    connect \ldst_port0_addr_exc_o \pimem_ldst_port0_addr_exc_o
+    connect \x_ld_i \pimem_x_ld_i
+    connect \x_st_i \pimem_x_st_i
+    connect \m_valid_i \pimem_m_valid_i
+    connect \x_valid_i \pimem_x_valid_i
+  end
+  cell \l0$123 \l0
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
+    connect \ldst_port0_is_ld_i \ldst_port0_is_ld_i
+    connect \ldst_port0_is_st_i \ldst_port0_is_st_i
+    connect \ldst_port0_data_len \ldst_port0_data_len
+    connect \ldst_port0_addr_i \ldst_port0_addr_i
+    connect \ldst_port0_addr_i_ok \ldst_port0_addr_i_ok
+    connect \ldst_port0_addr_exc_o \ldst_port0_addr_exc_o
+    connect \ldst_port0_addr_ok_o \ldst_port0_addr_ok_o
+    connect \ldst_port0_ld_data_o \ldst_port0_ld_data_o
+    connect \ldst_port0_ld_data_o_ok \ldst_port0_ld_data_o_ok
+    connect \ldst_port0_st_data_i \ldst_port0_st_data_i
+    connect \ldst_port0_st_data_i_ok \ldst_port0_st_data_i_ok
+    connect \ldst_port0_is_ld_i$1 \pimem_ldst_port0_is_ld_i
+    connect \ldst_port0_busy_o \pimem_ldst_port0_busy_o
+    connect \ldst_port0_is_st_i$2 \pimem_ldst_port0_is_st_i
+    connect \ldst_port0_data_len$3 \pimem_ldst_port0_data_len
+    connect \ldst_port0_addr_i$4 \pimem_ldst_port0_addr_i
+    connect \ldst_port0_addr_i_ok$5 \pimem_ldst_port0_addr_i_ok
+    connect \ldst_port0_addr_ok_o$6 \pimem_ldst_port0_addr_ok_o
+    connect \ldst_port0_ld_data_o$7 \pimem_ldst_port0_ld_data_o
+    connect \ldst_port0_ld_data_o_ok$8 \pimem_ldst_port0_ld_data_o_ok
+    connect \ldst_port0_st_data_i_ok$9 \pimem_ldst_port0_st_data_i_ok
+    connect \ldst_port0_st_data_i$10 \pimem_ldst_port0_st_data_i
+    connect \ldst_port0_addr_exc_o$11 \pimem_ldst_port0_addr_exc_o
+  end
+  cell \lsmem \lsmem
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
+    connect \x_mask_i \pimem_x_mask_i
+    connect \x_addr_i \pimem_x_addr_i
+    connect \m_ld_data_o \pimem_m_ld_data_o
+    connect \x_busy_o \pimem_x_busy_o
+    connect \x_st_data_i \pimem_x_st_data_i
+    connect \x_ld_i \pimem_x_ld_i
+    connect \x_st_i \pimem_x_st_i
+    connect \m_valid_i \pimem_m_valid_i
+    connect \x_valid_i \pimem_x_valid_i
+    connect \dbus__cyc \dbus__cyc
+    connect \dbus__ack \dbus__ack
+    connect \dbus__err \dbus__err
+    connect \dbus__stb \dbus__stb
+    connect \dbus__dat_r \dbus__dat_r
+    connect \dbus__adr \dbus__adr
+    connect \dbus__sel \dbus__sel
+    connect \dbus__we \dbus__we
+    connect \dbus__dat_w \dbus__dat_w
+  end
+  connect \pimem_ldst_port0_addr_exc_o 1'0
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.int.reg_0"
+module \reg_0
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 2 \src10__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 3 \src10__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 4 \src20__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 5 \src20__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 6 \src30__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 7 \src30__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 8 \dmi0__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 9 \dmi0__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 10 \dest10__wen
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 input 11 \dest10__data_i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 12 \dest20__wen
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 input 13 \dest20__data_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+  wire width 1 \wr_detect
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $1
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $2
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src10__ren
+    connect \B 1'1
+    connect \Y $1
+  end
+  process $group_0
+    assign \wr_detect 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $1 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        assign \wr_detect 1'0
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest10__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect 1'1
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest20__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect 1'1
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $3
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $4
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src10__ren
+    connect \B 1'1
+    connect \Y $3
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  wire width 1 $5
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  cell $not $6
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_detect
+    connect \Y $5
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
+  wire width 64 \reg
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
+  wire width 64 \reg$next
+  process $group_1
+    assign \src10__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $3 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest10__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src10__data_o \dest10__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest20__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src10__data_o \dest20__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+        switch { $5 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+          case 1'1
+            assign \src10__data_o \reg
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+        assign \src10__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+  wire width 1 \wr_detect$7
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $8
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $9
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src20__ren
+    connect \B 1'1
+    connect \Y $8
+  end
+  process $group_2
+    assign \wr_detect$7 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $8 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        assign \wr_detect$7 1'0
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest10__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$7 1'1
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest20__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$7 1'1
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $10
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $11
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src20__ren
+    connect \B 1'1
+    connect \Y $10
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  wire width 1 $12
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  cell $not $13
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_detect$7
+    connect \Y $12
+  end
+  process $group_3
+    assign \src20__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $10 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest10__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src20__data_o \dest10__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest20__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src20__data_o \dest20__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+        switch { $12 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+          case 1'1
+            assign \src20__data_o \reg
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+        assign \src20__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+  wire width 1 \wr_detect$14
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $15
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $16
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src30__ren
+    connect \B 1'1
+    connect \Y $15
+  end
+  process $group_4
+    assign \wr_detect$14 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $15 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        assign \wr_detect$14 1'0
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest10__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$14 1'1
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest20__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$14 1'1
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $17
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $18
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src30__ren
+    connect \B 1'1
+    connect \Y $17
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  wire width 1 $19
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  cell $not $20
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_detect$14
+    connect \Y $19
+  end
+  process $group_5
+    assign \src30__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $17 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest10__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src30__data_o \dest10__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest20__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src30__data_o \dest20__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+        switch { $19 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+          case 1'1
+            assign \src30__data_o \reg
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+        assign \src30__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+  wire width 1 \wr_detect$21
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $22
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $23
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \dmi0__ren
+    connect \B 1'1
+    connect \Y $22
+  end
+  process $group_6
+    assign \wr_detect$21 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $22 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        assign \wr_detect$21 1'0
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest10__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$21 1'1
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest20__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$21 1'1
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $24
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $25
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \dmi0__ren
+    connect \B 1'1
+    connect \Y $24
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  wire width 1 $26
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  cell $not $27
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_detect$21
+    connect \Y $26
+  end
+  process $group_7
+    assign \dmi0__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $24 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest10__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \dmi0__data_o \dest10__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest20__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \dmi0__data_o \dest20__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+        switch { $26 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+          case 1'1
+            assign \dmi0__data_o \reg
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+        assign \dmi0__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+  end
+  process $group_8
+    assign \reg$next \reg
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+    switch { \dest10__wen }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+      case 1'1
+        assign \reg$next \dest10__data_i
+    end
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+    switch { \dest20__wen }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+      case 1'1
+        assign \reg$next \dest20__data_i
+    end
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
+      case 1'1
+        assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+      update \reg 64'0000000000000000000000000000000000000000000000000000000000000000
+    sync posedge \coresync_clk
+      update \reg \reg$next
+  end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.int.reg_1"
+module \reg_1
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 2 \src11__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 3 \src11__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 4 \src21__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 5 \src21__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 6 \src31__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 7 \src31__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 8 \dmi1__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 9 \dmi1__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 10 \dest11__wen
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 input 11 \dest11__data_i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 12 \dest21__wen
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 input 13 \dest21__data_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+  wire width 1 \wr_detect
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $1
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $2
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src11__ren
+    connect \B 1'1
+    connect \Y $1
+  end
+  process $group_0
+    assign \wr_detect 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $1 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        assign \wr_detect 1'0
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest11__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect 1'1
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest21__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect 1'1
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $3
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $4
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src11__ren
+    connect \B 1'1
+    connect \Y $3
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  wire width 1 $5
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  cell $not $6
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_detect
+    connect \Y $5
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
+  wire width 64 \reg
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
+  wire width 64 \reg$next
+  process $group_1
+    assign \src11__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $3 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest11__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src11__data_o \dest11__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest21__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src11__data_o \dest21__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+        switch { $5 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+          case 1'1
+            assign \src11__data_o \reg
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+        assign \src11__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+  wire width 1 \wr_detect$7
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $8
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $9
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src21__ren
+    connect \B 1'1
+    connect \Y $8
+  end
+  process $group_2
+    assign \wr_detect$7 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $8 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        assign \wr_detect$7 1'0
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest11__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$7 1'1
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest21__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$7 1'1
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $10
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $11
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src21__ren
+    connect \B 1'1
+    connect \Y $10
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  wire width 1 $12
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  cell $not $13
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_detect$7
+    connect \Y $12
+  end
+  process $group_3
+    assign \src21__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $10 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest11__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src21__data_o \dest11__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest21__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src21__data_o \dest21__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+        switch { $12 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+          case 1'1
+            assign \src21__data_o \reg
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+        assign \src21__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+  wire width 1 \wr_detect$14
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $15
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $16
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src31__ren
+    connect \B 1'1
+    connect \Y $15
+  end
+  process $group_4
+    assign \wr_detect$14 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $15 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        assign \wr_detect$14 1'0
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest11__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$14 1'1
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest21__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$14 1'1
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $17
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $18
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src31__ren
+    connect \B 1'1
+    connect \Y $17
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  wire width 1 $19
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  cell $not $20
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_detect$14
+    connect \Y $19
+  end
+  process $group_5
+    assign \src31__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $17 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest11__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src31__data_o \dest11__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest21__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src31__data_o \dest21__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+        switch { $19 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+          case 1'1
+            assign \src31__data_o \reg
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+        assign \src31__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+  wire width 1 \wr_detect$21
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $22
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $23
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \dmi1__ren
+    connect \B 1'1
+    connect \Y $22
+  end
+  process $group_6
+    assign \wr_detect$21 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $22 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        assign \wr_detect$21 1'0
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest11__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$21 1'1
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest21__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$21 1'1
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $24
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $25
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \dmi1__ren
+    connect \B 1'1
+    connect \Y $24
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  wire width 1 $26
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  cell $not $27
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_detect$21
+    connect \Y $26
+  end
+  process $group_7
+    assign \dmi1__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $24 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest11__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \dmi1__data_o \dest11__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest21__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \dmi1__data_o \dest21__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+        switch { $26 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+          case 1'1
+            assign \dmi1__data_o \reg
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+        assign \dmi1__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+  end
+  process $group_8
+    assign \reg$next \reg
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+    switch { \dest11__wen }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+      case 1'1
+        assign \reg$next \dest11__data_i
+    end
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+    switch { \dest21__wen }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+      case 1'1
+        assign \reg$next \dest21__data_i
+    end
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
+      case 1'1
+        assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+      update \reg 64'0000000000000000000000000000000000000000000000000000000000000000
+    sync posedge \coresync_clk
+      update \reg \reg$next
+  end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.int.reg_2"
+module \reg_2
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 2 \src12__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 3 \src12__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 4 \src22__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 5 \src22__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 6 \src32__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 7 \src32__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 8 \dmi2__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 9 \dmi2__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 10 \dest12__wen
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 input 11 \dest12__data_i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 12 \dest22__wen
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 input 13 \dest22__data_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+  wire width 1 \wr_detect
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $1
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $2
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src12__ren
+    connect \B 1'1
+    connect \Y $1
+  end
+  process $group_0
+    assign \wr_detect 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $1 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        assign \wr_detect 1'0
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest12__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect 1'1
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest22__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect 1'1
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $3
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $4
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src12__ren
+    connect \B 1'1
+    connect \Y $3
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  wire width 1 $5
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  cell $not $6
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_detect
+    connect \Y $5
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
+  wire width 64 \reg
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
+  wire width 64 \reg$next
+  process $group_1
+    assign \src12__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $3 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest12__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src12__data_o \dest12__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest22__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src12__data_o \dest22__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+        switch { $5 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+          case 1'1
+            assign \src12__data_o \reg
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+        assign \src12__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+  wire width 1 \wr_detect$7
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $8
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $9
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src22__ren
+    connect \B 1'1
+    connect \Y $8
+  end
+  process $group_2
+    assign \wr_detect$7 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $8 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        assign \wr_detect$7 1'0
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest12__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$7 1'1
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest22__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$7 1'1
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $10
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $11
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src22__ren
+    connect \B 1'1
+    connect \Y $10
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  wire width 1 $12
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  cell $not $13
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_detect$7
+    connect \Y $12
+  end
+  process $group_3
+    assign \src22__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $10 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest12__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src22__data_o \dest12__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest22__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src22__data_o \dest22__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+        switch { $12 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+          case 1'1
+            assign \src22__data_o \reg
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+        assign \src22__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+  wire width 1 \wr_detect$14
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $15
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $16
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src32__ren
+    connect \B 1'1
+    connect \Y $15
+  end
+  process $group_4
+    assign \wr_detect$14 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $15 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        assign \wr_detect$14 1'0
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest12__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$14 1'1
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest22__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$14 1'1
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $17
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $18
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src32__ren
+    connect \B 1'1
+    connect \Y $17
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  wire width 1 $19
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  cell $not $20
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_detect$14
+    connect \Y $19
+  end
+  process $group_5
+    assign \src32__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $17 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest12__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src32__data_o \dest12__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest22__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src32__data_o \dest22__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+        switch { $19 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+          case 1'1
+            assign \src32__data_o \reg
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+        assign \src32__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+  wire width 1 \wr_detect$21
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $22
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $23
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \dmi2__ren
+    connect \B 1'1
+    connect \Y $22
+  end
+  process $group_6
+    assign \wr_detect$21 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $22 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        assign \wr_detect$21 1'0
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest12__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$21 1'1
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest22__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$21 1'1
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $24
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $25
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \dmi2__ren
+    connect \B 1'1
+    connect \Y $24
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  wire width 1 $26
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  cell $not $27
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_detect$21
+    connect \Y $26
+  end
+  process $group_7
+    assign \dmi2__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $24 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest12__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \dmi2__data_o \dest12__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest22__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \dmi2__data_o \dest22__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+        switch { $26 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+          case 1'1
+            assign \dmi2__data_o \reg
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+        assign \dmi2__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+  end
+  process $group_8
+    assign \reg$next \reg
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+    switch { \dest12__wen }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+      case 1'1
+        assign \reg$next \dest12__data_i
+    end
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+    switch { \dest22__wen }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+      case 1'1
+        assign \reg$next \dest22__data_i
+    end
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
+      case 1'1
+        assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+      update \reg 64'0000000000000000000000000000000000000000000000000000000000000000
+    sync posedge \coresync_clk
+      update \reg \reg$next
+  end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.int.reg_3"
+module \reg_3
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 2 \src13__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 3 \src13__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 4 \src23__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 5 \src23__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 6 \src33__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 7 \src33__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 8 \dmi3__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 9 \dmi3__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 10 \dest13__wen
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 input 11 \dest13__data_i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 12 \dest23__wen
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 input 13 \dest23__data_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+  wire width 1 \wr_detect
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $1
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $2
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src13__ren
+    connect \B 1'1
+    connect \Y $1
+  end
+  process $group_0
+    assign \wr_detect 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $1 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        assign \wr_detect 1'0
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest13__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect 1'1
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest23__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect 1'1
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $3
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $4
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src13__ren
+    connect \B 1'1
+    connect \Y $3
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  wire width 1 $5
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  cell $not $6
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_detect
+    connect \Y $5
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
+  wire width 64 \reg
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
+  wire width 64 \reg$next
+  process $group_1
+    assign \src13__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $3 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest13__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src13__data_o \dest13__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest23__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src13__data_o \dest23__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+        switch { $5 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+          case 1'1
+            assign \src13__data_o \reg
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+        assign \src13__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+  wire width 1 \wr_detect$7
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $8
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $9
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src23__ren
+    connect \B 1'1
+    connect \Y $8
+  end
+  process $group_2
+    assign \wr_detect$7 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $8 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        assign \wr_detect$7 1'0
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest13__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$7 1'1
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest23__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$7 1'1
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $10
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $11
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src23__ren
+    connect \B 1'1
+    connect \Y $10
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  wire width 1 $12
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  cell $not $13
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_detect$7
+    connect \Y $12
+  end
+  process $group_3
+    assign \src23__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $10 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest13__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src23__data_o \dest13__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest23__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src23__data_o \dest23__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+        switch { $12 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+          case 1'1
+            assign \src23__data_o \reg
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+        assign \src23__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+  wire width 1 \wr_detect$14
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $15
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $16
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src33__ren
+    connect \B 1'1
+    connect \Y $15
+  end
+  process $group_4
+    assign \wr_detect$14 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $15 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        assign \wr_detect$14 1'0
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest13__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$14 1'1
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest23__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$14 1'1
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $17
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $18
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src33__ren
+    connect \B 1'1
+    connect \Y $17
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  wire width 1 $19
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  cell $not $20
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_detect$14
+    connect \Y $19
+  end
+  process $group_5
+    assign \src33__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $17 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest13__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src33__data_o \dest13__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest23__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src33__data_o \dest23__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+        switch { $19 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+          case 1'1
+            assign \src33__data_o \reg
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+        assign \src33__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+  wire width 1 \wr_detect$21
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $22
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $23
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \dmi3__ren
+    connect \B 1'1
+    connect \Y $22
+  end
+  process $group_6
+    assign \wr_detect$21 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $22 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        assign \wr_detect$21 1'0
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest13__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$21 1'1
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest23__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$21 1'1
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $24
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $25
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \dmi3__ren
+    connect \B 1'1
+    connect \Y $24
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  wire width 1 $26
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  cell $not $27
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_detect$21
+    connect \Y $26
+  end
+  process $group_7
+    assign \dmi3__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $24 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest13__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \dmi3__data_o \dest13__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest23__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \dmi3__data_o \dest23__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+        switch { $26 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+          case 1'1
+            assign \dmi3__data_o \reg
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+        assign \dmi3__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+  end
+  process $group_8
+    assign \reg$next \reg
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+    switch { \dest13__wen }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+      case 1'1
+        assign \reg$next \dest13__data_i
+    end
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+    switch { \dest23__wen }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+      case 1'1
+        assign \reg$next \dest23__data_i
+    end
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
+      case 1'1
+        assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+      update \reg 64'0000000000000000000000000000000000000000000000000000000000000000
+    sync posedge \coresync_clk
+      update \reg \reg$next
+  end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.int.reg_4"
+module \reg_4
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 2 \src14__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 3 \src14__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 4 \src24__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 5 \src24__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 6 \src34__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 7 \src34__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 8 \dmi4__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 9 \dmi4__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 10 \dest14__wen
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 input 11 \dest14__data_i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 12 \dest24__wen
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 input 13 \dest24__data_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+  wire width 1 \wr_detect
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $1
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $2
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src14__ren
+    connect \B 1'1
+    connect \Y $1
+  end
+  process $group_0
+    assign \wr_detect 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $1 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        assign \wr_detect 1'0
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest14__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect 1'1
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest24__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect 1'1
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $3
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $4
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src14__ren
+    connect \B 1'1
+    connect \Y $3
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  wire width 1 $5
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  cell $not $6
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_detect
+    connect \Y $5
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
+  wire width 64 \reg
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
+  wire width 64 \reg$next
+  process $group_1
+    assign \src14__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $3 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest14__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src14__data_o \dest14__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest24__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src14__data_o \dest24__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+        switch { $5 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+          case 1'1
+            assign \src14__data_o \reg
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+        assign \src14__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+  wire width 1 \wr_detect$7
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $8
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $9
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src24__ren
+    connect \B 1'1
+    connect \Y $8
+  end
+  process $group_2
+    assign \wr_detect$7 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $8 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        assign \wr_detect$7 1'0
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest14__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$7 1'1
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest24__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$7 1'1
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $10
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $11
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src24__ren
+    connect \B 1'1
+    connect \Y $10
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  wire width 1 $12
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  cell $not $13
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_detect$7
+    connect \Y $12
+  end
+  process $group_3
+    assign \src24__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $10 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest14__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src24__data_o \dest14__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest24__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src24__data_o \dest24__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+        switch { $12 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+          case 1'1
+            assign \src24__data_o \reg
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+        assign \src24__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+  wire width 1 \wr_detect$14
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $15
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $16
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src34__ren
+    connect \B 1'1
+    connect \Y $15
+  end
+  process $group_4
+    assign \wr_detect$14 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $15 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        assign \wr_detect$14 1'0
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest14__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$14 1'1
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest24__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$14 1'1
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $17
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $18
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src34__ren
+    connect \B 1'1
+    connect \Y $17
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  wire width 1 $19
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  cell $not $20
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_detect$14
+    connect \Y $19
+  end
+  process $group_5
+    assign \src34__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $17 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest14__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src34__data_o \dest14__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest24__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src34__data_o \dest24__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+        switch { $19 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+          case 1'1
+            assign \src34__data_o \reg
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+        assign \src34__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+  wire width 1 \wr_detect$21
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $22
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $23
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \dmi4__ren
+    connect \B 1'1
+    connect \Y $22
+  end
+  process $group_6
+    assign \wr_detect$21 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $22 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        assign \wr_detect$21 1'0
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest14__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$21 1'1
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest24__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$21 1'1
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $24
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $25
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \dmi4__ren
+    connect \B 1'1
+    connect \Y $24
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  wire width 1 $26
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  cell $not $27
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_detect$21
+    connect \Y $26
+  end
+  process $group_7
+    assign \dmi4__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $24 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest14__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \dmi4__data_o \dest14__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest24__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \dmi4__data_o \dest24__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+        switch { $26 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+          case 1'1
+            assign \dmi4__data_o \reg
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+        assign \dmi4__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+  end
+  process $group_8
+    assign \reg$next \reg
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+    switch { \dest14__wen }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+      case 1'1
+        assign \reg$next \dest14__data_i
+    end
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+    switch { \dest24__wen }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+      case 1'1
+        assign \reg$next \dest24__data_i
+    end
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
+      case 1'1
+        assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+      update \reg 64'0000000000000000000000000000000000000000000000000000000000000000
+    sync posedge \coresync_clk
+      update \reg \reg$next
+  end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.int.reg_5"
+module \reg_5
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 2 \src15__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 3 \src15__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 4 \src25__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 5 \src25__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 6 \src35__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 7 \src35__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 8 \dmi5__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 9 \dmi5__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 10 \dest15__wen
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 input 11 \dest15__data_i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 12 \dest25__wen
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 input 13 \dest25__data_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+  wire width 1 \wr_detect
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $1
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $2
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src15__ren
+    connect \B 1'1
+    connect \Y $1
+  end
+  process $group_0
+    assign \wr_detect 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $1 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        assign \wr_detect 1'0
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest15__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect 1'1
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest25__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect 1'1
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $3
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $4
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src15__ren
+    connect \B 1'1
+    connect \Y $3
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  wire width 1 $5
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  cell $not $6
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_detect
+    connect \Y $5
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
+  wire width 64 \reg
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
+  wire width 64 \reg$next
+  process $group_1
+    assign \src15__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $3 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest15__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src15__data_o \dest15__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest25__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src15__data_o \dest25__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+        switch { $5 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+          case 1'1
+            assign \src15__data_o \reg
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+        assign \src15__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+  wire width 1 \wr_detect$7
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $8
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $9
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src25__ren
+    connect \B 1'1
+    connect \Y $8
+  end
+  process $group_2
+    assign \wr_detect$7 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $8 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        assign \wr_detect$7 1'0
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest15__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$7 1'1
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest25__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$7 1'1
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $10
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $11
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src25__ren
+    connect \B 1'1
+    connect \Y $10
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  wire width 1 $12
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  cell $not $13
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_detect$7
+    connect \Y $12
+  end
+  process $group_3
+    assign \src25__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $10 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest15__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src25__data_o \dest15__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest25__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src25__data_o \dest25__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+        switch { $12 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+          case 1'1
+            assign \src25__data_o \reg
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+        assign \src25__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+  wire width 1 \wr_detect$14
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $15
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $16
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src35__ren
+    connect \B 1'1
+    connect \Y $15
+  end
+  process $group_4
+    assign \wr_detect$14 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $15 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        assign \wr_detect$14 1'0
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest15__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$14 1'1
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest25__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$14 1'1
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $17
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $18
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src35__ren
+    connect \B 1'1
+    connect \Y $17
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  wire width 1 $19
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  cell $not $20
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_detect$14
+    connect \Y $19
+  end
+  process $group_5
+    assign \src35__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $17 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest15__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src35__data_o \dest15__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest25__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src35__data_o \dest25__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+        switch { $19 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+          case 1'1
+            assign \src35__data_o \reg
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+        assign \src35__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+  wire width 1 \wr_detect$21
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $22
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $23
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \dmi5__ren
+    connect \B 1'1
+    connect \Y $22
+  end
+  process $group_6
+    assign \wr_detect$21 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $22 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        assign \wr_detect$21 1'0
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest15__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$21 1'1
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest25__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$21 1'1
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $24
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $25
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \dmi5__ren
+    connect \B 1'1
+    connect \Y $24
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  wire width 1 $26
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  cell $not $27
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_detect$21
+    connect \Y $26
+  end
+  process $group_7
+    assign \dmi5__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $24 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest15__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \dmi5__data_o \dest15__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest25__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \dmi5__data_o \dest25__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+        switch { $26 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+          case 1'1
+            assign \dmi5__data_o \reg
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+        assign \dmi5__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+  end
+  process $group_8
+    assign \reg$next \reg
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+    switch { \dest15__wen }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+      case 1'1
+        assign \reg$next \dest15__data_i
+    end
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+    switch { \dest25__wen }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+      case 1'1
+        assign \reg$next \dest25__data_i
+    end
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
+      case 1'1
+        assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+      update \reg 64'0000000000000000000000000000000000000000000000000000000000000000
+    sync posedge \coresync_clk
+      update \reg \reg$next
+  end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.int.reg_6"
+module \reg_6
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 2 \src16__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 3 \src16__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 4 \src26__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 5 \src26__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 6 \src36__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 7 \src36__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 8 \dmi6__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 9 \dmi6__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 10 \dest16__wen
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 input 11 \dest16__data_i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 12 \dest26__wen
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 input 13 \dest26__data_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+  wire width 1 \wr_detect
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $1
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $2
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src16__ren
+    connect \B 1'1
+    connect \Y $1
+  end
+  process $group_0
+    assign \wr_detect 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $1 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        assign \wr_detect 1'0
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest16__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect 1'1
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest26__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect 1'1
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $3
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $4
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src16__ren
+    connect \B 1'1
+    connect \Y $3
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  wire width 1 $5
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  cell $not $6
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_detect
+    connect \Y $5
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
+  wire width 64 \reg
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
+  wire width 64 \reg$next
+  process $group_1
+    assign \src16__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $3 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest16__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src16__data_o \dest16__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest26__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src16__data_o \dest26__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+        switch { $5 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+          case 1'1
+            assign \src16__data_o \reg
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+        assign \src16__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+  wire width 1 \wr_detect$7
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $8
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $9
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src26__ren
+    connect \B 1'1
+    connect \Y $8
+  end
+  process $group_2
+    assign \wr_detect$7 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $8 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        assign \wr_detect$7 1'0
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest16__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$7 1'1
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest26__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$7 1'1
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $10
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $11
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src26__ren
+    connect \B 1'1
+    connect \Y $10
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  wire width 1 $12
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  cell $not $13
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_detect$7
+    connect \Y $12
+  end
+  process $group_3
+    assign \src26__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $10 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest16__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src26__data_o \dest16__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest26__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src26__data_o \dest26__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+        switch { $12 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+          case 1'1
+            assign \src26__data_o \reg
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+        assign \src26__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+  wire width 1 \wr_detect$14
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $15
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $16
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src36__ren
+    connect \B 1'1
+    connect \Y $15
+  end
+  process $group_4
+    assign \wr_detect$14 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $15 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        assign \wr_detect$14 1'0
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest16__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$14 1'1
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest26__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$14 1'1
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $17
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $18
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src36__ren
+    connect \B 1'1
+    connect \Y $17
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  wire width 1 $19
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  cell $not $20
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_detect$14
+    connect \Y $19
+  end
+  process $group_5
+    assign \src36__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $17 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest16__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src36__data_o \dest16__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest26__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src36__data_o \dest26__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+        switch { $19 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+          case 1'1
+            assign \src36__data_o \reg
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+        assign \src36__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+  wire width 1 \wr_detect$21
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $22
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $23
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \dmi6__ren
+    connect \B 1'1
+    connect \Y $22
+  end
+  process $group_6
+    assign \wr_detect$21 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $22 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        assign \wr_detect$21 1'0
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest16__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$21 1'1
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest26__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$21 1'1
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $24
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $25
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \dmi6__ren
+    connect \B 1'1
+    connect \Y $24
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  wire width 1 $26
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  cell $not $27
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_detect$21
+    connect \Y $26
+  end
+  process $group_7
+    assign \dmi6__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $24 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest16__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \dmi6__data_o \dest16__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest26__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \dmi6__data_o \dest26__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+        switch { $26 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+          case 1'1
+            assign \dmi6__data_o \reg
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+        assign \dmi6__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+  end
+  process $group_8
+    assign \reg$next \reg
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+    switch { \dest16__wen }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+      case 1'1
+        assign \reg$next \dest16__data_i
+    end
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+    switch { \dest26__wen }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+      case 1'1
+        assign \reg$next \dest26__data_i
+    end
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
+      case 1'1
+        assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+      update \reg 64'0000000000000000000000000000000000000000000000000000000000000000
+    sync posedge \coresync_clk
+      update \reg \reg$next
+  end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.int.reg_7"
+module \reg_7
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 2 \src17__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 3 \src17__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 4 \src27__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 5 \src27__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 6 \src37__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 7 \src37__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 8 \dmi7__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 9 \dmi7__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 10 \dest17__wen
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 input 11 \dest17__data_i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 12 \dest27__wen
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 input 13 \dest27__data_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+  wire width 1 \wr_detect
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $1
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $2
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src17__ren
+    connect \B 1'1
+    connect \Y $1
+  end
+  process $group_0
+    assign \wr_detect 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $1 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        assign \wr_detect 1'0
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest17__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect 1'1
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest27__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect 1'1
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $3
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $4
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src17__ren
+    connect \B 1'1
+    connect \Y $3
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  wire width 1 $5
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  cell $not $6
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_detect
+    connect \Y $5
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
+  wire width 64 \reg
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
+  wire width 64 \reg$next
+  process $group_1
+    assign \src17__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $3 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest17__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src17__data_o \dest17__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest27__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src17__data_o \dest27__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+        switch { $5 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+          case 1'1
+            assign \src17__data_o \reg
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+        assign \src17__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+  wire width 1 \wr_detect$7
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $8
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $9
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src27__ren
+    connect \B 1'1
+    connect \Y $8
+  end
+  process $group_2
+    assign \wr_detect$7 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $8 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        assign \wr_detect$7 1'0
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest17__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$7 1'1
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest27__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$7 1'1
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $10
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $11
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src27__ren
+    connect \B 1'1
+    connect \Y $10
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  wire width 1 $12
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  cell $not $13
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_detect$7
+    connect \Y $12
+  end
+  process $group_3
+    assign \src27__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $10 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest17__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src27__data_o \dest17__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest27__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src27__data_o \dest27__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+        switch { $12 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+          case 1'1
+            assign \src27__data_o \reg
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+        assign \src27__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+  wire width 1 \wr_detect$14
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $15
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $16
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src37__ren
+    connect \B 1'1
+    connect \Y $15
+  end
+  process $group_4
+    assign \wr_detect$14 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $15 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        assign \wr_detect$14 1'0
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest17__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$14 1'1
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest27__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$14 1'1
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $17
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $18
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src37__ren
+    connect \B 1'1
+    connect \Y $17
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  wire width 1 $19
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  cell $not $20
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_detect$14
+    connect \Y $19
+  end
+  process $group_5
+    assign \src37__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $17 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest17__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src37__data_o \dest17__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest27__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src37__data_o \dest27__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+        switch { $19 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+          case 1'1
+            assign \src37__data_o \reg
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+        assign \src37__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+  wire width 1 \wr_detect$21
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $22
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $23
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \dmi7__ren
+    connect \B 1'1
+    connect \Y $22
+  end
+  process $group_6
+    assign \wr_detect$21 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $22 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        assign \wr_detect$21 1'0
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest17__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$21 1'1
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest27__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$21 1'1
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $24
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $25
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \dmi7__ren
+    connect \B 1'1
+    connect \Y $24
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  wire width 1 $26
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  cell $not $27
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_detect$21
+    connect \Y $26
+  end
+  process $group_7
+    assign \dmi7__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $24 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest17__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \dmi7__data_o \dest17__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest27__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \dmi7__data_o \dest27__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+        switch { $26 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+          case 1'1
+            assign \dmi7__data_o \reg
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+        assign \dmi7__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+  end
+  process $group_8
+    assign \reg$next \reg
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+    switch { \dest17__wen }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+      case 1'1
+        assign \reg$next \dest17__data_i
+    end
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+    switch { \dest27__wen }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+      case 1'1
+        assign \reg$next \dest27__data_i
+    end
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
+      case 1'1
+        assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+      update \reg 64'0000000000000000000000000000000000000000000000000000000000000000
+    sync posedge \coresync_clk
+      update \reg \reg$next
+  end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.int.reg_8"
+module \reg_8
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 2 \src18__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 3 \src18__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 4 \src28__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 5 \src28__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 6 \src38__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 7 \src38__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 8 \dmi8__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 9 \dmi8__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 10 \dest18__wen
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 input 11 \dest18__data_i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 12 \dest28__wen
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 input 13 \dest28__data_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+  wire width 1 \wr_detect
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $1
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $2
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src18__ren
+    connect \B 1'1
+    connect \Y $1
+  end
+  process $group_0
+    assign \wr_detect 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $1 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        assign \wr_detect 1'0
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest18__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect 1'1
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest28__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect 1'1
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $3
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $4
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src18__ren
+    connect \B 1'1
+    connect \Y $3
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  wire width 1 $5
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  cell $not $6
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_detect
+    connect \Y $5
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
+  wire width 64 \reg
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
+  wire width 64 \reg$next
+  process $group_1
+    assign \src18__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $3 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest18__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src18__data_o \dest18__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest28__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src18__data_o \dest28__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+        switch { $5 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+          case 1'1
+            assign \src18__data_o \reg
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+        assign \src18__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+  wire width 1 \wr_detect$7
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $8
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $9
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src28__ren
+    connect \B 1'1
+    connect \Y $8
+  end
+  process $group_2
+    assign \wr_detect$7 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $8 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        assign \wr_detect$7 1'0
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest18__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$7 1'1
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest28__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$7 1'1
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $10
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $11
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src28__ren
+    connect \B 1'1
+    connect \Y $10
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  wire width 1 $12
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  cell $not $13
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_detect$7
+    connect \Y $12
+  end
+  process $group_3
+    assign \src28__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $10 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest18__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src28__data_o \dest18__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest28__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src28__data_o \dest28__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+        switch { $12 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+          case 1'1
+            assign \src28__data_o \reg
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+        assign \src28__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+  wire width 1 \wr_detect$14
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $15
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $16
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src38__ren
+    connect \B 1'1
+    connect \Y $15
+  end
+  process $group_4
+    assign \wr_detect$14 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $15 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        assign \wr_detect$14 1'0
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest18__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$14 1'1
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest28__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$14 1'1
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $17
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $18
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src38__ren
+    connect \B 1'1
+    connect \Y $17
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  wire width 1 $19
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  cell $not $20
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_detect$14
+    connect \Y $19
+  end
+  process $group_5
+    assign \src38__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $17 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest18__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src38__data_o \dest18__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest28__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src38__data_o \dest28__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+        switch { $19 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+          case 1'1
+            assign \src38__data_o \reg
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+        assign \src38__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+  wire width 1 \wr_detect$21
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $22
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $23
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \dmi8__ren
+    connect \B 1'1
+    connect \Y $22
+  end
+  process $group_6
+    assign \wr_detect$21 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $22 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        assign \wr_detect$21 1'0
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest18__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$21 1'1
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest28__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$21 1'1
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $24
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $25
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \dmi8__ren
+    connect \B 1'1
+    connect \Y $24
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  wire width 1 $26
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  cell $not $27
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_detect$21
+    connect \Y $26
+  end
+  process $group_7
+    assign \dmi8__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $24 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest18__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \dmi8__data_o \dest18__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest28__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \dmi8__data_o \dest28__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+        switch { $26 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+          case 1'1
+            assign \dmi8__data_o \reg
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+        assign \dmi8__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+  end
+  process $group_8
+    assign \reg$next \reg
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+    switch { \dest18__wen }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+      case 1'1
+        assign \reg$next \dest18__data_i
+    end
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+    switch { \dest28__wen }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+      case 1'1
+        assign \reg$next \dest28__data_i
+    end
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
+      case 1'1
+        assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+      update \reg 64'0000000000000000000000000000000000000000000000000000000000000000
+    sync posedge \coresync_clk
+      update \reg \reg$next
+  end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.int.reg_9"
+module \reg_9
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 2 \src19__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 3 \src19__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 4 \src29__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 5 \src29__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 6 \src39__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 7 \src39__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 8 \dmi9__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 9 \dmi9__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 10 \dest19__wen
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 input 11 \dest19__data_i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 12 \dest29__wen
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 input 13 \dest29__data_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+  wire width 1 \wr_detect
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $1
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $2
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src19__ren
+    connect \B 1'1
+    connect \Y $1
+  end
+  process $group_0
+    assign \wr_detect 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $1 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        assign \wr_detect 1'0
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest19__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect 1'1
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest29__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect 1'1
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $3
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $4
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src19__ren
+    connect \B 1'1
+    connect \Y $3
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  wire width 1 $5
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  cell $not $6
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_detect
+    connect \Y $5
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
+  wire width 64 \reg
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
+  wire width 64 \reg$next
+  process $group_1
+    assign \src19__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $3 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest19__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src19__data_o \dest19__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest29__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src19__data_o \dest29__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+        switch { $5 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+          case 1'1
+            assign \src19__data_o \reg
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+        assign \src19__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+  wire width 1 \wr_detect$7
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $8
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $9
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src29__ren
+    connect \B 1'1
+    connect \Y $8
+  end
+  process $group_2
+    assign \wr_detect$7 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $8 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        assign \wr_detect$7 1'0
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest19__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$7 1'1
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest29__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$7 1'1
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $10
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $11
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src29__ren
+    connect \B 1'1
+    connect \Y $10
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  wire width 1 $12
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  cell $not $13
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_detect$7
+    connect \Y $12
+  end
+  process $group_3
+    assign \src29__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $10 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest19__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src29__data_o \dest19__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest29__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src29__data_o \dest29__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+        switch { $12 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+          case 1'1
+            assign \src29__data_o \reg
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+        assign \src29__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+  wire width 1 \wr_detect$14
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $15
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $16
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src39__ren
+    connect \B 1'1
+    connect \Y $15
+  end
+  process $group_4
+    assign \wr_detect$14 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $15 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        assign \wr_detect$14 1'0
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest19__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$14 1'1
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest29__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$14 1'1
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $17
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $18
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src39__ren
+    connect \B 1'1
+    connect \Y $17
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  wire width 1 $19
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  cell $not $20
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_detect$14
+    connect \Y $19
+  end
+  process $group_5
+    assign \src39__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $17 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest19__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src39__data_o \dest19__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest29__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src39__data_o \dest29__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+        switch { $19 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+          case 1'1
+            assign \src39__data_o \reg
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+        assign \src39__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+  wire width 1 \wr_detect$21
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $22
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $23
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \dmi9__ren
+    connect \B 1'1
+    connect \Y $22
+  end
+  process $group_6
+    assign \wr_detect$21 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $22 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        assign \wr_detect$21 1'0
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest19__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$21 1'1
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest29__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$21 1'1
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $24
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $25
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \dmi9__ren
+    connect \B 1'1
+    connect \Y $24
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  wire width 1 $26
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  cell $not $27
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_detect$21
+    connect \Y $26
+  end
+  process $group_7
+    assign \dmi9__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $24 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest19__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \dmi9__data_o \dest19__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest29__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \dmi9__data_o \dest29__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+        switch { $26 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+          case 1'1
+            assign \dmi9__data_o \reg
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+        assign \dmi9__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+  end
+  process $group_8
+    assign \reg$next \reg
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+    switch { \dest19__wen }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+      case 1'1
+        assign \reg$next \dest19__data_i
+    end
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+    switch { \dest29__wen }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+      case 1'1
+        assign \reg$next \dest29__data_i
+    end
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
+      case 1'1
+        assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+      update \reg 64'0000000000000000000000000000000000000000000000000000000000000000
+    sync posedge \coresync_clk
+      update \reg \reg$next
+  end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.int.reg_10"
+module \reg_10
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 2 \src110__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 3 \src110__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 4 \src210__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 5 \src210__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 6 \src310__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 7 \src310__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 8 \dmi10__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 9 \dmi10__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 10 \dest110__wen
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 input 11 \dest110__data_i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 12 \dest210__wen
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 input 13 \dest210__data_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+  wire width 1 \wr_detect
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $1
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $2
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src110__ren
+    connect \B 1'1
+    connect \Y $1
+  end
+  process $group_0
+    assign \wr_detect 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $1 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        assign \wr_detect 1'0
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest110__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect 1'1
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest210__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect 1'1
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $3
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $4
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src110__ren
+    connect \B 1'1
+    connect \Y $3
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  wire width 1 $5
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  cell $not $6
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_detect
+    connect \Y $5
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
+  wire width 64 \reg
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
+  wire width 64 \reg$next
+  process $group_1
+    assign \src110__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $3 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest110__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src110__data_o \dest110__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest210__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src110__data_o \dest210__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+        switch { $5 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+          case 1'1
+            assign \src110__data_o \reg
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+        assign \src110__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+  wire width 1 \wr_detect$7
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $8
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $9
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src210__ren
+    connect \B 1'1
+    connect \Y $8
+  end
+  process $group_2
+    assign \wr_detect$7 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $8 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        assign \wr_detect$7 1'0
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest110__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$7 1'1
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest210__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$7 1'1
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $10
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $11
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src210__ren
+    connect \B 1'1
+    connect \Y $10
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  wire width 1 $12
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  cell $not $13
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_detect$7
+    connect \Y $12
+  end
+  process $group_3
+    assign \src210__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $10 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest110__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src210__data_o \dest110__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest210__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src210__data_o \dest210__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+        switch { $12 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+          case 1'1
+            assign \src210__data_o \reg
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+        assign \src210__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+  wire width 1 \wr_detect$14
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $15
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $16
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src310__ren
+    connect \B 1'1
+    connect \Y $15
+  end
+  process $group_4
+    assign \wr_detect$14 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $15 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        assign \wr_detect$14 1'0
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest110__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$14 1'1
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest210__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$14 1'1
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $17
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $18
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src310__ren
+    connect \B 1'1
+    connect \Y $17
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  wire width 1 $19
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  cell $not $20
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_detect$14
+    connect \Y $19
+  end
+  process $group_5
+    assign \src310__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $17 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest110__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src310__data_o \dest110__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest210__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src310__data_o \dest210__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+        switch { $19 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+          case 1'1
+            assign \src310__data_o \reg
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+        assign \src310__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+  wire width 1 \wr_detect$21
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $22
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $23
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \dmi10__ren
+    connect \B 1'1
+    connect \Y $22
+  end
+  process $group_6
+    assign \wr_detect$21 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $22 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        assign \wr_detect$21 1'0
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest110__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$21 1'1
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest210__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$21 1'1
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $24
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $25
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \dmi10__ren
+    connect \B 1'1
+    connect \Y $24
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  wire width 1 $26
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  cell $not $27
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_detect$21
+    connect \Y $26
+  end
+  process $group_7
+    assign \dmi10__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $24 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest110__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \dmi10__data_o \dest110__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest210__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \dmi10__data_o \dest210__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+        switch { $26 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+          case 1'1
+            assign \dmi10__data_o \reg
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+        assign \dmi10__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+  end
+  process $group_8
+    assign \reg$next \reg
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+    switch { \dest110__wen }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+      case 1'1
+        assign \reg$next \dest110__data_i
+    end
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+    switch { \dest210__wen }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+      case 1'1
+        assign \reg$next \dest210__data_i
+    end
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
+      case 1'1
+        assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+      update \reg 64'0000000000000000000000000000000000000000000000000000000000000000
+    sync posedge \coresync_clk
+      update \reg \reg$next
+  end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.int.reg_11"
+module \reg_11
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 2 \src111__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 3 \src111__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 4 \src211__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 5 \src211__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 6 \src311__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 7 \src311__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 8 \dmi11__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 9 \dmi11__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 10 \dest111__wen
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 input 11 \dest111__data_i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 12 \dest211__wen
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 input 13 \dest211__data_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+  wire width 1 \wr_detect
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $1
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $2
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src111__ren
+    connect \B 1'1
+    connect \Y $1
+  end
+  process $group_0
+    assign \wr_detect 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $1 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        assign \wr_detect 1'0
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest111__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect 1'1
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest211__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect 1'1
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $3
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $4
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src111__ren
+    connect \B 1'1
+    connect \Y $3
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  wire width 1 $5
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  cell $not $6
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_detect
+    connect \Y $5
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
+  wire width 64 \reg
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
+  wire width 64 \reg$next
+  process $group_1
+    assign \src111__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $3 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest111__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src111__data_o \dest111__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest211__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src111__data_o \dest211__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+        switch { $5 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+          case 1'1
+            assign \src111__data_o \reg
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+        assign \src111__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+  wire width 1 \wr_detect$7
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $8
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $9
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src211__ren
+    connect \B 1'1
+    connect \Y $8
+  end
+  process $group_2
+    assign \wr_detect$7 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $8 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        assign \wr_detect$7 1'0
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest111__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$7 1'1
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest211__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$7 1'1
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $10
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $11
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src211__ren
+    connect \B 1'1
+    connect \Y $10
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  wire width 1 $12
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  cell $not $13
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_detect$7
+    connect \Y $12
+  end
+  process $group_3
+    assign \src211__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $10 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest111__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src211__data_o \dest111__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest211__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src211__data_o \dest211__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+        switch { $12 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+          case 1'1
+            assign \src211__data_o \reg
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+        assign \src211__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+  wire width 1 \wr_detect$14
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $15
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $16
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src311__ren
+    connect \B 1'1
+    connect \Y $15
+  end
+  process $group_4
+    assign \wr_detect$14 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $15 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        assign \wr_detect$14 1'0
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest111__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$14 1'1
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest211__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$14 1'1
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $17
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $18
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src311__ren
+    connect \B 1'1
+    connect \Y $17
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  wire width 1 $19
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  cell $not $20
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_detect$14
+    connect \Y $19
+  end
+  process $group_5
+    assign \src311__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $17 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest111__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src311__data_o \dest111__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest211__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src311__data_o \dest211__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+        switch { $19 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+          case 1'1
+            assign \src311__data_o \reg
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+        assign \src311__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+  wire width 1 \wr_detect$21
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $22
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $23
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \dmi11__ren
+    connect \B 1'1
+    connect \Y $22
+  end
+  process $group_6
+    assign \wr_detect$21 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $22 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        assign \wr_detect$21 1'0
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest111__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$21 1'1
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest211__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$21 1'1
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $24
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $25
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \dmi11__ren
+    connect \B 1'1
+    connect \Y $24
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  wire width 1 $26
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  cell $not $27
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_detect$21
+    connect \Y $26
+  end
+  process $group_7
+    assign \dmi11__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $24 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest111__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \dmi11__data_o \dest111__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest211__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \dmi11__data_o \dest211__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+        switch { $26 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+          case 1'1
+            assign \dmi11__data_o \reg
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+        assign \dmi11__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+  end
+  process $group_8
+    assign \reg$next \reg
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+    switch { \dest111__wen }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+      case 1'1
+        assign \reg$next \dest111__data_i
+    end
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+    switch { \dest211__wen }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+      case 1'1
+        assign \reg$next \dest211__data_i
+    end
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
+      case 1'1
+        assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+      update \reg 64'0000000000000000000000000000000000000000000000000000000000000000
+    sync posedge \coresync_clk
+      update \reg \reg$next
+  end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.int.reg_12"
+module \reg_12
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 2 \src112__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 3 \src112__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 4 \src212__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 5 \src212__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 6 \src312__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 7 \src312__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 8 \dmi12__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 9 \dmi12__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 10 \dest112__wen
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 input 11 \dest112__data_i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 12 \dest212__wen
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 input 13 \dest212__data_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+  wire width 1 \wr_detect
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $1
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $2
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src112__ren
+    connect \B 1'1
+    connect \Y $1
+  end
+  process $group_0
+    assign \wr_detect 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $1 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        assign \wr_detect 1'0
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest112__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect 1'1
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest212__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect 1'1
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $3
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $4
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src112__ren
+    connect \B 1'1
+    connect \Y $3
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  wire width 1 $5
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  cell $not $6
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_detect
+    connect \Y $5
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
+  wire width 64 \reg
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
+  wire width 64 \reg$next
+  process $group_1
+    assign \src112__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $3 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest112__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src112__data_o \dest112__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest212__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src112__data_o \dest212__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+        switch { $5 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+          case 1'1
+            assign \src112__data_o \reg
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+        assign \src112__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+  wire width 1 \wr_detect$7
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $8
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $9
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src212__ren
+    connect \B 1'1
+    connect \Y $8
+  end
+  process $group_2
+    assign \wr_detect$7 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $8 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        assign \wr_detect$7 1'0
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest112__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$7 1'1
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest212__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$7 1'1
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $10
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $11
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src212__ren
+    connect \B 1'1
+    connect \Y $10
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  wire width 1 $12
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  cell $not $13
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_detect$7
+    connect \Y $12
+  end
+  process $group_3
+    assign \src212__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $10 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest112__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src212__data_o \dest112__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest212__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src212__data_o \dest212__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+        switch { $12 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+          case 1'1
+            assign \src212__data_o \reg
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+        assign \src212__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+  wire width 1 \wr_detect$14
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $15
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $16
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src312__ren
+    connect \B 1'1
+    connect \Y $15
+  end
+  process $group_4
+    assign \wr_detect$14 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $15 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        assign \wr_detect$14 1'0
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest112__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$14 1'1
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest212__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$14 1'1
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $17
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $18
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src312__ren
+    connect \B 1'1
+    connect \Y $17
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  wire width 1 $19
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  cell $not $20
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_detect$14
+    connect \Y $19
+  end
+  process $group_5
+    assign \src312__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $17 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest112__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src312__data_o \dest112__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest212__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src312__data_o \dest212__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+        switch { $19 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+          case 1'1
+            assign \src312__data_o \reg
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+        assign \src312__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+  wire width 1 \wr_detect$21
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $22
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $23
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \dmi12__ren
+    connect \B 1'1
+    connect \Y $22
+  end
+  process $group_6
+    assign \wr_detect$21 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $22 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        assign \wr_detect$21 1'0
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest112__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$21 1'1
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest212__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$21 1'1
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $24
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $25
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \dmi12__ren
+    connect \B 1'1
+    connect \Y $24
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  wire width 1 $26
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  cell $not $27
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_detect$21
+    connect \Y $26
+  end
+  process $group_7
+    assign \dmi12__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $24 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest112__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \dmi12__data_o \dest112__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest212__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \dmi12__data_o \dest212__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+        switch { $26 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+          case 1'1
+            assign \dmi12__data_o \reg
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+        assign \dmi12__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+  end
+  process $group_8
+    assign \reg$next \reg
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+    switch { \dest112__wen }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+      case 1'1
+        assign \reg$next \dest112__data_i
+    end
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+    switch { \dest212__wen }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+      case 1'1
+        assign \reg$next \dest212__data_i
+    end
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
+      case 1'1
+        assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+      update \reg 64'0000000000000000000000000000000000000000000000000000000000000000
+    sync posedge \coresync_clk
+      update \reg \reg$next
+  end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.int.reg_13"
+module \reg_13
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 2 \src113__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 3 \src113__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 4 \src213__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 5 \src213__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 6 \src313__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 7 \src313__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 8 \dmi13__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 9 \dmi13__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 10 \dest113__wen
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 input 11 \dest113__data_i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 12 \dest213__wen
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 input 13 \dest213__data_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+  wire width 1 \wr_detect
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $1
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $2
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src113__ren
+    connect \B 1'1
+    connect \Y $1
+  end
+  process $group_0
+    assign \wr_detect 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $1 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        assign \wr_detect 1'0
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest113__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect 1'1
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest213__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect 1'1
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $3
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $4
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src113__ren
+    connect \B 1'1
+    connect \Y $3
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  wire width 1 $5
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  cell $not $6
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_detect
+    connect \Y $5
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
+  wire width 64 \reg
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
+  wire width 64 \reg$next
+  process $group_1
+    assign \src113__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $3 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest113__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src113__data_o \dest113__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest213__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src113__data_o \dest213__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+        switch { $5 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+          case 1'1
+            assign \src113__data_o \reg
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+        assign \src113__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+  wire width 1 \wr_detect$7
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $8
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $9
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src213__ren
+    connect \B 1'1
+    connect \Y $8
+  end
+  process $group_2
+    assign \wr_detect$7 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $8 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        assign \wr_detect$7 1'0
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest113__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$7 1'1
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest213__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$7 1'1
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $10
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $11
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src213__ren
+    connect \B 1'1
+    connect \Y $10
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  wire width 1 $12
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  cell $not $13
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_detect$7
+    connect \Y $12
+  end
+  process $group_3
+    assign \src213__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $10 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest113__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src213__data_o \dest113__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest213__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src213__data_o \dest213__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+        switch { $12 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+          case 1'1
+            assign \src213__data_o \reg
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+        assign \src213__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+  wire width 1 \wr_detect$14
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $15
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $16
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src313__ren
+    connect \B 1'1
+    connect \Y $15
+  end
+  process $group_4
+    assign \wr_detect$14 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $15 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        assign \wr_detect$14 1'0
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest113__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$14 1'1
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest213__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$14 1'1
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $17
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $18
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src313__ren
+    connect \B 1'1
+    connect \Y $17
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  wire width 1 $19
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  cell $not $20
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_detect$14
+    connect \Y $19
+  end
+  process $group_5
+    assign \src313__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $17 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest113__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src313__data_o \dest113__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest213__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src313__data_o \dest213__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+        switch { $19 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+          case 1'1
+            assign \src313__data_o \reg
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+        assign \src313__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+  wire width 1 \wr_detect$21
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $22
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $23
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \dmi13__ren
+    connect \B 1'1
+    connect \Y $22
+  end
+  process $group_6
+    assign \wr_detect$21 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $22 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        assign \wr_detect$21 1'0
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest113__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$21 1'1
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest213__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$21 1'1
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $24
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $25
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \dmi13__ren
+    connect \B 1'1
+    connect \Y $24
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  wire width 1 $26
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  cell $not $27
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_detect$21
+    connect \Y $26
+  end
+  process $group_7
+    assign \dmi13__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $24 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest113__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \dmi13__data_o \dest113__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest213__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \dmi13__data_o \dest213__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+        switch { $26 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+          case 1'1
+            assign \dmi13__data_o \reg
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+        assign \dmi13__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+  end
+  process $group_8
+    assign \reg$next \reg
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+    switch { \dest113__wen }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+      case 1'1
+        assign \reg$next \dest113__data_i
+    end
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+    switch { \dest213__wen }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+      case 1'1
+        assign \reg$next \dest213__data_i
+    end
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
+      case 1'1
+        assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+      update \reg 64'0000000000000000000000000000000000000000000000000000000000000000
+    sync posedge \coresync_clk
+      update \reg \reg$next
+  end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.int.reg_14"
+module \reg_14
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 2 \src114__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 3 \src114__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 4 \src214__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 5 \src214__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 6 \src314__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 7 \src314__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 8 \dmi14__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 9 \dmi14__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 10 \dest114__wen
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 input 11 \dest114__data_i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 12 \dest214__wen
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 input 13 \dest214__data_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+  wire width 1 \wr_detect
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $1
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $2
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src114__ren
+    connect \B 1'1
+    connect \Y $1
+  end
+  process $group_0
+    assign \wr_detect 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $1 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        assign \wr_detect 1'0
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest114__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect 1'1
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest214__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect 1'1
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $3
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $4
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src114__ren
+    connect \B 1'1
+    connect \Y $3
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  wire width 1 $5
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  cell $not $6
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_detect
+    connect \Y $5
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
+  wire width 64 \reg
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
+  wire width 64 \reg$next
+  process $group_1
+    assign \src114__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $3 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest114__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src114__data_o \dest114__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest214__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src114__data_o \dest214__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+        switch { $5 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+          case 1'1
+            assign \src114__data_o \reg
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+        assign \src114__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+  wire width 1 \wr_detect$7
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $8
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $9
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src214__ren
+    connect \B 1'1
+    connect \Y $8
+  end
+  process $group_2
+    assign \wr_detect$7 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $8 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        assign \wr_detect$7 1'0
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest114__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$7 1'1
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest214__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$7 1'1
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $10
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $11
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src214__ren
+    connect \B 1'1
+    connect \Y $10
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  wire width 1 $12
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  cell $not $13
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_detect$7
+    connect \Y $12
+  end
+  process $group_3
+    assign \src214__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $10 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest114__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src214__data_o \dest114__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest214__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src214__data_o \dest214__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+        switch { $12 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+          case 1'1
+            assign \src214__data_o \reg
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+        assign \src214__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+  wire width 1 \wr_detect$14
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $15
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $16
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src314__ren
+    connect \B 1'1
+    connect \Y $15
+  end
+  process $group_4
+    assign \wr_detect$14 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $15 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        assign \wr_detect$14 1'0
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest114__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$14 1'1
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest214__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$14 1'1
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $17
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $18
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src314__ren
+    connect \B 1'1
+    connect \Y $17
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  wire width 1 $19
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  cell $not $20
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_detect$14
+    connect \Y $19
+  end
+  process $group_5
+    assign \src314__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $17 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest114__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src314__data_o \dest114__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest214__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src314__data_o \dest214__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+        switch { $19 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+          case 1'1
+            assign \src314__data_o \reg
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+        assign \src314__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+  wire width 1 \wr_detect$21
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $22
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $23
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \dmi14__ren
+    connect \B 1'1
+    connect \Y $22
+  end
+  process $group_6
+    assign \wr_detect$21 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $22 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        assign \wr_detect$21 1'0
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest114__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$21 1'1
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest214__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$21 1'1
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $24
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $25
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \dmi14__ren
+    connect \B 1'1
+    connect \Y $24
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  wire width 1 $26
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  cell $not $27
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_detect$21
+    connect \Y $26
+  end
+  process $group_7
+    assign \dmi14__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $24 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest114__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \dmi14__data_o \dest114__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest214__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \dmi14__data_o \dest214__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+        switch { $26 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+          case 1'1
+            assign \dmi14__data_o \reg
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+        assign \dmi14__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+  end
+  process $group_8
+    assign \reg$next \reg
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+    switch { \dest114__wen }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+      case 1'1
+        assign \reg$next \dest114__data_i
+    end
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+    switch { \dest214__wen }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+      case 1'1
+        assign \reg$next \dest214__data_i
+    end
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
+      case 1'1
+        assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+      update \reg 64'0000000000000000000000000000000000000000000000000000000000000000
+    sync posedge \coresync_clk
+      update \reg \reg$next
+  end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.int.reg_15"
+module \reg_15
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 2 \src115__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 3 \src115__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 4 \src215__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 5 \src215__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 6 \src315__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 7 \src315__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 8 \dmi15__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 9 \dmi15__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 10 \dest115__wen
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 input 11 \dest115__data_i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 12 \dest215__wen
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 input 13 \dest215__data_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+  wire width 1 \wr_detect
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $1
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $2
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src115__ren
+    connect \B 1'1
+    connect \Y $1
+  end
+  process $group_0
+    assign \wr_detect 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $1 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        assign \wr_detect 1'0
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest115__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect 1'1
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest215__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect 1'1
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $3
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $4
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src115__ren
+    connect \B 1'1
+    connect \Y $3
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  wire width 1 $5
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  cell $not $6
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_detect
+    connect \Y $5
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
+  wire width 64 \reg
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
+  wire width 64 \reg$next
+  process $group_1
+    assign \src115__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $3 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest115__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src115__data_o \dest115__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest215__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src115__data_o \dest215__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+        switch { $5 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+          case 1'1
+            assign \src115__data_o \reg
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+        assign \src115__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+  wire width 1 \wr_detect$7
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $8
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $9
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src215__ren
+    connect \B 1'1
+    connect \Y $8
+  end
+  process $group_2
+    assign \wr_detect$7 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $8 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        assign \wr_detect$7 1'0
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest115__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$7 1'1
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest215__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$7 1'1
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $10
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $11
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src215__ren
+    connect \B 1'1
+    connect \Y $10
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  wire width 1 $12
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  cell $not $13
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_detect$7
+    connect \Y $12
+  end
+  process $group_3
+    assign \src215__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $10 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest115__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src215__data_o \dest115__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest215__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src215__data_o \dest215__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+        switch { $12 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+          case 1'1
+            assign \src215__data_o \reg
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+        assign \src215__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+  wire width 1 \wr_detect$14
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $15
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $16
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src315__ren
+    connect \B 1'1
+    connect \Y $15
+  end
+  process $group_4
+    assign \wr_detect$14 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $15 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        assign \wr_detect$14 1'0
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest115__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$14 1'1
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest215__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$14 1'1
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $17
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $18
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src315__ren
+    connect \B 1'1
+    connect \Y $17
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  wire width 1 $19
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  cell $not $20
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_detect$14
+    connect \Y $19
+  end
+  process $group_5
+    assign \src315__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $17 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest115__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src315__data_o \dest115__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest215__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src315__data_o \dest215__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+        switch { $19 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+          case 1'1
+            assign \src315__data_o \reg
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+        assign \src315__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+  wire width 1 \wr_detect$21
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $22
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $23
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \dmi15__ren
+    connect \B 1'1
+    connect \Y $22
+  end
+  process $group_6
+    assign \wr_detect$21 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $22 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        assign \wr_detect$21 1'0
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest115__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$21 1'1
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest215__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$21 1'1
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $24
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $25
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \dmi15__ren
+    connect \B 1'1
+    connect \Y $24
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  wire width 1 $26
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  cell $not $27
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_detect$21
+    connect \Y $26
+  end
+  process $group_7
+    assign \dmi15__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $24 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest115__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \dmi15__data_o \dest115__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest215__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \dmi15__data_o \dest215__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+        switch { $26 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+          case 1'1
+            assign \dmi15__data_o \reg
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+        assign \dmi15__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+  end
+  process $group_8
+    assign \reg$next \reg
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+    switch { \dest115__wen }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+      case 1'1
+        assign \reg$next \dest115__data_i
+    end
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+    switch { \dest215__wen }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+      case 1'1
+        assign \reg$next \dest215__data_i
+    end
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
+      case 1'1
+        assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+      update \reg 64'0000000000000000000000000000000000000000000000000000000000000000
+    sync posedge \coresync_clk
+      update \reg \reg$next
+  end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.int.reg_16"
+module \reg_16
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 2 \src116__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 3 \src116__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 4 \src216__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 5 \src216__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 6 \src316__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 7 \src316__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 8 \dmi16__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 9 \dmi16__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 10 \dest116__wen
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 input 11 \dest116__data_i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 12 \dest216__wen
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 input 13 \dest216__data_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+  wire width 1 \wr_detect
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $1
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $2
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src116__ren
+    connect \B 1'1
+    connect \Y $1
+  end
+  process $group_0
+    assign \wr_detect 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $1 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        assign \wr_detect 1'0
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest116__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect 1'1
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest216__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect 1'1
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $3
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $4
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src116__ren
+    connect \B 1'1
+    connect \Y $3
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  wire width 1 $5
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  cell $not $6
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_detect
+    connect \Y $5
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
+  wire width 64 \reg
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
+  wire width 64 \reg$next
+  process $group_1
+    assign \src116__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $3 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest116__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src116__data_o \dest116__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest216__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src116__data_o \dest216__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+        switch { $5 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+          case 1'1
+            assign \src116__data_o \reg
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+        assign \src116__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+  wire width 1 \wr_detect$7
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $8
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $9
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src216__ren
+    connect \B 1'1
+    connect \Y $8
+  end
+  process $group_2
+    assign \wr_detect$7 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $8 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        assign \wr_detect$7 1'0
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest116__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$7 1'1
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest216__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$7 1'1
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $10
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $11
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src216__ren
+    connect \B 1'1
+    connect \Y $10
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  wire width 1 $12
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  cell $not $13
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_detect$7
+    connect \Y $12
+  end
+  process $group_3
+    assign \src216__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $10 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest116__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src216__data_o \dest116__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest216__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src216__data_o \dest216__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+        switch { $12 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+          case 1'1
+            assign \src216__data_o \reg
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+        assign \src216__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+  wire width 1 \wr_detect$14
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $15
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $16
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src316__ren
+    connect \B 1'1
+    connect \Y $15
+  end
+  process $group_4
+    assign \wr_detect$14 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $15 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        assign \wr_detect$14 1'0
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest116__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$14 1'1
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest216__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$14 1'1
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $17
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $18
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src316__ren
+    connect \B 1'1
+    connect \Y $17
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  wire width 1 $19
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  cell $not $20
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_detect$14
+    connect \Y $19
+  end
+  process $group_5
+    assign \src316__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $17 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest116__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src316__data_o \dest116__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest216__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src316__data_o \dest216__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+        switch { $19 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+          case 1'1
+            assign \src316__data_o \reg
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+        assign \src316__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+  wire width 1 \wr_detect$21
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $22
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $23
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \dmi16__ren
+    connect \B 1'1
+    connect \Y $22
+  end
+  process $group_6
+    assign \wr_detect$21 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $22 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        assign \wr_detect$21 1'0
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest116__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$21 1'1
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest216__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$21 1'1
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $24
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $25
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \dmi16__ren
+    connect \B 1'1
+    connect \Y $24
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  wire width 1 $26
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  cell $not $27
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_detect$21
+    connect \Y $26
+  end
+  process $group_7
+    assign \dmi16__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $24 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest116__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \dmi16__data_o \dest116__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest216__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \dmi16__data_o \dest216__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+        switch { $26 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+          case 1'1
+            assign \dmi16__data_o \reg
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+        assign \dmi16__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+  end
+  process $group_8
+    assign \reg$next \reg
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+    switch { \dest116__wen }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+      case 1'1
+        assign \reg$next \dest116__data_i
+    end
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+    switch { \dest216__wen }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+      case 1'1
+        assign \reg$next \dest216__data_i
+    end
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
+      case 1'1
+        assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+      update \reg 64'0000000000000000000000000000000000000000000000000000000000000000
+    sync posedge \coresync_clk
+      update \reg \reg$next
+  end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.int.reg_17"
+module \reg_17
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 2 \src117__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 3 \src117__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 4 \src217__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 5 \src217__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 6 \src317__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 7 \src317__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 8 \dmi17__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 9 \dmi17__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 10 \dest117__wen
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 input 11 \dest117__data_i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 12 \dest217__wen
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 input 13 \dest217__data_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+  wire width 1 \wr_detect
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $1
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $2
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src117__ren
+    connect \B 1'1
+    connect \Y $1
+  end
+  process $group_0
+    assign \wr_detect 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $1 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        assign \wr_detect 1'0
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest117__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect 1'1
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest217__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect 1'1
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $3
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $4
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src117__ren
+    connect \B 1'1
+    connect \Y $3
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  wire width 1 $5
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  cell $not $6
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_detect
+    connect \Y $5
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
+  wire width 64 \reg
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
+  wire width 64 \reg$next
+  process $group_1
+    assign \src117__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $3 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest117__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src117__data_o \dest117__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest217__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src117__data_o \dest217__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+        switch { $5 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+          case 1'1
+            assign \src117__data_o \reg
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+        assign \src117__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+  wire width 1 \wr_detect$7
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $8
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $9
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src217__ren
+    connect \B 1'1
+    connect \Y $8
+  end
+  process $group_2
+    assign \wr_detect$7 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $8 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        assign \wr_detect$7 1'0
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest117__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$7 1'1
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest217__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$7 1'1
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $10
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $11
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src217__ren
+    connect \B 1'1
+    connect \Y $10
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  wire width 1 $12
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  cell $not $13
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_detect$7
+    connect \Y $12
+  end
+  process $group_3
+    assign \src217__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $10 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest117__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src217__data_o \dest117__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest217__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src217__data_o \dest217__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+        switch { $12 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+          case 1'1
+            assign \src217__data_o \reg
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+        assign \src217__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+  wire width 1 \wr_detect$14
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $15
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $16
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src317__ren
+    connect \B 1'1
+    connect \Y $15
+  end
+  process $group_4
+    assign \wr_detect$14 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $15 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        assign \wr_detect$14 1'0
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest117__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$14 1'1
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest217__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$14 1'1
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $17
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $18
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src317__ren
+    connect \B 1'1
+    connect \Y $17
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  wire width 1 $19
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  cell $not $20
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_detect$14
+    connect \Y $19
+  end
+  process $group_5
+    assign \src317__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $17 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest117__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src317__data_o \dest117__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest217__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src317__data_o \dest217__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+        switch { $19 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+          case 1'1
+            assign \src317__data_o \reg
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+        assign \src317__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+  wire width 1 \wr_detect$21
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $22
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $23
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \dmi17__ren
+    connect \B 1'1
+    connect \Y $22
+  end
+  process $group_6
+    assign \wr_detect$21 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $22 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        assign \wr_detect$21 1'0
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest117__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$21 1'1
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest217__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$21 1'1
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $24
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $25
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \dmi17__ren
+    connect \B 1'1
+    connect \Y $24
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  wire width 1 $26
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  cell $not $27
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_detect$21
+    connect \Y $26
+  end
+  process $group_7
+    assign \dmi17__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $24 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest117__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \dmi17__data_o \dest117__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest217__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \dmi17__data_o \dest217__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+        switch { $26 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+          case 1'1
+            assign \dmi17__data_o \reg
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+        assign \dmi17__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+  end
+  process $group_8
+    assign \reg$next \reg
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+    switch { \dest117__wen }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+      case 1'1
+        assign \reg$next \dest117__data_i
+    end
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+    switch { \dest217__wen }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+      case 1'1
+        assign \reg$next \dest217__data_i
+    end
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
+      case 1'1
+        assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+      update \reg 64'0000000000000000000000000000000000000000000000000000000000000000
+    sync posedge \coresync_clk
+      update \reg \reg$next
+  end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.int.reg_18"
+module \reg_18
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 2 \src118__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 3 \src118__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 4 \src218__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 5 \src218__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 6 \src318__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 7 \src318__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 8 \dmi18__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 9 \dmi18__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 10 \dest118__wen
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 input 11 \dest118__data_i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 12 \dest218__wen
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 input 13 \dest218__data_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+  wire width 1 \wr_detect
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $1
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $2
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src118__ren
+    connect \B 1'1
+    connect \Y $1
+  end
+  process $group_0
+    assign \wr_detect 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $1 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        assign \wr_detect 1'0
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest118__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect 1'1
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest218__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect 1'1
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $3
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $4
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src118__ren
+    connect \B 1'1
+    connect \Y $3
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  wire width 1 $5
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  cell $not $6
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_detect
+    connect \Y $5
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
+  wire width 64 \reg
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
+  wire width 64 \reg$next
+  process $group_1
+    assign \src118__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $3 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest118__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src118__data_o \dest118__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest218__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src118__data_o \dest218__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+        switch { $5 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+          case 1'1
+            assign \src118__data_o \reg
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+        assign \src118__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+  wire width 1 \wr_detect$7
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $8
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $9
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src218__ren
+    connect \B 1'1
+    connect \Y $8
+  end
+  process $group_2
+    assign \wr_detect$7 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $8 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        assign \wr_detect$7 1'0
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest118__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$7 1'1
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest218__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$7 1'1
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $10
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $11
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src218__ren
+    connect \B 1'1
+    connect \Y $10
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  wire width 1 $12
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  cell $not $13
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_detect$7
+    connect \Y $12
+  end
+  process $group_3
+    assign \src218__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $10 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest118__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src218__data_o \dest118__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest218__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src218__data_o \dest218__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+        switch { $12 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+          case 1'1
+            assign \src218__data_o \reg
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+        assign \src218__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+  wire width 1 \wr_detect$14
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $15
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $16
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src318__ren
+    connect \B 1'1
+    connect \Y $15
+  end
+  process $group_4
+    assign \wr_detect$14 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $15 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        assign \wr_detect$14 1'0
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest118__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$14 1'1
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest218__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$14 1'1
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $17
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $18
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src318__ren
+    connect \B 1'1
+    connect \Y $17
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  wire width 1 $19
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  cell $not $20
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_detect$14
+    connect \Y $19
+  end
+  process $group_5
+    assign \src318__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $17 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest118__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src318__data_o \dest118__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest218__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src318__data_o \dest218__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+        switch { $19 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+          case 1'1
+            assign \src318__data_o \reg
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+        assign \src318__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+  wire width 1 \wr_detect$21
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $22
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $23
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \dmi18__ren
+    connect \B 1'1
+    connect \Y $22
+  end
+  process $group_6
+    assign \wr_detect$21 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $22 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        assign \wr_detect$21 1'0
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest118__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$21 1'1
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest218__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$21 1'1
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $24
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $25
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \dmi18__ren
+    connect \B 1'1
+    connect \Y $24
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  wire width 1 $26
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  cell $not $27
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_detect$21
+    connect \Y $26
+  end
+  process $group_7
+    assign \dmi18__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $24 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest118__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \dmi18__data_o \dest118__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest218__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \dmi18__data_o \dest218__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+        switch { $26 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+          case 1'1
+            assign \dmi18__data_o \reg
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+        assign \dmi18__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+  end
+  process $group_8
+    assign \reg$next \reg
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+    switch { \dest118__wen }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+      case 1'1
+        assign \reg$next \dest118__data_i
+    end
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+    switch { \dest218__wen }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+      case 1'1
+        assign \reg$next \dest218__data_i
+    end
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
+      case 1'1
+        assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+      update \reg 64'0000000000000000000000000000000000000000000000000000000000000000
+    sync posedge \coresync_clk
+      update \reg \reg$next
+  end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.int.reg_19"
+module \reg_19
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 2 \src119__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 3 \src119__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 4 \src219__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 5 \src219__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 6 \src319__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 7 \src319__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 8 \dmi19__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 9 \dmi19__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 10 \dest119__wen
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 input 11 \dest119__data_i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 12 \dest219__wen
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 input 13 \dest219__data_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+  wire width 1 \wr_detect
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $1
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $2
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src119__ren
+    connect \B 1'1
+    connect \Y $1
+  end
+  process $group_0
+    assign \wr_detect 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $1 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        assign \wr_detect 1'0
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest119__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect 1'1
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest219__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect 1'1
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $3
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $4
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src119__ren
+    connect \B 1'1
+    connect \Y $3
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  wire width 1 $5
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  cell $not $6
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_detect
+    connect \Y $5
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
+  wire width 64 \reg
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
+  wire width 64 \reg$next
+  process $group_1
+    assign \src119__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $3 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest119__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src119__data_o \dest119__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest219__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src119__data_o \dest219__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+        switch { $5 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+          case 1'1
+            assign \src119__data_o \reg
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+        assign \src119__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+  wire width 1 \wr_detect$7
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $8
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $9
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src219__ren
+    connect \B 1'1
+    connect \Y $8
+  end
+  process $group_2
+    assign \wr_detect$7 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $8 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        assign \wr_detect$7 1'0
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest119__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$7 1'1
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest219__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$7 1'1
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $10
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $11
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src219__ren
+    connect \B 1'1
+    connect \Y $10
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  wire width 1 $12
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  cell $not $13
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_detect$7
+    connect \Y $12
+  end
+  process $group_3
+    assign \src219__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $10 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest119__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src219__data_o \dest119__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest219__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src219__data_o \dest219__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+        switch { $12 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+          case 1'1
+            assign \src219__data_o \reg
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+        assign \src219__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+  wire width 1 \wr_detect$14
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $15
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $16
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src319__ren
+    connect \B 1'1
+    connect \Y $15
+  end
+  process $group_4
+    assign \wr_detect$14 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $15 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        assign \wr_detect$14 1'0
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest119__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$14 1'1
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest219__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$14 1'1
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $17
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $18
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src319__ren
+    connect \B 1'1
+    connect \Y $17
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  wire width 1 $19
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  cell $not $20
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_detect$14
+    connect \Y $19
+  end
+  process $group_5
+    assign \src319__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $17 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest119__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src319__data_o \dest119__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest219__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src319__data_o \dest219__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+        switch { $19 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+          case 1'1
+            assign \src319__data_o \reg
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+        assign \src319__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+  wire width 1 \wr_detect$21
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $22
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $23
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \dmi19__ren
+    connect \B 1'1
+    connect \Y $22
+  end
+  process $group_6
+    assign \wr_detect$21 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $22 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        assign \wr_detect$21 1'0
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest119__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$21 1'1
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest219__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$21 1'1
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $24
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $25
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \dmi19__ren
+    connect \B 1'1
+    connect \Y $24
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  wire width 1 $26
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  cell $not $27
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_detect$21
+    connect \Y $26
+  end
+  process $group_7
+    assign \dmi19__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $24 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest119__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \dmi19__data_o \dest119__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest219__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \dmi19__data_o \dest219__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+        switch { $26 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+          case 1'1
+            assign \dmi19__data_o \reg
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+        assign \dmi19__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+  end
+  process $group_8
+    assign \reg$next \reg
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+    switch { \dest119__wen }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+      case 1'1
+        assign \reg$next \dest119__data_i
+    end
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+    switch { \dest219__wen }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+      case 1'1
+        assign \reg$next \dest219__data_i
+    end
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
+      case 1'1
+        assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+      update \reg 64'0000000000000000000000000000000000000000000000000000000000000000
+    sync posedge \coresync_clk
+      update \reg \reg$next
+  end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.int.reg_20"
+module \reg_20
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 2 \src120__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 3 \src120__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 4 \src220__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 5 \src220__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 6 \src320__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 7 \src320__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 8 \dmi20__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 9 \dmi20__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 10 \dest120__wen
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 input 11 \dest120__data_i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 12 \dest220__wen
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 input 13 \dest220__data_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+  wire width 1 \wr_detect
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $1
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $2
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src120__ren
+    connect \B 1'1
+    connect \Y $1
+  end
+  process $group_0
+    assign \wr_detect 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $1 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        assign \wr_detect 1'0
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest120__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect 1'1
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest220__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect 1'1
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $3
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $4
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src120__ren
+    connect \B 1'1
+    connect \Y $3
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  wire width 1 $5
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  cell $not $6
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_detect
+    connect \Y $5
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
+  wire width 64 \reg
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
+  wire width 64 \reg$next
+  process $group_1
+    assign \src120__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $3 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest120__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src120__data_o \dest120__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest220__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src120__data_o \dest220__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+        switch { $5 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+          case 1'1
+            assign \src120__data_o \reg
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+        assign \src120__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+  wire width 1 \wr_detect$7
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $8
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $9
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src220__ren
+    connect \B 1'1
+    connect \Y $8
+  end
+  process $group_2
+    assign \wr_detect$7 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $8 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        assign \wr_detect$7 1'0
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest120__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$7 1'1
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest220__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$7 1'1
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $10
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $11
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src220__ren
+    connect \B 1'1
+    connect \Y $10
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  wire width 1 $12
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  cell $not $13
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_detect$7
+    connect \Y $12
+  end
+  process $group_3
+    assign \src220__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $10 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest120__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src220__data_o \dest120__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest220__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src220__data_o \dest220__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+        switch { $12 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+          case 1'1
+            assign \src220__data_o \reg
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+        assign \src220__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+  wire width 1 \wr_detect$14
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $15
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $16
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src320__ren
+    connect \B 1'1
+    connect \Y $15
+  end
+  process $group_4
+    assign \wr_detect$14 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $15 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        assign \wr_detect$14 1'0
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest120__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$14 1'1
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest220__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$14 1'1
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $17
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $18
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src320__ren
+    connect \B 1'1
+    connect \Y $17
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  wire width 1 $19
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  cell $not $20
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_detect$14
+    connect \Y $19
+  end
+  process $group_5
+    assign \src320__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $17 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest120__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src320__data_o \dest120__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest220__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src320__data_o \dest220__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+        switch { $19 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+          case 1'1
+            assign \src320__data_o \reg
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+        assign \src320__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+  wire width 1 \wr_detect$21
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $22
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $23
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \dmi20__ren
+    connect \B 1'1
+    connect \Y $22
+  end
+  process $group_6
+    assign \wr_detect$21 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $22 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        assign \wr_detect$21 1'0
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest120__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$21 1'1
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest220__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$21 1'1
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $24
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $25
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \dmi20__ren
+    connect \B 1'1
+    connect \Y $24
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  wire width 1 $26
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  cell $not $27
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_detect$21
+    connect \Y $26
+  end
+  process $group_7
+    assign \dmi20__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $24 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest120__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \dmi20__data_o \dest120__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest220__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \dmi20__data_o \dest220__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+        switch { $26 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+          case 1'1
+            assign \dmi20__data_o \reg
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+        assign \dmi20__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+  end
+  process $group_8
+    assign \reg$next \reg
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+    switch { \dest120__wen }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+      case 1'1
+        assign \reg$next \dest120__data_i
+    end
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+    switch { \dest220__wen }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+      case 1'1
+        assign \reg$next \dest220__data_i
+    end
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
+      case 1'1
+        assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+      update \reg 64'0000000000000000000000000000000000000000000000000000000000000000
+    sync posedge \coresync_clk
+      update \reg \reg$next
+  end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.int.reg_21"
+module \reg_21
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 2 \src121__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 3 \src121__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 4 \src221__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 5 \src221__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 6 \src321__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 7 \src321__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 8 \dmi21__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 9 \dmi21__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 10 \dest121__wen
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 input 11 \dest121__data_i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 12 \dest221__wen
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 input 13 \dest221__data_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+  wire width 1 \wr_detect
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $1
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $2
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src121__ren
+    connect \B 1'1
+    connect \Y $1
+  end
+  process $group_0
+    assign \wr_detect 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $1 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        assign \wr_detect 1'0
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest121__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect 1'1
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest221__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect 1'1
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $3
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $4
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src121__ren
+    connect \B 1'1
+    connect \Y $3
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  wire width 1 $5
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  cell $not $6
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_detect
+    connect \Y $5
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
+  wire width 64 \reg
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
+  wire width 64 \reg$next
+  process $group_1
+    assign \src121__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $3 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest121__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src121__data_o \dest121__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest221__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src121__data_o \dest221__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+        switch { $5 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+          case 1'1
+            assign \src121__data_o \reg
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+        assign \src121__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+  wire width 1 \wr_detect$7
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $8
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $9
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src221__ren
+    connect \B 1'1
+    connect \Y $8
+  end
+  process $group_2
+    assign \wr_detect$7 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $8 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        assign \wr_detect$7 1'0
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest121__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$7 1'1
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest221__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$7 1'1
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $10
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $11
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src221__ren
+    connect \B 1'1
+    connect \Y $10
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  wire width 1 $12
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  cell $not $13
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_detect$7
+    connect \Y $12
+  end
+  process $group_3
+    assign \src221__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $10 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest121__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src221__data_o \dest121__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest221__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src221__data_o \dest221__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+        switch { $12 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+          case 1'1
+            assign \src221__data_o \reg
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+        assign \src221__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+  wire width 1 \wr_detect$14
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $15
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $16
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src321__ren
+    connect \B 1'1
+    connect \Y $15
+  end
+  process $group_4
+    assign \wr_detect$14 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $15 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        assign \wr_detect$14 1'0
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest121__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$14 1'1
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest221__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$14 1'1
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $17
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $18
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src321__ren
+    connect \B 1'1
+    connect \Y $17
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  wire width 1 $19
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  cell $not $20
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_detect$14
+    connect \Y $19
+  end
+  process $group_5
+    assign \src321__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $17 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest121__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src321__data_o \dest121__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest221__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src321__data_o \dest221__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+        switch { $19 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+          case 1'1
+            assign \src321__data_o \reg
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+        assign \src321__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+  wire width 1 \wr_detect$21
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $22
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $23
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \dmi21__ren
+    connect \B 1'1
+    connect \Y $22
+  end
+  process $group_6
+    assign \wr_detect$21 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $22 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        assign \wr_detect$21 1'0
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest121__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$21 1'1
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest221__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$21 1'1
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $24
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $25
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \dmi21__ren
+    connect \B 1'1
+    connect \Y $24
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  wire width 1 $26
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  cell $not $27
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_detect$21
+    connect \Y $26
+  end
+  process $group_7
+    assign \dmi21__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $24 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest121__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \dmi21__data_o \dest121__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest221__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \dmi21__data_o \dest221__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+        switch { $26 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+          case 1'1
+            assign \dmi21__data_o \reg
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+        assign \dmi21__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+  end
+  process $group_8
+    assign \reg$next \reg
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+    switch { \dest121__wen }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+      case 1'1
+        assign \reg$next \dest121__data_i
+    end
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+    switch { \dest221__wen }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+      case 1'1
+        assign \reg$next \dest221__data_i
+    end
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
+      case 1'1
+        assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+      update \reg 64'0000000000000000000000000000000000000000000000000000000000000000
+    sync posedge \coresync_clk
+      update \reg \reg$next
+  end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.int.reg_22"
+module \reg_22
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 2 \src122__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 3 \src122__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 4 \src222__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 5 \src222__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 6 \src322__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 7 \src322__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 8 \dmi22__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 9 \dmi22__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 10 \dest122__wen
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 input 11 \dest122__data_i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 12 \dest222__wen
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 input 13 \dest222__data_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+  wire width 1 \wr_detect
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $1
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $2
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src122__ren
+    connect \B 1'1
+    connect \Y $1
+  end
+  process $group_0
+    assign \wr_detect 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $1 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        assign \wr_detect 1'0
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest122__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect 1'1
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest222__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect 1'1
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $3
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $4
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src122__ren
+    connect \B 1'1
+    connect \Y $3
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  wire width 1 $5
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  cell $not $6
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_detect
+    connect \Y $5
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
+  wire width 64 \reg
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
+  wire width 64 \reg$next
+  process $group_1
+    assign \src122__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $3 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest122__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src122__data_o \dest122__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest222__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src122__data_o \dest222__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+        switch { $5 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+          case 1'1
+            assign \src122__data_o \reg
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+        assign \src122__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+  wire width 1 \wr_detect$7
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $8
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $9
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src222__ren
+    connect \B 1'1
+    connect \Y $8
+  end
+  process $group_2
+    assign \wr_detect$7 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $8 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        assign \wr_detect$7 1'0
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest122__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$7 1'1
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest222__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$7 1'1
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $10
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $11
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src222__ren
+    connect \B 1'1
+    connect \Y $10
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  wire width 1 $12
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  cell $not $13
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_detect$7
+    connect \Y $12
+  end
+  process $group_3
+    assign \src222__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $10 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest122__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src222__data_o \dest122__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest222__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src222__data_o \dest222__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+        switch { $12 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+          case 1'1
+            assign \src222__data_o \reg
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+        assign \src222__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+  wire width 1 \wr_detect$14
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $15
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $16
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src322__ren
+    connect \B 1'1
+    connect \Y $15
+  end
+  process $group_4
+    assign \wr_detect$14 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $15 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        assign \wr_detect$14 1'0
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest122__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$14 1'1
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest222__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$14 1'1
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $17
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $18
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src322__ren
+    connect \B 1'1
+    connect \Y $17
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  wire width 1 $19
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  cell $not $20
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_detect$14
+    connect \Y $19
+  end
+  process $group_5
+    assign \src322__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $17 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest122__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src322__data_o \dest122__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest222__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src322__data_o \dest222__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+        switch { $19 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+          case 1'1
+            assign \src322__data_o \reg
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+        assign \src322__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+  wire width 1 \wr_detect$21
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $22
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $23
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \dmi22__ren
+    connect \B 1'1
+    connect \Y $22
+  end
+  process $group_6
+    assign \wr_detect$21 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $22 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        assign \wr_detect$21 1'0
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest122__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$21 1'1
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest222__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$21 1'1
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $24
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $25
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \dmi22__ren
+    connect \B 1'1
+    connect \Y $24
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  wire width 1 $26
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  cell $not $27
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_detect$21
+    connect \Y $26
+  end
+  process $group_7
+    assign \dmi22__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $24 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest122__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \dmi22__data_o \dest122__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest222__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \dmi22__data_o \dest222__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+        switch { $26 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+          case 1'1
+            assign \dmi22__data_o \reg
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+        assign \dmi22__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+  end
+  process $group_8
+    assign \reg$next \reg
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+    switch { \dest122__wen }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+      case 1'1
+        assign \reg$next \dest122__data_i
+    end
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+    switch { \dest222__wen }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+      case 1'1
+        assign \reg$next \dest222__data_i
+    end
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
+      case 1'1
+        assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+      update \reg 64'0000000000000000000000000000000000000000000000000000000000000000
+    sync posedge \coresync_clk
+      update \reg \reg$next
+  end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.int.reg_23"
+module \reg_23
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 2 \src123__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 3 \src123__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 4 \src223__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 5 \src223__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 6 \src323__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 7 \src323__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 8 \dmi23__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 9 \dmi23__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 10 \dest123__wen
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 input 11 \dest123__data_i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 12 \dest223__wen
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 input 13 \dest223__data_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+  wire width 1 \wr_detect
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $1
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $2
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src123__ren
+    connect \B 1'1
+    connect \Y $1
+  end
+  process $group_0
+    assign \wr_detect 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $1 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        assign \wr_detect 1'0
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest123__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect 1'1
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest223__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect 1'1
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $3
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $4
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src123__ren
+    connect \B 1'1
+    connect \Y $3
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  wire width 1 $5
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  cell $not $6
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_detect
+    connect \Y $5
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
+  wire width 64 \reg
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
+  wire width 64 \reg$next
+  process $group_1
+    assign \src123__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $3 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest123__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src123__data_o \dest123__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest223__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src123__data_o \dest223__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+        switch { $5 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+          case 1'1
+            assign \src123__data_o \reg
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+        assign \src123__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+  wire width 1 \wr_detect$7
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $8
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $9
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src223__ren
+    connect \B 1'1
+    connect \Y $8
+  end
+  process $group_2
+    assign \wr_detect$7 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $8 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        assign \wr_detect$7 1'0
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest123__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$7 1'1
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest223__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$7 1'1
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $10
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $11
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src223__ren
+    connect \B 1'1
+    connect \Y $10
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  wire width 1 $12
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  cell $not $13
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_detect$7
+    connect \Y $12
+  end
+  process $group_3
+    assign \src223__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $10 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest123__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src223__data_o \dest123__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest223__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src223__data_o \dest223__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+        switch { $12 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+          case 1'1
+            assign \src223__data_o \reg
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+        assign \src223__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+  wire width 1 \wr_detect$14
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $15
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $16
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src323__ren
+    connect \B 1'1
+    connect \Y $15
+  end
+  process $group_4
+    assign \wr_detect$14 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $15 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        assign \wr_detect$14 1'0
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest123__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$14 1'1
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest223__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$14 1'1
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $17
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $18
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src323__ren
+    connect \B 1'1
+    connect \Y $17
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  wire width 1 $19
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  cell $not $20
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_detect$14
+    connect \Y $19
+  end
+  process $group_5
+    assign \src323__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $17 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest123__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src323__data_o \dest123__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest223__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src323__data_o \dest223__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+        switch { $19 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+          case 1'1
+            assign \src323__data_o \reg
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+        assign \src323__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+  wire width 1 \wr_detect$21
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $22
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $23
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \dmi23__ren
+    connect \B 1'1
+    connect \Y $22
+  end
+  process $group_6
+    assign \wr_detect$21 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $22 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        assign \wr_detect$21 1'0
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest123__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$21 1'1
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest223__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$21 1'1
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $24
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $25
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \dmi23__ren
+    connect \B 1'1
+    connect \Y $24
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  wire width 1 $26
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  cell $not $27
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_detect$21
+    connect \Y $26
+  end
+  process $group_7
+    assign \dmi23__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $24 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest123__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \dmi23__data_o \dest123__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest223__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \dmi23__data_o \dest223__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+        switch { $26 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+          case 1'1
+            assign \dmi23__data_o \reg
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+        assign \dmi23__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+  end
+  process $group_8
+    assign \reg$next \reg
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+    switch { \dest123__wen }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+      case 1'1
+        assign \reg$next \dest123__data_i
+    end
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+    switch { \dest223__wen }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+      case 1'1
+        assign \reg$next \dest223__data_i
+    end
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
+      case 1'1
+        assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+      update \reg 64'0000000000000000000000000000000000000000000000000000000000000000
+    sync posedge \coresync_clk
+      update \reg \reg$next
+  end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.int.reg_24"
+module \reg_24
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 2 \src124__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 3 \src124__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 4 \src224__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 5 \src224__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 6 \src324__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 7 \src324__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 8 \dmi24__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 9 \dmi24__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 10 \dest124__wen
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 input 11 \dest124__data_i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 12 \dest224__wen
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 input 13 \dest224__data_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+  wire width 1 \wr_detect
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $1
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $2
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src124__ren
+    connect \B 1'1
+    connect \Y $1
+  end
+  process $group_0
+    assign \wr_detect 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $1 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        assign \wr_detect 1'0
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest124__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect 1'1
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest224__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect 1'1
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $3
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $4
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src124__ren
+    connect \B 1'1
+    connect \Y $3
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  wire width 1 $5
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  cell $not $6
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_detect
+    connect \Y $5
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
+  wire width 64 \reg
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
+  wire width 64 \reg$next
+  process $group_1
+    assign \src124__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $3 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest124__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src124__data_o \dest124__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest224__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src124__data_o \dest224__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+        switch { $5 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+          case 1'1
+            assign \src124__data_o \reg
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+        assign \src124__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+  wire width 1 \wr_detect$7
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $8
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $9
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src224__ren
+    connect \B 1'1
+    connect \Y $8
+  end
+  process $group_2
+    assign \wr_detect$7 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $8 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        assign \wr_detect$7 1'0
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest124__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$7 1'1
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest224__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$7 1'1
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $10
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $11
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src224__ren
+    connect \B 1'1
+    connect \Y $10
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  wire width 1 $12
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  cell $not $13
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_detect$7
+    connect \Y $12
+  end
+  process $group_3
+    assign \src224__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $10 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest124__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src224__data_o \dest124__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest224__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src224__data_o \dest224__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+        switch { $12 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+          case 1'1
+            assign \src224__data_o \reg
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+        assign \src224__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+  wire width 1 \wr_detect$14
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $15
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $16
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src324__ren
+    connect \B 1'1
+    connect \Y $15
+  end
+  process $group_4
+    assign \wr_detect$14 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $15 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        assign \wr_detect$14 1'0
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest124__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$14 1'1
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest224__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$14 1'1
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $17
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $18
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src324__ren
+    connect \B 1'1
+    connect \Y $17
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  wire width 1 $19
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  cell $not $20
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_detect$14
+    connect \Y $19
+  end
+  process $group_5
+    assign \src324__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $17 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest124__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src324__data_o \dest124__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest224__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src324__data_o \dest224__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+        switch { $19 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+          case 1'1
+            assign \src324__data_o \reg
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+        assign \src324__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+  wire width 1 \wr_detect$21
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $22
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $23
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \dmi24__ren
+    connect \B 1'1
+    connect \Y $22
+  end
+  process $group_6
+    assign \wr_detect$21 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $22 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        assign \wr_detect$21 1'0
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest124__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$21 1'1
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest224__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$21 1'1
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $24
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $25
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \dmi24__ren
+    connect \B 1'1
+    connect \Y $24
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  wire width 1 $26
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  cell $not $27
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_detect$21
+    connect \Y $26
+  end
+  process $group_7
+    assign \dmi24__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $24 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest124__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \dmi24__data_o \dest124__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest224__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \dmi24__data_o \dest224__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+        switch { $26 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+          case 1'1
+            assign \dmi24__data_o \reg
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+        assign \dmi24__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+  end
+  process $group_8
+    assign \reg$next \reg
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+    switch { \dest124__wen }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+      case 1'1
+        assign \reg$next \dest124__data_i
+    end
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+    switch { \dest224__wen }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+      case 1'1
+        assign \reg$next \dest224__data_i
+    end
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
+      case 1'1
+        assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+      update \reg 64'0000000000000000000000000000000000000000000000000000000000000000
+    sync posedge \coresync_clk
+      update \reg \reg$next
+  end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.int.reg_25"
+module \reg_25
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 2 \src125__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 3 \src125__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 4 \src225__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 5 \src225__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 6 \src325__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 7 \src325__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 8 \dmi25__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 9 \dmi25__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 10 \dest125__wen
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 input 11 \dest125__data_i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 12 \dest225__wen
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 input 13 \dest225__data_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+  wire width 1 \wr_detect
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $1
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $2
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src125__ren
+    connect \B 1'1
+    connect \Y $1
+  end
+  process $group_0
+    assign \wr_detect 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $1 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        assign \wr_detect 1'0
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest125__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect 1'1
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest225__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect 1'1
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $3
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $4
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src125__ren
+    connect \B 1'1
+    connect \Y $3
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  wire width 1 $5
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  cell $not $6
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_detect
+    connect \Y $5
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
+  wire width 64 \reg
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
+  wire width 64 \reg$next
+  process $group_1
+    assign \src125__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $3 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest125__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src125__data_o \dest125__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest225__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src125__data_o \dest225__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+        switch { $5 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+          case 1'1
+            assign \src125__data_o \reg
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+        assign \src125__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+  wire width 1 \wr_detect$7
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $8
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $9
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src225__ren
+    connect \B 1'1
+    connect \Y $8
+  end
+  process $group_2
+    assign \wr_detect$7 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $8 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        assign \wr_detect$7 1'0
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest125__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$7 1'1
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest225__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$7 1'1
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $10
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $11
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src225__ren
+    connect \B 1'1
+    connect \Y $10
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  wire width 1 $12
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  cell $not $13
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_detect$7
+    connect \Y $12
+  end
+  process $group_3
+    assign \src225__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $10 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest125__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src225__data_o \dest125__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest225__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src225__data_o \dest225__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+        switch { $12 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+          case 1'1
+            assign \src225__data_o \reg
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+        assign \src225__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+  wire width 1 \wr_detect$14
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $15
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $16
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src325__ren
+    connect \B 1'1
+    connect \Y $15
+  end
+  process $group_4
+    assign \wr_detect$14 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $15 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        assign \wr_detect$14 1'0
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest125__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$14 1'1
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest225__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$14 1'1
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $17
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $18
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src325__ren
+    connect \B 1'1
+    connect \Y $17
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  wire width 1 $19
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  cell $not $20
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_detect$14
+    connect \Y $19
+  end
+  process $group_5
+    assign \src325__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $17 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest125__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src325__data_o \dest125__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest225__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src325__data_o \dest225__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+        switch { $19 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+          case 1'1
+            assign \src325__data_o \reg
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+        assign \src325__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+  wire width 1 \wr_detect$21
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $22
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $23
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \dmi25__ren
+    connect \B 1'1
+    connect \Y $22
+  end
+  process $group_6
+    assign \wr_detect$21 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $22 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        assign \wr_detect$21 1'0
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest125__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$21 1'1
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest225__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$21 1'1
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $24
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $25
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \dmi25__ren
+    connect \B 1'1
+    connect \Y $24
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  wire width 1 $26
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  cell $not $27
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_detect$21
+    connect \Y $26
+  end
+  process $group_7
+    assign \dmi25__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $24 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest125__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \dmi25__data_o \dest125__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest225__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \dmi25__data_o \dest225__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+        switch { $26 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+          case 1'1
+            assign \dmi25__data_o \reg
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+        assign \dmi25__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+  end
+  process $group_8
+    assign \reg$next \reg
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+    switch { \dest125__wen }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+      case 1'1
+        assign \reg$next \dest125__data_i
+    end
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+    switch { \dest225__wen }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+      case 1'1
+        assign \reg$next \dest225__data_i
+    end
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
+      case 1'1
+        assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+      update \reg 64'0000000000000000000000000000000000000000000000000000000000000000
+    sync posedge \coresync_clk
+      update \reg \reg$next
+  end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.int.reg_26"
+module \reg_26
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 2 \src126__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 3 \src126__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 4 \src226__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 5 \src226__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 6 \src326__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 7 \src326__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 8 \dmi26__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 9 \dmi26__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 10 \dest126__wen
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 input 11 \dest126__data_i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 12 \dest226__wen
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 input 13 \dest226__data_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+  wire width 1 \wr_detect
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $1
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $2
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src126__ren
+    connect \B 1'1
+    connect \Y $1
+  end
+  process $group_0
+    assign \wr_detect 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $1 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        assign \wr_detect 1'0
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest126__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect 1'1
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest226__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect 1'1
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $3
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $4
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src126__ren
+    connect \B 1'1
+    connect \Y $3
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  wire width 1 $5
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  cell $not $6
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_detect
+    connect \Y $5
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
+  wire width 64 \reg
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:55"
+  wire width 64 \reg$next
+  process $group_1
+    assign \src126__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $3 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest126__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src126__data_o \dest126__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest226__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src126__data_o \dest226__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+        switch { $5 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+          case 1'1
+            assign \src126__data_o \reg
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+        assign \src126__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+  wire width 1 \wr_detect$7
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $8
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $9
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src226__ren
+    connect \B 1'1
+    connect \Y $8
+  end
+  process $group_2
+    assign \wr_detect$7 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $8 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        assign \wr_detect$7 1'0
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest126__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$7 1'1
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest226__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$7 1'1
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $10
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $11
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src226__ren
+    connect \B 1'1
+    connect \Y $10
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  wire width 1 $12
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  cell $not $13
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_detect$7
+    connect \Y $12
+  end
+  process $group_3
+    assign \src226__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $10 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest126__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src226__data_o \dest126__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest226__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src226__data_o \dest226__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+        switch { $12 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+          case 1'1
+            assign \src226__data_o \reg
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+        assign \src226__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+  wire width 1 \wr_detect$14
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $15
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $16
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src326__ren
+    connect \B 1'1
+    connect \Y $15
+  end
+  process $group_4
+    assign \wr_detect$14 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $15 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        assign \wr_detect$14 1'0
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest126__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$14 1'1
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest226__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$14 1'1
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $17
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $18
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \src326__ren
+    connect \B 1'1
+    connect \Y $17
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  wire width 1 $19
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  cell $not $20
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_detect$14
+    connect \Y $19
+  end
+  process $group_5
+    assign \src326__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $17 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest126__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src326__data_o \dest126__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest226__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \src326__data_o \dest226__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+        switch { $19 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+          case 1'1
+            assign \src326__data_o \reg
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+        assign \src326__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+  wire width 1 \wr_detect$21
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $22
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $23
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \dmi26__ren
+    connect \B 1'1
+    connect \Y $22
+  end
+  process $group_6
+    assign \wr_detect$21 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $22 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        assign \wr_detect$21 1'0
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest126__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$21 1'1
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest226__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$21 1'1
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $24
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $25
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \dmi26__ren
+    connect \B 1'1
+    connect \Y $24
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  wire width 1 $26
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  cell $not $27
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_detect$21
+    connect \Y $26
+  end
+  process $group_7
+    assign \dmi26__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $24 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest126__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \dmi26__data_o \dest126__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest226__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \dmi26__data_o \dest226__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+        switch { $26 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+          case 1'1
+            assign \dmi26__data_o \reg
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+        assign \dmi26__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+  end
+  process $group_8
+    assign \reg$next \reg
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+    switch { \dest126__wen }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+      case 1'1
+        assign \reg$next \dest126__data_i
+    end
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+    switch { \dest226__wen }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
+      case 1'1
+        assign \reg$next \dest226__data_i
+    end
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
+      case 1'1
+        assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+      update \reg 64'0000000000000000000000000000000000000000000000000000000000000000
+    sync posedge \coresync_clk
+      update \reg \reg$next
+  end
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.core.int.reg_27"
+module \reg_27
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 2 \src127__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 3 \src127__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 4 \src227__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 5 \src227__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 6 \src327__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 7 \src327__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 8 \dmi27__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 9 \dmi27__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 10 \dest127__wen
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 input 11 \dest127__data_i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 12 \dest227__wen
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 input 13 \dest227__data_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+  wire width 1 \wr_detect
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $1
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $2
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
@@ -125962,7 +140538,99 @@ module \reg_27
     end
     sync init
   end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+  wire width 1 \wr_detect$21
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $22
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $23
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \dmi27__ren
+    connect \B 1'1
+    connect \Y $22
+  end
   process $group_6
+    assign \wr_detect$21 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $22 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        assign \wr_detect$21 1'0
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest127__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$21 1'1
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest227__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$21 1'1
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $24
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $25
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \dmi27__ren
+    connect \B 1'1
+    connect \Y $24
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  wire width 1 $26
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  cell $not $27
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_detect$21
+    connect \Y $26
+  end
+  process $group_7
+    assign \dmi27__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $24 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest127__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \dmi27__data_o \dest127__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest227__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \dmi27__data_o \dest227__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+        switch { $26 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+          case 1'1
+            assign \dmi27__data_o \reg
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+        assign \dmi27__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+  end
+  process $group_8
     assign \reg$next \reg
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
     switch { \dest127__wen }
@@ -125977,23 +140645,23 @@ module \reg_27
         assign \reg$next \dest227__data_i
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
     end
     sync init
       update \reg 64'0000000000000000000000000000000000000000000000000000000000000000
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \reg \reg$next
   end
 end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.int.reg_28"
 module \reg_28
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 input 2 \src128__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
@@ -126007,13 +140675,17 @@ module \reg_28
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 output 7 \src328__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 8 \dest128__wen
+  wire width 1 input 8 \dmi28__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 9 \dest128__data_i
+  wire width 64 output 9 \dmi28__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 10 \dest228__wen
+  wire width 1 input 10 \dest128__wen
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 11 \dest228__data_i
+  wire width 64 input 11 \dest128__data_i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 12 \dest228__wen
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 input 13 \dest228__data_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
   wire width 1 \wr_detect
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
@@ -126294,7 +140966,99 @@ module \reg_28
     end
     sync init
   end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+  wire width 1 \wr_detect$21
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $22
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $23
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \dmi28__ren
+    connect \B 1'1
+    connect \Y $22
+  end
   process $group_6
+    assign \wr_detect$21 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $22 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        assign \wr_detect$21 1'0
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest128__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$21 1'1
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest228__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$21 1'1
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $24
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $25
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \dmi28__ren
+    connect \B 1'1
+    connect \Y $24
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  wire width 1 $26
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  cell $not $27
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_detect$21
+    connect \Y $26
+  end
+  process $group_7
+    assign \dmi28__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $24 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest128__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \dmi28__data_o \dest128__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest228__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \dmi28__data_o \dest228__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+        switch { $26 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+          case 1'1
+            assign \dmi28__data_o \reg
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+        assign \dmi28__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+  end
+  process $group_8
     assign \reg$next \reg
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
     switch { \dest128__wen }
@@ -126309,23 +141073,23 @@ module \reg_28
         assign \reg$next \dest228__data_i
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
     end
     sync init
       update \reg 64'0000000000000000000000000000000000000000000000000000000000000000
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \reg \reg$next
   end
 end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.int.reg_29"
 module \reg_29
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 input 2 \src129__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
@@ -126339,13 +141103,17 @@ module \reg_29
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 output 7 \src329__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 8 \dest129__wen
+  wire width 1 input 8 \dmi29__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 9 \dmi29__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 9 \dest129__data_i
+  wire width 1 input 10 \dest129__wen
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 10 \dest229__wen
+  wire width 64 input 11 \dest129__data_i
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 11 \dest229__data_i
+  wire width 1 input 12 \dest229__wen
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 input 13 \dest229__data_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
   wire width 1 \wr_detect
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
@@ -126626,7 +141394,99 @@ module \reg_29
     end
     sync init
   end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+  wire width 1 \wr_detect$21
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $22
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $23
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \dmi29__ren
+    connect \B 1'1
+    connect \Y $22
+  end
   process $group_6
+    assign \wr_detect$21 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $22 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        assign \wr_detect$21 1'0
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest129__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$21 1'1
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest229__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$21 1'1
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $24
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $25
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \dmi29__ren
+    connect \B 1'1
+    connect \Y $24
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  wire width 1 $26
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  cell $not $27
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_detect$21
+    connect \Y $26
+  end
+  process $group_7
+    assign \dmi29__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $24 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest129__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \dmi29__data_o \dest129__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest229__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \dmi29__data_o \dest229__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+        switch { $26 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+          case 1'1
+            assign \dmi29__data_o \reg
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+        assign \dmi29__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+  end
+  process $group_8
     assign \reg$next \reg
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
     switch { \dest129__wen }
@@ -126641,23 +141501,23 @@ module \reg_29
         assign \reg$next \dest229__data_i
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
     end
     sync init
       update \reg 64'0000000000000000000000000000000000000000000000000000000000000000
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \reg \reg$next
   end
 end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.int.reg_30"
 module \reg_30
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 input 2 \src130__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
@@ -126671,13 +141531,17 @@ module \reg_30
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 output 7 \src330__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 8 \dest130__wen
+  wire width 1 input 8 \dmi30__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 9 \dmi30__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 10 \dest130__wen
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 9 \dest130__data_i
+  wire width 64 input 11 \dest130__data_i
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 10 \dest230__wen
+  wire width 1 input 12 \dest230__wen
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 11 \dest230__data_i
+  wire width 64 input 13 \dest230__data_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
   wire width 1 \wr_detect
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
@@ -126958,7 +141822,99 @@ module \reg_30
     end
     sync init
   end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+  wire width 1 \wr_detect$21
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $22
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $23
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \dmi30__ren
+    connect \B 1'1
+    connect \Y $22
+  end
   process $group_6
+    assign \wr_detect$21 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $22 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        assign \wr_detect$21 1'0
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest130__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$21 1'1
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest230__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$21 1'1
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $24
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $25
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \dmi30__ren
+    connect \B 1'1
+    connect \Y $24
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  wire width 1 $26
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  cell $not $27
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_detect$21
+    connect \Y $26
+  end
+  process $group_7
+    assign \dmi30__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $24 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest130__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \dmi30__data_o \dest130__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest230__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \dmi30__data_o \dest230__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+        switch { $26 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+          case 1'1
+            assign \dmi30__data_o \reg
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+        assign \dmi30__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+  end
+  process $group_8
     assign \reg$next \reg
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
     switch { \dest130__wen }
@@ -126973,23 +141929,23 @@ module \reg_30
         assign \reg$next \dest230__data_i
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
     end
     sync init
       update \reg 64'0000000000000000000000000000000000000000000000000000000000000000
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \reg \reg$next
   end
 end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.int.reg_31"
 module \reg_31
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 input 2 \src131__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
@@ -127003,13 +141959,17 @@ module \reg_31
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 output 7 \src331__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 8 \dest131__wen
+  wire width 1 input 8 \dmi31__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 9 \dest131__data_i
+  wire width 64 output 9 \dmi31__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 10 \dest231__wen
+  wire width 1 input 10 \dest131__wen
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 11 \dest231__data_i
+  wire width 64 input 11 \dest131__data_i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 input 12 \dest231__wen
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 input 13 \dest231__data_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
   wire width 1 \wr_detect
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
@@ -127290,7 +142250,99 @@ module \reg_31
     end
     sync init
   end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:61"
+  wire width 1 \wr_detect$21
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $22
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $23
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \dmi31__ren
+    connect \B 1'1
+    connect \Y $22
+  end
   process $group_6
+    assign \wr_detect$21 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $22 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        assign \wr_detect$21 1'0
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest131__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$21 1'1
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest231__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \wr_detect$21 1'1
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  wire width 1 $24
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+  cell $eq $25
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \dmi31__ren
+    connect \B 1'1
+    connect \Y $24
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  wire width 1 $26
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+  cell $not $27
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \wr_detect$21
+    connect \Y $26
+  end
+  process $group_7
+    assign \dmi31__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+    switch { $24 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest131__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \dmi31__data_o \dest131__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+        switch { \dest231__wen }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:64"
+          case 1'1
+            assign \dmi31__data_o \dest231__data_i
+        end
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+        switch { $26 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:67"
+          case 1'1
+            assign \dmi31__data_o \reg
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71"
+      case
+        assign \dmi31__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    end
+    sync init
+  end
+  process $group_8
     assign \reg$next \reg
     attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:76"
     switch { \dest131__wen }
@@ -127305,43 +142357,47 @@ module \reg_31
         assign \reg$next \dest231__data_i
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
     end
     sync init
       update \reg 64'0000000000000000000000000000000000000000000000000000000000000000
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \reg \reg$next
   end
 end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.int"
 module \int
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 32 input 1 \dmi__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 2 \dmi__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 32 input 2 \src1__ren
+  wire width 32 input 3 \src1__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 3 \src1__data_o
+  wire width 64 output 4 \src1__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 32 input 4 \src2__ren
+  wire width 32 input 5 \src2__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 5 \src2__data_o
+  wire width 64 output 6 \src2__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 32 input 6 \src3__ren
+  wire width 32 input 7 \src3__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 7 \src3__data_o
+  wire width 64 output 8 \src3__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 32 input 8 \wen
+  wire width 32 input 9 \wen
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 9 \data_i
+  wire width 64 input 10 \data_i
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 32 input 10 \wen$1
+  wire width 32 input 11 \wen$1
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 11 \data_i$2
+  wire width 64 input 12 \data_i$2
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 13 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 \reg_0_src10__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
@@ -127355,6 +142411,10 @@ module \int
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_0_src30__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 \reg_0_dmi0__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 \reg_0_dmi0__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 \reg_0_dest10__wen
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_0_dest10__data_i
@@ -127363,14 +142423,16 @@ module \int
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_0_dest20__data_i
   cell \reg_0 \reg_0
-    connect \rst \rst
-    connect \clk \clk
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
     connect \src10__ren \reg_0_src10__ren
     connect \src10__data_o \reg_0_src10__data_o
     connect \src20__ren \reg_0_src20__ren
     connect \src20__data_o \reg_0_src20__data_o
     connect \src30__ren \reg_0_src30__ren
     connect \src30__data_o \reg_0_src30__data_o
+    connect \dmi0__ren \reg_0_dmi0__ren
+    connect \dmi0__data_o \reg_0_dmi0__data_o
     connect \dest10__wen \reg_0_dest10__wen
     connect \dest10__data_i \reg_0_dest10__data_i
     connect \dest20__wen \reg_0_dest20__wen
@@ -127389,6 +142451,10 @@ module \int
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_1_src31__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 \reg_1_dmi1__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 \reg_1_dmi1__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 \reg_1_dest11__wen
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_1_dest11__data_i
@@ -127397,14 +142463,16 @@ module \int
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_1_dest21__data_i
   cell \reg_1 \reg_1
-    connect \rst \rst
-    connect \clk \clk
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
     connect \src11__ren \reg_1_src11__ren
     connect \src11__data_o \reg_1_src11__data_o
     connect \src21__ren \reg_1_src21__ren
     connect \src21__data_o \reg_1_src21__data_o
     connect \src31__ren \reg_1_src31__ren
     connect \src31__data_o \reg_1_src31__data_o
+    connect \dmi1__ren \reg_1_dmi1__ren
+    connect \dmi1__data_o \reg_1_dmi1__data_o
     connect \dest11__wen \reg_1_dest11__wen
     connect \dest11__data_i \reg_1_dest11__data_i
     connect \dest21__wen \reg_1_dest21__wen
@@ -127423,6 +142491,10 @@ module \int
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_2_src32__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 \reg_2_dmi2__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 \reg_2_dmi2__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 \reg_2_dest12__wen
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_2_dest12__data_i
@@ -127431,14 +142503,16 @@ module \int
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_2_dest22__data_i
   cell \reg_2 \reg_2
-    connect \rst \rst
-    connect \clk \clk
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
     connect \src12__ren \reg_2_src12__ren
     connect \src12__data_o \reg_2_src12__data_o
     connect \src22__ren \reg_2_src22__ren
     connect \src22__data_o \reg_2_src22__data_o
     connect \src32__ren \reg_2_src32__ren
     connect \src32__data_o \reg_2_src32__data_o
+    connect \dmi2__ren \reg_2_dmi2__ren
+    connect \dmi2__data_o \reg_2_dmi2__data_o
     connect \dest12__wen \reg_2_dest12__wen
     connect \dest12__data_i \reg_2_dest12__data_i
     connect \dest22__wen \reg_2_dest22__wen
@@ -127457,6 +142531,10 @@ module \int
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_3_src33__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 \reg_3_dmi3__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 \reg_3_dmi3__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 \reg_3_dest13__wen
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_3_dest13__data_i
@@ -127465,14 +142543,16 @@ module \int
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_3_dest23__data_i
   cell \reg_3 \reg_3
-    connect \rst \rst
-    connect \clk \clk
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
     connect \src13__ren \reg_3_src13__ren
     connect \src13__data_o \reg_3_src13__data_o
     connect \src23__ren \reg_3_src23__ren
     connect \src23__data_o \reg_3_src23__data_o
     connect \src33__ren \reg_3_src33__ren
     connect \src33__data_o \reg_3_src33__data_o
+    connect \dmi3__ren \reg_3_dmi3__ren
+    connect \dmi3__data_o \reg_3_dmi3__data_o
     connect \dest13__wen \reg_3_dest13__wen
     connect \dest13__data_i \reg_3_dest13__data_i
     connect \dest23__wen \reg_3_dest23__wen
@@ -127491,6 +142571,10 @@ module \int
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_4_src34__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 \reg_4_dmi4__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 \reg_4_dmi4__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 \reg_4_dest14__wen
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_4_dest14__data_i
@@ -127499,14 +142583,16 @@ module \int
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_4_dest24__data_i
   cell \reg_4 \reg_4
-    connect \rst \rst
-    connect \clk \clk
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
     connect \src14__ren \reg_4_src14__ren
     connect \src14__data_o \reg_4_src14__data_o
     connect \src24__ren \reg_4_src24__ren
     connect \src24__data_o \reg_4_src24__data_o
     connect \src34__ren \reg_4_src34__ren
     connect \src34__data_o \reg_4_src34__data_o
+    connect \dmi4__ren \reg_4_dmi4__ren
+    connect \dmi4__data_o \reg_4_dmi4__data_o
     connect \dest14__wen \reg_4_dest14__wen
     connect \dest14__data_i \reg_4_dest14__data_i
     connect \dest24__wen \reg_4_dest24__wen
@@ -127525,6 +142611,10 @@ module \int
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_5_src35__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 \reg_5_dmi5__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 \reg_5_dmi5__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 \reg_5_dest15__wen
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_5_dest15__data_i
@@ -127533,14 +142623,16 @@ module \int
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_5_dest25__data_i
   cell \reg_5 \reg_5
-    connect \rst \rst
-    connect \clk \clk
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
     connect \src15__ren \reg_5_src15__ren
     connect \src15__data_o \reg_5_src15__data_o
     connect \src25__ren \reg_5_src25__ren
     connect \src25__data_o \reg_5_src25__data_o
     connect \src35__ren \reg_5_src35__ren
     connect \src35__data_o \reg_5_src35__data_o
+    connect \dmi5__ren \reg_5_dmi5__ren
+    connect \dmi5__data_o \reg_5_dmi5__data_o
     connect \dest15__wen \reg_5_dest15__wen
     connect \dest15__data_i \reg_5_dest15__data_i
     connect \dest25__wen \reg_5_dest25__wen
@@ -127559,6 +142651,10 @@ module \int
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_6_src36__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 \reg_6_dmi6__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 \reg_6_dmi6__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 \reg_6_dest16__wen
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_6_dest16__data_i
@@ -127567,14 +142663,16 @@ module \int
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_6_dest26__data_i
   cell \reg_6 \reg_6
-    connect \rst \rst
-    connect \clk \clk
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
     connect \src16__ren \reg_6_src16__ren
     connect \src16__data_o \reg_6_src16__data_o
     connect \src26__ren \reg_6_src26__ren
     connect \src26__data_o \reg_6_src26__data_o
     connect \src36__ren \reg_6_src36__ren
     connect \src36__data_o \reg_6_src36__data_o
+    connect \dmi6__ren \reg_6_dmi6__ren
+    connect \dmi6__data_o \reg_6_dmi6__data_o
     connect \dest16__wen \reg_6_dest16__wen
     connect \dest16__data_i \reg_6_dest16__data_i
     connect \dest26__wen \reg_6_dest26__wen
@@ -127593,6 +142691,10 @@ module \int
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_7_src37__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 \reg_7_dmi7__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 \reg_7_dmi7__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 \reg_7_dest17__wen
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_7_dest17__data_i
@@ -127601,14 +142703,16 @@ module \int
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_7_dest27__data_i
   cell \reg_7 \reg_7
-    connect \rst \rst
-    connect \clk \clk
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
     connect \src17__ren \reg_7_src17__ren
     connect \src17__data_o \reg_7_src17__data_o
     connect \src27__ren \reg_7_src27__ren
     connect \src27__data_o \reg_7_src27__data_o
     connect \src37__ren \reg_7_src37__ren
     connect \src37__data_o \reg_7_src37__data_o
+    connect \dmi7__ren \reg_7_dmi7__ren
+    connect \dmi7__data_o \reg_7_dmi7__data_o
     connect \dest17__wen \reg_7_dest17__wen
     connect \dest17__data_i \reg_7_dest17__data_i
     connect \dest27__wen \reg_7_dest27__wen
@@ -127627,6 +142731,10 @@ module \int
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_8_src38__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 \reg_8_dmi8__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 \reg_8_dmi8__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 \reg_8_dest18__wen
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_8_dest18__data_i
@@ -127635,14 +142743,16 @@ module \int
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_8_dest28__data_i
   cell \reg_8 \reg_8
-    connect \rst \rst
-    connect \clk \clk
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
     connect \src18__ren \reg_8_src18__ren
     connect \src18__data_o \reg_8_src18__data_o
     connect \src28__ren \reg_8_src28__ren
     connect \src28__data_o \reg_8_src28__data_o
     connect \src38__ren \reg_8_src38__ren
     connect \src38__data_o \reg_8_src38__data_o
+    connect \dmi8__ren \reg_8_dmi8__ren
+    connect \dmi8__data_o \reg_8_dmi8__data_o
     connect \dest18__wen \reg_8_dest18__wen
     connect \dest18__data_i \reg_8_dest18__data_i
     connect \dest28__wen \reg_8_dest28__wen
@@ -127661,6 +142771,10 @@ module \int
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_9_src39__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 \reg_9_dmi9__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 \reg_9_dmi9__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 \reg_9_dest19__wen
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_9_dest19__data_i
@@ -127669,14 +142783,16 @@ module \int
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_9_dest29__data_i
   cell \reg_9 \reg_9
-    connect \rst \rst
-    connect \clk \clk
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
     connect \src19__ren \reg_9_src19__ren
     connect \src19__data_o \reg_9_src19__data_o
     connect \src29__ren \reg_9_src29__ren
     connect \src29__data_o \reg_9_src29__data_o
     connect \src39__ren \reg_9_src39__ren
     connect \src39__data_o \reg_9_src39__data_o
+    connect \dmi9__ren \reg_9_dmi9__ren
+    connect \dmi9__data_o \reg_9_dmi9__data_o
     connect \dest19__wen \reg_9_dest19__wen
     connect \dest19__data_i \reg_9_dest19__data_i
     connect \dest29__wen \reg_9_dest29__wen
@@ -127695,6 +142811,10 @@ module \int
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_10_src310__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 \reg_10_dmi10__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 \reg_10_dmi10__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 \reg_10_dest110__wen
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_10_dest110__data_i
@@ -127703,14 +142823,16 @@ module \int
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_10_dest210__data_i
   cell \reg_10 \reg_10
-    connect \rst \rst
-    connect \clk \clk
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
     connect \src110__ren \reg_10_src110__ren
     connect \src110__data_o \reg_10_src110__data_o
     connect \src210__ren \reg_10_src210__ren
     connect \src210__data_o \reg_10_src210__data_o
     connect \src310__ren \reg_10_src310__ren
     connect \src310__data_o \reg_10_src310__data_o
+    connect \dmi10__ren \reg_10_dmi10__ren
+    connect \dmi10__data_o \reg_10_dmi10__data_o
     connect \dest110__wen \reg_10_dest110__wen
     connect \dest110__data_i \reg_10_dest110__data_i
     connect \dest210__wen \reg_10_dest210__wen
@@ -127729,6 +142851,10 @@ module \int
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_11_src311__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 \reg_11_dmi11__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 \reg_11_dmi11__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 \reg_11_dest111__wen
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_11_dest111__data_i
@@ -127737,14 +142863,16 @@ module \int
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_11_dest211__data_i
   cell \reg_11 \reg_11
-    connect \rst \rst
-    connect \clk \clk
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
     connect \src111__ren \reg_11_src111__ren
     connect \src111__data_o \reg_11_src111__data_o
     connect \src211__ren \reg_11_src211__ren
     connect \src211__data_o \reg_11_src211__data_o
     connect \src311__ren \reg_11_src311__ren
     connect \src311__data_o \reg_11_src311__data_o
+    connect \dmi11__ren \reg_11_dmi11__ren
+    connect \dmi11__data_o \reg_11_dmi11__data_o
     connect \dest111__wen \reg_11_dest111__wen
     connect \dest111__data_i \reg_11_dest111__data_i
     connect \dest211__wen \reg_11_dest211__wen
@@ -127763,6 +142891,10 @@ module \int
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_12_src312__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 \reg_12_dmi12__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 \reg_12_dmi12__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 \reg_12_dest112__wen
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_12_dest112__data_i
@@ -127771,14 +142903,16 @@ module \int
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_12_dest212__data_i
   cell \reg_12 \reg_12
-    connect \rst \rst
-    connect \clk \clk
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
     connect \src112__ren \reg_12_src112__ren
     connect \src112__data_o \reg_12_src112__data_o
     connect \src212__ren \reg_12_src212__ren
     connect \src212__data_o \reg_12_src212__data_o
     connect \src312__ren \reg_12_src312__ren
     connect \src312__data_o \reg_12_src312__data_o
+    connect \dmi12__ren \reg_12_dmi12__ren
+    connect \dmi12__data_o \reg_12_dmi12__data_o
     connect \dest112__wen \reg_12_dest112__wen
     connect \dest112__data_i \reg_12_dest112__data_i
     connect \dest212__wen \reg_12_dest212__wen
@@ -127797,6 +142931,10 @@ module \int
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_13_src313__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 \reg_13_dmi13__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 \reg_13_dmi13__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 \reg_13_dest113__wen
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_13_dest113__data_i
@@ -127805,14 +142943,16 @@ module \int
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_13_dest213__data_i
   cell \reg_13 \reg_13
-    connect \rst \rst
-    connect \clk \clk
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
     connect \src113__ren \reg_13_src113__ren
     connect \src113__data_o \reg_13_src113__data_o
     connect \src213__ren \reg_13_src213__ren
     connect \src213__data_o \reg_13_src213__data_o
     connect \src313__ren \reg_13_src313__ren
     connect \src313__data_o \reg_13_src313__data_o
+    connect \dmi13__ren \reg_13_dmi13__ren
+    connect \dmi13__data_o \reg_13_dmi13__data_o
     connect \dest113__wen \reg_13_dest113__wen
     connect \dest113__data_i \reg_13_dest113__data_i
     connect \dest213__wen \reg_13_dest213__wen
@@ -127831,6 +142971,10 @@ module \int
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_14_src314__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 \reg_14_dmi14__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 \reg_14_dmi14__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 \reg_14_dest114__wen
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_14_dest114__data_i
@@ -127839,14 +142983,16 @@ module \int
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_14_dest214__data_i
   cell \reg_14 \reg_14
-    connect \rst \rst
-    connect \clk \clk
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
     connect \src114__ren \reg_14_src114__ren
     connect \src114__data_o \reg_14_src114__data_o
     connect \src214__ren \reg_14_src214__ren
     connect \src214__data_o \reg_14_src214__data_o
     connect \src314__ren \reg_14_src314__ren
     connect \src314__data_o \reg_14_src314__data_o
+    connect \dmi14__ren \reg_14_dmi14__ren
+    connect \dmi14__data_o \reg_14_dmi14__data_o
     connect \dest114__wen \reg_14_dest114__wen
     connect \dest114__data_i \reg_14_dest114__data_i
     connect \dest214__wen \reg_14_dest214__wen
@@ -127865,6 +143011,10 @@ module \int
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_15_src315__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 \reg_15_dmi15__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 \reg_15_dmi15__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 \reg_15_dest115__wen
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_15_dest115__data_i
@@ -127873,14 +143023,16 @@ module \int
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_15_dest215__data_i
   cell \reg_15 \reg_15
-    connect \rst \rst
-    connect \clk \clk
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
     connect \src115__ren \reg_15_src115__ren
     connect \src115__data_o \reg_15_src115__data_o
     connect \src215__ren \reg_15_src215__ren
     connect \src215__data_o \reg_15_src215__data_o
     connect \src315__ren \reg_15_src315__ren
     connect \src315__data_o \reg_15_src315__data_o
+    connect \dmi15__ren \reg_15_dmi15__ren
+    connect \dmi15__data_o \reg_15_dmi15__data_o
     connect \dest115__wen \reg_15_dest115__wen
     connect \dest115__data_i \reg_15_dest115__data_i
     connect \dest215__wen \reg_15_dest215__wen
@@ -127899,6 +143051,10 @@ module \int
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_16_src316__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 \reg_16_dmi16__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 \reg_16_dmi16__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 \reg_16_dest116__wen
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_16_dest116__data_i
@@ -127907,14 +143063,16 @@ module \int
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_16_dest216__data_i
   cell \reg_16 \reg_16
-    connect \rst \rst
-    connect \clk \clk
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
     connect \src116__ren \reg_16_src116__ren
     connect \src116__data_o \reg_16_src116__data_o
     connect \src216__ren \reg_16_src216__ren
     connect \src216__data_o \reg_16_src216__data_o
     connect \src316__ren \reg_16_src316__ren
     connect \src316__data_o \reg_16_src316__data_o
+    connect \dmi16__ren \reg_16_dmi16__ren
+    connect \dmi16__data_o \reg_16_dmi16__data_o
     connect \dest116__wen \reg_16_dest116__wen
     connect \dest116__data_i \reg_16_dest116__data_i
     connect \dest216__wen \reg_16_dest216__wen
@@ -127933,6 +143091,10 @@ module \int
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_17_src317__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 \reg_17_dmi17__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 \reg_17_dmi17__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 \reg_17_dest117__wen
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_17_dest117__data_i
@@ -127941,14 +143103,16 @@ module \int
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_17_dest217__data_i
   cell \reg_17 \reg_17
-    connect \rst \rst
-    connect \clk \clk
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
     connect \src117__ren \reg_17_src117__ren
     connect \src117__data_o \reg_17_src117__data_o
     connect \src217__ren \reg_17_src217__ren
     connect \src217__data_o \reg_17_src217__data_o
     connect \src317__ren \reg_17_src317__ren
     connect \src317__data_o \reg_17_src317__data_o
+    connect \dmi17__ren \reg_17_dmi17__ren
+    connect \dmi17__data_o \reg_17_dmi17__data_o
     connect \dest117__wen \reg_17_dest117__wen
     connect \dest117__data_i \reg_17_dest117__data_i
     connect \dest217__wen \reg_17_dest217__wen
@@ -127967,6 +143131,10 @@ module \int
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_18_src318__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 \reg_18_dmi18__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 \reg_18_dmi18__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 \reg_18_dest118__wen
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_18_dest118__data_i
@@ -127975,14 +143143,16 @@ module \int
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_18_dest218__data_i
   cell \reg_18 \reg_18
-    connect \rst \rst
-    connect \clk \clk
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
     connect \src118__ren \reg_18_src118__ren
     connect \src118__data_o \reg_18_src118__data_o
     connect \src218__ren \reg_18_src218__ren
     connect \src218__data_o \reg_18_src218__data_o
     connect \src318__ren \reg_18_src318__ren
     connect \src318__data_o \reg_18_src318__data_o
+    connect \dmi18__ren \reg_18_dmi18__ren
+    connect \dmi18__data_o \reg_18_dmi18__data_o
     connect \dest118__wen \reg_18_dest118__wen
     connect \dest118__data_i \reg_18_dest118__data_i
     connect \dest218__wen \reg_18_dest218__wen
@@ -128001,6 +143171,10 @@ module \int
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_19_src319__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 \reg_19_dmi19__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 \reg_19_dmi19__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 \reg_19_dest119__wen
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_19_dest119__data_i
@@ -128009,14 +143183,16 @@ module \int
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_19_dest219__data_i
   cell \reg_19 \reg_19
-    connect \rst \rst
-    connect \clk \clk
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
     connect \src119__ren \reg_19_src119__ren
     connect \src119__data_o \reg_19_src119__data_o
     connect \src219__ren \reg_19_src219__ren
     connect \src219__data_o \reg_19_src219__data_o
     connect \src319__ren \reg_19_src319__ren
     connect \src319__data_o \reg_19_src319__data_o
+    connect \dmi19__ren \reg_19_dmi19__ren
+    connect \dmi19__data_o \reg_19_dmi19__data_o
     connect \dest119__wen \reg_19_dest119__wen
     connect \dest119__data_i \reg_19_dest119__data_i
     connect \dest219__wen \reg_19_dest219__wen
@@ -128035,6 +143211,10 @@ module \int
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_20_src320__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 \reg_20_dmi20__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 \reg_20_dmi20__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 \reg_20_dest120__wen
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_20_dest120__data_i
@@ -128043,14 +143223,16 @@ module \int
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_20_dest220__data_i
   cell \reg_20 \reg_20
-    connect \rst \rst
-    connect \clk \clk
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
     connect \src120__ren \reg_20_src120__ren
     connect \src120__data_o \reg_20_src120__data_o
     connect \src220__ren \reg_20_src220__ren
     connect \src220__data_o \reg_20_src220__data_o
     connect \src320__ren \reg_20_src320__ren
     connect \src320__data_o \reg_20_src320__data_o
+    connect \dmi20__ren \reg_20_dmi20__ren
+    connect \dmi20__data_o \reg_20_dmi20__data_o
     connect \dest120__wen \reg_20_dest120__wen
     connect \dest120__data_i \reg_20_dest120__data_i
     connect \dest220__wen \reg_20_dest220__wen
@@ -128069,6 +143251,10 @@ module \int
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_21_src321__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 \reg_21_dmi21__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 \reg_21_dmi21__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 \reg_21_dest121__wen
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_21_dest121__data_i
@@ -128077,14 +143263,16 @@ module \int
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_21_dest221__data_i
   cell \reg_21 \reg_21
-    connect \rst \rst
-    connect \clk \clk
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
     connect \src121__ren \reg_21_src121__ren
     connect \src121__data_o \reg_21_src121__data_o
     connect \src221__ren \reg_21_src221__ren
     connect \src221__data_o \reg_21_src221__data_o
     connect \src321__ren \reg_21_src321__ren
     connect \src321__data_o \reg_21_src321__data_o
+    connect \dmi21__ren \reg_21_dmi21__ren
+    connect \dmi21__data_o \reg_21_dmi21__data_o
     connect \dest121__wen \reg_21_dest121__wen
     connect \dest121__data_i \reg_21_dest121__data_i
     connect \dest221__wen \reg_21_dest221__wen
@@ -128103,6 +143291,10 @@ module \int
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_22_src322__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 \reg_22_dmi22__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 \reg_22_dmi22__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 \reg_22_dest122__wen
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_22_dest122__data_i
@@ -128111,14 +143303,16 @@ module \int
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_22_dest222__data_i
   cell \reg_22 \reg_22
-    connect \rst \rst
-    connect \clk \clk
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
     connect \src122__ren \reg_22_src122__ren
     connect \src122__data_o \reg_22_src122__data_o
     connect \src222__ren \reg_22_src222__ren
     connect \src222__data_o \reg_22_src222__data_o
     connect \src322__ren \reg_22_src322__ren
     connect \src322__data_o \reg_22_src322__data_o
+    connect \dmi22__ren \reg_22_dmi22__ren
+    connect \dmi22__data_o \reg_22_dmi22__data_o
     connect \dest122__wen \reg_22_dest122__wen
     connect \dest122__data_i \reg_22_dest122__data_i
     connect \dest222__wen \reg_22_dest222__wen
@@ -128137,6 +143331,10 @@ module \int
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_23_src323__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 \reg_23_dmi23__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 \reg_23_dmi23__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 \reg_23_dest123__wen
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_23_dest123__data_i
@@ -128145,14 +143343,16 @@ module \int
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_23_dest223__data_i
   cell \reg_23 \reg_23
-    connect \rst \rst
-    connect \clk \clk
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
     connect \src123__ren \reg_23_src123__ren
     connect \src123__data_o \reg_23_src123__data_o
     connect \src223__ren \reg_23_src223__ren
     connect \src223__data_o \reg_23_src223__data_o
     connect \src323__ren \reg_23_src323__ren
     connect \src323__data_o \reg_23_src323__data_o
+    connect \dmi23__ren \reg_23_dmi23__ren
+    connect \dmi23__data_o \reg_23_dmi23__data_o
     connect \dest123__wen \reg_23_dest123__wen
     connect \dest123__data_i \reg_23_dest123__data_i
     connect \dest223__wen \reg_23_dest223__wen
@@ -128171,6 +143371,10 @@ module \int
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_24_src324__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 \reg_24_dmi24__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 \reg_24_dmi24__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 \reg_24_dest124__wen
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_24_dest124__data_i
@@ -128179,14 +143383,16 @@ module \int
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_24_dest224__data_i
   cell \reg_24 \reg_24
-    connect \rst \rst
-    connect \clk \clk
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
     connect \src124__ren \reg_24_src124__ren
     connect \src124__data_o \reg_24_src124__data_o
     connect \src224__ren \reg_24_src224__ren
     connect \src224__data_o \reg_24_src224__data_o
     connect \src324__ren \reg_24_src324__ren
     connect \src324__data_o \reg_24_src324__data_o
+    connect \dmi24__ren \reg_24_dmi24__ren
+    connect \dmi24__data_o \reg_24_dmi24__data_o
     connect \dest124__wen \reg_24_dest124__wen
     connect \dest124__data_i \reg_24_dest124__data_i
     connect \dest224__wen \reg_24_dest224__wen
@@ -128205,6 +143411,10 @@ module \int
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_25_src325__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 \reg_25_dmi25__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 \reg_25_dmi25__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 \reg_25_dest125__wen
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_25_dest125__data_i
@@ -128213,14 +143423,16 @@ module \int
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_25_dest225__data_i
   cell \reg_25 \reg_25
-    connect \rst \rst
-    connect \clk \clk
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
     connect \src125__ren \reg_25_src125__ren
     connect \src125__data_o \reg_25_src125__data_o
     connect \src225__ren \reg_25_src225__ren
     connect \src225__data_o \reg_25_src225__data_o
     connect \src325__ren \reg_25_src325__ren
     connect \src325__data_o \reg_25_src325__data_o
+    connect \dmi25__ren \reg_25_dmi25__ren
+    connect \dmi25__data_o \reg_25_dmi25__data_o
     connect \dest125__wen \reg_25_dest125__wen
     connect \dest125__data_i \reg_25_dest125__data_i
     connect \dest225__wen \reg_25_dest225__wen
@@ -128239,6 +143451,10 @@ module \int
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_26_src326__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 \reg_26_dmi26__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 \reg_26_dmi26__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 \reg_26_dest126__wen
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_26_dest126__data_i
@@ -128247,14 +143463,16 @@ module \int
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_26_dest226__data_i
   cell \reg_26 \reg_26
-    connect \rst \rst
-    connect \clk \clk
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
     connect \src126__ren \reg_26_src126__ren
     connect \src126__data_o \reg_26_src126__data_o
     connect \src226__ren \reg_26_src226__ren
     connect \src226__data_o \reg_26_src226__data_o
     connect \src326__ren \reg_26_src326__ren
     connect \src326__data_o \reg_26_src326__data_o
+    connect \dmi26__ren \reg_26_dmi26__ren
+    connect \dmi26__data_o \reg_26_dmi26__data_o
     connect \dest126__wen \reg_26_dest126__wen
     connect \dest126__data_i \reg_26_dest126__data_i
     connect \dest226__wen \reg_26_dest226__wen
@@ -128273,6 +143491,10 @@ module \int
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_27_src327__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 \reg_27_dmi27__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 \reg_27_dmi27__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 \reg_27_dest127__wen
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_27_dest127__data_i
@@ -128281,14 +143503,16 @@ module \int
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_27_dest227__data_i
   cell \reg_27 \reg_27
-    connect \rst \rst
-    connect \clk \clk
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
     connect \src127__ren \reg_27_src127__ren
     connect \src127__data_o \reg_27_src127__data_o
     connect \src227__ren \reg_27_src227__ren
     connect \src227__data_o \reg_27_src227__data_o
     connect \src327__ren \reg_27_src327__ren
     connect \src327__data_o \reg_27_src327__data_o
+    connect \dmi27__ren \reg_27_dmi27__ren
+    connect \dmi27__data_o \reg_27_dmi27__data_o
     connect \dest127__wen \reg_27_dest127__wen
     connect \dest127__data_i \reg_27_dest127__data_i
     connect \dest227__wen \reg_27_dest227__wen
@@ -128307,6 +143531,10 @@ module \int
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_28_src328__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 \reg_28_dmi28__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 \reg_28_dmi28__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 \reg_28_dest128__wen
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_28_dest128__data_i
@@ -128315,14 +143543,16 @@ module \int
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_28_dest228__data_i
   cell \reg_28 \reg_28
-    connect \rst \rst
-    connect \clk \clk
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
     connect \src128__ren \reg_28_src128__ren
     connect \src128__data_o \reg_28_src128__data_o
     connect \src228__ren \reg_28_src228__ren
     connect \src228__data_o \reg_28_src228__data_o
     connect \src328__ren \reg_28_src328__ren
     connect \src328__data_o \reg_28_src328__data_o
+    connect \dmi28__ren \reg_28_dmi28__ren
+    connect \dmi28__data_o \reg_28_dmi28__data_o
     connect \dest128__wen \reg_28_dest128__wen
     connect \dest128__data_i \reg_28_dest128__data_i
     connect \dest228__wen \reg_28_dest228__wen
@@ -128341,6 +143571,10 @@ module \int
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_29_src329__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 \reg_29_dmi29__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 \reg_29_dmi29__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 \reg_29_dest129__wen
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_29_dest129__data_i
@@ -128349,14 +143583,16 @@ module \int
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_29_dest229__data_i
   cell \reg_29 \reg_29
-    connect \rst \rst
-    connect \clk \clk
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
     connect \src129__ren \reg_29_src129__ren
     connect \src129__data_o \reg_29_src129__data_o
     connect \src229__ren \reg_29_src229__ren
     connect \src229__data_o \reg_29_src229__data_o
     connect \src329__ren \reg_29_src329__ren
     connect \src329__data_o \reg_29_src329__data_o
+    connect \dmi29__ren \reg_29_dmi29__ren
+    connect \dmi29__data_o \reg_29_dmi29__data_o
     connect \dest129__wen \reg_29_dest129__wen
     connect \dest129__data_i \reg_29_dest129__data_i
     connect \dest229__wen \reg_29_dest229__wen
@@ -128375,6 +143611,10 @@ module \int
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_30_src330__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 \reg_30_dmi30__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 \reg_30_dmi30__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 \reg_30_dest130__wen
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_30_dest130__data_i
@@ -128383,14 +143623,16 @@ module \int
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_30_dest230__data_i
   cell \reg_30 \reg_30
-    connect \rst \rst
-    connect \clk \clk
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
     connect \src130__ren \reg_30_src130__ren
     connect \src130__data_o \reg_30_src130__data_o
     connect \src230__ren \reg_30_src230__ren
     connect \src230__data_o \reg_30_src230__data_o
     connect \src330__ren \reg_30_src330__ren
     connect \src330__data_o \reg_30_src330__data_o
+    connect \dmi30__ren \reg_30_dmi30__ren
+    connect \dmi30__data_o \reg_30_dmi30__data_o
     connect \dest130__wen \reg_30_dest130__wen
     connect \dest130__data_i \reg_30_dest130__data_i
     connect \dest230__wen \reg_30_dest230__wen
@@ -128409,6 +143651,10 @@ module \int
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_31_src331__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 \reg_31_dmi31__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 \reg_31_dmi31__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 \reg_31_dest131__wen
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_31_dest131__data_i
@@ -128417,14 +143663,16 @@ module \int
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_31_dest231__data_i
   cell \reg_31 \reg_31
-    connect \rst \rst
-    connect \clk \clk
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
     connect \src131__ren \reg_31_src131__ren
     connect \src131__data_o \reg_31_src131__data_o
     connect \src231__ren \reg_31_src231__ren
     connect \src231__data_o \reg_31_src231__data_o
     connect \src331__ren \reg_31_src331__ren
     connect \src331__data_o \reg_31_src331__data_o
+    connect \dmi31__ren \reg_31_dmi31__ren
+    connect \dmi31__data_o \reg_31_dmi31__data_o
     connect \dest131__wen \reg_31_dest131__wen
     connect \dest131__data_i \reg_31_dest131__data_i
     connect \dest231__wen \reg_31_dest231__wen
@@ -129763,6 +145011,450 @@ module \int
     sync init
   end
   process $group_99
+    assign \reg_0_dmi0__ren 1'0
+    assign \reg_1_dmi1__ren 1'0
+    assign \reg_2_dmi2__ren 1'0
+    assign \reg_3_dmi3__ren 1'0
+    assign \reg_4_dmi4__ren 1'0
+    assign \reg_5_dmi5__ren 1'0
+    assign \reg_6_dmi6__ren 1'0
+    assign \reg_7_dmi7__ren 1'0
+    assign \reg_8_dmi8__ren 1'0
+    assign \reg_9_dmi9__ren 1'0
+    assign \reg_10_dmi10__ren 1'0
+    assign \reg_11_dmi11__ren 1'0
+    assign \reg_12_dmi12__ren 1'0
+    assign \reg_13_dmi13__ren 1'0
+    assign \reg_14_dmi14__ren 1'0
+    assign \reg_15_dmi15__ren 1'0
+    assign \reg_16_dmi16__ren 1'0
+    assign \reg_17_dmi17__ren 1'0
+    assign \reg_18_dmi18__ren 1'0
+    assign \reg_19_dmi19__ren 1'0
+    assign \reg_20_dmi20__ren 1'0
+    assign \reg_21_dmi21__ren 1'0
+    assign \reg_22_dmi22__ren 1'0
+    assign \reg_23_dmi23__ren 1'0
+    assign \reg_24_dmi24__ren 1'0
+    assign \reg_25_dmi25__ren 1'0
+    assign \reg_26_dmi26__ren 1'0
+    assign \reg_27_dmi27__ren 1'0
+    assign \reg_28_dmi28__ren 1'0
+    assign \reg_29_dmi29__ren 1'0
+    assign \reg_30_dmi30__ren 1'0
+    assign \reg_31_dmi31__ren 1'0
+    assign { \reg_31_dmi31__ren \reg_30_dmi30__ren \reg_29_dmi29__ren \reg_28_dmi28__ren \reg_27_dmi27__ren \reg_26_dmi26__ren \reg_25_dmi25__ren \reg_24_dmi24__ren \reg_23_dmi23__ren \reg_22_dmi22__ren \reg_21_dmi21__ren \reg_20_dmi20__ren \reg_19_dmi19__ren \reg_18_dmi18__ren \reg_17_dmi17__ren \reg_16_dmi16__ren \reg_15_dmi15__ren \reg_14_dmi14__ren \reg_13_dmi13__ren \reg_12_dmi12__ren \reg_11_dmi11__ren \reg_10_dmi10__ren \reg_9_dmi9__ren \reg_8_dmi8__ren \reg_7_dmi7__ren \reg_6_dmi6__ren \reg_5_dmi5__ren \reg_4_dmi4__ren \reg_3_dmi3__ren \reg_2_dmi2__ren \reg_1_dmi1__ren \reg_0_dmi0__ren } \dmi__ren
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+  wire width 64 $189
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+  cell $or $190
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 64
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 64
+    parameter \Y_WIDTH 64
+    connect \A \reg_0_dmi0__data_o
+    connect \B \reg_1_dmi1__data_o
+    connect \Y $189
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+  wire width 64 $191
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+  cell $or $192
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 64
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 64
+    parameter \Y_WIDTH 64
+    connect \A \reg_2_dmi2__data_o
+    connect \B \reg_3_dmi3__data_o
+    connect \Y $191
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+  wire width 64 $193
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+  cell $or $194
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 64
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 64
+    parameter \Y_WIDTH 64
+    connect \A $189
+    connect \B $191
+    connect \Y $193
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+  wire width 64 $195
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+  cell $or $196
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 64
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 64
+    parameter \Y_WIDTH 64
+    connect \A \reg_4_dmi4__data_o
+    connect \B \reg_5_dmi5__data_o
+    connect \Y $195
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+  wire width 64 $197
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+  cell $or $198
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 64
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 64
+    parameter \Y_WIDTH 64
+    connect \A \reg_6_dmi6__data_o
+    connect \B \reg_7_dmi7__data_o
+    connect \Y $197
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+  wire width 64 $199
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+  cell $or $200
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 64
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 64
+    parameter \Y_WIDTH 64
+    connect \A $195
+    connect \B $197
+    connect \Y $199
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+  wire width 64 $201
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+  cell $or $202
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 64
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 64
+    parameter \Y_WIDTH 64
+    connect \A $193
+    connect \B $199
+    connect \Y $201
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+  wire width 64 $203
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+  cell $or $204
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 64
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 64
+    parameter \Y_WIDTH 64
+    connect \A \reg_8_dmi8__data_o
+    connect \B \reg_9_dmi9__data_o
+    connect \Y $203
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+  wire width 64 $205
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+  cell $or $206
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 64
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 64
+    parameter \Y_WIDTH 64
+    connect \A \reg_10_dmi10__data_o
+    connect \B \reg_11_dmi11__data_o
+    connect \Y $205
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+  wire width 64 $207
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+  cell $or $208
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 64
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 64
+    parameter \Y_WIDTH 64
+    connect \A $203
+    connect \B $205
+    connect \Y $207
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+  wire width 64 $209
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+  cell $or $210
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 64
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 64
+    parameter \Y_WIDTH 64
+    connect \A \reg_12_dmi12__data_o
+    connect \B \reg_13_dmi13__data_o
+    connect \Y $209
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+  wire width 64 $211
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+  cell $or $212
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 64
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 64
+    parameter \Y_WIDTH 64
+    connect \A \reg_14_dmi14__data_o
+    connect \B \reg_15_dmi15__data_o
+    connect \Y $211
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+  wire width 64 $213
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+  cell $or $214
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 64
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 64
+    parameter \Y_WIDTH 64
+    connect \A $209
+    connect \B $211
+    connect \Y $213
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+  wire width 64 $215
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+  cell $or $216
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 64
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 64
+    parameter \Y_WIDTH 64
+    connect \A $207
+    connect \B $213
+    connect \Y $215
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+  wire width 64 $217
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+  cell $or $218
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 64
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 64
+    parameter \Y_WIDTH 64
+    connect \A $201
+    connect \B $215
+    connect \Y $217
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+  wire width 64 $219
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+  cell $or $220
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 64
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 64
+    parameter \Y_WIDTH 64
+    connect \A \reg_16_dmi16__data_o
+    connect \B \reg_17_dmi17__data_o
+    connect \Y $219
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+  wire width 64 $221
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+  cell $or $222
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 64
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 64
+    parameter \Y_WIDTH 64
+    connect \A \reg_18_dmi18__data_o
+    connect \B \reg_19_dmi19__data_o
+    connect \Y $221
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+  wire width 64 $223
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+  cell $or $224
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 64
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 64
+    parameter \Y_WIDTH 64
+    connect \A $219
+    connect \B $221
+    connect \Y $223
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+  wire width 64 $225
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+  cell $or $226
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 64
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 64
+    parameter \Y_WIDTH 64
+    connect \A \reg_20_dmi20__data_o
+    connect \B \reg_21_dmi21__data_o
+    connect \Y $225
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+  wire width 64 $227
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+  cell $or $228
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 64
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 64
+    parameter \Y_WIDTH 64
+    connect \A \reg_22_dmi22__data_o
+    connect \B \reg_23_dmi23__data_o
+    connect \Y $227
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+  wire width 64 $229
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+  cell $or $230
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 64
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 64
+    parameter \Y_WIDTH 64
+    connect \A $225
+    connect \B $227
+    connect \Y $229
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+  wire width 64 $231
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+  cell $or $232
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 64
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 64
+    parameter \Y_WIDTH 64
+    connect \A $223
+    connect \B $229
+    connect \Y $231
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+  wire width 64 $233
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+  cell $or $234
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 64
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 64
+    parameter \Y_WIDTH 64
+    connect \A \reg_24_dmi24__data_o
+    connect \B \reg_25_dmi25__data_o
+    connect \Y $233
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+  wire width 64 $235
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+  cell $or $236
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 64
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 64
+    parameter \Y_WIDTH 64
+    connect \A \reg_26_dmi26__data_o
+    connect \B \reg_27_dmi27__data_o
+    connect \Y $235
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+  wire width 64 $237
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+  cell $or $238
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 64
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 64
+    parameter \Y_WIDTH 64
+    connect \A $233
+    connect \B $235
+    connect \Y $237
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+  wire width 64 $239
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+  cell $or $240
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 64
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 64
+    parameter \Y_WIDTH 64
+    connect \A \reg_28_dmi28__data_o
+    connect \B \reg_29_dmi29__data_o
+    connect \Y $239
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+  wire width 64 $241
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+  cell $or $242
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 64
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 64
+    parameter \Y_WIDTH 64
+    connect \A \reg_30_dmi30__data_o
+    connect \B \reg_31_dmi31__data_o
+    connect \Y $241
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+  wire width 64 $243
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+  cell $or $244
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 64
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 64
+    parameter \Y_WIDTH 64
+    connect \A $239
+    connect \B $241
+    connect \Y $243
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+  wire width 64 $245
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+  cell $or $246
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 64
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 64
+    parameter \Y_WIDTH 64
+    connect \A $237
+    connect \B $243
+    connect \Y $245
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+  wire width 64 $247
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+  cell $or $248
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 64
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 64
+    parameter \Y_WIDTH 64
+    connect \A $231
+    connect \B $245
+    connect \Y $247
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+  wire width 64 $249
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+  cell $or $250
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 64
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 64
+    parameter \Y_WIDTH 64
+    connect \A $217
+    connect \B $247
+    connect \Y $249
+  end
+  process $group_131
+    assign \dmi__data_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \dmi__data_o $249
+    sync init
+  end
+  process $group_132
     assign \reg_0_dest10__wen 1'0
     assign \reg_1_dest11__wen 1'0
     assign \reg_2_dest12__wen 1'0
@@ -129798,167 +145490,167 @@ module \int
     assign { \reg_31_dest131__wen \reg_30_dest130__wen \reg_29_dest129__wen \reg_28_dest128__wen \reg_27_dest127__wen \reg_26_dest126__wen \reg_25_dest125__wen \reg_24_dest124__wen \reg_23_dest123__wen \reg_22_dest122__wen \reg_21_dest121__wen \reg_20_dest120__wen \reg_19_dest119__wen \reg_18_dest118__wen \reg_17_dest117__wen \reg_16_dest116__wen \reg_15_dest115__wen \reg_14_dest114__wen \reg_13_dest113__wen \reg_12_dest112__wen \reg_11_dest111__wen \reg_10_dest110__wen \reg_9_dest19__wen \reg_8_dest18__wen \reg_7_dest17__wen \reg_6_dest16__wen \reg_5_dest15__wen \reg_4_dest14__wen \reg_3_dest13__wen \reg_2_dest12__wen \reg_1_dest11__wen \reg_0_dest10__wen } \wen
     sync init
   end
-  process $group_131
+  process $group_164
     assign \reg_0_dest10__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
     assign \reg_0_dest10__data_i \data_i
     sync init
   end
-  process $group_132
+  process $group_165
     assign \reg_1_dest11__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
     assign \reg_1_dest11__data_i \data_i
     sync init
   end
-  process $group_133
+  process $group_166
     assign \reg_2_dest12__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
     assign \reg_2_dest12__data_i \data_i
     sync init
   end
-  process $group_134
+  process $group_167
     assign \reg_3_dest13__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
     assign \reg_3_dest13__data_i \data_i
     sync init
   end
-  process $group_135
+  process $group_168
     assign \reg_4_dest14__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
     assign \reg_4_dest14__data_i \data_i
     sync init
   end
-  process $group_136
+  process $group_169
     assign \reg_5_dest15__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
     assign \reg_5_dest15__data_i \data_i
     sync init
   end
-  process $group_137
+  process $group_170
     assign \reg_6_dest16__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
     assign \reg_6_dest16__data_i \data_i
     sync init
   end
-  process $group_138
+  process $group_171
     assign \reg_7_dest17__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
     assign \reg_7_dest17__data_i \data_i
     sync init
   end
-  process $group_139
+  process $group_172
     assign \reg_8_dest18__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
     assign \reg_8_dest18__data_i \data_i
     sync init
   end
-  process $group_140
+  process $group_173
     assign \reg_9_dest19__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
     assign \reg_9_dest19__data_i \data_i
     sync init
   end
-  process $group_141
+  process $group_174
     assign \reg_10_dest110__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
     assign \reg_10_dest110__data_i \data_i
     sync init
   end
-  process $group_142
+  process $group_175
     assign \reg_11_dest111__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
     assign \reg_11_dest111__data_i \data_i
     sync init
   end
-  process $group_143
+  process $group_176
     assign \reg_12_dest112__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
     assign \reg_12_dest112__data_i \data_i
     sync init
   end
-  process $group_144
+  process $group_177
     assign \reg_13_dest113__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
     assign \reg_13_dest113__data_i \data_i
     sync init
   end
-  process $group_145
+  process $group_178
     assign \reg_14_dest114__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
     assign \reg_14_dest114__data_i \data_i
     sync init
   end
-  process $group_146
+  process $group_179
     assign \reg_15_dest115__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
     assign \reg_15_dest115__data_i \data_i
     sync init
   end
-  process $group_147
+  process $group_180
     assign \reg_16_dest116__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
     assign \reg_16_dest116__data_i \data_i
     sync init
   end
-  process $group_148
+  process $group_181
     assign \reg_17_dest117__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
     assign \reg_17_dest117__data_i \data_i
     sync init
   end
-  process $group_149
+  process $group_182
     assign \reg_18_dest118__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
     assign \reg_18_dest118__data_i \data_i
     sync init
   end
-  process $group_150
+  process $group_183
     assign \reg_19_dest119__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
     assign \reg_19_dest119__data_i \data_i
     sync init
   end
-  process $group_151
+  process $group_184
     assign \reg_20_dest120__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
     assign \reg_20_dest120__data_i \data_i
     sync init
   end
-  process $group_152
+  process $group_185
     assign \reg_21_dest121__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
     assign \reg_21_dest121__data_i \data_i
     sync init
   end
-  process $group_153
+  process $group_186
     assign \reg_22_dest122__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
     assign \reg_22_dest122__data_i \data_i
     sync init
   end
-  process $group_154
+  process $group_187
     assign \reg_23_dest123__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
     assign \reg_23_dest123__data_i \data_i
     sync init
   end
-  process $group_155
+  process $group_188
     assign \reg_24_dest124__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
     assign \reg_24_dest124__data_i \data_i
     sync init
   end
-  process $group_156
+  process $group_189
     assign \reg_25_dest125__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
     assign \reg_25_dest125__data_i \data_i
     sync init
   end
-  process $group_157
+  process $group_190
     assign \reg_26_dest126__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
     assign \reg_26_dest126__data_i \data_i
     sync init
   end
-  process $group_158
+  process $group_191
     assign \reg_27_dest127__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
     assign \reg_27_dest127__data_i \data_i
     sync init
   end
-  process $group_159
+  process $group_192
     assign \reg_28_dest128__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
     assign \reg_28_dest128__data_i \data_i
     sync init
   end
-  process $group_160
+  process $group_193
     assign \reg_29_dest129__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
     assign \reg_29_dest129__data_i \data_i
     sync init
   end
-  process $group_161
+  process $group_194
     assign \reg_30_dest130__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
     assign \reg_30_dest130__data_i \data_i
     sync init
   end
-  process $group_162
+  process $group_195
     assign \reg_31_dest131__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
     assign \reg_31_dest131__data_i \data_i
     sync init
   end
-  process $group_163
+  process $group_196
     assign \reg_0_dest20__wen 1'0
     assign \reg_1_dest21__wen 1'0
     assign \reg_2_dest22__wen 1'0
@@ -129994,162 +145686,162 @@ module \int
     assign { \reg_31_dest231__wen \reg_30_dest230__wen \reg_29_dest229__wen \reg_28_dest228__wen \reg_27_dest227__wen \reg_26_dest226__wen \reg_25_dest225__wen \reg_24_dest224__wen \reg_23_dest223__wen \reg_22_dest222__wen \reg_21_dest221__wen \reg_20_dest220__wen \reg_19_dest219__wen \reg_18_dest218__wen \reg_17_dest217__wen \reg_16_dest216__wen \reg_15_dest215__wen \reg_14_dest214__wen \reg_13_dest213__wen \reg_12_dest212__wen \reg_11_dest211__wen \reg_10_dest210__wen \reg_9_dest29__wen \reg_8_dest28__wen \reg_7_dest27__wen \reg_6_dest26__wen \reg_5_dest25__wen \reg_4_dest24__wen \reg_3_dest23__wen \reg_2_dest22__wen \reg_1_dest21__wen \reg_0_dest20__wen } \wen$1
     sync init
   end
-  process $group_195
+  process $group_228
     assign \reg_0_dest20__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
     assign \reg_0_dest20__data_i \data_i$2
     sync init
   end
-  process $group_196
+  process $group_229
     assign \reg_1_dest21__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
     assign \reg_1_dest21__data_i \data_i$2
     sync init
   end
-  process $group_197
+  process $group_230
     assign \reg_2_dest22__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
     assign \reg_2_dest22__data_i \data_i$2
     sync init
   end
-  process $group_198
+  process $group_231
     assign \reg_3_dest23__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
     assign \reg_3_dest23__data_i \data_i$2
     sync init
   end
-  process $group_199
+  process $group_232
     assign \reg_4_dest24__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
     assign \reg_4_dest24__data_i \data_i$2
     sync init
   end
-  process $group_200
+  process $group_233
     assign \reg_5_dest25__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
     assign \reg_5_dest25__data_i \data_i$2
     sync init
   end
-  process $group_201
+  process $group_234
     assign \reg_6_dest26__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
     assign \reg_6_dest26__data_i \data_i$2
     sync init
   end
-  process $group_202
+  process $group_235
     assign \reg_7_dest27__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
     assign \reg_7_dest27__data_i \data_i$2
     sync init
   end
-  process $group_203
+  process $group_236
     assign \reg_8_dest28__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
     assign \reg_8_dest28__data_i \data_i$2
     sync init
   end
-  process $group_204
+  process $group_237
     assign \reg_9_dest29__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
     assign \reg_9_dest29__data_i \data_i$2
     sync init
   end
-  process $group_205
+  process $group_238
     assign \reg_10_dest210__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
     assign \reg_10_dest210__data_i \data_i$2
     sync init
   end
-  process $group_206
+  process $group_239
     assign \reg_11_dest211__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
     assign \reg_11_dest211__data_i \data_i$2
     sync init
   end
-  process $group_207
+  process $group_240
     assign \reg_12_dest212__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
     assign \reg_12_dest212__data_i \data_i$2
     sync init
   end
-  process $group_208
+  process $group_241
     assign \reg_13_dest213__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
     assign \reg_13_dest213__data_i \data_i$2
     sync init
   end
-  process $group_209
+  process $group_242
     assign \reg_14_dest214__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
     assign \reg_14_dest214__data_i \data_i$2
     sync init
   end
-  process $group_210
+  process $group_243
     assign \reg_15_dest215__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
     assign \reg_15_dest215__data_i \data_i$2
     sync init
   end
-  process $group_211
+  process $group_244
     assign \reg_16_dest216__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
     assign \reg_16_dest216__data_i \data_i$2
     sync init
   end
-  process $group_212
+  process $group_245
     assign \reg_17_dest217__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
     assign \reg_17_dest217__data_i \data_i$2
     sync init
   end
-  process $group_213
+  process $group_246
     assign \reg_18_dest218__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
     assign \reg_18_dest218__data_i \data_i$2
     sync init
   end
-  process $group_214
+  process $group_247
     assign \reg_19_dest219__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
     assign \reg_19_dest219__data_i \data_i$2
     sync init
   end
-  process $group_215
+  process $group_248
     assign \reg_20_dest220__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
     assign \reg_20_dest220__data_i \data_i$2
     sync init
   end
-  process $group_216
+  process $group_249
     assign \reg_21_dest221__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
     assign \reg_21_dest221__data_i \data_i$2
     sync init
   end
-  process $group_217
+  process $group_250
     assign \reg_22_dest222__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
     assign \reg_22_dest222__data_i \data_i$2
     sync init
   end
-  process $group_218
+  process $group_251
     assign \reg_23_dest223__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
     assign \reg_23_dest223__data_i \data_i$2
     sync init
   end
-  process $group_219
+  process $group_252
     assign \reg_24_dest224__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
     assign \reg_24_dest224__data_i \data_i$2
     sync init
   end
-  process $group_220
+  process $group_253
     assign \reg_25_dest225__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
     assign \reg_25_dest225__data_i \data_i$2
     sync init
   end
-  process $group_221
+  process $group_254
     assign \reg_26_dest226__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
     assign \reg_26_dest226__data_i \data_i$2
     sync init
   end
-  process $group_222
+  process $group_255
     assign \reg_27_dest227__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
     assign \reg_27_dest227__data_i \data_i$2
     sync init
   end
-  process $group_223
+  process $group_256
     assign \reg_28_dest228__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
     assign \reg_28_dest228__data_i \data_i$2
     sync init
   end
-  process $group_224
+  process $group_257
     assign \reg_29_dest229__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
     assign \reg_29_dest229__data_i \data_i$2
     sync init
   end
-  process $group_225
+  process $group_258
     assign \reg_30_dest230__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
     assign \reg_30_dest230__data_i \data_i$2
     sync init
   end
-  process $group_226
+  process $group_259
     assign \reg_31_dest231__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
     assign \reg_31_dest231__data_i \data_i$2
     sync init
@@ -130157,11 +145849,11 @@ module \int
 end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.cr.reg_0"
-module \reg_0$108
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
+module \reg_0$125
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 input 2 \src10__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
@@ -130631,23 +146323,23 @@ module \reg_0$108
         assign \reg$next \w0__data_i
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \reg$next 4'0000
     end
     sync init
       update \reg 4'0000
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \reg \reg$next
   end
 end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.cr.reg_1"
-module \reg_1$109
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
+module \reg_1$126
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 input 2 \src11__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
@@ -131117,23 +146809,23 @@ module \reg_1$109
         assign \reg$next \w1__data_i
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \reg$next 4'0000
     end
     sync init
       update \reg 4'0000
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \reg \reg$next
   end
 end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.cr.reg_2"
-module \reg_2$110
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
+module \reg_2$127
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 input 2 \src12__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
@@ -131603,23 +147295,23 @@ module \reg_2$110
         assign \reg$next \w2__data_i
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \reg$next 4'0000
     end
     sync init
       update \reg 4'0000
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \reg \reg$next
   end
 end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.cr.reg_3"
-module \reg_3$111
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
+module \reg_3$128
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 input 2 \src13__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
@@ -132089,23 +147781,23 @@ module \reg_3$111
         assign \reg$next \w3__data_i
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \reg$next 4'0000
     end
     sync init
       update \reg 4'0000
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \reg \reg$next
   end
 end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.cr.reg_4"
-module \reg_4$112
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
+module \reg_4$129
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 input 2 \src14__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
@@ -132575,23 +148267,23 @@ module \reg_4$112
         assign \reg$next \w4__data_i
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \reg$next 4'0000
     end
     sync init
       update \reg 4'0000
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \reg \reg$next
   end
 end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.cr.reg_5"
-module \reg_5$113
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
+module \reg_5$130
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 input 2 \src15__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
@@ -133061,23 +148753,23 @@ module \reg_5$113
         assign \reg$next \w5__data_i
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \reg$next 4'0000
     end
     sync init
       update \reg 4'0000
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \reg \reg$next
   end
 end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.cr.reg_6"
-module \reg_6$114
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
+module \reg_6$131
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 input 2 \src16__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
@@ -133547,23 +149239,23 @@ module \reg_6$114
         assign \reg$next \w6__data_i
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \reg$next 4'0000
     end
     sync init
       update \reg 4'0000
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \reg \reg$next
   end
 end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.cr.reg_7"
-module \reg_7$115
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
+module \reg_7$132
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 input 2 \src17__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
@@ -134033,47 +149725,47 @@ module \reg_7$115
         assign \reg$next \w7__data_i
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \reg$next 4'0000
     end
     sync init
       update \reg 4'0000
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \reg \reg$next
   end
 end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.cr"
 module \cr
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 8 input 2 \full_rd__ren
+  wire width 8 input 1 \full_rd__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 32 output 3 \full_rd__data_o
+  wire width 32 output 2 \full_rd__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 8 input 4 \src1__ren
+  wire width 8 input 3 \src1__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 4 output 5 \src1__data_o
+  wire width 4 output 4 \src1__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 8 input 6 \src2__ren
+  wire width 8 input 5 \src2__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 4 output 7 \src2__data_o
+  wire width 4 output 6 \src2__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 8 input 8 \src3__ren
+  wire width 8 input 7 \src3__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 4 output 9 \src3__data_o
+  wire width 4 output 8 \src3__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 8 input 10 \full_wr__wen
+  wire width 8 input 9 \full_wr__wen
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 32 input 11 \full_wr__data_i
+  wire width 32 input 10 \full_wr__data_i
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 8 input 12 \wen
+  wire width 8 input 11 \wen
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 4 input 13 \data_i
+  wire width 4 input 12 \data_i
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 13 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 \reg_0_src10__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
@@ -134102,9 +149794,9 @@ module \cr
   wire width 4 \reg_0_w0__data_i
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 \reg_0_w0__wen
-  cell \reg_0$108 \reg_0
-    connect \rst \rst
-    connect \clk \clk
+  cell \reg_0$125 \reg_0
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
     connect \src10__ren \reg_0_src10__ren
     connect \src10__data_o \reg_0_src10__data_o
     connect \src20__ren \reg_0_src20__ren
@@ -134148,9 +149840,9 @@ module \cr
   wire width 4 \reg_1_w1__data_i
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 \reg_1_w1__wen
-  cell \reg_1$109 \reg_1
-    connect \rst \rst
-    connect \clk \clk
+  cell \reg_1$126 \reg_1
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
     connect \src11__ren \reg_1_src11__ren
     connect \src11__data_o \reg_1_src11__data_o
     connect \src21__ren \reg_1_src21__ren
@@ -134194,9 +149886,9 @@ module \cr
   wire width 4 \reg_2_w2__data_i
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 \reg_2_w2__wen
-  cell \reg_2$110 \reg_2
-    connect \rst \rst
-    connect \clk \clk
+  cell \reg_2$127 \reg_2
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
     connect \src12__ren \reg_2_src12__ren
     connect \src12__data_o \reg_2_src12__data_o
     connect \src22__ren \reg_2_src22__ren
@@ -134240,9 +149932,9 @@ module \cr
   wire width 4 \reg_3_w3__data_i
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 \reg_3_w3__wen
-  cell \reg_3$111 \reg_3
-    connect \rst \rst
-    connect \clk \clk
+  cell \reg_3$128 \reg_3
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
     connect \src13__ren \reg_3_src13__ren
     connect \src13__data_o \reg_3_src13__data_o
     connect \src23__ren \reg_3_src23__ren
@@ -134286,9 +149978,9 @@ module \cr
   wire width 4 \reg_4_w4__data_i
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 \reg_4_w4__wen
-  cell \reg_4$112 \reg_4
-    connect \rst \rst
-    connect \clk \clk
+  cell \reg_4$129 \reg_4
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
     connect \src14__ren \reg_4_src14__ren
     connect \src14__data_o \reg_4_src14__data_o
     connect \src24__ren \reg_4_src24__ren
@@ -134332,9 +150024,9 @@ module \cr
   wire width 4 \reg_5_w5__data_i
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 \reg_5_w5__wen
-  cell \reg_5$113 \reg_5
-    connect \rst \rst
-    connect \clk \clk
+  cell \reg_5$130 \reg_5
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
     connect \src15__ren \reg_5_src15__ren
     connect \src15__data_o \reg_5_src15__data_o
     connect \src25__ren \reg_5_src25__ren
@@ -134378,9 +150070,9 @@ module \cr
   wire width 4 \reg_6_w6__data_i
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 \reg_6_w6__wen
-  cell \reg_6$114 \reg_6
-    connect \rst \rst
-    connect \clk \clk
+  cell \reg_6$131 \reg_6
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
     connect \src16__ren \reg_6_src16__ren
     connect \src16__data_o \reg_6_src16__data_o
     connect \src26__ren \reg_6_src26__ren
@@ -134424,9 +150116,9 @@ module \cr
   wire width 4 \reg_7_w7__data_i
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 \reg_7_w7__wen
-  cell \reg_7$115 \reg_7
-    connect \rst \rst
-    connect \clk \clk
+  cell \reg_7$132 \reg_7
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
     connect \src17__ren \reg_7_src17__ren
     connect \src17__data_o \reg_7_src17__data_o
     connect \src27__ren \reg_7_src27__ren
@@ -134920,11 +150612,11 @@ module \cr
 end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.xer.reg_0"
-module \reg_0$116
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
+module \reg_0$133
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 input 2 \src10__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
@@ -135452,23 +151144,23 @@ module \reg_0$116
         assign \reg$next \w0__data_i
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \reg$next 2'00
     end
     sync init
       update \reg 2'00
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \reg \reg$next
   end
 end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.xer.reg_1"
-module \reg_1$117
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
+module \reg_1$134
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 input 2 \src11__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
@@ -135996,23 +151688,23 @@ module \reg_1$117
         assign \reg$next \w1__data_i
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \reg$next 2'00
     end
     sync init
       update \reg 2'00
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \reg \reg$next
   end
 end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.xer.reg_2"
-module \reg_2$118
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
+module \reg_2$135
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 input 2 \src12__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
@@ -136540,47 +152232,47 @@ module \reg_2$118
         assign \reg$next \w2__data_i
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \reg$next 2'00
     end
     sync init
       update \reg 2'00
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \reg \reg$next
   end
 end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.xer"
 module \xer
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 3 input 2 \src1__ren
+  wire width 3 input 1 \src1__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 2 output 3 \src1__data_o
+  wire width 2 output 2 \src1__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 3 input 4 \src2__ren
+  wire width 3 input 3 \src2__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 2 output 5 \src2__data_o
+  wire width 2 output 4 \src2__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 3 input 6 \src3__ren
+  wire width 3 input 5 \src3__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 2 output 7 \src3__data_o
+  wire width 2 output 6 \src3__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 3 input 8 \wen
+  wire width 3 input 7 \wen
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 2 input 9 \data_i
+  wire width 2 input 8 \data_i
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 3 input 10 \wen$1
+  wire width 3 input 9 \wen$1
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 2 input 11 \data_i$2
+  wire width 2 input 10 \data_i$2
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 3 input 12 \wen$3
+  wire width 3 input 11 \wen$3
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 2 input 13 \data_i$4
+  wire width 2 input 12 \data_i$4
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 13 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 \reg_0_src10__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
@@ -136613,9 +152305,9 @@ module \xer
   wire width 2 \reg_0_w0__data_i
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 \reg_0_w0__wen
-  cell \reg_0$116 \reg_0
-    connect \rst \rst
-    connect \clk \clk
+  cell \reg_0$133 \reg_0
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
     connect \src10__ren \reg_0_src10__ren
     connect \src10__data_o \reg_0_src10__data_o
     connect \src20__ren \reg_0_src20__ren
@@ -136665,9 +152357,9 @@ module \xer
   wire width 2 \reg_1_w1__data_i
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 \reg_1_w1__wen
-  cell \reg_1$117 \reg_1
-    connect \rst \rst
-    connect \clk \clk
+  cell \reg_1$134 \reg_1
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
     connect \src11__ren \reg_1_src11__ren
     connect \src11__data_o \reg_1_src11__data_o
     connect \src21__ren \reg_1_src21__ren
@@ -136717,9 +152409,9 @@ module \xer
   wire width 2 \reg_2_w2__data_i
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 \reg_2_w2__wen
-  cell \reg_2$118 \reg_2
-    connect \rst \rst
-    connect \clk \clk
+  cell \reg_2$135 \reg_2
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
     connect \src12__ren \reg_2_src12__ren
     connect \src12__data_o \reg_2_src12__data_o
     connect \src22__ren \reg_2_src22__ren
@@ -136957,11 +152649,11 @@ module \xer
 end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fast.reg_0"
-module \reg_0$119
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
+module \reg_0$136
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 input 2 \cia0__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
@@ -137547,23 +153239,23 @@ module \reg_0$119
         assign \reg$next \d_wr10__data_i
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
     end
     sync init
       update \reg 64'0000000000000000000000000000000000000000000000000000000000000000
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \reg \reg$next
   end
 end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fast.reg_1"
-module \reg_1$120
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
+module \reg_1$137
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 input 2 \cia1__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
@@ -138149,23 +153841,23 @@ module \reg_1$120
         assign \reg$next \d_wr11__data_i
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
     end
     sync init
       update \reg 64'0000000000000000000000000000000000000000000000000000000000000000
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \reg \reg$next
   end
 end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fast.reg_2"
-module \reg_2$121
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
+module \reg_2$138
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 input 2 \cia2__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
@@ -138751,23 +154443,23 @@ module \reg_2$121
         assign \reg$next \d_wr12__data_i
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
     end
     sync init
       update \reg 64'0000000000000000000000000000000000000000000000000000000000000000
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \reg \reg$next
   end
 end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fast.reg_3"
-module \reg_3$122
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
+module \reg_3$139
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 input 2 \cia3__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
@@ -139353,23 +155045,23 @@ module \reg_3$122
         assign \reg$next \d_wr13__data_i
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
     end
     sync init
       update \reg 64'0000000000000000000000000000000000000000000000000000000000000000
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \reg \reg$next
   end
 end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fast.reg_4"
-module \reg_4$123
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
+module \reg_4$140
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 input 2 \cia4__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
@@ -139955,23 +155647,23 @@ module \reg_4$123
         assign \reg$next \d_wr14__data_i
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
     end
     sync init
       update \reg 64'0000000000000000000000000000000000000000000000000000000000000000
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \reg \reg$next
   end
 end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fast.reg_5"
-module \reg_5$124
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
+module \reg_5$141
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 input 2 \cia5__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
@@ -140557,23 +156249,23 @@ module \reg_5$124
         assign \reg$next \d_wr15__data_i
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
     end
     sync init
       update \reg 64'0000000000000000000000000000000000000000000000000000000000000000
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \reg \reg$next
   end
 end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fast.reg_6"
-module \reg_6$125
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
+module \reg_6$142
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 input 2 \cia6__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
@@ -141159,23 +156851,23 @@ module \reg_6$125
         assign \reg$next \d_wr16__data_i
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
     end
     sync init
       update \reg 64'0000000000000000000000000000000000000000000000000000000000000000
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \reg \reg$next
   end
 end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fast.reg_7"
-module \reg_7$126
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
+module \reg_7$143
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 1 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 input 2 \cia7__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
@@ -141761,59 +157453,59 @@ module \reg_7$126
         assign \reg$next \d_wr17__data_i
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
     end
     sync init
       update \reg 64'0000000000000000000000000000000000000000000000000000000000000000
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \reg \reg$next
   end
 end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.fast"
 module \fast
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 8 input 0 \cia__ren
+  wire width 8 input 1 \cia__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 1 \cia__data_o
+  wire width 64 output 2 \cia__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 8 input 2 \msr__ren
+  wire width 8 input 3 \msr__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 3 \msr__data_o
+  wire width 64 output 4 \msr__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 8 input 4 \fast_nia_wen
+  wire width 8 input 5 \fast_nia_wen
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 8 input 5 \wen
+  wire width 8 input 6 \wen
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 6 \data_i
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 7 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 8 \clk
+  wire width 64 input 7 \data_i
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 8 input 9 \src1__ren
+  wire width 8 input 8 \src1__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 10 \src1__data_o
+  wire width 64 output 9 \src1__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 8 input 11 \src2__ren
+  wire width 8 input 10 \src2__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 12 \src2__data_o
+  wire width 64 output 11 \src2__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 8 input 13 \wen$1
+  wire width 8 input 12 \wen$1
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 14 \data_i$2
+  wire width 64 input 13 \data_i$2
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 8 input 15 \wen$3
+  wire width 8 input 14 \wen$3
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 16 \data_i$4
+  wire width 64 input 15 \data_i$4
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 17 \data_i$5
+  wire width 64 input 16 \data_i$5
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 8 input 18 \wen$6
+  wire width 8 input 17 \wen$6
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 19 \data_i$7
+  wire width 64 input 18 \data_i$7
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 19 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 1 \reg_0_cia0__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
@@ -141850,9 +157542,9 @@ module \fast
   wire width 1 \reg_0_d_wr10__wen
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_0_d_wr10__data_i
-  cell \reg_0$119 \reg_0
-    connect \rst \rst
-    connect \clk \clk
+  cell \reg_0$136 \reg_0
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
     connect \cia0__ren \reg_0_cia0__ren
     connect \cia0__data_o \reg_0_cia0__data_o
     connect \msr0__ren \reg_0_msr0__ren
@@ -141908,9 +157600,9 @@ module \fast
   wire width 1 \reg_1_d_wr11__wen
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_1_d_wr11__data_i
-  cell \reg_1$120 \reg_1
-    connect \rst \rst
-    connect \clk \clk
+  cell \reg_1$137 \reg_1
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
     connect \cia1__ren \reg_1_cia1__ren
     connect \cia1__data_o \reg_1_cia1__data_o
     connect \msr1__ren \reg_1_msr1__ren
@@ -141966,9 +157658,9 @@ module \fast
   wire width 1 \reg_2_d_wr12__wen
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_2_d_wr12__data_i
-  cell \reg_2$121 \reg_2
-    connect \rst \rst
-    connect \clk \clk
+  cell \reg_2$138 \reg_2
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
     connect \cia2__ren \reg_2_cia2__ren
     connect \cia2__data_o \reg_2_cia2__data_o
     connect \msr2__ren \reg_2_msr2__ren
@@ -142024,9 +157716,9 @@ module \fast
   wire width 1 \reg_3_d_wr13__wen
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_3_d_wr13__data_i
-  cell \reg_3$122 \reg_3
-    connect \rst \rst
-    connect \clk \clk
+  cell \reg_3$139 \reg_3
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
     connect \cia3__ren \reg_3_cia3__ren
     connect \cia3__data_o \reg_3_cia3__data_o
     connect \msr3__ren \reg_3_msr3__ren
@@ -142082,9 +157774,9 @@ module \fast
   wire width 1 \reg_4_d_wr14__wen
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_4_d_wr14__data_i
-  cell \reg_4$123 \reg_4
-    connect \rst \rst
-    connect \clk \clk
+  cell \reg_4$140 \reg_4
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
     connect \cia4__ren \reg_4_cia4__ren
     connect \cia4__data_o \reg_4_cia4__data_o
     connect \msr4__ren \reg_4_msr4__ren
@@ -142140,9 +157832,9 @@ module \fast
   wire width 1 \reg_5_d_wr15__wen
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_5_d_wr15__data_i
-  cell \reg_5$124 \reg_5
-    connect \rst \rst
-    connect \clk \clk
+  cell \reg_5$141 \reg_5
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
     connect \cia5__ren \reg_5_cia5__ren
     connect \cia5__data_o \reg_5_cia5__data_o
     connect \msr5__ren \reg_5_msr5__ren
@@ -142198,9 +157890,9 @@ module \fast
   wire width 1 \reg_6_d_wr16__wen
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_6_d_wr16__data_i
-  cell \reg_6$125 \reg_6
-    connect \rst \rst
-    connect \clk \clk
+  cell \reg_6$142 \reg_6
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
     connect \cia6__ren \reg_6_cia6__ren
     connect \cia6__data_o \reg_6_cia6__data_o
     connect \msr6__ren \reg_6_msr6__ren
@@ -142256,9 +157948,9 @@ module \fast
   wire width 1 \reg_7_d_wr17__wen
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \reg_7_d_wr17__data_i
-  cell \reg_7$126 \reg_7
-    connect \rst \rst
-    connect \clk \clk
+  cell \reg_7$143 \reg_7
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
     connect \cia7__ren \reg_7_cia7__ren
     connect \cia7__data_o \reg_7_cia7__data_o
     connect \msr7__ren \reg_7_msr7__ren
@@ -142974,18 +158666,18 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core.spr"
 module \spr
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 0 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 1 \clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 2 \src__ren
+  wire width 1 input 1 \src__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 3 \src__data_o
+  wire width 64 output 2 \src__data_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 input 4 \dest__wen
+  wire width 1 input 3 \dest__wen
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 input 5 \dest__data_i
+  wire width 64 input 4 \dest__data_i
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 5 \coresync_rst
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:199"
   wire width 1 \wr_detect
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:203"
@@ -143908,7 +159600,7 @@ module \spr
         end
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    switch \coresync_rst
       case 1'1
         assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000
         assign \reg$9$next 64'0000000000000000000000000000000000000000000000000000000000000000
@@ -144132,7 +159824,7 @@ module \spr
       update \reg$115 64'0000000000000000000000000000000000000000000000000000000000000000
       update \reg$116 64'0000000000000000000000000000000000000000000000000000000000000000
       update \reg$117 64'0000000000000000000000000000000000000000000000000000000000000000
-    sync posedge \clk
+    sync posedge \coresync_clk
       update \reg \reg$next
       update \reg$9 \reg$9$next
       update \reg$10 \reg$10$next
@@ -144253,23 +159945,23 @@ module \rdpick_INT_ra
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
   wire width 1 output 0 \en_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
-  wire width 8 input 1 \i
+  wire width 9 input 1 \i
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
-  wire width 8 output 2 \o
+  wire width 9 output 2 \o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42"
-  wire width 8 \ni
+  wire width 9 \ni
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
-  wire width 8 $1
+  wire width 9 $1
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
   cell $not $2
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 8
-    parameter \Y_WIDTH 8
+    parameter \A_WIDTH 9
+    parameter \Y_WIDTH 9
     connect \A \i
     connect \Y $1
   end
   process $group_0
-    assign \ni 8'00000000
+    assign \ni 9'000000000
     assign \ni $1
     sync init
   end
@@ -144469,24 +160161,51 @@ module \rdpick_INT_ra
     assign \t7 $27
     sync init
   end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
+  wire width 1 \t8
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  wire width 1 $31
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  wire width 1 $32
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  cell $reduce_bool $33
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 9
+    parameter \Y_WIDTH 1
+    connect \A { \i [7:0] [7] \i [7:0] [6] \i [7:0] [5] \i [7:0] [4] \i [7:0] [3] \i [7:0] [2] \i [7:0] [1] \i [7:0] [0] \ni [8] }
+    connect \Y $32
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  cell $not $34
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $32
+    connect \Y $31
+  end
   process $group_9
-    assign \o 8'00000000
-    assign \o { \t7 \t6 \t5 \t4 \t3 \t2 \t1 \t0 }
+    assign \t8 1'0
+    assign \t8 $31
+    sync init
+  end
+  process $group_10
+    assign \o 9'000000000
+    assign \o { \t8 \t7 \t6 \t5 \t4 \t3 \t2 \t1 \t0 }
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
-  wire width 1 $31
+  wire width 1 $35
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
-  cell $reduce_bool $32
+  cell $reduce_bool $36
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 8
+    parameter \A_WIDTH 9
     parameter \Y_WIDTH 1
     connect \A \o
-    connect \Y $31
+    connect \Y $35
   end
-  process $group_10
+  process $group_11
     assign \en_o 1'0
-    assign \en_o $31
+    assign \en_o $35
     sync init
   end
 end
@@ -144496,23 +160215,23 @@ module \rdpick_INT_rb
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
   wire width 1 output 0 \en_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
-  wire width 7 input 1 \i
+  wire width 8 input 1 \i
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
-  wire width 7 output 2 \o
+  wire width 8 output 2 \o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42"
-  wire width 7 \ni
+  wire width 8 \ni
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
-  wire width 7 $1
+  wire width 8 $1
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
   cell $not $2
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 7
-    parameter \Y_WIDTH 7
+    parameter \A_WIDTH 8
+    parameter \Y_WIDTH 8
     connect \A \i
     connect \Y $1
   end
   process $group_0
-    assign \ni 7'0000000
+    assign \ni 8'00000000
     assign \ni $1
     sync init
   end
@@ -144685,24 +160404,51 @@ module \rdpick_INT_rb
     assign \t6 $23
     sync init
   end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
+  wire width 1 \t7
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  wire width 1 $27
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  wire width 1 $28
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  cell $reduce_bool $29
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 8
+    parameter \Y_WIDTH 1
+    connect \A { \i [6:0] [6] \i [6:0] [5] \i [6:0] [4] \i [6:0] [3] \i [6:0] [2] \i [6:0] [1] \i [6:0] [0] \ni [7] }
+    connect \Y $28
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  cell $not $30
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $28
+    connect \Y $27
+  end
   process $group_8
-    assign \o 7'0000000
-    assign \o { \t6 \t5 \t4 \t3 \t2 \t1 \t0 }
+    assign \t7 1'0
+    assign \t7 $27
+    sync init
+  end
+  process $group_9
+    assign \o 8'00000000
+    assign \o { \t7 \t6 \t5 \t4 \t3 \t2 \t1 \t0 }
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
-  wire width 1 $27
+  wire width 1 $31
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
-  cell $reduce_bool $28
+  cell $reduce_bool $32
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 7
+    parameter \A_WIDTH 8
     parameter \Y_WIDTH 1
     connect \A \o
-    connect \Y $27
+    connect \Y $31
   end
-  process $group_9
+  process $group_10
     assign \en_o 1'0
-    assign \en_o $27
+    assign \en_o $31
     sync init
   end
 end
@@ -144793,23 +160539,23 @@ module \rdpick_XER_xer_so
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
   wire width 1 output 0 \en_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
-  wire width 3 input 1 \i
+  wire width 4 input 1 \i
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
-  wire width 3 output 2 \o
+  wire width 4 output 2 \o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42"
-  wire width 3 \ni
+  wire width 4 \ni
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
-  wire width 3 $1
+  wire width 4 $1
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
   cell $not $2
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 3
-    parameter \Y_WIDTH 3
+    parameter \A_WIDTH 4
+    parameter \Y_WIDTH 4
     connect \A \i
     connect \Y $1
   end
   process $group_0
-    assign \ni 3'000
+    assign \ni 4'0000
     assign \ni $1
     sync init
   end
@@ -144874,24 +160620,51 @@ module \rdpick_XER_xer_so
     assign \t2 $7
     sync init
   end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
+  wire width 1 \t3
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  wire width 1 $11
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  wire width 1 $12
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  cell $reduce_bool $13
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 4
+    parameter \Y_WIDTH 1
+    connect \A { \i [2:0] [2] \i [2:0] [1] \i [2:0] [0] \ni [3] }
+    connect \Y $12
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  cell $not $14
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $12
+    connect \Y $11
+  end
   process $group_4
-    assign \o 3'000
-    assign \o { \t2 \t1 \t0 }
+    assign \t3 1'0
+    assign \t3 $11
+    sync init
+  end
+  process $group_5
+    assign \o 4'0000
+    assign \o { \t3 \t2 \t1 \t0 }
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
-  wire width 1 $11
+  wire width 1 $15
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
-  cell $reduce_bool $12
+  cell $reduce_bool $16
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 3
+    parameter \A_WIDTH 4
     parameter \Y_WIDTH 1
     connect \A \o
-    connect \Y $11
+    connect \Y $15
   end
-  process $group_5
+  process $group_6
     assign \en_o 1'0
-    assign \en_o $11
+    assign \en_o $15
     sync init
   end
 end
@@ -145549,23 +161322,23 @@ module \wrpick_INT_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
   wire width 1 output 0 \en_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
-  wire width 8 input 1 \i
+  wire width 9 input 1 \i
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
-  wire width 8 output 2 \o
+  wire width 9 output 2 \o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42"
-  wire width 8 \ni
+  wire width 9 \ni
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
-  wire width 8 $1
+  wire width 9 $1
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
   cell $not $2
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 8
-    parameter \Y_WIDTH 8
+    parameter \A_WIDTH 9
+    parameter \Y_WIDTH 9
     connect \A \i
     connect \Y $1
   end
   process $group_0
-    assign \ni 8'00000000
+    assign \ni 9'000000000
     assign \ni $1
     sync init
   end
@@ -145765,24 +161538,51 @@ module \wrpick_INT_o
     assign \t7 $27
     sync init
   end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
+  wire width 1 \t8
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  wire width 1 $31
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  wire width 1 $32
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  cell $reduce_bool $33
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 9
+    parameter \Y_WIDTH 1
+    connect \A { \i [7:0] [7] \i [7:0] [6] \i [7:0] [5] \i [7:0] [4] \i [7:0] [3] \i [7:0] [2] \i [7:0] [1] \i [7:0] [0] \ni [8] }
+    connect \Y $32
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  cell $not $34
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $32
+    connect \Y $31
+  end
   process $group_9
-    assign \o 8'00000000
-    assign \o { \t7 \t6 \t5 \t4 \t3 \t2 \t1 \t0 }
+    assign \t8 1'0
+    assign \t8 $31
+    sync init
+  end
+  process $group_10
+    assign \o 9'000000000
+    assign \o { \t8 \t7 \t6 \t5 \t4 \t3 \t2 \t1 \t0 }
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
-  wire width 1 $31
+  wire width 1 $35
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
-  cell $reduce_bool $32
+  cell $reduce_bool $36
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 8
+    parameter \A_WIDTH 9
     parameter \Y_WIDTH 1
     connect \A \o
-    connect \Y $31
+    connect \Y $35
   end
-  process $group_10
+  process $group_11
     assign \en_o 1'0
-    assign \en_o $31
+    assign \en_o $35
     sync init
   end
 end
@@ -145900,23 +161700,23 @@ module \wrpick_CR_cr_a
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
   wire width 1 output 0 \en_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
-  wire width 5 input 1 \i
+  wire width 6 input 1 \i
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
-  wire width 5 output 2 \o
+  wire width 6 output 2 \o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42"
-  wire width 5 \ni
+  wire width 6 \ni
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
-  wire width 5 $1
+  wire width 6 $1
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
   cell $not $2
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 5
-    parameter \Y_WIDTH 5
+    parameter \A_WIDTH 6
+    parameter \Y_WIDTH 6
     connect \A \i
     connect \Y $1
   end
   process $group_0
-    assign \ni 5'00000
+    assign \ni 6'000000
     assign \ni $1
     sync init
   end
@@ -146035,24 +161835,51 @@ module \wrpick_CR_cr_a
     assign \t4 $15
     sync init
   end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
+  wire width 1 \t5
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  wire width 1 $19
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  wire width 1 $20
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  cell $reduce_bool $21
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 6
+    parameter \Y_WIDTH 1
+    connect \A { \i [4:0] [4] \i [4:0] [3] \i [4:0] [2] \i [4:0] [1] \i [4:0] [0] \ni [5] }
+    connect \Y $20
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  cell $not $22
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $20
+    connect \Y $19
+  end
   process $group_6
-    assign \o 5'00000
-    assign \o { \t4 \t3 \t2 \t1 \t0 }
+    assign \t5 1'0
+    assign \t5 $19
+    sync init
+  end
+  process $group_7
+    assign \o 6'000000
+    assign \o { \t5 \t4 \t3 \t2 \t1 \t0 }
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
-  wire width 1 $19
+  wire width 1 $23
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
-  cell $reduce_bool $20
+  cell $reduce_bool $24
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 5
+    parameter \A_WIDTH 6
     parameter \Y_WIDTH 1
     connect \A \o
-    connect \Y $19
+    connect \Y $23
   end
-  process $group_7
+  process $group_8
     assign \en_o 1'0
-    assign \en_o $19
+    assign \en_o $23
     sync init
   end
 end
@@ -146197,23 +162024,23 @@ module \wrpick_XER_xer_ov
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
   wire width 1 output 0 \en_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
-  wire width 3 input 1 \i
+  wire width 4 input 1 \i
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
-  wire width 3 output 2 \o
+  wire width 4 output 2 \o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42"
-  wire width 3 \ni
+  wire width 4 \ni
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
-  wire width 3 $1
+  wire width 4 $1
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
   cell $not $2
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 3
-    parameter \Y_WIDTH 3
+    parameter \A_WIDTH 4
+    parameter \Y_WIDTH 4
     connect \A \i
     connect \Y $1
   end
   process $group_0
-    assign \ni 3'000
+    assign \ni 4'0000
     assign \ni $1
     sync init
   end
@@ -146278,24 +162105,51 @@ module \wrpick_XER_xer_ov
     assign \t2 $7
     sync init
   end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
+  wire width 1 \t3
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  wire width 1 $11
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  wire width 1 $12
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  cell $reduce_bool $13
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 4
+    parameter \Y_WIDTH 1
+    connect \A { \i [2:0] [2] \i [2:0] [1] \i [2:0] [0] \ni [3] }
+    connect \Y $12
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  cell $not $14
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $12
+    connect \Y $11
+  end
   process $group_4
-    assign \o 3'000
-    assign \o { \t2 \t1 \t0 }
+    assign \t3 1'0
+    assign \t3 $11
+    sync init
+  end
+  process $group_5
+    assign \o 4'0000
+    assign \o { \t3 \t2 \t1 \t0 }
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
-  wire width 1 $11
+  wire width 1 $15
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
-  cell $reduce_bool $12
+  cell $reduce_bool $16
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 3
+    parameter \A_WIDTH 4
     parameter \Y_WIDTH 1
     connect \A \o
-    connect \Y $11
+    connect \Y $15
   end
-  process $group_5
+  process $group_6
     assign \en_o 1'0
-    assign \en_o $11
+    assign \en_o $15
     sync init
   end
 end
@@ -146305,23 +162159,23 @@ module \wrpick_XER_xer_so
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
   wire width 1 output 0 \en_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
-  wire width 3 input 1 \i
+  wire width 4 input 1 \i
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
-  wire width 3 output 2 \o
+  wire width 4 output 2 \o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42"
-  wire width 3 \ni
+  wire width 4 \ni
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
-  wire width 3 $1
+  wire width 4 $1
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:43"
   cell $not $2
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 3
-    parameter \Y_WIDTH 3
+    parameter \A_WIDTH 4
+    parameter \Y_WIDTH 4
     connect \A \i
     connect \Y $1
   end
   process $group_0
-    assign \ni 3'000
+    assign \ni 4'0000
     assign \ni $1
     sync init
   end
@@ -146386,24 +162240,51 @@ module \wrpick_XER_xer_so
     assign \t2 $7
     sync init
   end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:45"
+  wire width 1 \t3
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  wire width 1 $11
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  wire width 1 $12
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  cell $reduce_bool $13
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 4
+    parameter \Y_WIDTH 1
+    connect \A { \i [2:0] [2] \i [2:0] [1] \i [2:0] [0] \ni [3] }
+    connect \Y $12
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:50"
+  cell $not $14
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $12
+    connect \Y $11
+  end
   process $group_4
-    assign \o 3'000
-    assign \o { \t2 \t1 \t0 }
+    assign \t3 1'0
+    assign \t3 $11
+    sync init
+  end
+  process $group_5
+    assign \o 4'0000
+    assign \o { \t3 \t2 \t1 \t0 }
     sync init
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
-  wire width 1 $11
+  wire width 1 $15
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:55"
-  cell $reduce_bool $12
+  cell $reduce_bool $16
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 3
+    parameter \A_WIDTH 4
     parameter \Y_WIDTH 1
     connect \A \o
-    connect \Y $11
+    connect \Y $15
   end
-  process $group_5
+  process $group_6
     assign \en_o 1'0
-    assign \en_o $11
+    assign \en_o $15
     sync init
   end
 end
@@ -146788,29 +162669,31 @@ end
 attribute \generator "nMigen"
 attribute \nmigen.hierarchy "test_issuer.core"
 module \core
+  attribute \src "simple/issuer.py:87"
+  wire width 1 input 0 \coresync_clk
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:80"
-  wire width 1 output 0 \corebusy_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:89"
-  wire width 1 output 1 \core_terminated_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:87"
-  wire width 1 input 2 \core_start_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:88"
-  wire width 1 input 3 \core_stop_i
+  wire width 1 output 1 \corebusy_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
-  wire width 1 input 4 \bigendian
+  wire width 1 input 2 \bigendian
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 1 input 5 \cu_ad__go_i
+  wire width 1 input 3 \cu_ad__go_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 1 output 6 \cu_ad__rel_o
+  wire width 1 output 4 \cu_ad__rel_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 1 input 7 \cu_st__go_i
+  wire width 1 input 5 \cu_st__go_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 1 output 8 \cu_st__rel_o
+  wire width 1 output 6 \cu_st__rel_o
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 8 input 9 \cia__ren
+  wire width 8 input 7 \cia__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 output 10 \cia__data_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:571"
+  wire width 64 output 8 \cia__data_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:88"
+  wire width 1 input 9 \core_reset_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:89"
+  wire width 1 output 10 \core_terminate_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:89"
+  wire width 1 \core_terminate_o$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:581"
   wire width 1 input 11 \valid
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:79"
   wire width 1 input 12 \issue_i
@@ -146820,10 +162703,10 @@ module \core
   wire width 8 input 14 \msr__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 output 15 \msr__data_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:574"
-  wire width 64 input 16 \msr
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575"
-  wire width 64 input 17 \cia
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:9"
+  wire width 64 input 16 \dec2_msr
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:8"
+  wire width 64 input 17 \dec2_pc
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
   attribute \enum_value_0000001 "OP_NOP"
@@ -146905,10 +162788,10 @@ module \core
   wire width 8 input 20 \wen
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 input 21 \data_i
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 22 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 23 \clk
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 32 input 22 \dmi__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 output 23 \dmi__data_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
   wire width 1 output 24 \dbus__cyc
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
@@ -146927,6 +162810,8 @@ module \core
   wire width 1 output 31 \dbus__we
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
   wire width 64 output 32 \dbus__dat_w
+  attribute \src "simple/issuer.py:87"
+  wire width 1 \coresync_rst
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -147281,8 +163166,8 @@ module \core
   cell \pdecode2 \pdecode2
     connect \bigendian \bigendian
     connect \raw_opcode_in \raw_opcode_in
-    connect \msr \msr
-    connect \cia \cia
+    connect \dec2_msr \dec2_msr
+    connect \dec2_pc \dec2_pc
     connect \insn_type \insn_type
     connect \fn_unit \pdecode2_fn_unit
     connect \imm \pdecode2_imm
@@ -147309,11 +163194,11 @@ module \core
     connect \cr_in1_ok \pdecode2_cr_in1_ok
     connect \cr_in2_ok \pdecode2_cr_in2_ok
     connect \cr_in2_ok$1 \pdecode2_cr_in2_ok$1
-    connect \cia$2 \pdecode2_cia
+    connect \cia \pdecode2_cia
     connect \lk \pdecode2_lk
     connect \fast1_ok \pdecode2_fast1_ok
     connect \fast2_ok \pdecode2_fast2_ok
-    connect \msr$3 \pdecode2_msr
+    connect \msr \pdecode2_msr
     connect \traptype \pdecode2_traptype
     connect \trapaddr \pdecode2_trapaddr
     connect \spr1_ok \pdecode2_spr1_ok
@@ -147328,7 +163213,7 @@ module \core
     connect \reg3 \pdecode2_reg3
     connect \cr_in1 \pdecode2_cr_in1
     connect \cr_in2 \pdecode2_cr_in2
-    connect \cr_in2$4 \pdecode2_cr_in2$2
+    connect \cr_in2$2 \pdecode2_cr_in2$2
     connect \fast1 \pdecode2_fast1
     connect \fast2 \pdecode2_fast2
     connect \spr1 \pdecode2_spr1
@@ -147990,7 +163875,106 @@ module \core
   attribute \enum_value_1001001 "OP_SC"
   attribute \enum_value_1001010 "OP_MTMSR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 7 \fus_oper_i_alu_spr0__insn_type
+  wire width 7 \fus_oper_i_alu_spr0__insn_type
+  attribute \enum_base_type "Function"
+  attribute \enum_value_00000000000 "NONE"
+  attribute \enum_value_00000000010 "ALU"
+  attribute \enum_value_00000000100 "LDST"
+  attribute \enum_value_00000001000 "SHIFT_ROT"
+  attribute \enum_value_00000010000 "LOGICAL"
+  attribute \enum_value_00000100000 "BRANCH"
+  attribute \enum_value_00001000000 "CR"
+  attribute \enum_value_00010000000 "TRAP"
+  attribute \enum_value_00100000000 "MUL"
+  attribute \enum_value_01000000000 "DIV"
+  attribute \enum_value_10000000000 "SPR"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 11 \fus_oper_i_alu_spr0__fn_unit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \fus_oper_i_alu_spr0__insn
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \fus_oper_i_alu_spr0__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
+  wire width 1 \fus_cu_issue_i$15
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:106"
+  wire width 1 \fus_cu_busy_o$16
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
+  wire width 6 \fus_cu_rdmaskn_i$17
+  attribute \enum_base_type "MicrOp"
+  attribute \enum_value_0000000 "OP_ILLEGAL"
+  attribute \enum_value_0000001 "OP_NOP"
+  attribute \enum_value_0000010 "OP_ADD"
+  attribute \enum_value_0000011 "OP_ADDPCIS"
+  attribute \enum_value_0000100 "OP_AND"
+  attribute \enum_value_0000101 "OP_ATTN"
+  attribute \enum_value_0000110 "OP_B"
+  attribute \enum_value_0000111 "OP_BC"
+  attribute \enum_value_0001000 "OP_BCREG"
+  attribute \enum_value_0001001 "OP_BPERM"
+  attribute \enum_value_0001010 "OP_CMP"
+  attribute \enum_value_0001011 "OP_CMPB"
+  attribute \enum_value_0001100 "OP_CMPEQB"
+  attribute \enum_value_0001101 "OP_CMPRB"
+  attribute \enum_value_0001110 "OP_CNTZ"
+  attribute \enum_value_0001111 "OP_CRAND"
+  attribute \enum_value_0010000 "OP_CRANDC"
+  attribute \enum_value_0010001 "OP_CREQV"
+  attribute \enum_value_0010010 "OP_CRNAND"
+  attribute \enum_value_0010011 "OP_CRNOR"
+  attribute \enum_value_0010100 "OP_CROR"
+  attribute \enum_value_0010101 "OP_CRORC"
+  attribute \enum_value_0010110 "OP_CRXOR"
+  attribute \enum_value_0010111 "OP_DARN"
+  attribute \enum_value_0011000 "OP_DCBF"
+  attribute \enum_value_0011001 "OP_DCBST"
+  attribute \enum_value_0011010 "OP_DCBT"
+  attribute \enum_value_0011011 "OP_DCBTST"
+  attribute \enum_value_0011100 "OP_DCBZ"
+  attribute \enum_value_0011101 "OP_DIV"
+  attribute \enum_value_0011110 "OP_DIVE"
+  attribute \enum_value_0011111 "OP_EXTS"
+  attribute \enum_value_0100000 "OP_EXTSWSLI"
+  attribute \enum_value_0100001 "OP_ICBI"
+  attribute \enum_value_0100010 "OP_ICBT"
+  attribute \enum_value_0100011 "OP_ISEL"
+  attribute \enum_value_0100100 "OP_ISYNC"
+  attribute \enum_value_0100101 "OP_LOAD"
+  attribute \enum_value_0100110 "OP_STORE"
+  attribute \enum_value_0100111 "OP_MADDHD"
+  attribute \enum_value_0101000 "OP_MADDHDU"
+  attribute \enum_value_0101001 "OP_MADDLD"
+  attribute \enum_value_0101010 "OP_MCRF"
+  attribute \enum_value_0101011 "OP_MCRXR"
+  attribute \enum_value_0101100 "OP_MCRXRX"
+  attribute \enum_value_0101101 "OP_MFCR"
+  attribute \enum_value_0101110 "OP_MFSPR"
+  attribute \enum_value_0101111 "OP_MOD"
+  attribute \enum_value_0110000 "OP_MTCRF"
+  attribute \enum_value_0110001 "OP_MTSPR"
+  attribute \enum_value_0110010 "OP_MUL_L64"
+  attribute \enum_value_0110011 "OP_MUL_H64"
+  attribute \enum_value_0110100 "OP_MUL_H32"
+  attribute \enum_value_0110101 "OP_OR"
+  attribute \enum_value_0110110 "OP_POPCNT"
+  attribute \enum_value_0110111 "OP_PRTY"
+  attribute \enum_value_0111000 "OP_RLC"
+  attribute \enum_value_0111001 "OP_RLCL"
+  attribute \enum_value_0111010 "OP_RLCR"
+  attribute \enum_value_0111011 "OP_SETB"
+  attribute \enum_value_0111100 "OP_SHL"
+  attribute \enum_value_0111101 "OP_SHR"
+  attribute \enum_value_0111110 "OP_SYNC"
+  attribute \enum_value_0111111 "OP_TRAP"
+  attribute \enum_value_1000011 "OP_XOR"
+  attribute \enum_value_1000100 "OP_SIM_CONFIG"
+  attribute \enum_value_1000101 "OP_CROP"
+  attribute \enum_value_1000110 "OP_RFID"
+  attribute \enum_value_1000111 "OP_MFMSR"
+  attribute \enum_value_1001000 "OP_MTMSRD"
+  attribute \enum_value_1001001 "OP_SC"
+  attribute \enum_value_1001010 "OP_MTMSR"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 7 \fus_oper_i_alu_div0__insn_type
   attribute \enum_base_type "Function"
   attribute \enum_value_00000000000 "NONE"
   attribute \enum_value_00000000010 "ALU"
@@ -148004,17 +163988,49 @@ module \core
   attribute \enum_value_01000000000 "DIV"
   attribute \enum_value_10000000000 "SPR"
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 11 \fus_oper_i_alu_spr0__fn_unit
+  wire width 11 \fus_oper_i_alu_div0__fn_unit
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 32 \fus_oper_i_alu_spr0__insn
+  wire width 64 \fus_oper_i_alu_div0__imm_data__imm
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
-  wire width 1 \fus_oper_i_alu_spr0__is_32bit
+  wire width 1 \fus_oper_i_alu_div0__imm_data__imm_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \fus_oper_i_alu_div0__rc__rc
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \fus_oper_i_alu_div0__rc__rc_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \fus_oper_i_alu_div0__oe__oe
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \fus_oper_i_alu_div0__oe__oe_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \fus_oper_i_alu_div0__invert_a
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \fus_oper_i_alu_div0__zero_a
+  attribute \enum_base_type "CryIn"
+  attribute \enum_value_00 "ZERO"
+  attribute \enum_value_01 "ONE"
+  attribute \enum_value_10 "CA"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 2 \fus_oper_i_alu_div0__input_carry
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \fus_oper_i_alu_div0__invert_out
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \fus_oper_i_alu_div0__write_cr0
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \fus_oper_i_alu_div0__output_carry
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \fus_oper_i_alu_div0__is_32bit
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 1 \fus_oper_i_alu_div0__is_signed
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 4 \fus_oper_i_alu_div0__data_len
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
+  wire width 32 \fus_oper_i_alu_div0__insn
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
-  wire width 1 \fus_cu_issue_i$15
+  wire width 1 \fus_cu_issue_i$18
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:106"
-  wire width 1 \fus_cu_busy_o$16
+  wire width 1 \fus_cu_busy_o$19
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
-  wire width 6 \fus_cu_rdmaskn_i$17
+  wire width 3 \fus_cu_rdmaskn_i$20
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
   attribute \enum_value_0000001 "OP_NOP"
@@ -148131,11 +164147,11 @@ module \core
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
   wire width 32 \fus_oper_i_alu_mul0__insn
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
-  wire width 1 \fus_cu_issue_i$18
+  wire width 1 \fus_cu_issue_i$21
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:106"
-  wire width 1 \fus_cu_busy_o$19
+  wire width 1 \fus_cu_busy_o$22
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
-  wire width 3 \fus_cu_rdmaskn_i$20
+  wire width 3 \fus_cu_rdmaskn_i$23
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
   attribute \enum_value_0000001 "OP_NOP"
@@ -148256,11 +164272,11 @@ module \core
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
   wire width 32 \fus_oper_i_alu_shift_rot0__insn
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
-  wire width 1 \fus_cu_issue_i$21
+  wire width 1 \fus_cu_issue_i$24
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:106"
-  wire width 1 \fus_cu_busy_o$22
+  wire width 1 \fus_cu_busy_o$25
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
-  wire width 4 \fus_cu_rdmaskn_i$23
+  wire width 4 \fus_cu_rdmaskn_i$26
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
   attribute \enum_value_0000001 "OP_NOP"
@@ -148368,11 +164384,11 @@ module \core
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18"
   wire width 2 \fus_oper_i_ldst_ldst0__ldst_mode
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:99"
-  wire width 1 \fus_cu_issue_i$24
+  wire width 1 \fus_cu_issue_i$27
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:106"
-  wire width 1 \fus_cu_busy_o$25
+  wire width 1 \fus_cu_busy_o$28
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:95"
-  wire width 3 \fus_cu_rdmaskn_i$26
+  wire width 3 \fus_cu_rdmaskn_i$29
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
   wire width 4 \fus_cu_rd__rel_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
@@ -148380,39 +164396,33 @@ module \core
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
   wire width 64 \fus_src1_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 6 \fus_cu_rd__rel_o$27
+  wire width 6 \fus_cu_rd__rel_o$30
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 6 \fus_cu_rd__go_i$28
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
-  wire width 64 \fus_src1_i$29
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 4 \fus_cu_rd__rel_o$30
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 4 \fus_cu_rd__go_i$31
+  wire width 6 \fus_cu_rd__go_i$31
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
   wire width 64 \fus_src1_i$32
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 2 \fus_cu_rd__rel_o$33
+  wire width 4 \fus_cu_rd__rel_o$33
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 2 \fus_cu_rd__go_i$34
+  wire width 4 \fus_cu_rd__go_i$34
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
   wire width 64 \fus_src1_i$35
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 6 \fus_cu_rd__rel_o$36
+  wire width 2 \fus_cu_rd__rel_o$36
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 6 \fus_cu_rd__go_i$37
+  wire width 2 \fus_cu_rd__go_i$37
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
   wire width 64 \fus_src1_i$38
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 3 \fus_cu_rd__rel_o$39
+  wire width 6 \fus_cu_rd__rel_o$39
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 3 \fus_cu_rd__go_i$40
+  wire width 6 \fus_cu_rd__go_i$40
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
   wire width 64 \fus_src1_i$41
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 4 \fus_cu_rd__rel_o$42
+  wire width 3 \fus_cu_rd__rel_o$42
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 4 \fus_cu_rd__go_i$43
+  wire width 3 \fus_cu_rd__go_i$43
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
   wire width 64 \fus_src1_i$44
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
@@ -148421,64 +164431,80 @@ module \core
   wire width 3 \fus_cu_rd__go_i$46
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
   wire width 64 \fus_src1_i$47
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+  wire width 4 \fus_cu_rd__rel_o$48
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+  wire width 4 \fus_cu_rd__go_i$49
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
+  wire width 64 \fus_src1_i$50
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+  wire width 3 \fus_cu_rd__rel_o$51
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+  wire width 3 \fus_cu_rd__go_i$52
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
+  wire width 64 \fus_src1_i$53
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
   wire width 64 \fus_src2_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
-  wire width 64 \fus_src2_i$48
+  wire width 64 \fus_src2_i$54
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
+  wire width 64 \fus_src2_i$55
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
-  wire width 64 \fus_src2_i$49
+  wire width 64 \fus_src2_i$56
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
-  wire width 64 \fus_src2_i$50
+  wire width 64 \fus_src2_i$57
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
-  wire width 64 \fus_src2_i$51
+  wire width 64 \fus_src2_i$58
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
-  wire width 64 \fus_src2_i$52
+  wire width 64 \fus_src2_i$59
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
-  wire width 64 \fus_src2_i$53
+  wire width 64 \fus_src2_i$60
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
   wire width 64 \fus_src3_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
-  wire width 64 \fus_src3_i$54
+  wire width 64 \fus_src3_i$61
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
-  wire width 1 \fus_src3_i$55
+  wire width 1 \fus_src3_i$62
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
   wire width 1 \fus_src4_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
-  wire width 1 \fus_src3_i$56
+  wire width 1 \fus_src3_i$63
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
-  wire width 2 \fus_src4_i$57
+  wire width 1 \fus_src3_i$64
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
+  wire width 2 \fus_src4_i$65
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
   wire width 2 \fus_src6_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
-  wire width 2 \fus_src4_i$58
+  wire width 2 \fus_src4_i$66
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
   wire width 2 \fus_src5_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
-  wire width 32 \fus_src3_i$59
+  wire width 32 \fus_src3_i$67
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
-  wire width 4 \fus_src4_i$60
+  wire width 4 \fus_src4_i$68
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 3 \fus_cu_rd__rel_o$61
+  wire width 3 \fus_cu_rd__rel_o$69
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 3 \fus_cu_rd__go_i$62
+  wire width 3 \fus_cu_rd__go_i$70
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
-  wire width 4 \fus_src3_i$63
+  wire width 4 \fus_src3_i$71
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
-  wire width 4 \fus_src5_i$64
+  wire width 4 \fus_src5_i$72
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
-  wire width 4 \fus_src6_i$65
+  wire width 4 \fus_src6_i$73
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
-  wire width 64 \fus_src1_i$66
+  wire width 64 \fus_src1_i$74
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
-  wire width 64 \fus_src3_i$67
+  wire width 64 \fus_src3_i$75
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
-  wire width 64 \fus_src3_i$68
+  wire width 64 \fus_src3_i$76
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
-  wire width 64 \fus_src2_i$69
+  wire width 64 \fus_src2_i$77
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
-  wire width 64 \fus_src4_i$70
+  wire width 64 \fus_src4_i$78
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:71"
-  wire width 64 \fus_src2_i$71
+  wire width 64 \fus_src2_i$79
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \fus_o_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
@@ -148486,59 +164512,67 @@ module \core
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
   wire width 5 \fus_cu_wr__go_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 \fus_o_ok$72
+  wire width 1 \fus_o_ok$80
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+  wire width 3 \fus_cu_wr__rel_o$81
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
+  wire width 3 \fus_cu_wr__go_i$82
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 \fus_o_ok$83
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 3 \fus_cu_wr__rel_o$73
+  wire width 5 \fus_cu_wr__rel_o$84
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 3 \fus_cu_wr__go_i$74
+  wire width 5 \fus_cu_wr__go_i$85
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 \fus_o_ok$75
+  wire width 1 \fus_o_ok$86
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 5 \fus_cu_wr__rel_o$76
+  wire width 3 \fus_cu_wr__rel_o$87
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 5 \fus_cu_wr__go_i$77
+  wire width 3 \fus_cu_wr__go_i$88
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 \fus_o_ok$78
+  wire width 1 \fus_o_ok$89
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 3 \fus_cu_wr__rel_o$79
+  wire width 6 \fus_cu_wr__rel_o$90
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 3 \fus_cu_wr__go_i$80
+  wire width 6 \fus_cu_wr__go_i$91
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 \fus_o_ok$81
+  wire width 1 \fus_o_ok$92
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 6 \fus_cu_wr__rel_o$82
+  wire width 4 \fus_cu_wr__rel_o$93
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 6 \fus_cu_wr__go_i$83
+  wire width 4 \fus_cu_wr__go_i$94
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 \fus_o_ok$84
+  wire width 1 \fus_o_ok$95
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 4 \fus_cu_wr__rel_o$85
+  wire width 4 \fus_cu_wr__rel_o$96
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 4 \fus_cu_wr__go_i$86
+  wire width 4 \fus_cu_wr__go_i$97
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 \fus_o_ok$87
+  wire width 1 \fus_o_ok$98
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 3 \fus_cu_wr__rel_o$88
+  wire width 3 \fus_cu_wr__rel_o$99
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 3 \fus_cu_wr__go_i$89
+  wire width 3 \fus_cu_wr__go_i$100
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 2 \fus_cu_wr__rel_o$90
+  wire width 2 \fus_cu_wr__rel_o$101
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 2 \fus_cu_wr__go_i$91
+  wire width 2 \fus_cu_wr__go_i$102
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
   wire width 64 \fus_dest1_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
-  wire width 64 \fus_dest1_o$92
+  wire width 64 \fus_dest1_o$103
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
-  wire width 64 \fus_dest1_o$93
+  wire width 64 \fus_dest1_o$104
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
-  wire width 64 \fus_dest1_o$94
+  wire width 64 \fus_dest1_o$105
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
-  wire width 64 \fus_dest1_o$95
+  wire width 64 \fus_dest1_o$106
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
-  wire width 64 \fus_dest1_o$96
+  wire width 64 \fus_dest1_o$107
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
-  wire width 64 \fus_dest1_o$97
+  wire width 64 \fus_dest1_o$108
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
+  wire width 64 \fus_dest1_o$109
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 64 \fus_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
@@ -148550,103 +164584,115 @@ module \core
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \fus_cr_a_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 \fus_cr_a_ok$98
+  wire width 1 \fus_cr_a_ok$110
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 \fus_cr_a_ok$111
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 \fus_cr_a_ok$99
+  wire width 1 \fus_cr_a_ok$112
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 \fus_cr_a_ok$100
+  wire width 1 \fus_cr_a_ok$113
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 \fus_cr_a_ok$101
+  wire width 1 \fus_cr_a_ok$114
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
-  wire width 4 \fus_dest2_o$102
+  wire width 4 \fus_dest2_o$115
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
   wire width 4 \fus_dest3_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
-  wire width 4 \fus_dest2_o$103
+  wire width 4 \fus_dest2_o$116
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
+  wire width 4 \fus_dest2_o$117
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
-  wire width 4 \fus_dest2_o$104
+  wire width 4 \fus_dest2_o$118
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
-  wire width 4 \fus_dest2_o$105
+  wire width 4 \fus_dest2_o$119
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \fus_xer_ca_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 \fus_xer_ca_ok$106
+  wire width 1 \fus_xer_ca_ok$120
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 \fus_xer_ca_ok$107
+  wire width 1 \fus_xer_ca_ok$121
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 \fus_xer_ca_ok$108
+  wire width 1 \fus_xer_ca_ok$122
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
-  wire width 2 \fus_dest3_o$109
+  wire width 2 \fus_dest3_o$123
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
-  wire width 2 \fus_dest3_o$110
+  wire width 2 \fus_dest3_o$124
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
   wire width 2 \fus_dest6_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
-  wire width 2 \fus_dest3_o$111
+  wire width 2 \fus_dest3_o$125
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \fus_xer_ov_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 \fus_xer_ov_ok$112
+  wire width 1 \fus_xer_ov_ok$126
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 \fus_xer_ov_ok$113
+  wire width 1 \fus_xer_ov_ok$127
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 \fus_xer_ov_ok$128
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
   wire width 2 \fus_dest4_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
   wire width 2 \fus_dest5_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
-  wire width 2 \fus_dest3_o$114
+  wire width 2 \fus_dest3_o$129
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
+  wire width 2 \fus_dest3_o$130
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \fus_xer_so_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 \fus_xer_so_ok$115
+  wire width 1 \fus_xer_so_ok$131
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 \fus_xer_so_ok$116
+  wire width 1 \fus_xer_so_ok$132
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 \fus_xer_so_ok$133
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
+  wire width 1 \fus_dest5_o$134
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
-  wire width 1 \fus_dest5_o$117
+  wire width 1 \fus_dest4_o$135
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
-  wire width 1 \fus_dest4_o$118
+  wire width 1 \fus_dest4_o$136
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
-  wire width 1 \fus_dest4_o$119
+  wire width 1 \fus_dest4_o$137
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \fus_fast1_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 3 \fus_cu_wr__rel_o$120
+  wire width 3 \fus_cu_wr__rel_o$138
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
-  wire width 3 \fus_cu_wr__go_i$121
+  wire width 3 \fus_cu_wr__go_i$139
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 \fus_fast1_ok$122
+  wire width 1 \fus_fast1_ok$140
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 \fus_fast1_ok$123
+  wire width 1 \fus_fast1_ok$141
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
-  wire width 64 \fus_dest1_o$124
+  wire width 64 \fus_dest1_o$142
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
-  wire width 64 \fus_dest2_o$125
+  wire width 64 \fus_dest2_o$143
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
-  wire width 64 \fus_dest3_o$126
+  wire width 64 \fus_dest3_o$144
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \fus_fast2_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 \fus_fast2_ok$127
+  wire width 1 \fus_fast2_ok$145
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
-  wire width 64 \fus_dest2_o$128
+  wire width 64 \fus_dest2_o$146
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
-  wire width 64 \fus_dest3_o$129
+  wire width 64 \fus_dest3_o$147
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \fus_nia_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 \fus_nia_ok$130
+  wire width 1 \fus_nia_ok$148
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
-  wire width 64 \fus_dest3_o$131
+  wire width 64 \fus_dest3_o$149
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
-  wire width 64 \fus_dest4_o$132
+  wire width 64 \fus_dest4_o$150
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \fus_msr_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
-  wire width 64 \fus_dest5_o$133
+  wire width 64 \fus_dest5_o$151
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \fus_spr1_ok
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:83"
-  wire width 64 \fus_dest2_o$134
+  wire width 64 \fus_dest2_o$152
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:95"
   wire width 1 \fus_ldst_port0_is_ld_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:96"
@@ -148670,12 +164716,11 @@ module \core
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 \fus_ldst_port0_st_data_i_ok
   cell \fus \fus
+    connect \coresync_clk \coresync_clk
     connect \cu_ad__go_i \cu_ad__go_i
     connect \cu_ad__rel_o \cu_ad__rel_o
     connect \cu_st__go_i \cu_st__go_i
     connect \cu_st__rel_o \cu_st__rel_o
-    connect \rst \rst
-    connect \clk \clk
     connect \oper_i_alu_alu0__insn_type \fus_oper_i_alu_alu0__insn_type
     connect \oper_i_alu_alu0__fn_unit \fus_oper_i_alu_alu0__fn_unit
     connect \oper_i_alu_alu0__imm_data__imm \fus_oper_i_alu_alu0__imm_data__imm
@@ -148755,6 +164800,27 @@ module \core
     connect \cu_issue_i$13 \fus_cu_issue_i$15
     connect \cu_busy_o$14 \fus_cu_busy_o$16
     connect \cu_rdmaskn_i$15 \fus_cu_rdmaskn_i$17
+    connect \oper_i_alu_div0__insn_type \fus_oper_i_alu_div0__insn_type
+    connect \oper_i_alu_div0__fn_unit \fus_oper_i_alu_div0__fn_unit
+    connect \oper_i_alu_div0__imm_data__imm \fus_oper_i_alu_div0__imm_data__imm
+    connect \oper_i_alu_div0__imm_data__imm_ok \fus_oper_i_alu_div0__imm_data__imm_ok
+    connect \oper_i_alu_div0__rc__rc \fus_oper_i_alu_div0__rc__rc
+    connect \oper_i_alu_div0__rc__rc_ok \fus_oper_i_alu_div0__rc__rc_ok
+    connect \oper_i_alu_div0__oe__oe \fus_oper_i_alu_div0__oe__oe
+    connect \oper_i_alu_div0__oe__oe_ok \fus_oper_i_alu_div0__oe__oe_ok
+    connect \oper_i_alu_div0__invert_a \fus_oper_i_alu_div0__invert_a
+    connect \oper_i_alu_div0__zero_a \fus_oper_i_alu_div0__zero_a
+    connect \oper_i_alu_div0__input_carry \fus_oper_i_alu_div0__input_carry
+    connect \oper_i_alu_div0__invert_out \fus_oper_i_alu_div0__invert_out
+    connect \oper_i_alu_div0__write_cr0 \fus_oper_i_alu_div0__write_cr0
+    connect \oper_i_alu_div0__output_carry \fus_oper_i_alu_div0__output_carry
+    connect \oper_i_alu_div0__is_32bit \fus_oper_i_alu_div0__is_32bit
+    connect \oper_i_alu_div0__is_signed \fus_oper_i_alu_div0__is_signed
+    connect \oper_i_alu_div0__data_len \fus_oper_i_alu_div0__data_len
+    connect \oper_i_alu_div0__insn \fus_oper_i_alu_div0__insn
+    connect \cu_issue_i$16 \fus_cu_issue_i$18
+    connect \cu_busy_o$17 \fus_cu_busy_o$19
+    connect \cu_rdmaskn_i$18 \fus_cu_rdmaskn_i$20
     connect \oper_i_alu_mul0__insn_type \fus_oper_i_alu_mul0__insn_type
     connect \oper_i_alu_mul0__fn_unit \fus_oper_i_alu_mul0__fn_unit
     connect \oper_i_alu_mul0__imm_data__imm \fus_oper_i_alu_mul0__imm_data__imm
@@ -148770,9 +164836,9 @@ module \core
     connect \oper_i_alu_mul0__is_32bit \fus_oper_i_alu_mul0__is_32bit
     connect \oper_i_alu_mul0__is_signed \fus_oper_i_alu_mul0__is_signed
     connect \oper_i_alu_mul0__insn \fus_oper_i_alu_mul0__insn
-    connect \cu_issue_i$16 \fus_cu_issue_i$18
-    connect \cu_busy_o$17 \fus_cu_busy_o$19
-    connect \cu_rdmaskn_i$18 \fus_cu_rdmaskn_i$20
+    connect \cu_issue_i$19 \fus_cu_issue_i$21
+    connect \cu_busy_o$20 \fus_cu_busy_o$22
+    connect \cu_rdmaskn_i$21 \fus_cu_rdmaskn_i$23
     connect \oper_i_alu_shift_rot0__insn_type \fus_oper_i_alu_shift_rot0__insn_type
     connect \oper_i_alu_shift_rot0__fn_unit \fus_oper_i_alu_shift_rot0__fn_unit
     connect \oper_i_alu_shift_rot0__imm_data__imm \fus_oper_i_alu_shift_rot0__imm_data__imm
@@ -148788,9 +164854,9 @@ module \core
     connect \oper_i_alu_shift_rot0__is_32bit \fus_oper_i_alu_shift_rot0__is_32bit
     connect \oper_i_alu_shift_rot0__is_signed \fus_oper_i_alu_shift_rot0__is_signed
     connect \oper_i_alu_shift_rot0__insn \fus_oper_i_alu_shift_rot0__insn
-    connect \cu_issue_i$19 \fus_cu_issue_i$21
-    connect \cu_busy_o$20 \fus_cu_busy_o$22
-    connect \cu_rdmaskn_i$21 \fus_cu_rdmaskn_i$23
+    connect \cu_issue_i$22 \fus_cu_issue_i$24
+    connect \cu_busy_o$23 \fus_cu_busy_o$25
+    connect \cu_rdmaskn_i$24 \fus_cu_rdmaskn_i$26
     connect \oper_i_ldst_ldst0__insn_type \fus_oper_i_ldst_ldst0__insn_type
     connect \oper_i_ldst_ldst0__imm_data__imm \fus_oper_i_ldst_ldst0__imm_data__imm
     connect \oper_i_ldst_ldst0__imm_data__imm_ok \fus_oper_i_ldst_ldst0__imm_data__imm_ok
@@ -148805,15 +164871,12 @@ module \core
     connect \oper_i_ldst_ldst0__byte_reverse \fus_oper_i_ldst_ldst0__byte_reverse
     connect \oper_i_ldst_ldst0__sign_extend \fus_oper_i_ldst_ldst0__sign_extend
     connect \oper_i_ldst_ldst0__ldst_mode \fus_oper_i_ldst_ldst0__ldst_mode
-    connect \cu_issue_i$22 \fus_cu_issue_i$24
-    connect \cu_busy_o$23 \fus_cu_busy_o$25
-    connect \cu_rdmaskn_i$24 \fus_cu_rdmaskn_i$26
+    connect \cu_issue_i$25 \fus_cu_issue_i$27
+    connect \cu_busy_o$26 \fus_cu_busy_o$28
+    connect \cu_rdmaskn_i$27 \fus_cu_rdmaskn_i$29
     connect \cu_rd__rel_o \fus_cu_rd__rel_o
     connect \cu_rd__go_i \fus_cu_rd__go_i
     connect \src1_i \fus_src1_i
-    connect \cu_rd__rel_o$25 \fus_cu_rd__rel_o$27
-    connect \cu_rd__go_i$26 \fus_cu_rd__go_i$28
-    connect \src1_i$27 \fus_src1_i$29
     connect \cu_rd__rel_o$28 \fus_cu_rd__rel_o$30
     connect \cu_rd__go_i$29 \fus_cu_rd__go_i$31
     connect \src1_i$30 \fus_src1_i$32
@@ -148832,119 +164895,138 @@ module \core
     connect \cu_rd__rel_o$43 \fus_cu_rd__rel_o$45
     connect \cu_rd__go_i$44 \fus_cu_rd__go_i$46
     connect \src1_i$45 \fus_src1_i$47
+    connect \cu_rd__rel_o$46 \fus_cu_rd__rel_o$48
+    connect \cu_rd__go_i$47 \fus_cu_rd__go_i$49
+    connect \src1_i$48 \fus_src1_i$50
+    connect \cu_rd__rel_o$49 \fus_cu_rd__rel_o$51
+    connect \cu_rd__go_i$50 \fus_cu_rd__go_i$52
+    connect \src1_i$51 \fus_src1_i$53
     connect \src2_i \fus_src2_i
-    connect \src2_i$46 \fus_src2_i$48
-    connect \src2_i$47 \fus_src2_i$49
-    connect \src2_i$48 \fus_src2_i$50
-    connect \src2_i$49 \fus_src2_i$51
-    connect \src2_i$50 \fus_src2_i$52
-    connect \src2_i$51 \fus_src2_i$53
+    connect \src2_i$52 \fus_src2_i$54
+    connect \src2_i$53 \fus_src2_i$55
+    connect \src2_i$54 \fus_src2_i$56
+    connect \src2_i$55 \fus_src2_i$57
+    connect \src2_i$56 \fus_src2_i$58
+    connect \src2_i$57 \fus_src2_i$59
+    connect \src2_i$58 \fus_src2_i$60
     connect \src3_i \fus_src3_i
-    connect \src3_i$52 \fus_src3_i$54
-    connect \src3_i$53 \fus_src3_i$55
+    connect \src3_i$59 \fus_src3_i$61
+    connect \src3_i$60 \fus_src3_i$62
     connect \src4_i \fus_src4_i
-    connect \src3_i$54 \fus_src3_i$56
-    connect \src4_i$55 \fus_src4_i$57
+    connect \src3_i$61 \fus_src3_i$63
+    connect \src3_i$62 \fus_src3_i$64
+    connect \src4_i$63 \fus_src4_i$65
     connect \src6_i \fus_src6_i
-    connect \src4_i$56 \fus_src4_i$58
+    connect \src4_i$64 \fus_src4_i$66
     connect \src5_i \fus_src5_i
-    connect \src3_i$57 \fus_src3_i$59
-    connect \src4_i$58 \fus_src4_i$60
-    connect \cu_rd__rel_o$59 \fus_cu_rd__rel_o$61
-    connect \cu_rd__go_i$60 \fus_cu_rd__go_i$62
-    connect \src3_i$61 \fus_src3_i$63
-    connect \src5_i$62 \fus_src5_i$64
-    connect \src6_i$63 \fus_src6_i$65
-    connect \src1_i$64 \fus_src1_i$66
     connect \src3_i$65 \fus_src3_i$67
-    connect \src3_i$66 \fus_src3_i$68
-    connect \src2_i$67 \fus_src2_i$69
-    connect \src4_i$68 \fus_src4_i$70
-    connect \src2_i$69 \fus_src2_i$71
+    connect \src4_i$66 \fus_src4_i$68
+    connect \cu_rd__rel_o$67 \fus_cu_rd__rel_o$69
+    connect \cu_rd__go_i$68 \fus_cu_rd__go_i$70
+    connect \src3_i$69 \fus_src3_i$71
+    connect \src5_i$70 \fus_src5_i$72
+    connect \src6_i$71 \fus_src6_i$73
+    connect \src1_i$72 \fus_src1_i$74
+    connect \src3_i$73 \fus_src3_i$75
+    connect \src3_i$74 \fus_src3_i$76
+    connect \src2_i$75 \fus_src2_i$77
+    connect \src4_i$76 \fus_src4_i$78
+    connect \src2_i$77 \fus_src2_i$79
     connect \o_ok \fus_o_ok
     connect \cu_wr__rel_o \fus_cu_wr__rel_o
     connect \cu_wr__go_i \fus_cu_wr__go_i
-    connect \o_ok$70 \fus_o_ok$72
-    connect \cu_wr__rel_o$71 \fus_cu_wr__rel_o$73
-    connect \cu_wr__go_i$72 \fus_cu_wr__go_i$74
-    connect \o_ok$73 \fus_o_ok$75
-    connect \cu_wr__rel_o$74 \fus_cu_wr__rel_o$76
-    connect \cu_wr__go_i$75 \fus_cu_wr__go_i$77
-    connect \o_ok$76 \fus_o_ok$78
-    connect \cu_wr__rel_o$77 \fus_cu_wr__rel_o$79
-    connect \cu_wr__go_i$78 \fus_cu_wr__go_i$80
-    connect \o_ok$79 \fus_o_ok$81
-    connect \cu_wr__rel_o$80 \fus_cu_wr__rel_o$82
-    connect \cu_wr__go_i$81 \fus_cu_wr__go_i$83
-    connect \o_ok$82 \fus_o_ok$84
-    connect \cu_wr__rel_o$83 \fus_cu_wr__rel_o$85
-    connect \cu_wr__go_i$84 \fus_cu_wr__go_i$86
-    connect \o_ok$85 \fus_o_ok$87
-    connect \cu_wr__rel_o$86 \fus_cu_wr__rel_o$88
-    connect \cu_wr__go_i$87 \fus_cu_wr__go_i$89
+    connect \o_ok$78 \fus_o_ok$80
+    connect \cu_wr__rel_o$79 \fus_cu_wr__rel_o$81
+    connect \cu_wr__go_i$80 \fus_cu_wr__go_i$82
+    connect \o_ok$81 \fus_o_ok$83
+    connect \cu_wr__rel_o$82 \fus_cu_wr__rel_o$84
+    connect \cu_wr__go_i$83 \fus_cu_wr__go_i$85
+    connect \o_ok$84 \fus_o_ok$86
+    connect \cu_wr__rel_o$85 \fus_cu_wr__rel_o$87
+    connect \cu_wr__go_i$86 \fus_cu_wr__go_i$88
+    connect \o_ok$87 \fus_o_ok$89
     connect \cu_wr__rel_o$88 \fus_cu_wr__rel_o$90
     connect \cu_wr__go_i$89 \fus_cu_wr__go_i$91
+    connect \o_ok$90 \fus_o_ok$92
+    connect \cu_wr__rel_o$91 \fus_cu_wr__rel_o$93
+    connect \cu_wr__go_i$92 \fus_cu_wr__go_i$94
+    connect \o_ok$93 \fus_o_ok$95
+    connect \cu_wr__rel_o$94 \fus_cu_wr__rel_o$96
+    connect \cu_wr__go_i$95 \fus_cu_wr__go_i$97
+    connect \o_ok$96 \fus_o_ok$98
+    connect \cu_wr__rel_o$97 \fus_cu_wr__rel_o$99
+    connect \cu_wr__go_i$98 \fus_cu_wr__go_i$100
+    connect \cu_wr__rel_o$99 \fus_cu_wr__rel_o$101
+    connect \cu_wr__go_i$100 \fus_cu_wr__go_i$102
     connect \dest1_o \fus_dest1_o
-    connect \dest1_o$90 \fus_dest1_o$92
-    connect \dest1_o$91 \fus_dest1_o$93
-    connect \dest1_o$92 \fus_dest1_o$94
-    connect \dest1_o$93 \fus_dest1_o$95
-    connect \dest1_o$94 \fus_dest1_o$96
-    connect \dest1_o$95 \fus_dest1_o$97
+    connect \dest1_o$101 \fus_dest1_o$103
+    connect \dest1_o$102 \fus_dest1_o$104
+    connect \dest1_o$103 \fus_dest1_o$105
+    connect \dest1_o$104 \fus_dest1_o$106
+    connect \dest1_o$105 \fus_dest1_o$107
+    connect \dest1_o$106 \fus_dest1_o$108
+    connect \dest1_o$107 \fus_dest1_o$109
     connect \o \fus_o
     connect \ea \fus_ea
     connect \full_cr_ok \fus_full_cr_ok
     connect \dest2_o \fus_dest2_o
     connect \cr_a_ok \fus_cr_a_ok
-    connect \cr_a_ok$96 \fus_cr_a_ok$98
-    connect \cr_a_ok$97 \fus_cr_a_ok$99
-    connect \cr_a_ok$98 \fus_cr_a_ok$100
-    connect \cr_a_ok$99 \fus_cr_a_ok$101
-    connect \dest2_o$100 \fus_dest2_o$102
+    connect \cr_a_ok$108 \fus_cr_a_ok$110
+    connect \cr_a_ok$109 \fus_cr_a_ok$111
+    connect \cr_a_ok$110 \fus_cr_a_ok$112
+    connect \cr_a_ok$111 \fus_cr_a_ok$113
+    connect \cr_a_ok$112 \fus_cr_a_ok$114
+    connect \dest2_o$113 \fus_dest2_o$115
     connect \dest3_o \fus_dest3_o
-    connect \dest2_o$101 \fus_dest2_o$103
-    connect \dest2_o$102 \fus_dest2_o$104
-    connect \dest2_o$103 \fus_dest2_o$105
+    connect \dest2_o$114 \fus_dest2_o$116
+    connect \dest2_o$115 \fus_dest2_o$117
+    connect \dest2_o$116 \fus_dest2_o$118
+    connect \dest2_o$117 \fus_dest2_o$119
     connect \xer_ca_ok \fus_xer_ca_ok
-    connect \xer_ca_ok$104 \fus_xer_ca_ok$106
-    connect \xer_ca_ok$105 \fus_xer_ca_ok$107
-    connect \xer_ca_ok$106 \fus_xer_ca_ok$108
-    connect \dest3_o$107 \fus_dest3_o$109
-    connect \dest3_o$108 \fus_dest3_o$110
+    connect \xer_ca_ok$118 \fus_xer_ca_ok$120
+    connect \xer_ca_ok$119 \fus_xer_ca_ok$121
+    connect \xer_ca_ok$120 \fus_xer_ca_ok$122
+    connect \dest3_o$121 \fus_dest3_o$123
+    connect \dest3_o$122 \fus_dest3_o$124
     connect \dest6_o \fus_dest6_o
-    connect \dest3_o$109 \fus_dest3_o$111
+    connect \dest3_o$123 \fus_dest3_o$125
     connect \xer_ov_ok \fus_xer_ov_ok
-    connect \xer_ov_ok$110 \fus_xer_ov_ok$112
-    connect \xer_ov_ok$111 \fus_xer_ov_ok$113
+    connect \xer_ov_ok$124 \fus_xer_ov_ok$126
+    connect \xer_ov_ok$125 \fus_xer_ov_ok$127
+    connect \xer_ov_ok$126 \fus_xer_ov_ok$128
     connect \dest4_o \fus_dest4_o
     connect \dest5_o \fus_dest5_o
-    connect \dest3_o$112 \fus_dest3_o$114
+    connect \dest3_o$127 \fus_dest3_o$129
+    connect \dest3_o$128 \fus_dest3_o$130
     connect \xer_so_ok \fus_xer_so_ok
-    connect \xer_so_ok$113 \fus_xer_so_ok$115
-    connect \xer_so_ok$114 \fus_xer_so_ok$116
-    connect \dest5_o$115 \fus_dest5_o$117
-    connect \dest4_o$116 \fus_dest4_o$118
-    connect \dest4_o$117 \fus_dest4_o$119
+    connect \xer_so_ok$129 \fus_xer_so_ok$131
+    connect \xer_so_ok$130 \fus_xer_so_ok$132
+    connect \xer_so_ok$131 \fus_xer_so_ok$133
+    connect \dest5_o$132 \fus_dest5_o$134
+    connect \dest4_o$133 \fus_dest4_o$135
+    connect \dest4_o$134 \fus_dest4_o$136
+    connect \dest4_o$135 \fus_dest4_o$137
     connect \fast1_ok \fus_fast1_ok
-    connect \cu_wr__rel_o$118 \fus_cu_wr__rel_o$120
-    connect \cu_wr__go_i$119 \fus_cu_wr__go_i$121
-    connect \fast1_ok$120 \fus_fast1_ok$122
-    connect \fast1_ok$121 \fus_fast1_ok$123
-    connect \dest1_o$122 \fus_dest1_o$124
-    connect \dest2_o$123 \fus_dest2_o$125
-    connect \dest3_o$124 \fus_dest3_o$126
+    connect \cu_wr__rel_o$136 \fus_cu_wr__rel_o$138
+    connect \cu_wr__go_i$137 \fus_cu_wr__go_i$139
+    connect \fast1_ok$138 \fus_fast1_ok$140
+    connect \fast1_ok$139 \fus_fast1_ok$141
+    connect \dest1_o$140 \fus_dest1_o$142
+    connect \dest2_o$141 \fus_dest2_o$143
+    connect \dest3_o$142 \fus_dest3_o$144
     connect \fast2_ok \fus_fast2_ok
-    connect \fast2_ok$125 \fus_fast2_ok$127
-    connect \dest2_o$126 \fus_dest2_o$128
-    connect \dest3_o$127 \fus_dest3_o$129
+    connect \fast2_ok$143 \fus_fast2_ok$145
+    connect \dest2_o$144 \fus_dest2_o$146
+    connect \dest3_o$145 \fus_dest3_o$147
     connect \nia_ok \fus_nia_ok
-    connect \nia_ok$128 \fus_nia_ok$130
-    connect \dest3_o$129 \fus_dest3_o$131
-    connect \dest4_o$130 \fus_dest4_o$132
+    connect \nia_ok$146 \fus_nia_ok$148
+    connect \dest3_o$147 \fus_dest3_o$149
+    connect \dest4_o$148 \fus_dest4_o$150
     connect \msr_ok \fus_msr_ok
-    connect \dest5_o$131 \fus_dest5_o$133
+    connect \dest5_o$149 \fus_dest5_o$151
     connect \spr1_ok \fus_spr1_ok
-    connect \dest2_o$132 \fus_dest2_o$134
+    connect \dest2_o$150 \fus_dest2_o$152
+    connect \coresync_rst \coresync_rst
     connect \ldst_port0_is_ld_i \fus_ldst_port0_is_ld_i
     connect \ldst_port0_is_st_i \fus_ldst_port0_is_st_i
     connect \ldst_port0_data_len \fus_ldst_port0_data_len
@@ -148957,1450 +165039,3834 @@ module \core
     connect \ldst_port0_st_data_i \fus_ldst_port0_st_data_i
     connect \ldst_port0_st_data_i_ok \fus_ldst_port0_st_data_i_ok
   end
-  cell \l0 \l0
-    connect \rst \rst
-    connect \clk \clk
-    connect \ldst_port0_is_ld_i \fus_ldst_port0_is_ld_i
-    connect \ldst_port0_is_st_i \fus_ldst_port0_is_st_i
-    connect \ldst_port0_data_len \fus_ldst_port0_data_len
-    connect \ldst_port0_addr_i \fus_ldst_port0_addr_i
-    connect \ldst_port0_addr_i_ok \fus_ldst_port0_addr_i_ok
-    connect \ldst_port0_addr_exc_o \fus_ldst_port0_addr_exc_o
-    connect \ldst_port0_addr_ok_o \fus_ldst_port0_addr_ok_o
-    connect \ldst_port0_ld_data_o \fus_ldst_port0_ld_data_o
-    connect \ldst_port0_ld_data_o_ok \fus_ldst_port0_ld_data_o_ok
-    connect \ldst_port0_st_data_i \fus_ldst_port0_st_data_i
-    connect \ldst_port0_st_data_i_ok \fus_ldst_port0_st_data_i_ok
-    connect \dbus__cyc \dbus__cyc
-    connect \dbus__ack \dbus__ack
-    connect \dbus__err \dbus__err
-    connect \dbus__stb \dbus__stb
-    connect \dbus__dat_r \dbus__dat_r
-    connect \dbus__adr \dbus__adr
-    connect \dbus__sel \dbus__sel
-    connect \dbus__we \dbus__we
-    connect \dbus__dat_w \dbus__dat_w
+  cell \l0 \l0
+    connect \coresync_clk \coresync_clk
+    connect \coresync_rst \coresync_rst
+    connect \ldst_port0_is_ld_i \fus_ldst_port0_is_ld_i
+    connect \ldst_port0_is_st_i \fus_ldst_port0_is_st_i
+    connect \ldst_port0_data_len \fus_ldst_port0_data_len
+    connect \ldst_port0_addr_i \fus_ldst_port0_addr_i
+    connect \ldst_port0_addr_i_ok \fus_ldst_port0_addr_i_ok
+    connect \ldst_port0_addr_exc_o \fus_ldst_port0_addr_exc_o
+    connect \ldst_port0_addr_ok_o \fus_ldst_port0_addr_ok_o
+    connect \ldst_port0_ld_data_o \fus_ldst_port0_ld_data_o
+    connect \ldst_port0_ld_data_o_ok \fus_ldst_port0_ld_data_o_ok
+    connect \ldst_port0_st_data_i \fus_ldst_port0_st_data_i
+    connect \ldst_port0_st_data_i_ok \fus_ldst_port0_st_data_i_ok
+    connect \dbus__cyc \dbus__cyc
+    connect \dbus__ack \dbus__ack
+    connect \dbus__err \dbus__err
+    connect \dbus__stb \dbus__stb
+    connect \dbus__dat_r \dbus__dat_r
+    connect \dbus__adr \dbus__adr
+    connect \dbus__sel \dbus__sel
+    connect \dbus__we \dbus__we
+    connect \dbus__dat_w \dbus__dat_w
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 32 \int_src1__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 \int_src1__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 32 \int_src2__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 \int_src2__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 32 \int_src3__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 \int_src3__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 32 \int_wen
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 \int_data_i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 32 \int_wen$153
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 \int_data_i$154
+  cell \int \int
+    connect \coresync_clk \coresync_clk
+    connect \dmi__ren \dmi__ren
+    connect \dmi__data_o \dmi__data_o
+    connect \src1__ren \int_src1__ren
+    connect \src1__data_o \int_src1__data_o
+    connect \src2__ren \int_src2__ren
+    connect \src2__data_o \int_src2__data_o
+    connect \src3__ren \int_src3__ren
+    connect \src3__data_o \int_src3__data_o
+    connect \wen \int_wen
+    connect \data_i \int_data_i
+    connect \wen$1 \int_wen$153
+    connect \data_i$2 \int_data_i$154
+    connect \coresync_rst \coresync_rst
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 8 \cr_full_rd__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 32 \cr_full_rd__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 8 \cr_src1__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 4 \cr_src1__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 8 \cr_src2__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 4 \cr_src2__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 8 \cr_src3__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 4 \cr_src3__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 8 \cr_full_wr__wen
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 32 \cr_full_wr__data_i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 8 \cr_wen
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 4 \cr_data_i
+  cell \cr \cr
+    connect \coresync_clk \coresync_clk
+    connect \full_rd__ren \cr_full_rd__ren
+    connect \full_rd__data_o \cr_full_rd__data_o
+    connect \src1__ren \cr_src1__ren
+    connect \src1__data_o \cr_src1__data_o
+    connect \src2__ren \cr_src2__ren
+    connect \src2__data_o \cr_src2__data_o
+    connect \src3__ren \cr_src3__ren
+    connect \src3__data_o \cr_src3__data_o
+    connect \full_wr__wen \cr_full_wr__wen
+    connect \full_wr__data_i \cr_full_wr__data_i
+    connect \wen \cr_wen
+    connect \data_i \cr_data_i
+    connect \coresync_rst \coresync_rst
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 3 \xer_src1__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 2 \xer_src1__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 3 \xer_src2__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 2 \xer_src2__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 3 \xer_src3__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 2 \xer_src3__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 3 \xer_wen
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 2 \xer_data_i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 3 \xer_wen$155
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 2 \xer_data_i$156
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 3 \xer_wen$157
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 2 \xer_data_i$158
+  cell \xer \xer
+    connect \coresync_clk \coresync_clk
+    connect \src1__ren \xer_src1__ren
+    connect \src1__data_o \xer_src1__data_o
+    connect \src2__ren \xer_src2__ren
+    connect \src2__data_o \xer_src2__data_o
+    connect \src3__ren \xer_src3__ren
+    connect \src3__data_o \xer_src3__data_o
+    connect \wen \xer_wen
+    connect \data_i \xer_data_i
+    connect \wen$1 \xer_wen$155
+    connect \data_i$2 \xer_data_i$156
+    connect \wen$3 \xer_wen$157
+    connect \data_i$4 \xer_data_i$158
+    connect \coresync_rst \coresync_rst
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 8 \fast_src1__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 \fast_src1__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 8 \fast_src2__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 \fast_src2__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 8 \fast_wen
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 \fast_data_i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 8 \fast_wen$159
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 \fast_data_i$160
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 \fast_data_i$161
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 8 \fast_wen$162
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 \fast_data_i$163
+  cell \fast \fast
+    connect \coresync_clk \coresync_clk
+    connect \cia__ren \cia__ren
+    connect \cia__data_o \cia__data_o
+    connect \msr__ren \msr__ren
+    connect \msr__data_o \msr__data_o
+    connect \fast_nia_wen \fast_nia_wen
+    connect \wen \wen
+    connect \data_i \data_i
+    connect \src1__ren \fast_src1__ren
+    connect \src1__data_o \fast_src1__data_o
+    connect \src2__ren \fast_src2__ren
+    connect \src2__data_o \fast_src2__data_o
+    connect \wen$1 \fast_wen
+    connect \data_i$2 \fast_data_i
+    connect \wen$3 \fast_wen$159
+    connect \data_i$4 \fast_data_i$160
+    connect \data_i$5 \fast_data_i$161
+    connect \wen$6 \fast_wen$162
+    connect \data_i$7 \fast_data_i$163
+    connect \coresync_rst \coresync_rst
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 \spr_src__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 \spr_src__data_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 1 \spr_dest__wen
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 \spr_dest__data_i
+  cell \spr \spr
+    connect \coresync_clk \coresync_clk
+    connect \src__ren \spr_src__ren
+    connect \src__data_o \spr_src__data_o
+    connect \dest__wen \spr_dest__wen
+    connect \dest__data_i \spr_dest__data_i
+    connect \coresync_rst \coresync_rst
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
+  wire width 1 \rdpick_INT_ra_en_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
+  wire width 9 \rdpick_INT_ra_i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
+  wire width 9 \rdpick_INT_ra_o
+  cell \rdpick_INT_ra \rdpick_INT_ra
+    connect \en_o \rdpick_INT_ra_en_o
+    connect \i \rdpick_INT_ra_i
+    connect \o \rdpick_INT_ra_o
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
+  wire width 1 \rdpick_INT_rb_en_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
+  wire width 8 \rdpick_INT_rb_i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
+  wire width 8 \rdpick_INT_rb_o
+  cell \rdpick_INT_rb \rdpick_INT_rb
+    connect \en_o \rdpick_INT_rb_en_o
+    connect \i \rdpick_INT_rb_i
+    connect \o \rdpick_INT_rb_o
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
+  wire width 1 \rdpick_INT_rc_en_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
+  wire width 2 \rdpick_INT_rc_i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
+  wire width 2 \rdpick_INT_rc_o
+  cell \rdpick_INT_rc \rdpick_INT_rc
+    connect \en_o \rdpick_INT_rc_en_o
+    connect \i \rdpick_INT_rc_i
+    connect \o \rdpick_INT_rc_o
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
+  wire width 1 \rdpick_XER_xer_so_en_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
+  wire width 4 \rdpick_XER_xer_so_i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
+  wire width 4 \rdpick_XER_xer_so_o
+  cell \rdpick_XER_xer_so \rdpick_XER_xer_so
+    connect \en_o \rdpick_XER_xer_so_en_o
+    connect \i \rdpick_XER_xer_so_i
+    connect \o \rdpick_XER_xer_so_o
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
+  wire width 1 \rdpick_XER_xer_ca_en_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
+  wire width 3 \rdpick_XER_xer_ca_i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
+  wire width 3 \rdpick_XER_xer_ca_o
+  cell \rdpick_XER_xer_ca \rdpick_XER_xer_ca
+    connect \en_o \rdpick_XER_xer_ca_en_o
+    connect \i \rdpick_XER_xer_ca_i
+    connect \o \rdpick_XER_xer_ca_o
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
+  wire width 1 \rdpick_XER_xer_ov_en_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
+  wire width 1 \rdpick_XER_xer_ov_i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
+  wire width 1 \rdpick_XER_xer_ov_o
+  cell \rdpick_XER_xer_ov \rdpick_XER_xer_ov
+    connect \en_o \rdpick_XER_xer_ov_en_o
+    connect \i \rdpick_XER_xer_ov_i
+    connect \o \rdpick_XER_xer_ov_o
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
+  wire width 1 \rdpick_CR_full_cr_en_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
+  wire width 1 \rdpick_CR_full_cr_i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
+  wire width 1 \rdpick_CR_full_cr_o
+  cell \rdpick_CR_full_cr \rdpick_CR_full_cr
+    connect \en_o \rdpick_CR_full_cr_en_o
+    connect \i \rdpick_CR_full_cr_i
+    connect \o \rdpick_CR_full_cr_o
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
+  wire width 1 \rdpick_CR_cr_a_en_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
+  wire width 2 \rdpick_CR_cr_a_i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
+  wire width 2 \rdpick_CR_cr_a_o
+  cell \rdpick_CR_cr_a \rdpick_CR_cr_a
+    connect \en_o \rdpick_CR_cr_a_en_o
+    connect \i \rdpick_CR_cr_a_i
+    connect \o \rdpick_CR_cr_a_o
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
+  wire width 1 \rdpick_CR_cr_b_en_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
+  wire width 1 \rdpick_CR_cr_b_i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
+  wire width 1 \rdpick_CR_cr_b_o
+  cell \rdpick_CR_cr_b \rdpick_CR_cr_b
+    connect \en_o \rdpick_CR_cr_b_en_o
+    connect \i \rdpick_CR_cr_b_i
+    connect \o \rdpick_CR_cr_b_o
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
+  wire width 1 \rdpick_CR_cr_c_en_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
+  wire width 1 \rdpick_CR_cr_c_i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
+  wire width 1 \rdpick_CR_cr_c_o
+  cell \rdpick_CR_cr_c \rdpick_CR_cr_c
+    connect \en_o \rdpick_CR_cr_c_en_o
+    connect \i \rdpick_CR_cr_c_i
+    connect \o \rdpick_CR_cr_c_o
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
+  wire width 1 \rdpick_FAST_fast1_en_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
+  wire width 3 \rdpick_FAST_fast1_i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
+  wire width 3 \rdpick_FAST_fast1_o
+  cell \rdpick_FAST_fast1 \rdpick_FAST_fast1
+    connect \en_o \rdpick_FAST_fast1_en_o
+    connect \i \rdpick_FAST_fast1_i
+    connect \o \rdpick_FAST_fast1_o
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
+  wire width 1 \rdpick_FAST_fast2_en_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
+  wire width 2 \rdpick_FAST_fast2_i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
+  wire width 2 \rdpick_FAST_fast2_o
+  cell \rdpick_FAST_fast2 \rdpick_FAST_fast2
+    connect \en_o \rdpick_FAST_fast2_en_o
+    connect \i \rdpick_FAST_fast2_i
+    connect \o \rdpick_FAST_fast2_o
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
+  wire width 1 \rdpick_SPR_spr1_en_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
+  wire width 1 \rdpick_SPR_spr1_i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
+  wire width 1 \rdpick_SPR_spr1_o
+  cell \rdpick_SPR_spr1 \rdpick_SPR_spr1
+    connect \en_o \rdpick_SPR_spr1_en_o
+    connect \i \rdpick_SPR_spr1_i
+    connect \o \rdpick_SPR_spr1_o
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
+  wire width 1 \wrpick_INT_o_en_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
+  wire width 9 \wrpick_INT_o_i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
+  wire width 9 \wrpick_INT_o_o
+  cell \wrpick_INT_o \wrpick_INT_o
+    connect \en_o \wrpick_INT_o_en_o
+    connect \i \wrpick_INT_o_i
+    connect \o \wrpick_INT_o_o
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
+  wire width 1 \wrpick_INT_o1_en_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
+  wire width 1 \wrpick_INT_o1_i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
+  wire width 1 \wrpick_INT_o1_o
+  cell \wrpick_INT_o1 \wrpick_INT_o1
+    connect \en_o \wrpick_INT_o1_en_o
+    connect \i \wrpick_INT_o1_i
+    connect \o \wrpick_INT_o1_o
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
+  wire width 1 \wrpick_CR_full_cr_en_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
+  wire width 1 \wrpick_CR_full_cr_i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
+  wire width 1 \wrpick_CR_full_cr_o
+  cell \wrpick_CR_full_cr \wrpick_CR_full_cr
+    connect \en_o \wrpick_CR_full_cr_en_o
+    connect \i \wrpick_CR_full_cr_i
+    connect \o \wrpick_CR_full_cr_o
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
+  wire width 1 \wrpick_CR_cr_a_en_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
+  wire width 6 \wrpick_CR_cr_a_i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
+  wire width 6 \wrpick_CR_cr_a_o
+  cell \wrpick_CR_cr_a \wrpick_CR_cr_a
+    connect \en_o \wrpick_CR_cr_a_en_o
+    connect \i \wrpick_CR_cr_a_i
+    connect \o \wrpick_CR_cr_a_o
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
+  wire width 1 \wrpick_XER_xer_ca_en_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
+  wire width 4 \wrpick_XER_xer_ca_i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
+  wire width 4 \wrpick_XER_xer_ca_o
+  cell \wrpick_XER_xer_ca \wrpick_XER_xer_ca
+    connect \en_o \wrpick_XER_xer_ca_en_o
+    connect \i \wrpick_XER_xer_ca_i
+    connect \o \wrpick_XER_xer_ca_o
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
+  wire width 1 \wrpick_XER_xer_ov_en_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
+  wire width 4 \wrpick_XER_xer_ov_i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
+  wire width 4 \wrpick_XER_xer_ov_o
+  cell \wrpick_XER_xer_ov \wrpick_XER_xer_ov
+    connect \en_o \wrpick_XER_xer_ov_en_o
+    connect \i \wrpick_XER_xer_ov_i
+    connect \o \wrpick_XER_xer_ov_o
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
+  wire width 1 \wrpick_XER_xer_so_en_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
+  wire width 4 \wrpick_XER_xer_so_i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
+  wire width 4 \wrpick_XER_xer_so_o
+  cell \wrpick_XER_xer_so \wrpick_XER_xer_so
+    connect \en_o \wrpick_XER_xer_so_en_o
+    connect \i \wrpick_XER_xer_so_i
+    connect \o \wrpick_XER_xer_so_o
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
+  wire width 1 \wrpick_FAST_fast1_en_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
+  wire width 3 \wrpick_FAST_fast1_i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
+  wire width 3 \wrpick_FAST_fast1_o
+  cell \wrpick_FAST_fast1 \wrpick_FAST_fast1
+    connect \en_o \wrpick_FAST_fast1_en_o
+    connect \i \wrpick_FAST_fast1_i
+    connect \o \wrpick_FAST_fast1_o
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
+  wire width 1 \wrpick_FAST_fast2_en_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
+  wire width 2 \wrpick_FAST_fast2_i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
+  wire width 2 \wrpick_FAST_fast2_o
+  cell \wrpick_FAST_fast2 \wrpick_FAST_fast2
+    connect \en_o \wrpick_FAST_fast2_en_o
+    connect \i \wrpick_FAST_fast2_i
+    connect \o \wrpick_FAST_fast2_o
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
+  wire width 1 \wrpick_FAST_nia_en_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
+  wire width 2 \wrpick_FAST_nia_i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
+  wire width 2 \wrpick_FAST_nia_o
+  cell \wrpick_FAST_nia \wrpick_FAST_nia
+    connect \en_o \wrpick_FAST_nia_en_o
+    connect \i \wrpick_FAST_nia_i
+    connect \o \wrpick_FAST_nia_o
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
+  wire width 1 \wrpick_FAST_msr_en_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
+  wire width 1 \wrpick_FAST_msr_i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
+  wire width 1 \wrpick_FAST_msr_o
+  cell \wrpick_FAST_msr \wrpick_FAST_msr
+    connect \en_o \wrpick_FAST_msr_en_o
+    connect \i \wrpick_FAST_msr_i
+    connect \o \wrpick_FAST_msr_o
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
+  wire width 1 \wrpick_SPR_spr1_en_o
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
+  wire width 1 \wrpick_SPR_spr1_i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
+  wire width 1 \wrpick_SPR_spr1_o
+  cell \wrpick_SPR_spr1 \wrpick_SPR_spr1
+    connect \en_o \wrpick_SPR_spr1_en_o
+    connect \i \wrpick_SPR_spr1_i
+    connect \o \wrpick_SPR_spr1_o
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:138"
+  wire width 1 \en_alu0
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:139"
+  wire width 1 $164
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:139"
+  wire width 11 $165
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:139"
+  cell $and $166
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 11
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 2
+    parameter \Y_WIDTH 11
+    connect \A \pdecode2_fn_unit
+    connect \B 2'10
+    connect \Y $165
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:139"
+  cell $reduce_bool $167
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 11
+    parameter \Y_WIDTH 1
+    connect \A $165
+    connect \Y $164
+  end
+  process $group_0
+    assign \en_alu0 1'0
+    assign \en_alu0 $164
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:128"
+  wire width 10 \fu_enable
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:138"
+  wire width 1 \en_cr0
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:138"
+  wire width 1 \en_branch0
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:138"
+  wire width 1 \en_trap0
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:138"
+  wire width 1 \en_logical0
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:138"
+  wire width 1 \en_spr0
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:138"
+  wire width 1 \en_div0
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:138"
+  wire width 1 \en_mul0
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:138"
+  wire width 1 \en_shiftrot0
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:138"
+  wire width 1 \en_ldst0
+  process $group_1
+    assign \fu_enable 10'0000000000
+    assign \fu_enable [0] \en_alu0
+    assign \fu_enable [1] \en_cr0
+    assign \fu_enable [2] \en_branch0
+    assign \fu_enable [3] \en_trap0
+    assign \fu_enable [4] \en_logical0
+    assign \fu_enable [5] \en_spr0
+    assign \fu_enable [6] \en_div0
+    assign \fu_enable [7] \en_mul0
+    assign \fu_enable [8] \en_shiftrot0
+    assign \fu_enable [9] \en_ldst0
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:139"
+  wire width 1 $168
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:139"
+  wire width 11 $169
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:139"
+  cell $and $170
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 11
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 7
+    parameter \Y_WIDTH 11
+    connect \A \pdecode2_fn_unit
+    connect \B 7'1000000
+    connect \Y $169
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:139"
+  cell $reduce_bool $171
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 11
+    parameter \Y_WIDTH 1
+    connect \A $169
+    connect \Y $168
+  end
+  process $group_2
+    assign \en_cr0 1'0
+    assign \en_cr0 $168
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:139"
+  wire width 1 $172
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:139"
+  wire width 11 $173
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:139"
+  cell $and $174
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 11
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 6
+    parameter \Y_WIDTH 11
+    connect \A \pdecode2_fn_unit
+    connect \B 6'100000
+    connect \Y $173
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:139"
+  cell $reduce_bool $175
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 11
+    parameter \Y_WIDTH 1
+    connect \A $173
+    connect \Y $172
+  end
+  process $group_3
+    assign \en_branch0 1'0
+    assign \en_branch0 $172
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:139"
+  wire width 1 $176
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:139"
+  wire width 11 $177
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:139"
+  cell $and $178
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 11
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 8
+    parameter \Y_WIDTH 11
+    connect \A \pdecode2_fn_unit
+    connect \B 8'10000000
+    connect \Y $177
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:139"
+  cell $reduce_bool $179
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 11
+    parameter \Y_WIDTH 1
+    connect \A $177
+    connect \Y $176
+  end
+  process $group_4
+    assign \en_trap0 1'0
+    assign \en_trap0 $176
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:139"
+  wire width 1 $180
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:139"
+  wire width 11 $181
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:139"
+  cell $and $182
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 11
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 5
+    parameter \Y_WIDTH 11
+    connect \A \pdecode2_fn_unit
+    connect \B 5'10000
+    connect \Y $181
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:139"
+  cell $reduce_bool $183
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 11
+    parameter \Y_WIDTH 1
+    connect \A $181
+    connect \Y $180
+  end
+  process $group_5
+    assign \en_logical0 1'0
+    assign \en_logical0 $180
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:139"
+  wire width 1 $184
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:139"
+  wire width 11 $185
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:139"
+  cell $and $186
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 11
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 11
+    parameter \Y_WIDTH 11
+    connect \A \pdecode2_fn_unit
+    connect \B 11'10000000000
+    connect \Y $185
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:139"
+  cell $reduce_bool $187
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 11
+    parameter \Y_WIDTH 1
+    connect \A $185
+    connect \Y $184
+  end
+  process $group_6
+    assign \en_spr0 1'0
+    assign \en_spr0 $184
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:139"
+  wire width 1 $188
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:139"
+  wire width 11 $189
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:139"
+  cell $and $190
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 11
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 10
+    parameter \Y_WIDTH 11
+    connect \A \pdecode2_fn_unit
+    connect \B 10'1000000000
+    connect \Y $189
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:139"
+  cell $reduce_bool $191
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 11
+    parameter \Y_WIDTH 1
+    connect \A $189
+    connect \Y $188
+  end
+  process $group_7
+    assign \en_div0 1'0
+    assign \en_div0 $188
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:139"
+  wire width 1 $192
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:139"
+  wire width 11 $193
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:139"
+  cell $and $194
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 11
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 9
+    parameter \Y_WIDTH 11
+    connect \A \pdecode2_fn_unit
+    connect \B 9'100000000
+    connect \Y $193
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:139"
+  cell $reduce_bool $195
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 11
+    parameter \Y_WIDTH 1
+    connect \A $193
+    connect \Y $192
+  end
+  process $group_8
+    assign \en_mul0 1'0
+    assign \en_mul0 $192
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:139"
+  wire width 1 $196
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:139"
+  wire width 11 $197
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:139"
+  cell $and $198
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 11
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 4
+    parameter \Y_WIDTH 11
+    connect \A \pdecode2_fn_unit
+    connect \B 4'1000
+    connect \Y $197
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:139"
+  cell $reduce_bool $199
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 11
+    parameter \Y_WIDTH 1
+    connect \A $197
+    connect \Y $196
+  end
+  process $group_9
+    assign \en_shiftrot0 1'0
+    assign \en_shiftrot0 $196
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:139"
+  wire width 1 $200
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:139"
+  wire width 11 $201
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:139"
+  cell $and $202
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 11
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 3
+    parameter \Y_WIDTH 11
+    connect \A \pdecode2_fn_unit
+    connect \B 3'100
+    connect \Y $201
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:139"
+  cell $reduce_bool $203
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 11
+    parameter \Y_WIDTH 1
+    connect \A $201
+    connect \Y $200
+  end
+  process $group_10
+    assign \en_ldst0 1'0
+    assign \en_ldst0 $200
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:143"
+  wire width 2 \counter
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:143"
+  wire width 2 \counter$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:144"
+  wire width 1 $204
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:144"
+  cell $ne $205
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 2
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \counter
+    connect \B 1'0
+    connect \Y $204
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:145"
+  wire width 3 $206
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:145"
+  wire width 3 $207
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:145"
+  cell $sub $208
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 2
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 3
+    connect \A \counter
+    connect \B 1'1
+    connect \Y $207
+  end
+  connect $206 $207
+  process $group_11
+    assign \counter$next \counter
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:144"
+    switch { $204 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:144"
+      case 1'1
+        assign \counter$next $206 [1:0]
+    end
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+            assign \counter$next 2'10
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+          attribute \nmigen.decoding ""
+          case
+        end
+    end
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
+      case 1'1
+        assign \counter$next 2'00
+    end
+    sync init
+      update \counter 2'00
+    sync posedge \coresync_clk
+      update \counter \counter$next
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:144"
+  wire width 1 $209
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:144"
+  cell $ne $210
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 2
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \counter
+    connect \B 1'0
+    connect \Y $209
+  end
+  process $group_12
+    assign \corebusy_o 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:144"
+    switch { $209 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:144"
+      case 1'1
+        assign \corebusy_o 1'1
+    end
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+            assign \corebusy_o 1'1
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            switch { \fu_enable [0] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+              case 1'1
+                assign \corebusy_o \fus_cu_busy_o
+            end
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            switch { \fu_enable [1] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+              case 1'1
+                assign \corebusy_o \fus_cu_busy_o$4
+            end
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            switch { \fu_enable [2] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+              case 1'1
+                assign \corebusy_o \fus_cu_busy_o$7
+            end
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            switch { \fu_enable [3] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+              case 1'1
+                assign \corebusy_o \fus_cu_busy_o$10
+            end
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            switch { \fu_enable [4] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+              case 1'1
+                assign \corebusy_o \fus_cu_busy_o$13
+            end
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            switch { \fu_enable [5] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+              case 1'1
+                assign \corebusy_o \fus_cu_busy_o$16
+            end
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            switch { \fu_enable [6] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+              case 1'1
+                assign \corebusy_o \fus_cu_busy_o$19
+            end
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            switch { \fu_enable [7] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+              case 1'1
+                assign \corebusy_o \fus_cu_busy_o$22
+            end
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            switch { \fu_enable [8] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+              case 1'1
+                assign \corebusy_o \fus_cu_busy_o$25
+            end
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            switch { \fu_enable [9] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+              case 1'1
+                assign \corebusy_o \fus_cu_busy_o$28
+            end
+        end
+    end
+    sync init
+  end
+  process $group_13
+    assign \core_terminate_o$next \core_terminate_o
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+            assign \core_terminate_o$next 1'1
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+          attribute \nmigen.decoding ""
+          case
+        end
+    end
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \coresync_rst
+      case 1'1
+        assign \core_terminate_o$next 1'0
+    end
+    sync init
+      update \core_terminate_o 1'0
+    sync posedge \coresync_clk
+      update \core_terminate_o \core_terminate_o$next
+  end
+  process $group_14
+    assign \fus_oper_i_alu_alu0__insn_type 7'0000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            switch { \fu_enable [0] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+              case 1'1
+                assign \fus_oper_i_alu_alu0__insn_type \insn_type
+            end
+        end
+    end
+    sync init
+  end
+  process $group_15
+    assign \fus_oper_i_alu_alu0__fn_unit 11'00000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            switch { \fu_enable [0] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+              case 1'1
+                assign \fus_oper_i_alu_alu0__fn_unit \pdecode2_fn_unit
+            end
+        end
+    end
+    sync init
+  end
+  process $group_16
+    assign \fus_oper_i_alu_alu0__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \fus_oper_i_alu_alu0__imm_data__imm_ok 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            switch { \fu_enable [0] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+              case 1'1
+                assign { \fus_oper_i_alu_alu0__imm_data__imm_ok \fus_oper_i_alu_alu0__imm_data__imm } { \pdecode2_imm_ok \pdecode2_imm }
+            end
+        end
+    end
+    sync init
+  end
+  process $group_18
+    assign \fus_oper_i_alu_alu0__rc__rc 1'0
+    assign \fus_oper_i_alu_alu0__rc__rc_ok 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            switch { \fu_enable [0] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+              case 1'1
+                assign { \fus_oper_i_alu_alu0__rc__rc_ok \fus_oper_i_alu_alu0__rc__rc } { \pdecode2_rc_ok \pdecode2_rc }
+            end
+        end
+    end
+    sync init
+  end
+  process $group_20
+    assign \fus_oper_i_alu_alu0__oe__oe 1'0
+    assign \fus_oper_i_alu_alu0__oe__oe_ok 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            switch { \fu_enable [0] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+              case 1'1
+                assign { \fus_oper_i_alu_alu0__oe__oe_ok \fus_oper_i_alu_alu0__oe__oe } { \pdecode2_oe_ok \pdecode2_oe }
+            end
+        end
+    end
+    sync init
+  end
+  process $group_22
+    assign \fus_oper_i_alu_alu0__invert_a 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            switch { \fu_enable [0] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+              case 1'1
+                assign \fus_oper_i_alu_alu0__invert_a \pdecode2_invert_a
+            end
+        end
+    end
+    sync init
+  end
+  process $group_23
+    assign \fus_oper_i_alu_alu0__zero_a 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            switch { \fu_enable [0] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+              case 1'1
+                assign \fus_oper_i_alu_alu0__zero_a \pdecode2_zero_a
+            end
+        end
+    end
+    sync init
+  end
+  process $group_24
+    assign \fus_oper_i_alu_alu0__invert_out 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            switch { \fu_enable [0] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+              case 1'1
+                assign \fus_oper_i_alu_alu0__invert_out \pdecode2_invert_out
+            end
+        end
+    end
+    sync init
+  end
+  process $group_25
+    assign \fus_oper_i_alu_alu0__write_cr0 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            switch { \fu_enable [0] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+              case 1'1
+                assign \fus_oper_i_alu_alu0__write_cr0 \pdecode2_write_cr0
+            end
+        end
+    end
+    sync init
+  end
+  process $group_26
+    assign \fus_oper_i_alu_alu0__input_carry 2'00
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            switch { \fu_enable [0] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+              case 1'1
+                assign \fus_oper_i_alu_alu0__input_carry \pdecode2_input_carry
+            end
+        end
+    end
+    sync init
+  end
+  process $group_27
+    assign \fus_oper_i_alu_alu0__output_carry 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            switch { \fu_enable [0] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+              case 1'1
+                assign \fus_oper_i_alu_alu0__output_carry \pdecode2_output_carry
+            end
+        end
+    end
+    sync init
+  end
+  process $group_28
+    assign \fus_oper_i_alu_alu0__is_32bit 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            switch { \fu_enable [0] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+              case 1'1
+                assign \fus_oper_i_alu_alu0__is_32bit \pdecode2_is_32bit
+            end
+        end
+    end
+    sync init
+  end
+  process $group_29
+    assign \fus_oper_i_alu_alu0__is_signed 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            switch { \fu_enable [0] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+              case 1'1
+                assign \fus_oper_i_alu_alu0__is_signed \pdecode2_is_signed
+            end
+        end
+    end
+    sync init
+  end
+  process $group_30
+    assign \fus_oper_i_alu_alu0__data_len 4'0000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            switch { \fu_enable [0] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+              case 1'1
+                assign \fus_oper_i_alu_alu0__data_len \pdecode2_data_len
+            end
+        end
+    end
+    sync init
+  end
+  process $group_31
+    assign \fus_oper_i_alu_alu0__insn 32'00000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            switch { \fu_enable [0] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+              case 1'1
+                assign \fus_oper_i_alu_alu0__insn \pdecode2_insn
+            end
+        end
+    end
+    sync init
+  end
+  process $group_32
+    assign \fus_cu_issue_i 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            switch { \fu_enable [0] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+              case 1'1
+                assign \fus_cu_issue_i \issue_i
+            end
+        end
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:170"
+  wire width 4 $211
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79"
+  wire width 1 $212
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79"
+  cell $and $213
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \pdecode2_oe
+    connect \B \pdecode2_oe_ok
+    connect \Y $212
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79"
+  wire width 1 $214
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79"
+  cell $or $215
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $212
+    connect \B \pdecode2_xer_in
+    connect \Y $214
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83"
+  wire width 1 $216
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83"
+  cell $eq $217
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 2
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 2
+    parameter \Y_WIDTH 1
+    connect \A \pdecode2_input_carry
+    connect \B 2'10
+    connect \Y $216
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83"
+  wire width 1 $218
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83"
+  cell $or $219
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $216
+    connect \B \pdecode2_xer_in
+    connect \Y $218
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:170"
+  cell $not $220
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 4
+    parameter \Y_WIDTH 4
+    connect \A { $218 $214 \pdecode2_reg2_ok \pdecode2_reg1_ok }
+    connect \Y $211
+  end
+  process $group_33
+    assign \fus_cu_rdmaskn_i 4'0000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            switch { \fu_enable [0] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+              case 1'1
+                assign \fus_cu_rdmaskn_i $211
+            end
+        end
+    end
+    sync init
+  end
+  process $group_34
+    assign \fus_oper_i_alu_cr0__insn_type 7'0000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            switch { \fu_enable [1] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+              case 1'1
+                assign \fus_oper_i_alu_cr0__insn_type \insn_type
+            end
+        end
+    end
+    sync init
+  end
+  process $group_35
+    assign \fus_oper_i_alu_cr0__fn_unit 11'00000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            switch { \fu_enable [1] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+              case 1'1
+                assign \fus_oper_i_alu_cr0__fn_unit \pdecode2_fn_unit
+            end
+        end
+    end
+    sync init
+  end
+  process $group_36
+    assign \fus_oper_i_alu_cr0__insn 32'00000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            switch { \fu_enable [1] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+              case 1'1
+                assign \fus_oper_i_alu_cr0__insn \pdecode2_insn
+            end
+        end
+    end
+    sync init
+  end
+  process $group_37
+    assign \fus_oper_i_alu_cr0__read_cr_whole 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            switch { \fu_enable [1] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+              case 1'1
+                assign \fus_oper_i_alu_cr0__read_cr_whole \pdecode2_read_cr_whole
+            end
+        end
+    end
+    sync init
+  end
+  process $group_38
+    assign \fus_oper_i_alu_cr0__write_cr_whole 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            switch { \fu_enable [1] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+              case 1'1
+                assign \fus_oper_i_alu_cr0__write_cr_whole \pdecode2_write_cr_whole
+            end
+        end
+    end
+    sync init
+  end
+  process $group_39
+    assign \fus_cu_issue_i$3 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            switch { \fu_enable [1] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+              case 1'1
+                assign \fus_cu_issue_i$3 \issue_i
+            end
+        end
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:170"
+  wire width 6 $221
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:170"
+  cell $not $222
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 6
+    parameter \Y_WIDTH 6
+    connect \A { \pdecode2_cr_in2_ok$1 \pdecode2_cr_in2_ok \pdecode2_cr_in1_ok \pdecode2_read_cr_whole \pdecode2_reg2_ok \pdecode2_reg1_ok }
+    connect \Y $221
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 32 \int_src1__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \int_src1__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 32 \int_src2__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \int_src2__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 32 \int_src3__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \int_src3__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 32 \int_wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \int_data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 32 \int_wen$135
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \int_data_i$136
-  cell \int \int
-    connect \rst \rst
-    connect \clk \clk
-    connect \src1__ren \int_src1__ren
-    connect \src1__data_o \int_src1__data_o
-    connect \src2__ren \int_src2__ren
-    connect \src2__data_o \int_src2__data_o
-    connect \src3__ren \int_src3__ren
-    connect \src3__data_o \int_src3__data_o
-    connect \wen \int_wen
-    connect \data_i \int_data_i
-    connect \wen$1 \int_wen$135
-    connect \data_i$2 \int_data_i$136
+  process $group_40
+    assign \fus_cu_rdmaskn_i$5 6'000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            switch { \fu_enable [1] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+              case 1'1
+                assign \fus_cu_rdmaskn_i$5 $221
+            end
+        end
+    end
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 8 \cr_full_rd__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 32 \cr_full_rd__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 8 \cr_src1__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 4 \cr_src1__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 8 \cr_src2__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 4 \cr_src2__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 8 \cr_src3__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 4 \cr_src3__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 8 \cr_full_wr__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 32 \cr_full_wr__data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 8 \cr_wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 4 \cr_data_i
-  cell \cr \cr
-    connect \rst \rst
-    connect \clk \clk
-    connect \full_rd__ren \cr_full_rd__ren
-    connect \full_rd__data_o \cr_full_rd__data_o
-    connect \src1__ren \cr_src1__ren
-    connect \src1__data_o \cr_src1__data_o
-    connect \src2__ren \cr_src2__ren
-    connect \src2__data_o \cr_src2__data_o
-    connect \src3__ren \cr_src3__ren
-    connect \src3__data_o \cr_src3__data_o
-    connect \full_wr__wen \cr_full_wr__wen
-    connect \full_wr__data_i \cr_full_wr__data_i
-    connect \wen \cr_wen
-    connect \data_i \cr_data_i
+  process $group_41
+    assign \fus_oper_i_alu_branch0__cia 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            switch { \fu_enable [2] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+              case 1'1
+                assign \fus_oper_i_alu_branch0__cia \pdecode2_cia
+            end
+        end
+    end
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 3 \xer_src1__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 2 \xer_src1__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 3 \xer_src2__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 2 \xer_src2__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 3 \xer_src3__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 2 \xer_src3__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 3 \xer_wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 2 \xer_data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 3 \xer_wen$137
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 2 \xer_data_i$138
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 3 \xer_wen$139
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 2 \xer_data_i$140
-  cell \xer \xer
-    connect \rst \rst
-    connect \clk \clk
-    connect \src1__ren \xer_src1__ren
-    connect \src1__data_o \xer_src1__data_o
-    connect \src2__ren \xer_src2__ren
-    connect \src2__data_o \xer_src2__data_o
-    connect \src3__ren \xer_src3__ren
-    connect \src3__data_o \xer_src3__data_o
-    connect \wen \xer_wen
-    connect \data_i \xer_data_i
-    connect \wen$1 \xer_wen$137
-    connect \data_i$2 \xer_data_i$138
-    connect \wen$3 \xer_wen$139
-    connect \data_i$4 \xer_data_i$140
+  process $group_42
+    assign \fus_oper_i_alu_branch0__insn_type 7'0000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            switch { \fu_enable [2] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+              case 1'1
+                assign \fus_oper_i_alu_branch0__insn_type \insn_type
+            end
+        end
+    end
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 8 \fast_src1__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \fast_src1__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 8 \fast_src2__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \fast_src2__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 8 \fast_wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \fast_data_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 8 \fast_wen$141
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \fast_data_i$142
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \fast_data_i$143
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 8 \fast_wen$144
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \fast_data_i$145
-  cell \fast \fast
-    connect \cia__ren \cia__ren
-    connect \cia__data_o \cia__data_o
-    connect \msr__ren \msr__ren
-    connect \msr__data_o \msr__data_o
-    connect \fast_nia_wen \fast_nia_wen
-    connect \wen \wen
-    connect \data_i \data_i
-    connect \rst \rst
-    connect \clk \clk
-    connect \src1__ren \fast_src1__ren
-    connect \src1__data_o \fast_src1__data_o
-    connect \src2__ren \fast_src2__ren
-    connect \src2__data_o \fast_src2__data_o
-    connect \wen$1 \fast_wen
-    connect \data_i$2 \fast_data_i
-    connect \wen$3 \fast_wen$141
-    connect \data_i$4 \fast_data_i$142
-    connect \data_i$5 \fast_data_i$143
-    connect \wen$6 \fast_wen$144
-    connect \data_i$7 \fast_data_i$145
+  process $group_43
+    assign \fus_oper_i_alu_branch0__fn_unit 11'00000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            switch { \fu_enable [2] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+              case 1'1
+                assign \fus_oper_i_alu_branch0__fn_unit \pdecode2_fn_unit
+            end
+        end
+    end
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \spr_src__ren
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \spr_src__data_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 1 \spr_dest__wen
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
-  wire width 64 \spr_dest__data_i
-  cell \spr \spr
-    connect \rst \rst
-    connect \clk \clk
-    connect \src__ren \spr_src__ren
-    connect \src__data_o \spr_src__data_o
-    connect \dest__wen \spr_dest__wen
-    connect \dest__data_i \spr_dest__data_i
+  process $group_44
+    assign \fus_oper_i_alu_branch0__insn 32'00000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            switch { \fu_enable [2] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+              case 1'1
+                assign \fus_oper_i_alu_branch0__insn \pdecode2_insn
+            end
+        end
+    end
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
-  wire width 1 \rdpick_INT_ra_en_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
-  wire width 8 \rdpick_INT_ra_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
-  wire width 8 \rdpick_INT_ra_o
-  cell \rdpick_INT_ra \rdpick_INT_ra
-    connect \en_o \rdpick_INT_ra_en_o
-    connect \i \rdpick_INT_ra_i
-    connect \o \rdpick_INT_ra_o
+  process $group_45
+    assign \fus_oper_i_alu_branch0__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \fus_oper_i_alu_branch0__imm_data__imm_ok 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            switch { \fu_enable [2] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+              case 1'1
+                assign { \fus_oper_i_alu_branch0__imm_data__imm_ok \fus_oper_i_alu_branch0__imm_data__imm } { \pdecode2_imm_ok \pdecode2_imm }
+            end
+        end
+    end
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
-  wire width 1 \rdpick_INT_rb_en_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
-  wire width 7 \rdpick_INT_rb_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
-  wire width 7 \rdpick_INT_rb_o
-  cell \rdpick_INT_rb \rdpick_INT_rb
-    connect \en_o \rdpick_INT_rb_en_o
-    connect \i \rdpick_INT_rb_i
-    connect \o \rdpick_INT_rb_o
+  process $group_47
+    assign \fus_oper_i_alu_branch0__lk 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            switch { \fu_enable [2] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+              case 1'1
+                assign \fus_oper_i_alu_branch0__lk \pdecode2_lk
+            end
+        end
+    end
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
-  wire width 1 \rdpick_INT_rc_en_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
-  wire width 2 \rdpick_INT_rc_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
-  wire width 2 \rdpick_INT_rc_o
-  cell \rdpick_INT_rc \rdpick_INT_rc
-    connect \en_o \rdpick_INT_rc_en_o
-    connect \i \rdpick_INT_rc_i
-    connect \o \rdpick_INT_rc_o
+  process $group_48
+    assign \fus_oper_i_alu_branch0__is_32bit 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            switch { \fu_enable [2] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+              case 1'1
+                assign \fus_oper_i_alu_branch0__is_32bit \pdecode2_is_32bit
+            end
+        end
+    end
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
-  wire width 1 \rdpick_XER_xer_so_en_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
-  wire width 3 \rdpick_XER_xer_so_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
-  wire width 3 \rdpick_XER_xer_so_o
-  cell \rdpick_XER_xer_so \rdpick_XER_xer_so
-    connect \en_o \rdpick_XER_xer_so_en_o
-    connect \i \rdpick_XER_xer_so_i
-    connect \o \rdpick_XER_xer_so_o
+  process $group_49
+    assign \fus_cu_issue_i$6 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            switch { \fu_enable [2] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+              case 1'1
+                assign \fus_cu_issue_i$6 \issue_i
+            end
+        end
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:170"
+  wire width 3 $223
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:170"
+  cell $not $224
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 3
+    parameter \Y_WIDTH 3
+    connect \A { \pdecode2_cr_in1_ok \pdecode2_fast2_ok \pdecode2_fast1_ok }
+    connect \Y $223
+  end
+  process $group_50
+    assign \fus_cu_rdmaskn_i$8 3'000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            switch { \fu_enable [2] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+              case 1'1
+                assign \fus_cu_rdmaskn_i$8 $223
+            end
+        end
+    end
+    sync init
+  end
+  process $group_51
+    assign \fus_oper_i_alu_trap0__insn_type 7'0000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            switch { \fu_enable [3] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+              case 1'1
+                assign \fus_oper_i_alu_trap0__insn_type \insn_type
+            end
+        end
+    end
+    sync init
+  end
+  process $group_52
+    assign \fus_oper_i_alu_trap0__fn_unit 11'00000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            switch { \fu_enable [3] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+              case 1'1
+                assign \fus_oper_i_alu_trap0__fn_unit \pdecode2_fn_unit
+            end
+        end
+    end
+    sync init
+  end
+  process $group_53
+    assign \fus_oper_i_alu_trap0__insn 32'00000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            switch { \fu_enable [3] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+              case 1'1
+                assign \fus_oper_i_alu_trap0__insn \pdecode2_insn
+            end
+        end
+    end
+    sync init
+  end
+  process $group_54
+    assign \fus_oper_i_alu_trap0__msr 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            switch { \fu_enable [3] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+              case 1'1
+                assign \fus_oper_i_alu_trap0__msr \pdecode2_msr
+            end
+        end
+    end
+    sync init
+  end
+  process $group_55
+    assign \fus_oper_i_alu_trap0__cia 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            switch { \fu_enable [3] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+              case 1'1
+                assign \fus_oper_i_alu_trap0__cia \pdecode2_cia
+            end
+        end
+    end
+    sync init
+  end
+  process $group_56
+    assign \fus_oper_i_alu_trap0__is_32bit 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            switch { \fu_enable [3] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+              case 1'1
+                assign \fus_oper_i_alu_trap0__is_32bit \pdecode2_is_32bit
+            end
+        end
+    end
+    sync init
+  end
+  process $group_57
+    assign \fus_oper_i_alu_trap0__traptype 5'00000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            switch { \fu_enable [3] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+              case 1'1
+                assign \fus_oper_i_alu_trap0__traptype \pdecode2_traptype
+            end
+        end
+    end
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
-  wire width 1 \rdpick_XER_xer_ca_en_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
-  wire width 3 \rdpick_XER_xer_ca_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
-  wire width 3 \rdpick_XER_xer_ca_o
-  cell \rdpick_XER_xer_ca \rdpick_XER_xer_ca
-    connect \en_o \rdpick_XER_xer_ca_en_o
-    connect \i \rdpick_XER_xer_ca_i
-    connect \o \rdpick_XER_xer_ca_o
+  process $group_58
+    assign \fus_oper_i_alu_trap0__trapaddr 13'0000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            switch { \fu_enable [3] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+              case 1'1
+                assign \fus_oper_i_alu_trap0__trapaddr \pdecode2_trapaddr
+            end
+        end
+    end
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
-  wire width 1 \rdpick_XER_xer_ov_en_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
-  wire width 1 \rdpick_XER_xer_ov_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
-  wire width 1 \rdpick_XER_xer_ov_o
-  cell \rdpick_XER_xer_ov \rdpick_XER_xer_ov
-    connect \en_o \rdpick_XER_xer_ov_en_o
-    connect \i \rdpick_XER_xer_ov_i
-    connect \o \rdpick_XER_xer_ov_o
+  process $group_59
+    assign \fus_cu_issue_i$9 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            switch { \fu_enable [3] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+              case 1'1
+                assign \fus_cu_issue_i$9 \issue_i
+            end
+        end
+    end
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
-  wire width 1 \rdpick_CR_full_cr_en_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
-  wire width 1 \rdpick_CR_full_cr_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
-  wire width 1 \rdpick_CR_full_cr_o
-  cell \rdpick_CR_full_cr \rdpick_CR_full_cr
-    connect \en_o \rdpick_CR_full_cr_en_o
-    connect \i \rdpick_CR_full_cr_i
-    connect \o \rdpick_CR_full_cr_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:170"
+  wire width 4 $225
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:170"
+  cell $not $226
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 4
+    parameter \Y_WIDTH 4
+    connect \A { \pdecode2_fast2_ok \pdecode2_fast1_ok \pdecode2_reg2_ok \pdecode2_reg1_ok }
+    connect \Y $225
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
-  wire width 1 \rdpick_CR_cr_a_en_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
-  wire width 2 \rdpick_CR_cr_a_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
-  wire width 2 \rdpick_CR_cr_a_o
-  cell \rdpick_CR_cr_a \rdpick_CR_cr_a
-    connect \en_o \rdpick_CR_cr_a_en_o
-    connect \i \rdpick_CR_cr_a_i
-    connect \o \rdpick_CR_cr_a_o
+  process $group_60
+    assign \fus_cu_rdmaskn_i$11 4'0000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            switch { \fu_enable [3] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+              case 1'1
+                assign \fus_cu_rdmaskn_i$11 $225
+            end
+        end
+    end
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
-  wire width 1 \rdpick_CR_cr_b_en_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
-  wire width 1 \rdpick_CR_cr_b_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
-  wire width 1 \rdpick_CR_cr_b_o
-  cell \rdpick_CR_cr_b \rdpick_CR_cr_b
-    connect \en_o \rdpick_CR_cr_b_en_o
-    connect \i \rdpick_CR_cr_b_i
-    connect \o \rdpick_CR_cr_b_o
+  process $group_61
+    assign \fus_oper_i_alu_logical0__insn_type 7'0000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            switch { \fu_enable [4] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+              case 1'1
+                assign \fus_oper_i_alu_logical0__insn_type \insn_type
+            end
+        end
+    end
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
-  wire width 1 \rdpick_CR_cr_c_en_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
-  wire width 1 \rdpick_CR_cr_c_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
-  wire width 1 \rdpick_CR_cr_c_o
-  cell \rdpick_CR_cr_c \rdpick_CR_cr_c
-    connect \en_o \rdpick_CR_cr_c_en_o
-    connect \i \rdpick_CR_cr_c_i
-    connect \o \rdpick_CR_cr_c_o
+  process $group_62
+    assign \fus_oper_i_alu_logical0__fn_unit 11'00000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            switch { \fu_enable [4] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+              case 1'1
+                assign \fus_oper_i_alu_logical0__fn_unit \pdecode2_fn_unit
+            end
+        end
+    end
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
-  wire width 1 \rdpick_FAST_fast1_en_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
-  wire width 3 \rdpick_FAST_fast1_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
-  wire width 3 \rdpick_FAST_fast1_o
-  cell \rdpick_FAST_fast1 \rdpick_FAST_fast1
-    connect \en_o \rdpick_FAST_fast1_en_o
-    connect \i \rdpick_FAST_fast1_i
-    connect \o \rdpick_FAST_fast1_o
+  process $group_63
+    assign \fus_oper_i_alu_logical0__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \fus_oper_i_alu_logical0__imm_data__imm_ok 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            switch { \fu_enable [4] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+              case 1'1
+                assign { \fus_oper_i_alu_logical0__imm_data__imm_ok \fus_oper_i_alu_logical0__imm_data__imm } { \pdecode2_imm_ok \pdecode2_imm }
+            end
+        end
+    end
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
-  wire width 1 \rdpick_FAST_fast2_en_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
-  wire width 2 \rdpick_FAST_fast2_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
-  wire width 2 \rdpick_FAST_fast2_o
-  cell \rdpick_FAST_fast2 \rdpick_FAST_fast2
-    connect \en_o \rdpick_FAST_fast2_en_o
-    connect \i \rdpick_FAST_fast2_i
-    connect \o \rdpick_FAST_fast2_o
+  process $group_65
+    assign \fus_oper_i_alu_logical0__rc__rc 1'0
+    assign \fus_oper_i_alu_logical0__rc__rc_ok 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            switch { \fu_enable [4] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+              case 1'1
+                assign { \fus_oper_i_alu_logical0__rc__rc_ok \fus_oper_i_alu_logical0__rc__rc } { \pdecode2_rc_ok \pdecode2_rc }
+            end
+        end
+    end
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
-  wire width 1 \rdpick_SPR_spr1_en_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
-  wire width 1 \rdpick_SPR_spr1_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
-  wire width 1 \rdpick_SPR_spr1_o
-  cell \rdpick_SPR_spr1 \rdpick_SPR_spr1
-    connect \en_o \rdpick_SPR_spr1_en_o
-    connect \i \rdpick_SPR_spr1_i
-    connect \o \rdpick_SPR_spr1_o
+  process $group_67
+    assign \fus_oper_i_alu_logical0__oe__oe 1'0
+    assign \fus_oper_i_alu_logical0__oe__oe_ok 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            switch { \fu_enable [4] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+              case 1'1
+                assign { \fus_oper_i_alu_logical0__oe__oe_ok \fus_oper_i_alu_logical0__oe__oe } { \pdecode2_oe_ok \pdecode2_oe }
+            end
+        end
+    end
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
-  wire width 1 \wrpick_INT_o_en_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
-  wire width 8 \wrpick_INT_o_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
-  wire width 8 \wrpick_INT_o_o
-  cell \wrpick_INT_o \wrpick_INT_o
-    connect \en_o \wrpick_INT_o_en_o
-    connect \i \wrpick_INT_o_i
-    connect \o \wrpick_INT_o_o
+  process $group_69
+    assign \fus_oper_i_alu_logical0__invert_a 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            switch { \fu_enable [4] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+              case 1'1
+                assign \fus_oper_i_alu_logical0__invert_a \pdecode2_invert_a
+            end
+        end
+    end
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
-  wire width 1 \wrpick_INT_o1_en_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
-  wire width 1 \wrpick_INT_o1_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
-  wire width 1 \wrpick_INT_o1_o
-  cell \wrpick_INT_o1 \wrpick_INT_o1
-    connect \en_o \wrpick_INT_o1_en_o
-    connect \i \wrpick_INT_o1_i
-    connect \o \wrpick_INT_o1_o
+  process $group_70
+    assign \fus_oper_i_alu_logical0__zero_a 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            switch { \fu_enable [4] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+              case 1'1
+                assign \fus_oper_i_alu_logical0__zero_a \pdecode2_zero_a
+            end
+        end
+    end
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
-  wire width 1 \wrpick_CR_full_cr_en_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
-  wire width 1 \wrpick_CR_full_cr_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
-  wire width 1 \wrpick_CR_full_cr_o
-  cell \wrpick_CR_full_cr \wrpick_CR_full_cr
-    connect \en_o \wrpick_CR_full_cr_en_o
-    connect \i \wrpick_CR_full_cr_i
-    connect \o \wrpick_CR_full_cr_o
+  process $group_71
+    assign \fus_oper_i_alu_logical0__input_carry 2'00
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            switch { \fu_enable [4] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+              case 1'1
+                assign \fus_oper_i_alu_logical0__input_carry \pdecode2_input_carry
+            end
+        end
+    end
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
-  wire width 1 \wrpick_CR_cr_a_en_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
-  wire width 5 \wrpick_CR_cr_a_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
-  wire width 5 \wrpick_CR_cr_a_o
-  cell \wrpick_CR_cr_a \wrpick_CR_cr_a
-    connect \en_o \wrpick_CR_cr_a_en_o
-    connect \i \wrpick_CR_cr_a_i
-    connect \o \wrpick_CR_cr_a_o
+  process $group_72
+    assign \fus_oper_i_alu_logical0__invert_out 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            switch { \fu_enable [4] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+              case 1'1
+                assign \fus_oper_i_alu_logical0__invert_out \pdecode2_invert_out
+            end
+        end
+    end
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
-  wire width 1 \wrpick_XER_xer_ca_en_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
-  wire width 4 \wrpick_XER_xer_ca_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
-  wire width 4 \wrpick_XER_xer_ca_o
-  cell \wrpick_XER_xer_ca \wrpick_XER_xer_ca
-    connect \en_o \wrpick_XER_xer_ca_en_o
-    connect \i \wrpick_XER_xer_ca_i
-    connect \o \wrpick_XER_xer_ca_o
+  process $group_73
+    assign \fus_oper_i_alu_logical0__write_cr0 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            switch { \fu_enable [4] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+              case 1'1
+                assign \fus_oper_i_alu_logical0__write_cr0 \pdecode2_write_cr0
+            end
+        end
+    end
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
-  wire width 1 \wrpick_XER_xer_ov_en_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
-  wire width 3 \wrpick_XER_xer_ov_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
-  wire width 3 \wrpick_XER_xer_ov_o
-  cell \wrpick_XER_xer_ov \wrpick_XER_xer_ov
-    connect \en_o \wrpick_XER_xer_ov_en_o
-    connect \i \wrpick_XER_xer_ov_i
-    connect \o \wrpick_XER_xer_ov_o
+  process $group_74
+    assign \fus_oper_i_alu_logical0__output_carry 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            switch { \fu_enable [4] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+              case 1'1
+                assign \fus_oper_i_alu_logical0__output_carry \pdecode2_output_carry
+            end
+        end
+    end
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
-  wire width 1 \wrpick_XER_xer_so_en_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
-  wire width 3 \wrpick_XER_xer_so_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
-  wire width 3 \wrpick_XER_xer_so_o
-  cell \wrpick_XER_xer_so \wrpick_XER_xer_so
-    connect \en_o \wrpick_XER_xer_so_en_o
-    connect \i \wrpick_XER_xer_so_i
-    connect \o \wrpick_XER_xer_so_o
+  process $group_75
+    assign \fus_oper_i_alu_logical0__is_32bit 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            switch { \fu_enable [4] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+              case 1'1
+                assign \fus_oper_i_alu_logical0__is_32bit \pdecode2_is_32bit
+            end
+        end
+    end
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
-  wire width 1 \wrpick_FAST_fast1_en_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
-  wire width 3 \wrpick_FAST_fast1_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
-  wire width 3 \wrpick_FAST_fast1_o
-  cell \wrpick_FAST_fast1 \wrpick_FAST_fast1
-    connect \en_o \wrpick_FAST_fast1_en_o
-    connect \i \wrpick_FAST_fast1_i
-    connect \o \wrpick_FAST_fast1_o
+  process $group_76
+    assign \fus_oper_i_alu_logical0__is_signed 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            switch { \fu_enable [4] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+              case 1'1
+                assign \fus_oper_i_alu_logical0__is_signed \pdecode2_is_signed
+            end
+        end
+    end
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
-  wire width 1 \wrpick_FAST_fast2_en_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
-  wire width 2 \wrpick_FAST_fast2_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
-  wire width 2 \wrpick_FAST_fast2_o
-  cell \wrpick_FAST_fast2 \wrpick_FAST_fast2
-    connect \en_o \wrpick_FAST_fast2_en_o
-    connect \i \wrpick_FAST_fast2_i
-    connect \o \wrpick_FAST_fast2_o
+  process $group_77
+    assign \fus_oper_i_alu_logical0__data_len 4'0000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            switch { \fu_enable [4] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+              case 1'1
+                assign \fus_oper_i_alu_logical0__data_len \pdecode2_data_len
+            end
+        end
+    end
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
-  wire width 1 \wrpick_FAST_nia_en_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
-  wire width 2 \wrpick_FAST_nia_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
-  wire width 2 \wrpick_FAST_nia_o
-  cell \wrpick_FAST_nia \wrpick_FAST_nia
-    connect \en_o \wrpick_FAST_nia_en_o
-    connect \i \wrpick_FAST_nia_i
-    connect \o \wrpick_FAST_nia_o
+  process $group_78
+    assign \fus_oper_i_alu_logical0__insn 32'00000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            switch { \fu_enable [4] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+              case 1'1
+                assign \fus_oper_i_alu_logical0__insn \pdecode2_insn
+            end
+        end
+    end
+    sync init
+  end
+  process $group_79
+    assign \fus_cu_issue_i$12 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            switch { \fu_enable [4] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+              case 1'1
+                assign \fus_cu_issue_i$12 \issue_i
+            end
+        end
+    end
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
-  wire width 1 \wrpick_FAST_msr_en_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
-  wire width 1 \wrpick_FAST_msr_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
-  wire width 1 \wrpick_FAST_msr_o
-  cell \wrpick_FAST_msr \wrpick_FAST_msr
-    connect \en_o \wrpick_FAST_msr_en_o
-    connect \i \wrpick_FAST_msr_i
-    connect \o \wrpick_FAST_msr_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:170"
+  wire width 2 $227
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:170"
+  cell $not $228
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 2
+    parameter \Y_WIDTH 2
+    connect \A { \pdecode2_reg2_ok \pdecode2_reg1_ok }
+    connect \Y $227
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:35"
-  wire width 1 \wrpick_SPR_spr1_en_o
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:33"
-  wire width 1 \wrpick_SPR_spr1_i
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:34"
-  wire width 1 \wrpick_SPR_spr1_o
-  cell \wrpick_SPR_spr1 \wrpick_SPR_spr1
-    connect \en_o \wrpick_SPR_spr1_en_o
-    connect \i \wrpick_SPR_spr1_i
-    connect \o \wrpick_SPR_spr1_o
+  process $group_80
+    assign \fus_cu_rdmaskn_i$14 2'00
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            switch { \fu_enable [4] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+              case 1'1
+                assign \fus_cu_rdmaskn_i$14 $227
+            end
+        end
+    end
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:102"
-  wire width 1 \core_stopped
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:102"
-  wire width 1 \core_stopped$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:140"
-  wire width 1 \can_run
-  process $group_0
-    assign \core_stopped$next \core_stopped
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:105"
-    switch { \core_start_i }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:105"
+  process $group_81
+    assign \fus_oper_i_alu_spr0__insn_type 7'0000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
       case 1'1
-        assign \core_stopped$next 1'0
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            switch { \fu_enable [5] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+              case 1'1
+                assign \fus_oper_i_alu_spr0__insn_type \insn_type
+            end
+        end
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:107"
-    switch { \core_stop_i }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:107"
+    sync init
+  end
+  process $group_82
+    assign \fus_oper_i_alu_spr0__fn_unit 11'00000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
       case 1'1
-        assign \core_stopped$next 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            switch { \fu_enable [5] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+              case 1'1
+                assign \fus_oper_i_alu_spr0__fn_unit \pdecode2_fn_unit
+            end
+        end
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-    switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+    sync init
+  end
+  process $group_83
+    assign \fus_oper_i_alu_spr0__insn 32'00000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-            assign \core_stopped$next 1'1
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
           attribute \nmigen.decoding ""
           case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            switch { \fu_enable [5] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+              case 1'1
+                assign \fus_oper_i_alu_spr0__insn \pdecode2_insn
+            end
         end
     end
-    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
+    sync init
+  end
+  process $group_84
+    assign \fus_oper_i_alu_spr0__is_32bit 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
       case 1'1
-        assign \core_stopped$next 1'0
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            switch { \fu_enable [5] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+              case 1'1
+                assign \fus_oper_i_alu_spr0__is_32bit \pdecode2_is_32bit
+            end
+        end
     end
     sync init
-      update \core_stopped 1'0
-    sync posedge \clk
-      update \core_stopped \core_stopped$next
   end
-  process $group_1
-    assign \core_terminated_o 1'0
-    assign \core_terminated_o \core_stopped
+  process $group_85
+    assign \fus_cu_issue_i$15 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            switch { \fu_enable [5] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+              case 1'1
+                assign \fus_cu_issue_i$15 \issue_i
+            end
+        end
+    end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:141"
-  wire width 1 $146
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:141"
-  cell $not $147
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:170"
+  wire width 6 $229
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79"
+  wire width 1 $230
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79"
+  cell $and $231
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \core_stopped
-    connect \Y $146
+    connect \A \pdecode2_oe
+    connect \B \pdecode2_oe_ok
+    connect \Y $230
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:141"
-  wire width 1 $148
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:141"
-  cell $and $149
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79"
+  wire width 1 $232
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79"
+  cell $or $233
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \valid
-    connect \B $146
-    connect \Y $148
-  end
-  process $group_2
-    assign \can_run 1'0
-    assign \can_run $148
-    sync init
+    connect \A $230
+    connect \B \pdecode2_xer_in
+    connect \Y $232
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-  wire width 1 \en_alu0
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-  wire width 1 $150
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-  wire width 11 $151
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-  cell $and $152
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81"
+  wire width 1 $234
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81"
+  cell $and $235
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 11
+    parameter \A_WIDTH 1
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 2
-    parameter \Y_WIDTH 11
-    connect \A \pdecode2_fn_unit
-    connect \B 2'10
-    connect \Y $151
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-  cell $reduce_bool $153
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 11
+    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $151
-    connect \Y $150
-  end
-  process $group_3
-    assign \en_alu0 1'0
-    assign \en_alu0 $150
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:135"
-  wire width 9 \fu_enable
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-  wire width 1 \en_cr0
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-  wire width 1 \en_branch0
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-  wire width 1 \en_trap0
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-  wire width 1 \en_logical0
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-  wire width 1 \en_spr0
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-  wire width 1 \en_mul0
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-  wire width 1 \en_shiftrot0
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
-  wire width 1 \en_ldst0
-  process $group_4
-    assign \fu_enable 9'000000000
-    assign \fu_enable [0] \en_alu0
-    assign \fu_enable [1] \en_cr0
-    assign \fu_enable [2] \en_branch0
-    assign \fu_enable [3] \en_trap0
-    assign \fu_enable [4] \en_logical0
-    assign \fu_enable [5] \en_spr0
-    assign \fu_enable [6] \en_mul0
-    assign \fu_enable [7] \en_shiftrot0
-    assign \fu_enable [8] \en_ldst0
-    sync init
+    connect \A \pdecode2_oe
+    connect \B \pdecode2_oe_ok
+    connect \Y $234
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-  wire width 1 $154
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-  wire width 11 $155
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-  cell $and $156
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81"
+  wire width 1 $236
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81"
+  cell $or $237
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 11
+    parameter \A_WIDTH 1
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 7
-    parameter \Y_WIDTH 11
-    connect \A \pdecode2_fn_unit
-    connect \B 7'1000000
-    connect \Y $155
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-  cell $reduce_bool $157
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 11
+    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $155
-    connect \Y $154
-  end
-  process $group_5
-    assign \en_cr0 1'0
-    assign \en_cr0 $154
-    sync init
+    connect \A $234
+    connect \B \pdecode2_xer_in
+    connect \Y $236
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-  wire width 1 $158
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-  wire width 11 $159
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-  cell $and $160
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83"
+  wire width 1 $238
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83"
+  cell $eq $239
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 11
+    parameter \A_WIDTH 2
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 6
-    parameter \Y_WIDTH 11
-    connect \A \pdecode2_fn_unit
-    connect \B 6'100000
-    connect \Y $159
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-  cell $reduce_bool $161
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 11
+    parameter \B_WIDTH 2
     parameter \Y_WIDTH 1
-    connect \A $159
-    connect \Y $158
-  end
-  process $group_6
-    assign \en_branch0 1'0
-    assign \en_branch0 $158
-    sync init
+    connect \A \pdecode2_input_carry
+    connect \B 2'10
+    connect \Y $238
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-  wire width 1 $162
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-  wire width 11 $163
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-  cell $and $164
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83"
+  wire width 1 $240
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83"
+  cell $or $241
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 11
+    parameter \A_WIDTH 1
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 8
-    parameter \Y_WIDTH 11
-    connect \A \pdecode2_fn_unit
-    connect \B 8'10000000
-    connect \Y $163
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-  cell $reduce_bool $165
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 11
+    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $163
-    connect \Y $162
-  end
-  process $group_7
-    assign \en_trap0 1'0
-    assign \en_trap0 $162
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-  wire width 1 $166
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-  wire width 11 $167
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-  cell $and $168
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 11
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 5
-    parameter \Y_WIDTH 11
-    connect \A \pdecode2_fn_unit
-    connect \B 5'10000
-    connect \Y $167
+    connect \A $238
+    connect \B \pdecode2_xer_in
+    connect \Y $240
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-  cell $reduce_bool $169
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:170"
+  cell $not $242
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 11
-    parameter \Y_WIDTH 1
-    connect \A $167
-    connect \Y $166
+    parameter \A_WIDTH 6
+    parameter \Y_WIDTH 6
+    connect \A { $240 $236 $232 \pdecode2_fast1_ok \pdecode2_spr1_ok \pdecode2_reg1_ok }
+    connect \Y $229
   end
-  process $group_8
-    assign \en_logical0 1'0
-    assign \en_logical0 $166
+  process $group_86
+    assign \fus_cu_rdmaskn_i$17 6'000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            switch { \fu_enable [5] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+              case 1'1
+                assign \fus_cu_rdmaskn_i$17 $229
+            end
+        end
+    end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-  wire width 1 $170
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-  wire width 11 $171
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-  cell $and $172
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 11
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 11
-    parameter \Y_WIDTH 11
-    connect \A \pdecode2_fn_unit
-    connect \B 11'10000000000
-    connect \Y $171
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-  cell $reduce_bool $173
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 11
-    parameter \Y_WIDTH 1
-    connect \A $171
-    connect \Y $170
-  end
-  process $group_9
-    assign \en_spr0 1'0
-    assign \en_spr0 $170
+  process $group_87
+    assign \fus_oper_i_alu_div0__insn_type 7'0000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            switch { \fu_enable [6] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+              case 1'1
+                assign \fus_oper_i_alu_div0__insn_type \insn_type
+            end
+        end
+    end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-  wire width 1 $174
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-  wire width 11 $175
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-  cell $and $176
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 11
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 9
-    parameter \Y_WIDTH 11
-    connect \A \pdecode2_fn_unit
-    connect \B 9'100000000
-    connect \Y $175
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-  cell $reduce_bool $177
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 11
-    parameter \Y_WIDTH 1
-    connect \A $175
-    connect \Y $174
-  end
-  process $group_10
-    assign \en_mul0 1'0
-    assign \en_mul0 $174
+  process $group_88
+    assign \fus_oper_i_alu_div0__fn_unit 11'00000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            switch { \fu_enable [6] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+              case 1'1
+                assign \fus_oper_i_alu_div0__fn_unit \pdecode2_fn_unit
+            end
+        end
+    end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-  wire width 1 $178
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-  wire width 11 $179
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-  cell $and $180
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 11
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 4
-    parameter \Y_WIDTH 11
-    connect \A \pdecode2_fn_unit
-    connect \B 4'1000
-    connect \Y $179
+  process $group_89
+    assign \fus_oper_i_alu_div0__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \fus_oper_i_alu_div0__imm_data__imm_ok 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            switch { \fu_enable [6] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+              case 1'1
+                assign { \fus_oper_i_alu_div0__imm_data__imm_ok \fus_oper_i_alu_div0__imm_data__imm } { \pdecode2_imm_ok \pdecode2_imm }
+            end
+        end
+    end
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-  cell $reduce_bool $181
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 11
-    parameter \Y_WIDTH 1
-    connect \A $179
-    connect \Y $178
+  process $group_91
+    assign \fus_oper_i_alu_div0__rc__rc 1'0
+    assign \fus_oper_i_alu_div0__rc__rc_ok 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            switch { \fu_enable [6] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+              case 1'1
+                assign { \fus_oper_i_alu_div0__rc__rc_ok \fus_oper_i_alu_div0__rc__rc } { \pdecode2_rc_ok \pdecode2_rc }
+            end
+        end
+    end
+    sync init
   end
-  process $group_11
-    assign \en_shiftrot0 1'0
-    assign \en_shiftrot0 $178
+  process $group_93
+    assign \fus_oper_i_alu_div0__oe__oe 1'0
+    assign \fus_oper_i_alu_div0__oe__oe_ok 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            switch { \fu_enable [6] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+              case 1'1
+                assign { \fus_oper_i_alu_div0__oe__oe_ok \fus_oper_i_alu_div0__oe__oe } { \pdecode2_oe_ok \pdecode2_oe }
+            end
+        end
+    end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-  wire width 1 $182
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-  wire width 11 $183
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-  cell $and $184
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 11
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 3
-    parameter \Y_WIDTH 11
-    connect \A \pdecode2_fn_unit
-    connect \B 3'100
-    connect \Y $183
+  process $group_95
+    assign \fus_oper_i_alu_div0__invert_a 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            switch { \fu_enable [6] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+              case 1'1
+                assign \fus_oper_i_alu_div0__invert_a \pdecode2_invert_a
+            end
+        end
+    end
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
-  cell $reduce_bool $185
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 11
-    parameter \Y_WIDTH 1
-    connect \A $183
-    connect \Y $182
+  process $group_96
+    assign \fus_oper_i_alu_div0__zero_a 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            switch { \fu_enable [6] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+              case 1'1
+                assign \fus_oper_i_alu_div0__zero_a \pdecode2_zero_a
+            end
+        end
+    end
+    sync init
   end
-  process $group_12
-    assign \en_ldst0 1'0
-    assign \en_ldst0 $182
+  process $group_97
+    assign \fus_oper_i_alu_div0__input_carry 2'00
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            switch { \fu_enable [6] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+              case 1'1
+                assign \fus_oper_i_alu_div0__input_carry \pdecode2_input_carry
+            end
+        end
+    end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
-  wire width 2 \counter
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:153"
-  wire width 2 \counter$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
-  wire width 1 $186
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
-  cell $ne $187
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 2
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \counter
-    connect \B 1'0
-    connect \Y $186
+  process $group_98
+    assign \fus_oper_i_alu_div0__invert_out 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            switch { \fu_enable [6] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+              case 1'1
+                assign \fus_oper_i_alu_div0__invert_out \pdecode2_invert_out
+            end
+        end
+    end
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:155"
-  wire width 3 $188
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:155"
-  wire width 3 $189
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:155"
-  cell $sub $190
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 2
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 3
-    connect \A \counter
-    connect \B 1'1
-    connect \Y $189
+  process $group_99
+    assign \fus_oper_i_alu_div0__write_cr0 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            switch { \fu_enable [6] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+              case 1'1
+                assign \fus_oper_i_alu_div0__write_cr0 \pdecode2_write_cr0
+            end
+        end
+    end
+    sync init
   end
-  connect $188 $189
-  process $group_13
-    assign \counter$next \counter
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
-    switch { $186 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+  process $group_100
+    assign \fus_oper_i_alu_div0__output_carry 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
       case 1'1
-        assign \counter$next $188 [1:0]
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            switch { \fu_enable [6] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+              case 1'1
+                assign \fus_oper_i_alu_div0__output_carry \pdecode2_output_carry
+            end
+        end
     end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-    switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+    sync init
+  end
+  process $group_101
+    assign \fus_oper_i_alu_div0__is_32bit 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-            assign \counter$next 2'10
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
           attribute \nmigen.decoding ""
           case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            switch { \fu_enable [6] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+              case 1'1
+                assign \fus_oper_i_alu_div0__is_32bit \pdecode2_is_32bit
+            end
         end
     end
-    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
-      case 1'1
-        assign \counter$next 2'00
-    end
     sync init
-      update \counter 2'00
-    sync posedge \clk
-      update \counter \counter$next
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
-  wire width 1 $191
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
-  cell $ne $192
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 2
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \counter
-    connect \B 1'0
-    connect \Y $191
   end
-  process $group_14
-    assign \corebusy_o 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
-    switch { $191 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
-      case 1'1
-        assign \corebusy_o 1'1
-    end
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-    switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+  process $group_102
+    assign \fus_oper_i_alu_div0__is_signed 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-            assign \corebusy_o 1'1
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-            switch { \fu_enable [0] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-              case 1'1
-                assign \corebusy_o \fus_cu_busy_o
-            end
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-            switch { \fu_enable [1] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-              case 1'1
-                assign \corebusy_o \fus_cu_busy_o$4
-            end
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-            switch { \fu_enable [2] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-              case 1'1
-                assign \corebusy_o \fus_cu_busy_o$7
-            end
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-            switch { \fu_enable [3] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-              case 1'1
-                assign \corebusy_o \fus_cu_busy_o$10
-            end
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-            switch { \fu_enable [4] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-              case 1'1
-                assign \corebusy_o \fus_cu_busy_o$13
-            end
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-            switch { \fu_enable [5] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-              case 1'1
-                assign \corebusy_o \fus_cu_busy_o$16
-            end
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
             switch { \fu_enable [6] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-              case 1'1
-                assign \corebusy_o \fus_cu_busy_o$19
-            end
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-            switch { \fu_enable [7] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
               case 1'1
-                assign \corebusy_o \fus_cu_busy_o$22
+                assign \fus_oper_i_alu_div0__is_signed \pdecode2_is_signed
             end
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-            switch { \fu_enable [8] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+        end
+    end
+    sync init
+  end
+  process $group_103
+    assign \fus_oper_i_alu_div0__data_len 4'0000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            switch { \fu_enable [6] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
               case 1'1
-                assign \corebusy_o \fus_cu_busy_o$25
+                assign \fus_oper_i_alu_div0__data_len \pdecode2_data_len
             end
         end
     end
     sync init
   end
-  process $group_15
-    assign \fus_oper_i_alu_alu0__insn_type 7'0000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-    switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+  process $group_104
+    assign \fus_oper_i_alu_div0__insn 32'00000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-            switch { \fu_enable [0] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            switch { \fu_enable [6] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
               case 1'1
-                assign \fus_oper_i_alu_alu0__insn_type \insn_type
+                assign \fus_oper_i_alu_div0__insn \pdecode2_insn
             end
         end
     end
     sync init
   end
-  process $group_16
-    assign \fus_oper_i_alu_alu0__fn_unit 11'00000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-    switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+  process $group_105
+    assign \fus_cu_issue_i$18 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-            switch { \fu_enable [0] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            switch { \fu_enable [6] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
               case 1'1
-                assign \fus_oper_i_alu_alu0__fn_unit \pdecode2_fn_unit
+                assign \fus_cu_issue_i$18 \issue_i
             end
         end
     end
     sync init
   end
-  process $group_17
-    assign \fus_oper_i_alu_alu0__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \fus_oper_i_alu_alu0__imm_data__imm_ok 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-    switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:170"
+  wire width 3 $243
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79"
+  wire width 1 $244
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79"
+  cell $and $245
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \pdecode2_oe
+    connect \B \pdecode2_oe_ok
+    connect \Y $244
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79"
+  wire width 1 $246
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79"
+  cell $or $247
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $244
+    connect \B \pdecode2_xer_in
+    connect \Y $246
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:170"
+  cell $not $248
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 3
+    parameter \Y_WIDTH 3
+    connect \A { $246 \pdecode2_reg2_ok \pdecode2_reg1_ok }
+    connect \Y $243
+  end
+  process $group_106
+    assign \fus_cu_rdmaskn_i$20 3'000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-            switch { \fu_enable [0] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            switch { \fu_enable [6] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
               case 1'1
-                assign { \fus_oper_i_alu_alu0__imm_data__imm_ok \fus_oper_i_alu_alu0__imm_data__imm } { \pdecode2_imm_ok \pdecode2_imm }
+                assign \fus_cu_rdmaskn_i$20 $243
             end
         end
     end
     sync init
   end
-  process $group_19
-    assign \fus_oper_i_alu_alu0__rc__rc 1'0
-    assign \fus_oper_i_alu_alu0__rc__rc_ok 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-    switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+  process $group_107
+    assign \fus_oper_i_alu_mul0__insn_type 7'0000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-            switch { \fu_enable [0] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            switch { \fu_enable [7] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
               case 1'1
-                assign { \fus_oper_i_alu_alu0__rc__rc_ok \fus_oper_i_alu_alu0__rc__rc } { \pdecode2_rc_ok \pdecode2_rc }
+                assign \fus_oper_i_alu_mul0__insn_type \insn_type
             end
         end
     end
     sync init
   end
-  process $group_21
-    assign \fus_oper_i_alu_alu0__oe__oe 1'0
-    assign \fus_oper_i_alu_alu0__oe__oe_ok 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-    switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+  process $group_108
+    assign \fus_oper_i_alu_mul0__fn_unit 11'00000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-            switch { \fu_enable [0] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            switch { \fu_enable [7] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
               case 1'1
-                assign { \fus_oper_i_alu_alu0__oe__oe_ok \fus_oper_i_alu_alu0__oe__oe } { \pdecode2_oe_ok \pdecode2_oe }
+                assign \fus_oper_i_alu_mul0__fn_unit \pdecode2_fn_unit
             end
         end
     end
     sync init
   end
-  process $group_23
-    assign \fus_oper_i_alu_alu0__invert_a 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-    switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+  process $group_109
+    assign \fus_oper_i_alu_mul0__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \fus_oper_i_alu_mul0__imm_data__imm_ok 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-            switch { \fu_enable [0] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            switch { \fu_enable [7] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
               case 1'1
-                assign \fus_oper_i_alu_alu0__invert_a \pdecode2_invert_a
+                assign { \fus_oper_i_alu_mul0__imm_data__imm_ok \fus_oper_i_alu_mul0__imm_data__imm } { \pdecode2_imm_ok \pdecode2_imm }
             end
         end
     end
     sync init
   end
-  process $group_24
-    assign \fus_oper_i_alu_alu0__zero_a 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-    switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+  process $group_111
+    assign \fus_oper_i_alu_mul0__rc__rc 1'0
+    assign \fus_oper_i_alu_mul0__rc__rc_ok 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-            switch { \fu_enable [0] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            switch { \fu_enable [7] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
               case 1'1
-                assign \fus_oper_i_alu_alu0__zero_a \pdecode2_zero_a
+                assign { \fus_oper_i_alu_mul0__rc__rc_ok \fus_oper_i_alu_mul0__rc__rc } { \pdecode2_rc_ok \pdecode2_rc }
             end
         end
     end
     sync init
   end
-  process $group_25
-    assign \fus_oper_i_alu_alu0__invert_out 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-    switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+  process $group_113
+    assign \fus_oper_i_alu_mul0__oe__oe 1'0
+    assign \fus_oper_i_alu_mul0__oe__oe_ok 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-            switch { \fu_enable [0] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            switch { \fu_enable [7] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
               case 1'1
-                assign \fus_oper_i_alu_alu0__invert_out \pdecode2_invert_out
+                assign { \fus_oper_i_alu_mul0__oe__oe_ok \fus_oper_i_alu_mul0__oe__oe } { \pdecode2_oe_ok \pdecode2_oe }
             end
         end
     end
     sync init
   end
-  process $group_26
-    assign \fus_oper_i_alu_alu0__write_cr0 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-    switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+  process $group_115
+    assign \fus_oper_i_alu_mul0__invert_a 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-            switch { \fu_enable [0] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            switch { \fu_enable [7] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
               case 1'1
-                assign \fus_oper_i_alu_alu0__write_cr0 \pdecode2_write_cr0
+                assign \fus_oper_i_alu_mul0__invert_a \pdecode2_invert_a
             end
         end
     end
     sync init
   end
-  process $group_27
-    assign \fus_oper_i_alu_alu0__input_carry 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-    switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+  process $group_116
+    assign \fus_oper_i_alu_mul0__zero_a 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-            switch { \fu_enable [0] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            switch { \fu_enable [7] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
               case 1'1
-                assign \fus_oper_i_alu_alu0__input_carry \pdecode2_input_carry
+                assign \fus_oper_i_alu_mul0__zero_a \pdecode2_zero_a
             end
         end
     end
     sync init
   end
-  process $group_28
-    assign \fus_oper_i_alu_alu0__output_carry 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-    switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+  process $group_117
+    assign \fus_oper_i_alu_mul0__invert_out 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-            switch { \fu_enable [0] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            switch { \fu_enable [7] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
               case 1'1
-                assign \fus_oper_i_alu_alu0__output_carry \pdecode2_output_carry
+                assign \fus_oper_i_alu_mul0__invert_out \pdecode2_invert_out
             end
         end
     end
     sync init
   end
-  process $group_29
-    assign \fus_oper_i_alu_alu0__is_32bit 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-    switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+  process $group_118
+    assign \fus_oper_i_alu_mul0__write_cr0 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-            switch { \fu_enable [0] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            switch { \fu_enable [7] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
               case 1'1
-                assign \fus_oper_i_alu_alu0__is_32bit \pdecode2_is_32bit
+                assign \fus_oper_i_alu_mul0__write_cr0 \pdecode2_write_cr0
             end
         end
     end
     sync init
   end
-  process $group_30
-    assign \fus_oper_i_alu_alu0__is_signed 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-    switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+  process $group_119
+    assign \fus_oper_i_alu_mul0__is_32bit 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-            switch { \fu_enable [0] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            switch { \fu_enable [7] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
               case 1'1
-                assign \fus_oper_i_alu_alu0__is_signed \pdecode2_is_signed
+                assign \fus_oper_i_alu_mul0__is_32bit \pdecode2_is_32bit
             end
         end
     end
     sync init
   end
-  process $group_31
-    assign \fus_oper_i_alu_alu0__data_len 4'0000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-    switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+  process $group_120
+    assign \fus_oper_i_alu_mul0__is_signed 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-            switch { \fu_enable [0] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            switch { \fu_enable [7] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
               case 1'1
-                assign \fus_oper_i_alu_alu0__data_len \pdecode2_data_len
+                assign \fus_oper_i_alu_mul0__is_signed \pdecode2_is_signed
             end
         end
     end
     sync init
   end
-  process $group_32
-    assign \fus_oper_i_alu_alu0__insn 32'00000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-    switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+  process $group_121
+    assign \fus_oper_i_alu_mul0__insn 32'00000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-            switch { \fu_enable [0] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            switch { \fu_enable [7] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
               case 1'1
-                assign \fus_oper_i_alu_alu0__insn \pdecode2_insn
+                assign \fus_oper_i_alu_mul0__insn \pdecode2_insn
             end
         end
     end
     sync init
   end
-  process $group_33
-    assign \fus_cu_issue_i 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-    switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+  process $group_122
+    assign \fus_cu_issue_i$21 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-            switch { \fu_enable [0] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            switch { \fu_enable [7] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
               case 1'1
-                assign \fus_cu_issue_i \issue_i
+                assign \fus_cu_issue_i$21 \issue_i
             end
         end
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:180"
-  wire width 4 $193
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:170"
+  wire width 3 $249
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79"
-  wire width 1 $194
+  wire width 1 $250
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79"
-  cell $and $195
+  cell $and $251
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -150408,1454 +168874,1969 @@ module \core
     parameter \Y_WIDTH 1
     connect \A \pdecode2_oe
     connect \B \pdecode2_oe_ok
-    connect \Y $194
+    connect \Y $250
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79"
-  wire width 1 $196
+  wire width 1 $252
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79"
-  cell $or $197
+  cell $or $253
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $194
+    connect \A $250
     connect \B \pdecode2_xer_in
-    connect \Y $196
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83"
-  wire width 1 $198
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83"
-  cell $eq $199
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 2
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 2
-    parameter \Y_WIDTH 1
-    connect \A \pdecode2_input_carry
-    connect \B 2'10
-    connect \Y $198
+    connect \Y $252
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83"
-  wire width 1 $200
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83"
-  cell $or $201
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:170"
+  cell $not $254
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A $198
-    connect \B \pdecode2_xer_in
-    connect \Y $200
+    parameter \A_WIDTH 3
+    parameter \Y_WIDTH 3
+    connect \A { $252 \pdecode2_reg2_ok \pdecode2_reg1_ok }
+    connect \Y $249
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:180"
-  cell $not $202
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 4
-    parameter \Y_WIDTH 4
-    connect \A { $200 $196 \pdecode2_reg2_ok \pdecode2_reg1_ok }
-    connect \Y $193
+  process $group_123
+    assign \fus_cu_rdmaskn_i$23 3'000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            switch { \fu_enable [7] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+              case 1'1
+                assign \fus_cu_rdmaskn_i$23 $249
+            end
+        end
+    end
+    sync init
   end
-  process $group_34
-    assign \fus_cu_rdmaskn_i 4'0000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-    switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+  process $group_124
+    assign \fus_oper_i_alu_shift_rot0__insn_type 7'0000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-            switch { \fu_enable [0] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            switch { \fu_enable [8] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
               case 1'1
-                assign \fus_cu_rdmaskn_i $193
+                assign \fus_oper_i_alu_shift_rot0__insn_type \insn_type
             end
         end
     end
     sync init
   end
-  process $group_35
-    assign \fus_oper_i_alu_cr0__insn_type 7'0000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-    switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+  process $group_125
+    assign \fus_oper_i_alu_shift_rot0__fn_unit 11'00000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-            switch { \fu_enable [1] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            switch { \fu_enable [8] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
               case 1'1
-                assign \fus_oper_i_alu_cr0__insn_type \insn_type
+                assign \fus_oper_i_alu_shift_rot0__fn_unit \pdecode2_fn_unit
             end
         end
     end
     sync init
   end
-  process $group_36
-    assign \fus_oper_i_alu_cr0__fn_unit 11'00000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-    switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+  process $group_126
+    assign \fus_oper_i_alu_shift_rot0__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \fus_oper_i_alu_shift_rot0__imm_data__imm_ok 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-            switch { \fu_enable [1] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            switch { \fu_enable [8] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
               case 1'1
-                assign \fus_oper_i_alu_cr0__fn_unit \pdecode2_fn_unit
+                assign { \fus_oper_i_alu_shift_rot0__imm_data__imm_ok \fus_oper_i_alu_shift_rot0__imm_data__imm } { \pdecode2_imm_ok \pdecode2_imm }
             end
         end
     end
     sync init
   end
-  process $group_37
-    assign \fus_oper_i_alu_cr0__insn 32'00000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-    switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+  process $group_128
+    assign \fus_oper_i_alu_shift_rot0__rc__rc 1'0
+    assign \fus_oper_i_alu_shift_rot0__rc__rc_ok 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-            switch { \fu_enable [1] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            switch { \fu_enable [8] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
               case 1'1
-                assign \fus_oper_i_alu_cr0__insn \pdecode2_insn
+                assign { \fus_oper_i_alu_shift_rot0__rc__rc_ok \fus_oper_i_alu_shift_rot0__rc__rc } { \pdecode2_rc_ok \pdecode2_rc }
             end
         end
     end
     sync init
   end
-  process $group_38
-    assign \fus_oper_i_alu_cr0__read_cr_whole 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-    switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+  process $group_130
+    assign \fus_oper_i_alu_shift_rot0__oe__oe 1'0
+    assign \fus_oper_i_alu_shift_rot0__oe__oe_ok 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-            switch { \fu_enable [1] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            switch { \fu_enable [8] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
               case 1'1
-                assign \fus_oper_i_alu_cr0__read_cr_whole \pdecode2_read_cr_whole
+                assign { \fus_oper_i_alu_shift_rot0__oe__oe_ok \fus_oper_i_alu_shift_rot0__oe__oe } { \pdecode2_oe_ok \pdecode2_oe }
             end
         end
     end
     sync init
   end
-  process $group_39
-    assign \fus_oper_i_alu_cr0__write_cr_whole 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-    switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+  process $group_132
+    assign { } 0'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-            switch { \fu_enable [1] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            switch { \fu_enable [8] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
               case 1'1
-                assign \fus_oper_i_alu_cr0__write_cr_whole \pdecode2_write_cr_whole
+                assign { } {}
             end
         end
     end
     sync init
   end
-  process $group_40
-    assign \fus_cu_issue_i$3 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-    switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+  process $group_133
+    assign \fus_oper_i_alu_shift_rot0__input_carry 2'00
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-            switch { \fu_enable [1] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            switch { \fu_enable [8] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
               case 1'1
-                assign \fus_cu_issue_i$3 \issue_i
+                assign \fus_oper_i_alu_shift_rot0__input_carry \pdecode2_input_carry
             end
         end
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:180"
-  wire width 6 $203
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:180"
-  cell $not $204
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 6
-    parameter \Y_WIDTH 6
-    connect \A { \pdecode2_cr_in2_ok$1 \pdecode2_cr_in2_ok \pdecode2_cr_in1_ok \pdecode2_read_cr_whole \pdecode2_reg2_ok \pdecode2_reg1_ok }
-    connect \Y $203
+  process $group_134
+    assign \fus_oper_i_alu_shift_rot0__output_carry 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            switch { \fu_enable [8] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+              case 1'1
+                assign \fus_oper_i_alu_shift_rot0__output_carry \pdecode2_output_carry
+            end
+        end
+    end
+    sync init
   end
-  process $group_41
-    assign \fus_cu_rdmaskn_i$5 6'000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-    switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+  process $group_135
+    assign \fus_oper_i_alu_shift_rot0__input_cr 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-            switch { \fu_enable [1] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            switch { \fu_enable [8] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
               case 1'1
-                assign \fus_cu_rdmaskn_i$5 $203
+                assign \fus_oper_i_alu_shift_rot0__input_cr \pdecode2_input_cr
             end
         end
     end
     sync init
   end
-  process $group_42
-    assign \fus_oper_i_alu_branch0__cia 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-    switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+  process $group_136
+    assign \fus_oper_i_alu_shift_rot0__output_cr 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-            switch { \fu_enable [2] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            switch { \fu_enable [8] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
               case 1'1
-                assign \fus_oper_i_alu_branch0__cia \pdecode2_cia
+                assign \fus_oper_i_alu_shift_rot0__output_cr \pdecode2_output_cr
             end
         end
     end
     sync init
   end
-  process $group_43
-    assign \fus_oper_i_alu_branch0__insn_type 7'0000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-    switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+  process $group_137
+    assign \fus_oper_i_alu_shift_rot0__is_32bit 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-            switch { \fu_enable [2] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            switch { \fu_enable [8] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
               case 1'1
-                assign \fus_oper_i_alu_branch0__insn_type \insn_type
+                assign \fus_oper_i_alu_shift_rot0__is_32bit \pdecode2_is_32bit
             end
         end
     end
     sync init
   end
-  process $group_44
-    assign \fus_oper_i_alu_branch0__fn_unit 11'00000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-    switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+  process $group_138
+    assign \fus_oper_i_alu_shift_rot0__is_signed 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-            switch { \fu_enable [2] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            switch { \fu_enable [8] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
               case 1'1
-                assign \fus_oper_i_alu_branch0__fn_unit \pdecode2_fn_unit
+                assign \fus_oper_i_alu_shift_rot0__is_signed \pdecode2_is_signed
             end
         end
     end
     sync init
   end
-  process $group_45
-    assign \fus_oper_i_alu_branch0__insn 32'00000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-    switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+  process $group_139
+    assign \fus_oper_i_alu_shift_rot0__insn 32'00000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-            switch { \fu_enable [2] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            switch { \fu_enable [8] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
               case 1'1
-                assign \fus_oper_i_alu_branch0__insn \pdecode2_insn
+                assign \fus_oper_i_alu_shift_rot0__insn \pdecode2_insn
             end
         end
     end
     sync init
   end
-  process $group_46
-    assign \fus_oper_i_alu_branch0__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \fus_oper_i_alu_branch0__imm_data__imm_ok 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-    switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+  process $group_140
+    assign \fus_cu_issue_i$24 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-            switch { \fu_enable [2] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            switch { \fu_enable [8] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
               case 1'1
-                assign { \fus_oper_i_alu_branch0__imm_data__imm_ok \fus_oper_i_alu_branch0__imm_data__imm } { \pdecode2_imm_ok \pdecode2_imm }
+                assign \fus_cu_issue_i$24 \issue_i
             end
         end
     end
     sync init
   end
-  process $group_48
-    assign \fus_oper_i_alu_branch0__lk 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-    switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:170"
+  wire width 4 $255
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83"
+  wire width 1 $256
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83"
+  cell $eq $257
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 2
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 2
+    parameter \Y_WIDTH 1
+    connect \A \pdecode2_input_carry
+    connect \B 2'10
+    connect \Y $256
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83"
+  wire width 1 $258
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83"
+  cell $or $259
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $256
+    connect \B \pdecode2_xer_in
+    connect \Y $258
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:170"
+  cell $not $260
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 4
+    parameter \Y_WIDTH 4
+    connect \A { $258 \pdecode2_reg3_ok \pdecode2_reg2_ok \pdecode2_reg1_ok }
+    connect \Y $255
+  end
+  process $group_141
+    assign \fus_cu_rdmaskn_i$26 4'0000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-            switch { \fu_enable [2] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            switch { \fu_enable [8] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
               case 1'1
-                assign \fus_oper_i_alu_branch0__lk \pdecode2_lk
+                assign \fus_cu_rdmaskn_i$26 $255
             end
         end
     end
     sync init
   end
-  process $group_49
-    assign \fus_oper_i_alu_branch0__is_32bit 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-    switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+  process $group_142
+    assign \fus_oper_i_ldst_ldst0__insn_type 7'0000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-            switch { \fu_enable [2] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            switch { \fu_enable [9] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
               case 1'1
-                assign \fus_oper_i_alu_branch0__is_32bit \pdecode2_is_32bit
+                assign \fus_oper_i_ldst_ldst0__insn_type \insn_type
             end
         end
     end
     sync init
   end
-  process $group_50
-    assign \fus_cu_issue_i$6 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-    switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+  process $group_143
+    assign \fus_oper_i_ldst_ldst0__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \fus_oper_i_ldst_ldst0__imm_data__imm_ok 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-            switch { \fu_enable [2] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            switch { \fu_enable [9] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
               case 1'1
-                assign \fus_cu_issue_i$6 \issue_i
+                assign { \fus_oper_i_ldst_ldst0__imm_data__imm_ok \fus_oper_i_ldst_ldst0__imm_data__imm } { \pdecode2_imm_ok \pdecode2_imm }
             end
         end
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:180"
-  wire width 3 $205
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:180"
-  cell $not $206
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 3
-    parameter \Y_WIDTH 3
-    connect \A { \pdecode2_cr_in1_ok \pdecode2_fast2_ok \pdecode2_fast1_ok }
-    connect \Y $205
+  process $group_145
+    assign \fus_oper_i_ldst_ldst0__zero_a 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+      case 1'1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
+        switch \insn_type
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
+          attribute \nmigen.decoding "OP_ATTN/5"
+          case 7'0000101
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
+          attribute \nmigen.decoding "OP_NOP/1"
+          case 7'0000001
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+          attribute \nmigen.decoding ""
+          case
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            switch { \fu_enable [9] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+              case 1'1
+                assign \fus_oper_i_ldst_ldst0__zero_a \pdecode2_zero_a
+            end
+        end
+    end
+    sync init
   end
-  process $group_51
-    assign \fus_cu_rdmaskn_i$8 3'000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-    switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+  process $group_146
+    assign \fus_oper_i_ldst_ldst0__rc__rc 1'0
+    assign \fus_oper_i_ldst_ldst0__rc__rc_ok 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-            switch { \fu_enable [2] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            switch { \fu_enable [9] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
               case 1'1
-                assign \fus_cu_rdmaskn_i$8 $205
+                assign { \fus_oper_i_ldst_ldst0__rc__rc_ok \fus_oper_i_ldst_ldst0__rc__rc } { \pdecode2_rc_ok \pdecode2_rc }
             end
         end
     end
     sync init
   end
-  process $group_52
-    assign \fus_oper_i_alu_trap0__insn_type 7'0000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-    switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+  process $group_148
+    assign \fus_oper_i_ldst_ldst0__oe__oe 1'0
+    assign \fus_oper_i_ldst_ldst0__oe__oe_ok 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-            switch { \fu_enable [3] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            switch { \fu_enable [9] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
               case 1'1
-                assign \fus_oper_i_alu_trap0__insn_type \insn_type
+                assign { \fus_oper_i_ldst_ldst0__oe__oe_ok \fus_oper_i_ldst_ldst0__oe__oe } { \pdecode2_oe_ok \pdecode2_oe }
             end
         end
     end
     sync init
   end
-  process $group_53
-    assign \fus_oper_i_alu_trap0__fn_unit 11'00000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-    switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+  process $group_150
+    assign \fus_oper_i_ldst_ldst0__is_32bit 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-            switch { \fu_enable [3] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            switch { \fu_enable [9] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
               case 1'1
-                assign \fus_oper_i_alu_trap0__fn_unit \pdecode2_fn_unit
+                assign \fus_oper_i_ldst_ldst0__is_32bit \pdecode2_is_32bit
             end
         end
     end
     sync init
   end
-  process $group_54
-    assign \fus_oper_i_alu_trap0__insn 32'00000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-    switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+  process $group_151
+    assign \fus_oper_i_ldst_ldst0__is_signed 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-            switch { \fu_enable [3] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            switch { \fu_enable [9] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
               case 1'1
-                assign \fus_oper_i_alu_trap0__insn \pdecode2_insn
+                assign \fus_oper_i_ldst_ldst0__is_signed \pdecode2_is_signed
             end
         end
     end
     sync init
   end
-  process $group_55
-    assign \fus_oper_i_alu_trap0__msr 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-    switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+  process $group_152
+    assign \fus_oper_i_ldst_ldst0__data_len 4'0000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-            switch { \fu_enable [3] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            switch { \fu_enable [9] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
               case 1'1
-                assign \fus_oper_i_alu_trap0__msr \pdecode2_msr
+                assign \fus_oper_i_ldst_ldst0__data_len \pdecode2_data_len
             end
         end
     end
     sync init
   end
-  process $group_56
-    assign \fus_oper_i_alu_trap0__cia 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-    switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+  process $group_153
+    assign \fus_oper_i_ldst_ldst0__byte_reverse 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-            switch { \fu_enable [3] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            switch { \fu_enable [9] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
               case 1'1
-                assign \fus_oper_i_alu_trap0__cia \pdecode2_cia
+                assign \fus_oper_i_ldst_ldst0__byte_reverse \pdecode2_byte_reverse
             end
         end
     end
     sync init
   end
-  process $group_57
-    assign \fus_oper_i_alu_trap0__is_32bit 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-    switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+  process $group_154
+    assign \fus_oper_i_ldst_ldst0__sign_extend 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-            switch { \fu_enable [3] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            switch { \fu_enable [9] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
               case 1'1
-                assign \fus_oper_i_alu_trap0__is_32bit \pdecode2_is_32bit
+                assign \fus_oper_i_ldst_ldst0__sign_extend \pdecode2_sign_extend
             end
         end
     end
     sync init
   end
-  process $group_58
-    assign \fus_oper_i_alu_trap0__traptype 5'00000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-    switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+  process $group_155
+    assign \fus_oper_i_ldst_ldst0__ldst_mode 2'00
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-            switch { \fu_enable [3] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            switch { \fu_enable [9] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
               case 1'1
-                assign \fus_oper_i_alu_trap0__traptype \pdecode2_traptype
+                assign \fus_oper_i_ldst_ldst0__ldst_mode \pdecode2_ldst_mode
             end
         end
     end
     sync init
   end
-  process $group_59
-    assign \fus_oper_i_alu_trap0__trapaddr 13'0000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-    switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+  process $group_156
+    assign \fus_cu_issue_i$27 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-            switch { \fu_enable [3] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            switch { \fu_enable [9] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
               case 1'1
-                assign \fus_oper_i_alu_trap0__trapaddr \pdecode2_trapaddr
+                assign \fus_cu_issue_i$27 \issue_i
             end
         end
     end
     sync init
   end
-  process $group_60
-    assign \fus_cu_issue_i$9 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-    switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:170"
+  wire width 3 $261
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:170"
+  cell $not $262
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 3
+    parameter \Y_WIDTH 3
+    connect \A { \pdecode2_reg3_ok \pdecode2_reg2_ok \pdecode2_reg1_ok }
+    connect \Y $261
+  end
+  process $group_157
+    assign \fus_cu_rdmaskn_i$29 3'000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
+    switch { \valid }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:148"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:149"
         switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:151"
           attribute \nmigen.decoding "OP_ATTN/5"
           case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:154"
           attribute \nmigen.decoding "OP_NOP/1"
           case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
           attribute \nmigen.decoding ""
           case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-            switch { \fu_enable [3] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
+            switch { \fu_enable [9] }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
               case 1'1
-                assign \fus_cu_issue_i$9 \issue_i
+                assign \fus_cu_rdmaskn_i$29 $261
             end
         end
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:180"
-  wire width 4 $207
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:180"
-  cell $not $208
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202"
+  wire width 1 \rdflag_INT_ra
+  process $group_158
+    assign \rdflag_INT_ra 1'0
+    assign \rdflag_INT_ra \pdecode2_reg1_ok
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:51"
+  wire width 32 $263
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:51"
+  cell $sshl $264
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 4
-    parameter \Y_WIDTH 4
-    connect \A { \pdecode2_fast2_ok \pdecode2_fast1_ok \pdecode2_reg2_ok \pdecode2_reg1_ok }
-    connect \Y $207
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 5
+    parameter \Y_WIDTH 32
+    connect \A 1'1
+    connect \B \pdecode2_reg1
+    connect \Y $263
+  end
+  process $group_159
+    assign \int_src1__ren 32'00000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:216"
+    switch { \rdpick_INT_ra_en_o }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:216"
+      case 1'1
+        assign \int_src1__ren $263
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  wire width 1 $265
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  cell $and $266
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \fus_cu_rd__rel_o [0]
+    connect \B \fu_enable [0]
+    connect \Y $265
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  wire width 1 $267
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  cell $and $268
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $265
+    connect \B \rdflag_INT_ra
+    connect \Y $267
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  wire width 1 $269
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  cell $and $270
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \fus_cu_rd__rel_o$30 [0]
+    connect \B \fu_enable [1]
+    connect \Y $269
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  wire width 1 $271
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  cell $and $272
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $269
+    connect \B \rdflag_INT_ra
+    connect \Y $271
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  wire width 1 $273
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  cell $and $274
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
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+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \fus_cu_rd__rel_o$33 [0]
+    connect \B \fu_enable [3]
+    connect \Y $273
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  wire width 1 $275
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  cell $and $276
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $273
+    connect \B \rdflag_INT_ra
+    connect \Y $275
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  wire width 1 $277
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  cell $and $278
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
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+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \fus_cu_rd__rel_o$36 [0]
+    connect \B \fu_enable [4]
+    connect \Y $277
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  wire width 1 $279
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  cell $and $280
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $277
+    connect \B \rdflag_INT_ra
+    connect \Y $279
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  wire width 1 $281
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  cell $and $282
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
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+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \fus_cu_rd__rel_o$39 [0]
+    connect \B \fu_enable [5]
+    connect \Y $281
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  wire width 1 $283
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  cell $and $284
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $281
+    connect \B \rdflag_INT_ra
+    connect \Y $283
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  wire width 1 $285
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  cell $and $286
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \fus_cu_rd__rel_o$42 [0]
+    connect \B \fu_enable [6]
+    connect \Y $285
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  wire width 1 $287
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  cell $and $288
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $285
+    connect \B \rdflag_INT_ra
+    connect \Y $287
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  wire width 1 $289
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  cell $and $290
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \fus_cu_rd__rel_o$45 [0]
+    connect \B \fu_enable [7]
+    connect \Y $289
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  wire width 1 $291
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  cell $and $292
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $289
+    connect \B \rdflag_INT_ra
+    connect \Y $291
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  wire width 1 $293
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  cell $and $294
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \fus_cu_rd__rel_o$48 [0]
+    connect \B \fu_enable [8]
+    connect \Y $293
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  wire width 1 $295
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  cell $and $296
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $293
+    connect \B \rdflag_INT_ra
+    connect \Y $295
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  wire width 1 $297
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  cell $and $298
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \fus_cu_rd__rel_o$51 [0]
+    connect \B \fu_enable [9]
+    connect \Y $297
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  wire width 1 $299
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  cell $and $300
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $297
+    connect \B \rdflag_INT_ra
+    connect \Y $299
+  end
+  process $group_160
+    assign \rdpick_INT_ra_i 9'000000000
+    assign \rdpick_INT_ra_i [0] $267
+    assign \rdpick_INT_ra_i [1] $271
+    assign \rdpick_INT_ra_i [2] $275
+    assign \rdpick_INT_ra_i [3] $279
+    assign \rdpick_INT_ra_i [4] $283
+    assign \rdpick_INT_ra_i [5] $287
+    assign \rdpick_INT_ra_i [6] $291
+    assign \rdpick_INT_ra_i [7] $295
+    assign \rdpick_INT_ra_i [8] $299
+    sync init
+  end
+  process $group_161
+    assign \fus_cu_rd__go_i 4'0000
+    assign \fus_cu_rd__go_i [0] \rdpick_INT_ra_o [0]
+    assign \fus_cu_rd__go_i [1] \rdpick_INT_rb_o [0]
+    assign \fus_cu_rd__go_i [2] \rdpick_XER_xer_so_o [0]
+    assign \fus_cu_rd__go_i [3] \rdpick_XER_xer_ca_o [0]
+    sync init
+  end
+  process $group_162
+    assign \fus_src1_i 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \fus_src1_i \int_src1__data_o
+    sync init
+  end
+  process $group_163
+    assign \fus_cu_rd__go_i$31 6'000000
+    assign \fus_cu_rd__go_i$31 [0] \rdpick_INT_ra_o [1]
+    assign \fus_cu_rd__go_i$31 [1] \rdpick_INT_rb_o [1]
+    assign \fus_cu_rd__go_i$31 [2] \rdpick_CR_full_cr_o
+    assign \fus_cu_rd__go_i$31 [3] \rdpick_CR_cr_a_o [0]
+    assign \fus_cu_rd__go_i$31 [4] \rdpick_CR_cr_b_o
+    assign \fus_cu_rd__go_i$31 [5] \rdpick_CR_cr_c_o
+    sync init
+  end
+  process $group_164
+    assign \fus_src1_i$32 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \fus_src1_i$32 \int_src1__data_o
+    sync init
+  end
+  process $group_165
+    assign \fus_cu_rd__go_i$34 4'0000
+    assign \fus_cu_rd__go_i$34 [0] \rdpick_INT_ra_o [2]
+    assign \fus_cu_rd__go_i$34 [1] \rdpick_INT_rb_o [2]
+    assign \fus_cu_rd__go_i$34 [2] \rdpick_FAST_fast1_o [1]
+    assign \fus_cu_rd__go_i$34 [3] \rdpick_FAST_fast2_o [1]
+    sync init
+  end
+  process $group_166
+    assign \fus_src1_i$35 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \fus_src1_i$35 \int_src1__data_o
+    sync init
+  end
+  process $group_167
+    assign \fus_cu_rd__go_i$37 2'00
+    assign \fus_cu_rd__go_i$37 [0] \rdpick_INT_ra_o [3]
+    assign \fus_cu_rd__go_i$37 [1] \rdpick_INT_rb_o [3]
+    sync init
+  end
+  process $group_168
+    assign \fus_src1_i$38 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \fus_src1_i$38 \int_src1__data_o
+    sync init
+  end
+  process $group_169
+    assign \fus_cu_rd__go_i$40 6'000000
+    assign \fus_cu_rd__go_i$40 [0] \rdpick_INT_ra_o [4]
+    assign \fus_cu_rd__go_i$40 [3] \rdpick_XER_xer_so_o [1]
+    assign \fus_cu_rd__go_i$40 [5] \rdpick_XER_xer_ca_o [1]
+    assign \fus_cu_rd__go_i$40 [4] \rdpick_XER_xer_ov_o
+    assign \fus_cu_rd__go_i$40 [2] \rdpick_FAST_fast1_o [2]
+    assign \fus_cu_rd__go_i$40 [1] \rdpick_SPR_spr1_o
+    sync init
+  end
+  process $group_170
+    assign \fus_src1_i$41 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \fus_src1_i$41 \int_src1__data_o
+    sync init
+  end
+  process $group_171
+    assign \fus_cu_rd__go_i$43 3'000
+    assign \fus_cu_rd__go_i$43 [0] \rdpick_INT_ra_o [5]
+    assign \fus_cu_rd__go_i$43 [1] \rdpick_INT_rb_o [4]
+    assign \fus_cu_rd__go_i$43 [2] \rdpick_XER_xer_so_o [2]
+    sync init
+  end
+  process $group_172
+    assign \fus_src1_i$44 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \fus_src1_i$44 \int_src1__data_o
+    sync init
+  end
+  process $group_173
+    assign \fus_cu_rd__go_i$46 3'000
+    assign \fus_cu_rd__go_i$46 [0] \rdpick_INT_ra_o [6]
+    assign \fus_cu_rd__go_i$46 [1] \rdpick_INT_rb_o [5]
+    assign \fus_cu_rd__go_i$46 [2] \rdpick_XER_xer_so_o [3]
+    sync init
+  end
+  process $group_174
+    assign \fus_src1_i$47 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \fus_src1_i$47 \int_src1__data_o
+    sync init
+  end
+  process $group_175
+    assign \fus_cu_rd__go_i$49 4'0000
+    assign \fus_cu_rd__go_i$49 [0] \rdpick_INT_ra_o [7]
+    assign \fus_cu_rd__go_i$49 [1] \rdpick_INT_rb_o [6]
+    assign \fus_cu_rd__go_i$49 [2] \rdpick_INT_rc_o [0]
+    assign \fus_cu_rd__go_i$49 [3] \rdpick_XER_xer_ca_o [2]
+    sync init
+  end
+  process $group_176
+    assign \fus_src1_i$50 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \fus_src1_i$50 \int_src1__data_o
+    sync init
+  end
+  process $group_177
+    assign \fus_cu_rd__go_i$52 3'000
+    assign \fus_cu_rd__go_i$52 [0] \rdpick_INT_ra_o [8]
+    assign \fus_cu_rd__go_i$52 [1] \rdpick_INT_rb_o [7]
+    assign \fus_cu_rd__go_i$52 [2] \rdpick_INT_rc_o [1]
+    sync init
+  end
+  process $group_178
+    assign \fus_src1_i$53 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \fus_src1_i$53 \int_src1__data_o
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202"
+  wire width 1 \rdflag_INT_rb
+  process $group_179
+    assign \rdflag_INT_rb 1'0
+    assign \rdflag_INT_rb \pdecode2_reg2_ok
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:53"
+  wire width 32 $301
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:53"
+  cell $sshl $302
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 5
+    parameter \Y_WIDTH 32
+    connect \A 1'1
+    connect \B \pdecode2_reg2
+    connect \Y $301
+  end
+  process $group_180
+    assign \int_src2__ren 32'00000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:216"
+    switch { \rdpick_INT_rb_en_o }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:216"
+      case 1'1
+        assign \int_src2__ren $301
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  wire width 1 $303
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  cell $and $304
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \fus_cu_rd__rel_o [1]
+    connect \B \fu_enable [0]
+    connect \Y $303
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  wire width 1 $305
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  cell $and $306
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $303
+    connect \B \rdflag_INT_rb
+    connect \Y $305
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  wire width 1 $307
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  cell $and $308
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \fus_cu_rd__rel_o$30 [1]
+    connect \B \fu_enable [1]
+    connect \Y $307
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  wire width 1 $309
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  cell $and $310
+    parameter \A_SIGNED 0
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+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
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+    connect \A $307
+    connect \B \rdflag_INT_rb
+    connect \Y $309
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  wire width 1 $311
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  cell $and $312
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \fus_cu_rd__rel_o$33 [1]
+    connect \B \fu_enable [3]
+    connect \Y $311
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  wire width 1 $313
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  cell $and $314
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+    parameter \B_WIDTH 1
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+    connect \A $311
+    connect \B \rdflag_INT_rb
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+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  wire width 1 $315
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  cell $and $316
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+    parameter \Y_WIDTH 1
+    connect \A \fus_cu_rd__rel_o$36 [1]
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+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  wire width 1 $317
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  cell $and $318
+    parameter \A_SIGNED 0
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+    parameter \B_WIDTH 1
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+    connect \A $315
+    connect \B \rdflag_INT_rb
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+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  wire width 1 $319
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  cell $and $320
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+    connect \A \fus_cu_rd__rel_o$42 [1]
+    connect \B \fu_enable [6]
+    connect \Y $319
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  wire width 1 $321
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  cell $and $322
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+    parameter \B_WIDTH 1
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+    connect \A $319
+    connect \B \rdflag_INT_rb
+    connect \Y $321
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  wire width 1 $323
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  cell $and $324
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+    connect \A \fus_cu_rd__rel_o$45 [1]
+    connect \B \fu_enable [7]
+    connect \Y $323
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  wire width 1 $325
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  cell $and $326
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $323
+    connect \B \rdflag_INT_rb
+    connect \Y $325
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  wire width 1 $327
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  cell $and $328
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+    connect \A \fus_cu_rd__rel_o$48 [1]
+    connect \B \fu_enable [8]
+    connect \Y $327
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  wire width 1 $329
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  cell $and $330
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $327
+    connect \B \rdflag_INT_rb
+    connect \Y $329
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  wire width 1 $331
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  cell $and $332
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \fus_cu_rd__rel_o$51 [1]
+    connect \B \fu_enable [9]
+    connect \Y $331
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  wire width 1 $333
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  cell $and $334
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $331
+    connect \B \rdflag_INT_rb
+    connect \Y $333
   end
-  process $group_61
-    assign \fus_cu_rdmaskn_i$11 4'0000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-    switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-            switch { \fu_enable [3] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-              case 1'1
-                assign \fus_cu_rdmaskn_i$11 $207
-            end
-        end
-    end
+  process $group_181
+    assign \rdpick_INT_rb_i 8'00000000
+    assign \rdpick_INT_rb_i [0] $305
+    assign \rdpick_INT_rb_i [1] $309
+    assign \rdpick_INT_rb_i [2] $313
+    assign \rdpick_INT_rb_i [3] $317
+    assign \rdpick_INT_rb_i [4] $321
+    assign \rdpick_INT_rb_i [5] $325
+    assign \rdpick_INT_rb_i [6] $329
+    assign \rdpick_INT_rb_i [7] $333
     sync init
   end
-  process $group_62
-    assign \fus_oper_i_alu_logical0__insn_type 7'0000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-    switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-            switch { \fu_enable [4] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-              case 1'1
-                assign \fus_oper_i_alu_logical0__insn_type \insn_type
-            end
-        end
-    end
+  process $group_182
+    assign \fus_src2_i 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \fus_src2_i \int_src2__data_o
     sync init
   end
-  process $group_63
-    assign \fus_oper_i_alu_logical0__fn_unit 11'00000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-    switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-            switch { \fu_enable [4] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-              case 1'1
-                assign \fus_oper_i_alu_logical0__fn_unit \pdecode2_fn_unit
-            end
-        end
-    end
+  process $group_183
+    assign \fus_src2_i$54 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \fus_src2_i$54 \int_src2__data_o
     sync init
   end
-  process $group_64
-    assign \fus_oper_i_alu_logical0__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \fus_oper_i_alu_logical0__imm_data__imm_ok 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-    switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-            switch { \fu_enable [4] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-              case 1'1
-                assign { \fus_oper_i_alu_logical0__imm_data__imm_ok \fus_oper_i_alu_logical0__imm_data__imm } { \pdecode2_imm_ok \pdecode2_imm }
-            end
-        end
-    end
+  process $group_184
+    assign \fus_src2_i$55 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \fus_src2_i$55 \int_src2__data_o
     sync init
   end
-  process $group_66
-    assign \fus_oper_i_alu_logical0__rc__rc 1'0
-    assign \fus_oper_i_alu_logical0__rc__rc_ok 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-    switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-            switch { \fu_enable [4] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-              case 1'1
-                assign { \fus_oper_i_alu_logical0__rc__rc_ok \fus_oper_i_alu_logical0__rc__rc } { \pdecode2_rc_ok \pdecode2_rc }
-            end
-        end
-    end
+  process $group_185
+    assign \fus_src2_i$56 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \fus_src2_i$56 \int_src2__data_o
     sync init
   end
-  process $group_68
-    assign \fus_oper_i_alu_logical0__oe__oe 1'0
-    assign \fus_oper_i_alu_logical0__oe__oe_ok 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-    switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-            switch { \fu_enable [4] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-              case 1'1
-                assign { \fus_oper_i_alu_logical0__oe__oe_ok \fus_oper_i_alu_logical0__oe__oe } { \pdecode2_oe_ok \pdecode2_oe }
-            end
-        end
-    end
+  process $group_186
+    assign \fus_src2_i$57 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \fus_src2_i$57 \int_src2__data_o
     sync init
   end
-  process $group_70
-    assign \fus_oper_i_alu_logical0__invert_a 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-    switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-            switch { \fu_enable [4] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-              case 1'1
-                assign \fus_oper_i_alu_logical0__invert_a \pdecode2_invert_a
-            end
-        end
-    end
+  process $group_187
+    assign \fus_src2_i$58 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \fus_src2_i$58 \int_src2__data_o
     sync init
   end
-  process $group_71
-    assign \fus_oper_i_alu_logical0__zero_a 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-    switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-            switch { \fu_enable [4] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-              case 1'1
-                assign \fus_oper_i_alu_logical0__zero_a \pdecode2_zero_a
-            end
-        end
-    end
+  process $group_188
+    assign \fus_src2_i$59 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \fus_src2_i$59 \int_src2__data_o
     sync init
   end
-  process $group_72
-    assign \fus_oper_i_alu_logical0__input_carry 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-    switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-            switch { \fu_enable [4] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-              case 1'1
-                assign \fus_oper_i_alu_logical0__input_carry \pdecode2_input_carry
-            end
-        end
-    end
+  process $group_189
+    assign \fus_src2_i$60 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \fus_src2_i$60 \int_src2__data_o
     sync init
   end
-  process $group_73
-    assign \fus_oper_i_alu_logical0__invert_out 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-    switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-            switch { \fu_enable [4] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-              case 1'1
-                assign \fus_oper_i_alu_logical0__invert_out \pdecode2_invert_out
-            end
-        end
-    end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202"
+  wire width 1 \rdflag_INT_rc
+  process $group_190
+    assign \rdflag_INT_rc 1'0
+    assign \rdflag_INT_rc \pdecode2_reg3_ok
     sync init
   end
-  process $group_74
-    assign \fus_oper_i_alu_logical0__write_cr0 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-    switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-            switch { \fu_enable [4] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-              case 1'1
-                assign \fus_oper_i_alu_logical0__write_cr0 \pdecode2_write_cr0
-            end
-        end
-    end
-    sync init
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:55"
+  wire width 32 $335
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:55"
+  cell $sshl $336
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 5
+    parameter \Y_WIDTH 32
+    connect \A 1'1
+    connect \B \pdecode2_reg3
+    connect \Y $335
   end
-  process $group_75
-    assign \fus_oper_i_alu_logical0__output_carry 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-    switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+  process $group_191
+    assign \int_src3__ren 32'00000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:216"
+    switch { \rdpick_INT_rc_en_o }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:216"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-            switch { \fu_enable [4] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-              case 1'1
-                assign \fus_oper_i_alu_logical0__output_carry \pdecode2_output_carry
-            end
-        end
+        assign \int_src3__ren $335
     end
     sync init
   end
-  process $group_76
-    assign \fus_oper_i_alu_logical0__is_32bit 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-    switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-            switch { \fu_enable [4] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-              case 1'1
-                assign \fus_oper_i_alu_logical0__is_32bit \pdecode2_is_32bit
-            end
-        end
-    end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  wire width 1 $337
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  cell $and $338
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \fus_cu_rd__rel_o$48 [2]
+    connect \B \fu_enable [8]
+    connect \Y $337
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  wire width 1 $339
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  cell $and $340
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $337
+    connect \B \rdflag_INT_rc
+    connect \Y $339
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  wire width 1 $341
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  cell $and $342
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \fus_cu_rd__rel_o$51 [2]
+    connect \B \fu_enable [9]
+    connect \Y $341
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  wire width 1 $343
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  cell $and $344
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $341
+    connect \B \rdflag_INT_rc
+    connect \Y $343
+  end
+  process $group_192
+    assign \rdpick_INT_rc_i 2'00
+    assign \rdpick_INT_rc_i [0] $339
+    assign \rdpick_INT_rc_i [1] $343
     sync init
   end
-  process $group_77
-    assign \fus_oper_i_alu_logical0__is_signed 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-    switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-            switch { \fu_enable [4] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-              case 1'1
-                assign \fus_oper_i_alu_logical0__is_signed \pdecode2_is_signed
-            end
-        end
-    end
+  process $group_193
+    assign \fus_src3_i 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \fus_src3_i \int_src3__data_o
     sync init
   end
-  process $group_78
-    assign \fus_oper_i_alu_logical0__data_len 4'0000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-    switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-            switch { \fu_enable [4] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-              case 1'1
-                assign \fus_oper_i_alu_logical0__data_len \pdecode2_data_len
-            end
-        end
-    end
+  process $group_194
+    assign \fus_src3_i$61 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \fus_src3_i$61 \int_src3__data_o
     sync init
   end
-  process $group_79
-    assign \fus_oper_i_alu_logical0__insn 32'00000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-    switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-            switch { \fu_enable [4] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-              case 1'1
-                assign \fus_oper_i_alu_logical0__insn \pdecode2_insn
-            end
-        end
-    end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202"
+  wire width 1 \rdflag_XER_xer_so
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79"
+  wire width 1 $345
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79"
+  cell $and $346
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \pdecode2_oe
+    connect \B \pdecode2_oe_ok
+    connect \Y $345
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79"
+  wire width 1 $347
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79"
+  cell $or $348
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $345
+    connect \B \pdecode2_xer_in
+    connect \Y $347
+  end
+  process $group_195
+    assign \rdflag_XER_xer_so 1'0
+    assign \rdflag_XER_xer_so $347
     sync init
   end
-  process $group_80
-    assign \fus_cu_issue_i$12 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-    switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+  process $group_196
+    assign \xer_src1__ren 3'000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:216"
+    switch { \rdpick_XER_xer_so_en_o }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:216"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-            switch { \fu_enable [4] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-              case 1'1
-                assign \fus_cu_issue_i$12 \issue_i
-            end
-        end
+        assign \xer_src1__ren 3'001
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:180"
-  wire width 2 $209
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:180"
-  cell $not $210
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  wire width 1 $349
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  cell $and $350
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 2
-    parameter \Y_WIDTH 2
-    connect \A { \pdecode2_reg2_ok \pdecode2_reg1_ok }
-    connect \Y $209
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \fus_cu_rd__rel_o [2]
+    connect \B \fu_enable [0]
+    connect \Y $349
   end
-  process $group_81
-    assign \fus_cu_rdmaskn_i$14 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-    switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-            switch { \fu_enable [4] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-              case 1'1
-                assign \fus_cu_rdmaskn_i$14 $209
-            end
-        end
-    end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  wire width 1 $351
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  cell $and $352
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $349
+    connect \B \rdflag_XER_xer_so
+    connect \Y $351
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  wire width 1 $353
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  cell $and $354
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \fus_cu_rd__rel_o$39 [3]
+    connect \B \fu_enable [5]
+    connect \Y $353
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  wire width 1 $355
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  cell $and $356
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $353
+    connect \B \rdflag_XER_xer_so
+    connect \Y $355
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  wire width 1 $357
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  cell $and $358
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \fus_cu_rd__rel_o$42 [2]
+    connect \B \fu_enable [6]
+    connect \Y $357
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  wire width 1 $359
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  cell $and $360
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $357
+    connect \B \rdflag_XER_xer_so
+    connect \Y $359
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  wire width 1 $361
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  cell $and $362
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \fus_cu_rd__rel_o$45 [2]
+    connect \B \fu_enable [7]
+    connect \Y $361
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  wire width 1 $363
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  cell $and $364
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $361
+    connect \B \rdflag_XER_xer_so
+    connect \Y $363
+  end
+  process $group_197
+    assign \rdpick_XER_xer_so_i 4'0000
+    assign \rdpick_XER_xer_so_i [0] $351
+    assign \rdpick_XER_xer_so_i [1] $355
+    assign \rdpick_XER_xer_so_i [2] $359
+    assign \rdpick_XER_xer_so_i [3] $363
     sync init
   end
-  process $group_82
-    assign \fus_oper_i_alu_spr0__insn_type 7'0000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-    switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-            switch { \fu_enable [5] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-              case 1'1
-                assign \fus_oper_i_alu_spr0__insn_type \insn_type
-            end
-        end
-    end
+  process $group_198
+    assign \fus_src3_i$62 1'0
+    assign \fus_src3_i$62 \xer_src1__data_o [0]
     sync init
   end
-  process $group_83
-    assign \fus_oper_i_alu_spr0__fn_unit 11'00000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-    switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-            switch { \fu_enable [5] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-              case 1'1
-                assign \fus_oper_i_alu_spr0__fn_unit \pdecode2_fn_unit
-            end
-        end
-    end
+  process $group_199
+    assign \fus_src4_i 1'0
+    assign \fus_src4_i \xer_src1__data_o [0]
+    sync init
+  end
+  process $group_200
+    assign \fus_src3_i$63 1'0
+    assign \fus_src3_i$63 \xer_src1__data_o [0]
+    sync init
+  end
+  process $group_201
+    assign \fus_src3_i$64 1'0
+    assign \fus_src3_i$64 \xer_src1__data_o [0]
     sync init
   end
-  process $group_84
-    assign \fus_oper_i_alu_spr0__insn 32'00000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-    switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-            switch { \fu_enable [5] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-              case 1'1
-                assign \fus_oper_i_alu_spr0__insn \pdecode2_insn
-            end
-        end
-    end
-    sync init
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202"
+  wire width 1 \rdflag_XER_xer_ca
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83"
+  wire width 1 $365
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83"
+  cell $eq $366
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 2
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 2
+    parameter \Y_WIDTH 1
+    connect \A \pdecode2_input_carry
+    connect \B 2'10
+    connect \Y $365
   end
-  process $group_85
-    assign \fus_oper_i_alu_spr0__is_32bit 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-    switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-            switch { \fu_enable [5] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-              case 1'1
-                assign \fus_oper_i_alu_spr0__is_32bit \pdecode2_is_32bit
-            end
-        end
-    end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83"
+  wire width 1 $367
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83"
+  cell $or $368
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $365
+    connect \B \pdecode2_xer_in
+    connect \Y $367
+  end
+  process $group_202
+    assign \rdflag_XER_xer_ca 1'0
+    assign \rdflag_XER_xer_ca $367
     sync init
   end
-  process $group_86
-    assign \fus_cu_issue_i$15 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-    switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+  process $group_203
+    assign \xer_src2__ren 3'000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:216"
+    switch { \rdpick_XER_xer_ca_en_o }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:216"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-            switch { \fu_enable [5] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-              case 1'1
-                assign \fus_cu_issue_i$15 \issue_i
-            end
-        end
+        assign \xer_src2__ren 3'010
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:180"
-  wire width 6 $211
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79"
-  wire width 1 $212
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79"
-  cell $and $213
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  wire width 1 $369
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  cell $and $370
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \pdecode2_oe
-    connect \B \pdecode2_oe_ok
-    connect \Y $212
+    connect \A \fus_cu_rd__rel_o [3]
+    connect \B \fu_enable [0]
+    connect \Y $369
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79"
-  wire width 1 $214
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79"
-  cell $or $215
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  wire width 1 $371
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  cell $and $372
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $212
-    connect \B \pdecode2_xer_in
-    connect \Y $214
+    connect \A $369
+    connect \B \rdflag_XER_xer_ca
+    connect \Y $371
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  wire width 1 $373
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  cell $and $374
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \fus_cu_rd__rel_o$39 [5]
+    connect \B \fu_enable [5]
+    connect \Y $373
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  wire width 1 $375
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  cell $and $376
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $373
+    connect \B \rdflag_XER_xer_ca
+    connect \Y $375
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  wire width 1 $377
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  cell $and $378
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \fus_cu_rd__rel_o$48 [3]
+    connect \B \fu_enable [8]
+    connect \Y $377
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  wire width 1 $379
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  cell $and $380
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $377
+    connect \B \rdflag_XER_xer_ca
+    connect \Y $379
+  end
+  process $group_204
+    assign \rdpick_XER_xer_ca_i 3'000
+    assign \rdpick_XER_xer_ca_i [0] $371
+    assign \rdpick_XER_xer_ca_i [1] $375
+    assign \rdpick_XER_xer_ca_i [2] $379
+    sync init
+  end
+  process $group_205
+    assign \fus_src4_i$65 2'00
+    assign \fus_src4_i$65 \xer_src2__data_o
+    sync init
+  end
+  process $group_206
+    assign \fus_src6_i 2'00
+    assign \fus_src6_i \xer_src2__data_o
+    sync init
+  end
+  process $group_207
+    assign \fus_src4_i$66 2'00
+    assign \fus_src4_i$66 \xer_src2__data_o
+    sync init
   end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202"
+  wire width 1 \rdflag_XER_xer_ov
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81"
-  wire width 1 $216
+  wire width 1 $381
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81"
-  cell $and $217
+  cell $and $382
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -151863,5878 +170844,5172 @@ module \core
     parameter \Y_WIDTH 1
     connect \A \pdecode2_oe
     connect \B \pdecode2_oe_ok
-    connect \Y $216
+    connect \Y $381
   end
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81"
-  wire width 1 $218
+  wire width 1 $383
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81"
-  cell $or $219
+  cell $or $384
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $216
+    connect \A $381
     connect \B \pdecode2_xer_in
-    connect \Y $218
+    connect \Y $383
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83"
-  wire width 1 $220
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83"
-  cell $eq $221
+  process $group_208
+    assign \rdflag_XER_xer_ov 1'0
+    assign \rdflag_XER_xer_ov $383
+    sync init
+  end
+  process $group_209
+    assign \xer_src3__ren 3'000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:216"
+    switch { \rdpick_XER_xer_ov_en_o }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:216"
+      case 1'1
+        assign \xer_src3__ren 3'100
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  wire width 1 $385
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  cell $and $386
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 2
+    parameter \A_WIDTH 1
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 2
+    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \pdecode2_input_carry
-    connect \B 2'10
-    connect \Y $220
+    connect \A \fus_cu_rd__rel_o$39 [4]
+    connect \B \fu_enable [5]
+    connect \Y $385
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83"
-  wire width 1 $222
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83"
-  cell $or $223
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  wire width 1 $387
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  cell $and $388
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $220
-    connect \B \pdecode2_xer_in
-    connect \Y $222
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:180"
-  cell $not $224
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 6
-    parameter \Y_WIDTH 6
-    connect \A { $222 $218 $214 \pdecode2_fast1_ok \pdecode2_spr1_ok \pdecode2_reg1_ok }
-    connect \Y $211
+    connect \A $385
+    connect \B \rdflag_XER_xer_ov
+    connect \Y $387
   end
-  process $group_87
-    assign \fus_cu_rdmaskn_i$17 6'000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-    switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-            switch { \fu_enable [5] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-              case 1'1
-                assign \fus_cu_rdmaskn_i$17 $211
-            end
-        end
-    end
+  process $group_210
+    assign \rdpick_XER_xer_ov_i 1'0
+    assign \rdpick_XER_xer_ov_i $387
     sync init
   end
-  process $group_88
-    assign \fus_oper_i_alu_mul0__insn_type 7'0000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-    switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-            switch { \fu_enable [6] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-              case 1'1
-                assign \fus_oper_i_alu_mul0__insn_type \insn_type
-            end
-        end
-    end
+  process $group_211
+    assign \fus_src5_i 2'00
+    assign \fus_src5_i \xer_src3__data_o
     sync init
   end
-  process $group_89
-    assign \fus_oper_i_alu_mul0__fn_unit 11'00000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-    switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-            switch { \fu_enable [6] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-              case 1'1
-                assign \fus_oper_i_alu_mul0__fn_unit \pdecode2_fn_unit
-            end
-        end
-    end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202"
+  wire width 1 \rdflag_CR_full_cr
+  process $group_212
+    assign \rdflag_CR_full_cr 1'0
+    assign \rdflag_CR_full_cr \pdecode2_read_cr_whole
     sync init
   end
-  process $group_90
-    assign \fus_oper_i_alu_mul0__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \fus_oper_i_alu_mul0__imm_data__imm_ok 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-    switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+  process $group_213
+    assign \cr_full_rd__ren 8'00000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:216"
+    switch { \rdpick_CR_full_cr_en_o }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:216"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-            switch { \fu_enable [6] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-              case 1'1
-                assign { \fus_oper_i_alu_mul0__imm_data__imm_ok \fus_oper_i_alu_mul0__imm_data__imm } { \pdecode2_imm_ok \pdecode2_imm }
-            end
-        end
+        assign \cr_full_rd__ren 8'11111111
     end
     sync init
   end
-  process $group_92
-    assign \fus_oper_i_alu_mul0__rc__rc 1'0
-    assign \fus_oper_i_alu_mul0__rc__rc_ok 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-    switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-            switch { \fu_enable [6] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-              case 1'1
-                assign { \fus_oper_i_alu_mul0__rc__rc_ok \fus_oper_i_alu_mul0__rc__rc } { \pdecode2_rc_ok \pdecode2_rc }
-            end
-        end
-    end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  wire width 1 $389
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  cell $and $390
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \fus_cu_rd__rel_o$30 [2]
+    connect \B \fu_enable [1]
+    connect \Y $389
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  wire width 1 $391
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  cell $and $392
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $389
+    connect \B \rdflag_CR_full_cr
+    connect \Y $391
+  end
+  process $group_214
+    assign \rdpick_CR_full_cr_i 1'0
+    assign \rdpick_CR_full_cr_i $391
     sync init
   end
-  process $group_94
-    assign \fus_oper_i_alu_mul0__oe__oe 1'0
-    assign \fus_oper_i_alu_mul0__oe__oe_ok 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-    switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-            switch { \fu_enable [6] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-              case 1'1
-                assign { \fus_oper_i_alu_mul0__oe__oe_ok \fus_oper_i_alu_mul0__oe__oe } { \pdecode2_oe_ok \pdecode2_oe }
-            end
-        end
-    end
+  process $group_215
+    assign \fus_src3_i$67 32'00000000000000000000000000000000
+    assign \fus_src3_i$67 \cr_full_rd__data_o
     sync init
   end
-  process $group_96
-    assign \fus_oper_i_alu_mul0__invert_a 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-    switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-            switch { \fu_enable [6] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-              case 1'1
-                assign \fus_oper_i_alu_mul0__invert_a \pdecode2_invert_a
-            end
-        end
-    end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202"
+  wire width 1 \rdflag_CR_cr_a
+  process $group_216
+    assign \rdflag_CR_cr_a 1'0
+    assign \rdflag_CR_cr_a \pdecode2_cr_in1_ok
     sync init
   end
-  process $group_97
-    assign \fus_oper_i_alu_mul0__zero_a 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-    switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:65"
+  wire width 16 $393
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:65"
+  wire width 4 $394
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:65"
+  cell $sub $395
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 3
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 3
+    parameter \Y_WIDTH 4
+    connect \A 3'111
+    connect \B \pdecode2_cr_in1
+    connect \Y $394
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:65"
+  wire width 16 $396
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:65"
+  cell $sshl $397
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 4
+    parameter \Y_WIDTH 16
+    connect \A 1'1
+    connect \B $394
+    connect \Y $396
+  end
+  connect $393 $396
+  process $group_217
+    assign \cr_src1__ren 8'00000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:216"
+    switch { \rdpick_CR_cr_a_en_o }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:216"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-            switch { \fu_enable [6] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-              case 1'1
-                assign \fus_oper_i_alu_mul0__zero_a \pdecode2_zero_a
-            end
-        end
+        assign \cr_src1__ren $393 [7:0]
     end
     sync init
   end
-  process $group_98
-    assign \fus_oper_i_alu_mul0__invert_out 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-    switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-            switch { \fu_enable [6] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-              case 1'1
-                assign \fus_oper_i_alu_mul0__invert_out \pdecode2_invert_out
-            end
-        end
-    end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  wire width 1 $398
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  cell $and $399
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \fus_cu_rd__rel_o$30 [3]
+    connect \B \fu_enable [1]
+    connect \Y $398
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  wire width 1 $400
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  cell $and $401
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $398
+    connect \B \rdflag_CR_cr_a
+    connect \Y $400
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  wire width 1 $402
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  cell $and $403
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \fus_cu_rd__rel_o$69 [2]
+    connect \B \fu_enable [2]
+    connect \Y $402
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  wire width 1 $404
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  cell $and $405
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $402
+    connect \B \rdflag_CR_cr_a
+    connect \Y $404
+  end
+  process $group_218
+    assign \rdpick_CR_cr_a_i 2'00
+    assign \rdpick_CR_cr_a_i [0] $400
+    assign \rdpick_CR_cr_a_i [1] $404
     sync init
   end
-  process $group_99
-    assign \fus_oper_i_alu_mul0__write_cr0 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-    switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-            switch { \fu_enable [6] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-              case 1'1
-                assign \fus_oper_i_alu_mul0__write_cr0 \pdecode2_write_cr0
-            end
-        end
-    end
+  process $group_219
+    assign \fus_src4_i$68 4'0000
+    assign \fus_src4_i$68 \cr_src1__data_o
     sync init
   end
-  process $group_100
-    assign \fus_oper_i_alu_mul0__is_32bit 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-    switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-            switch { \fu_enable [6] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-              case 1'1
-                assign \fus_oper_i_alu_mul0__is_32bit \pdecode2_is_32bit
-            end
-        end
-    end
+  process $group_220
+    assign \fus_cu_rd__go_i$70 3'000
+    assign \fus_cu_rd__go_i$70 [2] \rdpick_CR_cr_a_o [1]
+    assign \fus_cu_rd__go_i$70 [0] \rdpick_FAST_fast1_o [0]
+    assign \fus_cu_rd__go_i$70 [1] \rdpick_FAST_fast2_o [0]
     sync init
   end
-  process $group_101
-    assign \fus_oper_i_alu_mul0__is_signed 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-    switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-            switch { \fu_enable [6] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-              case 1'1
-                assign \fus_oper_i_alu_mul0__is_signed \pdecode2_is_signed
-            end
-        end
-    end
+  process $group_221
+    assign \fus_src3_i$71 4'0000
+    assign \fus_src3_i$71 \cr_src1__data_o
     sync init
   end
-  process $group_102
-    assign \fus_oper_i_alu_mul0__insn 32'00000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-    switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-            switch { \fu_enable [6] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-              case 1'1
-                assign \fus_oper_i_alu_mul0__insn \pdecode2_insn
-            end
-        end
-    end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202"
+  wire width 1 \rdflag_CR_cr_b
+  process $group_222
+    assign \rdflag_CR_cr_b 1'0
+    assign \rdflag_CR_cr_b \pdecode2_cr_in2_ok
     sync init
   end
-  process $group_103
-    assign \fus_cu_issue_i$18 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-    switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:67"
+  wire width 16 $406
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:67"
+  wire width 4 $407
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:67"
+  cell $sub $408
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 3
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 3
+    parameter \Y_WIDTH 4
+    connect \A 3'111
+    connect \B \pdecode2_cr_in2
+    connect \Y $407
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:67"
+  wire width 16 $409
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:67"
+  cell $sshl $410
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 4
+    parameter \Y_WIDTH 16
+    connect \A 1'1
+    connect \B $407
+    connect \Y $409
+  end
+  connect $406 $409
+  process $group_223
+    assign \cr_src2__ren 8'00000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:216"
+    switch { \rdpick_CR_cr_b_en_o }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:216"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-            switch { \fu_enable [6] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-              case 1'1
-                assign \fus_cu_issue_i$18 \issue_i
-            end
-        end
+        assign \cr_src2__ren $406 [7:0]
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:180"
-  wire width 3 $225
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79"
-  wire width 1 $226
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79"
-  cell $and $227
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  wire width 1 $411
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  cell $and $412
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \pdecode2_oe
-    connect \B \pdecode2_oe_ok
-    connect \Y $226
+    connect \A \fus_cu_rd__rel_o$30 [4]
+    connect \B \fu_enable [1]
+    connect \Y $411
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79"
-  wire width 1 $228
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:79"
-  cell $or $229
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  wire width 1 $413
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  cell $and $414
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $226
-    connect \B \pdecode2_xer_in
-    connect \Y $228
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:180"
-  cell $not $230
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 3
-    parameter \Y_WIDTH 3
-    connect \A { $228 \pdecode2_reg2_ok \pdecode2_reg1_ok }
-    connect \Y $225
-  end
-  process $group_104
-    assign \fus_cu_rdmaskn_i$20 3'000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-    switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-            switch { \fu_enable [6] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-              case 1'1
-                assign \fus_cu_rdmaskn_i$20 $225
-            end
-        end
-    end
-    sync init
+    connect \A $411
+    connect \B \rdflag_CR_cr_b
+    connect \Y $413
   end
-  process $group_105
-    assign \fus_oper_i_alu_shift_rot0__insn_type 7'0000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-    switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-            switch { \fu_enable [7] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-              case 1'1
-                assign \fus_oper_i_alu_shift_rot0__insn_type \insn_type
-            end
-        end
-    end
+  process $group_224
+    assign \rdpick_CR_cr_b_i 1'0
+    assign \rdpick_CR_cr_b_i $413
     sync init
   end
-  process $group_106
-    assign \fus_oper_i_alu_shift_rot0__fn_unit 11'00000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-    switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-            switch { \fu_enable [7] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-              case 1'1
-                assign \fus_oper_i_alu_shift_rot0__fn_unit \pdecode2_fn_unit
-            end
-        end
-    end
+  process $group_225
+    assign \fus_src5_i$72 4'0000
+    assign \fus_src5_i$72 \cr_src2__data_o
     sync init
   end
-  process $group_107
-    assign \fus_oper_i_alu_shift_rot0__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \fus_oper_i_alu_shift_rot0__imm_data__imm_ok 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-    switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-            switch { \fu_enable [7] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-              case 1'1
-                assign { \fus_oper_i_alu_shift_rot0__imm_data__imm_ok \fus_oper_i_alu_shift_rot0__imm_data__imm } { \pdecode2_imm_ok \pdecode2_imm }
-            end
-        end
-    end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202"
+  wire width 1 \rdflag_CR_cr_c
+  process $group_226
+    assign \rdflag_CR_cr_c 1'0
+    assign \rdflag_CR_cr_c \pdecode2_cr_in2_ok$1
     sync init
   end
-  process $group_109
-    assign \fus_oper_i_alu_shift_rot0__rc__rc 1'0
-    assign \fus_oper_i_alu_shift_rot0__rc__rc_ok 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-    switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-            switch { \fu_enable [7] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-              case 1'1
-                assign { \fus_oper_i_alu_shift_rot0__rc__rc_ok \fus_oper_i_alu_shift_rot0__rc__rc } { \pdecode2_rc_ok \pdecode2_rc }
-            end
-        end
-    end
-    sync init
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:69"
+  wire width 16 $415
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:69"
+  wire width 4 $416
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:69"
+  cell $sub $417
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 3
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 3
+    parameter \Y_WIDTH 4
+    connect \A 3'111
+    connect \B \pdecode2_cr_in2$2
+    connect \Y $416
   end
-  process $group_111
-    assign \fus_oper_i_alu_shift_rot0__oe__oe 1'0
-    assign \fus_oper_i_alu_shift_rot0__oe__oe_ok 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-    switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-            switch { \fu_enable [7] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-              case 1'1
-                assign { \fus_oper_i_alu_shift_rot0__oe__oe_ok \fus_oper_i_alu_shift_rot0__oe__oe } { \pdecode2_oe_ok \pdecode2_oe }
-            end
-        end
-    end
-    sync init
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:69"
+  wire width 16 $418
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:69"
+  cell $sshl $419
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 4
+    parameter \Y_WIDTH 16
+    connect \A 1'1
+    connect \B $416
+    connect \Y $418
   end
-  process $group_113
-    assign { } 0'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-    switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+  connect $415 $418
+  process $group_227
+    assign \cr_src3__ren 8'00000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:216"
+    switch { \rdpick_CR_cr_c_en_o }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:216"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-            switch { \fu_enable [7] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-              case 1'1
-                assign { } {}
-            end
-        end
+        assign \cr_src3__ren $415 [7:0]
     end
     sync init
   end
-  process $group_114
-    assign \fus_oper_i_alu_shift_rot0__input_carry 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-    switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-            switch { \fu_enable [7] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-              case 1'1
-                assign \fus_oper_i_alu_shift_rot0__input_carry \pdecode2_input_carry
-            end
-        end
-    end
-    sync init
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  wire width 1 $420
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  cell $and $421
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \fus_cu_rd__rel_o$30 [5]
+    connect \B \fu_enable [1]
+    connect \Y $420
   end
-  process $group_115
-    assign \fus_oper_i_alu_shift_rot0__output_carry 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-    switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-            switch { \fu_enable [7] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-              case 1'1
-                assign \fus_oper_i_alu_shift_rot0__output_carry \pdecode2_output_carry
-            end
-        end
-    end
-    sync init
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  wire width 1 $422
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  cell $and $423
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $420
+    connect \B \rdflag_CR_cr_c
+    connect \Y $422
   end
-  process $group_116
-    assign \fus_oper_i_alu_shift_rot0__input_cr 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-    switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-            switch { \fu_enable [7] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-              case 1'1
-                assign \fus_oper_i_alu_shift_rot0__input_cr \pdecode2_input_cr
-            end
-        end
-    end
+  process $group_228
+    assign \rdpick_CR_cr_c_i 1'0
+    assign \rdpick_CR_cr_c_i $422
     sync init
   end
-  process $group_117
-    assign \fus_oper_i_alu_shift_rot0__output_cr 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-    switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-            switch { \fu_enable [7] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-              case 1'1
-                assign \fus_oper_i_alu_shift_rot0__output_cr \pdecode2_output_cr
-            end
-        end
-    end
+  process $group_229
+    assign \fus_src6_i$73 4'0000
+    assign \fus_src6_i$73 \cr_src3__data_o
     sync init
   end
-  process $group_118
-    assign \fus_oper_i_alu_shift_rot0__is_32bit 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-    switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-            switch { \fu_enable [7] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-              case 1'1
-                assign \fus_oper_i_alu_shift_rot0__is_32bit \pdecode2_is_32bit
-            end
-        end
-    end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202"
+  wire width 1 \rdflag_FAST_fast1
+  process $group_230
+    assign \rdflag_FAST_fast1 1'0
+    assign \rdflag_FAST_fast1 \pdecode2_fast1_ok
     sync init
   end
-  process $group_119
-    assign \fus_oper_i_alu_shift_rot0__is_signed 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-    switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-            switch { \fu_enable [7] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-              case 1'1
-                assign \fus_oper_i_alu_shift_rot0__is_signed \pdecode2_is_signed
-            end
-        end
-    end
-    sync init
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:102"
+  wire width 8 $424
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:102"
+  cell $sshl $425
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 3
+    parameter \Y_WIDTH 8
+    connect \A 1'1
+    connect \B \pdecode2_fast1
+    connect \Y $424
   end
-  process $group_120
-    assign \fus_oper_i_alu_shift_rot0__insn 32'00000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-    switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+  process $group_231
+    assign \fast_src1__ren 8'00000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:216"
+    switch { \rdpick_FAST_fast1_en_o }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:216"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-            switch { \fu_enable [7] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-              case 1'1
-                assign \fus_oper_i_alu_shift_rot0__insn \pdecode2_insn
-            end
-        end
+        assign \fast_src1__ren $424
     end
     sync init
   end
-  process $group_121
-    assign \fus_cu_issue_i$21 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-    switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-            switch { \fu_enable [7] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-              case 1'1
-                assign \fus_cu_issue_i$21 \issue_i
-            end
-        end
-    end
-    sync init
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  wire width 1 $426
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  cell $and $427
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \fus_cu_rd__rel_o$69 [0]
+    connect \B \fu_enable [2]
+    connect \Y $426
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:180"
-  wire width 4 $231
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83"
-  wire width 1 $232
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83"
-  cell $eq $233
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  wire width 1 $428
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  cell $and $429
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 2
+    parameter \A_WIDTH 1
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 2
+    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \pdecode2_input_carry
-    connect \B 2'10
-    connect \Y $232
+    connect \A $426
+    connect \B \rdflag_FAST_fast1
+    connect \Y $428
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83"
-  wire width 1 $234
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83"
-  cell $or $235
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  wire width 1 $430
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  cell $and $431
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $232
-    connect \B \pdecode2_xer_in
-    connect \Y $234
+    connect \A \fus_cu_rd__rel_o$33 [2]
+    connect \B \fu_enable [3]
+    connect \Y $430
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:180"
-  cell $not $236
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  wire width 1 $432
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  cell $and $433
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 4
-    parameter \Y_WIDTH 4
-    connect \A { $234 \pdecode2_reg3_ok \pdecode2_reg2_ok \pdecode2_reg1_ok }
-    connect \Y $231
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $430
+    connect \B \rdflag_FAST_fast1
+    connect \Y $432
   end
-  process $group_122
-    assign \fus_cu_rdmaskn_i$23 4'0000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-    switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-            switch { \fu_enable [7] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-              case 1'1
-                assign \fus_cu_rdmaskn_i$23 $231
-            end
-        end
-    end
-    sync init
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  wire width 1 $434
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  cell $and $435
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \fus_cu_rd__rel_o$39 [2]
+    connect \B \fu_enable [5]
+    connect \Y $434
   end
-  process $group_123
-    assign \fus_oper_i_ldst_ldst0__insn_type 7'0000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-    switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-            switch { \fu_enable [8] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-              case 1'1
-                assign \fus_oper_i_ldst_ldst0__insn_type \insn_type
-            end
-        end
-    end
-    sync init
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  wire width 1 $436
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  cell $and $437
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $434
+    connect \B \rdflag_FAST_fast1
+    connect \Y $436
   end
-  process $group_124
-    assign \fus_oper_i_ldst_ldst0__imm_data__imm 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \fus_oper_i_ldst_ldst0__imm_data__imm_ok 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-    switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-            switch { \fu_enable [8] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-              case 1'1
-                assign { \fus_oper_i_ldst_ldst0__imm_data__imm_ok \fus_oper_i_ldst_ldst0__imm_data__imm } { \pdecode2_imm_ok \pdecode2_imm }
-            end
-        end
-    end
+  process $group_232
+    assign \rdpick_FAST_fast1_i 3'000
+    assign \rdpick_FAST_fast1_i [0] $428
+    assign \rdpick_FAST_fast1_i [1] $432
+    assign \rdpick_FAST_fast1_i [2] $436
     sync init
   end
-  process $group_126
-    assign \fus_oper_i_ldst_ldst0__zero_a 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-    switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-            switch { \fu_enable [8] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-              case 1'1
-                assign \fus_oper_i_ldst_ldst0__zero_a \pdecode2_zero_a
-            end
-        end
-    end
+  process $group_233
+    assign \fus_src1_i$74 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \fus_src1_i$74 \fast_src1__data_o
     sync init
   end
-  process $group_127
-    assign \fus_oper_i_ldst_ldst0__rc__rc 1'0
-    assign \fus_oper_i_ldst_ldst0__rc__rc_ok 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-    switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-            switch { \fu_enable [8] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-              case 1'1
-                assign { \fus_oper_i_ldst_ldst0__rc__rc_ok \fus_oper_i_ldst_ldst0__rc__rc } { \pdecode2_rc_ok \pdecode2_rc }
-            end
-        end
-    end
+  process $group_234
+    assign \fus_src3_i$75 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \fus_src3_i$75 \fast_src1__data_o
     sync init
-  end
-  process $group_129
-    assign \fus_oper_i_ldst_ldst0__oe__oe 1'0
-    assign \fus_oper_i_ldst_ldst0__oe__oe_ok 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-    switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-            switch { \fu_enable [8] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-              case 1'1
-                assign { \fus_oper_i_ldst_ldst0__oe__oe_ok \fus_oper_i_ldst_ldst0__oe__oe } { \pdecode2_oe_ok \pdecode2_oe }
-            end
-        end
-    end
+  end
+  process $group_235
+    assign \fus_src3_i$76 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \fus_src3_i$76 \fast_src1__data_o
     sync init
   end
-  process $group_131
-    assign \fus_oper_i_ldst_ldst0__is_32bit 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-    switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-            switch { \fu_enable [8] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-              case 1'1
-                assign \fus_oper_i_ldst_ldst0__is_32bit \pdecode2_is_32bit
-            end
-        end
-    end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202"
+  wire width 1 \rdflag_FAST_fast2
+  process $group_236
+    assign \rdflag_FAST_fast2 1'0
+    assign \rdflag_FAST_fast2 \pdecode2_fast2_ok
     sync init
   end
-  process $group_132
-    assign \fus_oper_i_ldst_ldst0__is_signed 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-    switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:104"
+  wire width 8 $438
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:104"
+  cell $sshl $439
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 3
+    parameter \Y_WIDTH 8
+    connect \A 1'1
+    connect \B \pdecode2_fast2
+    connect \Y $438
+  end
+  process $group_237
+    assign \fast_src2__ren 8'00000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:216"
+    switch { \rdpick_FAST_fast2_en_o }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:216"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-            switch { \fu_enable [8] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-              case 1'1
-                assign \fus_oper_i_ldst_ldst0__is_signed \pdecode2_is_signed
-            end
-        end
+        assign \fast_src2__ren $438
     end
     sync init
   end
-  process $group_133
-    assign \fus_oper_i_ldst_ldst0__data_len 4'0000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-    switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-            switch { \fu_enable [8] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-              case 1'1
-                assign \fus_oper_i_ldst_ldst0__data_len \pdecode2_data_len
-            end
-        end
-    end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  wire width 1 $440
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  cell $and $441
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \fus_cu_rd__rel_o$69 [1]
+    connect \B \fu_enable [2]
+    connect \Y $440
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  wire width 1 $442
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  cell $and $443
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $440
+    connect \B \rdflag_FAST_fast2
+    connect \Y $442
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  wire width 1 $444
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  cell $and $445
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \fus_cu_rd__rel_o$33 [3]
+    connect \B \fu_enable [3]
+    connect \Y $444
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  wire width 1 $446
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  cell $and $447
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $444
+    connect \B \rdflag_FAST_fast2
+    connect \Y $446
+  end
+  process $group_238
+    assign \rdpick_FAST_fast2_i 2'00
+    assign \rdpick_FAST_fast2_i [0] $442
+    assign \rdpick_FAST_fast2_i [1] $446
     sync init
   end
-  process $group_134
-    assign \fus_oper_i_ldst_ldst0__byte_reverse 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-    switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-            switch { \fu_enable [8] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-              case 1'1
-                assign \fus_oper_i_ldst_ldst0__byte_reverse \pdecode2_byte_reverse
-            end
-        end
-    end
+  process $group_239
+    assign \fus_src2_i$77 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \fus_src2_i$77 \fast_src2__data_o
     sync init
   end
-  process $group_135
-    assign \fus_oper_i_ldst_ldst0__sign_extend 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-    switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-            switch { \fu_enable [8] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-              case 1'1
-                assign \fus_oper_i_ldst_ldst0__sign_extend \pdecode2_sign_extend
-            end
-        end
-    end
+  process $group_240
+    assign \fus_src4_i$78 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \fus_src4_i$78 \fast_src2__data_o
     sync init
   end
-  process $group_136
-    assign \fus_oper_i_ldst_ldst0__ldst_mode 2'00
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-    switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-      case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-            switch { \fu_enable [8] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-              case 1'1
-                assign \fus_oper_i_ldst_ldst0__ldst_mode \pdecode2_ldst_mode
-            end
-        end
-    end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:202"
+  wire width 1 \rdflag_SPR_spr1
+  process $group_241
+    assign \rdflag_SPR_spr1 1'0
+    assign \rdflag_SPR_spr1 \pdecode2_spr1_ok
     sync init
   end
-  process $group_137
-    assign \fus_cu_issue_i$24 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
-    switch { \can_run }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
+  process $group_242
+    assign \spr_src__ren 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:216"
+    switch { \rdpick_SPR_spr1_en_o }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:216"
       case 1'1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:159"
-        switch \insn_type
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161"
-          attribute \nmigen.decoding "OP_ATTN/5"
-          case 7'0000101
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-          attribute \nmigen.decoding "OP_NOP/1"
-          case 7'0000001
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
-          attribute \nmigen.decoding ""
-          case
-            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-            switch { \fu_enable [8] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-              case 1'1
-                assign \fus_cu_issue_i$24 \issue_i
-            end
-        end
+        assign \spr_src__ren \pdecode2_spr1 [0]
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:180"
-  wire width 3 $237
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:180"
-  cell $not $238
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  wire width 1 $448
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  cell $and $449
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 3
-    parameter \Y_WIDTH 3
-    connect \A { \pdecode2_reg3_ok \pdecode2_reg2_ok \pdecode2_reg1_ok }
-    connect \Y $237
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \fus_cu_rd__rel_o$39 [1]
+    connect \B \fu_enable [5]
+    connect \Y $448
   end
-  process $group_138
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-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
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-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:158"
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-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:164"
-          attribute \nmigen.decoding "OP_NOP/1"
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-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:168"
-          attribute \nmigen.decoding ""
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-            switch { \fu_enable [8] }
-              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:174"
-              case 1'1
-                assign \fus_cu_rdmaskn_i$26 $237
-            end
-        end
-    end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  wire width 1 $450
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  cell $and $451
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+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $448
+    connect \B \rdflag_SPR_spr1
+    connect \Y $450
+  end
+  process $group_243
+    assign \rdpick_SPR_spr1_i 1'0
+    assign \rdpick_SPR_spr1_i $450
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212"
-  wire width 1 \rdflag_INT_ra
-  process $group_139
-    assign \rdflag_INT_ra 1'0
-    assign \rdflag_INT_ra \pdecode2_reg1_ok
+  process $group_244
+    assign \fus_src2_i$79 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \fus_src2_i$79 \spr_src__data_o
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:51"
-  wire width 32 $239
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:51"
-  cell $sshl $240
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:125"
+  wire width 32 $452
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:125"
+  cell $sshl $453
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 5
     parameter \Y_WIDTH 32
     connect \A 1'1
-    connect \B \pdecode2_reg1
-    connect \Y $239
+    connect \B \pdecode2_rego
+    connect \Y $452
   end
-  process $group_140
-    assign \int_src1__ren 32'00000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-    switch { \rdpick_INT_ra_en_o }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  process $group_245
+    assign \int_wen 32'00000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279"
+    switch { \wrpick_INT_o_en_o }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279"
       case 1'1
-        assign \int_src1__ren $239
+        assign \int_wen $452
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
+      case
+        assign \int_wen 32'00000000000000000000000000000000
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     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  wire width 1 $241
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  cell $and $242
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292"
+  wire width 1 \wrflag_alu0_o_0
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
+  wire width 1 $454
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
+  cell $and $455
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_cu_rd__rel_o [0]
-    connect \B \fu_enable [0]
-    connect \Y $241
+    connect \A \fus_o_ok
+    connect \B \fus_cu_busy_o
+    connect \Y $454
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  wire width 1 $243
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-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A $241
-    connect \B \rdflag_INT_ra
-    connect \Y $243
+  process $group_246
+    assign \wrflag_alu0_o_0 1'0
+    assign \wrflag_alu0_o_0 $454
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  wire width 1 $245
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  cell $and $246
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+  wire width 1 $456
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+  cell $and $457
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
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     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_cu_rd__rel_o$27 [0]
-    connect \B \fu_enable [1]
-    connect \Y $245
+    connect \A \fus_cu_wr__rel_o [0]
+    connect \B \fu_enable [0]
+    connect \Y $456
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-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  wire width 1 $247
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  cell $and $248
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+  wire width 1 $458
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+  cell $and $459
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $245
-    connect \B \rdflag_INT_ra
-    connect \Y $247
+    connect \A \fus_cu_wr__rel_o$81 [0]
+    connect \B \fu_enable [1]
+    connect \Y $458
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-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  wire width 1 $249
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  cell $and $250
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+  wire width 1 $460
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+  cell $and $461
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_cu_rd__rel_o$30 [0]
+    connect \A \fus_cu_wr__rel_o$84 [0]
     connect \B \fu_enable [3]
-    connect \Y $249
+    connect \Y $460
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-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  wire width 1 $251
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  cell $and $252
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+  wire width 1 $462
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+  cell $and $463
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $249
-    connect \B \rdflag_INT_ra
-    connect \Y $251
+    connect \A \fus_cu_wr__rel_o$87 [0]
+    connect \B \fu_enable [4]
+    connect \Y $462
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-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  wire width 1 $253
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  cell $and $254
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+  wire width 1 $464
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+  cell $and $465
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
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     parameter \Y_WIDTH 1
-    connect \A \fus_cu_rd__rel_o$33 [0]
-    connect \B \fu_enable [4]
-    connect \Y $253
+    connect \A \fus_cu_wr__rel_o$90 [0]
+    connect \B \fu_enable [5]
+    connect \Y $464
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-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  wire width 1 $255
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  cell $and $256
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+  wire width 1 $466
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+  cell $and $467
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $253
-    connect \B \rdflag_INT_ra
-    connect \Y $255
+    connect \A \fus_cu_wr__rel_o$93 [0]
+    connect \B \fu_enable [6]
+    connect \Y $466
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-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  wire width 1 $257
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  cell $and $258
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+  wire width 1 $468
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+  cell $and $469
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_cu_rd__rel_o$36 [0]
-    connect \B \fu_enable [5]
-    connect \Y $257
+    connect \A \fus_cu_wr__rel_o$96 [0]
+    connect \B \fu_enable [7]
+    connect \Y $468
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  wire width 1 $259
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  cell $and $260
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+  wire width 1 $470
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+  cell $and $471
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $257
-    connect \B \rdflag_INT_ra
-    connect \Y $259
+    connect \A \fus_cu_wr__rel_o$99 [0]
+    connect \B \fu_enable [8]
+    connect \Y $470
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  wire width 1 $261
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  cell $and $262
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+  wire width 1 $472
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+  cell $and $473
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_cu_rd__rel_o$39 [0]
-    connect \B \fu_enable [6]
-    connect \Y $261
+    connect \A \fus_cu_wr__rel_o$101 [0]
+    connect \B \fu_enable [9]
+    connect \Y $472
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-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  wire width 1 $263
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  cell $and $264
+  process $group_247
+    assign \wrpick_INT_o_i 9'000000000
+    assign \wrpick_INT_o_i [0] $456
+    assign \wrpick_INT_o_i [1] $458
+    assign \wrpick_INT_o_i [2] $460
+    assign \wrpick_INT_o_i [3] $462
+    assign \wrpick_INT_o_i [4] $464
+    assign \wrpick_INT_o_i [5] $466
+    assign \wrpick_INT_o_i [6] $468
+    assign \wrpick_INT_o_i [7] $470
+    assign \wrpick_INT_o_i [8] $472
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299"
+  wire width 1 $474
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299"
+  cell $and $475
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $261
-    connect \B \rdflag_INT_ra
-    connect \Y $263
+    connect \A \wrpick_INT_o_o [0]
+    connect \B \wrpick_INT_o_en_o
+    connect \Y $474
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  wire width 1 $265
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  cell $and $266
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299"
+  wire width 1 $476
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299"
+  cell $and $477
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_cu_rd__rel_o$42 [0]
-    connect \B \fu_enable [7]
-    connect \Y $265
+    connect \A \wrpick_CR_cr_a_o [0]
+    connect \B \wrpick_CR_cr_a_en_o
+    connect \Y $476
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  wire width 1 $267
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  cell $and $268
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299"
+  wire width 1 $478
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299"
+  cell $and $479
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $265
-    connect \B \rdflag_INT_ra
-    connect \Y $267
+    connect \A \wrpick_XER_xer_ca_o [0]
+    connect \B \wrpick_XER_xer_ca_en_o
+    connect \Y $478
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  wire width 1 $269
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  cell $and $270
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299"
+  wire width 1 $480
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299"
+  cell $and $481
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_cu_rd__rel_o$45 [0]
-    connect \B \fu_enable [8]
-    connect \Y $269
+    connect \A \wrpick_XER_xer_ov_o [0]
+    connect \B \wrpick_XER_xer_ov_en_o
+    connect \Y $480
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-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  wire width 1 $271
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
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+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299"
+  wire width 1 $482
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299"
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-  process $group_141
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-  process $group_142
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-  process $group_143
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-  process $group_144
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-  process $group_147
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-  process $group_148
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-  process $group_150
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-  process $group_151
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-  process $group_152
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-    assign \fus_src1_i$47 64'0000000000000000000000000000000000000000000000000000000000000000
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+    assign \fus_cu_wr__go_i 5'00000
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-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
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-    connect \Y $275
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-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
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+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299"
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+    assign \fus_cu_wr__go_i$82 [1] $488
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-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
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     parameter \B_WIDTH 1
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-    connect \A $283
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+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299"
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     parameter \B_WIDTH 1
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-    connect \A $287
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-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  wire width 1 $291
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
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-    connect \Y $291
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-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
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+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299"
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     parameter \B_WIDTH 1
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-    connect \A $291
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+    connect \A \wrpick_FAST_msr_o
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-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  wire width 1 $295
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+    assign \fus_cu_wr__go_i$85 [3] $500
+    assign \fus_cu_wr__go_i$85 [4] $502
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+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292"
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+  wire width 1 $504
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-    connect \A \fus_cu_rd__rel_o$42 [1]
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-    connect \Y $295
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-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  wire width 1 $297
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
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-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  wire width 1 $299
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+    assign \fus_cu_wr__go_i$91 [2] $522
+    assign \fus_cu_wr__go_i$91 [1] $524
     sync init
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-    connect \A $317
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-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
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+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299"
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-    connect \A $321
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-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
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+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299"
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+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299"
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+    assign \fus_cu_wr__go_i$94 [0] $528
+    assign \fus_cu_wr__go_i$94 [1] $530
+    assign \fus_cu_wr__go_i$94 [2] $532
+    assign \fus_cu_wr__go_i$94 [3] $534
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+  wire width 1 \wrflag_mul0_o_0
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+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
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-    assign \fus_src4_i 1'0
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+    connect \A \fus_o_ok$95
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+    connect \Y $536
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-  process $group_178
-    assign \fus_src3_i$56 1'0
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+    assign \wrflag_mul0_o_0 1'0
+    assign \wrflag_mul0_o_0 $536
     sync init
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-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212"
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-  wire width 1 $331
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83"
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+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299"
+  wire width 1 $538
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299"
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-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  wire width 1 $333
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+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299"
+  wire width 1 $540
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299"
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-    connect \A \fus_cu_rd__rel_o [3]
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-    connect \Y $333
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-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
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-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
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-    connect \A $333
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-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
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+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299"
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-    connect \A \fus_cu_rd__rel_o$36 [5]
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-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
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-    connect \A $337
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-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
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-  process $group_184
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-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212"
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-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81"
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+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299"
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     parameter \B_WIDTH 1
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+    assign \fus_cu_wr__go_i$100 [2] $552
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+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292"
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-  end
-  process $group_185
-    assign \rdflag_XER_xer_ov 1'0
-    assign \rdflag_XER_xer_ov $347
-    sync init
+    connect \A \o_ok
+    connect \B \fus_cu_busy_o$28
+    connect \Y $554
   end
-  process $group_186
-    assign \xer_src3__ren 3'000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-    switch { \rdpick_XER_xer_ov_en_o }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-      case 1'1
-        assign \xer_src3__ren 3'100
-    end
+  process $group_263
+    assign \wrflag_ldst0_o_0 1'0
+    assign \wrflag_ldst0_o_0 $554
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  wire width 1 $349
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  cell $and $350
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299"
+  wire width 1 $556
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299"
+  cell $and $557
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_cu_rd__rel_o$36 [4]
-    connect \B \fu_enable [5]
-    connect \Y $349
+    connect \A \wrpick_INT_o_o [8]
+    connect \B \wrpick_INT_o_en_o
+    connect \Y $556
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  wire width 1 $351
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  cell $and $352
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299"
+  wire width 1 $558
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299"
+  cell $and $559
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $349
-    connect \B \rdflag_XER_xer_ov
-    connect \Y $351
-  end
-  process $group_187
-    assign \rdpick_XER_xer_ov_i 1'0
-    assign \rdpick_XER_xer_ov_i $351
-    sync init
+    connect \A \wrpick_INT_o1_o
+    connect \B \wrpick_INT_o1_en_o
+    connect \Y $558
   end
-  process $group_188
-    assign \fus_src5_i 2'00
-    assign \fus_src5_i \xer_src3__data_o
+  process $group_264
+    assign \fus_cu_wr__go_i$102 2'00
+    assign \fus_cu_wr__go_i$102 [0] $556
+    assign \fus_cu_wr__go_i$102 [1] $558
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212"
-  wire width 1 \rdflag_CR_full_cr
-  process $group_189
-    assign \rdflag_CR_full_cr 1'0
-    assign \rdflag_CR_full_cr \pdecode2_read_cr_whole
-    sync init
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+  wire width 65 $560
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+  wire width 64 $561
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+  cell $or $562
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 64
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 64
+    parameter \Y_WIDTH 64
+    connect \A \fus_dest1_o
+    connect \B \fus_dest1_o$103
+    connect \Y $561
   end
-  process $group_190
-    assign \cr_full_rd__ren 8'00000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-    switch { \rdpick_CR_full_cr_en_o }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-      case 1'1
-        assign \cr_full_rd__ren 8'11111111
-    end
-    sync init
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+  wire width 64 $563
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+  cell $or $564
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 64
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 64
+    parameter \Y_WIDTH 64
+    connect \A \fus_dest1_o$104
+    connect \B \fus_dest1_o$105
+    connect \Y $563
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  wire width 1 $353
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  cell $and $354
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+  wire width 64 $565
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+  cell $or $566
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
+    parameter \A_WIDTH 64
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \fus_cu_rd__rel_o$27 [2]
-    connect \B \fu_enable [1]
-    connect \Y $353
+    parameter \B_WIDTH 64
+    parameter \Y_WIDTH 64
+    connect \A $561
+    connect \B $563
+    connect \Y $565
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  wire width 1 $355
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  cell $and $356
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+  wire width 64 $567
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+  cell $or $568
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
+    parameter \A_WIDTH 64
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A $353
-    connect \B \rdflag_CR_full_cr
-    connect \Y $355
+    parameter \B_WIDTH 64
+    parameter \Y_WIDTH 64
+    connect \A \fus_dest1_o$106
+    connect \B \fus_dest1_o$107
+    connect \Y $567
   end
-  process $group_191
-    assign \rdpick_CR_full_cr_i 1'0
-    assign \rdpick_CR_full_cr_i $355
-    sync init
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+  wire width 65 $569
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+  cell $or $570
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 64
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 65
+    parameter \Y_WIDTH 65
+    connect \A \fus_dest1_o$109
+    connect \B { \o_ok \fus_o }
+    connect \Y $569
   end
-  process $group_192
-    assign \fus_src3_i$59 32'00000000000000000000000000000000
-    assign \fus_src3_i$59 \cr_full_rd__data_o
-    sync init
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+  wire width 65 $571
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+  cell $or $572
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 64
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 65
+    parameter \Y_WIDTH 65
+    connect \A \fus_dest1_o$108
+    connect \B $569
+    connect \Y $571
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212"
-  wire width 1 \rdflag_CR_cr_a
-  process $group_193
-    assign \rdflag_CR_cr_a 1'0
-    assign \rdflag_CR_cr_a \pdecode2_cr_in1_ok
-    sync init
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+  wire width 65 $573
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+  cell $or $574
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 64
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 65
+    parameter \Y_WIDTH 65
+    connect \A $567
+    connect \B $571
+    connect \Y $573
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:65"
-  wire width 16 $357
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:65"
-  wire width 4 $358
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:65"
-  cell $sub $359
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+  wire width 65 $575
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+  cell $or $576
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 3
+    parameter \A_WIDTH 64
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 3
-    parameter \Y_WIDTH 4
-    connect \A 3'111
-    connect \B \pdecode2_cr_in1
-    connect \Y $358
+    parameter \B_WIDTH 65
+    parameter \Y_WIDTH 65
+    connect \A $565
+    connect \B $573
+    connect \Y $575
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:65"
-  wire width 16 $360
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:65"
-  cell $sshl $361
+  connect $560 $575
+  process $group_265
+    assign \int_data_i 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \int_data_i $560 [63:0]
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:127"
+  wire width 32 $577
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:127"
+  cell $sshl $578
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 4
-    parameter \Y_WIDTH 16
+    parameter \B_WIDTH 5
+    parameter \Y_WIDTH 32
     connect \A 1'1
-    connect \B $358
-    connect \Y $360
+    connect \B \pdecode2_ea
+    connect \Y $577
   end
-  connect $357 $360
-  process $group_194
-    assign \cr_src1__ren 8'00000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-    switch { \rdpick_CR_cr_a_en_o }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  process $group_266
+    assign \int_wen$153 32'00000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279"
+    switch { \wrpick_INT_o1_en_o }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279"
       case 1'1
-        assign \cr_src1__ren $357 [7:0]
+        assign \int_wen$153 $577
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
+      case
+        assign \int_wen$153 32'00000000000000000000000000000000
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  wire width 1 $362
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  cell $and $363
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292"
+  wire width 1 \wrflag_ldst0_o1_1
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
+  wire width 1 \ea_ok
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
+  wire width 1 $579
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
+  cell $and $580
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_cu_rd__rel_o$27 [3]
-    connect \B \fu_enable [1]
-    connect \Y $362
+    connect \A \ea_ok
+    connect \B \fus_cu_busy_o$28
+    connect \Y $579
+  end
+  process $group_267
+    assign \wrflag_ldst0_o1_1 1'0
+    assign \wrflag_ldst0_o1_1 $579
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  wire width 1 $364
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  cell $and $365
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+  wire width 1 $581
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+  cell $and $582
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $362
-    connect \B \rdflag_CR_cr_a
-    connect \Y $364
+    connect \A \fus_cu_wr__rel_o$101 [1]
+    connect \B \fu_enable [9]
+    connect \Y $581
+  end
+  process $group_268
+    assign \wrpick_INT_o1_i 1'0
+    assign \wrpick_INT_o1_i $581
+    sync init
+  end
+  process $group_269
+    assign \int_data_i$154 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \int_data_i$154 { \ea_ok \fus_ea } [63:0]
+    sync init
+  end
+  process $group_270
+    assign \cr_full_wr__wen 8'00000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279"
+    switch { \wrpick_CR_full_cr_en_o }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279"
+      case 1'1
+        assign \cr_full_wr__wen 8'11111111
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
+      case
+        assign \cr_full_wr__wen 8'00000000
+    end
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  wire width 1 $366
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  cell $and $367
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292"
+  wire width 1 \wrflag_cr0_full_cr_1
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
+  wire width 1 $583
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
+  cell $and $584
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_cu_rd__rel_o$61 [2]
-    connect \B \fu_enable [2]
-    connect \Y $366
+    connect \A \fus_full_cr_ok
+    connect \B \fus_cu_busy_o$4
+    connect \Y $583
+  end
+  process $group_271
+    assign \wrflag_cr0_full_cr_1 1'0
+    assign \wrflag_cr0_full_cr_1 $583
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  wire width 1 $368
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  cell $and $369
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+  wire width 1 $585
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+  cell $and $586
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $366
-    connect \B \rdflag_CR_cr_a
-    connect \Y $368
-  end
-  process $group_195
-    assign \rdpick_CR_cr_a_i 2'00
-    assign \rdpick_CR_cr_a_i [0] $364
-    assign \rdpick_CR_cr_a_i [1] $368
-    sync init
-  end
-  process $group_196
-    assign \fus_src4_i$60 4'0000
-    assign \fus_src4_i$60 \cr_src1__data_o
-    sync init
-  end
-  process $group_197
-    assign \fus_cu_rd__go_i$62 3'000
-    assign \fus_cu_rd__go_i$62 [2] \rdpick_CR_cr_a_o [1]
-    assign \fus_cu_rd__go_i$62 [0] \rdpick_FAST_fast1_o [0]
-    assign \fus_cu_rd__go_i$62 [1] \rdpick_FAST_fast2_o [0]
-    sync init
+    connect \A \fus_cu_wr__rel_o$81 [1]
+    connect \B \fu_enable [1]
+    connect \Y $585
   end
-  process $group_198
-    assign \fus_src3_i$63 4'0000
-    assign \fus_src3_i$63 \cr_src1__data_o
+  process $group_272
+    assign \wrpick_CR_full_cr_i 1'0
+    assign \wrpick_CR_full_cr_i $585
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212"
-  wire width 1 \rdflag_CR_cr_b
-  process $group_199
-    assign \rdflag_CR_cr_b 1'0
-    assign \rdflag_CR_cr_b \pdecode2_cr_in2_ok
+  process $group_273
+    assign \cr_full_wr__data_i 32'00000000000000000000000000000000
+    assign \cr_full_wr__data_i \fus_dest2_o
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:67"
-  wire width 16 $370
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:67"
-  wire width 4 $371
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:67"
-  cell $sub $372
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:137"
+  wire width 16 $587
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:137"
+  wire width 4 $588
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:137"
+  cell $sub $589
     parameter \A_SIGNED 0
     parameter \A_WIDTH 3
     parameter \B_SIGNED 0
     parameter \B_WIDTH 3
     parameter \Y_WIDTH 4
     connect \A 3'111
-    connect \B \pdecode2_cr_in2
-    connect \Y $371
+    connect \B \pdecode2_cr_out
+    connect \Y $588
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:67"
-  wire width 16 $373
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:67"
-  cell $sshl $374
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:137"
+  wire width 16 $590
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:137"
+  cell $sshl $591
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 4
     parameter \Y_WIDTH 16
     connect \A 1'1
-    connect \B $371
-    connect \Y $373
+    connect \B $588
+    connect \Y $590
   end
-  connect $370 $373
-  process $group_200
-    assign \cr_src2__ren 8'00000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-    switch { \rdpick_CR_cr_b_en_o }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  connect $587 $590
+  process $group_274
+    assign \cr_wen 8'00000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279"
+    switch { \wrpick_CR_cr_a_en_o }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279"
       case 1'1
-        assign \cr_src2__ren $370 [7:0]
+        assign \cr_wen $587 [7:0]
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
+      case
+        assign \cr_wen 8'00000000
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  wire width 1 $375
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  cell $and $376
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292"
+  wire width 1 \wrflag_alu0_cr_a_1
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
+  wire width 1 $592
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
+  cell $and $593
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_cu_rd__rel_o$27 [4]
-    connect \B \fu_enable [1]
-    connect \Y $375
+    connect \A \fus_cr_a_ok
+    connect \B \fus_cu_busy_o
+    connect \Y $592
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  wire width 1 $377
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  cell $and $378
+  process $group_275
+    assign \wrflag_alu0_cr_a_1 1'0
+    assign \wrflag_alu0_cr_a_1 $592
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+  wire width 1 $594
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+  cell $and $595
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $375
-    connect \B \rdflag_CR_cr_b
-    connect \Y $377
-  end
-  process $group_201
-    assign \rdpick_CR_cr_b_i 1'0
-    assign \rdpick_CR_cr_b_i $377
-    sync init
-  end
-  process $group_202
-    assign \fus_src5_i$64 4'0000
-    assign \fus_src5_i$64 \cr_src2__data_o
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212"
-  wire width 1 \rdflag_CR_cr_c
-  process $group_203
-    assign \rdflag_CR_cr_c 1'0
-    assign \rdflag_CR_cr_c \pdecode2_cr_in2_ok$1
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:69"
-  wire width 16 $379
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:69"
-  wire width 4 $380
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:69"
-  cell $sub $381
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 3
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 3
-    parameter \Y_WIDTH 4
-    connect \A 3'111
-    connect \B \pdecode2_cr_in2$2
-    connect \Y $380
+    connect \A \fus_cu_wr__rel_o [1]
+    connect \B \fu_enable [0]
+    connect \Y $594
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:69"
-  wire width 16 $382
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:69"
-  cell $sshl $383
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+  wire width 1 $596
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+  cell $and $597
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 4
-    parameter \Y_WIDTH 16
-    connect \A 1'1
-    connect \B $380
-    connect \Y $382
-  end
-  connect $379 $382
-  process $group_204
-    assign \cr_src3__ren 8'00000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-    switch { \rdpick_CR_cr_c_en_o }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-      case 1'1
-        assign \cr_src3__ren $379 [7:0]
-    end
-    sync init
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \fus_cu_wr__rel_o$81 [2]
+    connect \B \fu_enable [1]
+    connect \Y $596
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  wire width 1 $384
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  cell $and $385
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+  wire width 1 $598
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+  cell $and $599
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_cu_rd__rel_o$27 [5]
-    connect \B \fu_enable [1]
-    connect \Y $384
+    connect \A \fus_cu_wr__rel_o$87 [1]
+    connect \B \fu_enable [4]
+    connect \Y $598
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  wire width 1 $386
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  cell $and $387
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+  wire width 1 $600
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+  cell $and $601
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $384
-    connect \B \rdflag_CR_cr_c
-    connect \Y $386
-  end
-  process $group_205
-    assign \rdpick_CR_cr_c_i 1'0
-    assign \rdpick_CR_cr_c_i $386
-    sync init
-  end
-  process $group_206
-    assign \fus_src6_i$65 4'0000
-    assign \fus_src6_i$65 \cr_src3__data_o
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212"
-  wire width 1 \rdflag_FAST_fast1
-  process $group_207
-    assign \rdflag_FAST_fast1 1'0
-    assign \rdflag_FAST_fast1 \pdecode2_fast1_ok
-    sync init
+    connect \A \fus_cu_wr__rel_o$93 [1]
+    connect \B \fu_enable [6]
+    connect \Y $600
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:102"
-  wire width 8 $388
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:102"
-  cell $sshl $389
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+  wire width 1 $602
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+  cell $and $603
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 3
-    parameter \Y_WIDTH 8
-    connect \A 1'1
-    connect \B \pdecode2_fast1
-    connect \Y $388
-  end
-  process $group_208
-    assign \fast_src1__ren 8'00000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-    switch { \rdpick_FAST_fast1_en_o }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-      case 1'1
-        assign \fast_src1__ren $388
-    end
-    sync init
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \fus_cu_wr__rel_o$96 [1]
+    connect \B \fu_enable [7]
+    connect \Y $602
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  wire width 1 $390
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  cell $and $391
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+  wire width 1 $604
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+  cell $and $605
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_cu_rd__rel_o$61 [0]
-    connect \B \fu_enable [2]
-    connect \Y $390
+    connect \A \fus_cu_wr__rel_o$99 [1]
+    connect \B \fu_enable [8]
+    connect \Y $604
+  end
+  process $group_276
+    assign \wrpick_CR_cr_a_i 6'000000
+    assign \wrpick_CR_cr_a_i [0] $594
+    assign \wrpick_CR_cr_a_i [1] $596
+    assign \wrpick_CR_cr_a_i [2] $598
+    assign \wrpick_CR_cr_a_i [3] $600
+    assign \wrpick_CR_cr_a_i [4] $602
+    assign \wrpick_CR_cr_a_i [5] $604
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  wire width 1 $392
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  cell $and $393
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292"
+  wire width 1 \wrflag_cr0_cr_a_2
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
+  wire width 1 $606
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
+  cell $and $607
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $390
-    connect \B \rdflag_FAST_fast1
-    connect \Y $392
+    connect \A \fus_cr_a_ok$110
+    connect \B \fus_cu_busy_o$4
+    connect \Y $606
+  end
+  process $group_277
+    assign \wrflag_cr0_cr_a_2 1'0
+    assign \wrflag_cr0_cr_a_2 $606
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  wire width 1 $394
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  cell $and $395
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292"
+  wire width 1 \wrflag_logical0_cr_a_1
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
+  wire width 1 $608
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
+  cell $and $609
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_cu_rd__rel_o$30 [2]
-    connect \B \fu_enable [3]
-    connect \Y $394
+    connect \A \fus_cr_a_ok$111
+    connect \B \fus_cu_busy_o$13
+    connect \Y $608
+  end
+  process $group_278
+    assign \wrflag_logical0_cr_a_1 1'0
+    assign \wrflag_logical0_cr_a_1 $608
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  wire width 1 $396
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  cell $and $397
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292"
+  wire width 1 \wrflag_div0_cr_a_1
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
+  wire width 1 $610
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
+  cell $and $611
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $394
-    connect \B \rdflag_FAST_fast1
-    connect \Y $396
+    connect \A \fus_cr_a_ok$112
+    connect \B \fus_cu_busy_o$19
+    connect \Y $610
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  wire width 1 $398
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  cell $and $399
+  process $group_279
+    assign \wrflag_div0_cr_a_1 1'0
+    assign \wrflag_div0_cr_a_1 $610
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292"
+  wire width 1 \wrflag_mul0_cr_a_1
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
+  wire width 1 $612
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
+  cell $and $613
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_cu_rd__rel_o$36 [2]
-    connect \B \fu_enable [5]
-    connect \Y $398
+    connect \A \fus_cr_a_ok$113
+    connect \B \fus_cu_busy_o$22
+    connect \Y $612
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  wire width 1 $400
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  cell $and $401
+  process $group_280
+    assign \wrflag_mul0_cr_a_1 1'0
+    assign \wrflag_mul0_cr_a_1 $612
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292"
+  wire width 1 \wrflag_shiftrot0_cr_a_1
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
+  wire width 1 $614
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
+  cell $and $615
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $398
-    connect \B \rdflag_FAST_fast1
-    connect \Y $400
+    connect \A \fus_cr_a_ok$114
+    connect \B \fus_cu_busy_o$25
+    connect \Y $614
   end
-  process $group_209
-    assign \rdpick_FAST_fast1_i 3'000
-    assign \rdpick_FAST_fast1_i [0] $392
-    assign \rdpick_FAST_fast1_i [1] $396
-    assign \rdpick_FAST_fast1_i [2] $400
+  process $group_281
+    assign \wrflag_shiftrot0_cr_a_1 1'0
+    assign \wrflag_shiftrot0_cr_a_1 $614
     sync init
   end
-  process $group_210
-    assign \fus_src1_i$66 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \fus_src1_i$66 \fast_src1__data_o
-    sync init
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+  wire width 4 $616
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+  cell $or $617
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 4
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 4
+    parameter \Y_WIDTH 4
+    connect \A \fus_dest3_o
+    connect \B \fus_dest2_o$116
+    connect \Y $616
   end
-  process $group_211
-    assign \fus_src3_i$67 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \fus_src3_i$67 \fast_src1__data_o
-    sync init
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+  wire width 4 $618
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+  cell $or $619
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 4
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 4
+    parameter \Y_WIDTH 4
+    connect \A \fus_dest2_o$115
+    connect \B $616
+    connect \Y $618
   end
-  process $group_212
-    assign \fus_src3_i$68 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \fus_src3_i$68 \fast_src1__data_o
-    sync init
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+  wire width 4 $620
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+  cell $or $621
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 4
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 4
+    parameter \Y_WIDTH 4
+    connect \A \fus_dest2_o$118
+    connect \B \fus_dest2_o$119
+    connect \Y $620
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212"
-  wire width 1 \rdflag_FAST_fast2
-  process $group_213
-    assign \rdflag_FAST_fast2 1'0
-    assign \rdflag_FAST_fast2 \pdecode2_fast2_ok
-    sync init
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+  wire width 4 $622
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+  cell $or $623
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 4
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 4
+    parameter \Y_WIDTH 4
+    connect \A \fus_dest2_o$117
+    connect \B $620
+    connect \Y $622
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:104"
-  wire width 8 $402
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:104"
-  cell $sshl $403
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+  wire width 4 $624
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+  cell $or $625
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
+    parameter \A_WIDTH 4
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 3
-    parameter \Y_WIDTH 8
-    connect \A 1'1
-    connect \B \pdecode2_fast2
-    connect \Y $402
+    parameter \B_WIDTH 4
+    parameter \Y_WIDTH 4
+    connect \A $618
+    connect \B $622
+    connect \Y $624
   end
-  process $group_214
-    assign \fast_src2__ren 8'00000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-    switch { \rdpick_FAST_fast2_en_o }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
+  process $group_282
+    assign \cr_data_i 4'0000
+    assign \cr_data_i $624
+    sync init
+  end
+  process $group_283
+    assign \xer_wen 3'000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279"
+    switch { \wrpick_XER_xer_ca_en_o }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279"
       case 1'1
-        assign \fast_src2__ren $402
+        assign \xer_wen 3'010
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
+      case
+        assign \xer_wen 3'000
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  wire width 1 $404
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  cell $and $405
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292"
+  wire width 1 \wrflag_alu0_xer_ca_2
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
+  wire width 1 $626
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
+  cell $and $627
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_cu_rd__rel_o$61 [1]
-    connect \B \fu_enable [2]
-    connect \Y $404
+    connect \A \fus_xer_ca_ok
+    connect \B \fus_cu_busy_o
+    connect \Y $626
+  end
+  process $group_284
+    assign \wrflag_alu0_xer_ca_2 1'0
+    assign \wrflag_alu0_xer_ca_2 $626
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  wire width 1 $406
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  cell $and $407
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+  wire width 1 $628
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+  cell $and $629
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $404
-    connect \B \rdflag_FAST_fast2
-    connect \Y $406
+    connect \A \fus_cu_wr__rel_o [2]
+    connect \B \fu_enable [0]
+    connect \Y $628
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  wire width 1 $408
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  cell $and $409
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+  wire width 1 $630
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+  cell $and $631
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_cu_rd__rel_o$30 [3]
-    connect \B \fu_enable [3]
-    connect \Y $408
+    connect \A \fus_cu_wr__rel_o$87 [2]
+    connect \B \fu_enable [4]
+    connect \Y $630
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  wire width 1 $410
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  cell $and $411
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+  wire width 1 $632
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+  cell $and $633
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $408
-    connect \B \rdflag_FAST_fast2
-    connect \Y $410
-  end
-  process $group_215
-    assign \rdpick_FAST_fast2_i 2'00
-    assign \rdpick_FAST_fast2_i [0] $406
-    assign \rdpick_FAST_fast2_i [1] $410
-    sync init
-  end
-  process $group_216
-    assign \fus_src2_i$69 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \fus_src2_i$69 \fast_src2__data_o
-    sync init
-  end
-  process $group_217
-    assign \fus_src4_i$70 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \fus_src4_i$70 \fast_src2__data_o
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:212"
-  wire width 1 \rdflag_SPR_spr1
-  process $group_218
-    assign \rdflag_SPR_spr1 1'0
-    assign \rdflag_SPR_spr1 \pdecode2_spr1_ok
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-  end
-  process $group_219
-    assign \spr_src__ren 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-    switch { \rdpick_SPR_spr1_en_o }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:226"
-      case 1'1
-        assign \spr_src__ren \pdecode2_spr1 [0]
-    end
-    sync init
+    connect \A \fus_cu_wr__rel_o$90 [5]
+    connect \B \fu_enable [5]
+    connect \Y $632
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  wire width 1 $412
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  cell $and $413
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+  wire width 1 $634
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+  cell $and $635
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_cu_rd__rel_o$36 [1]
-    connect \B \fu_enable [5]
-    connect \Y $412
+    connect \A \fus_cu_wr__rel_o$99 [2]
+    connect \B \fu_enable [8]
+    connect \Y $634
+  end
+  process $group_285
+    assign \wrpick_XER_xer_ca_i 4'0000
+    assign \wrpick_XER_xer_ca_i [0] $628
+    assign \wrpick_XER_xer_ca_i [1] $630
+    assign \wrpick_XER_xer_ca_i [2] $632
+    assign \wrpick_XER_xer_ca_i [3] $634
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  wire width 1 $414
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:236"
-  cell $and $415
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292"
+  wire width 1 \wrflag_logical0_xer_ca_2
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
+  wire width 1 $636
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
+  cell $and $637
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $412
-    connect \B \rdflag_SPR_spr1
-    connect \Y $414
-  end
-  process $group_220
-    assign \rdpick_SPR_spr1_i 1'0
-    assign \rdpick_SPR_spr1_i $414
-    sync init
+    connect \A \fus_xer_ca_ok$120
+    connect \B \fus_cu_busy_o$13
+    connect \Y $636
   end
-  process $group_221
-    assign \fus_src2_i$71 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \fus_src2_i$71 \spr_src__data_o
+  process $group_286
+    assign \wrflag_logical0_xer_ca_2 1'0
+    assign \wrflag_logical0_xer_ca_2 $636
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:125"
-  wire width 32 $416
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:125"
-  cell $sshl $417
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292"
+  wire width 1 \wrflag_spr0_xer_ca_5
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
+  wire width 1 $638
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
+  cell $and $639
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 5
-    parameter \Y_WIDTH 32
-    connect \A 1'1
-    connect \B \pdecode2_rego
-    connect \Y $416
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \fus_xer_ca_ok$121
+    connect \B \fus_cu_busy_o$16
+    connect \Y $638
   end
-  process $group_222
-    assign \int_wen 32'00000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289"
-    switch { \wrpick_INT_o_en_o }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289"
-      case 1'1
-        assign \int_wen $416
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291"
-      case
-        assign \int_wen 32'00000000000000000000000000000000
-    end
+  process $group_287
+    assign \wrflag_spr0_xer_ca_5 1'0
+    assign \wrflag_spr0_xer_ca_5 $638
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302"
-  wire width 1 \wrflag_alu0_o_0
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  wire width 1 $418
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  cell $and $419
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292"
+  wire width 1 \wrflag_shiftrot0_xer_ca_2
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
+  wire width 1 $640
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
+  cell $and $641
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_o_ok
-    connect \B \fus_cu_busy_o
-    connect \Y $418
+    connect \A \fus_xer_ca_ok$122
+    connect \B \fus_cu_busy_o$25
+    connect \Y $640
   end
-  process $group_223
-    assign \wrflag_alu0_o_0 1'0
-    assign \wrflag_alu0_o_0 $418
+  process $group_288
+    assign \wrflag_shiftrot0_xer_ca_2 1'0
+    assign \wrflag_shiftrot0_xer_ca_2 $640
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  wire width 1 $420
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  cell $and $421
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+  wire width 2 $642
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+  cell $or $643
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
+    parameter \A_WIDTH 2
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \fus_cu_wr__rel_o [0]
-    connect \B \fu_enable [0]
-    connect \Y $420
+    parameter \B_WIDTH 2
+    parameter \Y_WIDTH 2
+    connect \A \fus_dest3_o$123
+    connect \B \fus_dest3_o$124
+    connect \Y $642
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  wire width 1 $422
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  cell $and $423
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+  wire width 2 $644
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+  cell $or $645
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
+    parameter \A_WIDTH 2
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \fus_cu_wr__rel_o$73 [0]
-    connect \B \fu_enable [1]
-    connect \Y $422
+    parameter \B_WIDTH 2
+    parameter \Y_WIDTH 2
+    connect \A \fus_dest6_o
+    connect \B \fus_dest3_o$125
+    connect \Y $644
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+  wire width 2 $646
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+  cell $or $647
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 2
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 2
+    parameter \Y_WIDTH 2
+    connect \A $642
+    connect \B $644
+    connect \Y $646
+  end
+  process $group_289
+    assign \xer_data_i 2'00
+    assign \xer_data_i $646
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  wire width 1 $424
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  cell $and $425
+  process $group_290
+    assign \xer_wen$155 3'000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279"
+    switch { \wrpick_XER_xer_ov_en_o }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279"
+      case 1'1
+        assign \xer_wen$155 3'100
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
+      case
+        assign \xer_wen$155 3'000
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292"
+  wire width 1 \wrflag_alu0_xer_ov_3
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
+  wire width 1 $648
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
+  cell $and $649
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_cu_wr__rel_o$76 [0]
-    connect \B \fu_enable [3]
-    connect \Y $424
+    connect \A \fus_xer_ov_ok
+    connect \B \fus_cu_busy_o
+    connect \Y $648
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  wire width 1 $426
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  cell $and $427
+  process $group_291
+    assign \wrflag_alu0_xer_ov_3 1'0
+    assign \wrflag_alu0_xer_ov_3 $648
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+  wire width 1 $650
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+  cell $and $651
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_cu_wr__rel_o$79 [0]
-    connect \B \fu_enable [4]
-    connect \Y $426
+    connect \A \fus_cu_wr__rel_o [3]
+    connect \B \fu_enable [0]
+    connect \Y $650
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  wire width 1 $428
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  cell $and $429
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+  wire width 1 $652
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+  cell $and $653
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_cu_wr__rel_o$82 [0]
+    connect \A \fus_cu_wr__rel_o$90 [4]
     connect \B \fu_enable [5]
-    connect \Y $428
+    connect \Y $652
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  wire width 1 $430
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  cell $and $431
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+  wire width 1 $654
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+  cell $and $655
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_cu_wr__rel_o$85 [0]
+    connect \A \fus_cu_wr__rel_o$93 [2]
     connect \B \fu_enable [6]
-    connect \Y $430
+    connect \Y $654
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  wire width 1 $432
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  cell $and $433
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+  wire width 1 $656
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+  cell $and $657
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_cu_wr__rel_o$88 [0]
+    connect \A \fus_cu_wr__rel_o$96 [2]
     connect \B \fu_enable [7]
-    connect \Y $432
+    connect \Y $656
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  wire width 1 $434
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  cell $and $435
+  process $group_292
+    assign \wrpick_XER_xer_ov_i 4'0000
+    assign \wrpick_XER_xer_ov_i [0] $650
+    assign \wrpick_XER_xer_ov_i [1] $652
+    assign \wrpick_XER_xer_ov_i [2] $654
+    assign \wrpick_XER_xer_ov_i [3] $656
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292"
+  wire width 1 \wrflag_spr0_xer_ov_4
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
+  wire width 1 $658
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
+  cell $and $659
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_cu_wr__rel_o$90 [0]
-    connect \B \fu_enable [8]
-    connect \Y $434
+    connect \A \fus_xer_ov_ok$126
+    connect \B \fus_cu_busy_o$16
+    connect \Y $658
   end
-  process $group_224
-    assign \wrpick_INT_o_i 8'00000000
-    assign \wrpick_INT_o_i [0] $420
-    assign \wrpick_INT_o_i [1] $422
-    assign \wrpick_INT_o_i [2] $424
-    assign \wrpick_INT_o_i [3] $426
-    assign \wrpick_INT_o_i [4] $428
-    assign \wrpick_INT_o_i [5] $430
-    assign \wrpick_INT_o_i [6] $432
-    assign \wrpick_INT_o_i [7] $434
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  wire width 1 $436
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  cell $and $437
+  process $group_293
+    assign \wrflag_spr0_xer_ov_4 1'0
+    assign \wrflag_spr0_xer_ov_4 $658
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292"
+  wire width 1 \wrflag_div0_xer_ov_2
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
+  wire width 1 $660
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
+  cell $and $661
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wrpick_INT_o_o [0]
-    connect \B \wrpick_INT_o_en_o
-    connect \Y $436
+    connect \A \fus_xer_ov_ok$127
+    connect \B \fus_cu_busy_o$19
+    connect \Y $660
+  end
+  process $group_294
+    assign \wrflag_div0_xer_ov_2 1'0
+    assign \wrflag_div0_xer_ov_2 $660
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  wire width 1 $438
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  cell $and $439
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292"
+  wire width 1 \wrflag_mul0_xer_ov_2
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
+  wire width 1 $662
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
+  cell $and $663
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wrpick_CR_cr_a_o [0]
-    connect \B \wrpick_CR_cr_a_en_o
-    connect \Y $438
+    connect \A \fus_xer_ov_ok$128
+    connect \B \fus_cu_busy_o$22
+    connect \Y $662
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  wire width 1 $440
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  cell $and $441
+  process $group_295
+    assign \wrflag_mul0_xer_ov_2 1'0
+    assign \wrflag_mul0_xer_ov_2 $662
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+  wire width 2 $664
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+  cell $or $665
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
+    parameter \A_WIDTH 2
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \wrpick_XER_xer_ca_o [0]
-    connect \B \wrpick_XER_xer_ca_en_o
-    connect \Y $440
+    parameter \B_WIDTH 2
+    parameter \Y_WIDTH 2
+    connect \A \fus_dest4_o
+    connect \B \fus_dest5_o
+    connect \Y $664
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  wire width 1 $442
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  cell $and $443
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+  wire width 2 $666
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+  cell $or $667
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
+    parameter \A_WIDTH 2
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \wrpick_XER_xer_ov_o [0]
-    connect \B \wrpick_XER_xer_ov_en_o
-    connect \Y $442
+    parameter \B_WIDTH 2
+    parameter \Y_WIDTH 2
+    connect \A \fus_dest3_o$129
+    connect \B \fus_dest3_o$130
+    connect \Y $666
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  wire width 1 $444
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  cell $and $445
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+  wire width 2 $668
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+  cell $or $669
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
+    parameter \A_WIDTH 2
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \wrpick_XER_xer_so_o [0]
-    connect \B \wrpick_XER_xer_so_en_o
-    connect \Y $444
+    parameter \B_WIDTH 2
+    parameter \Y_WIDTH 2
+    connect \A $664
+    connect \B $666
+    connect \Y $668
   end
-  process $group_225
-    assign \fus_cu_wr__go_i 5'00000
-    assign \fus_cu_wr__go_i [0] $436
-    assign \fus_cu_wr__go_i [1] $438
-    assign \fus_cu_wr__go_i [2] $440
-    assign \fus_cu_wr__go_i [3] $442
-    assign \fus_cu_wr__go_i [4] $444
+  process $group_296
+    assign \xer_data_i$156 2'00
+    assign \xer_data_i$156 $668
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302"
-  wire width 1 \wrflag_cr0_o_0
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  wire width 1 $446
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  cell $and $447
+  process $group_297
+    assign \xer_wen$157 3'000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279"
+    switch { \wrpick_XER_xer_so_en_o }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279"
+      case 1'1
+        assign \xer_wen$157 3'001
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
+      case
+        assign \xer_wen$157 3'000
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292"
+  wire width 1 \wrflag_alu0_xer_so_4
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
+  wire width 1 $670
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
+  cell $and $671
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_o_ok$72
-    connect \B \fus_cu_busy_o$4
-    connect \Y $446
+    connect \A \fus_xer_so_ok
+    connect \B \fus_cu_busy_o
+    connect \Y $670
   end
-  process $group_226
-    assign \wrflag_cr0_o_0 1'0
-    assign \wrflag_cr0_o_0 $446
+  process $group_298
+    assign \wrflag_alu0_xer_so_4 1'0
+    assign \wrflag_alu0_xer_so_4 $670
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  wire width 1 $448
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  cell $and $449
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+  wire width 1 $672
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+  cell $and $673
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wrpick_INT_o_o [1]
-    connect \B \wrpick_INT_o_en_o
-    connect \Y $448
+    connect \A \fus_cu_wr__rel_o [4]
+    connect \B \fu_enable [0]
+    connect \Y $672
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  wire width 1 $450
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  cell $and $451
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+  wire width 1 $674
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+  cell $and $675
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wrpick_CR_full_cr_o
-    connect \B \wrpick_CR_full_cr_en_o
-    connect \Y $450
+    connect \A \fus_cu_wr__rel_o$90 [3]
+    connect \B \fu_enable [5]
+    connect \Y $674
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  wire width 1 $452
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  cell $and $453
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+  wire width 1 $676
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+  cell $and $677
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wrpick_CR_cr_a_o [1]
-    connect \B \wrpick_CR_cr_a_en_o
-    connect \Y $452
-  end
-  process $group_227
-    assign \fus_cu_wr__go_i$74 3'000
-    assign \fus_cu_wr__go_i$74 [0] $448
-    assign \fus_cu_wr__go_i$74 [1] $450
-    assign \fus_cu_wr__go_i$74 [2] $452
-    sync init
+    connect \A \fus_cu_wr__rel_o$93 [3]
+    connect \B \fu_enable [6]
+    connect \Y $676
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302"
-  wire width 1 \wrflag_trap0_o_0
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  wire width 1 $454
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  cell $and $455
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+  wire width 1 $678
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+  cell $and $679
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_o_ok$75
-    connect \B \fus_cu_busy_o$10
-    connect \Y $454
+    connect \A \fus_cu_wr__rel_o$96 [3]
+    connect \B \fu_enable [7]
+    connect \Y $678
   end
-  process $group_228
-    assign \wrflag_trap0_o_0 1'0
-    assign \wrflag_trap0_o_0 $454
+  process $group_299
+    assign \wrpick_XER_xer_so_i 4'0000
+    assign \wrpick_XER_xer_so_i [0] $672
+    assign \wrpick_XER_xer_so_i [1] $674
+    assign \wrpick_XER_xer_so_i [2] $676
+    assign \wrpick_XER_xer_so_i [3] $678
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  wire width 1 $456
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  cell $and $457
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292"
+  wire width 1 \wrflag_spr0_xer_so_3
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
+  wire width 1 $680
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
+  cell $and $681
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wrpick_INT_o_o [2]
-    connect \B \wrpick_INT_o_en_o
-    connect \Y $456
+    connect \A \fus_xer_so_ok$131
+    connect \B \fus_cu_busy_o$16
+    connect \Y $680
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  wire width 1 $458
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  cell $and $459
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \wrpick_FAST_fast1_o [1]
-    connect \B \wrpick_FAST_fast1_en_o
-    connect \Y $458
+  process $group_300
+    assign \wrflag_spr0_xer_so_3 1'0
+    assign \wrflag_spr0_xer_so_3 $680
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  wire width 1 $460
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  cell $and $461
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292"
+  wire width 1 \wrflag_div0_xer_so_3
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
+  wire width 1 $682
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
+  cell $and $683
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wrpick_FAST_fast2_o [1]
-    connect \B \wrpick_FAST_fast2_en_o
-    connect \Y $460
+    connect \A \fus_xer_so_ok$132
+    connect \B \fus_cu_busy_o$19
+    connect \Y $682
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  wire width 1 $462
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  cell $and $463
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \wrpick_FAST_nia_o [1]
-    connect \B \wrpick_FAST_nia_en_o
-    connect \Y $462
+  process $group_301
+    assign \wrflag_div0_xer_so_3 1'0
+    assign \wrflag_div0_xer_so_3 $682
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  wire width 1 $464
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  cell $and $465
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292"
+  wire width 1 \wrflag_mul0_xer_so_3
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
+  wire width 1 $684
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
+  cell $and $685
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wrpick_FAST_msr_o
-    connect \B \wrpick_FAST_msr_en_o
-    connect \Y $464
+    connect \A \fus_xer_so_ok$133
+    connect \B \fus_cu_busy_o$22
+    connect \Y $684
   end
-  process $group_229
-    assign \fus_cu_wr__go_i$77 5'00000
-    assign \fus_cu_wr__go_i$77 [0] $456
-    assign \fus_cu_wr__go_i$77 [1] $458
-    assign \fus_cu_wr__go_i$77 [2] $460
-    assign \fus_cu_wr__go_i$77 [3] $462
-    assign \fus_cu_wr__go_i$77 [4] $464
+  process $group_302
+    assign \wrflag_mul0_xer_so_3 1'0
+    assign \wrflag_mul0_xer_so_3 $684
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302"
-  wire width 1 \wrflag_logical0_o_0
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  wire width 1 $466
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  cell $and $467
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+  wire width 2 $686
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+  wire width 1 $687
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+  cell $or $688
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_o_ok$78
-    connect \B \fus_cu_busy_o$13
-    connect \Y $466
-  end
-  process $group_230
-    assign \wrflag_logical0_o_0 1'0
-    assign \wrflag_logical0_o_0 $466
-    sync init
+    connect \A \fus_dest5_o$134
+    connect \B \fus_dest4_o$135
+    connect \Y $687
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  wire width 1 $468
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  cell $and $469
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+  wire width 1 $689
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+  cell $or $690
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wrpick_INT_o_o [3]
-    connect \B \wrpick_INT_o_en_o
-    connect \Y $468
+    connect \A \fus_dest4_o$136
+    connect \B \fus_dest4_o$137
+    connect \Y $689
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  wire width 1 $470
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  cell $and $471
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+  wire width 1 $691
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+  cell $or $692
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wrpick_CR_cr_a_o [2]
-    connect \B \wrpick_CR_cr_a_en_o
-    connect \Y $470
+    connect \A $687
+    connect \B $689
+    connect \Y $691
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  wire width 1 $472
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  cell $and $473
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+  cell $pos $693
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \wrpick_XER_xer_ca_o [1]
-    connect \B \wrpick_XER_xer_ca_en_o
-    connect \Y $472
+    parameter \Y_WIDTH 2
+    connect \A $691
+    connect \Y $686
   end
-  process $group_231
-    assign \fus_cu_wr__go_i$80 3'000
-    assign \fus_cu_wr__go_i$80 [0] $468
-    assign \fus_cu_wr__go_i$80 [1] $470
-    assign \fus_cu_wr__go_i$80 [2] $472
+  process $group_303
+    assign \xer_data_i$158 2'00
+    assign \xer_data_i$158 $686
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302"
-  wire width 1 \wrflag_spr0_o_0
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  wire width 1 $474
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  cell $and $475
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:170"
+  wire width 8 $694
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:170"
+  cell $sshl $695
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \fus_o_ok$81
-    connect \B \fus_cu_busy_o$16
-    connect \Y $474
+    parameter \B_WIDTH 3
+    parameter \Y_WIDTH 8
+    connect \A 1'1
+    connect \B \pdecode2_fasto1
+    connect \Y $694
   end
-  process $group_232
-    assign \wrflag_spr0_o_0 1'0
-    assign \wrflag_spr0_o_0 $474
+  process $group_304
+    assign \fast_wen 8'00000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279"
+    switch { \wrpick_FAST_fast1_en_o }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279"
+      case 1'1
+        assign \fast_wen $694
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
+      case
+        assign \fast_wen 8'00000000
+    end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  wire width 1 $476
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  cell $and $477
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \wrpick_INT_o_o [4]
-    connect \B \wrpick_INT_o_en_o
-    connect \Y $476
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  wire width 1 $478
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  cell $and $479
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292"
+  wire width 1 \wrflag_branch0_fast1_0
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
+  wire width 1 $696
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
+  cell $and $697
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wrpick_XER_xer_ca_o [2]
-    connect \B \wrpick_XER_xer_ca_en_o
-    connect \Y $478
+    connect \A \fus_fast1_ok
+    connect \B \fus_cu_busy_o$7
+    connect \Y $696
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  wire width 1 $480
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  cell $and $481
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \wrpick_XER_xer_ov_o [1]
-    connect \B \wrpick_XER_xer_ov_en_o
-    connect \Y $480
+  process $group_305
+    assign \wrflag_branch0_fast1_0 1'0
+    assign \wrflag_branch0_fast1_0 $696
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  wire width 1 $482
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  cell $and $483
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+  wire width 1 $698
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+  cell $and $699
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wrpick_XER_xer_so_o [1]
-    connect \B \wrpick_XER_xer_so_en_o
-    connect \Y $482
+    connect \A \fus_cu_wr__rel_o$138 [0]
+    connect \B \fu_enable [2]
+    connect \Y $698
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  wire width 1 $484
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  cell $and $485
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+  wire width 1 $700
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+  cell $and $701
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wrpick_FAST_fast1_o [2]
-    connect \B \wrpick_FAST_fast1_en_o
-    connect \Y $484
+    connect \A \fus_cu_wr__rel_o$84 [1]
+    connect \B \fu_enable [3]
+    connect \Y $700
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  wire width 1 $486
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  cell $and $487
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+  wire width 1 $702
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+  cell $and $703
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wrpick_SPR_spr1_o
-    connect \B \wrpick_SPR_spr1_en_o
-    connect \Y $486
+    connect \A \fus_cu_wr__rel_o$90 [2]
+    connect \B \fu_enable [5]
+    connect \Y $702
   end
-  process $group_233
-    assign \fus_cu_wr__go_i$83 6'000000
-    assign \fus_cu_wr__go_i$83 [0] $476
-    assign \fus_cu_wr__go_i$83 [5] $478
-    assign \fus_cu_wr__go_i$83 [4] $480
-    assign \fus_cu_wr__go_i$83 [3] $482
-    assign \fus_cu_wr__go_i$83 [2] $484
-    assign \fus_cu_wr__go_i$83 [1] $486
+  process $group_306
+    assign \wrpick_FAST_fast1_i 3'000
+    assign \wrpick_FAST_fast1_i [0] $698
+    assign \wrpick_FAST_fast1_i [1] $700
+    assign \wrpick_FAST_fast1_i [2] $702
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302"
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-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  wire width 1 $488
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  cell $and $489
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299"
+  wire width 1 $704
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299"
+  cell $and $705
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_o_ok$84
-    connect \B \fus_cu_busy_o$19
-    connect \Y $488
-  end
-  process $group_234
-    assign \wrflag_mul0_o_0 1'0
-    assign \wrflag_mul0_o_0 $488
-    sync init
+    connect \A \wrpick_FAST_fast1_o [0]
+    connect \B \wrpick_FAST_fast1_en_o
+    connect \Y $704
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  wire width 1 $490
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  cell $and $491
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299"
+  wire width 1 $706
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299"
+  cell $and $707
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wrpick_INT_o_o [5]
-    connect \B \wrpick_INT_o_en_o
-    connect \Y $490
+    connect \A \wrpick_FAST_fast2_o [0]
+    connect \B \wrpick_FAST_fast2_en_o
+    connect \Y $706
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  wire width 1 $492
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  cell $and $493
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299"
+  wire width 1 $708
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:299"
+  cell $and $709
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wrpick_CR_cr_a_o [3]
-    connect \B \wrpick_CR_cr_a_en_o
-    connect \Y $492
+    connect \A \wrpick_FAST_nia_o [0]
+    connect \B \wrpick_FAST_nia_en_o
+    connect \Y $708
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  wire width 1 $494
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  cell $and $495
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \wrpick_XER_xer_ov_o [2]
-    connect \B \wrpick_XER_xer_ov_en_o
-    connect \Y $494
+  process $group_307
+    assign \fus_cu_wr__go_i$139 3'000
+    assign \fus_cu_wr__go_i$139 [0] $704
+    assign \fus_cu_wr__go_i$139 [1] $706
+    assign \fus_cu_wr__go_i$139 [2] $708
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  wire width 1 $496
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  cell $and $497
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292"
+  wire width 1 \wrflag_trap0_fast1_1
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
+  wire width 1 $710
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
+  cell $and $711
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wrpick_XER_xer_so_o [2]
-    connect \B \wrpick_XER_xer_so_en_o
-    connect \Y $496
+    connect \A \fus_fast1_ok$140
+    connect \B \fus_cu_busy_o$10
+    connect \Y $710
   end
-  process $group_235
-    assign \fus_cu_wr__go_i$86 4'0000
-    assign \fus_cu_wr__go_i$86 [0] $490
-    assign \fus_cu_wr__go_i$86 [1] $492
-    assign \fus_cu_wr__go_i$86 [2] $494
-    assign \fus_cu_wr__go_i$86 [3] $496
+  process $group_308
+    assign \wrflag_trap0_fast1_1 1'0
+    assign \wrflag_trap0_fast1_1 $710
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302"
-  wire width 1 \wrflag_shiftrot0_o_0
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  wire width 1 $498
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  cell $and $499
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292"
+  wire width 1 \wrflag_spr0_fast1_2
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
+  wire width 1 $712
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
+  cell $and $713
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_o_ok$87
-    connect \B \fus_cu_busy_o$22
-    connect \Y $498
+    connect \A \fus_fast1_ok$141
+    connect \B \fus_cu_busy_o$16
+    connect \Y $712
   end
-  process $group_236
-    assign \wrflag_shiftrot0_o_0 1'0
-    assign \wrflag_shiftrot0_o_0 $498
+  process $group_309
+    assign \wrflag_spr0_fast1_2 1'0
+    assign \wrflag_spr0_fast1_2 $712
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  wire width 1 $500
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  cell $and $501
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+  wire width 64 $714
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+  cell $or $715
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
+    parameter \A_WIDTH 64
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \wrpick_INT_o_o [6]
-    connect \B \wrpick_INT_o_en_o
-    connect \Y $500
+    parameter \B_WIDTH 64
+    parameter \Y_WIDTH 64
+    connect \A \fus_dest2_o$143
+    connect \B \fus_dest3_o$144
+    connect \Y $714
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  wire width 1 $502
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  cell $and $503
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+  wire width 64 $716
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
+  cell $or $717
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
+    parameter \A_WIDTH 64
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \wrpick_CR_cr_a_o [4]
-    connect \B \wrpick_CR_cr_a_en_o
-    connect \Y $502
+    parameter \B_WIDTH 64
+    parameter \Y_WIDTH 64
+    connect \A \fus_dest1_o$142
+    connect \B $714
+    connect \Y $716
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  wire width 1 $504
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  cell $and $505
+  process $group_310
+    assign \fast_data_i 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \fast_data_i $716
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:172"
+  wire width 8 $718
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:172"
+  cell $sshl $719
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \wrpick_XER_xer_ca_o [3]
-    connect \B \wrpick_XER_xer_ca_en_o
-    connect \Y $504
+    parameter \B_WIDTH 3
+    parameter \Y_WIDTH 8
+    connect \A 1'1
+    connect \B \pdecode2_fasto2
+    connect \Y $718
   end
-  process $group_237
-    assign \fus_cu_wr__go_i$89 3'000
-    assign \fus_cu_wr__go_i$89 [0] $500
-    assign \fus_cu_wr__go_i$89 [1] $502
-    assign \fus_cu_wr__go_i$89 [2] $504
+  process $group_311
+    assign \fast_wen$159 8'00000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279"
+    switch { \wrpick_FAST_fast2_en_o }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279"
+      case 1'1
+        assign \fast_wen$159 $718
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
+      case
+        assign \fast_wen$159 8'00000000
+    end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302"
-  wire width 1 \wrflag_ldst0_o_0
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 \o_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  wire width 1 $506
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  cell $and $507
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292"
+  wire width 1 \wrflag_branch0_fast2_1
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
+  wire width 1 $720
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
+  cell $and $721
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \o_ok
-    connect \B \fus_cu_busy_o$25
-    connect \Y $506
+    connect \A \fus_fast2_ok
+    connect \B \fus_cu_busy_o$7
+    connect \Y $720
   end
-  process $group_238
-    assign \wrflag_ldst0_o_0 1'0
-    assign \wrflag_ldst0_o_0 $506
+  process $group_312
+    assign \wrflag_branch0_fast2_1 1'0
+    assign \wrflag_branch0_fast2_1 $720
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  wire width 1 $508
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  cell $and $509
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+  wire width 1 $722
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+  cell $and $723
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wrpick_INT_o_o [7]
-    connect \B \wrpick_INT_o_en_o
-    connect \Y $508
+    connect \A \fus_cu_wr__rel_o$138 [1]
+    connect \B \fu_enable [2]
+    connect \Y $722
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  wire width 1 $510
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  cell $and $511
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+  wire width 1 $724
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+  cell $and $725
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wrpick_INT_o1_o
-    connect \B \wrpick_INT_o1_en_o
-    connect \Y $510
+    connect \A \fus_cu_wr__rel_o$84 [2]
+    connect \B \fu_enable [3]
+    connect \Y $724
   end
-  process $group_239
-    assign \fus_cu_wr__go_i$91 2'00
-    assign \fus_cu_wr__go_i$91 [0] $508
-    assign \fus_cu_wr__go_i$91 [1] $510
+  process $group_313
+    assign \wrpick_FAST_fast2_i 2'00
+    assign \wrpick_FAST_fast2_i [0] $722
+    assign \wrpick_FAST_fast2_i [1] $724
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  wire width 65 $512
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  wire width 64 $513
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  cell $or $514
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 64
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 64
-    parameter \Y_WIDTH 64
-    connect \A \fus_dest1_o
-    connect \B \fus_dest1_o$92
-    connect \Y $513
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  wire width 64 $515
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  cell $or $516
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 64
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 64
-    parameter \Y_WIDTH 64
-    connect \A \fus_dest1_o$93
-    connect \B \fus_dest1_o$94
-    connect \Y $515
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  wire width 64 $517
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  cell $or $518
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292"
+  wire width 1 \wrflag_trap0_fast2_2
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
+  wire width 1 $726
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
+  cell $and $727
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 64
+    parameter \A_WIDTH 1
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 64
-    parameter \Y_WIDTH 64
-    connect \A $513
-    connect \B $515
-    connect \Y $517
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \fus_fast2_ok$145
+    connect \B \fus_cu_busy_o$10
+    connect \Y $726
+  end
+  process $group_314
+    assign \wrflag_trap0_fast2_2 1'0
+    assign \wrflag_trap0_fast2_2 $726
+    sync init
   end
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  wire width 64 $519
+  wire width 64 $728
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  cell $or $520
+  cell $or $729
     parameter \A_SIGNED 0
     parameter \A_WIDTH 64
     parameter \B_SIGNED 0
     parameter \B_WIDTH 64
     parameter \Y_WIDTH 64
-    connect \A \fus_dest1_o$95
-    connect \B \fus_dest1_o$96
-    connect \Y $519
+    connect \A \fus_dest2_o$146
+    connect \B \fus_dest3_o$147
+    connect \Y $728
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  wire width 65 $521
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  cell $or $522
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 64
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 65
-    parameter \Y_WIDTH 65
-    connect \A \fus_dest1_o$97
-    connect \B { \o_ok \fus_o }
-    connect \Y $521
+  process $group_315
+    assign \fast_data_i$160 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \fast_data_i$160 $728
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  wire width 65 $523
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  cell $or $524
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 64
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 65
-    parameter \Y_WIDTH 65
-    connect \A $519
-    connect \B $521
-    connect \Y $523
+  process $group_316
+    assign \fast_nia_wen 8'00000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279"
+    switch { \wrpick_FAST_nia_en_o }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279"
+      case 1'1
+        assign \fast_nia_wen 8'00000001
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
+      case
+        assign \fast_nia_wen 8'00000000
+    end
+    sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  wire width 65 $525
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  cell $or $526
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292"
+  wire width 1 \wrflag_branch0_nia_2
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
+  wire width 1 $730
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
+  cell $and $731
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 64
+    parameter \A_WIDTH 1
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 65
-    parameter \Y_WIDTH 65
-    connect \A $517
-    connect \B $523
-    connect \Y $525
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \fus_nia_ok
+    connect \B \fus_cu_busy_o$7
+    connect \Y $730
   end
-  connect $512 $525
-  process $group_240
-    assign \int_data_i 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \int_data_i $512 [63:0]
+  process $group_317
+    assign \wrflag_branch0_nia_2 1'0
+    assign \wrflag_branch0_nia_2 $730
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:127"
-  wire width 32 $527
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:127"
-  cell $sshl $528
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+  wire width 1 $732
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+  cell $and $733
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 5
-    parameter \Y_WIDTH 32
-    connect \A 1'1
-    connect \B \pdecode2_ea
-    connect \Y $527
-  end
-  process $group_241
-    assign \int_wen$135 32'00000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289"
-    switch { \wrpick_INT_o1_en_o }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289"
-      case 1'1
-        assign \int_wen$135 $527
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291"
-      case
-        assign \int_wen$135 32'00000000000000000000000000000000
-    end
-    sync init
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \fus_cu_wr__rel_o$138 [2]
+    connect \B \fu_enable [2]
+    connect \Y $732
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302"
-  wire width 1 \wrflag_ldst0_o1_1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
-  wire width 1 \ea_ok
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  wire width 1 $529
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  cell $and $530
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+  wire width 1 $734
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+  cell $and $735
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \ea_ok
-    connect \B \fus_cu_busy_o$25
-    connect \Y $529
+    connect \A \fus_cu_wr__rel_o$84 [3]
+    connect \B \fu_enable [3]
+    connect \Y $734
   end
-  process $group_242
-    assign \wrflag_ldst0_o1_1 1'0
-    assign \wrflag_ldst0_o1_1 $529
+  process $group_318
+    assign \wrpick_FAST_nia_i 2'00
+    assign \wrpick_FAST_nia_i [0] $732
+    assign \wrpick_FAST_nia_i [1] $734
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  wire width 1 $531
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  cell $and $532
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292"
+  wire width 1 \wrflag_trap0_nia_3
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
+  wire width 1 $736
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
+  cell $and $737
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_cu_wr__rel_o$90 [1]
-    connect \B \fu_enable [8]
-    connect \Y $531
+    connect \A \fus_nia_ok$148
+    connect \B \fus_cu_busy_o$10
+    connect \Y $736
   end
-  process $group_243
-    assign \wrpick_INT_o1_i 1'0
-    assign \wrpick_INT_o1_i $531
+  process $group_319
+    assign \wrflag_trap0_nia_3 1'0
+    assign \wrflag_trap0_nia_3 $736
     sync init
   end
-  process $group_244
-    assign \int_data_i$136 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \int_data_i$136 { \ea_ok \fus_ea } [63:0]
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+  wire width 64 $738
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
+  cell $or $739
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 64
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 64
+    parameter \Y_WIDTH 64
+    connect \A \fus_dest3_o$149
+    connect \B \fus_dest4_o$150
+    connect \Y $738
+  end
+  process $group_320
+    assign \fast_data_i$161 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \fast_data_i$161 $738
     sync init
   end
-  process $group_245
-    assign \cr_full_wr__wen 8'00000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289"
-    switch { \wrpick_CR_full_cr_en_o }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289"
+  process $group_321
+    assign \fast_wen$162 8'00000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279"
+    switch { \wrpick_FAST_msr_en_o }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279"
       case 1'1
-        assign \cr_full_wr__wen 8'11111111
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291"
+        assign \fast_wen$162 8'00000010
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
       case
-        assign \cr_full_wr__wen 8'00000000
+        assign \fast_wen$162 8'00000000
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302"
-  wire width 1 \wrflag_cr0_full_cr_1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  wire width 1 $533
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  cell $and $534
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292"
+  wire width 1 \wrflag_trap0_msr_4
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
+  wire width 1 $740
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
+  cell $and $741
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_full_cr_ok
-    connect \B \fus_cu_busy_o$4
-    connect \Y $533
+    connect \A \fus_msr_ok
+    connect \B \fus_cu_busy_o$10
+    connect \Y $740
   end
-  process $group_246
-    assign \wrflag_cr0_full_cr_1 1'0
-    assign \wrflag_cr0_full_cr_1 $533
+  process $group_322
+    assign \wrflag_trap0_msr_4 1'0
+    assign \wrflag_trap0_msr_4 $740
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  wire width 1 $535
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  cell $and $536
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+  wire width 1 $742
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+  cell $and $743
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_cu_wr__rel_o$73 [1]
-    connect \B \fu_enable [1]
-    connect \Y $535
+    connect \A \fus_cu_wr__rel_o$84 [4]
+    connect \B \fu_enable [3]
+    connect \Y $742
   end
-  process $group_247
-    assign \wrpick_CR_full_cr_i 1'0
-    assign \wrpick_CR_full_cr_i $535
+  process $group_323
+    assign \wrpick_FAST_msr_i 1'0
+    assign \wrpick_FAST_msr_i $742
     sync init
   end
-  process $group_248
-    assign \cr_full_wr__data_i 32'00000000000000000000000000000000
-    assign \cr_full_wr__data_i \fus_dest2_o
+  process $group_324
+    assign \fast_data_i$163 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \fast_data_i$163 \fus_dest5_o$151
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:137"
-  wire width 16 $537
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:137"
-  wire width 4 $538
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:137"
-  cell $sub $539
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 3
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 3
-    parameter \Y_WIDTH 4
-    connect \A 3'111
-    connect \B \pdecode2_cr_out
-    connect \Y $538
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:137"
-  wire width 16 $540
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:137"
-  cell $sshl $541
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 4
-    parameter \Y_WIDTH 16
-    connect \A 1'1
-    connect \B $538
-    connect \Y $540
-  end
-  connect $537 $540
-  process $group_249
-    assign \cr_wen 8'00000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289"
-    switch { \wrpick_CR_cr_a_en_o }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289"
+  process $group_325
+    assign \spr_dest__wen 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279"
+    switch { \wrpick_SPR_spr1_en_o }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:279"
       case 1'1
-        assign \cr_wen $537 [7:0]
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291"
+        assign \spr_dest__wen \pdecode2_spro [0]
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:281"
       case
-        assign \cr_wen 8'00000000
+        assign \spr_dest__wen 1'0
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302"
-  wire width 1 \wrflag_alu0_cr_a_1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  wire width 1 $542
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  cell $and $543
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:292"
+  wire width 1 \wrflag_spr0_spr1_1
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
+  wire width 1 $744
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:293"
+  cell $and $745
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_cr_a_ok
-    connect \B \fus_cu_busy_o
-    connect \Y $542
+    connect \A \fus_spr1_ok
+    connect \B \fus_cu_busy_o$16
+    connect \Y $744
   end
-  process $group_250
-    assign \wrflag_alu0_cr_a_1 1'0
-    assign \wrflag_alu0_cr_a_1 $542
+  process $group_326
+    assign \wrflag_spr0_spr1_1 1'0
+    assign \wrflag_spr0_spr1_1 $744
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  wire width 1 $544
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  cell $and $545
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+  wire width 1 $746
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:297"
+  cell $and $747
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_cu_wr__rel_o [1]
-    connect \B \fu_enable [0]
-    connect \Y $544
+    connect \A \fus_cu_wr__rel_o$90 [1]
+    connect \B \fu_enable [5]
+    connect \Y $746
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  wire width 1 $546
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  cell $and $547
+  process $group_327
+    assign \wrpick_SPR_spr1_i 1'0
+    assign \wrpick_SPR_spr1_i $746
+    sync init
+  end
+  process $group_328
+    assign \spr_dest__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \spr_dest__data_i \fus_dest2_o$152
+    sync init
+  end
+  process $group_329
+    assign \coresync_rst 1'0
+    assign \coresync_rst \core_reset_i
+    sync init
+  end
+  connect \o_ok 1'0
+  connect \ea_ok 1'0
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.imem"
+module \imem
+  attribute \src "simple/issuer.py:86"
+  wire width 1 input 0 \clk
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:24"
+  wire width 48 input 1 \a_pc_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:26"
+  wire width 1 input 2 \a_valid_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:28"
+  wire width 1 input 3 \f_valid_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:32"
+  wire width 1 output 4 \f_busy_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:33"
+  wire width 64 output 5 \f_instr_o
+  attribute \src "simple/issuer.py:86"
+  wire width 1 input 6 \rst
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
+  wire width 1 output 7 \ibus__cyc
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
+  wire width 1 \ibus__cyc$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
+  wire width 1 input 8 \ibus__ack
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
+  wire width 1 input 9 \ibus__err
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
+  wire width 1 output 10 \ibus__stb
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
+  wire width 1 \ibus__stb$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
+  wire width 8 output 11 \ibus__sel
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
+  wire width 8 \ibus__sel$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
+  wire width 64 input 12 \ibus__dat_r
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
+  wire width 45 output 13 \ibus__adr
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
+  wire width 45 \ibus__adr$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68"
+  wire width 1 $1
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:25"
+  wire width 1 \a_stall_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68"
+  cell $not $2
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_cu_wr__rel_o$73 [2]
-    connect \B \fu_enable [1]
-    connect \Y $546
+    connect \A \a_stall_i
+    connect \Y $1
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  wire width 1 $548
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  cell $and $549
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68"
+  wire width 1 $3
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68"
+  cell $and $4
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_cu_wr__rel_o$79 [1]
-    connect \B \fu_enable [4]
-    connect \Y $548
+    connect \A \a_valid_i
+    connect \B $1
+    connect \Y $3
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  wire width 1 $550
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  cell $and $551
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61"
+  wire width 1 $5
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61"
+  cell $or $6
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_cu_wr__rel_o$85 [1]
-    connect \B \fu_enable [6]
-    connect \Y $550
+    connect \A \ibus__ack
+    connect \B \ibus__err
+    connect \Y $5
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  wire width 1 $552
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  cell $and $553
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61"
+  wire width 1 $7
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61"
+  cell $not $8
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_cu_wr__rel_o$88 [1]
-    connect \B \fu_enable [7]
-    connect \Y $552
-  end
-  process $group_251
-    assign \wrpick_CR_cr_a_i 5'00000
-    assign \wrpick_CR_cr_a_i [0] $544
-    assign \wrpick_CR_cr_a_i [1] $546
-    assign \wrpick_CR_cr_a_i [2] $548
-    assign \wrpick_CR_cr_a_i [3] $550
-    assign \wrpick_CR_cr_a_i [4] $552
-    sync init
+    connect \A \f_valid_i
+    connect \Y $7
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302"
-  wire width 1 \wrflag_cr0_cr_a_2
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  wire width 1 $554
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  cell $and $555
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61"
+  wire width 1 $9
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61"
+  cell $or $10
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_cr_a_ok$98
-    connect \B \fus_cu_busy_o$4
-    connect \Y $554
+    connect \A $5
+    connect \B $7
+    connect \Y $9
   end
-  process $group_252
-    assign \wrflag_cr0_cr_a_2 1'0
-    assign \wrflag_cr0_cr_a_2 $554
+  process $group_0
+    assign \ibus__cyc$next \ibus__cyc
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:60"
+    switch { $3 \ibus__cyc }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:60"
+      case 2'-1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61"
+        switch { $9 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61"
+          case 1'1
+            assign \ibus__cyc$next 1'0
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68"
+      case 2'1-
+        assign \ibus__cyc$next 1'1
+    end
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \rst
+      case 1'1
+        assign \ibus__cyc$next 1'0
+    end
     sync init
+      update \ibus__cyc 1'0
+    sync posedge \clk
+      update \ibus__cyc \ibus__cyc$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302"
-  wire width 1 \wrflag_logical0_cr_a_1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  wire width 1 $556
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  cell $and $557
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68"
+  wire width 1 $11
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68"
+  cell $not $12
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_cr_a_ok$99
-    connect \B \fus_cu_busy_o$13
-    connect \Y $556
-  end
-  process $group_253
-    assign \wrflag_logical0_cr_a_1 1'0
-    assign \wrflag_logical0_cr_a_1 $556
-    sync init
+    connect \A \a_stall_i
+    connect \Y $11
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302"
-  wire width 1 \wrflag_mul0_cr_a_1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  wire width 1 $558
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  cell $and $559
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68"
+  wire width 1 $13
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68"
+  cell $and $14
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_cr_a_ok$100
-    connect \B \fus_cu_busy_o$19
-    connect \Y $558
-  end
-  process $group_254
-    assign \wrflag_mul0_cr_a_1 1'0
-    assign \wrflag_mul0_cr_a_1 $558
-    sync init
+    connect \A \a_valid_i
+    connect \B $11
+    connect \Y $13
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302"
-  wire width 1 \wrflag_shiftrot0_cr_a_1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  wire width 1 $560
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  cell $and $561
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61"
+  wire width 1 $15
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61"
+  cell $or $16
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_cr_a_ok$101
-    connect \B \fus_cu_busy_o$22
-    connect \Y $560
-  end
-  process $group_255
-    assign \wrflag_shiftrot0_cr_a_1 1'0
-    assign \wrflag_shiftrot0_cr_a_1 $560
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  wire width 4 $562
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  cell $or $563
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 4
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 4
-    parameter \Y_WIDTH 4
-    connect \A \fus_dest2_o$102
-    connect \B \fus_dest3_o
-    connect \Y $562
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  wire width 4 $564
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  cell $or $565
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 4
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 4
-    parameter \Y_WIDTH 4
-    connect \A \fus_dest2_o$104
-    connect \B \fus_dest2_o$105
-    connect \Y $564
+    connect \A \ibus__ack
+    connect \B \ibus__err
+    connect \Y $15
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  wire width 4 $566
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  cell $or $567
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61"
+  wire width 1 $17
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61"
+  cell $not $18
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 4
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 4
-    parameter \Y_WIDTH 4
-    connect \A \fus_dest2_o$103
-    connect \B $564
-    connect \Y $566
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \f_valid_i
+    connect \Y $17
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  wire width 4 $568
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  cell $or $569
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61"
+  wire width 1 $19
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61"
+  cell $or $20
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 4
+    parameter \A_WIDTH 1
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 4
-    parameter \Y_WIDTH 4
-    connect \A $562
-    connect \B $566
-    connect \Y $568
-  end
-  process $group_256
-    assign \cr_data_i 4'0000
-    assign \cr_data_i $568
-    sync init
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $15
+    connect \B $17
+    connect \Y $19
   end
-  process $group_257
-    assign \xer_wen 3'000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289"
-    switch { \wrpick_XER_xer_ca_en_o }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289"
+  process $group_1
+    assign \ibus__stb$next \ibus__stb
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:60"
+    switch { $13 \ibus__cyc }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:60"
+      case 2'-1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61"
+        switch { $19 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61"
+          case 1'1
+            assign \ibus__stb$next 1'0
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68"
+      case 2'1-
+        assign \ibus__stb$next 1'1
+    end
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \rst
       case 1'1
-        assign \xer_wen 3'010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291"
-      case
-        assign \xer_wen 3'000
+        assign \ibus__stb$next 1'0
     end
     sync init
+      update \ibus__stb 1'0
+    sync posedge \clk
+      update \ibus__stb \ibus__stb$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302"
-  wire width 1 \wrflag_alu0_xer_ca_2
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  wire width 1 $570
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  cell $and $571
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68"
+  wire width 1 $21
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68"
+  cell $not $22
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_xer_ca_ok
-    connect \B \fus_cu_busy_o
-    connect \Y $570
-  end
-  process $group_258
-    assign \wrflag_alu0_xer_ca_2 1'0
-    assign \wrflag_alu0_xer_ca_2 $570
-    sync init
+    connect \A \a_stall_i
+    connect \Y $21
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  wire width 1 $572
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  cell $and $573
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68"
+  wire width 1 $23
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68"
+  cell $and $24
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_cu_wr__rel_o [2]
-    connect \B \fu_enable [0]
-    connect \Y $572
+    connect \A \a_valid_i
+    connect \B $21
+    connect \Y $23
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  wire width 1 $574
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  cell $and $575
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61"
+  wire width 1 $25
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61"
+  cell $or $26
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_cu_wr__rel_o$79 [2]
-    connect \B \fu_enable [4]
-    connect \Y $574
+    connect \A \ibus__ack
+    connect \B \ibus__err
+    connect \Y $25
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  wire width 1 $576
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  cell $and $577
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61"
+  wire width 1 $27
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61"
+  cell $not $28
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_cu_wr__rel_o$82 [5]
-    connect \B \fu_enable [5]
-    connect \Y $576
+    connect \A \f_valid_i
+    connect \Y $27
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  wire width 1 $578
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  cell $and $579
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61"
+  wire width 1 $29
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61"
+  cell $or $30
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_cu_wr__rel_o$88 [2]
-    connect \B \fu_enable [7]
-    connect \Y $578
+    connect \A $25
+    connect \B $27
+    connect \Y $29
   end
-  process $group_259
-    assign \wrpick_XER_xer_ca_i 4'0000
-    assign \wrpick_XER_xer_ca_i [0] $572
-    assign \wrpick_XER_xer_ca_i [1] $574
-    assign \wrpick_XER_xer_ca_i [2] $576
-    assign \wrpick_XER_xer_ca_i [3] $578
+  process $group_2
+    assign \ibus__sel$next \ibus__sel
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:60"
+    switch { $23 \ibus__cyc }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:60"
+      case 2'-1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61"
+        switch { $29 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61"
+          case 1'1
+            assign \ibus__sel$next 8'00000000
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68"
+      case 2'1-
+        assign \ibus__sel$next 8'11111111
+    end
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \rst
+      case 1'1
+        assign \ibus__sel$next 8'00000000
+    end
     sync init
+      update \ibus__sel 8'00000000
+    sync posedge \clk
+      update \ibus__sel \ibus__sel$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302"
-  wire width 1 \wrflag_logical0_xer_ca_2
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  wire width 1 $580
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  cell $and $581
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:59"
+  wire width 64 \ibus_rdata
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:59"
+  wire width 64 \ibus_rdata$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68"
+  wire width 1 $31
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68"
+  cell $not $32
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_xer_ca_ok$106
-    connect \B \fus_cu_busy_o$13
-    connect \Y $580
-  end
-  process $group_260
-    assign \wrflag_logical0_xer_ca_2 1'0
-    assign \wrflag_logical0_xer_ca_2 $580
-    sync init
+    connect \A \a_stall_i
+    connect \Y $31
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302"
-  wire width 1 \wrflag_spr0_xer_ca_5
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  wire width 1 $582
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  cell $and $583
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68"
+  wire width 1 $33
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68"
+  cell $and $34
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_xer_ca_ok$107
-    connect \B \fus_cu_busy_o$16
-    connect \Y $582
-  end
-  process $group_261
-    assign \wrflag_spr0_xer_ca_5 1'0
-    assign \wrflag_spr0_xer_ca_5 $582
-    sync init
+    connect \A \a_valid_i
+    connect \B $31
+    connect \Y $33
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302"
-  wire width 1 \wrflag_shiftrot0_xer_ca_2
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  wire width 1 $584
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  cell $and $585
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61"
+  wire width 1 $35
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61"
+  cell $or $36
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_xer_ca_ok$108
-    connect \B \fus_cu_busy_o$22
-    connect \Y $584
-  end
-  process $group_262
-    assign \wrflag_shiftrot0_xer_ca_2 1'0
-    assign \wrflag_shiftrot0_xer_ca_2 $584
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  wire width 2 $586
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  cell $or $587
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 2
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 2
-    parameter \Y_WIDTH 2
-    connect \A \fus_dest3_o$109
-    connect \B \fus_dest3_o$110
-    connect \Y $586
+    connect \A \ibus__ack
+    connect \B \ibus__err
+    connect \Y $35
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  wire width 2 $588
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  cell $or $589
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61"
+  wire width 1 $37
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61"
+  cell $not $38
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 2
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 2
-    parameter \Y_WIDTH 2
-    connect \A \fus_dest6_o
-    connect \B \fus_dest3_o$111
-    connect \Y $588
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \f_valid_i
+    connect \Y $37
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  wire width 2 $590
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  cell $or $591
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61"
+  wire width 1 $39
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61"
+  cell $or $40
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 2
+    parameter \A_WIDTH 1
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 2
-    parameter \Y_WIDTH 2
-    connect \A $586
-    connect \B $588
-    connect \Y $590
-  end
-  process $group_263
-    assign \xer_data_i 2'00
-    assign \xer_data_i $590
-    sync init
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A $35
+    connect \B $37
+    connect \Y $39
   end
-  process $group_264
-    assign \xer_wen$137 3'000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289"
-    switch { \wrpick_XER_xer_ov_en_o }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289"
+  process $group_3
+    assign \ibus_rdata$next \ibus_rdata
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:60"
+    switch { $33 \ibus__cyc }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:60"
+      case 2'-1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61"
+        switch { $39 }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61"
+          case 1'1
+            assign \ibus_rdata$next \ibus__dat_r
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68"
+      case 2'1-
+    end
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \rst
       case 1'1
-        assign \xer_wen$137 3'100
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291"
-      case
-        assign \xer_wen$137 3'000
+        assign \ibus_rdata$next 64'0000000000000000000000000000000000000000000000000000000000000000
     end
     sync init
+      update \ibus_rdata 64'0000000000000000000000000000000000000000000000000000000000000000
+    sync posedge \clk
+      update \ibus_rdata \ibus_rdata$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302"
-  wire width 1 \wrflag_alu0_xer_ov_3
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  wire width 1 $592
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  cell $and $593
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68"
+  wire width 1 $41
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68"
+  cell $not $42
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_xer_ov_ok
-    connect \B \fus_cu_busy_o
-    connect \Y $592
-  end
-  process $group_265
-    assign \wrflag_alu0_xer_ov_3 1'0
-    assign \wrflag_alu0_xer_ov_3 $592
-    sync init
+    connect \A \a_stall_i
+    connect \Y $41
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  wire width 1 $594
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  cell $and $595
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68"
+  wire width 1 $43
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68"
+  cell $and $44
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_cu_wr__rel_o [3]
-    connect \B \fu_enable [0]
-    connect \Y $594
+    connect \A \a_valid_i
+    connect \B $41
+    connect \Y $43
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  wire width 1 $596
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  cell $and $597
+  process $group_4
+    assign \ibus__adr$next \ibus__adr
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:60"
+    switch { $43 \ibus__cyc }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:60"
+      case 2'-1
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68"
+      case 2'1-
+        assign \ibus__adr$next \a_pc_i [47:3]
+    end
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \rst
+      case 1'1
+        assign \ibus__adr$next 45'000000000000000000000000000000000000000000000
+    end
+    sync init
+      update \ibus__adr 45'000000000000000000000000000000000000000000000
+    sync posedge \clk
+      update \ibus__adr \ibus__adr$next
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:34"
+  wire width 1 \f_fetch_err_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:34"
+  wire width 1 \f_fetch_err_o$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:76"
+  wire width 1 $45
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:76"
+  cell $and $46
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_cu_wr__rel_o$82 [4]
-    connect \B \fu_enable [5]
-    connect \Y $596
+    connect \A \ibus__cyc
+    connect \B \ibus__err
+    connect \Y $45
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  wire width 1 $598
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  cell $and $599
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:81"
+  wire width 1 $47
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:27"
+  wire width 1 \f_stall_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:81"
+  cell $not $48
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_cu_wr__rel_o$85 [2]
-    connect \B \fu_enable [6]
-    connect \Y $598
+    connect \A \f_stall_i
+    connect \Y $47
   end
-  process $group_266
-    assign \wrpick_XER_xer_ov_i 3'000
-    assign \wrpick_XER_xer_ov_i [0] $594
-    assign \wrpick_XER_xer_ov_i [1] $596
-    assign \wrpick_XER_xer_ov_i [2] $598
+  process $group_5
+    assign \f_fetch_err_o$next \f_fetch_err_o
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:76"
+    switch { $47 $45 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:76"
+      case 2'-1
+        assign \f_fetch_err_o$next 1'1
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:81"
+      case 2'1-
+        assign \f_fetch_err_o$next 1'0
+    end
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \rst
+      case 1'1
+        assign \f_fetch_err_o$next 1'0
+    end
     sync init
+      update \f_fetch_err_o 1'0
+    sync posedge \clk
+      update \f_fetch_err_o \f_fetch_err_o$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302"
-  wire width 1 \wrflag_spr0_xer_ov_4
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  wire width 1 $600
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  cell $and $601
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:35"
+  wire width 45 \f_badaddr_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:35"
+  wire width 45 \f_badaddr_o$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:76"
+  wire width 1 $49
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:76"
+  cell $and $50
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_xer_ov_ok$112
-    connect \B \fus_cu_busy_o$16
-    connect \Y $600
-  end
-  process $group_267
-    assign \wrflag_spr0_xer_ov_4 1'0
-    assign \wrflag_spr0_xer_ov_4 $600
-    sync init
+    connect \A \ibus__cyc
+    connect \B \ibus__err
+    connect \Y $49
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302"
-  wire width 1 \wrflag_mul0_xer_ov_2
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  wire width 1 $602
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  cell $and $603
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:81"
+  wire width 1 $51
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:81"
+  cell $not $52
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_xer_ov_ok$113
-    connect \B \fus_cu_busy_o$19
-    connect \Y $602
+    connect \A \f_stall_i
+    connect \Y $51
   end
-  process $group_268
-    assign \wrflag_mul0_xer_ov_2 1'0
-    assign \wrflag_mul0_xer_ov_2 $602
+  process $group_6
+    assign \f_badaddr_o$next \f_badaddr_o
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:76"
+    switch { $51 $49 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:76"
+      case 2'-1
+        assign \f_badaddr_o$next \ibus__adr
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:81"
+      case 2'1-
+    end
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \rst
+      case 1'1
+        assign \f_badaddr_o$next 45'000000000000000000000000000000000000000000000
+    end
     sync init
+      update \f_badaddr_o 45'000000000000000000000000000000000000000000000
+    sync posedge \clk
+      update \f_badaddr_o \f_badaddr_o$next
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  wire width 2 $604
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  cell $or $605
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 2
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 2
-    parameter \Y_WIDTH 2
-    connect \A \fus_dest5_o
-    connect \B \fus_dest3_o$114
-    connect \Y $604
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  wire width 2 $606
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  cell $or $607
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 2
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 2
-    parameter \Y_WIDTH 2
-    connect \A \fus_dest4_o
-    connect \B $604
-    connect \Y $606
-  end
-  process $group_269
-    assign \xer_data_i$138 2'00
-    assign \xer_data_i$138 $606
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:31"
+  wire width 1 \a_busy_o
+  process $group_7
+    assign \a_busy_o 1'0
+    assign \a_busy_o \ibus__cyc
     sync init
   end
-  process $group_270
-    assign \xer_wen$139 3'000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289"
-    switch { \wrpick_XER_xer_so_en_o }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289"
+  process $group_8
+    assign \f_busy_o 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86"
+    switch { \f_fetch_err_o }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86"
       case 1'1
-        assign \xer_wen$139 3'001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291"
+        assign \f_busy_o 1'0
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:88"
       case
-        assign \xer_wen$139 3'000
+        assign \f_busy_o \ibus__cyc
     end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302"
-  wire width 1 \wrflag_alu0_xer_so_4
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  wire width 1 $608
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  cell $and $609
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \fus_xer_so_ok
-    connect \B \fus_cu_busy_o
-    connect \Y $608
-  end
-  process $group_271
-    assign \wrflag_alu0_xer_so_4 1'0
-    assign \wrflag_alu0_xer_so_4 $608
+  process $group_9
+    assign \f_instr_o 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86"
+    switch { \f_fetch_err_o }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86"
+      case 1'1
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:88"
+      case
+        assign \f_instr_o \ibus_rdata
+    end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  wire width 1 $610
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  cell $and $611
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \fus_cu_wr__rel_o [4]
-    connect \B \fu_enable [0]
-    connect \Y $610
-  end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  wire width 1 $612
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  cell $and $613
+  connect \a_stall_i 1'0
+  connect \f_stall_i 1'0
+end
+attribute \generator "nMigen"
+attribute \nmigen.hierarchy "test_issuer.dbg"
+module \dbg
+  attribute \src "simple/issuer.py:86"
+  wire width 1 input 0 \clk
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:79"
+  wire width 1 output 1 \core_stop_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:80"
+  wire width 1 output 2 \core_rst_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:84"
+  wire width 1 input 3 \terminate_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:8"
+  wire width 64 input 4 \core_dbg_pc
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:9"
+  wire width 64 input 5 \core_dbg_msr
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:66"
+  wire width 1 output 6 \dbg_gpr_req
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:68"
+  wire width 7 output 7 \dbg_gpr_addr
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:69"
+  wire width 64 input 8 \dbg_gpr_data
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:67"
+  wire width 1 input 9 \dbg_gpr_ack
+  attribute \src "simple/issuer.py:86"
+  wire width 1 input 10 \rst
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:60"
+  wire width 1 output 11 \dmi_ack_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:55"
+  wire width 4 input 12 \dmi_addr_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:58"
+  wire width 1 input 13 \dmi_req_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:57"
+  wire width 64 output 14 \dmi_dout
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:59"
+  wire width 1 input 15 \dmi_we_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:56"
+  wire width 64 input 16 \dmi_din
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:130"
+  wire width 1 $1
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:129"
+  wire width 1 $2
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:129"
+  cell $eq $3
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
+    parameter \A_WIDTH 4
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
+    parameter \B_WIDTH 3
     parameter \Y_WIDTH 1
-    connect \A \fus_cu_wr__rel_o$82 [3]
-    connect \B \fu_enable [5]
-    connect \Y $612
+    connect \A \dmi_addr_i
+    connect \B 3'101
+    connect \Y $2
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  wire width 1 $614
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  cell $and $615
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \fus_cu_wr__rel_o$85 [3]
-    connect \B \fu_enable [6]
-    connect \Y $614
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:130"
+  cell $mux $4
+    parameter \WIDTH 1
+    connect \A \dmi_req_i
+    connect \B \dbg_gpr_ack
+    connect \S $2
+    connect \Y $1
   end
-  process $group_272
-    assign \wrpick_XER_xer_so_i 3'000
-    assign \wrpick_XER_xer_so_i [0] $610
-    assign \wrpick_XER_xer_so_i [1] $612
-    assign \wrpick_XER_xer_so_i [2] $614
+  process $group_0
+    assign \dmi_ack_o 1'0
+    assign \dmi_ack_o $1
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302"
-  wire width 1 \wrflag_spr0_xer_so_3
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  wire width 1 $616
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  cell $and $617
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:132"
+  wire width 1 $5
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:131"
+  wire width 1 $6
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:131"
+  cell $eq $7
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
+    parameter \A_WIDTH 4
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
+    parameter \B_WIDTH 3
     parameter \Y_WIDTH 1
-    connect \A \fus_xer_so_ok$115
-    connect \B \fus_cu_busy_o$16
-    connect \Y $616
+    connect \A \dmi_addr_i
+    connect \B 3'101
+    connect \Y $6
   end
-  process $group_273
-    assign \wrflag_spr0_xer_so_3 1'0
-    assign \wrflag_spr0_xer_so_3 $616
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:132"
+  cell $mux $8
+    parameter \WIDTH 1
+    connect \A 1'0
+    connect \B \dmi_req_i
+    connect \S $6
+    connect \Y $5
+  end
+  process $group_1
+    assign \dbg_gpr_req 1'0
+    assign \dbg_gpr_req $5
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302"
-  wire width 1 \wrflag_mul0_xer_so_3
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  wire width 1 $618
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  cell $and $619
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:109"
+  wire width 64 \stat_reg
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:137"
+  wire width 64 $9
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:112"
+  wire width 1 \stopping
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:112"
+  wire width 1 \stopping$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:85"
+  wire width 1 \core_stopped_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:116"
+  wire width 1 \terminated
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:116"
+  wire width 1 \terminated$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:137"
+  cell $pos $10
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \fus_xer_so_ok$116
-    connect \B \fus_cu_busy_o$19
-    connect \Y $618
+    parameter \A_WIDTH 3
+    parameter \Y_WIDTH 64
+    connect \A { \terminated \core_stopped_i \stopping }
+    connect \Y $9
   end
-  process $group_274
-    assign \wrflag_mul0_xer_so_3 1'0
-    assign \wrflag_mul0_xer_so_3 $618
+  process $group_2
+    assign \stat_reg 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \stat_reg $9
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:120"
+  wire width 32 \log_dmi_addr
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:120"
+  wire width 32 \log_dmi_addr$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:95"
+  wire width 32 \log_write_addr_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:121"
+  wire width 64 \log_dmi_data
+  process $group_3
+    assign \dmi_dout 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:140"
+    switch \dmi_addr_i
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:141"
+      case 4'0001
+        assign \dmi_dout \stat_reg
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:143"
+      case 4'0010
+        assign \dmi_dout \core_dbg_pc
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:145"
+      case 4'0011
+        assign \dmi_dout \core_dbg_msr
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:147"
+      case 4'0101
+        assign \dmi_dout \dbg_gpr_data
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:149"
+      case 4'0110
+        assign \dmi_dout { \log_write_addr_o \log_dmi_addr }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:152"
+      case 4'0111
+        assign \dmi_dout \log_dmi_data
+    end
     sync init
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  wire width 2 $620
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  wire width 1 $621
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  cell $or $622
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:113"
+  wire width 1 \do_step
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:113"
+  wire width 1 \do_step$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164"
+  wire width 1 $11
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:106"
+  wire width 1 \dmi_req_i_1
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:106"
+  wire width 1 \dmi_req_i_1$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164"
+  cell $not $12
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_dest4_o$118
-    connect \B \fus_dest4_o$119
-    connect \Y $621
+    connect \A \dmi_req_i_1
+    connect \Y $11
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  wire width 1 $623
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  cell $or $624
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164"
+  wire width 1 $13
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164"
+  cell $and $14
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_dest5_o$117
-    connect \B $621
-    connect \Y $623
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  cell $pos $625
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 2
-    connect \A $623
-    connect \Y $620
-  end
-  process $group_275
-    assign \xer_data_i$140 2'00
-    assign \xer_data_i$140 $620
-    sync init
+    connect \A \dmi_req_i
+    connect \B $11
+    connect \Y $13
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:170"
-  wire width 8 $626
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:170"
-  cell $sshl $627
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:124"
+  wire width 1 \dmi_read_log_data_1
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:124"
+  wire width 1 \dmi_read_log_data_1$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198"
+  wire width 1 $15
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:123"
+  wire width 1 \dmi_read_log_data
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:123"
+  wire width 1 \dmi_read_log_data$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198"
+  cell $not $16
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 3
-    parameter \Y_WIDTH 8
-    connect \A 1'1
-    connect \B \pdecode2_fasto1
-    connect \Y $626
-  end
-  process $group_276
-    assign \fast_wen 8'00000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289"
-    switch { \wrpick_FAST_fast1_en_o }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289"
-      case 1'1
-        assign \fast_wen $626
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291"
-      case
-        assign \fast_wen 8'00000000
-    end
-    sync init
+    parameter \Y_WIDTH 1
+    connect \A \dmi_read_log_data
+    connect \Y $15
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302"
-  wire width 1 \wrflag_branch0_fast1_0
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  wire width 1 $628
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  cell $and $629
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198"
+  wire width 1 $17
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198"
+  cell $and $18
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_fast1_ok
-    connect \B \fus_cu_busy_o$7
-    connect \Y $628
-  end
-  process $group_277
-    assign \wrflag_branch0_fast1_0 1'0
-    assign \wrflag_branch0_fast1_0 $628
-    sync init
+    connect \A \dmi_read_log_data_1
+    connect \B $15
+    connect \Y $17
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  wire width 1 $630
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  cell $and $631
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171"
+  wire width 1 $19
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171"
+  cell $eq $20
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
+    parameter \A_WIDTH 4
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_cu_wr__rel_o$120 [0]
-    connect \B \fu_enable [2]
-    connect \Y $630
+    connect \A \dmi_addr_i
+    connect \B 1'0
+    connect \Y $19
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  wire width 1 $632
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  cell $and $633
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:187"
+  wire width 1 $21
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:187"
+  cell $eq $22
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
+    parameter \A_WIDTH 4
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
+    parameter \B_WIDTH 3
     parameter \Y_WIDTH 1
-    connect \A \fus_cu_wr__rel_o$76 [1]
-    connect \B \fu_enable [3]
-    connect \Y $632
+    connect \A \dmi_addr_i
+    connect \B 3'100
+    connect \Y $21
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  wire width 1 $634
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  cell $and $635
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:191"
+  wire width 1 $23
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:191"
+  cell $eq $24
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
+    parameter \A_WIDTH 4
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
+    parameter \B_WIDTH 3
     parameter \Y_WIDTH 1
-    connect \A \fus_cu_wr__rel_o$82 [2]
-    connect \B \fu_enable [5]
-    connect \Y $634
+    connect \A \dmi_addr_i
+    connect \B 3'110
+    connect \Y $23
   end
-  process $group_278
-    assign \wrpick_FAST_fast1_i 3'000
-    assign \wrpick_FAST_fast1_i [0] $630
-    assign \wrpick_FAST_fast1_i [1] $632
-    assign \wrpick_FAST_fast1_i [2] $634
+  process $group_4
+    assign \do_step$next \do_step
+    assign \do_step$next 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164"
+    switch { $17 $13 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164"
+      case 2'-1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:165"
+        switch { \dmi_we_i }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:165"
+          case 1'1
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171"
+            switch { $23 $21 $19 }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171"
+              case 3'--1
+                attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:177"
+                switch { \dmi_din [3] }
+                  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:177"
+                  case 1'1
+                    assign \do_step$next 1'1
+                end
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:187"
+              case 3'-1-
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:191"
+              case 3'1--
+            end
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:194"
+          case
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198"
+      case 2'1-
+    end
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \rst
+      case 1'1
+        assign \do_step$next 1'0
+    end
     sync init
+      update \do_step 1'0
+    sync posedge \clk
+      update \do_step \do_step$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  wire width 1 $636
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  cell $and $637
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:114"
+  wire width 1 \do_reset
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:114"
+  wire width 1 \do_reset$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164"
+  wire width 1 $25
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164"
+  cell $not $26
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wrpick_FAST_fast1_o [0]
-    connect \B \wrpick_FAST_fast1_en_o
-    connect \Y $636
+    connect \A \dmi_req_i_1
+    connect \Y $25
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  wire width 1 $638
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  cell $and $639
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164"
+  wire width 1 $27
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164"
+  cell $and $28
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wrpick_FAST_fast2_o [0]
-    connect \B \wrpick_FAST_fast2_en_o
-    connect \Y $638
+    connect \A \dmi_req_i
+    connect \B $25
+    connect \Y $27
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  wire width 1 $640
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:309"
-  cell $and $641
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198"
+  wire width 1 $29
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198"
+  cell $not $30
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \wrpick_FAST_nia_o [0]
-    connect \B \wrpick_FAST_nia_en_o
-    connect \Y $640
-  end
-  process $group_279
-    assign \fus_cu_wr__go_i$121 3'000
-    assign \fus_cu_wr__go_i$121 [0] $636
-    assign \fus_cu_wr__go_i$121 [1] $638
-    assign \fus_cu_wr__go_i$121 [2] $640
-    sync init
+    connect \A \dmi_read_log_data
+    connect \Y $29
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302"
-  wire width 1 \wrflag_trap0_fast1_1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  wire width 1 $642
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  cell $and $643
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198"
+  wire width 1 $31
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198"
+  cell $and $32
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_fast1_ok$122
-    connect \B \fus_cu_busy_o$10
-    connect \Y $642
-  end
-  process $group_280
-    assign \wrflag_trap0_fast1_1 1'0
-    assign \wrflag_trap0_fast1_1 $642
-    sync init
+    connect \A \dmi_read_log_data_1
+    connect \B $29
+    connect \Y $31
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302"
-  wire width 1 \wrflag_spr0_fast1_2
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  wire width 1 $644
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  cell $and $645
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171"
+  wire width 1 $33
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171"
+  cell $eq $34
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
+    parameter \A_WIDTH 4
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_fast1_ok$123
-    connect \B \fus_cu_busy_o$16
-    connect \Y $644
-  end
-  process $group_281
-    assign \wrflag_spr0_fast1_2 1'0
-    assign \wrflag_spr0_fast1_2 $644
-    sync init
-  end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  wire width 64 $646
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  cell $or $647
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 64
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 64
-    parameter \Y_WIDTH 64
-    connect \A \fus_dest2_o$125
-    connect \B \fus_dest3_o$126
-    connect \Y $646
+    connect \A \dmi_addr_i
+    connect \B 1'0
+    connect \Y $33
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  wire width 64 $648
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29"
-  cell $or $649
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:187"
+  wire width 1 $35
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:187"
+  cell $eq $36
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 64
+    parameter \A_WIDTH 4
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 64
-    parameter \Y_WIDTH 64
-    connect \A \fus_dest1_o$124
-    connect \B $646
-    connect \Y $648
-  end
-  process $group_282
-    assign \fast_data_i 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \fast_data_i $648
-    sync init
+    parameter \B_WIDTH 3
+    parameter \Y_WIDTH 1
+    connect \A \dmi_addr_i
+    connect \B 3'100
+    connect \Y $35
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:172"
-  wire width 8 $650
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:172"
-  cell $sshl $651
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:191"
+  wire width 1 $37
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:191"
+  cell $eq $38
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
+    parameter \A_WIDTH 4
     parameter \B_SIGNED 0
     parameter \B_WIDTH 3
-    parameter \Y_WIDTH 8
-    connect \A 1'1
-    connect \B \pdecode2_fasto2
-    connect \Y $650
+    parameter \Y_WIDTH 1
+    connect \A \dmi_addr_i
+    connect \B 3'110
+    connect \Y $37
   end
-  process $group_283
-    assign \fast_wen$141 8'00000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289"
-    switch { \wrpick_FAST_fast2_en_o }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289"
+  process $group_5
+    assign \do_reset$next \do_reset
+    assign \do_reset$next 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164"
+    switch { $31 $27 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164"
+      case 2'-1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:165"
+        switch { \dmi_we_i }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:165"
+          case 1'1
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171"
+            switch { $37 $35 $33 }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171"
+              case 3'--1
+                attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:172"
+                switch { \dmi_din [1] }
+                  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:172"
+                  case 1'1
+                    assign \do_reset$next 1'1
+                end
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:187"
+              case 3'-1-
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:191"
+              case 3'1--
+            end
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:194"
+          case
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198"
+      case 2'1-
+    end
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \rst
       case 1'1
-        assign \fast_wen$141 $650
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291"
-      case
-        assign \fast_wen$141 8'00000000
+        assign \do_reset$next 1'0
     end
     sync init
+      update \do_reset 1'0
+    sync posedge \clk
+      update \do_reset \do_reset$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302"
-  wire width 1 \wrflag_branch0_fast2_1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  wire width 1 $652
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  cell $and $653
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:115"
+  wire width 1 \do_icreset
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:115"
+  wire width 1 \do_icreset$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164"
+  wire width 1 $39
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164"
+  cell $not $40
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_fast2_ok
-    connect \B \fus_cu_busy_o$7
-    connect \Y $652
-  end
-  process $group_284
-    assign \wrflag_branch0_fast2_1 1'0
-    assign \wrflag_branch0_fast2_1 $652
-    sync init
+    connect \A \dmi_req_i_1
+    connect \Y $39
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  wire width 1 $654
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  cell $and $655
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164"
+  wire width 1 $41
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164"
+  cell $and $42
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_cu_wr__rel_o$120 [1]
-    connect \B \fu_enable [2]
-    connect \Y $654
+    connect \A \dmi_req_i
+    connect \B $39
+    connect \Y $41
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  wire width 1 $656
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  cell $and $657
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198"
+  wire width 1 $43
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198"
+  cell $not $44
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_cu_wr__rel_o$76 [2]
-    connect \B \fu_enable [3]
-    connect \Y $656
-  end
-  process $group_285
-    assign \wrpick_FAST_fast2_i 2'00
-    assign \wrpick_FAST_fast2_i [0] $654
-    assign \wrpick_FAST_fast2_i [1] $656
-    sync init
+    connect \A \dmi_read_log_data
+    connect \Y $43
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302"
-  wire width 1 \wrflag_trap0_fast2_2
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  wire width 1 $658
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  cell $and $659
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198"
+  wire width 1 $45
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198"
+  cell $and $46
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_fast2_ok$127
-    connect \B \fus_cu_busy_o$10
-    connect \Y $658
+    connect \A \dmi_read_log_data_1
+    connect \B $43
+    connect \Y $45
   end
-  process $group_286
-    assign \wrflag_trap0_fast2_2 1'0
-    assign \wrflag_trap0_fast2_2 $658
-    sync init
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171"
+  wire width 1 $47
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171"
+  cell $eq $48
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 4
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \dmi_addr_i
+    connect \B 1'0
+    connect \Y $47
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  wire width 64 $660
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  cell $or $661
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:187"
+  wire width 1 $49
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:187"
+  cell $eq $50
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 64
+    parameter \A_WIDTH 4
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 64
-    parameter \Y_WIDTH 64
-    connect \A \fus_dest2_o$128
-    connect \B \fus_dest3_o$129
-    connect \Y $660
+    parameter \B_WIDTH 3
+    parameter \Y_WIDTH 1
+    connect \A \dmi_addr_i
+    connect \B 3'100
+    connect \Y $49
   end
-  process $group_287
-    assign \fast_data_i$142 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \fast_data_i$142 $660
-    sync init
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:191"
+  wire width 1 $51
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:191"
+  cell $eq $52
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 4
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 3
+    parameter \Y_WIDTH 1
+    connect \A \dmi_addr_i
+    connect \B 3'110
+    connect \Y $51
   end
-  process $group_288
-    assign \fast_nia_wen 8'00000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289"
-    switch { \wrpick_FAST_nia_en_o }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289"
+  process $group_6
+    assign \do_icreset$next \do_icreset
+    assign \do_icreset$next 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164"
+    switch { $45 $41 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164"
+      case 2'-1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:165"
+        switch { \dmi_we_i }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:165"
+          case 1'1
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171"
+            switch { $51 $49 $47 }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171"
+              case 3'--1
+                attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:180"
+                switch { \dmi_din [2] }
+                  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:180"
+                  case 1'1
+                    assign \do_icreset$next 1'1
+                end
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:187"
+              case 3'-1-
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:191"
+              case 3'1--
+            end
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:194"
+          case
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198"
+      case 2'1-
+    end
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \rst
       case 1'1
-        assign \fast_nia_wen 8'00000001
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291"
-      case
-        assign \fast_nia_wen 8'00000000
+        assign \do_icreset$next 1'0
     end
     sync init
+      update \do_icreset 1'0
+    sync posedge \clk
+      update \do_icreset \do_icreset$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302"
-  wire width 1 \wrflag_branch0_nia_2
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  wire width 1 $662
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  cell $and $663
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:122"
+  wire width 1 \do_dmi_log_rd
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:122"
+  wire width 1 \do_dmi_log_rd$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164"
+  wire width 1 $53
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164"
+  cell $not $54
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_nia_ok
-    connect \B \fus_cu_busy_o$7
-    connect \Y $662
-  end
-  process $group_289
-    assign \wrflag_branch0_nia_2 1'0
-    assign \wrflag_branch0_nia_2 $662
-    sync init
+    connect \A \dmi_req_i_1
+    connect \Y $53
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  wire width 1 $664
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  cell $and $665
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164"
+  wire width 1 $55
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164"
+  cell $and $56
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_cu_wr__rel_o$120 [2]
-    connect \B \fu_enable [2]
-    connect \Y $664
+    connect \A \dmi_req_i
+    connect \B $53
+    connect \Y $55
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  wire width 1 $666
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  cell $and $667
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198"
+  wire width 1 $57
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198"
+  cell $not $58
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_cu_wr__rel_o$76 [3]
-    connect \B \fu_enable [3]
-    connect \Y $666
-  end
-  process $group_290
-    assign \wrpick_FAST_nia_i 2'00
-    assign \wrpick_FAST_nia_i [0] $664
-    assign \wrpick_FAST_nia_i [1] $666
-    sync init
+    connect \A \dmi_read_log_data
+    connect \Y $57
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302"
-  wire width 1 \wrflag_trap0_nia_3
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  wire width 1 $668
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  cell $and $669
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198"
+  wire width 1 $59
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198"
+  cell $and $60
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_nia_ok$130
-    connect \B \fus_cu_busy_o$10
-    connect \Y $668
-  end
-  process $group_291
-    assign \wrflag_trap0_nia_3 1'0
-    assign \wrflag_trap0_nia_3 $668
-    sync init
+    connect \A \dmi_read_log_data_1
+    connect \B $57
+    connect \Y $59
   end
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  wire width 64 $670
-  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26"
-  cell $or $671
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171"
+  wire width 1 $61
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171"
+  cell $eq $62
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 64
+    parameter \A_WIDTH 4
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 64
-    parameter \Y_WIDTH 64
-    connect \A \fus_dest3_o$131
-    connect \B \fus_dest4_o$132
-    connect \Y $670
-  end
-  process $group_292
-    assign \fast_data_i$143 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \fast_data_i$143 $670
-    sync init
-  end
-  process $group_293
-    assign \fast_wen$144 8'00000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289"
-    switch { \wrpick_FAST_msr_en_o }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289"
-      case 1'1
-        assign \fast_wen$144 8'00000010
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291"
-      case
-        assign \fast_wen$144 8'00000000
-    end
-    sync init
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \dmi_addr_i
+    connect \B 1'0
+    connect \Y $61
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302"
-  wire width 1 \wrflag_trap0_msr_4
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  wire width 1 $672
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  cell $and $673
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:187"
+  wire width 1 $63
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:187"
+  cell $eq $64
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
+    parameter \A_WIDTH 4
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
+    parameter \B_WIDTH 3
     parameter \Y_WIDTH 1
-    connect \A \fus_msr_ok
-    connect \B \fus_cu_busy_o$10
-    connect \Y $672
-  end
-  process $group_294
-    assign \wrflag_trap0_msr_4 1'0
-    assign \wrflag_trap0_msr_4 $672
-    sync init
+    connect \A \dmi_addr_i
+    connect \B 3'100
+    connect \Y $63
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  wire width 1 $674
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  cell $and $675
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:191"
+  wire width 1 $65
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:191"
+  cell $eq $66
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
+    parameter \A_WIDTH 4
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
+    parameter \B_WIDTH 3
     parameter \Y_WIDTH 1
-    connect \A \fus_cu_wr__rel_o$76 [4]
-    connect \B \fu_enable [3]
-    connect \Y $674
-  end
-  process $group_295
-    assign \wrpick_FAST_msr_i 1'0
-    assign \wrpick_FAST_msr_i $674
-    sync init
+    connect \A \dmi_addr_i
+    connect \B 3'110
+    connect \Y $65
   end
-  process $group_296
-    assign \fast_data_i$145 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \fast_data_i$145 \fus_dest5_o$133
+  process $group_7
+    assign \do_dmi_log_rd$next \do_dmi_log_rd
+    assign \do_dmi_log_rd$next 1'0
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164"
+    switch { $59 $55 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164"
+      case 2'-1
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:165"
+        switch { \dmi_we_i }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:165"
+          case 1'1
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171"
+            switch { $65 $63 $61 }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171"
+              case 3'--1
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:187"
+              case 3'-1-
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:191"
+              case 3'1--
+                assign \do_dmi_log_rd$next 1'1
+            end
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:194"
+          case
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198"
+      case 2'1-
+        assign \do_dmi_log_rd$next 1'1
+    end
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \rst
+      case 1'1
+        assign \do_dmi_log_rd$next 1'0
+    end
     sync init
+      update \do_dmi_log_rd 1'0
+    sync posedge \clk
+      update \do_dmi_log_rd \do_dmi_log_rd$next
   end
-  process $group_297
-    assign \spr_dest__wen 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289"
-    switch { \wrpick_SPR_spr1_en_o }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:289"
+  process $group_8
+    assign \dmi_req_i_1$next \dmi_req_i_1
+    assign \dmi_req_i_1$next \dmi_req_i
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \rst
       case 1'1
-        assign \spr_dest__wen \pdecode2_spro [0]
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:291"
-      case
-        assign \spr_dest__wen 1'0
+        assign \dmi_req_i_1$next 1'0
     end
     sync init
+      update \dmi_req_i_1 1'0
+    sync posedge \clk
+      update \dmi_req_i_1 \dmi_req_i_1$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:302"
-  wire width 1 \wrflag_spr0_spr1_1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  wire width 1 $676
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:303"
-  cell $and $677
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164"
+  wire width 1 $67
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164"
+  cell $not $68
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_spr1_ok
-    connect \B \fus_cu_busy_o$16
-    connect \Y $676
-  end
-  process $group_298
-    assign \wrflag_spr0_spr1_1 1'0
-    assign \wrflag_spr0_spr1_1 $676
-    sync init
+    connect \A \dmi_req_i_1
+    connect \Y $67
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  wire width 1 $678
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:307"
-  cell $and $679
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164"
+  wire width 1 $69
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164"
+  cell $and $70
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \fus_cu_wr__rel_o$82 [1]
-    connect \B \fu_enable [5]
-    connect \Y $678
-  end
-  process $group_299
-    assign \wrpick_SPR_spr1_i 1'0
-    assign \wrpick_SPR_spr1_i $678
-    sync init
-  end
-  process $group_300
-    assign \spr_dest__data_i 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \spr_dest__data_i \fus_dest2_o$134
-    sync init
+    connect \A \dmi_req_i
+    connect \B $67
+    connect \Y $69
   end
-  connect \o_ok 1'0
-  connect \ea_ok 1'0
-end
-attribute \generator "nMigen"
-attribute \nmigen.hierarchy "test_issuer.imem"
-module \imem
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:24"
-  wire width 48 input 0 \a_pc_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:26"
-  wire width 1 input 1 \a_valid_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:28"
-  wire width 1 input 2 \f_valid_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:32"
-  wire width 1 output 3 \f_busy_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:33"
-  wire width 64 output 4 \f_instr_o
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 5 \rst
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 6 \clk
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
-  wire width 1 output 7 \ibus__cyc
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
-  wire width 1 \ibus__cyc$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
-  wire width 1 input 8 \ibus__ack
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
-  wire width 1 input 9 \ibus__err
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
-  wire width 1 output 10 \ibus__stb
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
-  wire width 1 \ibus__stb$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
-  wire width 8 output 11 \ibus__sel
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
-  wire width 8 \ibus__sel$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
-  wire width 64 input 12 \ibus__dat_r
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
-  wire width 45 output 13 \ibus__adr
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
-  wire width 45 \ibus__adr$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68"
-  wire width 1 $1
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:25"
-  wire width 1 \a_stall_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68"
-  cell $not $2
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198"
+  wire width 1 $71
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198"
+  cell $not $72
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \a_stall_i
-    connect \Y $1
+    connect \A \dmi_read_log_data
+    connect \Y $71
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68"
-  wire width 1 $3
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68"
-  cell $and $4
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198"
+  wire width 1 $73
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198"
+  cell $and $74
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \a_valid_i
-    connect \B $1
-    connect \Y $3
+    connect \A \dmi_read_log_data_1
+    connect \B $71
+    connect \Y $73
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61"
-  wire width 1 $5
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61"
-  cell $or $6
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171"
+  wire width 1 $75
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171"
+  cell $eq $76
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
+    parameter \A_WIDTH 4
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \ibus__ack
-    connect \B \ibus__err
-    connect \Y $5
+    connect \A \dmi_addr_i
+    connect \B 1'0
+    connect \Y $75
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61"
-  wire width 1 $7
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61"
-  cell $not $8
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:187"
+  wire width 1 $77
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:187"
+  cell $eq $78
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
+    parameter \A_WIDTH 4
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 3
     parameter \Y_WIDTH 1
-    connect \A \f_valid_i
-    connect \Y $7
+    connect \A \dmi_addr_i
+    connect \B 3'100
+    connect \Y $77
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61"
-  wire width 1 $9
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61"
-  cell $or $10
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:191"
+  wire width 1 $79
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:191"
+  cell $eq $80
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
+    parameter \A_WIDTH 4
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
+    parameter \B_WIDTH 3
     parameter \Y_WIDTH 1
-    connect \A $5
-    connect \B $7
-    connect \Y $9
+    connect \A \dmi_addr_i
+    connect \B 3'110
+    connect \Y $79
   end
-  process $group_0
-    assign \ibus__cyc$next \ibus__cyc
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:60"
-    switch { $3 \ibus__cyc }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:60"
+  process $group_9
+    assign \terminated$next \terminated
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164"
+    switch { $73 $69 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164"
       case 2'-1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61"
-        switch { $9 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61"
-          case 1'1
-            assign \ibus__cyc$next 1'0
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:165"
+        switch { \dmi_we_i }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:165"
+          case 1'1
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171"
+            switch { $79 $77 $75 }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171"
+              case 3'--1
+                attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:172"
+                switch { \dmi_din [1] }
+                  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:172"
+                  case 1'1
+                    assign \terminated$next 1'0
+                end
+                attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:177"
+                switch { \dmi_din [3] }
+                  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:177"
+                  case 1'1
+                    assign \terminated$next 1'0
+                end
+                attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:182"
+                switch { \dmi_din [4] }
+                  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:182"
+                  case 1'1
+                    assign \terminated$next 1'0
+                end
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:187"
+              case 3'-1-
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:191"
+              case 3'1--
+            end
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:194"
+          case
         end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198"
       case 2'1-
-        assign \ibus__cyc$next 1'1
+    end
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:211"
+    switch { \terminate_i }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:211"
+      case 1'1
+        assign \terminated$next 1'1
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
     switch \rst
       case 1'1
-        assign \ibus__cyc$next 1'0
+        assign \terminated$next 1'0
     end
     sync init
-      update \ibus__cyc 1'0
+      update \terminated 1'0
     sync posedge \clk
-      update \ibus__cyc \ibus__cyc$next
+      update \terminated \terminated$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68"
-  wire width 1 $11
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68"
-  cell $not $12
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164"
+  wire width 1 $81
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164"
+  cell $not $82
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \a_stall_i
-    connect \Y $11
+    connect \A \dmi_req_i_1
+    connect \Y $81
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68"
-  wire width 1 $13
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68"
-  cell $and $14
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164"
+  wire width 1 $83
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164"
+  cell $and $84
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \a_valid_i
-    connect \B $11
-    connect \Y $13
+    connect \A \dmi_req_i
+    connect \B $81
+    connect \Y $83
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61"
-  wire width 1 $15
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61"
-  cell $or $16
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198"
+  wire width 1 $85
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198"
+  cell $not $86
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \dmi_read_log_data
+    connect \Y $85
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198"
+  wire width 1 $87
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198"
+  cell $and $88
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \ibus__ack
-    connect \B \ibus__err
-    connect \Y $15
+    connect \A \dmi_read_log_data_1
+    connect \B $85
+    connect \Y $87
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61"
-  wire width 1 $17
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61"
-  cell $not $18
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171"
+  wire width 1 $89
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171"
+  cell $eq $90
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 4
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \dmi_addr_i
+    connect \B 1'0
+    connect \Y $89
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:187"
+  wire width 1 $91
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:187"
+  cell $eq $92
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
+    parameter \A_WIDTH 4
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 3
     parameter \Y_WIDTH 1
-    connect \A \f_valid_i
-    connect \Y $17
+    connect \A \dmi_addr_i
+    connect \B 3'100
+    connect \Y $91
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61"
-  wire width 1 $19
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61"
-  cell $or $20
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:191"
+  wire width 1 $93
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:191"
+  cell $eq $94
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
+    parameter \A_WIDTH 4
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
+    parameter \B_WIDTH 3
     parameter \Y_WIDTH 1
-    connect \A $15
-    connect \B $17
-    connect \Y $19
+    connect \A \dmi_addr_i
+    connect \B 3'110
+    connect \Y $93
   end
-  process $group_1
-    assign \ibus__stb$next \ibus__stb
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:60"
-    switch { $13 \ibus__cyc }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:60"
+  process $group_10
+    assign \stopping$next \stopping
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164"
+    switch { $87 $83 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164"
       case 2'-1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61"
-        switch { $19 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61"
-          case 1'1
-            assign \ibus__stb$next 1'0
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:165"
+        switch { \dmi_we_i }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:165"
+          case 1'1
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171"
+            switch { $93 $91 $89 }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171"
+              case 3'--1
+                attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:175"
+                switch { \dmi_din [0] }
+                  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:175"
+                  case 1'1
+                    assign \stopping$next 1'1
+                end
+                attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:182"
+                switch { \dmi_din [4] }
+                  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:182"
+                  case 1'1
+                    assign \stopping$next 1'0
+                end
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:187"
+              case 3'-1-
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:191"
+              case 3'1--
+            end
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:194"
+          case
         end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198"
       case 2'1-
-        assign \ibus__stb$next 1'1
+    end
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:211"
+    switch { \terminate_i }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:211"
+      case 1'1
+        assign \stopping$next 1'1
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
     switch \rst
       case 1'1
-        assign \ibus__stb$next 1'0
+        assign \stopping$next 1'0
     end
     sync init
-      update \ibus__stb 1'0
+      update \stopping 1'0
     sync posedge \clk
-      update \ibus__stb \ibus__stb$next
+      update \stopping \stopping$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68"
-  wire width 1 $21
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68"
-  cell $not $22
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:118"
+  wire width 7 \gspr_index
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:118"
+  wire width 7 \gspr_index$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164"
+  wire width 1 $95
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164"
+  cell $not $96
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \a_stall_i
-    connect \Y $21
+    connect \A \dmi_req_i_1
+    connect \Y $95
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68"
-  wire width 1 $23
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68"
-  cell $and $24
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164"
+  wire width 1 $97
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164"
+  cell $and $98
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \a_valid_i
-    connect \B $21
-    connect \Y $23
+    connect \A \dmi_req_i
+    connect \B $95
+    connect \Y $97
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61"
-  wire width 1 $25
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61"
-  cell $or $26
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198"
+  wire width 1 $99
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198"
+  cell $not $100
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \ibus__ack
-    connect \B \ibus__err
-    connect \Y $25
+    connect \A \dmi_read_log_data
+    connect \Y $99
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61"
-  wire width 1 $27
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61"
-  cell $not $28
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198"
+  wire width 1 $101
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198"
+  cell $and $102
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \f_valid_i
-    connect \Y $27
+    connect \A \dmi_read_log_data_1
+    connect \B $99
+    connect \Y $101
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61"
-  wire width 1 $29
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61"
-  cell $or $30
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171"
+  wire width 1 $103
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171"
+  cell $eq $104
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
+    parameter \A_WIDTH 4
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $25
-    connect \B $27
-    connect \Y $29
+    connect \A \dmi_addr_i
+    connect \B 1'0
+    connect \Y $103
   end
-  process $group_2
-    assign \ibus__sel$next \ibus__sel
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:60"
-    switch { $23 \ibus__cyc }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:60"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:187"
+  wire width 1 $105
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:187"
+  cell $eq $106
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 4
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 3
+    parameter \Y_WIDTH 1
+    connect \A \dmi_addr_i
+    connect \B 3'100
+    connect \Y $105
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:191"
+  wire width 1 $107
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:191"
+  cell $eq $108
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 4
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 3
+    parameter \Y_WIDTH 1
+    connect \A \dmi_addr_i
+    connect \B 3'110
+    connect \Y $107
+  end
+  process $group_11
+    assign \gspr_index$next \gspr_index
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164"
+    switch { $101 $97 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164"
       case 2'-1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61"
-        switch { $29 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61"
-          case 1'1
-            assign \ibus__sel$next 8'00000000
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:165"
+        switch { \dmi_we_i }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:165"
+          case 1'1
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171"
+            switch { $107 $105 $103 }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171"
+              case 3'--1
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:187"
+              case 3'-1-
+                assign \gspr_index$next \dmi_din [6:0]
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:191"
+              case 3'1--
+            end
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:194"
+          case
         end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68"
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198"
       case 2'1-
-        assign \ibus__sel$next 8'11111111
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
     switch \rst
       case 1'1
-        assign \ibus__sel$next 8'00000000
+        assign \gspr_index$next 7'0000000
     end
     sync init
-      update \ibus__sel 8'00000000
+      update \gspr_index 7'0000000
     sync posedge \clk
-      update \ibus__sel \ibus__sel$next
+      update \gspr_index \gspr_index$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:59"
-  wire width 64 \ibus_rdata
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:59"
-  wire width 64 \ibus_rdata$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68"
-  wire width 1 $31
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68"
-  cell $not $32
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164"
+  wire width 1 $109
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164"
+  cell $not $110
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \a_stall_i
-    connect \Y $31
+    connect \A \dmi_req_i_1
+    connect \Y $109
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68"
-  wire width 1 $33
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68"
-  cell $and $34
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164"
+  wire width 1 $111
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164"
+  cell $and $112
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \a_valid_i
-    connect \B $31
-    connect \Y $33
+    connect \A \dmi_req_i
+    connect \B $109
+    connect \Y $111
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61"
-  wire width 1 $35
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61"
-  cell $or $36
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198"
+  wire width 1 $113
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198"
+  cell $not $114
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \ibus__ack
-    connect \B \ibus__err
-    connect \Y $35
+    connect \A \dmi_read_log_data
+    connect \Y $113
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61"
-  wire width 1 $37
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61"
-  cell $not $38
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198"
+  wire width 1 $115
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198"
+  cell $and $116
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \f_valid_i
-    connect \Y $37
+    connect \A \dmi_read_log_data_1
+    connect \B $113
+    connect \Y $115
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61"
-  wire width 1 $39
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61"
-  cell $or $40
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171"
+  wire width 1 $117
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171"
+  cell $eq $118
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
+    parameter \A_WIDTH 4
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A $35
-    connect \B $37
-    connect \Y $39
+    connect \A \dmi_addr_i
+    connect \B 1'0
+    connect \Y $117
   end
-  process $group_3
-    assign \ibus_rdata$next \ibus_rdata
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:60"
-    switch { $33 \ibus__cyc }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:60"
-      case 2'-1
-        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61"
-        switch { $39 }
-          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61"
-          case 1'1
-            assign \ibus_rdata$next \ibus__dat_r
-        end
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68"
-      case 2'1-
-    end
-    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
-      case 1'1
-        assign \ibus_rdata$next 64'0000000000000000000000000000000000000000000000000000000000000000
-    end
-    sync init
-      update \ibus_rdata 64'0000000000000000000000000000000000000000000000000000000000000000
-    sync posedge \clk
-      update \ibus_rdata \ibus_rdata$next
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:187"
+  wire width 1 $119
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:187"
+  cell $eq $120
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 4
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 3
+    parameter \Y_WIDTH 1
+    connect \A \dmi_addr_i
+    connect \B 3'100
+    connect \Y $119
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68"
-  wire width 1 $41
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68"
-  cell $not $42
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:191"
+  wire width 1 $121
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:191"
+  cell $eq $122
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
+    parameter \A_WIDTH 4
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 3
     parameter \Y_WIDTH 1
-    connect \A \a_stall_i
-    connect \Y $41
+    connect \A \dmi_addr_i
+    connect \B 3'110
+    connect \Y $121
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68"
-  wire width 1 $43
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68"
-  cell $and $44
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201"
+  wire width 3 $123
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201"
+  wire width 3 $124
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:201"
+  cell $add $125
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
+    parameter \A_WIDTH 2
     parameter \B_SIGNED 0
     parameter \B_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \a_valid_i
-    connect \B $41
-    connect \Y $43
+    parameter \Y_WIDTH 3
+    connect \A \log_dmi_addr [1:0]
+    connect \B 1'1
+    connect \Y $124
   end
-  process $group_4
-    assign \ibus__adr$next \ibus__adr
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:60"
-    switch { $43 \ibus__cyc }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:60"
+  connect $123 $124
+  process $group_12
+    assign \log_dmi_addr$next \log_dmi_addr
+    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164"
+    switch { $115 $111 }
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:164"
       case 2'-1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68"
+        attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:165"
+        switch { \dmi_we_i }
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:165"
+          case 1'1
+            attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171"
+            switch { $121 $119 $117 }
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:171"
+              case 3'--1
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:187"
+              case 3'-1-
+              attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:191"
+              case 3'1--
+                assign \log_dmi_addr$next \dmi_din [31:0]
+            end
+          attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:194"
+          case
+        end
+      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:198"
       case 2'1-
-        assign \ibus__adr$next \a_pc_i [47:3]
+        assign \log_dmi_addr$next [1:0] $123 [1:0]
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
     switch \rst
       case 1'1
-        assign \ibus__adr$next 45'000000000000000000000000000000000000000000000
+        assign \log_dmi_addr$next 32'00000000000000000000000000000000
     end
     sync init
-      update \ibus__adr 45'000000000000000000000000000000000000000000000
+      update \log_dmi_addr 32'00000000000000000000000000000000
     sync posedge \clk
-      update \ibus__adr \ibus__adr$next
+      update \log_dmi_addr \log_dmi_addr$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:34"
-  wire width 1 \f_fetch_err_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:34"
-  wire width 1 \f_fetch_err_o$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:76"
-  wire width 1 $45
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:76"
-  cell $and $46
+  process $group_13
+    assign \dmi_read_log_data_1$next \dmi_read_log_data_1
+    assign \dmi_read_log_data_1$next \dmi_read_log_data
+    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
+    switch \rst
+      case 1'1
+        assign \dmi_read_log_data_1$next 1'0
+    end
+    sync init
+      update \dmi_read_log_data_1 1'0
+    sync posedge \clk
+      update \dmi_read_log_data_1 \dmi_read_log_data_1$next
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:206"
+  wire width 1 $126
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:206"
+  cell $eq $127
     parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
+    parameter \A_WIDTH 4
     parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
+    parameter \B_WIDTH 3
     parameter \Y_WIDTH 1
-    connect \A \ibus__cyc
-    connect \B \ibus__err
-    connect \Y $45
+    connect \A \dmi_addr_i
+    connect \B 3'111
+    connect \Y $126
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:81"
-  wire width 1 $47
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:27"
-  wire width 1 \f_stall_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:81"
-  cell $not $48
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:206"
+  wire width 1 $128
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:206"
+  cell $and $129
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \f_stall_i
-    connect \Y $47
+    connect \A \dmi_req_i
+    connect \B $126
+    connect \Y $128
   end
-  process $group_5
-    assign \f_fetch_err_o$next \f_fetch_err_o
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:76"
-    switch { $47 $45 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:76"
-      case 2'-1
-        assign \f_fetch_err_o$next 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:81"
-      case 2'1-
-        assign \f_fetch_err_o$next 1'0
-    end
+  process $group_14
+    assign \dmi_read_log_data$next \dmi_read_log_data
+    assign \dmi_read_log_data$next $128
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
     switch \rst
       case 1'1
-        assign \f_fetch_err_o$next 1'0
+        assign \dmi_read_log_data$next 1'0
     end
     sync init
-      update \f_fetch_err_o 1'0
+      update \dmi_read_log_data 1'0
     sync posedge \clk
-      update \f_fetch_err_o \f_fetch_err_o$next
+      update \dmi_read_log_data \dmi_read_log_data$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:35"
-  wire width 45 \f_badaddr_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:35"
-  wire width 45 \f_badaddr_o$next
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:76"
-  wire width 1 $49
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:76"
-  cell $and $50
+  process $group_15
+    assign \dbg_gpr_addr 7'0000000
+    assign \dbg_gpr_addr \gspr_index
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:218"
+  wire width 1 $130
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:218"
+  cell $not $131
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
-    parameter \B_SIGNED 0
-    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \ibus__cyc
-    connect \B \ibus__err
-    connect \Y $49
+    connect \A \do_step
+    connect \Y $130
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:81"
-  wire width 1 $51
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:81"
-  cell $not $52
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:218"
+  wire width 1 $132
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:218"
+  cell $and $133
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \f_stall_i
-    connect \Y $51
+    connect \A \stopping
+    connect \B $130
+    connect \Y $132
   end
-  process $group_6
-    assign \f_badaddr_o$next \f_badaddr_o
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:76"
-    switch { $51 $49 }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:76"
-      case 2'-1
-        assign \f_badaddr_o$next \ibus__adr
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:81"
-      case 2'1-
-    end
-    attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
-    switch \rst
-      case 1'1
-        assign \f_badaddr_o$next 45'000000000000000000000000000000000000000000000
-    end
+  process $group_16
+    assign \core_stop_o 1'0
+    assign \core_stop_o $132
     sync init
-      update \f_badaddr_o 45'000000000000000000000000000000000000000000000
-    sync posedge \clk
-      update \f_badaddr_o \f_badaddr_o$next
   end
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:31"
-  wire width 1 \a_busy_o
-  process $group_7
-    assign \a_busy_o 1'0
-    assign \a_busy_o \ibus__cyc
+  process $group_17
+    assign \core_rst_o 1'0
+    assign \core_rst_o \do_reset
     sync init
   end
-  process $group_8
-    assign \f_busy_o 1'0
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86"
-    switch { \f_fetch_err_o }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86"
-      case 1'1
-        assign \f_busy_o 1'0
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:88"
-      case
-        assign \f_busy_o \ibus__cyc
-    end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:81"
+  wire width 1 \icache_rst_o
+  process $group_18
+    assign \icache_rst_o 1'0
+    assign \icache_rst_o \do_icreset
     sync init
   end
-  process $group_9
-    assign \f_instr_o 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86"
-    switch { \f_fetch_err_o }
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86"
-      case 1'1
-      attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:88"
-      case
-        assign \f_instr_o \ibus_rdata
-    end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:98"
+  wire width 1 \terminated_o
+  process $group_19
+    assign \terminated_o 1'0
+    assign \terminated_o \terminated
     sync init
   end
-  connect \a_stall_i 1'0
-  connect \f_stall_i 1'0
+  connect \core_stopped_i 1'0
+  connect \log_write_addr_o 32'00000000000000000000000000000000
+  connect \log_dmi_data 64'0000000000000000000000000000000000000000000000000000000000000000
 end
 attribute \generator "nMigen"
 attribute \top 1
@@ -157744,78 +176019,80 @@ module \test_issuer
   wire width 64 input 0 \pc_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17"
   wire width 1 input 1 \pc_i_ok
-  attribute \src "simple/issuer.py:49"
+  attribute \src "simple/issuer.py:54"
   wire width 64 output 2 \pc_o
-  attribute \src "simple/issuer.py:48"
-  wire width 1 input 3 \go_insn_i
+  attribute \src "simple/issuer.py:58"
+  wire width 1 input 3 \memerr_o
   attribute \src "simple/issuer.py:56"
-  wire width 1 input 4 \memerr_o
-  attribute \src "simple/issuer.py:51"
-  wire width 1 input 5 \core_start_i
-  attribute \src "simple/issuer.py:52"
-  wire width 1 input 6 \core_stop_i
-  attribute \src "simple/issuer.py:53"
-  wire width 1 input 7 \core_bigendian_i
-  attribute \src "simple/issuer.py:54"
-  wire width 1 output 8 \busy_o
-  attribute \src "simple/issuer.py:55"
-  wire width 1 output 9 \halted_o
+  wire width 1 input 4 \core_bigendian_i
+  attribute \src "simple/issuer.py:86"
+  wire width 1 input 5 \clk
+  attribute \src "simple/issuer.py:86"
+  wire width 1 input 6 \rst
+  attribute \src "simple/issuer.py:57"
+  wire width 1 output 7 \busy_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:55"
+  wire width 4 input 8 \dmi_addr_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:56"
+  wire width 64 input 9 \dmi_din
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:57"
+  wire width 64 output 10 \dmi_dout
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:58"
+  wire width 1 input 11 \dmi_req_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:59"
+  wire width 1 input 12 \dmi_we_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:60"
+  wire width 1 output 13 \dmi_ack_o
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
-  wire width 45 output 10 \ibus__adr
+  wire width 45 output 14 \ibus__adr
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
-  wire width 64 input 11 \ibus__dat_w
+  wire width 64 input 15 \ibus__dat_w
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
-  wire width 64 input 12 \ibus__dat_r
+  wire width 64 input 16 \ibus__dat_r
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
-  wire width 8 output 13 \ibus__sel
+  wire width 8 output 17 \ibus__sel
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
-  wire width 1 output 14 \ibus__cyc
+  wire width 1 output 18 \ibus__cyc
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
-  wire width 1 output 15 \ibus__stb
+  wire width 1 output 19 \ibus__stb
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
-  wire width 1 input 16 \ibus__ack
+  wire width 1 input 20 \ibus__ack
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
-  wire width 1 input 17 \ibus__we
+  wire width 1 input 21 \ibus__we
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
-  wire width 3 input 18 \ibus__cti
+  wire width 3 input 22 \ibus__cti
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
-  wire width 2 input 19 \ibus__bte
+  wire width 2 input 23 \ibus__bte
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20"
-  wire width 1 input 20 \ibus__err
+  wire width 1 input 24 \ibus__err
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
-  wire width 45 output 21 \dbus__adr
+  wire width 45 output 25 \dbus__adr
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
-  wire width 64 output 22 \dbus__dat_w
+  wire width 64 output 26 \dbus__dat_w
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
-  wire width 64 input 23 \dbus__dat_r
+  wire width 64 input 27 \dbus__dat_r
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
-  wire width 8 output 24 \dbus__sel
+  wire width 8 output 28 \dbus__sel
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
-  wire width 1 output 25 \dbus__cyc
+  wire width 1 output 29 \dbus__cyc
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
-  wire width 1 output 26 \dbus__stb
+  wire width 1 output 30 \dbus__stb
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
-  wire width 1 input 27 \dbus__ack
+  wire width 1 input 31 \dbus__ack
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
-  wire width 1 output 28 \dbus__we
+  wire width 1 output 32 \dbus__we
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
-  wire width 3 input 29 \dbus__cti
+  wire width 3 input 33 \dbus__cti
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
-  wire width 2 input 30 \dbus__bte
+  wire width 2 input 34 \dbus__bte
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:16"
-  wire width 1 input 31 \dbus__err
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 32 \clk
-  attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ir.py:526"
-  wire width 1 input 33 \rst
+  wire width 1 input 35 \dbus__err
+  attribute \src "simple/issuer.py:85"
+  wire width 1 \por_clk
+  attribute \src "simple/issuer.py:87"
+  wire width 1 \core_coresync_clk
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:80"
   wire width 1 \core_corebusy_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:89"
-  wire width 1 \core_core_terminated_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:87"
-  wire width 1 \core_core_start_i
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:88"
-  wire width 1 \core_core_stop_i
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:332"
   wire width 1 \core_bigendian
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:33"
@@ -157830,7 +176107,11 @@ module \test_issuer
   wire width 8 \core_cia__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \core_cia__data_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:571"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:88"
+  wire width 1 \core_core_reset_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:89"
+  wire width 1 \core_core_terminate_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:581"
   wire width 1 \core_valid
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:79"
   wire width 1 \core_issue_i
@@ -157840,10 +176121,10 @@ module \test_issuer
   wire width 8 \core_msr__ren
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \core_msr__data_o
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:574"
-  wire width 64 \core_msr
-  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575"
-  wire width 64 \core_cia
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:9"
+  wire width 64 \core_dec2_msr
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:8"
+  wire width 64 \core_dec2_pc
   attribute \enum_base_type "MicrOp"
   attribute \enum_value_0000000 "OP_ILLEGAL"
   attribute \enum_value_0000001 "OP_NOP"
@@ -157925,11 +176206,13 @@ module \test_issuer
   wire width 8 \core_wen
   attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
   wire width 64 \core_data_i
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 32 \core_dmi__ren
+  attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91"
+  wire width 64 \core_dmi__data_o
   cell \core \core
+    connect \coresync_clk \core_coresync_clk
     connect \corebusy_o \core_corebusy_o
-    connect \core_terminated_o \core_core_terminated_o
-    connect \core_start_i \core_core_start_i
-    connect \core_stop_i \core_core_stop_i
     connect \bigendian \core_bigendian
     connect \cu_ad__go_i \core_cu_ad__go_i
     connect \cu_ad__rel_o \core_cu_ad__rel_o
@@ -157937,19 +176220,21 @@ module \test_issuer
     connect \cu_st__rel_o \core_cu_st__rel_o
     connect \cia__ren \core_cia__ren
     connect \cia__data_o \core_cia__data_o
+    connect \core_reset_i \core_core_reset_i
+    connect \core_terminate_o \core_core_terminate_o
     connect \valid \core_valid
     connect \issue_i \core_issue_i
     connect \raw_opcode_in \core_raw_opcode_in
     connect \msr__ren \core_msr__ren
     connect \msr__data_o \core_msr__data_o
-    connect \msr \core_msr
-    connect \cia \core_cia
+    connect \dec2_msr \core_dec2_msr
+    connect \dec2_pc \core_dec2_pc
     connect \insn_type \core_insn_type
     connect \fast_nia_wen \core_fast_nia_wen
     connect \wen \core_wen
     connect \data_i \core_data_i
-    connect \rst \rst
-    connect \clk \clk
+    connect \dmi__ren \core_dmi__ren
+    connect \dmi__data_o \core_dmi__data_o
     connect \dbus__cyc \dbus__cyc
     connect \dbus__ack \dbus__ack
     connect \dbus__err \dbus__err
@@ -157971,13 +176256,13 @@ module \test_issuer
   attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:33"
   wire width 64 \imem_f_instr_o
   cell \imem \imem
+    connect \clk \clk
     connect \a_pc_i \imem_a_pc_i
     connect \a_valid_i \imem_a_valid_i
     connect \f_valid_i \imem_f_valid_i
     connect \f_busy_o \imem_f_busy_o
     connect \f_instr_o \imem_f_instr_o
     connect \rst \rst
-    connect \clk \clk
     connect \ibus__cyc \ibus__cyc
     connect \ibus__ack \ibus__ack
     connect \ibus__err \ibus__err
@@ -157986,24 +176271,102 @@ module \test_issuer
     connect \ibus__dat_r \ibus__dat_r
     connect \ibus__adr \ibus__adr
   end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:79"
+  wire width 1 \dbg_core_stop_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:80"
+  wire width 1 \dbg_core_rst_o
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:84"
+  wire width 1 \dbg_terminate_i
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:8"
+  wire width 64 \dbg_core_dbg_pc
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:9"
+  wire width 64 \dbg_core_dbg_msr
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:66"
+  wire width 1 \dbg_dbg_gpr_req
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:68"
+  wire width 7 \dbg_dbg_gpr_addr
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:69"
+  wire width 64 \dbg_dbg_gpr_data
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:67"
+  wire width 1 \dbg_dbg_gpr_ack
+  cell \dbg \dbg
+    connect \clk \clk
+    connect \core_stop_o \dbg_core_stop_o
+    connect \core_rst_o \dbg_core_rst_o
+    connect \terminate_i \dbg_terminate_i
+    connect \core_dbg_pc \dbg_core_dbg_pc
+    connect \core_dbg_msr \dbg_core_dbg_msr
+    connect \dbg_gpr_req \dbg_dbg_gpr_req
+    connect \dbg_gpr_addr \dbg_dbg_gpr_addr
+    connect \dbg_gpr_data \dbg_dbg_gpr_data
+    connect \dbg_gpr_ack \dbg_dbg_gpr_ack
+    connect \rst \rst
+    connect \dmi_ack_o \dmi_ack_o
+    connect \dmi_addr_i \dmi_addr_i
+    connect \dmi_req_i \dmi_req_i
+    connect \dmi_dout \dmi_dout
+    connect \dmi_we_i \dmi_we_i
+    connect \dmi_din \dmi_din
+  end
+  attribute \src "simple/issuer.py:90"
+  wire width 2 \delay
+  attribute \src "simple/issuer.py:90"
+  wire width 2 \delay$next
+  attribute \src "simple/issuer.py:91"
+  wire width 1 $1
+  attribute \src "simple/issuer.py:91"
+  cell $ne $2
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 2
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \delay
+    connect \B 1'0
+    connect \Y $1
+  end
+  attribute \src "simple/issuer.py:92"
+  wire width 3 $3
+  attribute \src "simple/issuer.py:92"
+  wire width 3 $4
+  attribute \src "simple/issuer.py:92"
+  cell $sub $5
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 2
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 3
+    connect \A \delay
+    connect \B 1'1
+    connect \Y $4
+  end
+  connect $3 $4
   process $group_0
-    assign \busy_o 1'0
-    assign \busy_o \core_corebusy_o
+    assign \delay$next \delay
+    attribute \src "simple/issuer.py:91"
+    switch { $1 }
+      attribute \src "simple/issuer.py:91"
+      case 1'1
+        assign \delay$next $3 [1:0]
+    end
     sync init
+      update \delay 2'01
+    sync posedge \por_clk
+      update \delay \delay$next
   end
   process $group_1
-    assign \halted_o 1'0
-    assign \halted_o \core_core_terminated_o
+    assign \por_clk 1'0
+    assign \por_clk \clk
     sync init
   end
   process $group_2
-    assign \core_core_start_i 1'0
-    assign \core_core_start_i \core_start_i
+    assign \core_coresync_clk 1'0
+    assign \core_coresync_clk \clk
     sync init
   end
   process $group_3
-    assign \core_core_stop_i 1'0
-    assign \core_core_stop_i \core_stop_i
+    assign \busy_o 1'0
+    assign \busy_o \core_corebusy_o
     sync init
   end
   process $group_4
@@ -158021,23 +176384,23 @@ module \test_issuer
     assign \core_cu_st__go_i \core_cu_st__rel_o
     sync init
   end
-  attribute \src "simple/issuer.py:89"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:8"
   wire width 64 \cur_pc
-  attribute \src "simple/issuer.py:89"
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:8"
   wire width 64 \cur_pc$next
   process $group_7
     assign \pc_o 64'0000000000000000000000000000000000000000000000000000000000000000
     assign \pc_o \cur_pc
     sync init
   end
-  attribute \src "simple/issuer.py:99"
+  attribute \src "simple/issuer.py:121"
   wire width 64 \nia
-  attribute \src "simple/issuer.py:100"
-  wire width 65 $1
-  attribute \src "simple/issuer.py:100"
-  wire width 65 $2
-  attribute \src "simple/issuer.py:100"
-  cell $add $3
+  attribute \src "simple/issuer.py:122"
+  wire width 65 $6
+  attribute \src "simple/issuer.py:122"
+  wire width 65 $7
+  attribute \src "simple/issuer.py:122"
+  cell $add $8
     parameter \A_SIGNED 0
     parameter \A_WIDTH 64
     parameter \B_SIGNED 0
@@ -158045,73 +176408,109 @@ module \test_issuer
     parameter \Y_WIDTH 65
     connect \A \cur_pc
     connect \B 3'100
-    connect \Y $2
+    connect \Y $7
   end
-  connect $1 $2
+  connect $6 $7
   process $group_8
     assign \nia 64'0000000000000000000000000000000000000000000000000000000000000000
-    assign \nia $1 [63:0]
+    assign \nia $6 [63:0]
     sync init
   end
-  attribute \src "simple/issuer.py:90"
+  attribute \src "simple/issuer.py:125"
+  wire width 64 \pc
+  process $group_9
+    assign \pc 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "simple/issuer.py:126"
+    switch { \pc_i_ok }
+      attribute \src "simple/issuer.py:126"
+      case 1'1
+        assign \pc \pc_i
+      attribute \src "simple/issuer.py:129"
+      case
+        assign \pc \core_cia__data_o
+    end
+    sync init
+  end
+  process $group_10
+    assign \core_cia__ren 8'00000000
+    attribute \src "simple/issuer.py:126"
+    switch { \pc_i_ok }
+      attribute \src "simple/issuer.py:126"
+      case 1'1
+      attribute \src "simple/issuer.py:129"
+      case
+        assign \core_cia__ren 8'00000001
+    end
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:87"
+  wire width 1 \core_stopped_i
+  process $group_11
+    assign \core_stopped_i 1'0
+    assign \core_stopped_i \dbg_core_stop_o
+    sync init
+  end
+  process $group_12
+    assign \core_core_reset_i 1'0
+    assign \core_core_reset_i \dbg_core_rst_o
+    sync init
+  end
+  process $group_13
+    assign \dbg_terminate_i 1'0
+    assign \dbg_terminate_i \core_core_terminate_o
+    sync init
+  end
+  process $group_14
+    assign \dbg_core_dbg_pc 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \dbg_core_dbg_pc \pc
+    sync init
+  end
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:9"
+  wire width 64 \cur_msr
+  attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:9"
+  wire width 64 \cur_msr$next
+  process $group_15
+    assign \dbg_core_dbg_msr 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \dbg_core_dbg_msr \cur_msr
+    sync init
+  end
+  attribute \src "simple/issuer.py:113"
   wire width 1 \pc_changed
-  attribute \src "simple/issuer.py:90"
+  attribute \src "simple/issuer.py:113"
   wire width 1 \pc_changed$next
-  attribute \src "simple/issuer.py:114"
-  wire width 1 $4
-  attribute \src "simple/issuer.py:114"
-  cell $not $5
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \core_core_terminated_o
-    connect \Y $4
-  end
-  attribute \src "simple/issuer.py:121"
+  attribute \src "simple/issuer.py:157"
   wire width 2 \fsm_state
-  attribute \src "simple/issuer.py:121"
+  attribute \src "simple/issuer.py:157"
   wire width 2 \fsm_state$next
   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
-  wire width 1 $6
+  wire width 1 $9
   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438"
-  cell $reduce_bool $7
+  cell $reduce_bool $10
     parameter \A_SIGNED 0
     parameter \A_WIDTH 8
     parameter \Y_WIDTH 1
     connect \A \core_fast_nia_wen
-    connect \Y $6
+    connect \Y $9
   end
-  process $group_9
+  process $group_16
     assign \pc_changed$next \pc_changed
-    attribute \src "simple/issuer.py:114"
-    switch { $4 }
-      attribute \src "simple/issuer.py:114"
-      case 1'1
-        attribute \src "simple/issuer.py:121"
-        switch \fsm_state
-          attribute \src "simple/issuer.py:124"
-          attribute \nmigen.decoding "IDLE/0"
-          case 2'00
-            assign \pc_changed$next 1'0
-          attribute \src "simple/issuer.py:146"
-          attribute \nmigen.decoding "INSN_READ/1"
-          case 2'01
-          attribute \src "simple/issuer.py:176"
-          attribute \nmigen.decoding "INSN_ACTIVE/2"
-          case 2'10
-            attribute \src "simple/issuer.py:177"
-            switch { \core_core_terminated_o }
-              attribute \src "simple/issuer.py:177"
-              case 1'1
-              attribute \src "simple/issuer.py:179"
-              case
-                attribute \src "simple/issuer.py:185"
-                switch { $6 }
-                  attribute \src "simple/issuer.py:185"
-                  case 1'1
-                    assign \pc_changed$next 1'1
-                end
-            end
+    attribute \src "simple/issuer.py:157"
+    switch \fsm_state
+      attribute \src "simple/issuer.py:160"
+      attribute \nmigen.decoding "IDLE/0"
+      case 2'00
+        assign \pc_changed$next 1'0
+      attribute \src "simple/issuer.py:174"
+      attribute \nmigen.decoding "INSN_READ/1"
+      case 2'01
+      attribute \src "simple/issuer.py:204"
+      attribute \nmigen.decoding "INSN_ACTIVE/2"
+      case 2'10
+        attribute \src "simple/issuer.py:209"
+        switch { $9 }
+          attribute \src "simple/issuer.py:209"
+          case 1'1
+            assign \pc_changed$next 1'1
         end
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
@@ -158124,258 +176523,147 @@ module \test_issuer
     sync posedge \clk
       update \pc_changed \pc_changed$next
   end
-  attribute \src "simple/issuer.py:128"
-  wire width 64 \pc
-  attribute \src "simple/issuer.py:114"
-  wire width 1 $8
-  attribute \src "simple/issuer.py:114"
-  cell $not $9
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \core_core_terminated_o
-    connect \Y $8
-  end
-  process $group_10
-    assign \pc 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "simple/issuer.py:114"
-    switch { $8 }
-      attribute \src "simple/issuer.py:114"
-      case 1'1
-        attribute \src "simple/issuer.py:121"
-        switch \fsm_state
-          attribute \src "simple/issuer.py:124"
-          attribute \nmigen.decoding "IDLE/0"
-          case 2'00
-            attribute \src "simple/issuer.py:126"
-            switch { \go_insn_i }
-              attribute \src "simple/issuer.py:126"
-              case 1'1
-                attribute \src "simple/issuer.py:129"
-                switch { \pc_i_ok }
-                  attribute \src "simple/issuer.py:129"
-                  case 1'1
-                    assign \pc \pc_i
-                  attribute \src "simple/issuer.py:132"
-                  case
-                    assign \pc \core_cia__data_o
-                end
-            end
-          attribute \src "simple/issuer.py:146"
-          attribute \nmigen.decoding "INSN_READ/1"
-          case 2'01
-          attribute \src "simple/issuer.py:176"
-          attribute \nmigen.decoding "INSN_ACTIVE/2"
-          case 2'10
-        end
-    end
-    sync init
-  end
-  attribute \src "simple/issuer.py:114"
-  wire width 1 $10
-  attribute \src "simple/issuer.py:114"
-  cell $not $11
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \core_core_terminated_o
-    connect \Y $10
-  end
-  process $group_11
-    assign \core_cia__ren 8'00000000
-    attribute \src "simple/issuer.py:114"
-    switch { $10 }
-      attribute \src "simple/issuer.py:114"
-      case 1'1
-        attribute \src "simple/issuer.py:121"
-        switch \fsm_state
-          attribute \src "simple/issuer.py:124"
-          attribute \nmigen.decoding "IDLE/0"
-          case 2'00
-            attribute \src "simple/issuer.py:126"
-            switch { \go_insn_i }
-              attribute \src "simple/issuer.py:126"
-              case 1'1
-                attribute \src "simple/issuer.py:129"
-                switch { \pc_i_ok }
-                  attribute \src "simple/issuer.py:129"
-                  case 1'1
-                  attribute \src "simple/issuer.py:132"
-                  case
-                    assign \core_cia__ren 8'00000001
-                end
-            end
-          attribute \src "simple/issuer.py:146"
-          attribute \nmigen.decoding "INSN_READ/1"
-          case 2'01
-          attribute \src "simple/issuer.py:176"
-          attribute \nmigen.decoding "INSN_ACTIVE/2"
-          case 2'10
-        end
-    end
-    sync init
-  end
-  attribute \src "simple/issuer.py:114"
-  wire width 1 $12
-  attribute \src "simple/issuer.py:114"
-  cell $not $13
+  attribute \src "simple/issuer.py:162"
+  wire width 1 $11
+  attribute \src "simple/issuer.py:162"
+  cell $not $12
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \core_core_terminated_o
-    connect \Y $12
+    connect \A \dbg_core_stop_o
+    connect \Y $11
   end
-  process $group_12
+  process $group_17
     assign \imem_a_pc_i 48'000000000000000000000000000000000000000000000000
-    attribute \src "simple/issuer.py:114"
-    switch { $12 }
-      attribute \src "simple/issuer.py:114"
-      case 1'1
-        attribute \src "simple/issuer.py:121"
-        switch \fsm_state
-          attribute \src "simple/issuer.py:124"
-          attribute \nmigen.decoding "IDLE/0"
-          case 2'00
-            attribute \src "simple/issuer.py:126"
-            switch { \go_insn_i }
-              attribute \src "simple/issuer.py:126"
-              case 1'1
-                assign \imem_a_pc_i \pc [47:0]
-            end
-          attribute \src "simple/issuer.py:146"
-          attribute \nmigen.decoding "INSN_READ/1"
-          case 2'01
-          attribute \src "simple/issuer.py:176"
-          attribute \nmigen.decoding "INSN_ACTIVE/2"
-          case 2'10
+    attribute \src "simple/issuer.py:157"
+    switch \fsm_state
+      attribute \src "simple/issuer.py:160"
+      attribute \nmigen.decoding "IDLE/0"
+      case 2'00
+        attribute \src "simple/issuer.py:162"
+        switch { $11 }
+          attribute \src "simple/issuer.py:162"
+          case 1'1
+            assign \imem_a_pc_i \pc [47:0]
         end
+      attribute \src "simple/issuer.py:174"
+      attribute \nmigen.decoding "INSN_READ/1"
+      case 2'01
+      attribute \src "simple/issuer.py:204"
+      attribute \nmigen.decoding "INSN_ACTIVE/2"
+      case 2'10
     end
     sync init
   end
-  attribute \src "simple/issuer.py:114"
-  wire width 1 $14
-  attribute \src "simple/issuer.py:114"
-  cell $not $15
+  attribute \src "simple/issuer.py:162"
+  wire width 1 $13
+  attribute \src "simple/issuer.py:162"
+  cell $not $14
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \core_core_terminated_o
-    connect \Y $14
+    connect \A \dbg_core_stop_o
+    connect \Y $13
   end
-  process $group_13
+  process $group_18
     assign \imem_a_valid_i 1'0
-    attribute \src "simple/issuer.py:114"
-    switch { $14 }
-      attribute \src "simple/issuer.py:114"
-      case 1'1
-        attribute \src "simple/issuer.py:121"
-        switch \fsm_state
-          attribute \src "simple/issuer.py:124"
-          attribute \nmigen.decoding "IDLE/0"
-          case 2'00
-            attribute \src "simple/issuer.py:126"
-            switch { \go_insn_i }
-              attribute \src "simple/issuer.py:126"
-              case 1'1
-                assign \imem_a_valid_i 1'1
-            end
-          attribute \src "simple/issuer.py:146"
-          attribute \nmigen.decoding "INSN_READ/1"
-          case 2'01
-            attribute \src "simple/issuer.py:147"
-            switch { \imem_f_busy_o }
-              attribute \src "simple/issuer.py:147"
-              case 1'1
-                assign \imem_a_valid_i 1'1
-              attribute \src "simple/issuer.py:151"
-              case
-            end
-          attribute \src "simple/issuer.py:176"
-          attribute \nmigen.decoding "INSN_ACTIVE/2"
-          case 2'10
+    attribute \src "simple/issuer.py:157"
+    switch \fsm_state
+      attribute \src "simple/issuer.py:160"
+      attribute \nmigen.decoding "IDLE/0"
+      case 2'00
+        attribute \src "simple/issuer.py:162"
+        switch { $13 }
+          attribute \src "simple/issuer.py:162"
+          case 1'1
+            assign \imem_a_valid_i 1'1
+        end
+      attribute \src "simple/issuer.py:174"
+      attribute \nmigen.decoding "INSN_READ/1"
+      case 2'01
+        attribute \src "simple/issuer.py:175"
+        switch { \imem_f_busy_o }
+          attribute \src "simple/issuer.py:175"
+          case 1'1
+            assign \imem_a_valid_i 1'1
+          attribute \src "simple/issuer.py:179"
+          case
         end
+      attribute \src "simple/issuer.py:204"
+      attribute \nmigen.decoding "INSN_ACTIVE/2"
+      case 2'10
     end
     sync init
   end
-  attribute \src "simple/issuer.py:114"
-  wire width 1 $16
-  attribute \src "simple/issuer.py:114"
-  cell $not $17
+  attribute \src "simple/issuer.py:162"
+  wire width 1 $15
+  attribute \src "simple/issuer.py:162"
+  cell $not $16
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \core_core_terminated_o
-    connect \Y $16
+    connect \A \dbg_core_stop_o
+    connect \Y $15
   end
-  process $group_14
+  process $group_19
     assign \imem_f_valid_i 1'0
-    attribute \src "simple/issuer.py:114"
-    switch { $16 }
-      attribute \src "simple/issuer.py:114"
-      case 1'1
-        attribute \src "simple/issuer.py:121"
-        switch \fsm_state
-          attribute \src "simple/issuer.py:124"
-          attribute \nmigen.decoding "IDLE/0"
-          case 2'00
-            attribute \src "simple/issuer.py:126"
-            switch { \go_insn_i }
-              attribute \src "simple/issuer.py:126"
-              case 1'1
-                assign \imem_f_valid_i 1'1
-            end
-          attribute \src "simple/issuer.py:146"
-          attribute \nmigen.decoding "INSN_READ/1"
-          case 2'01
-            attribute \src "simple/issuer.py:147"
-            switch { \imem_f_busy_o }
-              attribute \src "simple/issuer.py:147"
-              case 1'1
-                assign \imem_f_valid_i 1'1
-              attribute \src "simple/issuer.py:151"
-              case
-            end
-          attribute \src "simple/issuer.py:176"
-          attribute \nmigen.decoding "INSN_ACTIVE/2"
-          case 2'10
+    attribute \src "simple/issuer.py:157"
+    switch \fsm_state
+      attribute \src "simple/issuer.py:160"
+      attribute \nmigen.decoding "IDLE/0"
+      case 2'00
+        attribute \src "simple/issuer.py:162"
+        switch { $15 }
+          attribute \src "simple/issuer.py:162"
+          case 1'1
+            assign \imem_f_valid_i 1'1
+        end
+      attribute \src "simple/issuer.py:174"
+      attribute \nmigen.decoding "INSN_READ/1"
+      case 2'01
+        attribute \src "simple/issuer.py:175"
+        switch { \imem_f_busy_o }
+          attribute \src "simple/issuer.py:175"
+          case 1'1
+            assign \imem_f_valid_i 1'1
+          attribute \src "simple/issuer.py:179"
+          case
         end
+      attribute \src "simple/issuer.py:204"
+      attribute \nmigen.decoding "INSN_ACTIVE/2"
+      case 2'10
     end
     sync init
   end
-  attribute \src "simple/issuer.py:114"
-  wire width 1 $18
-  attribute \src "simple/issuer.py:114"
-  cell $not $19
+  attribute \src "simple/issuer.py:162"
+  wire width 1 $17
+  attribute \src "simple/issuer.py:162"
+  cell $not $18
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \core_core_terminated_o
-    connect \Y $18
+    connect \A \dbg_core_stop_o
+    connect \Y $17
   end
-  process $group_15
+  process $group_20
     assign \cur_pc$next \cur_pc
-    attribute \src "simple/issuer.py:114"
-    switch { $18 }
-      attribute \src "simple/issuer.py:114"
-      case 1'1
-        attribute \src "simple/issuer.py:121"
-        switch \fsm_state
-          attribute \src "simple/issuer.py:124"
-          attribute \nmigen.decoding "IDLE/0"
-          case 2'00
-            attribute \src "simple/issuer.py:126"
-            switch { \go_insn_i }
-              attribute \src "simple/issuer.py:126"
-              case 1'1
-                assign \cur_pc$next \pc
-            end
-          attribute \src "simple/issuer.py:146"
-          attribute \nmigen.decoding "INSN_READ/1"
-          case 2'01
-          attribute \src "simple/issuer.py:176"
-          attribute \nmigen.decoding "INSN_ACTIVE/2"
-          case 2'10
+    attribute \src "simple/issuer.py:157"
+    switch \fsm_state
+      attribute \src "simple/issuer.py:160"
+      attribute \nmigen.decoding "IDLE/0"
+      case 2'00
+        attribute \src "simple/issuer.py:162"
+        switch { $17 }
+          attribute \src "simple/issuer.py:162"
+          case 1'1
+            assign \cur_pc$next \pc
         end
+      attribute \src "simple/issuer.py:174"
+      attribute \nmigen.decoding "INSN_READ/1"
+      case 2'01
+      attribute \src "simple/issuer.py:204"
+      attribute \nmigen.decoding "INSN_ACTIVE/2"
+      case 2'10
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
     switch \rst
@@ -158387,71 +176675,58 @@ module \test_issuer
     sync posedge \clk
       update \cur_pc \cur_pc$next
   end
-  attribute \src "simple/issuer.py:114"
-  wire width 1 $20
-  attribute \src "simple/issuer.py:114"
-  cell $not $21
+  attribute \src "simple/issuer.py:162"
+  wire width 1 $19
+  attribute \src "simple/issuer.py:162"
+  cell $not $20
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
-    connect \A \core_core_terminated_o
-    connect \Y $20
+    connect \A \dbg_core_stop_o
+    connect \Y $19
   end
-  attribute \src "simple/issuer.py:187"
-  wire width 1 $22
-  attribute \src "simple/issuer.py:187"
-  cell $not $23
+  attribute \src "simple/issuer.py:211"
+  wire width 1 $21
+  attribute \src "simple/issuer.py:211"
+  cell $not $22
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \core_corebusy_o
-    connect \Y $22
+    connect \Y $21
   end
-  process $group_16
+  process $group_21
     assign \fsm_state$next \fsm_state
-    attribute \src "simple/issuer.py:114"
-    switch { $20 }
-      attribute \src "simple/issuer.py:114"
-      case 1'1
-        attribute \src "simple/issuer.py:121"
-        switch \fsm_state
-          attribute \src "simple/issuer.py:124"
-          attribute \nmigen.decoding "IDLE/0"
-          case 2'00
-            attribute \src "simple/issuer.py:126"
-            switch { \go_insn_i }
-              attribute \src "simple/issuer.py:126"
-              case 1'1
-                assign \fsm_state$next 2'01
-            end
-          attribute \src "simple/issuer.py:146"
-          attribute \nmigen.decoding "INSN_READ/1"
-          case 2'01
-            attribute \src "simple/issuer.py:147"
-            switch { \imem_f_busy_o }
-              attribute \src "simple/issuer.py:147"
-              case 1'1
-              attribute \src "simple/issuer.py:151"
-              case
-                assign \fsm_state$next 2'10
-            end
-          attribute \src "simple/issuer.py:176"
-          attribute \nmigen.decoding "INSN_ACTIVE/2"
-          case 2'10
-            attribute \src "simple/issuer.py:177"
-            switch { \core_core_terminated_o }
-              attribute \src "simple/issuer.py:177"
-              case 1'1
-                assign \fsm_state$next 2'00
-              attribute \src "simple/issuer.py:179"
-              case
-                attribute \src "simple/issuer.py:187"
-                switch { $22 }
-                  attribute \src "simple/issuer.py:187"
-                  case 1'1
-                    assign \fsm_state$next 2'00
-                end
-            end
+    attribute \src "simple/issuer.py:157"
+    switch \fsm_state
+      attribute \src "simple/issuer.py:160"
+      attribute \nmigen.decoding "IDLE/0"
+      case 2'00
+        attribute \src "simple/issuer.py:162"
+        switch { $19 }
+          attribute \src "simple/issuer.py:162"
+          case 1'1
+            assign \fsm_state$next 2'01
+        end
+      attribute \src "simple/issuer.py:174"
+      attribute \nmigen.decoding "INSN_READ/1"
+      case 2'01
+        attribute \src "simple/issuer.py:175"
+        switch { \imem_f_busy_o }
+          attribute \src "simple/issuer.py:175"
+          case 1'1
+          attribute \src "simple/issuer.py:179"
+          case
+            assign \fsm_state$next 2'10
+        end
+      attribute \src "simple/issuer.py:204"
+      attribute \nmigen.decoding "INSN_ACTIVE/2"
+      case 2'10
+        attribute \src "simple/issuer.py:211"
+        switch { $21 }
+          attribute \src "simple/issuer.py:211"
+          case 1'1
+            assign \fsm_state$next 2'00
         end
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
@@ -158464,24 +176739,14 @@ module \test_issuer
     sync posedge \clk
       update \fsm_state \fsm_state$next
   end
-  attribute \src "simple/issuer.py:88"
+  attribute \src "simple/issuer.py:112"
   wire width 32 \current_insn
-  attribute \src "simple/issuer.py:114"
-  wire width 1 $24
-  attribute \src "simple/issuer.py:114"
-  cell $not $25
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \core_core_terminated_o
-    connect \Y $24
-  end
-  attribute \src "simple/issuer.py:157"
-  wire width 32 $26
+  attribute \src "simple/issuer.py:185"
+  wire width 32 $23
   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609"
-  wire width 7 $27
+  wire width 7 $24
   attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609"
-  cell $mul $28
+  cell $mul $25
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \B_SIGNED 0
@@ -158489,62 +176754,47 @@ module \test_issuer
     parameter \Y_WIDTH 7
     connect \A \cur_pc [2]
     connect \B 6'100000
-    connect \Y $27
+    connect \Y $24
   end
-  attribute \src "simple/issuer.py:157"
-  cell $shift $29
+  attribute \src "simple/issuer.py:185"
+  cell $shift $26
     parameter \A_SIGNED 0
     parameter \A_WIDTH 64
     parameter \B_SIGNED 0
     parameter \B_WIDTH 7
     parameter \Y_WIDTH 32
     connect \A \imem_f_instr_o
-    connect \B $27
-    connect \Y $26
+    connect \B $24
+    connect \Y $23
   end
-  process $group_17
+  process $group_22
     assign \current_insn 32'00000000000000000000000000000000
-    attribute \src "simple/issuer.py:114"
-    switch { $24 }
-      attribute \src "simple/issuer.py:114"
-      case 1'1
-        attribute \src "simple/issuer.py:121"
-        switch \fsm_state
-          attribute \src "simple/issuer.py:124"
-          attribute \nmigen.decoding "IDLE/0"
-          case 2'00
-          attribute \src "simple/issuer.py:146"
-          attribute \nmigen.decoding "INSN_READ/1"
-          case 2'01
-            attribute \src "simple/issuer.py:147"
-            switch { \imem_f_busy_o }
-              attribute \src "simple/issuer.py:147"
-              case 1'1
-              attribute \src "simple/issuer.py:151"
-              case
-                assign \current_insn $26
-            end
-          attribute \src "simple/issuer.py:176"
-          attribute \nmigen.decoding "INSN_ACTIVE/2"
-          case 2'10
+    attribute \src "simple/issuer.py:157"
+    switch \fsm_state
+      attribute \src "simple/issuer.py:160"
+      attribute \nmigen.decoding "IDLE/0"
+      case 2'00
+      attribute \src "simple/issuer.py:174"
+      attribute \nmigen.decoding "INSN_READ/1"
+      case 2'01
+        attribute \src "simple/issuer.py:175"
+        switch { \imem_f_busy_o }
+          attribute \src "simple/issuer.py:175"
+          case 1'1
+          attribute \src "simple/issuer.py:179"
+          case
+            assign \current_insn $23
         end
+      attribute \src "simple/issuer.py:204"
+      attribute \nmigen.decoding "INSN_ACTIVE/2"
+      case 2'10
     end
     sync init
   end
-  attribute \src "simple/issuer.py:114"
-  wire width 1 $30
-  attribute \src "simple/issuer.py:114"
-  cell $not $31
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \core_core_terminated_o
-    connect \Y $30
-  end
-  attribute \src "simple/issuer.py:180"
-  wire width 1 $32
-  attribute \src "simple/issuer.py:180"
-  cell $ne $33
+  attribute \src "simple/issuer.py:205"
+  wire width 1 $27
+  attribute \src "simple/issuer.py:205"
+  cell $ne $28
     parameter \A_SIGNED 0
     parameter \A_WIDTH 7
     parameter \B_SIGNED 0
@@ -158552,176 +176802,112 @@ module \test_issuer
     parameter \Y_WIDTH 1
     connect \A \core_insn_type
     connect \B 7'0000001
-    connect \Y $32
+    connect \Y $27
   end
-  process $group_18
+  process $group_23
     assign \core_valid 1'0
-    attribute \src "simple/issuer.py:114"
-    switch { $30 }
-      attribute \src "simple/issuer.py:114"
-      case 1'1
-        attribute \src "simple/issuer.py:121"
-        switch \fsm_state
-          attribute \src "simple/issuer.py:124"
-          attribute \nmigen.decoding "IDLE/0"
-          case 2'00
-          attribute \src "simple/issuer.py:146"
-          attribute \nmigen.decoding "INSN_READ/1"
-          case 2'01
-            attribute \src "simple/issuer.py:147"
-            switch { \imem_f_busy_o }
-              attribute \src "simple/issuer.py:147"
-              case 1'1
-              attribute \src "simple/issuer.py:151"
-              case
-                assign \core_valid 1'1
-            end
-          attribute \src "simple/issuer.py:176"
-          attribute \nmigen.decoding "INSN_ACTIVE/2"
-          case 2'10
-            attribute \src "simple/issuer.py:177"
-            switch { \core_core_terminated_o }
-              attribute \src "simple/issuer.py:177"
-              case 1'1
-              attribute \src "simple/issuer.py:179"
-              case
-                attribute \src "simple/issuer.py:180"
-                switch { $32 }
-                  attribute \src "simple/issuer.py:180"
-                  case 1'1
-                    assign \core_valid 1'1
-                end
-            end
+    attribute \src "simple/issuer.py:157"
+    switch \fsm_state
+      attribute \src "simple/issuer.py:160"
+      attribute \nmigen.decoding "IDLE/0"
+      case 2'00
+      attribute \src "simple/issuer.py:174"
+      attribute \nmigen.decoding "INSN_READ/1"
+      case 2'01
+        attribute \src "simple/issuer.py:175"
+        switch { \imem_f_busy_o }
+          attribute \src "simple/issuer.py:175"
+          case 1'1
+          attribute \src "simple/issuer.py:179"
+          case
+            assign \core_valid 1'1
+        end
+      attribute \src "simple/issuer.py:204"
+      attribute \nmigen.decoding "INSN_ACTIVE/2"
+      case 2'10
+        attribute \src "simple/issuer.py:205"
+        switch { $27 }
+          attribute \src "simple/issuer.py:205"
+          case 1'1
+            assign \core_valid 1'1
         end
     end
     sync init
   end
-  attribute \src "simple/issuer.py:114"
-  wire width 1 $34
-  attribute \src "simple/issuer.py:114"
-  cell $not $35
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \core_core_terminated_o
-    connect \Y $34
-  end
-  process $group_19
+  process $group_24
     assign \core_issue_i 1'0
-    attribute \src "simple/issuer.py:114"
-    switch { $34 }
-      attribute \src "simple/issuer.py:114"
-      case 1'1
-        attribute \src "simple/issuer.py:121"
-        switch \fsm_state
-          attribute \src "simple/issuer.py:124"
-          attribute \nmigen.decoding "IDLE/0"
-          case 2'00
-          attribute \src "simple/issuer.py:146"
-          attribute \nmigen.decoding "INSN_READ/1"
-          case 2'01
-            attribute \src "simple/issuer.py:147"
-            switch { \imem_f_busy_o }
-              attribute \src "simple/issuer.py:147"
-              case 1'1
-              attribute \src "simple/issuer.py:151"
-              case
-                assign \core_issue_i 1'1
-            end
-          attribute \src "simple/issuer.py:176"
-          attribute \nmigen.decoding "INSN_ACTIVE/2"
-          case 2'10
+    attribute \src "simple/issuer.py:157"
+    switch \fsm_state
+      attribute \src "simple/issuer.py:160"
+      attribute \nmigen.decoding "IDLE/0"
+      case 2'00
+      attribute \src "simple/issuer.py:174"
+      attribute \nmigen.decoding "INSN_READ/1"
+      case 2'01
+        attribute \src "simple/issuer.py:175"
+        switch { \imem_f_busy_o }
+          attribute \src "simple/issuer.py:175"
+          case 1'1
+          attribute \src "simple/issuer.py:179"
+          case
+            assign \core_issue_i 1'1
         end
+      attribute \src "simple/issuer.py:204"
+      attribute \nmigen.decoding "INSN_ACTIVE/2"
+      case 2'10
     end
     sync init
   end
-  attribute \src "simple/issuer.py:114"
-  wire width 1 $36
-  attribute \src "simple/issuer.py:114"
-  cell $not $37
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \core_core_terminated_o
-    connect \Y $36
-  end
-  attribute \src "simple/issuer.py:92"
+  attribute \src "simple/issuer.py:115"
   wire width 32 \ilatch
-  attribute \src "simple/issuer.py:92"
+  attribute \src "simple/issuer.py:115"
   wire width 32 \ilatch$next
-  process $group_20
+  process $group_25
     assign \core_raw_opcode_in 32'00000000000000000000000000000000
-    attribute \src "simple/issuer.py:114"
-    switch { $36 }
-      attribute \src "simple/issuer.py:114"
-      case 1'1
-        attribute \src "simple/issuer.py:121"
-        switch \fsm_state
-          attribute \src "simple/issuer.py:124"
-          attribute \nmigen.decoding "IDLE/0"
-          case 2'00
-          attribute \src "simple/issuer.py:146"
-          attribute \nmigen.decoding "INSN_READ/1"
-          case 2'01
-            attribute \src "simple/issuer.py:147"
-            switch { \imem_f_busy_o }
-              attribute \src "simple/issuer.py:147"
-              case 1'1
-              attribute \src "simple/issuer.py:151"
-              case
-                assign \core_raw_opcode_in \current_insn
-            end
-          attribute \src "simple/issuer.py:176"
-          attribute \nmigen.decoding "INSN_ACTIVE/2"
-          case 2'10
-            attribute \src "simple/issuer.py:177"
-            switch { \core_core_terminated_o }
-              attribute \src "simple/issuer.py:177"
-              case 1'1
-              attribute \src "simple/issuer.py:179"
-              case
-                assign \core_raw_opcode_in \ilatch
-            end
+    attribute \src "simple/issuer.py:157"
+    switch \fsm_state
+      attribute \src "simple/issuer.py:160"
+      attribute \nmigen.decoding "IDLE/0"
+      case 2'00
+      attribute \src "simple/issuer.py:174"
+      attribute \nmigen.decoding "INSN_READ/1"
+      case 2'01
+        attribute \src "simple/issuer.py:175"
+        switch { \imem_f_busy_o }
+          attribute \src "simple/issuer.py:175"
+          case 1'1
+          attribute \src "simple/issuer.py:179"
+          case
+            assign \core_raw_opcode_in \current_insn
         end
+      attribute \src "simple/issuer.py:204"
+      attribute \nmigen.decoding "INSN_ACTIVE/2"
+      case 2'10
+        assign \core_raw_opcode_in \ilatch
     end
     sync init
   end
-  attribute \src "simple/issuer.py:114"
-  wire width 1 $38
-  attribute \src "simple/issuer.py:114"
-  cell $not $39
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \core_core_terminated_o
-    connect \Y $38
-  end
-  process $group_21
+  process $group_26
     assign \ilatch$next \ilatch
-    attribute \src "simple/issuer.py:114"
-    switch { $38 }
-      attribute \src "simple/issuer.py:114"
-      case 1'1
-        attribute \src "simple/issuer.py:121"
-        switch \fsm_state
-          attribute \src "simple/issuer.py:124"
-          attribute \nmigen.decoding "IDLE/0"
-          case 2'00
-          attribute \src "simple/issuer.py:146"
-          attribute \nmigen.decoding "INSN_READ/1"
-          case 2'01
-            attribute \src "simple/issuer.py:147"
-            switch { \imem_f_busy_o }
-              attribute \src "simple/issuer.py:147"
-              case 1'1
-              attribute \src "simple/issuer.py:151"
-              case
-                assign \ilatch$next \current_insn
-            end
-          attribute \src "simple/issuer.py:176"
-          attribute \nmigen.decoding "INSN_ACTIVE/2"
-          case 2'10
+    attribute \src "simple/issuer.py:157"
+    switch \fsm_state
+      attribute \src "simple/issuer.py:160"
+      attribute \nmigen.decoding "IDLE/0"
+      case 2'00
+      attribute \src "simple/issuer.py:174"
+      attribute \nmigen.decoding "INSN_READ/1"
+      case 2'01
+        attribute \src "simple/issuer.py:175"
+        switch { \imem_f_busy_o }
+          attribute \src "simple/issuer.py:175"
+          case 1'1
+          attribute \src "simple/issuer.py:179"
+          case
+            assign \ilatch$next \current_insn
         end
+      attribute \src "simple/issuer.py:204"
+      attribute \nmigen.decoding "INSN_ACTIVE/2"
+      case 2'10
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
     switch \rst
@@ -158733,173 +176919,104 @@ module \test_issuer
     sync posedge \clk
       update \ilatch \ilatch$next
   end
-  attribute \src "simple/issuer.py:114"
-  wire width 1 $40
-  attribute \src "simple/issuer.py:114"
-  cell $not $41
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \core_core_terminated_o
-    connect \Y $40
-  end
-  process $group_22
+  process $group_27
     assign \core_msr__ren 8'00000000
-    attribute \src "simple/issuer.py:114"
-    switch { $40 }
-      attribute \src "simple/issuer.py:114"
-      case 1'1
-        attribute \src "simple/issuer.py:121"
-        switch \fsm_state
-          attribute \src "simple/issuer.py:124"
-          attribute \nmigen.decoding "IDLE/0"
-          case 2'00
-          attribute \src "simple/issuer.py:146"
-          attribute \nmigen.decoding "INSN_READ/1"
-          case 2'01
-            attribute \src "simple/issuer.py:147"
-            switch { \imem_f_busy_o }
-              attribute \src "simple/issuer.py:147"
-              case 1'1
-              attribute \src "simple/issuer.py:151"
-              case
-                assign \core_msr__ren 8'00000010
-            end
-          attribute \src "simple/issuer.py:176"
-          attribute \nmigen.decoding "INSN_ACTIVE/2"
-          case 2'10
+    attribute \src "simple/issuer.py:157"
+    switch \fsm_state
+      attribute \src "simple/issuer.py:160"
+      attribute \nmigen.decoding "IDLE/0"
+      case 2'00
+      attribute \src "simple/issuer.py:174"
+      attribute \nmigen.decoding "INSN_READ/1"
+      case 2'01
+        attribute \src "simple/issuer.py:175"
+        switch { \imem_f_busy_o }
+          attribute \src "simple/issuer.py:175"
+          case 1'1
+          attribute \src "simple/issuer.py:179"
+          case
+            assign \core_msr__ren 8'00000010
         end
+      attribute \src "simple/issuer.py:204"
+      attribute \nmigen.decoding "INSN_ACTIVE/2"
+      case 2'10
     end
     sync init
   end
-  attribute \src "simple/issuer.py:96"
+  attribute \src "simple/issuer.py:118"
   wire width 64 \msr
-  attribute \src "simple/issuer.py:114"
-  wire width 1 $42
-  attribute \src "simple/issuer.py:114"
-  cell $not $43
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \core_core_terminated_o
-    connect \Y $42
-  end
-  process $group_23
+  process $group_28
     assign \msr 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "simple/issuer.py:114"
-    switch { $42 }
-      attribute \src "simple/issuer.py:114"
-      case 1'1
-        attribute \src "simple/issuer.py:121"
-        switch \fsm_state
-          attribute \src "simple/issuer.py:124"
-          attribute \nmigen.decoding "IDLE/0"
-          case 2'00
-          attribute \src "simple/issuer.py:146"
-          attribute \nmigen.decoding "INSN_READ/1"
-          case 2'01
-            attribute \src "simple/issuer.py:147"
-            switch { \imem_f_busy_o }
-              attribute \src "simple/issuer.py:147"
-              case 1'1
-              attribute \src "simple/issuer.py:151"
-              case
-                assign \msr \core_msr__data_o
-            end
-          attribute \src "simple/issuer.py:176"
-          attribute \nmigen.decoding "INSN_ACTIVE/2"
-          case 2'10
+    attribute \src "simple/issuer.py:157"
+    switch \fsm_state
+      attribute \src "simple/issuer.py:160"
+      attribute \nmigen.decoding "IDLE/0"
+      case 2'00
+      attribute \src "simple/issuer.py:174"
+      attribute \nmigen.decoding "INSN_READ/1"
+      case 2'01
+        attribute \src "simple/issuer.py:175"
+        switch { \imem_f_busy_o }
+          attribute \src "simple/issuer.py:175"
+          case 1'1
+          attribute \src "simple/issuer.py:179"
+          case
+            assign \msr \core_msr__data_o
         end
+      attribute \src "simple/issuer.py:204"
+      attribute \nmigen.decoding "INSN_ACTIVE/2"
+      case 2'10
     end
     sync init
   end
-  attribute \src "simple/issuer.py:114"
-  wire width 1 $44
-  attribute \src "simple/issuer.py:114"
-  cell $not $45
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \core_core_terminated_o
-    connect \Y $44
-  end
-  attribute \src "simple/issuer.py:95"
-  wire width 64 \cur_msr
-  attribute \src "simple/issuer.py:95"
-  wire width 64 \cur_msr$next
-  process $group_24
-    assign \core_msr 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "simple/issuer.py:114"
-    switch { $44 }
-      attribute \src "simple/issuer.py:114"
-      case 1'1
-        attribute \src "simple/issuer.py:121"
-        switch \fsm_state
-          attribute \src "simple/issuer.py:124"
-          attribute \nmigen.decoding "IDLE/0"
-          case 2'00
-          attribute \src "simple/issuer.py:146"
-          attribute \nmigen.decoding "INSN_READ/1"
-          case 2'01
-            attribute \src "simple/issuer.py:147"
-            switch { \imem_f_busy_o }
-              attribute \src "simple/issuer.py:147"
-              case 1'1
-              attribute \src "simple/issuer.py:151"
-              case
-                assign \core_msr \msr
-            end
-          attribute \src "simple/issuer.py:176"
-          attribute \nmigen.decoding "INSN_ACTIVE/2"
-          case 2'10
-            attribute \src "simple/issuer.py:177"
-            switch { \core_core_terminated_o }
-              attribute \src "simple/issuer.py:177"
-              case 1'1
-              attribute \src "simple/issuer.py:179"
-              case
-                assign \core_msr \cur_msr
-            end
+  process $group_31
+    assign \core_dec2_msr 64'0000000000000000000000000000000000000000000000000000000000000000
+    assign \core_dec2_pc 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "simple/issuer.py:157"
+    switch \fsm_state
+      attribute \src "simple/issuer.py:160"
+      attribute \nmigen.decoding "IDLE/0"
+      case 2'00
+      attribute \src "simple/issuer.py:174"
+      attribute \nmigen.decoding "INSN_READ/1"
+      case 2'01
+        attribute \src "simple/issuer.py:175"
+        switch { \imem_f_busy_o }
+          attribute \src "simple/issuer.py:175"
+          case 1'1
+          attribute \src "simple/issuer.py:179"
+          case
+            assign \core_dec2_msr \msr
+            assign \core_dec2_pc \cur_pc
         end
+      attribute \src "simple/issuer.py:204"
+      attribute \nmigen.decoding "INSN_ACTIVE/2"
+      case 2'10
+        assign { \core_dec2_msr \core_dec2_pc } { \cur_msr \cur_pc }
     end
     sync init
   end
-  attribute \src "simple/issuer.py:114"
-  wire width 1 $46
-  attribute \src "simple/issuer.py:114"
-  cell $not $47
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \core_core_terminated_o
-    connect \Y $46
-  end
-  process $group_25
+  process $group_30
     assign \cur_msr$next \cur_msr
-    attribute \src "simple/issuer.py:114"
-    switch { $46 }
-      attribute \src "simple/issuer.py:114"
-      case 1'1
-        attribute \src "simple/issuer.py:121"
-        switch \fsm_state
-          attribute \src "simple/issuer.py:124"
-          attribute \nmigen.decoding "IDLE/0"
-          case 2'00
-          attribute \src "simple/issuer.py:146"
-          attribute \nmigen.decoding "INSN_READ/1"
-          case 2'01
-            attribute \src "simple/issuer.py:147"
-            switch { \imem_f_busy_o }
-              attribute \src "simple/issuer.py:147"
-              case 1'1
-              attribute \src "simple/issuer.py:151"
-              case
-                assign \cur_msr$next \msr
-            end
-          attribute \src "simple/issuer.py:176"
-          attribute \nmigen.decoding "INSN_ACTIVE/2"
-          case 2'10
+    attribute \src "simple/issuer.py:157"
+    switch \fsm_state
+      attribute \src "simple/issuer.py:160"
+      attribute \nmigen.decoding "IDLE/0"
+      case 2'00
+      attribute \src "simple/issuer.py:174"
+      attribute \nmigen.decoding "INSN_READ/1"
+      case 2'01
+        attribute \src "simple/issuer.py:175"
+        switch { \imem_f_busy_o }
+          attribute \src "simple/issuer.py:175"
+          case 1'1
+          attribute \src "simple/issuer.py:179"
+          case
+            assign \cur_msr$next \msr
         end
+      attribute \src "simple/issuer.py:204"
+      attribute \nmigen.decoding "INSN_ACTIVE/2"
+      case 2'10
     end
     attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519"
     switch \rst
@@ -158911,189 +177028,144 @@ module \test_issuer
     sync posedge \clk
       update \cur_msr \cur_msr$next
   end
-  attribute \src "simple/issuer.py:114"
-  wire width 1 $48
-  attribute \src "simple/issuer.py:114"
-  cell $not $49
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \core_core_terminated_o
-    connect \Y $48
-  end
-  process $group_26
-    assign \core_cia 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "simple/issuer.py:114"
-    switch { $48 }
-      attribute \src "simple/issuer.py:114"
-      case 1'1
-        attribute \src "simple/issuer.py:121"
-        switch \fsm_state
-          attribute \src "simple/issuer.py:124"
-          attribute \nmigen.decoding "IDLE/0"
-          case 2'00
-          attribute \src "simple/issuer.py:146"
-          attribute \nmigen.decoding "INSN_READ/1"
-          case 2'01
-            attribute \src "simple/issuer.py:147"
-            switch { \imem_f_busy_o }
-              attribute \src "simple/issuer.py:147"
-              case 1'1
-              attribute \src "simple/issuer.py:151"
-              case
-                assign \core_cia \cur_pc
-            end
-          attribute \src "simple/issuer.py:176"
-          attribute \nmigen.decoding "INSN_ACTIVE/2"
-          case 2'10
-            attribute \src "simple/issuer.py:177"
-            switch { \core_core_terminated_o }
-              attribute \src "simple/issuer.py:177"
-              case 1'1
-              attribute \src "simple/issuer.py:179"
-              case
-                assign \core_cia \cur_pc
-            end
-        end
-    end
-    sync init
-  end
-  attribute \src "simple/issuer.py:114"
-  wire width 1 $50
-  attribute \src "simple/issuer.py:114"
-  cell $not $51
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \core_core_terminated_o
-    connect \Y $50
-  end
-  attribute \src "simple/issuer.py:187"
-  wire width 1 $52
-  attribute \src "simple/issuer.py:187"
-  cell $not $53
+  attribute \src "simple/issuer.py:211"
+  wire width 1 $29
+  attribute \src "simple/issuer.py:211"
+  cell $not $30
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \core_corebusy_o
-    connect \Y $52
+    connect \Y $29
   end
-  attribute \src "simple/issuer.py:191"
-  wire width 1 $54
-  attribute \src "simple/issuer.py:191"
-  cell $not $55
+  attribute \src "simple/issuer.py:215"
+  wire width 1 $31
+  attribute \src "simple/issuer.py:215"
+  cell $not $32
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \pc_changed
-    connect \Y $54
+    connect \Y $31
   end
-  process $group_27
+  process $group_32
     assign \core_wen 8'00000000
-    attribute \src "simple/issuer.py:114"
-    switch { $50 }
-      attribute \src "simple/issuer.py:114"
-      case 1'1
-        attribute \src "simple/issuer.py:121"
-        switch \fsm_state
-          attribute \src "simple/issuer.py:124"
-          attribute \nmigen.decoding "IDLE/0"
-          case 2'00
-          attribute \src "simple/issuer.py:146"
-          attribute \nmigen.decoding "INSN_READ/1"
-          case 2'01
-          attribute \src "simple/issuer.py:176"
-          attribute \nmigen.decoding "INSN_ACTIVE/2"
-          case 2'10
-            attribute \src "simple/issuer.py:177"
-            switch { \core_core_terminated_o }
-              attribute \src "simple/issuer.py:177"
+    attribute \src "simple/issuer.py:157"
+    switch \fsm_state
+      attribute \src "simple/issuer.py:160"
+      attribute \nmigen.decoding "IDLE/0"
+      case 2'00
+      attribute \src "simple/issuer.py:174"
+      attribute \nmigen.decoding "INSN_READ/1"
+      case 2'01
+      attribute \src "simple/issuer.py:204"
+      attribute \nmigen.decoding "INSN_ACTIVE/2"
+      case 2'10
+        attribute \src "simple/issuer.py:211"
+        switch { $29 }
+          attribute \src "simple/issuer.py:211"
+          case 1'1
+            attribute \src "simple/issuer.py:215"
+            switch { $31 }
+              attribute \src "simple/issuer.py:215"
               case 1'1
-              attribute \src "simple/issuer.py:179"
-              case
-                attribute \src "simple/issuer.py:187"
-                switch { $52 }
-                  attribute \src "simple/issuer.py:187"
-                  case 1'1
-                    attribute \src "simple/issuer.py:191"
-                    switch { $54 }
-                      attribute \src "simple/issuer.py:191"
-                      case 1'1
-                        assign \core_wen 8'00000001
-                    end
-                end
+                assign \core_wen 8'00000001
             end
         end
     end
     sync init
   end
-  attribute \src "simple/issuer.py:114"
-  wire width 1 $56
-  attribute \src "simple/issuer.py:114"
-  cell $not $57
-    parameter \A_SIGNED 0
-    parameter \A_WIDTH 1
-    parameter \Y_WIDTH 1
-    connect \A \core_core_terminated_o
-    connect \Y $56
-  end
-  attribute \src "simple/issuer.py:187"
-  wire width 1 $58
-  attribute \src "simple/issuer.py:187"
-  cell $not $59
+  attribute \src "simple/issuer.py:211"
+  wire width 1 $33
+  attribute \src "simple/issuer.py:211"
+  cell $not $34
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \core_corebusy_o
-    connect \Y $58
+    connect \Y $33
   end
-  attribute \src "simple/issuer.py:191"
-  wire width 1 $60
-  attribute \src "simple/issuer.py:191"
-  cell $not $61
+  attribute \src "simple/issuer.py:215"
+  wire width 1 $35
+  attribute \src "simple/issuer.py:215"
+  cell $not $36
     parameter \A_SIGNED 0
     parameter \A_WIDTH 1
     parameter \Y_WIDTH 1
     connect \A \pc_changed
-    connect \Y $60
+    connect \Y $35
   end
-  process $group_28
+  process $group_33
     assign \core_data_i 64'0000000000000000000000000000000000000000000000000000000000000000
-    attribute \src "simple/issuer.py:114"
-    switch { $56 }
-      attribute \src "simple/issuer.py:114"
-      case 1'1
-        attribute \src "simple/issuer.py:121"
-        switch \fsm_state
-          attribute \src "simple/issuer.py:124"
-          attribute \nmigen.decoding "IDLE/0"
-          case 2'00
-          attribute \src "simple/issuer.py:146"
-          attribute \nmigen.decoding "INSN_READ/1"
-          case 2'01
-          attribute \src "simple/issuer.py:176"
-          attribute \nmigen.decoding "INSN_ACTIVE/2"
-          case 2'10
-            attribute \src "simple/issuer.py:177"
-            switch { \core_core_terminated_o }
-              attribute \src "simple/issuer.py:177"
+    attribute \src "simple/issuer.py:157"
+    switch \fsm_state
+      attribute \src "simple/issuer.py:160"
+      attribute \nmigen.decoding "IDLE/0"
+      case 2'00
+      attribute \src "simple/issuer.py:174"
+      attribute \nmigen.decoding "INSN_READ/1"
+      case 2'01
+      attribute \src "simple/issuer.py:204"
+      attribute \nmigen.decoding "INSN_ACTIVE/2"
+      case 2'10
+        attribute \src "simple/issuer.py:211"
+        switch { $33 }
+          attribute \src "simple/issuer.py:211"
+          case 1'1
+            attribute \src "simple/issuer.py:215"
+            switch { $35 }
+              attribute \src "simple/issuer.py:215"
               case 1'1
-              attribute \src "simple/issuer.py:179"
-              case
-                attribute \src "simple/issuer.py:187"
-                switch { $58 }
-                  attribute \src "simple/issuer.py:187"
-                  case 1'1
-                    attribute \src "simple/issuer.py:191"
-                    switch { $60 }
-                      attribute \src "simple/issuer.py:191"
-                      case 1'1
-                        assign \core_data_i \nia
-                    end
-                end
+                assign \core_data_i \nia
             end
         end
     end
     sync init
   end
+  attribute \src "simple/issuer.py:226"
+  wire width 128 $37
+  attribute \src "simple/issuer.py:226"
+  wire width 128 $38
+  attribute \src "simple/issuer.py:226"
+  cell $sshl $39
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 7
+    parameter \Y_WIDTH 128
+    connect \A 1'1
+    connect \B \dbg_dbg_gpr_addr
+    connect \Y $38
+  end
+  connect $37 $38
+  process $group_34
+    assign \core_dmi__ren 32'00000000000000000000000000000000
+    attribute \src "simple/issuer.py:223"
+    switch { \dbg_dbg_gpr_req }
+      attribute \src "simple/issuer.py:223"
+      case 1'1
+        assign \core_dmi__ren $37 [31:0]
+    end
+    sync init
+  end
+  process $group_35
+    assign \dbg_dbg_gpr_data 64'0000000000000000000000000000000000000000000000000000000000000000
+    attribute \src "simple/issuer.py:223"
+    switch { \dbg_dbg_gpr_req }
+      attribute \src "simple/issuer.py:223"
+      case 1'1
+        assign \dbg_dbg_gpr_data \core_dmi__data_o
+    end
+    sync init
+  end
+  process $group_36
+    assign \dbg_dbg_gpr_ack 1'0
+    attribute \src "simple/issuer.py:223"
+    switch { \dbg_dbg_gpr_req }
+      attribute \src "simple/issuer.py:223"
+      case 1'1
+        assign \dbg_dbg_gpr_ack 1'1
+    end
+    sync init
+  end
 end