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ls2: fix keyword for declaring pin voltage type on Xilinx devices
authorCesar Strauss <cestrauss@gmail.com>
Sun, 7 Apr 2024 17:29:01 +0000 (14:29 -0300)
committerCesar Strauss <cestrauss@gmail.com>
Sat, 13 Apr 2024 18:28:43 +0000 (15:28 -0300)
src/ls2.py patch | blob | history

diff --git a/src/ls2.py b/src/ls2.py
index 5ffab701792d16ed503b67844a55692f28fc1991..2a17fae2771b15152c36f37229d4e3b24856a0a4 100644 (file)
--- a/src/ls2.py
+++ b/src/ls2.py
@@ -968,7 +968,7 @@ def build_platform(fpga, firmware):
                      Subsignal("dq3",  Pins("M14", dir="io")),
                      Subsignal("cs_n", Pins("L13", dir="o")),
                      Subsignal("clk",  Pins("L16", dir="o")),
-                     Attrs(PULLMODE="NONE", DRIVE="4", IO_TYPE="LVCMOS33"))
+                     Attrs(PULLMODE="NONE", DRIVE="4", IOSTANDARD="LVCMOS33"))
         ]
         platform.add_resources(spi_0_ios)
         spi_0_pins = platform.request("spi_0", 0)