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syntax error
author
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Fri, 8 Apr 2022 20:10:19 +0000
(21:10 +0100)
committer
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Fri, 8 Apr 2022 20:10:19 +0000
(21:10 +0100)
src/soc/bus/syscon.py
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diff --git
a/src/soc/bus/syscon.py
b/src/soc/bus/syscon.py
index 1f657523e210d3c1400288fd2663982ab1f727b3..b5826565cb026bd3650343477c6d66e37615dcaf 100644
(file)
--- a/
src/soc/bus/syscon.py
+++ b/
src/soc/bus/syscon.py
@@
-87,7
+87,7
@@
class MicrowattSYSCON(Peripheral, Elaboratable):
# Reg Info, defines what peripherals and characteristics are present
comb += self._reg_info_r.r_data[0].eq(self.has_uart) # has UART0
- comb += self._reg_info_r.r_data[1].eq(has_dram
# has DDR DRAM
+ comb += self._reg_info_r.r_data[1].eq(has_dram
)
# has DDR DRAM
comb += self._reg_info_r.r_data[3].eq(has_spi) # has SPI Flash
comb += self._reg_info_r.r_data[5].eq(1) # Large SYSCON