+++ /dev/null
-from string import digits
-try:
- from string import maketrans
-except ImportError:
- maketrans = str.maketrans
-
-
-# dictionary of properties of signals that are supported.
-dictionary = {
- "uart_rx" : "input",
- "uart_tx" : "output",
- "spi_sclk" : "output",
- "spi_mosi" : "output",
- "spi_ss" : "output",
- "spi_miso" : "input",
- "twi_sda" : "inout",
- "twi_scl" : "inout",
- "sd_clk": "output",
- "sd_cmd": "output",
- "sd_d": "inout",
- "pwm_pwm": "output"
-}
-
-
-# ============== common bsv templates ============ #
-# first argument is the io-cell number being assigned.
-# second argument is the mux value.
-# Third argument is the signal from the pinmap file
-mux_wire = '''
- rule assign_{2}_on_cell{0}(wrcell{0}_mux=={1});
- {2}<=cell{0}_mux_in;
- endrule
-'''
-dedicated_wire = '''
- rule assign_{1}_on_cell{0};
- {1}<=cell{0}_mux_in;
- endrule
-'''
-# ============================================================
-digits = maketrans('0123456789', ' ' * 10) # delete space later
-
-
-def cn(idx):
- return "cell%s_mux" % str(idx)
-
-
-def init(p):
- p.pinmux = ' '
- global dedicated_wire
- for cell in p.muxed_cells:
- p.pinmux += " %s_out=" % cn(cell[0])
- for i in range(0, len(cell) - 2):
- p.pinmux += "wr%s" % cn(cell[0]) + \
- "==" + str(i) + "?" + cell[i + 1] + "_io:\n\t\t\t"
- p.pinmux += cell[i + 2] + "_io"
- p.pinmux += ";\n"
- # ======================================================== #
-
- # check each cell if "peripheral input/inout" then assign its wire
- # Here we check the direction of each signal in the dictionary.
- # We choose to keep the dictionary within the code and not user-input
- # since the interfaces are always standard and cannot change from
- # user-to-user. Plus this also reduces human-error as well :)
- for i in range(0, len(cell) - 1):
- temp = cell[i + 1].translate(digits)
- temp = temp.replace(' ', '')
- x = dictionary.get(temp)
- assert x is not None, "ERROR: The signal : " + \
- str(cell[i + 1]) + \
- " of pinmap.txt isn't present \nin the current" + \
- " dictionary. Update dictionary or fix-typo."
- if x == "input":
- p.pinmux += \
- mux_wire.format(cell[0], i, "wr" + cell[i + 1]) + "\n"
- elif x == "inout":
- p.pinmux += \
- mux_wire.format(cell[0], i, "wr" + cell[i + 1] +
- "_in") + "\n"
- # ============================================================ #
-
- # ================== Logic for dedicated pins ========= #
- for cell in p.dedicated_cells:
- p.pinmux += " %s" % cn(cell[0]) + \
- "_out=" + cell[1] + "_io;\n"
- temp = cell[1].translate(digits)
- x = dictionary.get(temp)
- if x == "input":
- pinmux = pinmux + \
- dedicated_wire.format(cell[0], "wr" + cell[1]) + "\n"
- elif x == "inout":
- pinmux = pinmux + \
- dedicated_wire.format(cell[0], "wr" + cell[1] + "_in") + "\n"
- # =======================================================#
--- /dev/null
+from string import digits
+try:
+ from string import maketrans
+except ImportError:
+ maketrans = str.maketrans
+
+
+# dictionary of properties of signals that are supported.
+dictionary = {
+ "uart_rx" : "input",
+ "uart_tx" : "output",
+ "spi_sclk" : "output",
+ "spi_mosi" : "output",
+ "spi_ss" : "output",
+ "spi_miso" : "input",
+ "twi_sda" : "inout",
+ "twi_scl" : "inout",
+ "sd_clk": "output",
+ "sd_cmd": "output",
+ "sd_d": "inout",
+ "pwm_pwm": "output"
+}
+
+
+# ============== common bsv templates ============ #
+# first argument is the io-cell number being assigned.
+# second argument is the mux value.
+# Third argument is the signal from the pinmap file
+mux_wire = '''
+ rule assign_{2}_on_cell{0}(wrcell{0}_mux=={1});
+ {2}<=cell{0}_mux_in;
+ endrule
+'''
+dedicated_wire = '''
+ rule assign_{1}_on_cell{0};
+ {1}<=cell{0}_mux_in;
+ endrule
+'''
+# ============================================================
+digits = maketrans('0123456789', ' ' * 10) # delete space later
+
+
+def cn(idx):
+ return "cell%s_mux" % str(idx)
+
+
+def init(p):
+ p.pinmux = ' '
+ global dedicated_wire
+ for cell in p.muxed_cells:
+ p.pinmux += " %s_out=" % cn(cell[0])
+ for i in range(0, len(cell) - 2):
+ p.pinmux += "wr%s" % cn(cell[0]) + \
+ "==" + str(i) + "?" + cell[i + 1] + "_io:\n\t\t\t"
+ p.pinmux += cell[i + 2] + "_io"
+ p.pinmux += ";\n"
+ # ======================================================== #
+
+ # check each cell if "peripheral input/inout" then assign its wire
+ # Here we check the direction of each signal in the dictionary.
+ # We choose to keep the dictionary within the code and not user-input
+ # since the interfaces are always standard and cannot change from
+ # user-to-user. Plus this also reduces human-error as well :)
+ for i in range(0, len(cell) - 1):
+ temp = cell[i + 1].translate(digits)
+ temp = temp.replace(' ', '')
+ x = dictionary.get(temp)
+ assert x is not None, "ERROR: The signal : " + \
+ str(cell[i + 1]) + \
+ " of pinmap.txt isn't present \nin the current" + \
+ " dictionary. Update dictionary or fix-typo."
+ if x == "input":
+ p.pinmux += \
+ mux_wire.format(cell[0], i, "wr" + cell[i + 1]) + "\n"
+ elif x == "inout":
+ p.pinmux += \
+ mux_wire.format(cell[0], i, "wr" + cell[i + 1] +
+ "_in") + "\n"
+ # ============================================================ #
+
+ # ================== Logic for dedicated pins ========= #
+ for cell in p.dedicated_cells:
+ p.pinmux += " %s" % cn(cell[0]) + \
+ "_out=" + cell[1] + "_io;\n"
+ temp = cell[1].translate(digits)
+ x = dictionary.get(temp)
+ if x == "input":
+ pinmux = pinmux + \
+ dedicated_wire.format(cell[0], "wr" + cell[1]) + "\n"
+ elif x == "inout":
+ pinmux = pinmux + \
+ dedicated_wire.format(cell[0], "wr" + cell[1] + "_in") + "\n"
+ # =======================================================#
--- /dev/null
+
+axi4_lite = '''
+package bus;
+
+ /*=== Project imports ===*/
+ import AXI4_Lite_Types::*;
+ import PinTop::*;
+ import pinmux::*;
+ import Semi_FIFOF::*;
+ /*======================*/
+
+ interface Ifc_bus;
+ interface AXI4_Lite_Slave_IFC #({0}, {1}, 0) axi_side;
+ interface PeripheralSide peripheral_side;
+ endinterface
+
+ module mkbus(Ifc_bus);
+ Ifc_PintTop pintop <-mkPinTop;
+ AXI4_Lite_Slave_Xactor_IFC#({0}, {1}, 0) slave_xactor <-
+ mkAXI4_Lite_Slave_Xactor();
+ rule read_transaction;
+ let req<-pop_o(slave_xactor.o_rd_addr);
+ let {{err,data}}=pintop.read(req.araddr);
+ AXI4_Lite_Rd_Data#({0}, 0) r = AXI4_Lite_Rd_Data {{
+ rresp: err?AXI4_LITE_SLVERR:AXI4_LITE_OKAY,
+ rdata: zeroExtend(data) , ruser: 0}};
+ slave_xactor.i_rd_data.enq(r);
+ endrule
+
+ rule write_transaction;
+ let addr_req<-pop_o(slave_xactor.o_wr_addr);
+ let data_req<-pop_o(slave_xactor.o_wr_data);
+ let err<-pintop.write(addr_req.awaddr, data_req.wdata);
+ let b = AXI4_Lite_Wr_Resp {{bresp: err?AXI4_LITE_SLVERR:AXI4_LITE_OKAY,
+ buser: ?}};
+ slave_xactor.i_wr_resp.enq (b);
+ endrule
+ interface axi_side= slave_xactor.axi_side;
+ interface peripheral_side=pintop.peripheral_side;
+ endmodule
+endpackage
+'''
--- /dev/null
+# == Intermediate wire definitions, special cases ==#
+muxwire = '''
+ Wire#(Bit#({1})) wrcell{0}_mux<-mkDWire(0);'''
+generic_io = '''
+ GenericIOType cell{0}_mux_out=unpack(0);
+ Wire#(Bit#(1)) cell{0}_mux_in<-mkDWire(0);
+'''
+++ /dev/null
-
-axi4_lite = '''
-package bus;
-
- /*=== Project imports ===*/
- import AXI4_Lite_Types::*;
- import PinTop::*;
- import pinmux::*;
- import Semi_FIFOF::*;
- /*======================*/
-
- interface Ifc_bus;
- interface AXI4_Lite_Slave_IFC #({0}, {1}, 0) axi_side;
- interface PeripheralSide peripheral_side;
- endinterface
-
- module mkbus(Ifc_bus);
- Ifc_PintTop pintop <-mkPinTop;
- AXI4_Lite_Slave_Xactor_IFC#({0}, {1}, 0) slave_xactor <-
- mkAXI4_Lite_Slave_Xactor();
- rule read_transaction;
- let req<-pop_o(slave_xactor.o_rd_addr);
- let {{err,data}}=pintop.read(req.araddr);
- AXI4_Lite_Rd_Data#({0}, 0) r = AXI4_Lite_Rd_Data {{
- rresp: err?AXI4_LITE_SLVERR:AXI4_LITE_OKAY,
- rdata: zeroExtend(data) , ruser: 0}};
- slave_xactor.i_rd_data.enq(r);
- endrule
-
- rule write_transaction;
- let addr_req<-pop_o(slave_xactor.o_wr_addr);
- let data_req<-pop_o(slave_xactor.o_wr_data);
- let err<-pintop.write(addr_req.awaddr, data_req.wdata);
- let b = AXI4_Lite_Wr_Resp {{bresp: err?AXI4_LITE_SLVERR:AXI4_LITE_OKAY,
- buser: ?}};
- slave_xactor.i_wr_resp.enq (b);
- endrule
- interface axi_side= slave_xactor.axi_side;
- interface peripheral_side=pintop.peripheral_side;
- endmodule
-endpackage
-'''
+++ /dev/null
-# == Intermediate wire definitions, special cases ==#
-muxwire = '''
- Wire#(Bit#({1})) wrcell{0}_mux<-mkDWire(0);'''
-generic_io = '''
- GenericIOType cell{0}_mux_out=unpack(0);
- Wire#(Bit#(1)) cell{0}_mux_in<-mkDWire(0);
-'''
projects / pinmux.git / commitdiff