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add clk and ck so that ck is recognised for routing
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Tue, 25 Feb 2020 17:57:59 +0000 (17:57 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Tue, 25 Feb 2020 17:57:59 +0000 (17:57 +0000)
experiments4/coriolis2/settings.py patch | blob | history

diff --git a/experiments4/coriolis2/settings.py b/experiments4/coriolis2/settings.py
index f93e33d99202736654357e8bca453cc61e7bb1bd..85b6b479c4bffdb476af61653ad33460b4b97267 100644 (file)
--- a/experiments4/coriolis2/settings.py
+++ b/experiments4/coriolis2/settings.py
@@ -48,7 +48,7 @@ env = af.getEnvironment()
 env.addSYSTEM_LIBRARY( library=cellsTop+'/nsxlib', mode=CRL.Environment.Prepend )
 env.addSYSTEM_LIBRARY( library=cellsTop+'/mpxlib', mode=CRL.Environment.Prepend )
 #env.setCLOCK( '^clk$|m_clock' )
-env.setCLOCK( 'clk' )
+env.setCLOCK( 'clk|ck|cki' )
 env.setPOWER( 'vdd' )
 env.setGROUND( 'vss' )