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add one more up to path
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 1 Apr 2021 21:47:18 +0000 (22:47 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Thu, 1 Apr 2021 21:47:18 +0000 (22:47 +0100)
ls180/pre_pnr/Makefile patch | blob | history

diff --git a/ls180/pre_pnr/Makefile b/ls180/pre_pnr/Makefile
index 330c788d90b366d9fbdbd4fcabf2ae7bebda4349..663ece6e75a191366cff8bb96adbe45a32ae3452 100644 (file)
--- a/ls180/pre_pnr/Makefile
+++ b/ls180/pre_pnr/Makefile
@@ -7,8 +7,8 @@ TOPLEVEL_LANG := verilog
 # within soc repo, as submodule, this works after "make ls180"
 # is run inside the litex/florent subdirectory
 VERILOG_SOURCES := \
-  ../../litex/florent/libresoc.v \
-  ../../litex/florent/ls180.v \
+  ../../../litex/florent/libresoc.v \
+  ../../../litex/florent/ls180.v \
 # END VERILOG_SOURCES
 
 TOPLEVEL := ls180