remove unneeded code and inputs. convert to "naming" in CompUnit inputs

diff --git a/src/soc/fu/compunits/test/test_alu_compunit.py b/src/soc/fu/compunits/test/test_alu_compunit.py
index 2d001a0e602d7718656268fb8240a25486de131c..6041cd3ec2ab185bfd7ac1eb83b99e020786b3d8 100644 (file)
--- a/src/soc/fu/compunits/test/test_alu_compunit.py
+++ b/src/soc/fu/compunits/test/test_alu_compunit.py
@@ -1,68 +1,9 @@
-from nmigen import Module, Signal
-from nmigen.back.pysim import Simulator, Delay, Settle
-from nmigen.test.utils import FHDLTestCase
-from nmigen.cli import rtlil
 import unittest
-from soc.decoder.isa.caller import ISACaller, special_sprs
-from soc.decoder.power_decoder import (create_pdecode)
-from soc.decoder.power_decoder2 import (PowerDecode2)
-from soc.decoder.power_enums import (XER_bits, Function, InternalOp)
-from soc.decoder.selectable_int import SelectableInt
-from soc.simulator.program import Program
-from soc.decoder.isa.all import ISA
+from soc.decoder.power_enums import (XER_bits,)
 
 from soc.fu.alu.test.test_pipe_caller import TestCase, ALUTestCase, test_data
 from soc.fu.compunits.compunits import ALUFunctionUnit
 from soc.fu.compunits.test.test_compunit import TestRunner
-from soc.experiment.compalu_multi import find_ok # hack
-import random
-
-def set_cu_input(cu, idx, data):
-    rdop = cu.get_in_name(idx)
-    yield cu.src_i[idx].eq(data)
-    while True:
-        rd_rel_o = yield cu.rd.rel[idx]
-        print ("rd_rel %d wait HI" % idx, rd_rel_o, rdop, hex(data))
-        if rd_rel_o:
-            break
-        yield
-    yield cu.rd.go[idx].eq(1)
-    while True:
-        yield
-        rd_rel_o = yield cu.rd.rel[idx]
-        if rd_rel_o:
-            break
-        print ("rd_rel %d wait HI" % idx, rd_rel_o)
-        yield
-    yield cu.rd.go[idx].eq(0)
-
-
-def get_cu_output(cu, idx, code):
-    wrmask = yield cu.wrmask
-    wrop = cu.get_out_name(idx)
-    wrok = cu.get_out(idx)
-    fname = find_ok(wrok.fields)
-    wrok = yield getattr(wrok, fname)
-    print ("wr_rel mask", repr(code), idx, wrop, bin(wrmask), fname, wrok)
-    assert wrmask & (1<<idx), \
-            "get_cu_output '%s': mask bit %d not set\n" \
-            "write-operand '%s' Data.ok likely not set (%s)" \
-            % (code, idx, wrop, hex(wrok))
-    while True:
-        wr_relall_o = yield cu.wr.rel
-        wr_rel_o = yield cu.wr.rel[idx]
-        print ("wr_rel %d wait" % idx, hex(wr_relall_o), wr_rel_o)
-        if wr_rel_o:
-            break
-        yield
-    yield cu.wr.go[idx].eq(1)
-    yield Settle()
-    result = yield cu.dest[idx]
-    yield
-    yield cu.wr.go[idx].eq(0)
-    print ("result", repr(code), idx, wrop, wrok, hex(result))
-    return result
-
 
 
 class ALUTestRunner(TestRunner):
@@ -70,9 +11,8 @@ class ALUTestRunner(TestRunner):
         super().__init__(test_data, ALUFunctionUnit, self)
 
     def get_cu_inputs(self, dec2, sim):
-        # TODO: see https://bugs.libre-soc.org/show_bug.cgi?id=305#c43
-        # detect the immediate here (with m.If(self.i.ctx.op.imm_data.imm_ok))
-        # and place it into data_i.b
+        """naming (res) must conform to ALUFunctionUnit input regspec
+        """
         res = {}
 
         reg3_ok = yield dec2.e.read_reg3.ok
@@ -80,26 +20,27 @@ class ALUTestRunner(TestRunner):
         assert reg3_ok != reg1_ok
         if reg3_ok:
             data1 = yield dec2.e.read_reg3.data
-            res[0] = sim.gpr(data1).value
+            res['a'] = sim.gpr(data1).value
         elif reg1_ok:
             data1 = yield dec2.e.read_reg1.data
-            res[0] = sim.gpr(data1).value
+            res['a'] = sim.gpr(data1).value
 
-        # If there's an immediate, set the B operand to that
         reg2_ok = yield dec2.e.read_reg2.ok
         if reg2_ok:
             data2 = yield dec2.e.read_reg2.data
-            res[1] = sim.gpr(data2).value
+            res['b'] = sim.gpr(data2).value
 
         carry = 1 if sim.spr['XER'][XER_bits['CA']] else 0
         carry32 = 1 if sim.spr['XER'][XER_bits['CA32']] else 0
-        res[3] = carry | (carry32<<1)
+        res['xer_ca'] = carry | (carry32<<1)
         so = 1 if sim.spr['XER'][XER_bits['SO']] else 0
-        res[2] = so
+        res['xer_so'] = so
 
         return res
 
     def check_cu_outputs(self, res, dec2, sim, code):
+        """naming (res) must conform to ALUFunctionUnit output regspec
+        """
         out_reg_valid = yield dec2.e.write_reg.ok
         if out_reg_valid:
             write_reg_idx = yield dec2.e.write_reg.data

diff --git a/src/soc/fu/compunits/test/test_compunit.py b/src/soc/fu/compunits/test/test_compunit.py
index 93df11e50a78956d8a2ac3cb20439700960cdde9..06aef9fe4d88e91c891d115758008520fcb0be79 100644 (file)
--- a/src/soc/fu/compunits/test/test_compunit.py
+++ b/src/soc/fu/compunits/test/test_compunit.py
@@ -87,10 +87,19 @@ def get_cu_outputs(cu, code):
     return res
 
 
+def get_inp_indexed(cu, inp):
+    res = {}
+    for i in range(cu.n_src):
+        wrop = cu.get_in_name(i)
+        if wrop in inp:
+            res[i] = inp[wrop]
+    return res
+
 def get_cu_rd_mask(n_src, inp):
-    mask = 0 #((1<<n_src)-1)
-    for i in inp.keys():
-        mask |= 1<<i
+    mask = 0
+    for i in range(n_src):
+        if i in inp:
+            mask |= (1<<i)
     return mask
 
 
@@ -144,7 +153,8 @@ class TestRunner(FHDLTestCase):
 
                     # set operand and get inputs
                     yield from set_operand(cu, pdecode2, sim)
-                    inp = yield from self.iodef.get_cu_inputs(pdecode2, sim)
+                    iname = yield from self.iodef.get_cu_inputs(pdecode2, sim)
+                    inp = get_inp_indexed(cu, iname)
 
                     # reset read-operand mask
                     rdmask = get_cu_rd_mask(cu.n_src, inp)