add fast bus instance

diff --git a/src/bsv/Makefile.template b/src/bsv/Makefile.template
index aedb9bb1efebbf55018f46d451b7e87dca1e75f4..2950451c15434c532e0c0bf2ede54dbde95e7fce 100644 (file)
--- a/src/bsv/Makefile.template
+++ b/src/bsv/Makefile.template
@@ -19,6 +19,7 @@ BSVINCDIR:= $(BSVINCDIR):../../../src/peripherals/src/peripherals/pwm
 BSVINCDIR:= $(BSVINCDIR):../../../src/peripherals/src/peripherals/qspi
 BSVINCDIR:= $(BSVINCDIR):../../../src/peripherals/src/peripherals/spi
 BSVINCDIR:= $(BSVINCDIR):../../../src/peripherals/src/peripherals/sdmmc
+BSVINCDIR:= $(BSVINCDIR):../../../src/peripherals/src/peripherals/flexbus
 BSVINCDIR:= $(BSVINCDIR):../../../src/peripherals/src/peripherals/uart
 
 default: gen_verilog

diff --git a/src/bsv/bsv_lib/soc_template.bsv b/src/bsv/bsv_lib/soc_template.bsv
index a36243bcf9696d61c6bb9e4eec54c43fb8cedaf5..7a7b0ce8e2d1c32ad6a909958fd15abbc1a60fdc 100644 (file)
--- a/src/bsv/bsv_lib/soc_template.bsv
+++ b/src/bsv/bsv_lib/soc_template.bsv
@@ -285,26 +285,7 @@ package Soc;
     `ifdef DDR
       interface master=fabric.v_to_slaves[fromInteger(valueOf(Sdram_slave_num))];
     `endif
-               `ifdef Debug
-                       method Action tms_i(Bit#(1) tms);
-                               tap.tms_i(tms);
-                       endmethod
-                       method Action tdi_i(Bit#(1) tdi);
-                               tap.tdi_i(tdi);
-                       endmethod
-                       method Action bs_chain_i(Bit#(1) bs_chain);
-                               tap.bs_chain_i(bs_chain);
-                       endmethod
-                       method Bit#(1) shiftBscan2Edge=tap.shiftBscan2Edge;
-                       method Bit#(1) selectJtagInput=tap.selectJtagInput;
-                       method Bit#(1) selectJtagOutput=tap.selectJtagOutput;
-                       method Bit#(1) updateBscan=tap.updateBscan;
-                       method Bit#(1) bscan_in=tap.bscan_in;
-            method Bit#(1) scan_shift_en=tap.scan_shift_en;
-                       method Bit#(1) tdo=tap.tdo;
-                       method Bit#(1) tdo_oe=tap.tdo_oe;
-               `endif
                interface slow_ios=slow_peripherals.slow_ios;
-
+{6}
        endmodule
 endpackage

diff --git a/src/bsv/peripheral_gen/base.py b/src/bsv/peripheral_gen/base.py
index 51c87e8169efb0594ce835f8d59c8b313882d5e6..0cc11df529aca7517115ab82434e4655443b3244 100644 (file)
--- a/src/bsv/peripheral_gen/base.py
+++ b/src/bsv/peripheral_gen/base.py
@@ -207,6 +207,9 @@ class PBase(object):
     def mk_ext_ifacedef(self, iname, inum):
         return ''
 
+    def extfastifinstance(self, name, count):
+        return ''
+
     def extifinstance(self, name, count):
         sname = self.peripheral.iname().format(count)
         pname = self.get_iname(count)
@@ -287,7 +290,7 @@ class PeripheralIface(object):
             self.slow = slow(ifacename)
             self.slow.peripheral = self
         for fname in ['slowimport',
-                      'extifinstance', 'extifdecl',
+                      'extfastifinstance', 'extifinstance', 'extifdecl',
                       'slowifdecl', 'slowifdeclmux',
                       'fastifdecl',
                       'mkslow_peripheral', 
@@ -337,6 +340,17 @@ class PeripheralInterfaces(object):
             ret.append(self.data[name].slowimport())
         return '\n'.join(list(filter(None, ret)))
 
+    def extfastifinstance(self, *args):
+        ret = []
+        for (name, count) in self.ifacecount:
+            for i in range(count):
+                iname = self.data[name].iname().format(i)
+                print "extfast", iname, self.is_on_fastbus(name, i)
+                if self.is_on_fastbus(name, i):
+                    continue
+                ret.append(self.data[name].extfastifinstance(name, i))
+        return '\n'.join(list(filter(None, ret)))
+
     def extifinstance(self, *args):
         ret = []
         for (name, count) in self.ifacecount:

diff --git a/src/bsv/peripheral_gen/jtag.py b/src/bsv/peripheral_gen/jtag.py
index 75106096f0ba9e49847b7314d643abb87521e628..04d4481cbd29c3d08b6a261be1aa0dd4c81bf3c7 100644 (file)
--- a/src/bsv/peripheral_gen/jtag.py
+++ b/src/bsv/peripheral_gen/jtag.py
@@ -6,6 +6,31 @@ class jtag(PBase):
     def slowimport(self):
         return "    import jtagtdm::*;\n"
 
+    def extfastifinstance(self, name, count):
+        # YUK!
+        print "jtag", name, count
+        return """\
+            method Action tms_i(Bit#(1) tms);
+                {0}.tms_i(tms);
+            endmethod
+            method Action tdi_i(Bit#(1) tdi);
+                {0}.tdi_i(tdi);
+            endmethod
+            method Action bs_chain_i(Bit#(1) bs_chain);
+                {0}.bs_chain_i(bs_chain);
+            endmethod
+            method Bit#(1) shiftBscan2Edge={0}.shiftBscan2Edge;
+            method Bit#(1) selectJtagInput={0}.selectJtagInput;
+            method Bit#(1) selectJtagOutput={0}.selectJtagOutput;
+            method Bit#(1) updateBscan={0}.updateBscan;
+            method Bit#(1) bscan_in={0}.bscan_in;
+            method Bit#(1) scan_shift_en={0}.scan_shift_en;
+            method Bit#(1) tdo={0}.tdo;
+            method Bit#(1) tdo_oe={0}.tdo_oe;
+""".format(self.name, count)
+
+
+
     def fastifdecl(self, name, count):
         # YUK!
         template = """ \

diff --git a/src/bsv/pinmux_generator.py b/src/bsv/pinmux_generator.py
index 31b5c4d4ee899093b3bdc95c53b075b2a029ed78..b74fd47e6ed2bd0c4971d893680c878d86fb761f 100644 (file)
--- a/src/bsv/pinmux_generator.py
+++ b/src/bsv/pinmux_generator.py
@@ -142,14 +142,14 @@ def write_soc(soc, soct, p, ifaces, iocells):
     mkcon = ifaces.mk_fast_connection()
     mkcellcon = ifaces.mk_cellconn()
     pincon = ifaces.mk_pincon()
-    inst = ifaces.extifinstance()
+    inst = ifaces.extfastifinstance()
     mkplic = ifaces.mk_plic()
     numsloirqs = ifaces.mk_sloirqsdef()
     ifacedef = ifaces.mk_ext_ifacedef()
-    ifacedef = ifaces.mk_ext_ifacedef()
     with open(soc, "w") as bsv_file:
         bsv_file.write(soct.format(imports, ifdecl, mkfast,
                             slavedecl, mastdecl, mkcon,
+                            inst,
                             #'', '' #regdef, slavedecl,
                             #'', mkslow, #fnaddrmap, mkslow, mkcon, mkcellcon,
                             #pincon, inst, mkplic,