sigh, remove yet another int regfile read port

diff --git a/src/soc/regfile/regfiles.py b/src/soc/regfile/regfiles.py
index c3abdf004f2f89f4c113ac7016caf9636d08c927..0f29bb8fdc0d6846cf9482dfdf16620b51249a4f 100644 (file)
--- a/src/soc/regfile/regfiles.py
+++ b/src/soc/regfile/regfiles.py
@@ -70,8 +70,8 @@ class IntRegs(RegFileArray):
         self.w_ports = {'o': self.write_port("dest1"),
                         #'o1': self.write_port("dest2") # for now (LD/ST update)
                         }
-        self.r_ports = {'ra': self.read_port("src1"),
-                        'rbc': self.read_port("src3"),
+        self.r_ports = {'rabc': self.read_port("src1"),
+                        #'rbc': self.read_port("src3"),
                         'dmi': self.read_port("dmi")} # needed for Debug (DMI)
 
 

diff --git a/src/soc/simple/core.py b/src/soc/simple/core.py
index 71a9324387dd3f41a36af14462eeb001a67925d6..421180850201345b767f4432c9c28cbe7f767cf4 100644 (file)
--- a/src/soc/simple/core.py
+++ b/src/soc/simple/core.py
@@ -268,8 +268,9 @@ class NonProductionCore(Elaboratable):
             # argh.  an experiment to merge RA and RB in the INT regfile
             # (we have too many read/write ports)
             if regfile == 'INT':
-                fuspecs['rbc'] = [fuspecs.pop('rb')]
-                fuspecs['rbc'].append(fuspecs.pop('rc'))
+                fuspecs['rabc'] = [fuspecs.pop('rb')]
+                fuspecs['rabc'].append(fuspecs.pop('rc'))
+                fuspecs['rabc'].append(fuspecs.pop('ra'))
             if regfile == 'FAST':
                 fuspecs['fast1'] = [fuspecs.pop('fast1')]
                 fuspecs['fast1'].append(fuspecs.pop('fast2'))