fix UnusedElaboratable warning in TLB code

diff --git a/src/TLB/TLB.py b/src/TLB/TLB.py
index f2b7a9250e1dd9d2daa37a9bd672f82a685c05be..2feaf4b70e0a6f4f044b28ab263cb64712da7186 100644 (file)
--- a/src/TLB/TLB.py
+++ b/src/TLB/TLB.py
@@ -27,7 +27,7 @@ class TLB(Elaboratable):
         # Internal
         self.state = 0
         # L1 Cache Modules
-        L1_size = 8 # XXX overridden incoming argument?
+        ### L1_size = 8 # XXX overridden incoming argument?
         self.cam_L1 = Cam(vma_size, L1_size)
         self.mem_L1 = Memory(asid_size + pte_size, L1_size)
 
@@ -124,11 +124,12 @@ class TLB(Elaboratable):
         m = Module()
         # Add submodules
         # Submodules for L1 Cache
-        m.d.submodules.cam_L1 = self.cam_L1
-        m.d.sumbmodules.read_L1 = read_L1 = self.mem_L1.read_port()
-        m.d.sumbmodules.read_L1 = write_L1 = self.mem_L1.write_port()
+        m.submodules.cam_L1 = self.cam_L1
+        m.submodules.read_L1 = read_L1 = self.mem_L1.read_port()
+        m.submodules.write_L1 = write_L1 = self.mem_L1.write_port()
+        
         # Permission Validator Submodule
-        m.d.submodules.perm_valididator = self.perm_validator
+        m.submodules.perm_valididator = self.perm_validator
 
         # When MODE specifies translation
         # TODO add in different bit length handling ie prefix 0s

diff --git a/src/TLB/test/test_tlb.py b/src/TLB/test/test_tlb.py
index 8e26130a90888e3fdfe2bab55b1fa3759071ccba..73f34e4db8f20aa919ca9a7e3d56185e427f6840 100644 (file)
--- a/src/TLB/test/test_tlb.py
+++ b/src/TLB/test/test_tlb.py
@@ -1,6 +1,5 @@
-import tracemalloc
-
-tracemalloc.start()
+#import tracemalloc
+#tracemalloc.start()
 
 from nmigen.compat.sim import run_simulation
 
@@ -9,12 +8,13 @@ from TLB.TLB import TLB
 from TestUtil.test_helper import assert_op
 
 def tbench(dut):
-    pass
+    yield
+    yield
+    #TODO
 
 def test_tlb():
-    #FIXME UnusedElaboratable when the following line is uncommented
-    #dut = TLB(15,36,64,8)
-    #run_simulation(dut, tbench(dut), vcd_name="Waveforms/test_tlb.vcd")
+    dut = TLB(15,36,64,8)
+    run_simulation(dut, tbench(dut), vcd_name="Waveforms/test_tlb.vcd")
     print("TLB Unit Test TODO")
 
 if __name__ == "__main__":