add int fu-reg dep matrix

diff --git a/src/experiment/cscore.py b/src/experiment/cscore.py
index 2ba0271d67ff11b28e1d7aa63cd2c9013828f488..4ed775d368c130d6c67ff68a08a310267b7d3cf3 100644 (file)
--- a/src/experiment/cscore.py
+++ b/src/experiment/cscore.py
@@ -5,6 +5,7 @@ from nmigen import Module, Signal, Array, Elaboratable
 from regfile.regfile import RegFileArray
 from scoreboard.fn_unit import IntFnUnit, FPFnUnit, LDFnUnit, STFnUnit
 from scoreboard.fu_fu_matrix import FUFUDepMatrix
+from scoreboard.fu_reg_matrix import FURegDepMatrix
 from scoreboard.global_pending import GlobalPending
 from scoreboard.group_picker import GroupPicker
 from scoreboard.issue_unit import IntFPIssueUnit
@@ -63,9 +64,13 @@ class Scoreboard(Elaboratable):
 
         n_fus = n_int_fus + n_fp_fus # plus FP FUs
 
-        # Integer FU Dep Matrix
+        # Integer FU-FU Dep Matrix
         m.submodules.intfudeps = intfudeps = FUFUDepMatrix(n_int_fus, n_int_fus)
 
+        # Integer FU-Reg Dep Matrix
+        intregdeps = FUFUDepMatrix(self.n_regs, n_int_fus)
+        m.submodules.intregdeps = intregdeps
+
         # Integer Priority Picker 1: Adder + Subtractor
         m.submodules.intpick1 = GroupPicker(2) # picks between add and sub
 
@@ -74,10 +79,8 @@ class Scoreboard(Elaboratable):
         m.submodules.g_int_rd_pend_v = GlobalPending(self.rwid, int_rd_pend_v)
         m.submodules.g_int_wr_pend_v = GlobalPending(self.rwid, int_wr_pend_v)
 
-        # Issue Unit
-        m.submodules.issueunit = IntFPIssueUnit(self.rwid,
-                                                n_int_fus,
-                                                n_fp_fus)
+        # INT/FP Issue Unit
+        m.submodules.issueunit = IntFPIssueUnit(self.rwid, n_int_fus, n_fp_fus)
         return m
 
 

diff --git a/src/scoreboard/fu_reg_matrix.py b/src/scoreboard/fu_reg_matrix.py
index 0826ea5604616aade8e48421bd796853ce666693..9997d6e2f846206873f05536b4dc0963e6e0c8c1 100644 (file)
--- a/src/scoreboard/fu_reg_matrix.py
+++ b/src/scoreboard/fu_reg_matrix.py
@@ -3,9 +3,9 @@ from nmigen.cli import verilog, rtlil
 from nmigen import Module, Signal, Elaboratable, Array, Cat
 
 #from nmutil.latch import SRLatch
-from dependence_cell import DependenceCell
-from fu_wr_pending import FU_RW_Pend
-from reg_select import Reg_Rsv
+from .dependence_cell import DependenceCell
+from .fu_wr_pending import FU_RW_Pend
+from .reg_select import Reg_Rsv
 
 """