assign \$1 = sram4k_0_wb__cyc & (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:56" *) sram4k_0_wb__stb;
always @(posedge clk)
sram4k_0_wb__ack <= \sram4k_0_wb__ack$next ;
- spblock512w64b8w_0 spblock512w64b8w_0 (
+ spblock_512w64b8w spblock512w64b8w_0 (
.a(a),
.clk(clk),
.d(d),
assign \$1 = sram4k_1_wb__cyc & (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:56" *) sram4k_1_wb__stb;
always @(posedge clk)
sram4k_1_wb__ack <= \sram4k_1_wb__ack$next ;
- spblock512w64b8w_1 spblock512w64b8w_1 (
+ spblock_512w64b8w spblock512w64b8w_1 (
.a(a),
.clk(clk),
.d(d),
assign \$1 = sram4k_2_wb__cyc & (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:56" *) sram4k_2_wb__stb;
always @(posedge clk)
sram4k_2_wb__ack <= \sram4k_2_wb__ack$next ;
- spblock512w64b8w_2 spblock512w64b8w_2 (
+ spblock_512w64b8w spblock512w64b8w_2 (
.a(a),
.clk(clk),
.d(d),
assign \$1 = sram4k_3_wb__cyc & (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:56" *) sram4k_3_wb__stb;
always @(posedge clk)
sram4k_3_wb__ack <= \sram4k_3_wb__ack$next ;
- spblock512w64b8w_3 spblock512w64b8w_3 (
+ spblock_512w64b8w spblock512w64b8w_3 (
.a(a),
.clk(clk),
.d(d),
<* blackbox = 1 *)
-module spblock512w64b8w(a, d, q, we, clk);
+module spblock_512w64b8w(a, d, q, we, clk);
input [8:0] a;
input [63:0] d;
output [63:0] q;