rename spblock modules to just straight spblock_512w64b8w after
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Wed, 28 Apr 2021 17:01:18 +0000 (17:01 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Wed, 28 Apr 2021 17:01:18 +0000 (17:01 +0000)
JP sorted blackbox module loading

experiments9/non_generated/full_core_4_4ksram_libresoc.v
experiments9/non_generated/spblock512w64b8w.v

index 0d5f7fe682135553edec69e586059d03e563de4e..6f3af85e368b91c6338a2543a4cbd53289300099 100644 (file)
@@ -193401,7 +193401,7 @@ module sram4k_0(rst, enable, sram4k_0_wb__cyc, sram4k_0_wb__stb, sram4k_0_wb__ac
   assign \$1  = sram4k_0_wb__cyc & (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:56" *) sram4k_0_wb__stb;
   always @(posedge clk)
     sram4k_0_wb__ack <= \sram4k_0_wb__ack$next ;
-  spblock512w64b8w_0 spblock512w64b8w_0 (
+  spblock_512w64b8w spblock512w64b8w_0 (
     .a(a),
     .clk(clk),
     .d(d),
@@ -193545,7 +193545,7 @@ module sram4k_1(rst, enable, sram4k_1_wb__cyc, sram4k_1_wb__stb, sram4k_1_wb__ac
   assign \$1  = sram4k_1_wb__cyc & (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:56" *) sram4k_1_wb__stb;
   always @(posedge clk)
     sram4k_1_wb__ack <= \sram4k_1_wb__ack$next ;
-   spblock512w64b8w_1 spblock512w64b8w_1 (
+   spblock_512w64b8w spblock512w64b8w_1 (
     .a(a),
     .clk(clk),
     .d(d),
@@ -193689,7 +193689,7 @@ module sram4k_2(rst, enable, sram4k_2_wb__cyc, sram4k_2_wb__stb, sram4k_2_wb__ac
   assign \$1  = sram4k_2_wb__cyc & (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:56" *) sram4k_2_wb__stb;
   always @(posedge clk)
     sram4k_2_wb__ack <= \sram4k_2_wb__ack$next ;
-   spblock512w64b8w_2 spblock512w64b8w_2 (
+   spblock_512w64b8w spblock512w64b8w_2 (
     .a(a),
     .clk(clk),
     .d(d),
@@ -193833,7 +193833,7 @@ module sram4k_3(rst, enable, sram4k_3_wb__cyc, sram4k_3_wb__stb, sram4k_3_wb__ac
   assign \$1  = sram4k_3_wb__cyc & (* src = "/home/lkcl/src/libresoc/soc/src/soc/bus/SPBlock512W64B8W.py:56" *) sram4k_3_wb__stb;
   always @(posedge clk)
     sram4k_3_wb__ack <= \sram4k_3_wb__ack$next ;
-   spblock512w64b8w_3 spblock512w64b8w_3 (
+   spblock_512w64b8w spblock512w64b8w_3 (
     .a(a),
     .clk(clk),
     .d(d),
index ef3870f6d38131778e4048e3426c6419530c4902..4555b15512088b2250410b6f0a811446002a5ca3 100644 (file)
@@ -1,5 +1,5 @@
 <* blackbox = 1 *)
-module spblock512w64b8w(a, d, q, we, clk);
+module spblock_512w64b8w(a, d, q, we, clk);
        input [8:0] a;
        input [63:0] d;
        output [63:0] q;