more vst corrections, for chip definition

diff --git a/ls180/post_pnr/chip_corona/chip_r.vhd b/ls180/post_pnr/chip_corona/chip_r.vhd
index 3aada6ebd80b09e3a5130bef1243b8db9324f519..b11933d7cb80a549ca5478d802bec32504102eea 100644 (file)
--- a/ls180/post_pnr/chip_corona/chip_r.vhd
+++ b/ls180/post_pnr/chip_corona/chip_r.vhd
@@ -323,13 +323,24 @@ architecture structural of chip_r is
   signal chip_dummy_8                 :  bit;
   signal chip_dummy_9                 :  bit;
   signal eint_0_enable_to_pad         :  bit;
+  signal eint_0_from_pad              :  bit;
   signal eint_1_enable_to_pad         :  bit;
+  signal eint_1_from_pad              :  bit;
   signal eint_2_enable_to_pad         :  bit;
+  signal eint_2_from_pad              :  bit;
   signal i2c_scl_enable_to_pad        :  bit;
+  signal i2c_scl_to_pad               :  bit;
+  signal i2c_sda_i_from_pad           :  bit;
+  signal i2c_sda_o_to_pad             :  bit;
+  signal i2c_sda_oe_to_pad            :  bit;
   signal jtag_tck_enable_to_pad       :  bit;
+  signal jtag_tck_from_pad            :  bit;
   signal jtag_tdi_enable_to_pad       :  bit;
+  signal jtag_tdi_from_pad            :  bit;
   signal jtag_tdo_enable_to_pad       :  bit;
+  signal jtag_tdo_to_pad              :  bit;
   signal jtag_tms_enable_to_pad       :  bit;
+  signal jtag_tms_from_pad            :  bit;
   signal nc_0_enable_to_pad           :  bit;
   signal nc_10_enable_to_pad          :  bit;
   signal nc_11_enable_to_pad          :  bit;
@@ -386,21 +397,46 @@ architecture structural of chip_r is
   signal sdram_ba_0_enable_to_pad     :  bit;
   signal sdram_ba_1_enable_to_pad     :  bit;
   signal sdram_cas_n_enable_to_pad    :  bit;
+  signal sdram_cas_n_to_pad           :  bit;
   signal sdram_cke_enable_to_pad      :  bit;
+  signal sdram_cke_to_pad             :  bit;
   signal sdram_clock_enable_to_pad    :  bit;
+  signal sdram_clock_to_pad           :  bit;
   signal sdram_cs_n_enable_to_pad     :  bit;
+  signal sdram_cs_n_to_pad            :  bit;
   signal sdram_dm_0_enable_to_pad     :  bit;
   signal sdram_dm_1_enable_to_pad     :  bit;
   signal sdram_ras_n_enable_to_pad    :  bit;
+  signal sdram_ras_n_to_pad           :  bit;
   signal sdram_we_n_enable_to_pad     :  bit;
+  signal sdram_we_n_to_pad            :  bit;
   signal spimaster_clk_enable_to_pad  :  bit;
+  signal spimaster_clk_to_pad         :  bit;
   signal spimaster_cs_n_enable_to_pad :  bit;
+  signal spimaster_cs_n_to_pad        :  bit;
   signal spimaster_miso_enable_to_pad :  bit;
+  signal spimaster_miso_from_pad      :  bit;
   signal spimaster_mosi_enable_to_pad :  bit;
+  signal spimaster_mosi_to_pad        :  bit;
   signal sys_clk_enable_to_pad        :  bit;
+  signal sys_clk_from_pad             :  bit;
   signal sys_rst_enable_to_pad        :  bit;
+  signal sys_rst_from_pad             :  bit;
   signal uart_rx_enable_to_pad        :  bit;
+  signal uart_rx_from_pad             :  bit;
   signal uart_tx_enable_to_pad        :  bit;
+  signal uart_tx_from_pad             :  bit;
+  signal sdram_ba_to_pad              :  bit_vector(1 downto 0);
+  signal sdram_dm_to_pad              :  bit_vector(1 downto 0);
+  signal sdram_a_to_pad               :  bit_vector(12 downto 0);
+  signal gpio_i_from_pad              :  bit_vector(15 downto 0);
+  signal gpio_o_to_pad                :  bit_vector(15 downto 0);
+  signal gpio_oe_to_pad               :  bit_vector(15 downto 0);
+  signal sdram_dq_i_from_pad          :  bit_vector(15 downto 0);
+  signal sdram_dq_o_to_pad            :  bit_vector(15 downto 0);
+  signal sdram_dq_oe_to_pad           :  bit_vector(15 downto 0);
+  signal nc_from_pad                  :  bit_vector(39 downto 0);
+
 
 begin
 

diff --git a/ls180/post_pnr/chip_corona/corona.vhd b/ls180/post_pnr/chip_corona/corona.vhd
index c340681b3e36e8b37091adbfb2c8c662293ba6b7..dea3d9e706b256d31f8b4fd6def676e217334dc7 100644 (file)
--- a/ls180/post_pnr/chip_corona/corona.vhd
+++ b/ls180/post_pnr/chip_corona/corona.vhd
@@ -129,7 +129,7 @@ end corona;
 
 architecture structural of corona is
 
-  component cmpt_ls180
+  component ls180
     port ( eint_0                : in bit
          ; eint_1                : in bit
          ; eint_2                : in bit
@@ -253,7 +253,7 @@ architecture structural of corona is
 
 begin
 
-  core : cmpt_ls180
+  core : ls180
   port map ( eint_0                => eint_0_from_pad
            , eint_1                => eint_1_from_pad
            , eint_2                => eint_2_from_pad

diff --git a/ls180/post_pnr/vst_correct.py b/ls180/post_pnr/vst_correct.py
index 68bd2a0c9b0cec36485e4159080b88f0769dd81a..d78d08d6ef73e19e1c86fb855487587c6cc601e7 100755 (executable)
--- a/ls180/post_pnr/vst_correct.py
+++ b/ls180/post_pnr/vst_correct.py
@@ -6,11 +6,18 @@
 import os
 import sys
 
+vhdl_header = """\
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+
+"""
 # run through all files
 for fname in os.listdir("vst_src"):
     if not fname.endswith(".vst"):
         continue
     print (fname)
+    is_chip = fname.startswith("chip")
     # read the file
     fname = "vst_src/"+fname
     with open(fname) as f:
@@ -19,6 +26,40 @@ for fname in os.listdir("vst_src"):
     txt = txt.replace("linkage bit", "in bit")
     # and double-underscores
     txt = txt.replace("__", "_")
+    # special-case for chip.vst and chip_r.vst
+    if is_chip:
+        # add VHDL IEEE Library header
+        txt = vhdl_header + txt
+        # pad gpio fix
+        txt = txt.replace("pad   : inout mux_bit bus",
+                          "pad   : inout std_logic")
+        # reset fix
+        txt = txt.replace("sys_rst : gpio",
+                          "p_sys_rst: gpio")
+
+        # temporary hack to rename niolib to avoid name-clashes
+        for cell in ['gpio', 'vss', 'vdd', 'iovss', 'iovdd']:
+            txt = txt.replace(": %s" % cell, ": cmpt_%s" % cell)
+            txt = txt.replace("component %s" % cell, "component cmpt_%s" % cell)
+        # identify the chip ports and replace "in bit" with "inout std_logic"
+        res = []
+        found_chip = False
+        done_chip = False
+        for line in txt.splitlines():
+            if done_chip:
+                res.append(line)
+                continue
+            if not found_chip:
+                if line.startswith("entity chip"):
+                    found_chip = True
+            else:
+                # covers in bit_vector and out bit_vector as well
+                line = line.replace("in bit", "inout std_logic")
+                line = line.replace("out bit", "inout std_logic")
+                done_chip = line.startswith("end chip")
+            res.append(line)
+        # re-join lines
+        txt = '\n'.join(res)
     # write the file
     with open(fname, "w") as f:
         f.write(txt)